Atheros AR724x PLL/RST/PCI-E registers reset values

ar724x.txt

Below data was collected on:
TP-Link TL-WR842ND v1 (AR7241)

== JTAG signals ==

SIGNAL	PACKAGE PIN	LOCATION ON PCB
TDI	PIN81		R774 (near U13, right bottom corner)
TDO	PIN82		R617 (near U13, right bottom corner)
TMS	PIN84		R561 (near "Internet"/"USB" LEDs)
TCK	PIN85		R427 (near SOC, between SOC and FLASH chip)

== Photo ==

https://postimg.org/image/68dsm5ivf/

== PLL CONTROL REGISTERS ==

REG NAME			REG ADDRESS	RESET VALUE (CPU in halt mode, read over JTAG)
CPU_PLL_CONFIG			0x18050000	0x02090828
ETH_USB_PLL_CONFIG		0x18050004	0x0a09081e
CPU_CLOCK_CONTROL		0x18050008	0x00000000

PCIE_PLL_CONFIG			0x18050010	0x02050800
PCIE_PLL_MAX_LIMIT		0x18050014	0xc00a0000
PCIE_PLL_MIN_LIMIT		0x18050018	0x0009f33a
PCIE_PLL_DITHER_STEP		0x1805001C	0x0000000a
LDO_POWER_CONTROL		0x18050020	0x00000003
?????????????????		0x18050024	0x00000001
CURRENT_PCIE_PLL_DITHER		0x18050028	0x0009f33a

AUDIO_PLL_CONFIG		0x18050030	0x000010d3
AUDIO_PLL_MODULATION		0x18050034	0x0a47f028
AUDIO_PLL_MOD_STEP		0x18050038	0x00004000
CURRENT_AUDIO_PLL_MODULATION	0x1805003C	0x0523f814

== RESET REGISTERS ==

REG NAME		REG ADDRESS	RESET VALUE (CPU in halt mode, read over JTAG)
RST_RESET		0x1806001C	0x00c027f0
RST_REVISION_ID		0x18060090	0x00000101

== PCIE CONTROL REGISTERS ==

All below registers are not available before taking PCI-E out of reset.
CPU hangs just after read attempt.

After write 0x00C027B0 (bit[6]/PCIE_RESET cleared) to RST_RESET (0x1806001C):

REG NAME		REG ADDRESS	RESET VALUE (CPU in halt mode, read over JTAG)
PCIE_APP		0x180F0000	0x0001ffc0
PCIE_AER		0x180F0004	0x00000000
PCIE_PWR_MGMT		0x180F0008	0x00000000
PCIE_ELEC		0x180F000C	0x00000000
PCIE_CFG		0x180F0010	0x00c00008
PCIE_RX_CNTL		0x180F0014	0x00000000
PCIE_RESET		0x180F0018	0x00000004

PCIE_PHY_CFG_DATA	0x180F002C	0x00000005
PCIE_MAC_PHY		0x180F0030	0x00880376
PCIE_PHY_MAC		0x180F0034	0x00440000
PCIE_SIDEBAND1		0x180F0038	0x00000000
PCIE_SIDEBAND2		0x180F003C	0x00000008
PCIE_SPARE		0x180F0040	0x00000000
PCIE_MSI_ADDR		0x180F0044	0x00000000
PCIE_MSI_DATA		0x180F0048	0x00000000
PCIE_INT_STATUS		0x180F004C	0x00000000
PCIE_INT_MASK		0x180F0050	0x00000000

Additional notes about PCIE_RST_OUT_L/PERSTn signal
and its relationship with PCIE_RESET register:

Clear bit[2]/EP_RESET_L ===> PCIE_RST_OUT_L (PERSTn) goes LOW
Set   bit[2]/EP_RESET_L ===> PCIE_RST_OUT_L (PERSTn) goes HIGH