Mapping of buses

gistfile1.txt

    line_t addr_line[9] = {
               PORT(A, 12),
               PORT(A, 13),
               PORT(A, 14),
               PORT(E, 0),
               PORT(E, 1),
               PORT(E, 2),
               PORT(E, 3),
               PORT(C, 1),
               PORT(C, 7)
           },
           data_line[16] = {
               PORT(D, 0),
               PORT(D, 1),
               PORT(D, 2),
               PORT(D, 3),
               PORT(D, 4),
               PORT(D, 5),
               PORT(D, 6),
               PORT(C, 0),
               PORT(C, 3),
               PORT(C, 4),
               PORT(C, 5),
               PORT(B, 11),
               PORT(B, 12),
               PORT(C, 6),
               PORT(D, 7),
               PORT(D, 14),
           },
           chip_enable_line[1] = {PORT(F, 8)},
           cpu_enable_line[1] = {PORT(F, 9)},
           write_enable_line[1] = {PORT(B, 10)},
           cpu_state_line[2] = {
               PORT(D, 15),
               PORT(D, 13)
           };