eric1_lockstep_ram

; phase 1: 6502 is bus master (8 cycles)
; prepare atmega for memory access by preloading address (address lines are still inputs so this will only affect internal pull up resistors)
out     PORTA, lo       ; load lo address 
out     PORTB, hi       ; load hi address
st      X+, data        ; store data received in previous phase 0
adiw    address, 1      ; increment address
nop
nop

; phase 0: atmega is bus master (8 cycles)
out     PORTD, XX       ; BE low & enable SRAM
out     DDRA, 0xff      ; set address lines to output mode
out     DDRB, 0xff
nop
in      data, PINC      ; read data
out     DDRA, 0         ; set address lines to input mode
out     DDRB, 0
out     PORTD, XX       ; BE high & disable SRAM