only_defines.h

#define CONFIG_EXT4_USE_FOR_EXT2 1
#define __GFP_NOMEMALLOC ((__force gfp_t)___GFP_NOMEMALLOC)
#define MAS_WR_WARN_ON(__mas,__x) WARN_ON(__x)
#define SCHED_FLAG_UTIL_CLAMP (SCHED_FLAG_UTIL_CLAMP_MIN | SCHED_FLAG_UTIL_CLAMP_MAX)
#define SYS_PMSLATFR_EL1_CRn 9
#define cpu_to_be32 __cpu_to_be32
#define BLKSECDISCARD _IO(0x12,125)
#define TCR2_EL2_E0POE_SHIFT 2
#define ID_AA64MMFR0_EL1_EXS GENMASK(47, 44)
#define USE_CMPXCHG_LOCKREF (IS_ENABLED(CONFIG_ARCH_USE_CMPXCHG_LOCKREF) && IS_ENABLED(CONFIG_SMP) && SPINLOCK_SIZE <= 4)
#define lockdep_softirq_enter() do { current->softirq_context++; } while (0)
#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
#define ID_ISAR2_EL1_PSR_AR_SHIFT 24
#define AF_LLC 26
#define VM_NORESERVE 0x00200000
#define raw_cpu_cmpxchg64(pcp,oval,nval) raw_cpu_generic_cmpxchg(pcp, oval, nval)
#define ID_PFR0_EL1_CSV2_MASK GENMASK(19, 16)
#define SEMOPM 500
#define SUPPORTED_TP __ETHTOOL_LINK_MODE_LEGACY_MASK(TP)
#define MDIO_USXGMII_1000FULL 0x1400
#define xa_trylock(xa) spin_trylock(&(xa)->xa_lock)
#define __LINUX_NET_SCM_H 
#define NETIF_F_HW_VLAN_STAG_RX __NETIF_F(HW_VLAN_STAG_RX)
#define AT_STATX_SYNC_AS_STAT 0x0000
#define current_user_stack_pointer() user_stack_pointer(current_pt_regs())
#define SYS_OSDTRTX_EL1_Op1 0
#define ID_AA64ISAR1_EL1_FRINTTS_WIDTH 4
#define BITS_PER_LONG 64
#define HDFGRTR_EL2_DBGCLAIM_WIDTH 1
#define PSR_AA32_F_BIT 0x00000040
#define AF_MAX 46
#define ___GFP_NOFAIL 0x8000u
#define CONFIG_LEGACY_TIOCSTI 1
#define ID_ISAR1_EL1_Immediate_MASK GENMASK(23, 20)
#define PR_MDWE_REFUSE_EXEC_GAIN (1UL << 0)
#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
#define llist_for_each(pos,node) for ((pos) = (node); pos; (pos) = (pos)->next)
#define TIME_WAIT 4
#define MDIO_AN_T1_LP_M 518
#define SYS_ID_AA64MMFR2_EL1_Op0 3
#define SYS_ID_AA64MMFR2_EL1_Op2 2
#define ID_AA64SMFR0_EL1_SMEver_WIDTH 4
#define ID_MMFR3_EL1_Supersec_SHIFT 28
#define PR_SVE_SET_VL 50
#define PMSCR_EL1_PCT GENMASK(7, 6)
#define SKB_DR_OR(name,reason) do { if (name == SKB_DROP_REASON_NOT_SPECIFIED || name == SKB_NOT_DROPPED_YET) SKB_DR_SET(name, reason); } while (0)
#define MDIO_USXGMII_10FULL 0x1000
#define HFGxTR_EL2_ERRSELR_EL1 GENMASK(41, 41)
#define CONFIG_ARCH_USE_CMPXCHG_LOCKREF 1
#define write_lock_irq(lock) _raw_write_lock_irq(lock)
#define CMSG_NXTHDR(mhdr,cmsg) cmsg_nxthdr((mhdr), (cmsg))
#define CONFIG_PTP_1588_CLOCK 1
#define arch_xchg_acquire(...) __xchg_wrapper(_acq, __VA_ARGS__)
#define BLKFLSBUF _IO(0x12,97)
#define SKB_DST_NOREF 1UL
#define SVE_SIG_REGS_OFFSET ((sizeof(struct sve_context) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
#define __diag_GCC_error error
#define try_cmpxchg128_release(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); kcsan_release(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg128_release(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define __LINUX_BITMAP_H 
#define cpu_to_be64 __cpu_to_be64
#define RUSAGE_THREAD 1
#define __READ_ONCE(x) (*(const volatile __unqual_scalar_typeof(x) *)&(x))
#define ID_AA64ISAR1_EL1_GPA_NI UL(0b0000)
#define __refdata __section(".ref.data")
#define mas_lock(mas) spin_lock(&((mas)->tree->ma_lock))
#define ALTINSTR_ENTRY(cpucap) " .word 661b - .\n" " .word 663f - .\n" " .hword " __stringify(cpucap) "\n" " .byte 662b-661b\n" " .byte 664f-663f\n"
#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | ESR_ELx_SYS64_ISS_DIR_WRITE)
#define arch_start_context_switch(prev) do {} while (0)
#define ID_MMFR0_EL1_VMSA_VMSAv7_PXN UL(0b0100)
#define _CLASS_ATTR_STRING(_name,_mode,_str) { __ATTR(_name, _mode, show_class_attr_string, NULL), _str }
#define STATX_ATTR_AUTOMOUNT 0x00001000
#define HFGxTR_EL2_APDAKey_WIDTH 1
#define CONFIG_ARCH_USE_MEMTEST 1
#define CONFIG_LTO_NONE 1
#define RCU_NUM_LVLS 2
#define CONFIG_DEFAULT_MMAP_MIN_ADDR 4096
#define ifr_name ifr_ifrn.ifrn_name
#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
#define pmd_set_fixmap_offset(pud,addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
#define ETHTOOL_COALESCE_RX_USECS_IRQ BIT(2)
#define __no_profile __attribute__((__no_profile_instrument_function__))
#define CONFIG_GPIO_VIRTIO 1
#define time_is_after_eq_jiffies(a) time_before_eq(jiffies, a)
#define down_write_nest_lock(sem,nest_lock) do { typecheck(struct lockdep_map *, &(nest_lock)->dep_map); _down_write_nest_lock(sem, &(nest_lock)->dep_map); } while (0)
#define KEY_DESTROY 0xbd
#define __NR_remap_file_pages 234
#define SMCR_ELx_EZT0_SHIFT 30
#define EPOLLWRBAND (__force __poll_t)0x00000200
#define ftrace_set_filter_ip(ops,ip,remove,reset) ({ -ENODEV; })
#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
#define ID_AA64SMFR0_EL1_I8I32_MASK GENMASK(39, 36)
#define SDF_SHARED_PARENT 0x2
#define Elf_Word Elf64_Word
#define ID_ISAR5_EL1_SHA2_MASK GENMASK(15, 12)
#define rcu_dereference_raw(p) __rcu_dereference_raw(p, __UNIQUE_ID(rcu))
#define __copy(symbol) __attribute__((__copy__(symbol)))
#define SCTLR_EL1_EnTP2 GENMASK(60, 60)
#define REG_PMSNEVFR_EL1 S3_0_C9_C9_1
#define DCZID_EL0_DZP GENMASK(4, 4)
#define ESR_ELx_EC_SP_ALIGN (0x26)
#define SYS_ID_ISAR3_EL1_Op0 3
#define SYS_ID_ISAR3_EL1_Op1 0
#define SYS_ID_ISAR3_EL1_Op2 3
#define HCR_TDZ (UL(1) << 28)
#define BMSR_100FULL2 0x0400
#define ___ADDRESSABLE(sym,__attrs) static void * __used __attrs __UNIQUE_ID(__PASTE(__addressable_,sym)) = (void *)&sym;
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
#define ID_PFR1_EL1_Virt_frac GENMASK(27, 24)
#define ID_ISAR3_EL1_SIMD_SSAT UL(0b0001)
#define ETH_P_8021AH 0x88E7
#define PMBLIMITR_EL1_PMFZ_MASK GENMASK(5, 5)
#define SCTLR_EL1_TME0_WIDTH 1
#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
#define __ASM_STRING_H 
#define CONFIG_PROVE_RCU 1
#define SYS_CCSIDR_EL1_Op1 1
#define MVFR0_EL1_FPDP_MASK GENMASK(11, 8)
#define CONFIG_PREEMPT_NONE 1
#define DACR32_EL2_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define DACR32_EL2_RES1 (UL(0))
#define LORSA_EL1_Valid_SHIFT 0
#define _LINUX_INTERRUPT_H 
#define PMSIDR_EL1_FL_MASK GENMASK(2, 2)
#define ID_AA64ISAR0_EL1_TME_SHIFT 24
#define __diag_pop() __diag(pop)
#define CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC 1
#define PR_FP_EXC_OVF 0x020000
#define MDSCR_EL1_EHBWE_MASK GENMASK(35, 35)
#define ID_DFR0_EL1_PerfMon_PMUv3p7 UL(0b0111)
#define sum_zone_node_page_state(node,item) global_zone_page_state(item)
#define SWAPPER_TABLE_SHIFT PUD_SHIFT
#define ESR_ELx_CV (UL(1) << 24)
#define _DELAYED_CALL_H 
#define ETHTOOL_SSET 0x00000002
#define pr_alert(fmt,...) printk(KERN_ALERT pr_fmt(fmt), ##__VA_ARGS__)
#define dev_notice_once(dev,fmt,...) dev_level_once(dev_notice, dev, fmt, ##__VA_ARGS__)
#define ID_AA64ISAR1_EL1_BF16_EBF16 UL(0b0010)
#define MDIO_AN_C73_1_25GBASE_R_S BIT(14)
#define CONFIG_PCI_MSI 1
#define CLOCK_THREAD_CPUTIME_ID 3
#define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
#define DIV_U64_ROUND_CLOSEST(dividend,divisor) ({ u32 _tmp = (divisor); div_u64((u64)(dividend) + _tmp / 2, _tmp); })
#define COMPAT_OFF_T_MAX 0x7fffffff
#define IORESOURCE_IRQ 0x00000400
#define DT_STRTAB 5
#define STT_OBJECT 1
#define INPUT_DEVICE_ID_MATCH_RELBIT 0x0040
#define CLASS_ATTR_RO(_name) struct class_attribute class_attr_ ##_name = __ATTR_RO(_name)
#define HFGITR_EL2_TLBIVAALE1_SHIFT 47
#define IPV6_PRIORITY_14 0x0e00
#define ID_AA64PFR0_EL1_EL2_AARCH32 UL(0b0010)
#define ID_AA64PFR0_EL1_SVE_NI UL(0b0000)
#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
#define PMSNEVFR_EL1_UNKN (UL(0))
#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
#define FTR_STRICT true
#define __NR_semop 193
#define MDIO_PCS_CTRL2_10GBT 0x0003
#define __setup(str,fn) __setup_param(str, fn, fn, 0)
#define EM_SPARCV9 43
#define ID_ISAR1_EL1_IfThen_WIDTH 4
#define ID_MMFR2_EL1_L1HvdRng_MASK GENMASK(11, 8)
#define NETLINK_SMC 22
#define IPV6_PRIORITY_15 0x0f00
#define SPIN_DEBUG_INIT(lockname) .magic = SPINLOCK_MAGIC, .owner_cpu = -1, .owner = SPINLOCK_OWNER_INIT,
#define CONFIG_GENERIC_IRQ_IPI 1
#define Q_XQUOTASYNC XQM_CMD(7)
#define __NR_exit 93
#define atomic64_cond_read_relaxed(v,c) smp_cond_load_relaxed(&(v)->counter, (c))
#define CONFIG_HARDIRQS_SW_RESEND 1
#define __NR_swapoff 225
#define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
#define __get_dma_pages(gfp_mask,order) __get_free_pages((gfp_mask) | GFP_DMA, (order))
#define CONFIG_KEYBOARD_ATKBD 1
#define PM_EVENT_RESTORE 0x0040
#define __raw_writel __raw_writel
#define HWEIGHT16(w) (BUILD_BUG_ON_ZERO(!__builtin_constant_p(w)) + __const_hweight16(w))
#define IFF_ALLMULTI IFF_ALLMULTI
#define netdev_warn_once(dev,fmt,...) netdev_level_once(KERN_WARNING, dev, fmt, ##__VA_ARGS__)
#define ID_MMFR3_EL1_CMaintSW_MASK GENMASK(7, 4)
#define ERESTARTSYS 512
#define LPA_1000XFULL 0x0020
#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
#define ID_AA64PFR0_EL1_AMU_SIGNED false
#define per_cpu_ptr(ptr,cpu) ({ __verify_pcpu_ptr(ptr); SHIFT_PERCPU_PTR((ptr), per_cpu_offset((cpu))); })
#define param_get_bint param_get_int
#define EDESTADDRREQ 89
#define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
#define SOL_AX25 257
#define ISR_EL1_IS_SHIFT 10
#define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
#define is_compat_task() (0)
#define CONFIG_HAVE_KPROBES 1
#define fast_interrupts_enabled(regs) (!((regs)->pstate & PSR_F_BIT))
#define arch_atomic_sub_return arch_atomic_sub_return
#define _ASM_GENERIC_TRACE_CLOCK_H 
#define MVFR0_EL1_FPDivide_WIDTH 4
#define lru_to_page(head) (list_entry((head)->prev, struct page, lru))
#define PTE_UXN (_AT(pteval_t, 1) << 54)
#define SMPRIMAP_EL2_P10_SHIFT 40
#define PSR_A_BIT 0x00000100
#define PMSCR_EL2_PCT_PHYS UL(0b01)
#define raw_cmpxchg128_release arch_cmpxchg128
#define hashlen_hash(hashlen) ((u32)(hashlen))
#define might_lock_nested(lock,subclass) do { typecheck(struct lockdep_map *, &(lock)->dep_map); lock_acquire(&(lock)->dep_map, subclass, 0, 1, 1, NULL, _THIS_IP_); lock_release(&(lock)->dep_map, _THIS_IP_); } while (0)
#define NETIF_F_CSUM_MASK (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_HW_CSUM)
#define SRCU_STATE_IDLE 0
#define system_has_cmpxchg128() 1
#define PR_SET_UNALIGN 6
#define FS_HAS_SUBTYPE 4
#define static_branch_unlikely(x) unlikely_notrace(static_key_enabled(&(x)->key))
#define ADVERTISE_1000XFULL 0x0020
#define for_each_set_clump8(start,clump,bits,size) for ((start) = find_first_clump8(&(clump), (bits), (size)); (start) < (size); (start) = find_next_clump8(&(clump), (bits), (size), (start) + 8))
#define SLAB_TYPESAFE_BY_RCU ((slab_flags_t __force)0x00080000U)
#define _LINUX_INSTRUMENTED_H 
#define swait_event_timeout_exclusive(wq,condition,timeout) ({ long __ret = timeout; if (!___wait_cond_timeout(condition)) __ret = __swait_event_timeout(wq, condition, timeout); __ret; })
#define ID_MMFR2_EL1_WFIStall GENMASK(27, 24)
#define DACR32_EL2_D1_SHIFT 2
#define HWEIGHT32(w) (BUILD_BUG_ON_ZERO(!__builtin_constant_p(w)) + __const_hweight32(w))
#define HDFGRTR_EL2_nBRBIDR GENMASK(59, 59)
#define EV_CURRENT 1
#define HDFGRTR_EL2_TRCSSCSRn_WIDTH 1
#define __HCRX_EL2_MASK (0)
#define set_pte_at_notify set_pte_at
#define ID_AA64MMFR0_EL1_TGRAN64_2_WIDTH 4
#define POLLPRI 0x0002
#define SVE_PT_SIZE(vq,flags) (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) : ((((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD ? SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags) : SVE_PT_REGS_OFFSET)))
#define MII_SREVISION 0x16
#define ID_AA64AFR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 0))
#define ID_AA64AFR1_EL1_RES1 (UL(0))
#define KUNIT_INDENT_LEN 4
#define phys_to_virt phys_to_virt
#define SLAB_DEBUG_OBJECTS 0
#define EPOLLWAKEUP ((__force __poll_t)(1U << 29))
#define PTRACE_SEIZE 0x4206
#define IPV6_ADDRFORM 1
#define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
#define __NR_fdatasync 83
#define CONFIG_IOMMU_IO_PGTABLE_DART 1
#define ID_AA64PFR1_EL1_SME_MASK GENMASK(27, 24)
#define PMBSR_EL1_EC_FAULT_S2 UL(0b100101)
#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | ESR_ELx_SYS64_ISS_OP1_MASK | ESR_ELx_SYS64_ISS_CRN_MASK | ESR_ELx_SYS64_ISS_DIR_MASK)
#define ITIMER_VIRTUAL 1
#define __wait_event_killable_timeout(wq_head,condition,timeout) ___wait_event(wq_head, ___wait_cond_timeout(condition), TASK_KILLABLE, 0, timeout, __ret = schedule_timeout(__ret))
#define ETHTOOL_SEEE 0x00000045
#define PAGE_ALIGN_DOWN(addr) ALIGN_DOWN(addr, PAGE_SIZE)
#define HDFGWTR_EL2_nPMSNEVFR_EL1 GENMASK(62, 62)
#define _LINUX_ELF_H 
#define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
#define HDFGRTR_EL2_TRBIDR_EL1 GENMASK(51, 51)
#define SYS_FAR_EL1_Op0 3
#define SYS_FAR_EL1_Op1 0
#define SYS_FAR_EL1_Op2 0
#define CONFIG_ARM_PSCI_FW 1
#define EMLINK 31
#define __cpu_to_be16s(x) __swab16s((x))
#define ARM64_WORKAROUND_2966298 81
#define ID_AA64DFR0_EL1_CTX_CMPs_SHIFT 28
#define __no_kasan_or_inline __always_inline
#define BIN_ATTR_RW(_name,_size) struct bin_attribute bin_attr_ ##_name = __BIN_ATTR_RW(_name, _size)
#define current_fsuid_fsgid(_fsuid,_fsgid) do { const struct cred *__cred; __cred = current_cred(); *(_fsuid) = __cred->fsuid; *(_fsgid) = __cred->fsgid; } while(0)
#define p4d_alloc_one(mm,address) NULL
#define ID_ISAR0_EL1_Swap_SHIFT 0
#define PIE_GCS 0x9
#define _LINUX_TOPOLOGY_H 
#define phydev_info(_phydev,format,args...) dev_info(&_phydev->mdio.dev, format, ##args)
#define wait_event_interruptible_hrtimeout(wq,condition,timeout) ({ long __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_event_hrtimeout(wq, condition, timeout, TASK_INTERRUPTIBLE); __ret; })
#define sockfd_put(sock) fput(sock->file)
#define IORESOURCE_PCI_FIXED (1<<4)
#define IF_PROTO_HDLC_ETH 0x2007
#define raw_cpu_write(pcp,val) __pcpu_size_call(raw_cpu_write_, pcp, val)
#define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
#define PT_TRACE_CLONE PT_EVENT_FLAG(PTRACE_EVENT_CLONE)
#define _LINUX_DEBUGOBJECTS_H 
#define __ASM_GENERIC_SIGNAL_H 
#define HWEIGHT64(w) (BUILD_BUG_ON_ZERO(!__builtin_constant_p(w)) + __const_hweight64(w))
#define ARM64_HAS_GENERIC_AUTH_IMP_DEF 28
#define QTREE_INIT_REWRITE 2
#define ___GFP_DIRECT_RECLAIM 0x400u
#define LPA_SLCT 0x001f
#define HFGITR_EL2_TLBIVMALLE1IS GENMASK(28, 28)
#define _LINUX_MM_TYPES_TASK_H 
#define ETH_TP_MDI_INVALID 0x00
#define __NR_open_by_handle_at 265
#define CPACR_ELx_FPEN_WIDTH 2
#define PR_FP_EXC_ASYNC 2
#define PIRx_ELx_Perm11_MASK GENMASK(47, 44)
#define __skb_checksum_validate(skb,proto,complete,zero_okay,check,compute_pseudo) ({ __sum16 __ret = 0; skb->csum_valid = 0; if (__skb_checksum_validate_needed(skb, zero_okay, check)) __ret = __skb_checksum_validate_complete(skb, complete, compute_pseudo(skb, proto)); __ret; })
#define percpu_counter_init(fbc,value,gfp) percpu_counter_init_many(fbc, value, gfp, 1)
#define KASAN_TAG_KERNEL 0xFF
#define Q_XQUOTAON XQM_CMD(1)
#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
#define __NR_fchmodat2 452
#define PIRx_ELx_Perm0_WIDTH 4
#define ID_AA64ISAR2_EL1_PAC_frac_MASK GENMASK(27, 24)
#define PARITY_CRC32_PR1_CCITT 7
#define SIOCGHWTSTAMP 0x89b1
#define io_stop_wc() dgh()
#define CONFIG_WLAN_VENDOR_INTERSIL 1
#define TCR2_EL2_AMEC1_WIDTH 1
#define HSIPHASH_CONST_0 0U
#define PR_MPX_DISABLE_MANAGEMENT 44
#define param_check_ushort(name,p) __param_check(name, p, unsigned short)
#define pte_offset_kernel pte_offset_kernel
#define IPV6_TLV_JUMBO 194
#define F_RDLCK 0
#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
#define SYSCTL_FOUR ((void *)&sysctl_vals[4])
#define IPV6_IPSEC_POLICY 34
#define __DEFINE_UNLOCK_GUARD(_name,_type,_unlock,...) typedef struct { _type *lock; __VA_ARGS__; } class_ ##_name ##_t; static inline void class_ ##_name ##_destructor(class_ ##_name ##_t *_T) { if (_T->lock) { _unlock; } }
#define plist_prev(pos) list_prev_entry(pos, node_list)
#define ARM64_WORKAROUND_2658417 80
#define SCTLR_EL1_EnAS0_WIDTH 1
#define ARM_CPU_PART_CORTEX_A78AE 0xD42
#define ID_AA64MMFR1_EL1_PAN_NI UL(0b0000)
#define FIGETBSZ _IO(0x00,2)
#define SOCK_MAX (SOCK_PACKET + 1)
#define readb_relaxed_poll_timeout(addr,val,cond,delay_us,timeout_us) readx_poll_timeout(readb_relaxed, addr, val, cond, delay_us, timeout_us)
#define SYS_CONTEXTIDR_EL2_CRm 0
#define SYS_CONTEXTIDR_EL2_CRn 13
#define ID_ISAR6_EL1_DP_MASK GENMASK(7, 4)
#define LED_FUNCTION_LAN "lan"
#define Q_SETQUOTA 0x800008
#define list_next_rcu(list) (*((struct list_head __rcu **)(&(list)->next)))
#define SD_INIT_NAME(type) 
#define ID_ISAR1_EL1_Endian_WIDTH 4
#define PACKET_FANOUT_CBPF 6
#define STA_DEL 0x0020
#define CAP_FS_SET ((kernel_cap_t) { CAP_FS_MASK | BIT_ULL(CAP_LINUX_IMMUTABLE) })
#define IPV6_2292HOPOPTS 3
#define ID_AA64MMFR0_EL1_TGRAN4_2_TGRAN4 UL(0b0000)
#define CONFIG_ARCH_FORCE_MAX_ORDER 10
#define CONFIG_NET_VENDOR_MICREL 1
#define ID_AA64MMFR1_EL1_LO_SHIFT 16
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
#define HFGxTR_EL2_MAIR_EL1 GENMASK(24, 24)
#define ZCR_ELx_LEN_WIDTH 4
#define HFGITR_EL2_ATS1E1WP_WIDTH 1
#define QTREE_DEL_ALLOC 0
#define NETLINK_LISTEN_ALL_NSID 8
#define HFGITR_EL2_TLBIVALE1_SHIFT 46
#define CONFIG_NET_VENDOR_CAVIUM 1
#define ID_AA64ISAR1_EL1_DPB_WIDTH 4
#define local_softirq_pending_ref irq_stat.__softirq_pending
#define HFGxTR_EL2_DCZID_EL0_WIDTH 1
#define DBG_SPSR_SS (1 << 21)
#define IPPROTO_FRAGMENT 44
#define ID_AA64PFR0_EL1_DIT_WIDTH 4
#define _LINUX_PROJID_H 
#define hlist_for_each_entry_from_rcu(pos,member) for (; pos; pos = hlist_entry_safe(rcu_dereference_raw(hlist_next_rcu( &(pos)->member)), typeof(*(pos)), member))
#define SELECT_STACK_ALLOC FRONTEND_STACK_ALLOC
#define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
#define EPOLLEXCLUSIVE ((__force __poll_t)(1U << 28))
#define compat_r12_fiq regs[28]
#define SCHED_RR 2
#define HWCAP2_SVEF32MM (1 << 10)
#define TASK_UNINTERRUPTIBLE 0x00000002
#define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
#define __NR_sched_setparam 118
#define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
#define MDIO_MMD_VEND1 30
#define TCR2_EL1x_E0POE GENMASK(2, 2)
#define TRBIDR_EL1_EA GENMASK(11, 8)
#define MDSCR_EL1_SS_SHIFT 0
#define KBUILD_MODFILE "rust/bindings_generated"
#define ETHTOOL_GPHYSTATS 0x0000004a
#define __pass_dynamic_object_size(type) 
#define BLKTRACETEARDOWN _IO(0x12,118)
#define ID_AA64MMFR3_EL1_ADERR_FEAT_ADERR UL(0b0010)
#define HFGITR_EL2_ICIALLU_SHIFT 1
#define ETH_RSS_HASH_TOP __ETH_RSS_HASH(TOP)
#define SLAB_TRACE ((slab_flags_t __force)0x00200000U)
#define BMSR_LSTATUS 0x0004
#define __ASM_IO_H 
#define ID_AA64MMFR2_EL1_VARange_48 UL(0b0000)
#define BITMAP_MEM_MASK (BITMAP_MEM_ALIGNMENT - 1)
#define HFGxTR_EL2_nTPIDR2_EL0 GENMASK(55, 55)
#define NMI_MASK (__IRQ_MASK(NMI_BITS) << NMI_SHIFT)
#define __LINUX_COMPILER_ATTRIBUTES_H 
#define SB_NOATIME BIT(10)
#define PCI_ANY_ID (~0)
#define is_syscall_success(regs) (!IS_ERR_VALUE((unsigned long)(regs_return_value(regs))))
#define CONFIG_SECRETMEM 1
#define ID_PFR0_EL1_State0_WIDTH 4
#define CLONE_NEWNET 0x40000000
#define PSR_AA32_N_BIT 0x80000000
#define __NR_timer_gettime 108
#define PAGE_IS_SWAPPED (1 << 4)
#define __initdata __section(".init.data")
#define raw_xchg_release arch_xchg_release
#define MVFR1_EL1_FPFtZ_NI UL(0b0000)
#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
#define ID_AA64ISAR0_EL1_DP_IMP UL(0b0001)
#define REG_PMBIDR_EL1 S3_0_C9_C10_7
#define IPV6_TCLASS 67
#define __ASM_ATOMIC_LSE_H 
#define KASAN_TAG_WIDTH 0
#define LORID_EL1_RES0 (UL(0) | GENMASK_ULL(63, 24) | GENMASK_ULL(15, 8))
#define LORID_EL1_RES1 (UL(0))
#define CLIDR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 47))
#define CLIDR_EL1_RES1 (UL(0))
#define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39))
#define ID_DFR1_EL1_UNKN (UL(0))
#define HFGITR_EL2_TLBIVMALLE1OS GENMASK(18, 18)
#define _LINUX_PARAM_H 
#define ID_ISAR4_EL1_WithShifts_MASK GENMASK(7, 4)
#define ID_AA64MMFR1_EL1_XNX_SHIFT 28
#define SMPRIMAP_EL2_P15_WIDTH 4
#define CONFIG_LIBFDT 1
#define TRBSR_EL1_DAT_MASK GENMASK(23, 23)
#define HCR_VI (UL(1) << 7)
#define MDIO_AN_C73_1_100GBASE_KP4 BIT(11)
#define arch_atomic_fetch_andnot_relaxed arch_atomic_fetch_andnot_relaxed
#define __VDSO_BITS_H 
#define __ASM_GENERIC_DELAY_H 
#define _LINUX_WAIT_BIT_H 
#define ID_AA64PFR1_EL1_UNKN (UL(0))
#define ETH_P_NCSI 0x88F8
#define ALTIFNAMSIZ 128
#define lockdep_hardirq_exit() do { __this_cpu_dec(hardirq_context); } while (0)
#define TIMER_ARRAYMASK 0xFFC00000
#define si_ptr _sifields._rt._sigval.sival_ptr
#define FDPUT_FPUT 1
#define __NR_rseq 293
#define _LINUX_BUILDID_H 
#define NULLS_MARKER(value) (1UL | (((long)value) << 1))
#define LMI_CISCO 4
#define TRBMAR_EL1_UNKN (UL(0))
#define cpu_to_be32p __cpu_to_be32p
#define cpu_to_be32s __cpu_to_be32s
#define ETH_P_REALTEK 0x8899
#define MDIO_EEE_100GR_DS 0x2000
#define __ARCH_WANT_SYS_CLONE3 
#define ENOTTY 25
#define EM_88K 5
#define CONFIG_CRYPTO_ALGAPI2 1
#define HFGITR_EL2_TLBIRVAE1_SHIFT 38
#define MDIO_PMD_RXDET_0 0x0002
#define ARM64_WORKAROUND_AMPERE_AC03_CPU_38 82
#define MVFR1_EL1_FPHP_FP16 UL(0b0011)
#define TTBRx_EL1_ASID_MASK GENMASK(63, 48)
#define SO_ATTACH_REUSEPORT_CBPF 51
#define _KGDB_H_ 
#define U64_MAX ((u64)~0ULL)
#define list_for_each_continue(pos,head) for (pos = pos->next; !list_is_head(pos, (head)); pos = pos->next)
#define PAC_RESET_KEYS(tsk,arg) ptrauth_prctl_reset_keys(tsk, arg)
#define PF_KTHREAD 0x00200000
#define __cold 
#define HDFGWTR_EL2_TRCIMSPECn_WIDTH 1
#define MOD_NANO ADJ_NANO
#define F_LINUX_SPECIFIC_BASE 1024
#define ID_ISAR1_EL1_IfThen_MASK GENMASK(19, 16)
#define __malloc __attribute__((__malloc__))
#define MVFR1_EL1_SIMDLS GENMASK(11, 8)
#define NETIF_F_HW_TC __NETIF_F(HW_TC)
#define OBJPOOL_OBJECT_SIZE_MAX (1UL << 16)
#define raw_local_save_flags(flags) do { typecheck(unsigned long, flags); flags = arch_local_save_flags(); } while (0)
#define rcu_head callback_head
#define ID_AA64DFR0_EL1_MTPMU_WIDTH 4
#define static_branch_inc(x) static_key_slow_inc(&(x)->key)
#define ID_ISAR6_EL1_I8MM_SIGNED false
#define arch___test_and_clear_bit generic___test_and_clear_bit
#define SYS_HCRX_EL2_Op0 3
#define SYS_HCRX_EL2_Op1 4
#define SYS_HCRX_EL2_Op2 2
#define SIOCGIFTXQLEN 0x8942
#define _UAPI_LINUX_CONST_H 
#define rwsem_release(l,i) lock_release(l, i)
#define PMSCR_EL2_PA_WIDTH 1
#define ETHTOOL_FLASHDEV 0x00000033
#define ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
#define ID_AA64MMFR0_EL1_PARANGE_MASK GENMASK(3, 0)
#define ID_MMFR4_EL1_SpecSEI_MASK GENMASK(3, 0)
#define CONFIG_FREEZER 1
#define raw_cmpxchg_acquire arch_cmpxchg_acquire
#define pmd_offset_phys(dir,addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
#define UTIME_NOW ((1l << 30) - 1l)
#define REG_MDSCR_EL1 S2_0_C0_C2_2
#define DACR32_EL2_D9_MASK GENMASK(19, 18)
#define ZONES_SHIFT 2
#define unsafe_get_user(x,p,e) unsafe_op_wrap(__get_user(x,p),e)
#define ID_MMFR1_EL1_L1Hvd_WIDTH 4
#define ELFCLASS32 1
#define VTCR_EL2_TGRAN_SL0_BASE 2UL
#define MM_CP_UFFD_WP (1UL << 2)
#define ID_AA64MMFR0_EL1_EXS_MASK GENMASK(47, 44)
#define HDFGRTR_EL2_PMSCR_EL1 GENMASK(26, 26)
#define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
#define S_ISGID 0002000
#define BRCM_CPU_PART_VULCAN 0x516
#define LRU_GEN_PGOFF (KASAN_TAG_PGOFF - LRU_GEN_WIDTH)
#define HFGITR_EL2_TLBIRVAE1_MASK GENMASK(38, 38)
#define EPOLL_URING_WAKE ((__force __poll_t)(1U << 27))
#define __NR_copy_file_range 285
#define CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE 1
#define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
#define ARM64_HAS_GIC_PRIO_MASKING 30
#define MII_PHYSID1 0x02
#define ID_AA64PFR0_EL1_DIT_SIGNED false
#define ID_MMFR1_EL1_L1TstCln_SHIFT 24
#define MDIO_MMD_C22EXT 29
#define PF_KSWAPD 0x00020000
#define MDCCINT_EL1_RX GENMASK(30, 30)
#define SYS_ID_ISAR5_EL1_CRn 0
#define SYS_LOREA_EL1_Op0 3
#define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
#define CONFIG_ARM_GIC_V3 1
#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
#define ID_ISAR6_EL1_I8MM_IMP UL(0b0001)
#define HDFGWTR_EL2_PMCR_EL0_SHIFT 21
#define ___GFP_NORETRY 0x10000u
#define MDIO_STAT1_FAULT 0x0080
#define CLONE_NEWCGROUP 0x02000000
#define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
#define __ASM_TOPOLOGY_H 
#define smp_store_mb(var,value) do { kcsan_mb(); __smp_store_mb(var, value); } while (0)
#define PCMCIA_DEV_ID_MATCH_PROD_ID3 0x0040
#define PR_GET_SECUREBITS 27
#define __KERNEL_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define CONFIG_SND_JACK_INPUT_DEV 1
#define MVFR1_EL1_SIMDInt_IMP UL(0b0001)
#define IPV6_TLV_IOAM 49
#define offset_in_folio(folio,p) ((unsigned long)(p) & (folio_size(folio) - 1))
#define HCR_DCT (UL(1) << 57)
#define JOBCTL_LISTENING (1UL << JOBCTL_LISTENING_BIT)
#define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
#define RXH_L2DA (1 << 1)
#define JOBCTL_PTRACE_FROZEN (1UL << JOBCTL_PTRACE_FROZEN_BIT)
#define NETIF_F_HW_ESP __NETIF_F(HW_ESP)
#define SYS_MVFR0_EL1_CRm 3
#define for_each_present_cpu(cpu) for_each_cpu((cpu), cpu_present_mask)
#define HFGxTR_EL2_CCSIDR_EL1 GENMASK(9, 9)
#define INIT_CPU_TIMERBASES(b) { INIT_CPU_TIMERBASE(b[0]), INIT_CPU_TIMERBASE(b[1]), INIT_CPU_TIMERBASE(b[2]), }
#define TRBSR_EL1_MSS2_SHIFT 32
#define PFN_PHYS(x) ((phys_addr_t)(x) << PAGE_SHIFT)
#define DACR32_EL2_D5_SHIFT 10
#define ISR_EL1_I_WIDTH 1
#define arch_raw_cpu_ptr(ptr) SHIFT_PERCPU_PTR(ptr, __my_cpu_offset)
#define MDCCINT_EL1_TX GENMASK(29, 29)
#define __smp_mb__before_atomic() __smp_mb()
#define llist_for_each_entry_safe(pos,n,node,member) for (pos = llist_entry((node), typeof(*pos), member); member_address_is_nonnull(pos, member) && (n = llist_entry(pos->member.next, typeof(*n), member), true); pos = n)
#define CONFIG_TTY 1
#define CONFIG_EFI_PARTITION 1
#define SOL_TIPC 271
#define PR_SET_MM_ENV_END 11
#define xchg_relaxed(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_xchg_relaxed(__ai_ptr, __VA_ARGS__); })
#define ID_AA64ISAR0_EL1_CRC32_SIGNED false
#define DYNAMIC_DEBUG_BRANCH(descriptor) false
#define ___GFP_NOWARN 0x2000u
#define KUNIT_EXPECT_NOT_NULL(test,ptr) KUNIT_EXPECT_NOT_NULL_MSG(test, ptr, NULL)
#define devm_add_action(dev,action,data) __devm_add_action(dev, action, data, #action)
#define _LINUX_RANGE_H 
#define netif_info(priv,type,dev,fmt,args...) netif_level(info, priv, type, dev, fmt, ##args)
#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
#define SO_ERROR 4
#define SB_DEAD BIT(21)
#define ID_AA64ISAR1_EL1_LS64_LS64_V UL(0b0010)
#define NETIF_F_IPV6_CSUM __NETIF_F(IPV6_CSUM)
#define _Q_LOCKED_BITS 8
#define MVFR0_EL1_FPShVec_WIDTH 4
#define KCSAN_ACCESS_SCOPED (1 << 4)
#define HDFGRTR_EL2_PMSIDR_EL1_MASK GENMASK(30, 30)
#define ____is_defined(arg1_or_junk) __take_second_arg(arg1_or_junk 1, 0)
#define MVFR0_EL1_SIMDReg_NI UL(0b0000)
#define idr_lock(idr) xa_lock(&(idr)->idr_rt)
#define _UAPI_LINUX_KDEV_T_H 
#define ARM64_HAS_FPSIMD 24
#define MDIO_PMA_CTRL2_5GBT 0x0031
#define MDSCR_EL1_TFO_SHIFT 31
#define SLAB_OBJ_MIN_SIZE (KMALLOC_MIN_SIZE < 16 ? (KMALLOC_MIN_SIZE) : 16)
#define PACKET_USER 6
#define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
#define UTIL_AVG_UNCHANGED 0x80000000
#define s6_addr in6_u.u6_addr8
#define SKB_DST_PTRMASK ~(SKB_DST_NOREF)
#define __ASM_GENERIC_QRWLOCK_TYPES_H 
#define ID_ISAR4_EL1_SWP_frac_IMP UL(0b0001)
#define LOCKSTAT_POINTS 4
#define ID_AA64PFR0_EL1_RAS_SIGNED false
#define RATELIMIT_STATE_INIT_FLAGS(name,interval_init,burst_init,flags_init) { .lock = __RAW_SPIN_LOCK_UNLOCKED(name.lock), .interval = interval_init, .burst = burst_init, .flags = flags_init, }
#define _UAPI_LINUX_SECCOMP_H 
#define TCR2_EL1x_D128 GENMASK(5, 5)
#define MDIO_PCS_10GBRT_STAT2 33
#define __NR_faccessat 48
#define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x))
#define PMSG_SUSPEND ((struct pm_message){ .event = PM_EVENT_SUSPEND, })
#define CONFIG_GENERIC_IRQ_IPI_MUX 1
#define MVFR1_EL1_SIMDSP GENMASK(19, 16)
#define SEMAEM SEMVMX
#define ETH_P_DNA_RT 0x6003
#define ETHTOOL_RMON_HIST_MAX 10
#define ETH_P_NSH 0x894F
#define SHM_HUGE_1MB HUGETLB_FLAG_ENCODE_1MB
#define DBG_ESR_EVT_HWSS 0x1
#define IORESOURCE_MEM_16BIT (1<<3)
#define SKB_MAX_ORDER(X,ORDER) SKB_WITH_OVERHEAD((PAGE_SIZE << (ORDER)) - (X))
#define __NR_statx 291
#define ARM_CPU_PART_FOUNDATION 0xD00
#define HFGITR_EL2_DVPRCTX_MASK GENMASK(49, 49)
#define _LINUX_DQBLK_QTREE_H 
#define LED_SET_BLINK 8
#define CONFIG_NEED_SG_DMA_FLAGS 1
#define HDFGRTR_EL2_PMINTEN_WIDTH 1
#define REG_SMIDR_EL1 S3_1_C0_C0_6
#define HDFGRTR_EL2_PMEVTYPERn_EL0_MASK GENMASK(13, 13)
#define LMI_NONE 1
#define ENETRESET 102
#define MDCR_EL2_TDCC (UL(1) << 27)
#define ID_AFR0_EL1_IMPDEF3_MASK GENMASK(15, 12)
#define MDIO_PKGID2 15
#define ESR_ELx_EC_FP_EXC32 (0x28)
#define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
#define SECCOMP_ADDFD_FLAG_SETFD (1UL << 0)
#define MDSCR_EL1_MDE_WIDTH 1
#define HRTIMER_STATE_INACTIVE 0x00
#define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
#define AF_ROSE 11
#define SOL_SCTP 132
#define SECTIONS_SHIFT (MAX_PHYSMEM_BITS - SECTION_SIZE_BITS)
#define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
#define ID_AA64MMFR3_EL1_ANERR_FEAT_ANERR UL(0b0010)
#define FS_NOCOW_FL 0x00800000
#define ID_AA64ISAR1_EL1_BF16_MASK GENMASK(47, 44)
#define __LINKMODE_H 
#define arch_atomic_fetch_sub_acquire arch_atomic_fetch_sub_acquire
#define HFGITR_EL2_ATS1E1W_MASK GENMASK(13, 13)
#define IORESOURCE_PCI_EA_BEI (1<<5)
#define sve_vl_from_vq(vq) __sve_vl_from_vq(vq)
#define _UAPI_LINUX_ETHTOOL_H 
#define NT_S390_SYSTEM_CALL 0x307
#define ARM64_FEATURE_MASK(x) (x ##_MASK)
#define HFGxTR_EL2_LORC_EL1_WIDTH 1
#define CHRDEV_MAJOR_MAX 512
#define CONFIG_NET_VENDOR_AMAZON 1
#define ID_MMFR4_EL1_EVT_SIGNED false
#define CONFIG_ARM_GIC_V3_ITS_PCI 1
#define LPA_100FULL 0x0100
#define ifr_netmask ifr_ifru.ifru_netmask
#define RXH_IP_SRC (1 << 4)
#define REQUEUE_PENDING 1
#define REG_ID_MMFR1_EL1 S3_0_C0_C1_5
#define STATX_ATTR_CHANGE_MONOTONIC 0x8000000000000000ULL
#define CAP_FOWNER 3
#define __SVE_ZREG_OFFSET(vq,n) (__SVE_ZREGS_OFFSET + __SVE_ZREG_SIZE(vq) * (n))
#define xpaclri(ptr) ({ register unsigned long __xpaclri_ptr asm("x30") = (ptr); asm( ARM64_ASM_PREAMBLE "	hint	#7\n" : "+r" (__xpaclri_ptr)); __xpaclri_ptr; })
#define __assume_page_alignment __assume_aligned(PAGE_SIZE)
#define SHN_HIRESERVE 0xffff
#define MDIO_PCS_STAT2_10GBW 0x0004
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define ID_AA64PFR0_EL1_CSV2_MASK GENMASK(59, 56)
#define CRm_shift 8
#define write_seqcount_begin_nested(s,subclass) do { seqprop_assert(s); if (seqprop_preemptible(s)) preempt_disable(); do_write_seqcount_begin_nested(seqprop_ptr(s), subclass); } while (0)
#define PMBLIMITR_EL1_E_WIDTH 1
#define FTR_VISIBLE_IF_IS_ENABLED(config) (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
#define PR_GET_KEEPCAPS 7
#define ESR_ELx_EC_BRK64 (0x3C)
#define ID_MMFR3_EL1_Supersec_NI UL(0b1111)
#define ID_AA64DFR0_EL1_PMUVer_SHIFT 8
#define folio_ref_zero_or_close_to_overflow(folio) ((unsigned int) folio_ref_count(folio) + 127u <= 127u)
#define MVFR2_EL1_SIMDMisc_SHIFT 0
#define __NR_sysinfo 179
#define __ASM_GENERIC_BITS_PER_LONG 
#define raw_cpu_sub_return(pcp,val) raw_cpu_add_return(pcp, -(typeof(pcp))(val))
#define preemptible() (preempt_count() == 0 && !irqs_disabled())
#define __NR_getrandom 278
#define spin_acquire(l,s,t,i) lock_acquire_exclusive(l, s, t, NULL, i)
#define __swab16(x) (__u16)(__builtin_constant_p(x) ? ___constant_swab16(x) : __fswab16(x))
#define IORESOURCE_RANGELENGTH 0x00010000
#define CONFIG_FRAME_POINTER 1
#define MVFR1_EL1_SIMDFMAC_SIGNED false
#define DT_NULL 0
#define CLOCK_DEFAULT 0
#define PRIO_USER 2
#define ID_PFR0_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_PFR0_EL1_RES1 (UL(0))
#define MDIO_PHY_ID_C45_MASK (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
#define TP_FT_REQ_FILL_RXHASH 0x1
#define SYS_TRBMAR_EL1_Op2 4
#define _LINUX_SCHED_COREDUMP_H 
#define SIOCSIFBRDADDR 0x891a
#define ID_MMFR3_EL1_CohWalk_SHIFT 20
#define PTRACE_O_TRACESECCOMP (1 << PTRACE_EVENT_SECCOMP)
#define CAP_VALID_MASK (BIT_ULL(CAP_LAST_CAP+1)-1)
#define SYS_RECVMMSG 19
#define ID_AA64PFR1_EL1_DF2 GENMASK(59, 56)
#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34
#define __HDFGWTR_EL2_nMASK GENMASK(62, 60)
#define radix_tree_node xa_node
#define _UAPI_ASM_GENERIC_IOCTL_H 
#define ID_AA64PFR1_EL1_DF2_NI UL(0b0000)
#define hashlen_create(hash,len) ((u64)(len)<<32 | (u32)(hash))
#define __ETH_RSS_HASH(name) __ETH_RSS_HASH_BIT(ETH_RSS_HASH_ ##name ##_BIT)
#define PF_BLUETOOTH AF_BLUETOOTH
#define ERESTARTNOHAND 514
#define ETH_GSTRING_LEN 32
#define AARCH64_INSN_SIZE 4
#define IF_GET_IFACE 0x0001
#define ID_ISAR0_EL1_CmpBranch_NI UL(0b0000)
#define INIT_USER (&root_user)
#define __swab32(x) (__u32)(__builtin_constant_p(x) ? ___constant_swab32(x) : __fswab32(x))
#define HCR_FIEN (UL(1) << 47)
#define SOL_TCP 6
#define DEFINE_WAIT_BIT(name,word,bit) struct wait_bit_queue_entry name = { .key = __WAIT_BIT_KEY_INITIALIZER(word, bit), .wq_entry = { .private = current, .func = wake_bit_function, .entry = LIST_HEAD_INIT((name).wq_entry.entry), }, }
#define HZ_TO_USEC_SHR32 20
#define ARM_CPU_IMP_QCOM 0x51
#define ID_ISAR3_EL1_TrueNOP_MASK GENMASK(27, 24)
#define SKB_DR(name) SKB_DR_INIT(name, NOT_SPECIFIED)
#define __SYSCALL(x,y) 
#define pud_write(pud) pte_write(pud_pte(pud))
#define __level_param_cb(name,ops,arg,perm,level) __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, level, 0)
#define PSTATE_UAO pstate_field(0, 3)
#define NLMSG_MIN_TYPE 0x10
#define strtomem_pad(dest,src,pad) do { const size_t _dest_len = __builtin_object_size(dest, 1); const size_t _src_len = __builtin_object_size(src, 1); BUILD_BUG_ON(!__builtin_constant_p(_dest_len) || _dest_len == (size_t)-1); memcpy_and_pad(dest, _dest_len, src, strnlen(src, min(_src_len, _dest_len)), pad); } while (0)
#define ETHTOOL_GLINKSETTINGS 0x0000004c
#define transparent_hugepage_flags 0UL
#define ID_AA64MMFR3_EL1_ADERR_SHIFT 56
#define outsb outsb
#define ID_AA64DFR0_EL1_TraceVer GENMASK(7, 4)
#define CONFIG_DEFAULT_SECURITY_DAC 1
#define CONFIG_CC_HAS_BRANCH_PROT_PAC_RET 1
#define HFGITR_EL2_TLBIASIDE1_SHIFT 44
#define HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT 13
#define ETHTOOL_FEC_AUTO (1 << ETHTOOL_FEC_AUTO_BIT)
#define PHYS_ADDR_MAX (~(phys_addr_t)0)
#define _LINUX_PM_H 
#define HDFGRTR_EL2_PMUSERENR_EL0_SHIFT 57
#define ESP_V6_FLOW 0x0c
#define ID_AA64SMFR0_EL1_I16I32_NI UL(0b0000)
#define compat_fp regs[11]
#define SCTLR_EL1_UMA_WIDTH 1
#define SYS_PMSICR_EL1_Op1 0
#define ID_AA64PFR1_EL1_RAS_frac_NI UL(0b0000)
#define PF_WANPIPE AF_WANPIPE
#define MDIO_SUPPORTS_C45 2
#define ZORRO_DEVICE_MODALIAS_FMT "zorro:i%08X"
#define local_dec(l) atomic_long_dec(&(l)->a)
#define sig_fatal(t,signr) (!siginmask(signr, SIG_KERNEL_IGNORE_MASK|SIG_KERNEL_STOP_MASK) && (t)->sighand->action[(signr)-1].sa.sa_handler == SIG_DFL)
#define PF_USED_MATH 0x00002000
#define ID_AA64SMFR0_EL1_I8I32_NI UL(0b0000)
#define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
#define SYS_PIR_EL1_Op0 3
#define SYS_PIR_EL1_Op2 3
#define __NR_sched_getaffinity 123
#define TAINT_UNSIGNED_MODULE 13
#define ID_ISAR3_EL1_TabBranch_NI UL(0b0000)
#define CONFIG_ARM_GIC 1
#define PPM_SCALE ((s64)NSEC_PER_USEC << (NTP_SCALE_SHIFT - SHIFT_USEC))
#define TRBSR_EL1_MSS_MASK GENMASK(15, 0)
#define ___GFP_DMA 0x01u
#define current_gid() (current_cred_xxx(gid))
#define CONFIG_ARM64_4K_PAGES 1
#define SHM_UNLOCK 12
#define QUOTA_NL_BHARDWARN 4
#define time_is_before_jiffies(a) time_after(jiffies, a)
#define VM_MIXEDMAP 0x10000000
#define set_fixmap_io(idx,phys) __set_fixmap(idx, phys, FIXMAP_PAGE_IO)
#define FLOW_CTRL_TX 0x01
#define sync_cmpxchg(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_mb(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_sync_cmpxchg(__ai_ptr, __VA_ARGS__); })
#define TIME_SETTOD_SEC_MAX (KTIME_SEC_MAX - TIME_UPTIME_SEC_MAX)
#define CONFIG_CMDLINE_FROM_BOOTLOADER 1
#define PMBSR_EL1_S GENMASK(17, 17)
#define POLL_MSG 3
#define I_CREATING (1 << 15)
#define CONFIG_BLK_CGROUP 1
#define EM_LOONGARCH 258
#define CONFIG_RELOCATABLE 1
#define PIRx_ELx_Perm6_MASK GENMASK(27, 24)
#define ID_MMFR1_EL1_L1UniSW_NI UL(0b0000)
#define __TIMER_LOCKDEP_MAP_INITIALIZER(_kn) .lockdep_map = STATIC_LOCKDEP_MAP_INIT(_kn, &_kn),
#define TCR2_EL2_E0POE GENMASK(2, 2)
#define LOCK_READ 64
#define CLIDR_EL1_Ctype1_WIDTH 3
#define SCTLR_EL1_SPAN GENMASK(23, 23)
#define CONFIG_FSNOTIFY 1
#define pr_crit(fmt,...) printk(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__)
#define ___wait_cond_timeout(condition) ({ bool __cond = (condition); if (__cond && !__ret) __ret = 1; __cond || !__ret; })
#define SYS_LORSA_EL1_Op0 3
#define ptrauth_thread_init_user() 
#define __GFP_KSWAPD_RECLAIM ((__force gfp_t)___GFP_KSWAPD_RECLAIM)
#define FAULT_FLAG_DEFAULT (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | FAULT_FLAG_INTERRUPTIBLE)
#define SHF_WRITE 0x1
#define OVERFLOW_PROJID 65534
#define ID_AA64DFR0_EL1_MTPMU_NI_IMPDEF UL(0b0000)
#define MSG_SYN 0x400
#define PMSCR_EL1_PCT_MASK GENMASK(7, 6)
#define __I_NEW 3
#define AMPERE_CPU_PART_AMPERE1 0xAC3
#define raw_xchg_relaxed arch_xchg_relaxed
#define p4d_offset_lockless(pgdp,pgd,address) p4d_offset(&(pgd), address)
#define TCR2_EL2_PnCH_WIDTH 1
#define __NR_mq_notify 184
#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
#define CONFIG_NET_VENDOR_SILAN 1
#define CONFIG_CRYPTO_HASH 1
#define SYS_SMCR_EL12_CRm 2
#define SYS_SMCR_EL12_CRn 1
#define KUIDT_INIT(value) (kuid_t){ value }
#define IF_PROTO_FR_PVC 0x200A
#define SEM_STAT_ANY 20
#define BLKROGET _IO(0x12,94)
#define local64_inc(l) local_inc(&(l)->a)
#define Q_XGETQSTATV XQM_CMD(8)
#define UMOUNT_NOFOLLOW 0x00000008
#define pageblock_start_pfn(pfn) ALIGN_DOWN((pfn), pageblock_nr_pages)
#define PMSIDR_EL1_INTERVAL_3072 UL(0b0111)
#define CONFIG_INOTIFY_USER 1
#define ___constant_swahb32(x) ((__u32)( (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)))
#define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO)
#define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
#define __kcsan_check_read(ptr,size) __kcsan_check_access(ptr, size, 0)
#define raw_cpu_cmpxchg_1(pcp,oval,nval) raw_cpu_generic_cmpxchg(pcp, oval, nval)
#define raw_cpu_cmpxchg_2(pcp,oval,nval) raw_cpu_generic_cmpxchg(pcp, oval, nval)
#define PR_SET_MM 35
#define ID_AA64ZFR0_EL1_B16B16_IMP UL(0b0001)
#define __NR_semget 190
#define ID_AA64PFR0_EL1_SVE_SIGNED false
#define __SC_COMP(_nr,_sys,_comp) __SYSCALL(_nr, _sys)
#define TRBSR_EL1_UNKN (UL(0))
#define PHY_ANY_UID 0xffffffff
#define SIOCINQ FIONREAD
#define ADVERTISED_Autoneg __ETHTOOL_LINK_MODE_LEGACY_MASK(Autoneg)
#define SZ_512K 0x00080000
#define SZ_512M 0x20000000
#define NR_FWNODE_REFERENCE_ARGS 8
#define __local64_add(i,l) local64_set((l), local64_read(l) + (i))
#define ETH_P_SCA 0x6007
#define IORESOURCE_TYPE_BITS 0x00001f00
#define TCR2_EL2_PTTWI_WIDTH 1
#define PACKET_QDISC_BYPASS 20
#define CONFIG_NET_VENDOR_BROADCOM 1
#define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3)
#define DEPRECATED "[Deprecated]: "
#define ULL(x) (_ULL(x))
#define CAP_SYS_RESOURCE 24
#define MDCR_EL2_HPMFZS (UL(1) << 36)
#define ethtool_link_ksettings_test_link_mode(ptr,name,mode) test_bit(ETHTOOL_LINK_MODE_ ## mode ## _BIT, (ptr)->link_modes.name)
#define TCR2_EL1x_AIE GENMASK(4, 4)
#define SYS_ID_PFR1_EL1_Op0 3
#define ESR_ELx_FSC_SERROR (0x11)
#define HDFGRTR_EL2_PMBPTR_EL1_WIDTH 1
#define NR_SECTION_ROOTS DIV_ROUND_UP(NR_MEM_SECTIONS, SECTIONS_PER_ROOT)
#define DBG_ESR_EVT_VECC 0x5
#define cpu_possible_mask ((const struct cpumask *)&__cpu_possible_mask)
#define ID_PFR1_EL1_GenTimer GENMASK(19, 16)
#define ID_AA64ISAR1_EL1_FRINTTS_MASK GENMASK(35, 32)
#define DEVICE_ATTR(_name,_mode,_show,_store) struct device_attribute dev_attr_ ##_name = __ATTR(_name, _mode, _show, _store)
#define NETIF_F_HW_VLAN_CTAG_TX __NETIF_F(HW_VLAN_CTAG_TX)
#define SYS_ID_AA64MMFR2_EL1_Op1 0
#define CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 1
#define DEFINE_STATIC_SRCU(name) __DEFINE_SRCU(name, static)
#define PMSEVFR_EL1_E_MASK GENMASK(63, 0)
#define rt_sigmask(sig) sigmask(sig)
#define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
#define _LINUX_RETHOOK_H 
#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
#define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE)
#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU)
#define ARM64_NCAPS 97
#define ETH_RX_NFC_IP4 1
#define HDFGRTR_EL2_PMBIDR_EL1_MASK GENMASK(63, 63)
#define STA_PPSWANDER 0x0400
#define HFGxTR_EL2_TCR_EL1_SHIFT 32
#define compat_lr regs[14]
#define PMBIDR_EL1_F_WIDTH 1
#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
#define skb_queue_reverse_walk_from_safe(queue,skb,tmp) for (tmp = skb->prev; skb != (struct sk_buff *)(queue); skb = tmp, tmp = skb->prev)
#define CONFIG_NLATTR 1
#define try_cmpxchg64_acquire(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg64_acquire(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define KERNEL_HWCAP_SVE2P1 __khwcap2_feature(SVE2P1)
#define TRBLIMITR_EL1_UNKN (UL(0))
#define CNTPOFF_EL2_PhysicalOffset_MASK GENMASK(63, 0)
#define R_AARCH64_LDST64_ABS_LO12_NC 286
#define SYS_HDFGRTR_EL2_Op0 3
#define SYS_HDFGRTR_EL2_Op1 4
#define SYS_HDFGRTR_EL2_Op2 4
#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080
#define SCTLR_EL1_TME_MASK GENMASK(53, 53)
#define ID_AA64ISAR1_EL1_API_PAuth2 UL(0b0011)
#define __ASM_ALTERNATIVE_H 
#define s6_addr16 in6_u.u6_addr16
#define PR_TSC_SIGSEGV 2
#define PTRACE_POKEDATA 5
#define MDIO_PMA_10GBT_SNR_MAX 127
#define VM_DMA_COHERENT 0x00000010
#define ID_ISAR6_EL1_FHM_IMP UL(0b0001)
#define lockdep_posixtimer_enter() do { current->irq_config = 1; } while (0)
#define PR_SCHED_CORE_SHARE_FROM 3
#define HDFGRTR_EL2_PMSELR_EL0_WIDTH 1
#define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT)
#define ISR_EL1_A GENMASK(8, 8)
#define MMAP_LOCK_INITIALIZER(name) .mmap_lock = __RWSEM_INITIALIZER((name).mmap_lock),
#define ISR_EL1_F GENMASK(6, 6)
#define ISR_EL1_I GENMASK(7, 7)
#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
#define MVFR1_EL1_FPHP_FPHP UL(0b0001)
#define SUPPORTED_20000baseMLD2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseMLD2_Full)
#define cpu_to_le64p __cpu_to_le64p
#define DEFINE_XARRAY(name) DEFINE_XARRAY_FLAGS(name, 0)
#define cpu_to_le64s __cpu_to_le64s
#define SYS_ID_ISAR6_EL1_CRm 2
#define IFF_SLAVE IFF_SLAVE
#define ETH_RXFH_CONTEXT_ALLOC 0xffffffff
#define MDCR_EL2_TDRA (UL(1) << 11)
#define topology_ppin(cpu) ((void)(cpu), 0ull)
#define POLLWRNORM 0x0100
#define SO_TIMESTAMP_OLD 29
#define ID_AA64PFR0_EL1_CSV3_NI UL(0b0000)
#define TRBPTR_EL1_PTR GENMASK(63, 0)
#define SYS_PIRE0_EL1_Op2 2
#define ID_AA64ISAR0_EL1_TS_NI UL(0b0000)
#define NIL_COOKIE (struct pin_cookie){ .val = 0U, }
#define ARM64_WORKAROUND_REPEAT_TLBI 95
#define __NR_pwritev2 287
#define SCTLR_ELx_EOS (BIT(11))
#define SYS_SMPRI_EL1_CRn 1
#define NOTIFY_BAD (NOTIFY_STOP_MASK|0x0002)
#define HDFGWTR_EL2_TRCVICTLR GENMASK(48, 48)
#define F_OWNER_PGRP 2
#define ID_AA64SMFR0_EL1_I16I64_IMP UL(0b1111)
#define SOL_TLS 282
#define MAX_SCHEDULE_TIMEOUT LONG_MAX
#define ISR_EL1_A_WIDTH 1
#define test_syscall_work(fl) test_ti_thread_flag(current_thread_info(), TIF_ ##fl)
#define ESR_ELx_EC_CP10_ID (0x08)
#define TIMESTAMP_SIZE 30
#define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
#define HCR_AT (UL(1) << 44)
#define ETH_P_TIPC 0x88CA
#define ETH_P_CAN 0x000C
#define SVE_PT_SVE_ZREGS_SIZE(vq) (SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
#define _UAPI_LINUX_SEM_H 
#define INIT_RADIX_TREE(root,mask) xa_init_flags(root, mask)
#define CNTHCTL_EVNTI (0xF << 4)
#define symbol_put(x) do { } while (0)
#define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
#define AT_FDCWD -100
#define NODES_SHIFT 0
#define ARM64_HAS_ARMv8_4_TTL 10
#define _ASM_GENERIC_BITOPS_LOCK_H_ 
#define PF__HOLE__40000000 0x40000000
#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58)
#define ETHTOOL_GPAUSEPARAM 0x00000012
#define local_irq_save(flags) do { raw_local_irq_save(flags); if (!raw_irqs_disabled_flags(flags)) trace_hardirqs_off(); } while (0)
#define _ASM_GENERIC_INT_LL64_H 
#define elf_phdr elf64_phdr
#define SYS_PMBLIMITR_EL1_Op0 3
#define SYS_PMBLIMITR_EL1_Op1 0
#define CONFIG_NEED_SG_DMA_LENGTH 1
#define _ASM_GENERIC_HUGETLB_ENCODE_H_ 
#define SMCR_ELx_EZT0 GENMASK(30, 30)
#define QFMT_VFS_V1 4
#define CSSELR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 5))
#define CSSELR_EL1_RES1 (UL(0))
#define seqcount_LOCKNAME_init(s,_lock,lockname) do { seqcount_ ##lockname ##_t *____s = (s); seqcount_init(&____s->seqcount); __SEQ_LOCK(____s->lock = (_lock)); } while (0)
#define __NR_setfsgid 152
#define __USER_LABEL_PREFIX__ 
#define ID_AA64MMFR0_EL1_EXS_WIDTH 4
#define plist_for_each(pos,head) list_for_each_entry(pos, &(head)->node_list, node_list)
#define MDIO_DEVID1 MII_PHYSID1
#define CMSG_LEN(len) (sizeof(struct cmsghdr) + (len))
#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
#define SYS_ZCR_EL1_Op0 3
#define SYS_ZCR_EL1_Op1 0
#define SYS_ZCR_EL1_Op2 0
#define put_user __put_user
#define for_each_set_bit(bit,addr,size) for ((bit) = 0; (bit) = find_next_bit((addr), (size), (bit)), (bit) < (size); (bit)++)
#define OLD_DT_LOOS 0x60000000
#define ID_ISAR2_EL1_Reversal_WIDTH 4
#define ID_MMFR5_EL1_RES0 (UL(0) | GENMASK_ULL(63, 8))
#define ID_MMFR5_EL1_RES1 (UL(0))
#define key_validate(k) 0
#define MDCCINT_EL1_RX_SHIFT 30
#define PCMCIA_DEV_ID_MATCH_FAKE_CIS 0x0200
#define CONFIG_ARCH_INLINE_WRITE_LOCK 1
#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
#define HUGETLB_FLAG_ENCODE_512KB (19U << HUGETLB_FLAG_ENCODE_SHIFT)
#define __NR_personality 92
#define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features)
#define ID_AA64DFR0_EL1_DebugVer GENMASK(3, 0)
#define OSLAR_EL1_OSLK GENMASK(0, 0)
#define ID_AA64ISAR1_EL1_LS64_WIDTH 4
#define DEFINE_PER_CPU_READ_MOSTLY(type,name) DEFINE_PER_CPU_SECTION(type, name, "..read_mostly")
#define FIRST_USER_ADDRESS 0UL
#define ALLINT_ALLINT_SHIFT 13
#define LED_FUNCTION_FLASH "flash"
#define ADVERTISE_CSMA 0x0001
#define ID_ISAR2_EL1_MultS_MASK GENMASK(19, 16)
#define ilog2(n) ( __builtin_constant_p(n) ? ((n) < 2 ? 0 : 63 - __builtin_clzll(n)) : (sizeof(n) <= 4) ? __ilog2_u32(n) : __ilog2_u64(n) )
#define NLA_HDRLEN ((int) NLA_ALIGN(sizeof(struct nlattr)))
#define PR_PAC_APIAKEY (1UL << 0)
#define RENAME_NOREPLACE (1 << 0)
#define CONFIG_ARM64_LSE_ATOMICS 1
#define percpu_init_rwsem(sem) ({ static struct lock_class_key rwsem_key; __percpu_init_rwsem(sem, #sem, &rwsem_key); })
#define ID_AA64ISAR1_EL1_BF16 GENMASK(47, 44)
#define TRBIDR_EL1_P_SHIFT 4
#define WCONTINUED 0x00000008
#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
#define kunit_test_suites(__suites...) __kunit_test_suites(__UNIQUE_ID(array), ##__suites)
#define ID_AA64ZFR0_EL1_F64MM_MASK GENMASK(59, 56)
#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
#define PFA_SPEC_IB_DISABLE 5
#define RAW_SPIN_DEP_MAP_INIT(lockname) .dep_map = { .name = #lockname, .wait_type_inner = LD_WAIT_SPIN, }
#define compat_sp regs[13]
#define NL_SET_ERR_MSG_FMT(extack,fmt,args...) do { struct netlink_ext_ack *__extack = (extack); if (!__extack) break; if (snprintf(__extack->_msg_buf, NETLINK_MAX_FMTMSG_LEN, "%s" fmt "%s", "", ##args, "") >= NETLINK_MAX_FMTMSG_LEN) net_warn_ratelimited("%s" fmt "%s", "truncated extack: ", ##args, "\n"); do_trace_netlink_extack(__extack->_msg_buf); __extack->_msg = __extack->_msg_buf; } while (0)
#define static_call(name) ((typeof(STATIC_CALL_TRAMP(name))*)(STATIC_CALL_KEY(name).func))
#define raw_cmpxchg_relaxed arch_cmpxchg_relaxed
#define POLLOUT 0x0004
#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
#define ID_AA64ISAR2_EL1_BC_SIGNED false
#define PIRx_ELx_Perm12_MASK GENMASK(51, 48)
#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
#define HFGITR_EL2_DCCISW GENMASK(6, 6)
#define ID_AA64PFR0_EL1_CSV2 GENMASK(59, 56)
#define ID_AA64PFR0_EL1_CSV3 GENMASK(63, 60)
#define ENOTSUPP 524
#define ID_AA64MMFR3_EL1_Spec_FPACC_IMP UL(0b0001)
#define ID_AA64AFR0_EL1_IMPDEF0_SHIFT 0
#define LORSA_EL1_SA_WIDTH 36
#define PF_LOCAL_THROTTLE 0x00100000
#define PMSCR_EL2_PCT_SHIFT 6
#define SYS_DCZID_EL0_Op1 3
#define this_cpu_generic_xchg(pcp,nval) ({ typeof(pcp) __ret; unsigned long __flags; raw_local_irq_save(__flags); __ret = raw_cpu_generic_xchg(pcp, nval); raw_local_irq_restore(__flags); __ret; })
#define TCR2_EL2_SKL1 GENMASK(9, 8)
#define readq_poll_timeout_atomic(addr,val,cond,delay_us,timeout_us) readx_poll_timeout_atomic(readq, addr, val, cond, delay_us, timeout_us)
#define PSR_Z_BIT 0x40000000
#define ID_AA64SMFR0_EL1_F64F64_NI UL(0b0)
#define sig_specific_sicodes(sig) siginmask(sig, SIG_SPECIFIC_SICODES_MASK)
#define ID_ISAR5_EL1_RDM_NI UL(0b0000)
#define ACPI_DEVICE_CLASS(_cls,_msk) .cls = (_cls), .cls_msk = (_msk),
#define HFGITR_EL2_ATS1E1WP_SHIFT 17
#define ID_AA64SMFR0_EL1_F32F32_IMP UL(0b1)
#define TASK_RUNNING 0x00000000
#define HDFGRTR_EL2_PMSIRR_EL1_MASK GENMASK(31, 31)
#define ID_MMFR0_EL1_FCSE_SHIFT 24
#define IRQF_TRIGGER_MASK (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)
#define STATX_NLINK 0x00000004U
#define SYS_PIR_EL2_CRm 2
#define TPIDR_EL1_UNKN (UL(0))
#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define MDIO_AN_EEE_ADV_100TX 0x0002
#define HDFGRTR_EL2_MDSCR_EL1_SHIFT 4
#define CONFIG_CONSOLE_TRANSLATIONS 1
#define DIV_ROUND_UP_ULL(ll,d) DIV_ROUND_DOWN_ULL((unsigned long long)(ll) + (d) - 1, (d))
#define NETIF_F_HW_HSR_TAG_INS __NETIF_F(HW_HSR_TAG_INS)
#define idr_lock_irq(idr) xa_lock_irq(&(idr)->idr_rt)
#define TRBSR_EL1_WRAP_WIDTH 1
#define compat_r10_fiq regs[26]
#define PACKET_BROADCAST 1
#define CONFIG_VM_EVENT_COUNTERS 1
#define for_each_process_thread(p,t) for_each_process(p) for_each_thread(p, t)
#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
#define MDIO_AN_10GBT_STAT_LOCOK 0x2000
#define TPACKET2_HDRLEN (TPACKET_ALIGN(sizeof(struct tpacket2_hdr)) + sizeof(struct sockaddr_ll))
#define LED_COLOR_ID_ORANGE 11
#define __NR_renameat 38
#define REG_OSLAR_EL1 S2_0_C1_C0_4
#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | ESR_ELx_SYS64_ISS_OP1_MASK | ESR_ELx_SYS64_ISS_OP2_MASK | ESR_ELx_SYS64_ISS_CRN_MASK | ESR_ELx_SYS64_ISS_DIR_MASK)
#define HFGxTR_EL2_ERXSTATUS_EL1_SHIFT 44
#define FS_SYNC_FL 0x00000008
#define DQ_MOD_B 0
#define __verify_pcpu_ptr(ptr) do { const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; (void)__vpp_verify; } while (0)
#define rcutree_offline_cpu NULL
#define NETIF_F_RXCSUM __NETIF_F(RXCSUM)
#define SECCOMP_FILTER_FLAG_TSYNC (1UL << 0)
#define IRQ_NOTCONNECTED (1U << 31)
#define nodemask_parse_user(ubuf,ulen,dst) __nodemask_parse_user((ubuf), (ulen), &(dst), MAX_NUMNODES)
#define SECCOMP_NOTIFY_ADDFD_SIZE_VER0 24
#define QFMT_VFS_OLD 1
#define ID_AA64MMFR1_EL1_CMOW_MASK GENMASK(59, 56)
#define HWCAP_PACA (1 << 30)
#define ID_PFR0_EL1_State0_NI UL(0b0000)
#define SYS_ID_AA64AFR1_EL1_Op1 0
#define HWCAP_PACG (1UL << 31)
#define __HFGRTR_EL2_MASK GENMASK(49, 0)
#define ID_AA64DFR0_EL1_MTPMU_SHIFT 48
#define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
#define ANON_AND_FILE 2
#define TRBSR_EL1_TRG_MASK GENMASK(21, 21)
#define PT_TRACE_FORK PT_EVENT_FLAG(PTRACE_EVENT_FORK)
#define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
#define raw_try_cmpxchg_acquire(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg_acquire((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define __chk_user_ptr(x) (void)0
#define barrier_nospec() do { } while (0)
#define ENOLINK 67
#define HFGxTR_EL2_PAR_EL1_MASK GENMASK(27, 27)
#define ID_ISAR5_EL1_RDM_WIDTH 4
#define CONFIG_MEMFD_CREATE 1
#define raw_sync_try_cmpxchg(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_sync_cmpxchg((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define PFA_SPEC_SSB_FORCE_DISABLE 4
#define mutex_lock_nest_lock(lock,nest_lock) do { typecheck(struct lockdep_map *, &(nest_lock)->dep_map); _mutex_lock_nest_lock(lock, &(nest_lock)->dep_map); } while (0)
#define rootfs_initcall(fn) __define_initcall(fn, rootfs)
#define SIOCSIFMTU 0x8922
#define pud_none(pud) (!pud_val(pud))
#define MM_CP_TRY_CHANGE_WRITABLE (1UL << 0)
#define default_message_loglevel (console_printk[1])
#define PF_LLC AF_LLC
#define F_SEAL_SEAL 0x0001
#define ID_AA64MMFR3_EL1_S1PIE_SHIFT 8
#define ID_PFR1_EL1_GIC_WIDTH 4
#define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
#define PA_HVERSION_ANY_ID 0xffff
#define do_csum do_csum
#define ARCH_HAS_DMA_MINALIGN 
#define DEFINE_PER_CPU(type,name) DEFINE_PER_CPU_SECTION(type, name, "")
#define __NR_tee 77
#define __NR_ioctl 29
#define readw_poll_timeout(addr,val,cond,delay_us,timeout_us) readx_poll_timeout(readw, addr, val, cond, delay_us, timeout_us)
#define SO_BROADCAST 6
#define __SVE_NUM_ZREGS 32
#define HWCAP2_MTE (1 << 18)
#define MII_RERRCOUNTER 0x15
#define JOBCTL_STOP_DEQUEUED_BIT 16
#define flowi_l3mdev u.__fl_common.flowic_l3mdev
#define ID_AA64ISAR1_EL1_XS_IMP UL(0b0001)
#define SYS_TCR2_EL1_Op1 0
#define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0)
#define HFGITR_EL2_ATS1E1RP_SHIFT 16
#define REG_MVFR2_EL1 S3_0_C0_C3_2
#define SYSCTL_INT_MAX ((void *)&sysctl_vals[9])
#define CONFIG_RUSTC_VERSION_TEXT "rustc 1.75.0 (82e1608df 2023-12-21)"
#define BUG_BRK_IMM 0x800
#define ID_AA64ISAR1_EL1_SPECRES GENMASK(43, 40)
#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
#define ID_AA64MMFR0_EL1_PARANGE_36 UL(0b0001)
#define __wait_event_hrtimeout(wq_head,condition,timeout,state) ({ int __ret = 0; struct hrtimer_sleeper __t; hrtimer_init_sleeper_on_stack(&__t, CLOCK_MONOTONIC, HRTIMER_MODE_REL); if ((timeout) != KTIME_MAX) { hrtimer_set_expires_range_ns(&__t.timer, timeout, current->timer_slack_ns); hrtimer_sleeper_start_expires(&__t, HRTIMER_MODE_REL); } __ret = ___wait_event(wq_head, condition, state, 0, 0, if (!__t.task) { __ret = -ETIME; break; } schedule()); hrtimer_cancel(&__t.timer); destroy_hrtimer_on_stack(&__t.timer); __ret; })
#define MODULE_PARM_DESC(_parm,desc) __MODULE_INFO(parm, _parm, #_parm ":" desc)
#define HID_BUS_ANY 0xffff
#define MDIO_CTRL1 MII_BMCR
#define _DPRINTK_FLAGS_INCL_SOURCENAME (1<<5)
#define FAR_EL2_RES0 (UL(0))
#define SIGIO 29
#define HFGxTR_EL2_AMAIR_EL1_MASK GENMASK(3, 3)
#define ID_DFR0_EL1_MMapDbg_WIDTH 4
#define PSR_AA32_MODE_ABT 0x00000017
#define MDIO_CTRL2 7
#define DQF_GETINFO_MASK (DQF_ROOT_SQUASH | DQF_SYS_FILE)
#define generic_smp_call_function_interrupt generic_smp_call_function_single_interrupt
#define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
#define ID_PFR2_EL1_RAS_frac_NI UL(0b0000)
#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
#define SCHED_FIXEDPOINT_SCALE (1L << SCHED_FIXEDPOINT_SHIFT)
#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
#define net_get_random_once(buf,nbytes) get_random_once((buf), (nbytes))
#define ID_ISAR6_EL1_SPECRES_SIGNED false
#define HDFGRTR_EL2_TRBPTR_EL1_WIDTH 1
#define PR_SYS_DISPATCH_ON 1
#define ID_AA64ZFR0_EL1_AES_MASK GENMASK(7, 4)
#define PMSCR_EL2_TS_MASK GENMASK(5, 5)
#define MAY_WRITE 0x00000002
#define __acquires(x) 
#define PMBLIMITR_EL1_LIMIT_SHIFT 12
#define pud_present(pud) pte_present(pud_pte(pud))
#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
#define ID_AA64ISAR0_EL1_TS_SIGNED false
#define TCR2_EL1x_UNKN (UL(0))
#define FS_XFLAG_COWEXTSIZE 0x00010000
#define ID_AA64PFR0_EL1_SVE_IMP UL(0b0001)
#define lockdep_repin_lock(l,c) lock_repin_lock(&(l)->dep_map, (c))
#define CPUCLOCK_VIRT 1
#define MT_FLAGS_ALLOC_RANGE 0x01
#define ID_PFR1_EL1_ProgMod_SHIFT 0
#define postcore_initcall_sync(fn) __define_initcall(fn, 2s)
#define __PGTBL_PTE_MODIFIED 4
#define QC_RT_SPC_WARNS (1<<11)
#define ADVERTISED_56000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseCR4_Full)
#define module_param_named_unsafe(name,value,type,perm) param_check_ ##type(name, &(value)); module_param_cb_unsafe(name, &param_ops_ ##type, &value, perm); __MODULE_PARM_TYPE(name, #type)
#define pm_generic_prepare NULL
#define ID_AA64MMFR3_EL1_ANERR GENMASK(47, 44)
#define no_free_ptr(p) ((typeof(p)) __must_check_fn(__get_and_null_ptr(p)))
#define EISA_DEVICE_MODALIAS_FMT "eisa:s%s"
#define AT_RECURSIVE 0x8000
#define DACR32_EL2_D6_WIDTH 2
#define EM_RISCV 243
#define HDFGWTR_EL2_DBGBCRn_EL1_SHIFT 0
#define ID_MMFR5_EL1_ETS_IMP UL(0b0001)
#define SI_MESGQ -3
#define TCR2_EL1x_D128_SHIFT 5
#define local_softirq_pending() (__this_cpu_read(local_softirq_pending_ref))
#define HCR_NV (UL(1) << 42)
#define __request_mem_region(start,n,name,excl) __request_region(&iomem_resource, (start), (n), (name), excl)
#define readw_relaxed_poll_timeout_atomic(addr,val,cond,delay_us,timeout_us) readx_poll_timeout_atomic(readw_relaxed, addr, val, cond, delay_us, timeout_us)
#define FLOWI_FLAG_ANYSRC 0x01
#define HFGITR_EL2_nGCSPUSHM_EL1_SHIFT 57
#define SMPRIMAP_EL2_P4_SHIFT 16
#define ID_AA64ZFR0_EL1_UNKN (UL(0))
#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
#define ID_ISAR4_EL1_UNKN (UL(0))
#define SCTLR_EL1_WXN_SHIFT 19
#define ID_ISAR4_EL1_SWP_frac_WIDTH 4
#define pr_err_once(fmt,...) printk_once(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
#define SCTLR_EL1_EnTP2_MASK GENMASK(60, 60)
#define IOCB_SYNC (__force int) RWF_SYNC
#define ID_AA64ISAR2_EL1_GPA3_WIDTH 4
#define SVE_SET_VL(arg) sve_set_current_vl(arg)
#define ETHTOOL_SFECPARAM 0x00000051
#define BUGFLAG_WARNING (1 << 0)
#define HPAGE_MASK (~(HPAGE_SIZE - 1))
#define PIRx_ELx_Perm6_SHIFT 24
#define ID_ISAR5_EL1_CRC32_IMP UL(0b0001)
#define DECLARE_PER_CPU_SHARED_ALIGNED(type,name) DECLARE_PER_CPU_SECTION(type, name, PER_CPU_SHARED_ALIGNED_SECTION) ____cacheline_aligned_in_smp
#define MMIO_UPPER_LIMIT (IO_SPACE_LIMIT - PIO_INDIRECT_SIZE)
#define OSQ_UNLOCKED_VAL (0)
#define ETHTOOL_PERQUEUE 0x0000004b
#define __naked __attribute__((__naked__)) notrace
#define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
#define SMPRIMAP_EL2_P2_MASK GENMASK(11, 8)
#define TRAMP_VALIAS (__fix_to_virt(FIX_ENTRY_TRAMP_TEXT1))
#define HFGxTR_EL2_MIDR_EL1_WIDTH 1
#define HWCAP_ASIMDFHM (1 << 23)
#define CONFIG_ROCKCHIP_ERRATUM_3588001 1
#define CONFIG_UNIX 1
#define IOCB_NOWAIT (__force int) RWF_NOWAIT
#define CONFIG_NET_VENDOR_SEEQ 1
#define ID_AA64PFR0_EL1_GIC_IMP UL(0b0001)
#define _LINUX_ARCH_TOPOLOGY_H_ 
#define ftrace_set_notrace(ops,buf,len,reset) ({ -ENODEV; })
#define HDFGRTR_EL2_TRCCNTVRn_SHIFT 37
#define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
#define SYS_ID_AA64DFR1_EL1_CRn 0
#define NETIF_F_HW_L2FW_DOFFLOAD __NETIF_F(HW_L2FW_DOFFLOAD)
#define SYS_ID_AA64ZFR0_EL1_Op0 3
#define SYS_ID_AA64ZFR0_EL1_Op1 0
#define ID_MMFR4_EL1_EVT_NI UL(0b0000)
#define bytemask_from_count(cnt) (~(~0ul << (cnt)*8))
#define HDFGWTR_EL2_DBGWCRn_EL1_SHIFT 2
#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
#define WORK_OFFQ_POOL_NONE ((1ul << WORK_OFFQ_POOL_BITS) - 1)
#define rmb() do { kcsan_rmb(); __rmb(); } while (0)
#define arch_atomic_fetch_sub arch_atomic_fetch_sub
#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
#define SYS_SCTLR_EL1_Op0 3
#define SYS_SCTLR_EL1_Op1 0
#define SYS_SCTLR_EL1_Op2 0
#define NETLINK_FIREWALL 3
#define netdev_dbg(__dev,format,args...) ({ if (0) netdev_printk(KERN_DEBUG, __dev, format, ##args); })
#define CCW_DEVICE_ID_MATCH_DEVICE_MODEL 0x08
#define CONFIG_PHYS_ADDR_T_64BIT 1
#define __kernel 
#define ICH_LR_PRIORITY_SHIFT 48
#define __nosavedata __section(".data..nosave")
#define SYS_CCSIDR2_EL1_Op0 3
#define SYS_CCSIDR2_EL1_Op1 1
#define SYS_CCSIDR2_EL1_Op2 2
#define CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE 1
#define SO_TYPE 3
#define HFGITR_EL2_TLBIRVAAE1IS GENMASK(35, 35)
#define __DECLARE_FLEX_ARRAY(TYPE,NAME) struct { struct { } __empty_ ## NAME; TYPE NAME[]; }
#define SOL_DECNET 261
#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | ESR_ELx_WFx_ISS_WFI)
#define MOD_MICRO ADJ_MICRO
#define cmpxchg128_acquire(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg128_acquire(__ai_ptr, __VA_ARGS__); })
#define PHY_ALWAYS_CALL_SUSPEND 0x00000008
#define HFGxTR_EL2_ERXPFGCTL_EL1_SHIFT 47
#define ID_AA64ISAR1_EL1_XS_NI UL(0b0000)
#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
#define CONFIG_CONTIG_ALLOC 1
#define SCM_RIGHTS 0x01
#define compiletime_assert_atomic_type(t) compiletime_assert(__native_word(t), "Need native word sized stores/loads for atomicity.")
#define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1
#define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
#define HFGxTR_EL2_TPIDRRO_EL0_SHIFT 34
#define __LINUX_SPINLOCK_API_SMP_H 
#define CONFIG_PER_VMA_LOCK 1
#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
#define OSDTRRX_EL1_DTRRX_WIDTH 32
#define INIT_CSD(_csd,_func,_info) do { *(_csd) = CSD_INIT((_func), (_info)); } while (0)
#define __smp_mb__after_atomic() __smp_mb()
#define _ASM_EXTABLE_KACCESS_ERR(insn,fixup,err) _ASM_EXTABLE_KACCESS_ERR_ZERO(insn, fixup, err, wzr)
#define ID_AA64ISAR0_EL1_RDM_SIGNED false
#define CONFIG_ARCH_SUPPORTS_KEXEC_FILE 1
#define SYS_ID_AA64MMFR1_EL1_Op0 3
#define SYS_ID_AA64MMFR1_EL1_Op1 0
#define ID_AA64MMFR1_EL1_AFP_WIDTH 4
#define __pcpu_size_call_return2(stem,variable,...) ({ typeof(variable) pscr2_ret__; __verify_pcpu_ptr(&(variable)); switch(sizeof(variable)) { case 1: pscr2_ret__ = stem ##1(variable, __VA_ARGS__); break; case 2: pscr2_ret__ = stem ##2(variable, __VA_ARGS__); break; case 4: pscr2_ret__ = stem ##4(variable, __VA_ARGS__); break; case 8: pscr2_ret__ = stem ##8(variable, __VA_ARGS__); break; default: __bad_size_call_parameter(); break; } pscr2_ret__; })
#define KUNIT_ASSERT_STREQ(test,left,right) KUNIT_ASSERT_STREQ_MSG(test, left, right, NULL)
#define LOCK_EX 2
#define ID_AA64MMFR1_EL1_HCX_MASK GENMASK(43, 40)
#define __NR_mlockall 230
#define CONFIG_GDB_SCRIPTS 1
#define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features)
#define HFGxTR_EL2_nTPIDR2_EL0_MASK GENMASK(55, 55)
#define __NR_getresuid 148
#define ID_AA64PFR0_EL1_RME GENMASK(55, 52)
#define umax(x,y) __careful_cmp(max, (x) + 0u + 0ul + 0ull, (y) + 0u + 0ul + 0ull)
#define NETIF_F_HW_VLAN_STAG_TX __NETIF_F(HW_VLAN_STAG_TX)
#define outsl_p outsl_p
#define CONFIG_WLAN_VENDOR_MEDIATEK 1
#define SET_PSTATE(x,r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
#define CSSELR_EL1_InD_MASK GENMASK(0, 0)
#define MODULE_VERSION(_version) MODULE_INFO(version, _version); static struct module_version_attribute __modver_attr __used __section("__modver") __aligned(__alignof__(struct module_version_attribute)) = { .mattr = { .attr = { .name = "version", .mode = S_IRUGO, }, .show = __modver_version_show, }, .module_name = KBUILD_MODNAME, .version = _version, }
#define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
#define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
#define device_initcall(fn) __define_initcall(fn, 6)
#define HUGETLB_FLAG_ENCODE_16GB (34U << HUGETLB_FLAG_ENCODE_SHIFT)
#define SYS_GMID_EL1_CRn 0
#define printk_cpu_sync_get_irqsave(flags) for (;;) { local_irq_save(flags); if (__printk_cpu_sync_try_get()) break; local_irq_restore(flags); __printk_cpu_sync_wait(); }
#define ID_AA64PFR0_EL1_FP_WIDTH 4
#define iowrite16_rep iowrite16_rep
#define readw_relaxed readw_relaxed
#define memset_startat(obj,v,member) ({ u8 *__ptr = (u8 *)(obj); typeof(v) __val = (v); memset(__ptr + offsetof(typeof(*(obj)), member), __val, sizeof(*(obj)) - offsetof(typeof(*(obj)), member)); })
#define MIN_NICE -20
#define MAX_INPUT 255
#define HDFGWTR_EL2_MDSCR_EL1_SHIFT 4
#define VMEMMAP_START (-(UL(1) << (VA_BITS - VMEMMAP_SHIFT)))
#define ENETDOWN 100
#define ESTALE 116
#define MM_CP_UFFD_WP_RESOLVE (1UL << 3)
#define HDFGRTR_EL2_PMOVS GENMASK(18, 18)
#define ETHTOOL_GUFO 0x00000021
#define HDFGRTR_EL2_TRCAUXCTLR GENMASK(35, 35)
#define SOCK_SUPPORT_ZC 5
#define randomized_struct_fields_start 
#define PMSIDR_EL1_FORMAT GENMASK(23, 20)
#define SEGV_ACCADI 5
#define __no_kmsan_checks 
#define INIT_THREAD_INFO(tsk) { .flags = _TIF_FOREIGN_FPSTATE, .preempt_count = INIT_PREEMPT_COUNT, INIT_SCS }
#define __BUGVERBOSE_LOCATION(file,line) .pushsection .rodata.str,"aMS",@progbits,1; 14472: .string file; .popsection; .long 14472b - .; .short line;
#define SCTLR_EL1_TWEDEL_SHIFT 46
#define ATTR_KILL_PRIV (1 << 14)
#define SECTION_IS_EARLY BIT(SECTION_IS_EARLY_BIT)
#define TCR2_EL1x_E0POE_WIDTH 1
#define EX_DATA_REG_DATA GENMASK(4, 0)
#define PMSIDR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 25) | GENMASK_ULL(7, 7))
#define PMSIDR_EL1_RES1 (UL(0))
#define IOP_NOFOLLOW 0x0004
#define __HFGITR_EL2_nMASK GENMASK(56, 55)
#define ID_AA64MMFR3_EL1_Spec_FPACC_MASK GENMASK(63, 60)
#define SB_INLINECRYPT BIT(17)
#define MVFR0_EL1_FPDP_VFPv2 UL(0b0001)
#define MVFR0_EL1_FPDP_VFPv3 UL(0b0010)
#define VM_MAYREAD 0x00000010
#define MVFR1_EL1_FPFtZ_MASK GENMASK(3, 0)
#define EIOCBQUEUED 529
#define SOCK_TXREHASH_ENABLED 1
#define field_max(field) ((typeof(field))field_mask(field))
#define _UAPI__LINUX_UIO_H 
#define TCR2_EL2_DisCH0_SHIFT 14
#define EM_SET_ACTIVE_POWER_CB(em_cb,cb) do { } while (0)
#define __wait_event_timeout(wq_head,condition,timeout) ___wait_event(wq_head, ___wait_cond_timeout(condition), TASK_UNINTERRUPTIBLE, 0, timeout, __ret = schedule_timeout(__ret))
#define dev_alert_ratelimited(dev,fmt,...) dev_level_ratelimited(dev_alert, dev, fmt, ##__VA_ARGS__)
#define SMIDR_EL1_REVISION_MASK GENMASK(23, 16)
#define HDFGRTR_EL2_TRCIMSPECn GENMASK(41, 41)
#define SYS_ID_ISAR2_EL1_Op0 3
#define SYS_ID_ISAR2_EL1_Op1 0
#define SYS_ID_ISAR2_EL1_Op2 2
#define KUNIT_ASSERT_NOT_NULL(test,ptr) KUNIT_ASSERT_NOT_NULL_MSG(test, ptr, NULL)
#define VM_READ 0x00000001
#define VM_STACK_INCOMPLETE_SETUP (VM_RAND_READ | VM_SEQ_READ | VM_STACK_EARLY)
#define EXPORT_NS_DEV_PM_OPS(name,ns) _EXPORT_DEV_PM_OPS(name, "", #ns)
#define _LINUX_IO_H 
#define FAR_EL2_RES1 (UL(0))
#define PR_FPEMU_NOPRINT 1
#define HCRX_EL2_EnASR_MASK GENMASK(2, 2)
#define count_vm_vma_lock_event(x) do {} while (0)
#define MDCCINT_EL1_RES0 (UL(0) | GENMASK_ULL(63, 31) | GENMASK_ULL(28, 0))
#define SOCK_RCVBUF_LOCK 2
#define ____define_initcall(fn,__stub,__name,__sec) __define_initcall_stub(__stub, fn) asm(".section	\"" __sec "\", \"a\"		\n" __stringify(__name) ":			\n" ".long	" __stringify(__stub) " - .	\n" ".previous					\n"); static_assert(__same_type(initcall_t, &fn));
#define FMODE_NONOTIFY ((__force fmode_t)0x4000000)
#define R_AARCH64_PREL32 261
#define __NR_wait4 260
#define LED_FUNCTION_ACTIVITY "activity"
#define barrier_before_unreachable() asm volatile("")
#define LPA_PAUSE_ASYM 0x0800
#define ARM64_HAS_SB 42
#define KUNIT_BINARY_STR_ASSERTION(test,assert_type,left,op,right,fmt,...) do { const char *__left = (left); const char *__right = (right); static const struct kunit_binary_assert_text __text = { .operation = #op, .left_text = #left, .right_text = #right, }; if (likely(strcmp(__left, __right) op 0)) break; _KUNIT_FAILED(test, assert_type, kunit_binary_str_assert, kunit_binary_str_assert_format, KUNIT_INIT_ASSERT(.text = &__text, .left_value = __left, .right_value = __right), fmt, ##__VA_ARGS__); } while (0)
#define HFGITR_EL2_TLBIRVAAE1OS GENMASK(25, 25)
#define TCR2_EL1x_PIE GENMASK(1, 1)
#define __diag_GCC_8(s) __diag(s)
#define ETH_P_CAIF 0x00F7
#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
#define SMPRIMAP_EL2_P13_MASK GENMASK(55, 52)
#define raw_read_seqcount(s) ({ unsigned __seq = seqprop_sequence(s); smp_rmb(); kcsan_atomic_next(KCSAN_SEQLOCK_REGION_MAX); __seq; })
#define IORESOURCE_DMA_TYPE_MASK (3<<0)
#define ID_AA64PFR1_EL1_SME GENMASK(27, 24)
#define arch_write_unlock(l) queued_write_unlock(l)
#define list_lru_init_key(lru,key) __list_lru_init((lru), false, (key), NULL)
#define HUGETLB_FLAG_ENCODE_16KB (14U << HUGETLB_FLAG_ENCODE_SHIFT)
#define swait_event_interruptible_timeout_exclusive(wq,condition,timeout) ({ long __ret = timeout; if (!___wait_cond_timeout(condition)) __ret = __swait_event_interruptible_timeout(wq, condition, timeout); __ret; })
#define CONFIG_CC_CAN_LINK 1
#define NLMSG_NEXT(nlh,len) ((len) -= NLMSG_ALIGN((nlh)->nlmsg_len), (struct nlmsghdr *)(((char *)(nlh)) + NLMSG_ALIGN((nlh)->nlmsg_len)))
#define ID_ISAR5_EL1_RDM_SIGNED false
#define HVC_RESET_VECTORS 2
#define idr_lock_bh(idr) xa_lock_bh(&(idr)->idr_rt)
#define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
#define PAGE_ALLOC_COSTLY_ORDER 3
#define POLLRDHUP 0x2000
#define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
#define ack_bad_irq ack_bad_irq
#define CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH 1
#define AF_BLUETOOTH 31
#define KPROJIDT_INIT(value) (kprojid_t){ value }
#define CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 1
#define ALIGN_DOWN(x,a) __ALIGN_KERNEL((x) - ((a) - 1), (a))
#define ID_AA64ISAR1_EL1_API_NI UL(0b0000)
#define EXPORT_SYMBOL_GPL(sym) _EXPORT_SYMBOL(sym, "GPL")
#define CONFIG_NET_VENDOR_SOCIONEXT 1
#define SMCR_ELx_FA64_MASK GENMASK(31, 31)
#define CONFIG_EXPORTFS 1
#define ID_AA64PFR0_EL1_EL1_AARCH32 UL(0b0010)
#define SHM_REMAP 040000
#define TCR2_EL1x_DisCH0_SHIFT 14
#define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
#define KSYM_SYMBOL_LEN (sizeof("%s+%#lx/%#lx [%s %s]") + (KSYM_NAME_LEN - 1) + 2*(BITS_PER_LONG*3/10) + (MODULE_NAME_LEN - 1) + (BUILD_ID_SIZE_MAX * 2) + 1)
#define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1))
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
#define __wait_event_interruptible_exclusive(wq,condition) ___wait_event(wq, condition, TASK_INTERRUPTIBLE, 1, 0, schedule())
#define CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE 1
#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
#define CONFIG_ARCH_USE_QUEUED_RWLOCKS 1
#define _PAGE_DEFAULT (_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
#define ID_AA64MMFR0_EL1_FGT_SHIFT 56
#define pud_young(pud) pte_young(pud_pte(pud))
#define ARM64_ALWAYS_SYSTEM 1
#define __ASM_GENERIC_SHMPARAM_H 
#define offsetof(TYPE,MEMBER) __builtin_offsetof(TYPE, MEMBER)
#define EXIT_ZOMBIE 0x00000020
#define DEFINE_IDA(name) struct ida name = IDA_INIT(name)
#define HDFGRTR_EL2_TRBIDR_EL1_MASK GENMASK(51, 51)
#define irq_affinity_online_cpu NULL
#define MDIO_USXGMII_2500FULL 0x1800
#define mp_bvec_iter_offset(bvec,iter) (__bvec_iter_bvec((bvec), (iter))->bv_offset + (iter).bi_bvec_done)
#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
#define IPV6_RECVERR 25
#define ID_MMFR2_EL1_L1HvdRng_NI UL(0b0000)
#define HFGxTR_EL2_ESR_EL1 GENMASK(16, 16)
#define TP_STATUS_AVAILABLE 0
#define ID_MMFR4_EL1_EVT_SHIFT 28
#define MVFR2_EL1_FPMisc_SHIFT 4
#define MDIO_USXGMII_5000FULL 0x1a00
#define VFS_PTR_POISON ((void *)(0xF5 + POISON_POINTER_DELTA))
#define LED_CORE_SUSPENDRESUME BIT(16)
#define rcu_tasks_classic_qs(t,preempt) do { } while (0)
#define HFGxTR_EL2_CLIDR_EL1 GENMASK(10, 10)
#define __ASM_ESR_H 
#define mdio_module_driver(_mdio_driver) static int __init mdio_module_init(void) { return mdio_driver_register(&_mdio_driver); } module_init(mdio_module_init); static void __exit mdio_module_exit(void) { mdio_driver_unregister(&_mdio_driver); } module_exit(mdio_module_exit)
#define HDFGWTR_EL2_TRCSSCSRn_MASK GENMASK(46, 46)
#define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
#define __LINUX_PAGE_TABLE_CHECK_H 
#define ETHTOOL_GRXFH 0x00000029
#define umin(x,y) __careful_cmp(min, (x) + 0u + 0ul + 0ull, (y) + 0u + 0ul + 0ull)
#define SYS_ZCR_EL12_CRm 2
#define SYS_ZCR_EL12_CRn 1
#define IEEE1394_MATCH_SPECIFIER_ID 0x0004
#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
#define PARITY_CRC16_PR1_CCITT 5
#define ID_ISAR2_EL1_Mult_MLA UL(0b0001)
#define ID_AA64DFR0_EL1_DoubleLock_SHIFT 36
#define PMBSR_EL1_EC_SHIFT 26
#define NETIF_F_IP_CSUM __NETIF_F(IP_CSUM)
#define IORESOURCE_IRQ_LOWLEVEL (1<<3)
#define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x))
#define ZA_PT_VL_ONEXEC ((1 << 18) >> 16)
#define LOCK_NB 4
#define PTRACE_EVENT_SECCOMP 7
#define ID_ISAR6_EL1_JSCVT_SHIFT 0
#define MDIO_STAT2_DEVPRST 0xc000
#define arch_kasan_get_tag(addr) __tag_get(addr)
#define __NR_mbind 235
#define MAIR_ATTR_MASK UL(0xff)
#define _ASM_GENERIC_TOPOLOGY_H 
#define ENDIAN_SET_EL1 0
#define ENDIAN_SET_EL2 0
#define ATTRIBUTE_GROUPS(_name) static const struct attribute_group _name ##_group = { .attrs = _name ##_attrs, }; __ATTRIBUTE_GROUPS(_name)
#define TCR2_EL2_SKL0_WIDTH 2
#define PF_NPROC_EXCEEDED 0x00001000
#define __NR_io_submit 2
#define ID_AA64MMFR0_EL1_PARANGE_42 UL(0b0011)
#define HDFGRTR_EL2_PMSCR_EL1_SHIFT 26
#define MVFR0_EL1_FPRound GENMASK(31, 28)
#define pm_generic_restore NULL
#define _LINUX_CAPABILITY_U32S_2 2
#define ID_ISAR5_EL1_AES_IMP UL(0b0001)
#define ID_AA64MMFR0_EL1_TGRAN64_2_NI UL(0b0001)
#define pud_user(pud) pte_user(pud_pte(pud))
#define ID_MMFR4_EL1_AC2_SHIFT 4
#define __ASM_GENERIC_TIMEX_H 
#define PM_EVENT_AUTO_RESUME (PM_EVENT_AUTO | PM_EVENT_RESUME)
#define SO_DETACH_REUSEPORT_BPF 68
#define SG_CHAIN 0x01UL
#define PMBPTR_EL1_PTR GENMASK(63, 0)
#define ID_PFR1_EL1_GIC_GICv3 UL(0b0001)
#define IORESOURCE_EXT_TYPE_BITS 0x01000000
#define CONFIG_FAIR_GROUP_SCHED 1
#define KUNIT_BASE_BINARY_ASSERTION(test,assert_class,format_func,assert_type,left,op,right,fmt,...) do { const typeof(left) __left = (left); const typeof(right) __right = (right); static const struct kunit_binary_assert_text __text = { .operation = #op, .left_text = #left, .right_text = #right, }; if (likely(__left op __right)) break; _KUNIT_FAILED(test, assert_type, assert_class, format_func, KUNIT_INIT_ASSERT(.text = &__text, .left_value = __left, .right_value = __right), fmt, ##__VA_ARGS__); } while (0)
#define ID_MMFR1_EL1_L1HvdSW_WIDTH 4
#define ID_MMFR1_EL1_L1Hvd_CLEAN_AND_INVALIDATE UL(0b0011)
#define CONFIG_RCU_NEED_SEGCBLIST 1
#define get_current_cred() (get_cred(current_cred()))
#define ___constant_swab16(x) ((__u16)( (((__u16)(x) & (__u16)0x00ffU) << 8) | (((__u16)(x) & (__u16)0xff00U) >> 8)))
#define COMPAT_PT_TEXT_ADDR 0x10000
#define LONG_MAX ((long)(~0UL >> 1))
#define SHMLBA PAGE_SIZE
#define IPV6_RECVHOPOPTS 53
#define ADVERTISED_40000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseCR4_Full)
#define HFGITR_EL2_TLBIVAE1IS_SHIFT 29
#define BCMA_ANY_MANUF 0xFFFF
#define TCR2_EL1x_POE GENMASK(3, 3)
#define HFGITR_EL2_ICIALLU GENMASK(1, 1)
#define alloc_bucket_spinlocks(locks,lock_mask,max_size,cpu_mult,gfp) ({ static struct lock_class_key key; int ret; ret = __alloc_bucket_spinlocks(locks, lock_mask, max_size, cpu_mult, gfp, #locks, &key); ret; })
#define __put_user(x,ptr) ({ int __pu_err = 0; __put_user_error((x), (ptr), __pu_err); __pu_err; })
#define TRBLIMITR_EL1_TM_MASK GENMASK(4, 3)
#define PACKET_RESERVE 12
#define HWCAP2_SVEBF16 (1 << 12)
#define CONFIG_TIMERFD 1
#define SYSCTL_ZERO ((void *)&sysctl_vals[0])
#define ID_MMFR2_EL1_WFIStall_WIDTH 4
#define __HFGITR_EL2_MASK GENMASK(54, 0)
#define PSR_DIT_BIT 0x01000000
#define __kprobes 
#define VM_WARN_ON_ONCE_MM(cond,mm) BUILD_BUG_ON_INVALID(cond)
#define force_read_lock_recursive 0
#define __VDSO_TIME32_H 
#define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
#define DEFINE_IDR(name) struct idr name = IDR_INIT(name)
#define MEMFD_NOEXEC_SCOPE_EXEC 0
#define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
#define module_param_named(name,value,type,perm) param_check_ ##type(name, &(value)); module_param_cb(name, &param_ops_ ##type, &value, perm); __MODULE_PARM_TYPE(name, #type)
#define HUGETLB_FLAG_ENCODE_1GB (30U << HUGETLB_FLAG_ENCODE_SHIFT)
#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
#define trace_preempt_off(a0,a1) do { } while (0)
#define ID_MMFR0_EL1_PMSA_SHIFT 4
#define IORESOURCE_SYSRAM 0x01000000
#define AT_CRn 7
#define DCACHE_OP_COMPARE 0x00000002
#define ETHTOOL_GMODULEEEPROM 0x00000043
#define FLOW_DIS_CFM_MDL_MAX 7
#define PMSG_HIBERNATE ((struct pm_message){ .event = PM_EVENT_HIBERNATE, })
#define CONFIG_CGROUP_FREEZER 1
#define devm_release_mem_region(dev,start,n) __devm_release_region(dev, &iomem_resource, (start), (n))
#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
#define __pure __attribute__((__pure__))
#define net_emerg_ratelimited(fmt,...) net_ratelimited_function(pr_emerg, fmt, ##__VA_ARGS__)
#define HFGxTR_EL2_nPOR_EL1_WIDTH 1
#define ID_DFR0_EL1_MMapDbg GENMASK(11, 8)
#define HFGxTR_EL2_LORN_EL1_SHIFT 22
#define ETHTOOL_FEC_NONE (1 << ETHTOOL_FEC_NONE_BIT)
#define PAGE_MAPPING_DAX_SHARED ((void *)0x1)
#define dev_level_once(dev_level,dev,fmt,...) do { static bool __print_once __read_mostly; if (!__print_once) { __print_once = true; dev_level(dev, fmt, ##__VA_ARGS__); } } while (0)
#define INIT_CPU_TIMERS(s) .posix_cputimers = { .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), },
#define CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG 1
#define CONFIG_SOCK_CGROUP_DATA 1
#define SYS_ID_ISAR1_EL1_CRm 2
#define CONFIG_NET_VENDOR_3COM 1
#define GRND_INSECURE 0x0004
#define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED)
#define __io_bw() dma_wmb()
#define list_for_each_safe(pos,n,head) for (pos = (head)->next, n = pos->next; !list_is_head(pos, (head)); pos = n, n = pos->next)
#define ID_AA64ISAR2_EL1_CSSC GENMASK(55, 52)
#define REG_ID_ISAR5_EL1 S3_0_C0_C2_5
#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)
#define MDCR_EL2_E2PB_SHIFT (UL(12))
#define VMEMMAP_SIZE ((_PAGE_END(VA_BITS_MIN) - PAGE_OFFSET) >> VMEMMAP_SHIFT)
#define ID_PFR1_EL1_Security_EL3 UL(0b0001)
#define LOCK_RW 192
#define _LINUX_ETHTOOL_H 
#define DACR32_EL2_D10 GENMASK(21, 20)
#define DACR32_EL2_D11 GENMASK(23, 22)
#define DACR32_EL2_D12 GENMASK(25, 24)
#define DACR32_EL2_D13 GENMASK(27, 26)
#define DACR32_EL2_D14 GENMASK(29, 28)
#define DACR32_EL2_D15 GENMASK(31, 30)
#define IPV6_RECVERR_RFC4884 31
#define ID_MMFR4_EL1_CCIDX_IMP UL(0b0001)
#define get_kernel_nofault(val,ptr) ({ const typeof(val) *__gk_ptr = (ptr); copy_from_kernel_nofault(&(val), __gk_ptr, sizeof(val));})
#define SCTLR_EL1_EE_MASK GENMASK(25, 25)
#define ICC_NMIAR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 24))
#define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
#define ID_AA64MMFR3_EL1_D128_MASK GENMASK(35, 32)
#define HFGITR_EL2_TLBIVAE1 GENMASK(43, 43)
#define HFGITR_EL2_TLBIVALE1IS_MASK GENMASK(32, 32)
#define MDIO_EEE_10GT 0x0008
#define __HAVE_ARCH_COPY_HIGHPAGE 
#define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
#define ID_PFR0_EL1_AMU_SIGNED false
#define KERNEL_HWCAP_WFXT __khwcap2_feature(WFXT)
#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
#define CONFIG_DRM_PANEL_BRIDGE 1
#define SO_MAX_PACING_RATE 47
#define __swait_event_interruptible_timeout(wq,condition,timeout) ___swait_event(wq, ___wait_cond_timeout(condition), TASK_INTERRUPTIBLE, timeout, __ret = schedule_timeout(__ret))
#define ETH_P_ATALK 0x809B
#define PERCPU_MODULE_RESERVE 0
#define FS_DQ_RTBTIMER (1<<8)
#define arch_atomic64_fetch_andnot_relaxed arch_atomic64_fetch_andnot_relaxed
#define ID_AA64PFR0_EL1_FP_IMP UL(0b0000)
#define __this_cpu_dec_return(pcp) __this_cpu_add_return(pcp, -1)
#define ETHTOOL_GRXFHINDIR 0x00000038
#define IPV6_DSTOPTS 59
#define PSR_MODE_EL1h 0x00000005
#define _KUNIT_ASSERT_H 
#define KCSAN_ACCESS_ATOMIC (1 << 2)
#define _ASM_GENERIC_BITOPS_BUILTIN_FLS_H_ 
#define HDFGRTR_EL2_PMBSR_EL1 GENMASK(25, 25)
#define ID_AA64DFR0_EL1_WRPs_MASK GENMASK(23, 20)
#define ID_MMFR0_EL1_FCSE_NI UL(0b0000)
#define SCTLR_EL1_EIS_MASK GENMASK(22, 22)
#define nodelist_parse(buf,dst) __nodelist_parse((buf), &(dst), MAX_NUMNODES)
#define raw_cpu_generic_cmpxchg(pcp,oval,nval) ({ typeof(pcp) __old = (oval); raw_cpu_generic_try_cmpxchg(pcp, &__old, nval); __old; })
#define EM_MIPS 8
#define ITIMER_PROF 2
#define POLLIN 0x0001
#define module_init(x) __initcall(x);
#define LOW_RES_NSEC TICK_NSEC
#define SCTLR_EL1_TCF0_NONE UL(0b00)
#define NETIF_F_LLTX __NETIF_F(LLTX)
#define ATTR_OPEN (1 << 15)
#define ETHTOOL_COALESCE_RX_MAX_FRAMES_LOW BIT(13)
#define ID_MMFR1_EL1_BPred_MASK GENMASK(31, 28)
#define ID_ISAR5_EL1_SHA2_SIGNED false
#define insb insb
#define s6_addr32 in6_u.u6_addr32
#define arch_param_cb(name,ops,arg,perm) __level_param_cb(name, ops, arg, perm, 3)
#define REG_PMSIRR_EL1 S3_0_C9_C9_3
#define ___constant_swab64(x) ((__u64)( (((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | (((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | (((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | (((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | (((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | (((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | (((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | (((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56)))
#define SET_RUNTIME_PM_OPS(suspend_fn,resume_fn,idle_fn) RUNTIME_PM_OPS(suspend_fn, resume_fn, idle_fn)
#define __this_cpu_inc_return(pcp) __this_cpu_add_return(pcp, 1)
#define KERNEL_HWCAP_DCPODP __khwcap2_feature(DCPODP)
#define ID_AA64MMFR0_EL1_TGRAN64_2_MASK GENMASK(39, 36)
#define HDFGWTR_EL2_PMINTEN_MASK GENMASK(17, 17)
#define __SWAIT_QUEUE_HEAD_INITIALIZER(name) { .lock = __RAW_SPIN_LOCK_UNLOCKED(name.lock), .task_list = LIST_HEAD_INIT((name).task_list), }
#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
#define PFN_SECTION_SHIFT (SECTION_SIZE_BITS - PAGE_SHIFT)
#define ID_AA64PFR0_EL1_DIT_MASK GENMASK(51, 48)
#define __NR_io_setup 0
#define PMSCR_EL2_E2SPE_SHIFT 1
#define PF_DUMPCORE 0x00000200
#define CONFIG_RTC_INTF_SYSFS 1
#define DECLARE_RWSEM(name) struct rw_semaphore name = __RWSEM_INITIALIZER(name)
#define ZA_PT_SIZE(vq) (ZA_PT_ZA_OFFSET + ZA_PT_ZA_SIZE(vq))
#define __PAGETABLE_PUD_FOLDED 1
#define MVFR0_EL1_FPShVec_IMP UL(0b0001)
#define DEFINE_RES_NAMED(_start,_size,_name,_flags) (struct resource) { .start = (_start), .end = (_start) + (_size) - 1, .name = (_name), .flags = (_flags), .desc = IORES_DESC_NONE, }
#define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
#define FUJITSU_CPU_PART_A64FX 0x001
#define SPEED_200000 200000
#define HFGITR_EL2_DCZVA_WIDTH 1
#define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
#define SELFMAG 4
#define V2_DEL_REWRITE QTREE_DEL_REWRITE
#define REG_CCSIDR2_EL1 S3_1_C0_C0_2
#define VMALLOC_START (MODULES_END)
#define instrument_put_user(from,ptr,size) ({ kmsan_copy_to_user(ptr, &from, sizeof(from), 0); })
#define DEFINE_MSR_S __DEFINE_ASM_GPR_NUMS "	.macro	msr_s, sreg, rt\n" __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) "	.endm\n"
#define CTR_EL0_ERG_WIDTH 4
#define arch_cmpxchg128(ptr,o,n) ({ __cmpxchg128_mb((ptr), (o), (n)); })
#define CONFIG_SERIAL_EARLYCON 1
#define dev_WARN_ONCE(dev,condition,format,arg...) WARN_ONCE(condition, "%s %s: " format, dev_driver_string(dev), dev_name(dev), ## arg)
#define kcsan_rmb() do { } while (0)
#define NL_SET_ERR_MSG_WEAK(extack,msg) do { if ((extack) && !(extack)->_msg) NL_SET_ERR_MSG((extack), msg); } while (0)
#define CPU_STUCK_IN_KERNEL (2)
#define devm_alloc_percpu(dev,type) ((typeof(type) __percpu *)__devm_alloc_percpu((dev), sizeof(type), __alignof__(type)))
#define HFGITR_EL2_ICIVAU_MASK GENMASK(2, 2)
#define ID_AA64ISAR2_EL1_PAC_frac_NI UL(0b0000)
#define PORT_DA 0x05
#define ESR_ELx_EC_SYS64 (0x18)
#define raw_cpu_try_cmpxchg(pcp,ovalp,nval) __pcpu_size_call_return2bool(raw_cpu_try_cmpxchg_, pcp, ovalp, nval)
#define while_each_thread(g,t) while ((t = next_thread(t)) != g)
#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT
#define PMBIDR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 12) | GENMASK_ULL(7, 6))
#define PMBIDR_EL1_RES1 (UL(0))
#define MDIO_PMA_EXTABLE_100BTX 0x0080
#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En | (cpus_have_final_cap(ARM64_HAS_MOPS) ? (HCRX_EL2_MSCEn | HCRX_EL2_MCE2) : 0))
#define CONFIG_BINFMT_SCRIPT 1
#define IRQF_TRIGGER_RISING 0x00000001
#define ETHTOOL_GPERMADDR 0x00000020
#define num_active_cpus() cpumask_weight(cpu_active_mask)
#define HFGxTR_EL2_nGCS_EL0_WIDTH 1
#define LONG_MIN (-LONG_MAX - 1)
#define ID_AA64ISAR0_EL1_ATOMIC_MASK GENMASK(23, 20)
#define CONFIG_DEBUG_INFO_COMPRESSED_NONE 1
#define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd)))
#define CONFIG_UIO 1
#define MIGHT_RESCHED_PREEMPT_MASK ((1U << MIGHT_RESCHED_RCU_SHIFT) - 1)
#define RCU_NEXT_READY_TAIL 2
#define CTL_MAXNAME 10
#define HFGxTR_EL2_LORSA_EL1_WIDTH 1
#define IPV6_PRIORITY_FILLER 0x0100
#define CNTPOFF_EL2_RES0 (UL(0))
#define CNTPOFF_EL2_RES1 (UL(0))
#define ID_ISAR2_EL1_Mult_WIDTH 4
#define kunit_mark_skipped(test_or_suite,fmt,...) do { WRITE_ONCE((test_or_suite)->status, KUNIT_SKIPPED); scnprintf((test_or_suite)->status_comment, KUNIT_STATUS_COMMENT_SIZE, fmt, ##__VA_ARGS__); } while (0)
#define CONFIG_ARM64_PAGE_SHIFT 12
#define time_after_eq(a,b) (typecheck(unsigned long, a) && typecheck(unsigned long, b) && ((long)((a) - (b)) >= 0))
#define pm_generic_restore_early NULL
#define SYSFS_PREALLOC 010000
#define PR_SET_TAGGED_ADDR_CTRL 55
#define _LINUX_STAT_H 
#define ID_ISAR4_EL1_SynchPrim_frac_WIDTH 4
#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4
#define SYS_ID_MMFR3_EL1_Op0 3
#define HFGxTR_EL2_CSSELR_EL1_SHIFT 13
#define PMSIDR_EL1_FnE GENMASK(6, 6)
#define VM_DATA_FLAGS_TSK_EXEC (VM_READ | VM_WRITE | TASK_EXEC | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#define SME_GET_VL() sme_get_current_vl()
#define SYS_ID_AA64MMFR3_EL1_CRm 7
#define SYS_ID_AA64MMFR3_EL1_CRn 0
#define PTE_MAYBE_GP (system_supports_bti_kernel() ? PTE_GP : 0)
#define ID_AA64PFR0_EL1_EL3_NI UL(0b0000)
#define HCRX_EL2_EnIDCP128_MASK GENMASK(21, 21)
#define TRBMAR_EL1_SH GENMASK(9, 8)
#define NMI_BITS 4
#define EXDEV 18
#define randomized_struct_fields_end 
#define PAGE_FRAG_CACHE_MAX_ORDER get_order(PAGE_FRAG_CACHE_MAX_SIZE)
#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
#define __FPE_INVDEC 13
#define IORESOURCE_SHADOWABLE 0x00020000
#define MVFR0_EL1_FPShVec_MASK GENMASK(27, 24)
#define device_lock_reset_class(dev) do { struct device *__d __maybe_unused = dev; lock_set_novalidate_class(&__d->mutex.dep_map, "&dev->mutex", _THIS_IP_); } while (0)
#define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == PUD_TYPE_TABLE)
#define struct_group_attr(NAME,ATTRS,MEMBERS...) __struct_group( , NAME, ATTRS, MEMBERS)
#define plist_first_entry(head,type,member) container_of(plist_first(head), type, member)
#define PMSIDR_EL1_FE_MASK GENMASK(0, 0)
#define ID_AA64SMFR0_EL1_I16I32_MASK GENMASK(47, 44)
#define __NR_getdents64 61
#define nodes_remap(dst,src,old,new) __nodes_remap(&(dst), &(src), &(old), &(new), MAX_NUMNODES)
#define __NR_getpeername 205
#define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
#define ETH_P_IRDA 0x0017
#define MDCR_EL2_E2TB_SHIFT (UL(24))
#define SYS_CPACR_EL12_CRm 0
#define __SVE_FFR_SIZE(vq) __SVE_PREG_SIZE(vq)
#define current_euid() (current_cred_xxx(euid))
#define KUNIT_ASSERT_TRUE(test,condition) KUNIT_ASSERT_TRUE_MSG(test, condition, NULL)
#define PR_SET_PTRACER 0x59616d61
#define HWCAP_DCPOP (1 << 16)
#define IS_WHITEOUT(inode) (S_ISCHR(inode->i_mode) && (inode)->i_rdev == WHITEOUT_DEV)
#define __ASM_GENERIC_MMIOWB_H 
#define xa_lock_irqsave(xa,flags) spin_lock_irqsave(&(xa)->xa_lock, flags)
#define CLIDR_EL1_Ctype7_SHIFT 18
#define N_INLINE_POLL_ENTRIES (WQUEUES_STACK_ALLOC / sizeof(struct poll_table_entry))
#define ZA_PT_ZAV_OFFSET(vq,n) (ZA_PT_ZA_OFFSET + ((vq * __SVE_VQ_BYTES) * n))
#define ESR_ELx_FSC_FAULT (0x04)
#define DPM_FLAG_MAY_SKIP_RESUME BIT(3)
#define LOGLEVEL_ALERT 1
#define VIRTIO_DEV_ANY_ID 0xffffffff
#define ZONEID_MASK ((1UL << ZONEID_SHIFT) - 1)
#define CONFIG_HAVE_PERF_EVENTS 1
#define HDFGWTR_EL2_PMSCR_EL1 GENMASK(26, 26)
#define SCTLR_EL1_WXN GENMASK(19, 19)
#define CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE 1
#define REG_ID_AA64AFR1_EL1 S3_0_C0_C5_5
#define RXH_XFRM_SYM_XOR (1 << 0)
#define ID_AFR0_EL1_IMPDEF2_SHIFT 8
#define ICH_LR_HW (1ULL << 61)
#define SIGABRT 6
#define ID_AA64DFR0_EL1_MTPMU_NI UL(0b1111)
#define PR_PAC_SET_ENABLED_KEYS 60
#define IPV6_2292DSTOPTS 4
#define ID_ISAR2_EL1_MemHint_MASK GENMASK(7, 4)
#define ID_ISAR1_EL1_IfThen_IMP UL(0b0001)
#define netif_level(level,priv,type,dev,fmt,args...) do { if (netif_msg_ ##type(priv)) netdev_ ##level(dev, fmt, ##args); } while (0)
#define ETHTOOL_GET_DUMP_FLAG 0x0000003f
#define SIGSTKSZ 16384
#define ID_AA64DFR0_EL1_BRBE_BRBE_V1P1 UL(0b0010)
#define rb_entry(ptr,type,member) container_of(ptr, type, member)
#define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
#define CONFIG_RD_ZSTD 1
#define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
#define S_IFCHR 0020000
#define ID_ISAR6_EL1_FHM_NI UL(0b0000)
#define SOFTIRQ_LOCK_OFFSET (SOFTIRQ_DISABLE_OFFSET + PREEMPT_LOCK_OFFSET)
#define HFGxTR_EL2_AFSR0_EL1_MASK GENMASK(0, 0)
#define NLMSG_ALIGNTO 4U
#define SYS_ID_ISAR4_EL1_CRm 2
#define SYS_ID_ISAR4_EL1_CRn 0
#define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY))
#define __UAPI_DEF_IF_NET_DEVICE_FLAGS 1
#define HWCAP_ASIMDDP (1 << 20)
#define PORT_FIBRE 0x03
#define dma_map_single(d,a,s,r) dma_map_single_attrs(d, a, s, r, 0)
#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
#define core_initcall_sync(fn) __define_initcall(fn, 1s)
#define NT_LOONGARCH_LSX 0xa02
#define MPIDR_UP_BITMASK (0x1 << 30)
#define AF_UNIX 1
#define __weak __attribute__((__weak__))
#define RW_DEP_MAP_INIT(lockname) .dep_map = { .name = #lockname, .wait_type_inner = LD_WAIT_CONFIG, }
#define LPA_1000MSRES 0x4000
#define SIPHASH_CONST_1 0x646f72616e646f6dULL
#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
#define DACR32_EL2_D0 GENMASK(1, 0)
#define DACR32_EL2_D1 GENMASK(3, 2)
#define DACR32_EL2_D2 GENMASK(5, 4)
#define DACR32_EL2_D3 GENMASK(7, 6)
#define DACR32_EL2_D4 GENMASK(9, 8)
#define DACR32_EL2_D5 GENMASK(11, 10)
#define DACR32_EL2_D6 GENMASK(13, 12)
#define DACR32_EL2_D7 GENMASK(15, 14)
#define DACR32_EL2_D8 GENMASK(17, 16)
#define DACR32_EL2_D9 GENMASK(19, 18)
#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
#define SO_DONTROUTE 5
#define SYS_ID_AA64ISAR2_EL1_CRm 6
#define ID_AA64MMFR1_EL1_CMOW_SHIFT 56
#define ID_ISAR4_EL1_SMC_IMP UL(0b0001)
#define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
#define __ATTR(_name,_mode,_show,_store) { .attr = {.name = __stringify(_name), .mode = VERIFY_OCTAL_PERMISSIONS(_mode) }, .show = _show, .store = _store, }
#define SIPHASH_CONST_2 0x6c7967656e657261ULL
#define NICE_WIDTH (MAX_NICE - MIN_NICE + 1)
#define ZA_SIG_REGS_OFFSET ((sizeof(struct za_context) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
#define __pgprot(x) ((pgprot_t) { (x) } )
#define CONFIG_LD_ORPHAN_WARN 1
#define ID_ISAR1_EL1_Interwork_WIDTH 4
#define HDFGRTR_EL2_OSECCR_EL1_WIDTH 1
#define CHECKSUM_BREAK 76
#define HCRX_EL2_PTTWI_WIDTH 1
#define __LINUX_RWLOCK_H 
#define NETLINK_USERSOCK 2
#define EM_UNICORE 110
#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling)
#define ID_AA64ISAR1_EL1_LRCPC_SIGNED false
#define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
#define MDIO_PMA_STAT2_LBABLE 0x0001
#define DEFINE_NOIRQ_DEV_PM_OPS(name,suspend_fn,resume_fn) const struct dev_pm_ops name = { NOIRQ_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) }
#define HFGITR_EL2_ATS1E1R_SHIFT 12
#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
#define _inl _inl
#define ID_AA64PFR1_EL1_RNDR_trap_IMP UL(0b0001)
#define CONFIG_LOCK_DEBUGGING_SUPPORT 1
#define STATX_ATIME 0x00000020U
#define local_lock(lock) __local_lock(lock)
#define MAX_CLOCKS 16
#define ATTR_MTIME_SET (1 << 8)
#define COMPAT_HWCAP_CRUNCH (1 << 10)
#define ERFKILL 132
#define __ATTR_IGNORE_LOCKDEP(_name,_mode,_show,_store) { .attr = {.name = __stringify(_name), .mode = _mode, .ignore_lockdep = true }, .show = _show, .store = _store, }
#define SYS_TCR2_EL1_CRm 0
#define SYS_OSDTRTX_EL1_CRm 3
#define SYS_OSDTRTX_EL1_CRn 0
#define unlikely_notrace(x) unlikely(x)
#define DL_FLAG_MANAGED BIT(6)
#define HDFGRTR_EL2_PMCEIDn_EL0_WIDTH 1
#define MSGGET 13
#define HFGxTR_EL2_nMAIR2_EL1 GENMASK(62, 62)
#define __PASTE(a,b) ___PASTE(a,b)
#define HFGxTR_EL2_nPIR_EL1_WIDTH 1
#define __HAVE_ARCH_TAG_CLEAR_HIGHPAGE 
#define MVFR1_EL1_SIMDInt_SIGNED false
#define TASK_IDLE (TASK_UNINTERRUPTIBLE | TASK_NOLOAD)
#define SCTLR_EL1_UNKN (UL(0))
#define PT_NULL 0
#define PMSIRR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32) | GENMASK_ULL(7, 1))
#define PMSIRR_EL1_RES1 (UL(0))
#define __NR_rt_sigtimedwait 137
#define MDIO_NAME_SIZE 32
#define S_IALLUGO (S_ISUID|S_ISGID|S_ISVTX|S_IRWXUGO)
#define ID_AA64PFR1_EL1_MTE_frac_ASYNC UL(0b0000)
#define EPOLLRDHUP (__force __poll_t)0x00002000
#define SHM_HUGE_2GB HUGETLB_FLAG_ENCODE_2GB
#define ID_ISAR5_EL1_SEVL_MASK GENMASK(3, 0)
#define NSEC_CONVERSION ((unsigned long)((((u64)1 << NSEC_JIFFIE_SC) + TICK_NSEC -1) / (u64)TICK_NSEC))
#define PTRACE_MODE_ATTACH_FSCREDS (PTRACE_MODE_ATTACH | PTRACE_MODE_FSCREDS)
#define pr_warn(fmt,...) printk(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__)
#define dev_emerg(dev,fmt,...) dev_printk_index_wrap(_dev_emerg, KERN_EMERG, dev, dev_fmt(fmt), ##__VA_ARGS__)
#define IORESOURCE_MUXED 0x00400000
#define CONFIG_ARM_GIC_V3_ITS 1
#define nops(n) asm volatile(__nops(n))
#define _BITULL(x) (_ULL(1) << (x))
#define ACPI_ID_LEN 16
#define SYS_SMCR_EL12_Op2 6
#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
#define _LINUX_BUILD_BUG_H 
#define R_AARCH64_LD_PREL_LO19 273
#define ID_MMFR3_EL1_CMaintVA_MASK GENMASK(3, 0)
#define NLA_F_NESTED (1 << 15)
#define RWH_WRITE_LIFE_SHORT 2
#define IOP_DEFAULT_READLINK 0x0010
#define TASK_SIZE_64 (UL(1) << vabits_actual)
#define wfit(val) asm volatile("msr s0_3_c1_c0_1, %0" : : "r" (val) : "memory")
#define __ASM_EXTABLE_H 
#define MDSCR_EL1_TDA_WIDTH 1
#define HFGITR_EL2_TLBIVMALLE1OS_WIDTH 1
#define ETH_P_802_3_MIN 0x0600
#define __NR_setgid 144
#define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG))
#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
#define EXTRA_MAGIC 0x45585401
#define ESR_ELx_S1PTW_SHIFT (7)
#define REG_MVFR0_EL1 S3_0_C0_C3_0
#define HFGxTR_EL2_nPIR_EL1 GENMASK(58, 58)
#define PF_PHONET AF_PHONET
#define CONFIG_LD_ORPHAN_WARN_LEVEL "warn"
#define XA_FLAGS_ALLOC1 (XA_FLAGS_TRACK_FREE | XA_FLAGS_ZERO_BUSY)
#define xas_unlock_irq(xas) xa_unlock_irq((xas)->xa)
#define PT_HIPROC 0x7fffffff
#define IFHWADDRLEN 6
#define MAX_DVM_OPS PTRS_PER_PTE
#define TIF_RESTORE_SIGMASK 20
#define HDFGWTR_EL2_TRBTRG_EL1_SHIFT 56
#define ELFMAG "\177ELF"
#define ID_AFR0_EL1_RES1 (UL(0))
#define dev_emerg_ratelimited(dev,fmt,...) dev_level_ratelimited(dev_emerg, dev, fmt, ##__VA_ARGS__)
#define MTE_GRANULE_SIZE UL(16)
#define ID_AA64ISAR1_EL1_SB GENMASK(39, 36)
#define HDFGRTR_EL2_DBGWVRn_EL1_MASK GENMASK(3, 3)
#define ESR_ELx_EC_SMC64 (0x17)
#define __RAW_SPIN_LOCK_INITIALIZER(lockname) { .raw_lock = __ARCH_SPIN_LOCK_UNLOCKED, SPIN_DEBUG_INIT(lockname) RAW_SPIN_DEP_MAP_INIT(lockname) }
#define ID_AA64MMFR1_EL1_RES0 (UL(0))
#define STATIC_KEY_CHECK_USE(key) WARN(!static_key_initialized, "%s(): static key '%pS' used before call to jump_label_init()", __func__, (key))
#define __be64_to_cpus(x) __swab64s((x))
#define ID_AA64ISAR0_EL1_SM4_IMP UL(0b0001)
#define CONFIG_WLAN 1
#define POLLMSG 0x0400
#define _LINUX_STDDEF_H 
#define ID_ISAR3_EL1_Saturate_NI UL(0b0000)
#define CONFIG_SYNC_FILE 1
#define ETH_P_ERSPAN 0x88BE
#define HFGITR_EL2_DCZVA GENMASK(11, 11)
#define JOBCTL_PENDING_MASK (JOBCTL_STOP_PENDING | JOBCTL_TRAP_MASK)
#define work_on_cpu(_cpu,_fn,_arg) ({ static struct lock_class_key __key; work_on_cpu_key(_cpu, _fn, _arg, &__key); })
#define kcsan_check_atomic_read(ptr,size) kcsan_check_access(ptr, size, KCSAN_ACCESS_ATOMIC)
#define ARM_CPU_IMP_APM 0x50
#define DEFINE_XARRAY_ALLOC1(name) DEFINE_XARRAY_FLAGS(name, XA_FLAGS_ALLOC1)
#define QUOTA_NL_BSOFTBELOW 10
#define FMODE_CAN_READ ((__force fmode_t)0x20000)
#define SO_COOKIE 57
#define pm_generic_restore_noirq NULL
#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
#define elf_note elf64_note
#define ID_MMFR3_EL1_PAN_NI UL(0b0000)
#define PMBIDR_EL1_F_MASK GENMASK(5, 5)
#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
#define MNT_UMOUNT 0x8000000
#define TCR_A1 (UL(1) << 22)
#define SVE_SIG_PREGS_SIZE(vq) __SVE_PREGS_SIZE(vq)
#define CONFIG_EPOLL 1
#define set_personality(pers) (current->personality = (pers))
#define TCR2_EL1x_E0POE_MASK GENMASK(2, 2)
#define outb _outb
#define _ASM_EARLY_IOREMAP_H_ 
#define __CTL_TABLE_POLL_INITIALIZER(name) { .event = ATOMIC_INIT(0), .wait = __WAIT_QUEUE_HEAD_INITIALIZER(name.wait) }
#define HWCAP2_SVESM4 (1 << 6)
#define ETHTOOL_F_WISH (1 << ETHTOOL_F_WISH__BIT)
#define ID_AA64ISAR0_EL1_TLB_RANGE UL(0b0010)
#define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
#define outl _outl
#define HCRX_EL2_SMPME_WIDTH 1
#define arch_atomic64_set arch_atomic_set
#define S_NOATIME (1 << 1)
#define RWH_WRITE_LIFE_NOT_SET 0
#define PR_PAC_APGAKEY (1UL << 4)
#define NETLINK_KOBJECT_UEVENT 15
#define bvec_iter_bvec(bvec,iter) ((struct bio_vec) { .bv_page = bvec_iter_page((bvec), (iter)), .bv_len = bvec_iter_len((bvec), (iter)), .bv_offset = bvec_iter_offset((bvec), (iter)), })
#define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550)
#define KUNIT_EXPECT_TRUE_MSG(test,condition,fmt,...) KUNIT_TRUE_MSG_ASSERTION(test, KUNIT_EXPECTATION, condition, fmt, ##__VA_ARGS__)
#define TASK_EXEC ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0)
#define ID_AA64MMFR2_EL1_E0PD_WIDTH 4
#define CONFIG_PGTABLE_LEVELS 3
#define _LINUX_TYPES_H 
#define dgh() asm volatile("hint #6" : : : "memory")
#define ARM_CPU_IMP_ARM 0x41
#define ID_AA64MMFR1_EL1_ETS_NI UL(0b0000)
#define HDFGRTR_EL2_PMSICR_EL1_MASK GENMASK(29, 29)
#define HCRX_EL2_TCR2En_MASK GENMASK(14, 14)
#define ENOTEMPTY 39
#define VM_UFFD_WP 0x00001000
#define HDFGRTR_EL2_TRCAUXCTLR_SHIFT 35
#define ALLINT_RES0 (UL(0) | GENMASK_ULL(63, 14) | GENMASK_ULL(12, 0))
#define ALLINT_RES1 (UL(0))
#define spin_acquire_nest(l,s,t,n,i) lock_acquire_exclusive(l, s, t, n, i)
#define HFGITR_EL2_SVC_EL1_MASK GENMASK(53, 53)
#define SCTLR_ELx_ITFSB (BIT(37))
#define SCHED_CAPACITY_SHIFT SCHED_FIXEDPOINT_SHIFT
#define HFGxTR_EL2_SCTLR_EL1_MASK GENMASK(29, 29)
#define CONFIG_CMA_ALIGNMENT 8
#define IPV6_PREFER_SRC_PUBLIC 0x0002
#define PMSCR_EL2_CX_MASK GENMASK(3, 3)
#define SHM_HUGE_2MB HUGETLB_FLAG_ENCODE_2MB
#define pm_generic_poweroff_noirq NULL
#define HSTR_EL2_T(x) (1 << x)
#define list_first_entry(ptr,type,member) list_entry((ptr)->next, type, member)
#define SUPPORTED_10baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Full)
#define ID_AA64MMFR1_EL1_ETS_SHIFT 36
#define ID_AA64ZFR0_EL1_AES_PMULL128 UL(0b0010)
#define __NR_futex_wait 455
#define ID_AA64SMFR0_EL1_BI32I32 GENMASK(33, 33)
#define ID_PFR1_EL1_Sec_frac_SECURE_MEMORY UL(0b0010)
#define CONFIG_AS_HAS_LSE_ATOMICS 1
#define U32_MAX ((u32)~0U)
#define LSM_SETID_RE 2
#define pud_set_fixmap(addr) NULL
#define USEC_PER_MSEC 1000L
#define ENOTNAM 118
#define MDIO_PMA_LASI_LSALARM 0x0001
#define DT_RELSZ 18
#define SIGALRM 14
#define raw_spin_trylock_irq(lock) ({ local_irq_disable(); raw_spin_trylock(lock) ? 1 : ({ local_irq_enable(); 0; }); })
#define HWCAP_PMULL (1 << 4)
#define ID_PFR0_EL1_RAS_SIGNED false
#define _UAPI_LINUX_KERNEL_H 
#define ID_AA64MMFR3_EL1_S1POE_SHIFT 16
#define PIRx_ELx_Perm10_SHIFT 40
#define page_address_init() do { } while(0)
#define ESR_ELx_IDS_SHIFT (24)
#define KPROBE_FLAG_GONE 1
#define ID_PFR0_EL1_RAS GENMASK(31, 28)
#define data_race(expr) ({ __unqual_scalar_typeof(({ expr; })) __v = ({ __kcsan_disable_current(); expr; }); __kcsan_enable_current(); __v; })
#define __NR_munmap 215
#define MDIO_PCS_10T1L_CTRL_RESET 0x8000
#define CLD_EXITED 1
#define MDSCR_EL1_HDE GENMASK(14, 14)
#define EI_NIDENT 16
#define SCTP_V4_FLOW 0x03
#define flowi_proto u.__fl_common.flowic_proto
#define ID_AA64MMFR1_EL1_ETS_MASK GENMASK(39, 36)
#define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 0)
#define MDIO_USXGMII_10 0x0000
#define _PAGE_SHARED_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
#define ID_ISAR6_EL1_SPECRES_WIDTH 4
#define seqprop_preemptible(s) __seqprop(s, preemptible)(s)
#define SPEED_UNKNOWN -1
#define raw_copy_from_user(to,from,n) ({ unsigned long __acfu_ret; uaccess_ttbr0_enable(); __acfu_ret = __arch_copy_from_user((to), __uaccess_mask_ptr(from), (n)); uaccess_ttbr0_disable(); __acfu_ret; })
#define HWCAP2_SME2P1 (1UL << 38)
#define PT_NOTE 4
#define PAGE_MAPPING_MOVABLE 0x2
#define HDFGRTR_EL2_nBRBCTL_WIDTH 1
#define USB_DEVICE_ID_MATCH_DEV_CLASS 0x0010
#define EM_S390_OLD 0xA390
#define pte_valid_not_user(pte) ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
#define HDFGWTR_EL2_TRBTRG_EL1_WIDTH 1
#define SOCK_PASSSEC 4
#define _PTRDIFF_T 
#define ID_AA64DFR0_EL1_DebugVer_V8P2 UL(0b1000)
#define ID_AA64DFR0_EL1_DebugVer_V8P4 UL(0b1001)
#define ID_AA64DFR0_EL1_DebugVer_V8P8 UL(0b1010)
#define _LINUX_CLOCKSOURCE_IDS_H 
#define PSR_MODE_EL2t 0x00000008
#define ID_AA64PFR1_EL1_SSBS_WIDTH 4
#define CRm_mask 0xf
#define ID_AA64AFR0_EL1_IMPDEF5_WIDTH 4
#define ID_ISAR3_EL1_T32Copy_SHIFT 20
#define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
#define SCXTNUM_EL1_RES0 (UL(0))
#define SCXTNUM_EL1_RES1 (UL(0))
#define IPV6_PRIORITY_RESERVED1 0x0300
#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
#define MDCR_EL2_MTPME (UL(1) << 28)
#define PR_SET_MM_BRK 7
#define BIN_ATTR_WO(_name,_size) struct bin_attribute bin_attr_ ##_name = __BIN_ATTR_WO(_name, _size)
#define __NR_pidfd_open 434
#define IOPRIO_PRIO_VALUE_HINT(prioclass,priolevel,priohint) ioprio_value(prioclass, priolevel, priohint)
#define IPV6_PRIORITY_RESERVED2 0x0500
#define I_SYNC (1 << __I_SYNC)
#define LED_COLOR_ID_LIME 14
#define HCRX_EL2_EnALS GENMASK(1, 1)
#define __NR_readlinkat 78
#define ID_AA64PFR0_EL1_DIT GENMASK(51, 48)
#define SIGNAL_STOP_MASK (SIGNAL_CLD_MASK | SIGNAL_STOP_STOPPED | SIGNAL_STOP_CONTINUED)
#define AT_NO_AUTOMOUNT 0x800
#define ETH_P_ALL 0x0003
#define CONFIG_WLAN_VENDOR_SILABS 1
#define __GFP_HIGHMEM ((__force gfp_t)___GFP_HIGHMEM)
#define __VDSO_CONST_H 
#define NETLINK_UNUSED 1
#define _LINUX_DMA_DIRECTION_H 
#define LED_FUNCTION_PROGRAMMING "programming"
#define nmi_enter() do { __nmi_enter(); lockdep_hardirq_enter(); ct_nmi_enter(); instrumentation_begin(); ftrace_nmi_enter(); instrumentation_end(); } while (0)
#define HDFGRTR_EL2_PMCCNTR_EL0_SHIFT 15
#define SCM_TXTIME SO_TXTIME
#define SYS_SOCKETPAIR 8
#define ID_AA64PFR1_EL1_THE_MASK GENMASK(51, 48)
#define SYS_MPIDR_SAFE_VAL (BIT(31))
#define SCTLR_EL1_CP15BEN GENMASK(5, 5)
#define MDIO_PMD_TXDIS_0 0x0002
#define QUOTA_NL_ISOFTBELOW 8
#define ARCH_DLINFO do { NEW_AUX_ENT(AT_SYSINFO_EHDR, (elf_addr_t)current->mm->context.vdso); if (likely(signal_minsigstksz)) NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); else NEW_AUX_ENT(AT_IGNORE, 0); } while (0)
#define F_GETOWN 9
#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
#define ADVERTISE_100HALF 0x0080
#define KBUILD_BASENAME "bindings_generated"
#define HCR_TOCU (UL(1) << 52)
#define MVFR0_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define MVFR0_EL1_RES1 (UL(0))
#define DACR32_EL2_D2_MASK GENMASK(5, 4)
#define _LINUX_TIME_H 
#define __NR_lgetxattr 9
#define HFGxTR_EL2_ERRSELR_EL1_SHIFT 41
#define SUID_DUMP_DISABLE 0
#define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
#define max_t(type,x,y) __careful_cmp(max, (type)(x), (type)(y))
#define SCTLR_EL1_SPINTMASK_WIDTH 1
#define ID_AA64SMFR0_EL1_B16B16_WIDTH 1
#define create_singlethread_workqueue(name) alloc_ordered_workqueue("%s", __WQ_LEGACY | WQ_MEM_RECLAIM, name)
#define CONFIG_SPARSEMEM_VMEMMAP_ENABLE 1
#define PREEMPT_LOCK_RESCHED_OFFSETS PREEMPT_LOCK_OFFSET
#define FT_MAX 8
#define BUILD_BUG_ON(condition) BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
#define SYS_SENDMMSG 20
#define ESR_ELx_ISS2_SHIFT (32)
#define HDFGRTR_EL2_PMSFCR_EL1_MASK GENMASK(28, 28)
#define NOGROUP (-1)
#define __wait_event_interruptible_timeout(wq_head,condition,timeout) ___wait_event(wq_head, ___wait_cond_timeout(condition), TASK_INTERRUPTIBLE, 0, timeout, __ret = schedule_timeout(__ret))
#define RB_ROOT_CACHED (struct rb_root_cached) { {NULL, }, NULL }
#define ID_ISAR0_EL1_BitField_SHIFT 8
#define pgprot_dmacoherent(prot) __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
#define arch_atomic64_fetch_add_release arch_atomic64_fetch_add_release
#define HCRX_EL2_FnXS_SHIFT 3
#define raw_try_cmpxchg128_local(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg128_local((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define WAKE_FILTER (1 << 7)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define ID_ISAR2_EL1_Mult_NI UL(0b0000)
#define ID_AA64ISAR2_EL1_RPRFM_SIGNED false
#define IRQF_SHARED 0x00000080
#define ETHTOOL_PHY_FAST_LINK_DOWN_OFF 0xff
#define ID_AA64MMFR3_EL1_ANERR_ASYNC UL(0b0001)
#define SIG_KERNEL_COREDUMP_MASK ( rt_sigmask(SIGQUIT) | rt_sigmask(SIGILL) | rt_sigmask(SIGTRAP) | rt_sigmask(SIGABRT) | rt_sigmask(SIGFPE) | rt_sigmask(SIGSEGV) | rt_sigmask(SIGBUS) | rt_sigmask(SIGSYS) | rt_sigmask(SIGXCPU) | rt_sigmask(SIGXFSZ) | SIGEMT_MASK )
#define MDIO_USXGMII_EEE_CLK_STP 0x0080
#define for_each_and_bit(bit,addr1,addr2,size) for ((bit) = 0; (bit) = find_next_and_bit((addr1), (addr2), (size), (bit)), (bit) < (size); (bit)++)
#define ID_AA64MMFR0_EL1_BIGENDEL0 GENMASK(19, 16)
#define HDFGRTR_EL2_PMSIRR_EL1_WIDTH 1
#define dma_get_cache_alignment cache_line_size
#define _LINUX_SHM_H_ 
#define EM_MIPS_RS3_LE 10
#define MMF_DUMP_ANON_PRIVATE 2
#define local_try_cmpxchg(l,po,n) atomic_long_try_cmpxchg((&(l)->a), (po), (n))
#define FOLIO_PF_ONLY_HEAD 0
#define MT_S2_DEVICE_nGnRE 0x1
#define REG_ID_ISAR6_EL1 S3_0_C0_C2_7
#define ARM64_MTE_ASYMM 54
#define kunit_test_init_section_suite(suite) kunit_test_init_section_suites(&suite)
#define PCPU_BITMAP_BLOCK_BITS (PCPU_BITMAP_BLOCK_SIZE >> PCPU_MIN_ALLOC_SHIFT)
#define __LINUX_COMPILER_H 
#define _KERNEL_CAP_T_SIZE (sizeof(kernel_cap_t))
#define PCMCIA_DEV_ID_MATCH_PROD_ID2 0x0020
#define __NR_getresgid 150
#define IPV6_RECVHOPLIMIT 51
#define ID_AA64ISAR0_EL1_UNKN (UL(0))
#define CLIDR_EL1_LoUU_SHIFT 27
#define VTCR_EL2_LVLS_TO_SL0(levels) ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
#define CONFIG_IPV6_SIT 1
#define VMA_ITERATOR(name,__mm,__addr) struct vma_iterator name = { .mas = { .tree = &(__mm)->mm_mt, .index = __addr, .node = MAS_START, }, }
#define virt_store_mb(var,value) do { kcsan_mb(); __smp_store_mb(var, value); } while (0)
#define ADJ_TIMECONST 0x0020
#define U32_MIN ((u32)0)
#define CONFIG_OF_GPIO 1
#define TIF_SECCOMP 11
#define __IS_FLG(inode,flg) ((inode)->i_sb->s_flags & (flg))
#define hlist_for_each_entry_safe(pos,n,head,member) for (pos = hlist_entry_safe((head)->first, typeof(*pos), member); pos && ({ n = pos->member.next; 1; }); pos = hlist_entry_safe(n, typeof(*pos), member))
#define S_AUTOMOUNT (1 << 11)
#define VM_MTE_ALLOWED VM_NONE
#define SOL_UDP 17
#define ID_PFR1_EL1_GIC_SIGNED false
#define RESERVED_SWAPPER_OFFSET (PAGE_SIZE)
#define preempt_count_add(val) __preempt_count_add(val)
#define ID_AA64ISAR2_EL1_BC GENMASK(23, 20)
#define radix_tree_for_each_slot(slot,root,iter,start) for (slot = radix_tree_iter_init(iter, start) ; slot || (slot = radix_tree_next_chunk(root, iter, 0)) ; slot = radix_tree_next_slot(slot, iter, 0))
#define S_NOQUOTA (1 << 5)
#define XQM_PRJQUOTA 2
#define SYS_PMSCR_EL2_CRm 9
#define SYS_PMSCR_EL2_CRn 9
#define NLM_F_CAPPED 0x100
#define wake_up_poll_on_current_cpu(x,m) __wake_up_on_current_cpu(x, TASK_NORMAL, poll_to_key(m))
#define ID_ISAR3_EL1_T32Copy GENMASK(23, 20)
#define _TIF_UPROBE (1 << TIF_UPROBE)
#define raw_cpu_or(pcp,val) __pcpu_size_call(raw_cpu_or_, pcp, val)
#define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO)
#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
#define ADVERTISED_Asym_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Asym_Pause)
#define HCRX_EL2_D128En_MASK GENMASK(17, 17)
#define HCR_FWB (UL(1) << 46)
#define __ASM_IRQ_H 
#define SYS_PMBSR_EL1_Op0 3
#define SYS_PMBSR_EL1_Op1 0
#define SYS_PMBSR_EL1_Op2 3
#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400
#define PACKET_HOST 0
#define PR_SVE_SET_VL_ONEXEC (1 << 18)
#define ID_AA64PFR1_EL1_DF2_IMP UL(0b0001)
#define rcutree_dead_cpu NULL
#define ID_PFR0_EL1_AMU_NI UL(0b0000)
#define be32_to_cpu __be32_to_cpu
#define KUNIT_EXPECT_NE_MSG(test,left,right,fmt,...) KUNIT_BINARY_INT_ASSERTION(test, KUNIT_EXPECTATION, left, !=, right, fmt, ##__VA_ARGS__)
#define ___define_initcall(fn,id,__sec) __unique_initcall(fn, id, __sec, __initcall_id(fn))
#define _LINUX_SRCU_TREE_H 
#define _LINUX_NET_DEBUG_H 
#define __AC(X,Y) (X ##Y)
#define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
#define HDFGWTR_EL2_DBGCLAIM_WIDTH 1
#define ISOLATE_ASYNC_MIGRATE ((__force isolate_mode_t)0x4)
#define STATX_BLOCKS 0x00000400U
#define CONFIG_CC_HAS_K_CONSTRAINT 1
#define CONFIG_HAVE_ARCH_KASAN_SW_TAGS 1
#define __LINUX_GFP_TYPES_H 
#define HCRX_EL2_EnAS0 GENMASK(0, 0)
#define ID_AA64MMFR3_EL1_TCRX_IMP UL(0b0001)
#define ID_AA64ISAR0_EL1_FHM_SHIFT 48
#define EXPORT_DEV_SLEEP_PM_OPS(name) _EXPORT_DEV_SLEEP_PM_OPS(name, "", "")
#define SECTION_ROOT_MASK (SECTIONS_PER_ROOT - 1)
#define _LINUX_NOTIFIER_H 
#define phydev_err(_phydev,format,args...) dev_err(&_phydev->mdio.dev, format, ##args)
#define thread_saved_fp(tsk) ((unsigned long)(tsk->thread.cpu_context.fp))
#define __NR_sched_setattr 274
#define lockdep_assert_no_hardirq() do { WARN_ON_ONCE(__lockdep_enabled && (this_cpu_read(hardirq_context) || !this_cpu_read(hardirqs_enabled))); } while (0)
#define COMPAT_HWCAP_26BIT (1 << 3)
#define SO_RCVLOWAT 18
#define ASSERT_STRUCT_OFFSET(type,field,expected_offset) BUILD_BUG_ON_MSG(offsetof(type, field) != (expected_offset), "Offset of " #field " in " #type " has changed.")
#define lockdep_match_class(lock,key) lockdep_match_key(&(lock)->dep_map, key)
#define HCRX_EL2_EnASR GENMASK(2, 2)
#define CONFIG_ARCH_HAS_DEBUG_WX 1
#define KMALLOC_MAX_ORDER (KMALLOC_SHIFT_MAX - PAGE_SHIFT)
#define TAINT_OOT_MODULE 12
#define TTBR_CNP_BIT (UL(1) << 0)
#define ID_AA64DFR0_EL1_TraceBuffer_SHIFT 44
#define ZCR_ELx_UNKN (UL(0))
#define _ASM_GENERIC_ERROR_INJECTION_H 
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
#define ETHTOOL_GTXCSUM 0x00000016
#define __NR_openat 56
#define ___rcuwait_wait_event(w,condition,state,ret,cmd) ({ long __ret = ret; prepare_to_rcuwait(w); for (;;) { set_current_state(state); if (condition) break; if (signal_pending_state(state, current)) { __ret = -EINTR; break; } cmd; } finish_rcuwait(w); __ret; })
#define IPV6_FL_S_PROCESS 2
#define pgprot_tagged(prot) __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
#define CLOCK_REALTIME_COARSE 5
#define ZA_SIG_REGS_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
#define WQ_FLAG_WOKEN 0x02
#define PR_GET_FPEMU 9
#define pte_sw_mkyoung pte_sw_mkyoung
#define MPIDR_MT_BITMASK (0x1 << 24)
#define lockdep_assert_preemption_disabled() do { WARN_ON_ONCE(IS_ENABLED(CONFIG_PREEMPT_COUNT) && __lockdep_enabled && (preempt_count() == 0 && this_cpu_read(hardirqs_enabled))); } while (0)
#define PFN_SUBSECTION_SHIFT (SUBSECTION_SHIFT - PAGE_SHIFT)
#define NT_AUXV 6
#define CONFIG_ARCH_HAS_PTE_SPECIAL 1
#define HDFGRTR_EL2_TRCPRGCTLR_WIDTH 1
#define DECLARE_TASKLET(name,_callback) struct tasklet_struct name = { .count = ATOMIC_INIT(0), .callback = _callback, .use_callback = true, }
#define ID_MMFR0_EL1_TCM GENMASK(19, 16)
#define HDFGWTR_EL2_TRBPTR_EL1_SHIFT 54
#define unlikely(x) __builtin_expect(!!(x), 0)
#define CONFIG_PCIE_BUS_DEFAULT 1
#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
#define PORT_NONE 0xef
#define IPV6_FL_A_PUT 1
#define HFGITR_EL2_TLBIRVAAE1_WIDTH 1
#define ETHTOOL_FEC_RS (1 << ETHTOOL_FEC_RS_BIT)
#define S_APPEND (1 << 2)
#define R_AARCH64_MOVW_UABS_G1 265
#define raw_cpu_generic_to_op(pcp,val,op) do { *raw_cpu_ptr(&(pcp)) op val; } while (0)
#define ID_AA64ISAR1_EL1_LS64_MASK GENMASK(63, 60)
#define ID_AA64MMFR1_EL1_ETS_IMP UL(0b0001)
#define flowi_mark u.__fl_common.flowic_mark
#define S16_C(x) x
#define in_serving_softirq() (softirq_count() & SOFTIRQ_OFFSET)
#define TRBIDR_EL1_RES1 (UL(0))
#define R_AARCH64_MOVW_UABS_G2 267
#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
#define ID_AA64PFR0_EL1_RME_NI UL(0b0000)
#define SOL_BLUETOOTH 274
#define HFGxTR_EL2_nPOR_EL1_MASK GENMASK(60, 60)
#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
#define R_AARCH64_MOVW_UABS_G3 269
#define HFGxTR_EL2_FAR_EL1_WIDTH 1
#define raw_spin_trylock_irqsave(lock,flags) ({ local_irq_save(flags); raw_spin_trylock(lock) ? 1 : ({ local_irq_restore(flags); 0; }); })
#define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
#define CONFIG_SG_POOL 1
#define EM_PPC64 21
#define RUSAGE_CHILDREN (-1)
#define COMPAT_HWCAP_SWP (1 << 0)
#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
#define ID_MMFR1_EL1_L1HvdVA_NI UL(0b0000)
#define __NR_listxattr 11
#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
#define DEFINE_RES_REG(_start,_size) DEFINE_RES_REG_NAMED((_start), (_size), NULL)
#define SLAB_FAILSLAB 0
#define untagged_addr(addr) ({ u64 __addr = (__force u64)(addr); __addr &= __untagged_addr(__addr); (__force __typeof__(addr))__addr; })
#define TASK_REPORT_IDLE (TASK_REPORT + 1)
#define IF_PROTO_FR_ADD_PVC 0x2004
#define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
#define SCTLR_EL1_ATA0_MASK GENMASK(42, 42)
#define NR_REG_ARGUMENTS 8
#define S_IFREG 0100000
#define ID_AA64PFR0_EL1_MPAM_MASK GENMASK(43, 40)
#define __ptr_set_bit(nr,addr) ({ typecheck_pointer(*(addr)); __set_bit(nr, (unsigned long *)(addr)); })
#define CONFIG_SPI_DYNAMIC 1
#define DBG_MDSCR_MDE (1 << 15)
#define raw_read_seqcount_begin(s) ({ unsigned _seq = __read_seqcount_begin(s); smp_rmb(); _seq; })
#define do_trace_printk(fmt,args...) do { static const char *trace_printk_fmt __used __section("__trace_printk_fmt") = __builtin_constant_p(fmt) ? fmt : NULL; __trace_printk_check_format(fmt, ##args); if (__builtin_constant_p(fmt)) __trace_bprintk(_THIS_IP_, trace_printk_fmt, ##args); else __trace_printk(_THIS_IP_, fmt, ##args); } while (0)
#define HFGITR_EL2_TLBIVAE1IS GENMASK(29, 29)
#define FS_BINARY_MOUNTDATA 2
#define DBG_MAX_REG_NUM (_GP_REGS + _FP_REGS + _EXTRA_REGS)
#define PAGEBLOCK_FLAGS_H 
#define USEC_PER_SEC 1000000L
#define alloc_percpu(type) (typeof(type) __percpu *)__alloc_percpu(sizeof(type), __alignof__(type))
#define PMBSR_EL1_S_SHIFT 17
#define ___GFP_ZERO 0x100u
#define __NR_sched_getscheduler 120
#define devm_mdiobus_register(dev,bus) __devm_mdiobus_register(dev, bus, THIS_MODULE)
#define PR_GET_MDWE 66
#define trace_recursion_depth() (((current)->trace_recursion >> TRACE_GRAPH_DEPTH_START_BIT) & 3)
#define REG_LORID_EL1 S3_0_C10_C4_7
#define VTCR_EL2_HA (1 << 21)
#define TCR2_EL1x_PnCH_WIDTH 1
#define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK)
#define PF_MAX AF_MAX
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
#define __NR_pipe2 59
#define LPA_SGMII_1000 0x0800
#define netdev_info_once(dev,fmt,...) netdev_level_once(KERN_INFO, dev, fmt, ##__VA_ARGS__)
#define ADVERTISED_56000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseSR4_Full)
#define clear_task_syscall_work(t,fl) clear_ti_thread_flag(task_thread_info(t), TIF_ ##fl)
#define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1)))
#define ID_AA64MMFR3_EL1_AIE_NI UL(0b0000)
#define VM_ARCH_CLEAR VM_ARM64_BTI
#define CONFIG_DMA_OF 1
#define readb readb
#define this_cpu_generic_add_return(pcp,val) ({ typeof(pcp) __ret; unsigned long __flags; raw_local_irq_save(__flags); __ret = raw_cpu_generic_add_return(pcp, val); raw_local_irq_restore(__flags); __ret; })
#define STATX_ATTR_APPEND 0x00000020
#define CCSIDR_EL1_UNKN (UL(0) | GENMASK_ULL(31, 28))
#define wait_event_interruptible_exclusive(wq,condition) ({ int __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_event_interruptible_exclusive(wq, condition); __ret; })
#define conditional_stopped_child_used_math(condition,child) do { (child)->flags &= ~PF_USED_MATH, (child)->flags |= (condition) ? PF_USED_MATH : 0; } while (0)
#define CONFIG_ARCH_WANT_FRAME_POINTERS 1
#define MAPLE_HEIGHT_MAX 31
#define NT_ARM_SYSTEM_CALL 0x404
#define ID_AA64PFR0_EL1_RAS_WIDTH 4
#define REG_ID_ISAR3_EL1 S3_0_C0_C2_3
#define CLIDR_EL1_LoUU_MASK GENMASK(29, 27)
#define BITMAP_FROM_U64(n) (n)
#define BITS_PER_XA_VALUE (BITS_PER_LONG - 1)
#define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
#define COMPAT_HWCAP_THUMBEE (1 << 11)
#define ID_AA64DFR0_EL1_HPMN0_DEF UL(0b0001)
#define ID_ISAR6_EL1_RES0 (UL(0) | GENMASK_ULL(63, 28))
#define ID_ISAR6_EL1_RES1 (UL(0))
#define PHY_IS_INTERNAL 0x00000001
#define SSAM_MATCH_TARGET 0x1
#define SYS_MPAMVPM4_EL2 __SYS__MPAMVPMx_EL2(4)
#define ID_AA64DFR0_EL1_TraceBuffer_MASK GENMASK(47, 44)
#define WAKE_MCAST (1 << 2)
#define F_GETOWNER_UIDS 17
#define LORSA_EL1_Valid GENMASK(0, 0)
#define ADVERTISED_10000baseR_FEC __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseR_FEC)
#define PMSFCR_EL1_ST_MASK GENMASK(18, 18)
#define PMD_MAYBE_NG (arm64_use_ng_mappings ? PMD_SECT_NG : 0)
#define HFGxTR_EL2_ERXMISCn_EL1_SHIFT 45
#define CONFIG_NET_VENDOR_NATSEMI 1
#define arch_atomic64_fetch_xor arch_atomic64_fetch_xor
#define CONFIG_NET_VENDOR_ALACRITECH 1
#define AT_RSEQ_FEATURE_SIZE 27
#define PMBSR_EL1_UNKN (UL(0))
#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
#define KPROBES_BRK_SS_IMM 0x006
#define ID_MMFR4_EL1_HPDS_NI UL(0b0000)
#define nodes_andnot(dst,src1,src2) __nodes_andnot(&(dst), &(src1), &(src2), MAX_NUMNODES)
#define __ONCE_LITE_IF(condition) ({ static bool __section(".data.once") __already_done; bool __ret_cond = !!(condition); bool __ret_once = false; if (unlikely(__ret_cond && !__already_done)) { __already_done = true; __ret_once = true; } unlikely(__ret_once); })
#define PCPF_PREV_FREE_HIGH_ORDER BIT(0)
#define TRBLIMITR_EL1_TM_IRQ UL(0b01)
#define user_write_access_end user_access_end
#define HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT 34
#define IFNAMSIZ 16
#define arch_kasan_reset_tag(addr) __tag_reset(addr)
#define annotate_unreachable() 
#define kcsan_check_atomic_write(ptr,size) kcsan_check_access(ptr, size, KCSAN_ACCESS_ATOMIC | KCSAN_ACCESS_WRITE)
#define CONFIG_GENERIC_HWEIGHT 1
#define put_group_info(group_info) do { if (refcount_dec_and_test(&(group_info)->usage)) groups_free(group_info); } while (0)
#define HWCAP2_SME_F16F32 (1 << 27)
#define PMSICR_EL1_COUNT GENMASK(31, 0)
#define BMCR_ISOLATE 0x0400
#define REG_GMID_EL1 S3_1_C0_C0_4
#define SYS_TCR2_EL1 sys_reg(3, 0, 2, 0, 3)
#define SYS_TCR2_EL2 sys_reg(3, 4, 2, 0, 3)
#define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
#define PT_SEIZED 0x00010000
#define CLIDR_LOC_SHIFT 24
#define ID_AA64SMFR0_EL1_B16F32_SIGNED false
#define DEFINE_RES_REG_NAMED(_start,_size,_name) DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_REG)
#define CONFIG_HAVE_ARCH_AUDITSYSCALL 1
#define SDTL_OVERLAP 0x01
#define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
#define EIDRM 43
#define ESR_ELx_EC_WATCHPT_CUR (0x35)
#define SVE_SIG_PREG_OFFSET(vq,n) (SVE_SIG_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
#define SEMOP 1
#define ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
#define be16_to_cpu __be16_to_cpu
#define __NR_mmap __NR3264_mmap
#define MDIO_EEE_5GT 0x0002
#define HFGxTR_EL2_SCXTNUM_EL1_MASK GENMASK(30, 30)
#define HFGxTR_EL2_TTBR1_EL1_SHIFT 37
#define COMPAT_HWCAP_FPHP (1 << 22)
#define NLM_F_EXCL 0x200
#define __native_word(t) (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long))
#define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
#define ETH_P_PAE 0x888E
#define PHY_POLL -1
#define ID_ISAR3_EL1_T32EE GENMASK(31, 28)
#define ID_AA64ISAR1_EL1_API_PAuth UL(0b0001)
#define arch_setup_new_exec arch_setup_new_exec
#define TASK_SIZE_OF(tsk) TASK_SIZE
#define __LINUX_STRINGHASH_H 
#define __ASM_MTE_KASAN_H 
#define ID_AA64MMFR1_EL1_HCX GENMASK(43, 40)
#define PMSLATFR_EL1_UNKN (UL(0))
#define LOOPBACK_IFINDEX 1
#define arch_cmpxchg_release(...) __cmpxchg_wrapper(_rel, __VA_ARGS__)
#define ID_AA64ZFR0_EL1_BF16_SIGNED false
#define thread_saved_pc(tsk) ((unsigned long)(tsk->thread.cpu_context.pc))
#define __wait_event_state(wq,condition,state) ___wait_event(wq, condition, state, 0, 0, schedule())
#define __I_SYNC 7
#define KUNIT_ASSERT_STRNEQ_MSG(test,left,right,fmt,...) KUNIT_BINARY_STR_ASSERTION(test, KUNIT_ASSERTION, left, !=, right, fmt, ##__VA_ARGS__)
#define NULL_VM_UFFD_CTX ((struct vm_userfaultfd_ctx) {})
#define HDFGRTR_EL2_DBGBCRn_EL1_MASK GENMASK(0, 0)
#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | _TIF_UPROBE | _TIF_MTE_ASYNC_FAULT | _TIF_NOTIFY_SIGNAL)
#define set_fixmap(idx,phys) __set_fixmap(idx, phys, FIXMAP_PAGE_NORMAL)
#define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
#define MNT_SHARED 0x1000
#define HFGITR_EL2_TLBIVAAE1 GENMASK(45, 45)
#define SHRINK_EMPTY (~0UL - 1)
#define PMSG_RESTORE ((struct pm_message){ .event = PM_EVENT_RESTORE, })
#define MMF_HUGE_ZERO_PAGE 23
#define SIOCGIFFLAGS 0x8913
#define LLIST_H 
#define min_wmark_pages(z) (z->_watermark[WMARK_MIN] + z->watermark_boost)
#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0
#define PMSCR_EL1_PA_SHIFT 4
#define CONFIG_NET_VENDOR_OKI 1
#define ID_AA64AFR0_EL1_IMPDEF0 GENMASK(3, 0)
#define ID_AA64AFR0_EL1_IMPDEF1 GENMASK(7, 4)
#define ID_AA64AFR0_EL1_IMPDEF2 GENMASK(11, 8)
#define ID_AA64AFR0_EL1_IMPDEF3 GENMASK(15, 12)
#define ID_AA64AFR0_EL1_IMPDEF4 GENMASK(19, 16)
#define ID_AA64AFR0_EL1_IMPDEF5 GENMASK(23, 20)
#define ID_AA64AFR0_EL1_IMPDEF6 GENMASK(27, 24)
#define ID_AA64AFR0_EL1_IMPDEF7 GENMASK(31, 28)
#define RNDADDENTROPY _IOW( 'R', 0x03, int [2] )
#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | ESR_ELx_SYS64_ISS_DIR_READ)
#define SHIFT_PLL 2
#define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
#define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
#define TTBRx_EL1_BADDR GENMASK(47, 1)
#define SYS_MDSCR_EL1_CRm 2
#define SYS_MDSCR_EL1_CRn 0
#define CONFIG_LOG_CPU_MAX_BUF_SHIFT 12
#define SOL_PACKET 263
#define kcsan_check_atomic_read_write(ptr,size) kcsan_check_access(ptr, size, KCSAN_ACCESS_ATOMIC | KCSAN_ACCESS_WRITE | KCSAN_ACCESS_COMPOUND)
#define ID_AA64MMFR0_EL1_TGRAN16_52_BIT UL(0b0010)
#define PMSFCR_EL1_LD_MASK GENMASK(17, 17)
#define ADJ_STATUS 0x0010
#define pgd_ERROR(e) pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
#define SCTLR_EL1_I_MASK GENMASK(12, 12)
#define page_private(page) ((page)->private)
#define RWF_NOWAIT ((__force __kernel_rwf_t)0x00000008)
#define HDFGRTR_EL2_TRCSEQSTR_MASK GENMASK(45, 45)
#define ID_AA64MMFR3_EL1_Spec_FPACC_WIDTH 4
#define PAGE_READONLY __pgprot(_PAGE_READONLY)
#define ID_AA64MMFR2_EL1_BBM_WIDTH 4
#define ARM64_ASM_PREAMBLE ".arch " ARM64_ASM_ARCH "\n"
#define PR_GET_FPEXC 11
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2
#define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
#define BMCR_ANRESTART 0x0200
#define CACHELINE_PADDING(name) struct cacheline_padding name
#define ID_AA64PFR1_EL1_NMI GENMASK(39, 36)
#define PTE_MAYBE_NG (arm64_use_ng_mappings ? PTE_NG : 0)
#define ___GFP_HIGHMEM 0x02u
#define QC_RT_SPC_TIMER (1<<8)
#define PMSCR_EL1_PCT_SHIFT 6
#define ID_AA64SMFR0_EL1_I8I32_SIGNED false
#define ID_AA64ZFR0_EL1_F64MM_NI UL(0b0000)
#define SIGEV_THREAD 2
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
#define plist_next(pos) list_next_entry(pos, node_list)
#define ID_DFR0_EL1_CopSDbg_MASK GENMASK(7, 4)
#define ID_MMFR0_EL1_VMSA_VMSAv7_LONG UL(0b0101)
#define _LINUX_FWNODE_H_ 
#define CONFIG_NET_VENDOR_NI 1
#define CORE_DUMP_USE_REGSET 
#define ID_AA64PFR0_EL1_FP_SIGNED true
#define seqcount_spinlock_init(s,lock) seqcount_LOCKNAME_init(s, lock, spinlock)
#define PTRACE_GET_RSEQ_CONFIGURATION 0x420f
#define AF_IUCV 32
#define raw_cmpxchg64_release arch_cmpxchg64_release
#define IS_SETLKW64(cmd) ((cmd) == F_SETLKW)
#define NETIF_F_RX_UDP_TUNNEL_PORT __NETIF_F(RX_UDP_TUNNEL_PORT)
#define HFGITR_EL2_TLBIVMALLE1 GENMASK(42, 42)
#define SIOCSIFVLAN 0x8983
#define thread_saved_sp(tsk) ((unsigned long)(tsk->thread.cpu_context.sp))
#define ID_ISAR0_EL1_BitCount_SIGNED false
#define static_branch_disable_cpuslocked(x) static_key_disable_cpuslocked(&(x)->key)
#define PMSCR_EL1_TS_MASK GENMASK(5, 5)
#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
#define ID_MMFR4_EL1_HPDS_AA32HPD UL(0b0001)
#define ETH_RSS_HASH_NO_CHANGE 0
#define IDR_RT_MARKER (ROOT_IS_IDR | (__force gfp_t) (1 << (ROOT_TAG_SHIFT + IDR_FREE)))
#define __NR3264_fstatat 79
#define sev() asm volatile("sev" : : : "memory")
#define CLONE_PARENT_SETTID 0x00100000
#define PR_MCE_KILL_EARLY 1
#define SECCOMP_USER_NOTIF_FD_SYNC_WAKE_UP (1UL << 0)
#define HFGxTR_EL2_TPIDR_EL1_MASK GENMASK(33, 33)
#define __MODULE_PARM_TYPE(name,_type) __MODULE_INFO(parmtype, name ##type, #name ":" _type)
#define bit_clear_unless(ptr,clear,test) ({ const typeof(*(ptr)) clear__ = (clear), test__ = (test); typeof(*(ptr)) old__, new__; old__ = READ_ONCE(*(ptr)); do { if (old__ & test__) break; new__ = old__ & ~clear__; } while (!try_cmpxchg(ptr, &old__, new__)); !(old__ & test__); })
#define REG_ID_AA64MMFR3_EL1 S3_0_C0_C7_3
#define KASAN_BRK_MASK 0x0ff
#define HCRX_EL2_EnSNERR_MASK GENMASK(18, 18)
#define ID_AA64MMFR3_EL1_SNERR_WIDTH 4
#define ID_ISAR4_EL1_SWP_frac_NI UL(0b0000)
#define __NR_accept 202
#define S_IRWXUGO (S_IRWXU|S_IRWXG|S_IRWXO)
#define ID_ISAR5_EL1_AES GENMASK(7, 4)
#define pr_debug(fmt,...) no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
#define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
#define ARM64_CPUCAP_SYSTEM_FEATURE (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
#define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
#define MUTEX_DEBUG_INIT 0x11
#define ___test_and_clear_bit arch___test_and_clear_bit
#define ID_AA64ISAR2_EL1_APA3_EPAC UL(0b0010)
#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6)
#define ID_AA64MMFR0_EL1_TGRAN4_2_52_BIT UL(0b0011)
#define HZ_TO_MSEC_DEN 1
#define __NR_getuid 174
#define SIOCRTMSG 0x890D
#define __ARCH_WANT_TIME32_SYSCALLS 
#define nr_online_nodes 1U
#define HFGxTR_EL2_MAIR_EL1_SHIFT 24
#define SCTLR_EL1_ITD GENMASK(7, 7)
#define _LINUX_SCHED_USER_H 
#define __atomic_post_full_fence smp_mb__after_atomic
#define CONFIG_I2C_GPIO 1
#define __ASM_BITOPS_H 
#define ID_AA64MMFR0_EL1_ASIDBITS_WIDTH 4
#define ID_AA64MMFR2_EL1_IDS GENMASK(39, 36)
#define HFGITR_EL2_ICIVAU_WIDTH 1
#define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
#define SCTLR_EL1_EnIA_SHIFT 31
#define pm_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM), (_ptr))
#define CONFIG_HAVE_PERF_REGS 1
#define ETH_P_DSA_8021Q 0xDADB
#define CONFIG_CGROUP_NET_CLASSID 1
#define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
#define SCTLR_ELx_ENDA (BIT(27))
#define SCTLR_ELx_ENDB (BIT(13))
#define KERNEL_HWCAP_MTE3 __khwcap2_feature(MTE3)
#define SMPRI_EL1_PRIORITY_WIDTH 4
#define ID_AA64MMFR3_EL1_D128_SIGNED false
#define HDFGRTR_EL2_OSDLR_EL1_WIDTH 1
#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
#define DEFAULT_PRIO (MAX_RT_PRIO + NICE_WIDTH / 2)
#define DECLARE_COMPLETION_ONSTACK(work) struct completion work = COMPLETION_INITIALIZER_ONSTACK(work)
#define ID_ISAR3_EL1_TrueNOP_IMP UL(0b0001)
#define QC_SPC_WARNS (1<<9)
#define unsafe_op_wrap(op,err) do { if (unlikely(op)) goto err; } while (0)
#define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
#define DCACHE_NFSFS_RENAMED 0x00001000
#define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
#define ID_AA64MMFR3_EL1_S2POE_NI UL(0b0000)
#define static_key_slow_inc(key) static_key_fast_inc_not_disabled(key)
#define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
#define cpu_to_mem(cpu) ((void)(cpu),0)
#define ID_DFR1_EL1_HPMN0_SIGNED false
#define arch_atomic64_sub_return arch_atomic64_sub_return
#define ID_ISAR5_EL1_SHA1_SIGNED false
#define KUNIT_EXPECT_MEMEQ_MSG(test,left,right,size,fmt,...) KUNIT_MEM_ASSERTION(test, KUNIT_EXPECTATION, left, ==, right, size, fmt, ##__VA_ARGS__)
#define ID_AA64MMFR2_EL1_TTL GENMASK(51, 48)
#define KUNIT_CURRENT_LOC { .file = __FILE__, .line = __LINE__ }
#define ID_PFR1_EL1_UNKN (UL(0))
#define __dma_wmb() dmb(oshst)
#define ID_AA64MMFR0_EL1_ECV_WIDTH 4
#define LPA_SGMII_1000HALF 0x0800
#define XCVR_INTERNAL 0x00
#define ID_MMFR4_EL1_EVT GENMASK(31, 28)
#define __GFP_ZEROTAGS ((__force gfp_t)___GFP_ZEROTAGS)
#define _LINUX_SCHED_TASK_H 
#define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
#define VM_STACK_FLAGS (VM_STACK | VM_STACK_DEFAULT_FLAGS | VM_ACCOUNT)
#define ID_MMFR1_EL1_L1UniSW_WIDTH 4
#define ID_PFR1_EL1_Security_SHIFT 4
#define DN_RENAME 0x00000010
#define ID_AA64ZFR0_EL1_SVEver_SVE2 UL(0b0001)
#define TRBMAR_EL1_SH_OUTER_SHAREABLE UL(0b10)
#define ID_AA64PFR0_EL1_AdvSIMD_SIGNED true
#define current get_current()
#define current_cred() rcu_dereference_protected(current->cred, 1)
#define __UAPI_DEF_IPX_ROUTE_DEF 1
#define INIT_THREAD { .fpsimd_cpu = NR_CPUS, }
#define OFFSET_MAX type_max(loff_t)
#define pr_notice_ratelimited(fmt,...) printk_ratelimited(KERN_NOTICE pr_fmt(fmt), ##__VA_ARGS__)
#define SMCR_ELx_LEN GENMASK(3, 0)
#define ID_ISAR6_EL1_SPECRES_IMP UL(0b0001)
#define ID_AA64MMFR0_EL1_BIGENDEL0_SIGNED false
#define __wmb() dsb(st)
#define DACR32_EL2_D4_SHIFT 8
#define ETH_MODULE_SFF_8636_LEN 256
#define HFGITR_EL2_DCCVAP_SHIFT 8
#define HDFGRTR_EL2_TRBMAR_EL1_WIDTH 1
#define __GFP_NOLOCKDEP ((__force gfp_t)___GFP_NOLOCKDEP)
#define TP_STATUS_SEND_REQUEST (1 << 0)
#define MAX_RW_COUNT (INT_MAX & PAGE_MASK)
#define ID_AA64SMFR0_EL1_F16F16_WIDTH 1
#define CONFIG_DMA_DECLARE_COHERENT 1
#define arch_atomic_add_return arch_atomic_add_return
#define MSG_CONFIRM 0x800
#define KERNEL_HWCAP_SVE_EBF16 __khwcap2_feature(SVE_EBF16)
#define HDFGWTR_EL2_nBRBDATA_WIDTH 1
#define BLOCK_SIZE (1<<BLOCK_SIZE_BITS)
#define SPEED_10 10
#define MDIO_PCS_CTRL2_10GBX 0x0001
#define raw_try_cmpxchg128_release(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg128_release((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define __NR3264_fstatfs 44
#define CONFIG_REGMAP_SPI 1
#define VM_BUG_ON_MM(cond,mm) VM_BUG_ON(cond)
#define PTRACE_SYSCALL_INFO_EXIT 2
#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
#define skb_checksum_validate_zero_check(skb,proto,check,compute_pseudo) __skb_checksum_validate(skb, proto, true, true, check, compute_pseudo)
#define xas_for_each_conflict(xas,entry) while ((entry = xas_find_conflict(xas)))
#define SYS_ID_AA64MMFR0_EL1_Op0 3
#define SYS_ID_AA64MMFR0_EL1_Op1 0
#define SYS_ID_AA64MMFR0_EL1_Op2 0
#define ID_DFR0_EL1_CopTrc_WIDTH 4
#define SET_PERSONALITY(ex) ({ clear_thread_flag(TIF_32BIT); current->personality &= ~READ_IMPLIES_EXEC; })
#define ADVERTISED_MII __ETHTOOL_LINK_MODE_LEGACY_MASK(MII)
#define MTE_GRANULES_PER_PAGE (PAGE_SIZE / MTE_GRANULE_SIZE)
#define LED_FUNCTION_SCROLLLOCK "scrolllock"
#define __NR_setuid 146
#define ID_AA64MMFR2_EL1_BBM_SIGNED false
#define PER_CPU_ALIGNED_SECTION "..shared_aligned"
#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
#define pgd_populate(mm,pgd,p4d) do { } while (0)
#define HDFGWTR_EL2_TRBTRG_EL1_MASK GENMASK(56, 56)
#define ID_MMFR2_EL1_UniTLB_WIDTH 4
#define TCR2_EL2_SKL1_SHIFT 8
#define ELF64_R_TYPE(i) ((i) & 0xffffffff)
#define PCPU_BITMAP_BLOCK_SIZE PAGE_SIZE
#define ETHTOOL_SMSGLVL 0x00000008
#define SVCR_ZA_WIDTH 1
#define __LINUX_SIZES_H__ 
#define ID_AA64ISAR0_EL1_AES_PMULL UL(0b0010)
#define SIOCGIFNETMASK 0x891b
#define get_current_state() READ_ONCE(current->__state)
#define ID_AA64MMFR2_EL1_FWB_NI UL(0b0000)
#define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
#define SCTLR_ELx_ENIB (BIT(30))
#define __TLBI_RANGE_PAGES(num,scale) ((unsigned long)((num) + 1) << (5 * (scale) + 1))
#define PRINTK_MAX_SINGLE_HEADER_LEN 2
#define this_cpu_read(pcp) __pcpu_size_call_return(this_cpu_read_, pcp)
#define ID_AA64MMFR1_EL1_XNX_IMP UL(0b0001)
#define ioread16 ioread16
#define __cpu_to_be32s(x) __swab32s((x))
#define PIRx_ELx_Perm10 GENMASK(43, 40)
#define PIRx_ELx_Perm11 GENMASK(47, 44)
#define PIRx_ELx_Perm12 GENMASK(51, 48)
#define PIRx_ELx_Perm13 GENMASK(55, 52)
#define PIRx_ELx_Perm14 GENMASK(59, 56)
#define PIRx_ELx_Perm15 GENMASK(63, 60)
#define random_get_entropy() ((unsigned long)get_cycles())
#define IPV6_MULTICAST_HOPS 18
#define HFGITR_EL2_TLBIRVAE1IS GENMASK(34, 34)
#define SMPRIMAP_EL2_P1_WIDTH 4
#define NETLINK_MAX_COOKIE_LEN 20
#define ID_AA64MMFR3_EL1_ANERR_MASK GENMASK(47, 44)
#define ID_AA64ISAR1_EL1_DGH_IMP UL(0b0001)
#define SCTLR_EL1_TMT0_SHIFT 50
#define MVFR0_EL1_FPRound_MASK GENMASK(31, 28)
#define ID_MMFR4_EL1_CCIDX_SHIFT 24
#define ID_PFR0_EL1_State1_MASK GENMASK(7, 4)
#define BITS_TO_BYTES(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(char))
#define __NR_getegid 177
#define read_thread_flags() read_ti_thread_flags(current_thread_info())
#define PIRx_ELx_Perm3_WIDTH 4
#define PMSCR_EL2_UNKN (UL(0))
#define FS_BTREE_FL 0x00001000
#define ID_ISAR6_EL1_JSCVT GENMASK(3, 0)
#define MDIO_PMA_SPEED_10 0x0040
#define CONFIG_SERIO_SERPORT 1
#define PR_SET_PTRACER_ANY ((unsigned long)-1)
#define RUSAGE_SELF 0
#define BLKBSZGET _IOR(0x12,112,size_t)
#define ID_ISAR0_EL1_Coproc_MRRC2 UL(0b0100)
#define CONFIG_NET_VENDOR_MICROSEMI 1
#define NET_PTR_POISON ((void *)(0x801 + POISON_POINTER_DELTA))
#define HDFGRTR_EL2_PMCNTEN_MASK GENMASK(16, 16)
#define SECCOMP_RET_DATA 0x0000ffffU
#define SYS_ID_ISAR1_EL1_Op0 3
#define SYS_ID_ISAR1_EL1_Op2 1
#define LPA_SGMII_LINK 0x8000
#define xa_unlock(xa) spin_unlock(&(xa)->xa_lock)
#define __UAPI_DEF_IN6_ADDR_ALT 1
#define MDIO_PMD_RXDET_GLOBAL 0x0001
#define ETHTOOL_COALESCE_TX_AGGR_MAX_FRAMES BIT(25)
#define SO_NOFCS 43
#define __NR_pselect6 72
#define PSR_SSBS_BIT 0x00001000
#define CCSIDR_EL1_Associativity GENMASK(12, 3)
#define MDIO_PMA_CTRL2_1000BT 0x000c
#define ID_AA64DFR0_EL1_TraceFilt_WIDTH 4
#define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
#define CONFIG_NET_VENDOR_NVIDIA 1
#define MINSEC 256
#define EM_H8_300 46
#define __NR_fchown 55
#define this_cpu_read_1(pcp) _pcp_protect_return(__percpu_read_8, pcp)
#define this_cpu_read_2(pcp) _pcp_protect_return(__percpu_read_16, pcp)
#define this_cpu_read_4(pcp) _pcp_protect_return(__percpu_read_32, pcp)
#define this_cpu_read_8(pcp) _pcp_protect_return(__percpu_read_64, pcp)
#define ID_AA64PFR0_EL1_DIT_IMP UL(0b0001)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
#define min_t(type,x,y) __careful_cmp(min, (type)(x), (type)(y))
#define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
#define ID_AA64MMFR1_EL1_SpecSEI_MASK GENMASK(27, 24)
#define SIOCGIFMETRIC 0x891d
#define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
#define CONFIG_FS_IOMAP 1
#define EPROBE_DEFER 517
#define __NR_vmsplice 75
#define __NR_epoll_pwait2 441
#define REMOTE_DISTANCE 20
#define si_utime _sifields._sigchld._utime
#define _GP_REGS 33
#define CONFIG_HAVE_PERF_USER_STACK_DUMP 1
#define ASM_BUG_FLAGS(flags) __BUG_ENTRY(flags) brk BUG_BRK_IMM
#define _Q_TAIL_CPU_MASK _Q_SET_MASK(TAIL_CPU)
#define ptdesc_page(pt) (_Generic((pt), const struct ptdesc *: (const struct page *)(pt), struct ptdesc *: (struct page *)(pt)))
#define __pcpu_size_call_return(stem,variable) ({ typeof(variable) pscr_ret__; __verify_pcpu_ptr(&(variable)); switch(sizeof(variable)) { case 1: pscr_ret__ = stem ##1(variable); break; case 2: pscr_ret__ = stem ##2(variable); break; case 4: pscr_ret__ = stem ##4(variable); break; case 8: pscr_ret__ = stem ##8(variable); break; default: __bad_size_call_parameter(); break; } pscr_ret__; })
#define MDIO_STAT2_TXFAULT 0x0800
#define HDFGWTR_EL2_PMSELR_EL0_MASK GENMASK(19, 19)
#define MSG_BATCH 0x40000
#define NETIF_F_GSO_TUNNEL_REMCSUM __NETIF_F(GSO_TUNNEL_REMCSUM)
#define SVE_PT_SVE_FPSR_SIZE sizeof(__u32)
#define TRBTRG_EL1_TRG_SHIFT 0
#define MDIO_PMA_EXTABLE_1000BKX 0x0040
#define ID_AA64MMFR0_EL1_FGT_WIDTH 4
#define MT_S2_FWB_DEVICE_nGnRE 1
#define MDSCR_EL1_TXfull_WIDTH 1
#define __phys_to_virt(x) ((unsigned long)((x) - PHYS_OFFSET) | PAGE_OFFSET)
#define MVFR2_EL1_FPMisc_FP_ROUNDING UL(0b0011)
#define SIOCGSTAMP SIOCGSTAMP_OLD
#define __ASM_RWONCE_H 
#define ARM64_SSBS 62
#define MDIO_AN_C73_1_T_MASK GENMASK(4, 0)
#define PMSFCR_EL1_ST_SHIFT 18
#define MASTER_SLAVE_CFG_SLAVE_FORCE 5
#define CACHELINE_ASSERT_GROUP_MEMBER(TYPE,GROUP,MEMBER) BUILD_BUG_ON(!(offsetof(TYPE, MEMBER) >= offsetofend(TYPE, __cacheline_group_begin__ ##GROUP) && offsetofend(TYPE, MEMBER) <= offsetof(TYPE, __cacheline_group_end__ ##GROUP)))
#define ID_AA64PFR0_EL1_EL0_AARCH32 UL(0b0010)
#define CONFIG_IOMMU_DMA 1
#define ID_DFR0_EL1_MProfDbg_IMP UL(0b0001)
#define CSUM_MANGLED_0 ((__force __sum16)0xffff)
#define EI_DATA 5
#define ID_AA64ISAR1_EL1_DGH_MASK GENMASK(51, 48)
#define PGMAP_ALTMAP_VALID (1 << 0)
#define arch_enter_lazy_mmu_mode() do {} while (0)
#define SCTLR_EL1_EIS GENMASK(22, 22)
#define ISR_EL1_FS GENMASK(9, 9)
#define SCHED_FLAG_UTIL_CLAMP_MIN 0x20
#define ID_AA64SMFR0_EL1_B16F32_IMP UL(0b1)
#define KUNIT_EXPECT_LT(test,left,right) KUNIT_EXPECT_LT_MSG(test, left, right, NULL)
#define DEFAULT_OVERFLOWUID 65534
#define cmpxchg128_local(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg128_local(__ai_ptr, __VA_ARGS__); })
#define BLKIOMIN _IO(0x12,120)
#define PMSIDR_EL1_COUNTSIZE_16_BIT_SAT UL(0b0011)
#define HDFGRTR_EL2_nPMSNEVFR_EL1_MASK GENMASK(62, 62)
#define MVFR0_EL1_FPSqrt_MASK GENMASK(23, 20)
#define ID_PFR0_EL1_State3_WIDTH 4
#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
#define ifr_data ifr_ifru.ifru_data
#define SUPPORTED_FIBRE __ETHTOOL_LINK_MODE_LEGACY_MASK(FIBRE)
#define __NR_process_madvise 440
#define CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE 1
#define MAX_ORDER_NR_PAGES (1 << MAX_ORDER)
#define SYSCTL_NEG_ONE ((void *)&sysctl_vals[11])
#define pmem_wmb() wmb()
#define DACR32_EL2_D13_MASK GENMASK(27, 26)
#define VM_WARN_ON(cond) BUILD_BUG_ON_INVALID(cond)
#define MKDEV(ma,mi) (((ma) << MINORBITS) | (mi))
#define for_each_zone_zonelist_nodemask(zone,z,zlist,highidx,nodemask) for (z = first_zones_zonelist(zlist, highidx, nodemask), zone = zonelist_zone(z); zone; z = next_zones_zonelist(++z, highidx, nodemask), zone = zonelist_zone(z))
#define HFGITR_EL2_TLBIRVAAE1OS_SHIFT 25
#define PCMCIA_DEV_ID_MATCH_ANONYMOUS 0x0400
#define LED_FUNCTION_PLAYER4 "player-4"
#define SIG_UNBLOCK 1
#define NETIF_F_SG __NETIF_F(SG)
#define EI_VERSION 6
#define ARM64_HAS_DCPODP 15
#define for_each_irq_nr(irq) for (irq = 0; irq < nr_irqs; irq++)
#define HFGITR_EL2_TLBIRVAE1OS GENMASK(24, 24)
#define __ASM_GENERIC_FIXMAP_H 
#define PMSICR_EL1_RES0 (UL(0) | GENMASK_ULL(55, 32))
#define HDFGWTR_EL2_TRCCLAIM_MASK GENMASK(36, 36)
#define FS_IMAGIC_FL 0x00002000
#define SCTLR_EL1_TCF_NONE UL(0b00)
#define SCTLR_EL1_I_SHIFT 12
#define PACKET_IGNORE_OUTGOING 23
#define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
#define AUXILIARY_MODULE_PREFIX "auxiliary:"
#define try_cmpxchg_release(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); kcsan_release(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg_release(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define SIOCSIFENCAP 0x8926
#define _LINUX_NSPROXY_H 
#define HCR_TID2 (UL(1) << 17)
#define SYS_SMCR_EL1_Op0 3
#define SYS_SMCR_EL1_Op2 6
#define SHM_HUGE_MASK HUGETLB_FLAG_ENCODE_MASK
#define IOPRIO_HINT_SHIFT IOPRIO_LEVEL_NR_BITS
#define ID_MMFR0_EL1_InnerShr_IGNORED UL(0b1111)
#define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
#define raw_try_cmpxchg(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define ID_AA64PFR1_EL1_SSBS_SIGNED false
#define ID_AA64ISAR0_EL1_SHA1 GENMASK(11, 8)
#define ext2_set_bit_atomic(l,nr,addr) test_and_set_bit_le(nr, addr)
#define ESR_ELx_EC_MAX (0x3F)
#define CONFIG_XARRAY_MULTI 1
#define EL2HLT 51
#define ISR_EL1_IS GENMASK(10, 10)
#define this_cpu_cmpxchg_4(pcp,o,n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
#define ID_DFR0_EL1_PerfMon_IMPDEF UL(0b1111)
#define Elf_Dyn Elf64_Dyn
#define RLIM64_INFINITY (~0ULL)
#define ID_AA64ISAR0_EL1_DP_MASK GENMASK(47, 44)
#define TIF_MTE_ASYNC_FAULT 5
#define HFGITR_EL2_CPPRCTX_MASK GENMASK(50, 50)
#define readl_poll_timeout(addr,val,cond,delay_us,timeout_us) readx_poll_timeout(readl, addr, val, cond, delay_us, timeout_us)
#define ID_AA64ISAR1_EL1_APA_PAuth UL(0b0001)
#define __meminitconst __section(".meminit.rodata")
#define ID_AA64MMFR1_EL1_VH_WIDTH 4
#define I_CLEAR (1 << 6)
#define atomic_dec_and_raw_lock(atomic,lock) __cond_lock(lock, _atomic_dec_and_raw_lock(atomic, lock))
#define SECCOMP_MODE_FILTER 2
#define FS_DQ_IHARD (1<<1)
#define CONFIG_SND_SPI 1
#define __mrs_s(v,r) DEFINE_MRS_S "	mrs_s " v ", " __stringify(r) "\n" UNDEFINE_MRS_S
#define __careful_cmp(op,x,y) __builtin_choose_expr(__is_constexpr((x) - (y)), __cmp(op, x, y), __cmp_once(op, x, y, __UNIQUE_ID(__x), __UNIQUE_ID(__y)))
#define DEF_PRIORITY 12
#define ETHTOOL_COALESCE_USE_CQE (ETHTOOL_COALESCE_USE_CQE_RX | ETHTOOL_COALESCE_USE_CQE_TX)
#define SYS_ID_AA64DFR1_EL1_Op2 1
#define MVFR1_EL1_SIMDSP_SIGNED false
#define CONFIG_ARCH_HAS_SYSCALL_WRAPPER 1
#define arch_atomic64_fetch_sub_release arch_atomic64_fetch_sub_release
#define CONFIG_IPV6 1
#define folio_page_idx(folio,p) ((p) - &(folio)->page)
#define TASK_REPORT_MAX (TASK_REPORT_IDLE << 1)
#define ID_MMFR4_EL1_XNX GENMASK(11, 8)
#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
#define RATE_MATCH_OPEN_LOOP 3
#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
#define DCACHE_NEED_AUTOMOUNT 0x00020000
#define _DEVICE_BUS_H_ 
#define ID_MMFR5_EL1_nTLBPA GENMASK(7, 4)
#define CONFIG_ARM_AMBA 1
#define PTRACE_SET_SYSCALL_USER_DISPATCH_CONFIG 0x4210
#define EINVAL 22
#define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5))
#define SYS_PIRE0_EL12_Op0 3
#define SYS_PIRE0_EL12_Op1 5
#define SYS_PIRE0_EL12_Op2 2
#define DT_VERDEFNUM 0x6ffffffd
#define DECLARE_SWAITQUEUE(name) struct swait_queue name = __SWAITQUEUE_INITIALIZER(name)
#define __ASM_MEMORY_MODEL_H 
#define MVFR1_EL1_FPFtZ_WIDTH 4
#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
#define ARM64_HAS_TLB_RANGE 46
#define CONFIG_PRINTK 1
#define ADJ_OFFSET 0x0001
#define CONFIG_ARCH_HAS_SET_DIRECT_MAP 1
#define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
#define fops_get(fops) (((fops) && try_module_get((fops)->owner) ? (fops) : NULL))
#define BLKALIGNOFF _IO(0x12,122)
#define KERNEL_HWCAP_FLAGM __khwcap_feature(FLAGM)
#define LMI_CCITT 3
#define ID_AA64DFR0_EL1_TraceVer_NI UL(0b0000)
#define CPACR_ELx_ZEN_MASK GENMASK(17, 16)
#define DECLARE_TRACEPOINT(tp) extern struct tracepoint __tracepoint_ ##tp
#define ID_AA64SMFR0_EL1_F16F16_MASK GENMASK(42, 42)
#define PACKET_VNET_HDR 15
#define CONFIG_ARM64_ERRATUM_2645198 1
#define __ASM_INSN_DEF_H 
#define CONFIG_DEBUG_LOCK_ALLOC 1
#define sg_dma_len(sg) ((sg)->dma_length)
#define CONFIG_CRYPTO 1
#define SS_ONSTACK 1
#define EX_TYPE_UACCESS_ERR_ZERO 2
#define __wait_event_interruptible(wq_head,condition) ___wait_event(wq_head, condition, TASK_INTERRUPTIBLE, 0, 0, schedule())
#define no_llseek NULL
#define __wait_event_lock_irq(wq_head,condition,lock,cmd) (void)___wait_event(wq_head, condition, TASK_UNINTERRUPTIBLE, 0, 0, spin_unlock_irq(&lock); cmd; schedule(); spin_lock_irq(&lock))
#define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
#define HDFGWTR_EL2_PMCR_EL0 GENMASK(21, 21)
#define HFGxTR_EL2_AFSR1_EL1 GENMASK(1, 1)
#define __unrcu_pointer(p,local) ({ typeof(*p) *local = (typeof(*p) *__force)(p); rcu_check_sparse(p, __rcu); ((typeof(*p) __force __kernel *)(local)); })
#define list_for_each_rcu(pos,head) for (pos = rcu_dereference((head)->next); !list_is_head(pos, (head)); pos = rcu_dereference(pos->next))
#define plist_for_each_safe(pos,n,head) list_for_each_entry_safe(pos, n, &(head)->node_list, node_list)
#define SYS_TRBBASER_EL1_Op2 2
#define ID_AA64ISAR0_EL1_SHA3_WIDTH 4
#define HDFGWTR_EL2_PMINTEN_SHIFT 17
#define PMSFCR_EL1_FE_SHIFT 0
#define SYS_BIND 2
#define ID_AA64MMFR0_EL1_PARANGE_WIDTH 4
#define DQF_SYS_FILE (1 << DQF_SYS_FILE_B)
#define ID_AA64PFR0_EL1_SVE GENMASK(35, 32)
#define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
#define PID_MAX_LIMIT (CONFIG_BASE_SMALL ? PAGE_SIZE * 8 : (sizeof(long) > 4 ? 4 * 1024 * 1024 : PID_MAX_DEFAULT))
#define ADVERTISED_AUI __ETHTOOL_LINK_MODE_LEGACY_MASK(AUI)
#define REG_HFGWTR_EL2 S3_4_C1_C1_5
#define CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS 1
#define HDFGWTR_EL2_PMBSR_EL1 GENMASK(25, 25)
#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
#define ID_AA64MMFR2_EL1_AT_SHIFT 32
#define F_SEAL_SHRINK 0x0002
#define ICH_HCR_TDIR (1 << 14)
#define flush_pmd_tlb_range(vma,addr,end) BUILD_BUG()
#define SB_DIRSYNC BIT(7)
#define ARM64_HAS_LSE_ATOMICS 34
#define _test_bit_acquire arch_test_bit_acquire
#define INIT_ARCH_ELF_STATE { .flags = 0, }
#define THREADINFO_GFP (GFP_KERNEL_ACCOUNT | __GFP_ZERO)
#define ID_ISAR5_EL1_AES_SHIFT 4
#define __ATTRIBUTE_GROUPS(_name) static const struct attribute_group *_name ##_groups[] = { &_name ##_group, NULL, }
#define ___GFP_ZEROTAGS 0x800000u
#define p4d_addr_end(addr,end) (end)
#define NETLINK_NFLOG 5
#define PMSFCR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 19) | GENMASK_ULL(15, 4))
#define PMSFCR_EL1_RES1 (UL(0))
#define ID_DFR0_EL1_CopTrc_IMP UL(0b0001)
#define INIT_SCS 
#define CONTEXTIDR_ELx_PROCID_SHIFT 0
#define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
#define SZ_32K 0x00008000
#define VM_WARN_ON_ONCE(cond) BUILD_BUG_ON_INVALID(cond)
#define SIPHASH_ALIGNMENT __alignof__(u64)
#define HCR_TACR (UL(1) << 21)
#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
#define _LINUX_TIMEKEEPING_H 
#define __wait_event_interruptible_locked(wq,condition,exclusive,fn) ({ int __ret; DEFINE_WAIT(__wait); if (exclusive) __wait.flags |= WQ_FLAG_EXCLUSIVE; do { __ret = fn(&(wq), &__wait); if (__ret) break; } while (!(condition)); __remove_wait_queue(&(wq), &__wait); __set_current_state(TASK_RUNNING); __ret; })
#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
#define lower_16_bits(n) ((u16)((n) & 0xffff))
#define ID_AA64ZFR0_EL1_AES_IMP UL(0b0001)
#define __NR_set_tid_address 96
#define PORT_MII 0x02
#define init_swait_queue_head(q) do { static struct lock_class_key __key; __init_swait_queue_head((q), #q, &__key); } while (0)
#define MDIO_PMA_10GBR_FSRT_CSR 147
#define __ASM_SYSREG_H 
#define swab32 __swab32
#define MDSCR_EL1_INTdis_WIDTH 2
#define __FINITDATA .previous
#define ETHTOOL_GRXRINGS 0x0000002d
#define _ASM_GENERIC_KMAP_SIZE_H 
#define this_cpu_xchg_1(pcp,val) _pcp_protect_return(xchg_relaxed, pcp, val)
#define MDCCINT_EL1_TX_WIDTH 1
#define MVFR0_EL1_FPShVec_SHIFT 24
#define MDIO_USXGMII_1000 0x0400
#define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
#define HFGITR_EL2_CFPRCTX_WIDTH 1
#define HFGxTR_EL2_TTBR0_EL1_MASK GENMASK(36, 36)
#define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000
#define CONFIG_DMA_NONCOHERENT_MMAP 1
#define AF_MPLS 28
#define ID_AA64PFR0_EL1_AMU_MASK GENMASK(47, 44)
#define ID_ISAR0_EL1_CmpBranch_IMP UL(0b0001)
#define si_addr_lsb _sifields._sigfault._addr_lsb
#define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
#define HDFGWTR_EL2_PMSFCR_EL1_WIDTH 1
#define CONFIG_ARM64_PA_BITS 48
#define readq_relaxed_poll_timeout_atomic(addr,val,cond,delay_us,timeout_us) readx_poll_timeout_atomic(readq_relaxed, addr, val, cond, delay_us, timeout_us)
#define ID_AA64ISAR0_EL1_TS_WIDTH 4
#define SYS_ID_AA64ZFR0_EL1_Op2 4
#define pmd_index pmd_index
#define PF_ROSE AF_ROSE
#define LOREA_EL1_EA_47_16_MASK GENMASK(47, 16)
#define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED)
#define raw_try_cmpxchg64_relaxed(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg64_relaxed((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define IPV6_TLV_ROUTERALERT 5
#define to_phy_led(d) container_of(d, struct phy_led, led_cdev)
#define MVFR1_EL1_SIMDLS_IMP UL(0b0001)
#define LED_FUNCTION_CPU "cpu"
#define CONFIG_OF_FLATTREE 1
#define UMOUNT_UNUSED 0x80000000
#define KMEM_CACHE(__struct,__flags) kmem_cache_create(#__struct, sizeof(struct __struct), __alignof__(struct __struct), (__flags), NULL)
#define ID_ISAR3_EL1_SVC_SHIFT 8
#define ZT_SIG_REGS_SIZE(n) (ZT_SIG_REG_BYTES * n)
#define KERNEL_HWCAP_SVESM4 __khwcap2_feature(SVESM4)
#define CSSELR_EL1_TnD_WIDTH 1
#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
#define QC_INO_COUNT (1<<13)
#define MEI_CL_NAME_SIZE 32
#define STATIC_KEY_TRUE_INIT (struct static_key_true) { .key = STATIC_KEY_INIT_TRUE, }
#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
#define ICH_HCR_TALL1 (1 << 12)
#define pte_set_fixmap_offset(pmd,addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
#define ARM_CPU_IMP_HISI 0x48
#define SA_EXPOSE_TAGBITS 0x00000800
#define __MEMINIT .section ".meminit.text", "ax"
#define CONFIG_SMP 1
#define SCTLR_EL1_TCF_ASYMM UL(0b11)
#define CONFIG_NET_VENDOR_MELLANOX 1
#define S64_MIN ((s64)(-S64_MAX - 1))
#define RLIMIT_NPROC 6
#define ID_AA64ISAR0_EL1_TME_NI UL(0b0000)
#define SCTLR_EL1_ATA0_WIDTH 1
#define readb_relaxed readb_relaxed
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define SIGNAL_STOP_STOPPED 0x00000001
#define HCR_NV2 (UL(1) << 45)
#define EPOLL_PACKED 
#define IPCCALL(version,op) ((version)<<16 | (op))
#define JOBCTL_STOPPED (1UL << JOBCTL_STOPPED_BIT)
#define update_thread_flag(flag,value) update_ti_thread_flag(current_thread_info(), flag, value)
#define early_param_on_off(str_on,str_off,var,config) int var = IS_ENABLED(config); static int __init parse_ ##var ##_on(char *arg) { var = 1; return 0; } early_param(str_on, parse_ ##var ##_on); static int __init parse_ ##var ##_off(char *arg) { var = 0; return 0; } early_param(str_off, parse_ ##var ##_off)
#define SYS_FIELD_PREP_ENUM(reg,field,val) FIELD_PREP(reg ##_ ##field ##_MASK, reg ##_ ##field ##_ ##val)
#define CLIDR_EL1_LoC_WIDTH 3
#define SO_DOMAIN 39
#define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
#define ID_ISAR2_EL1_Mult_SHIFT 12
#define ID_PFR0_EL1_DIT GENMASK(27, 24)
#define TRBLIMITR_EL1_FM_SHIFT 1
#define CONFIG_HAVE_KRETPROBES 1
#define PT_HIOS 0x6fffffff
#define SYS_ID_AA64MMFR2_EL1_CRm 7
#define SYS_ID_AA64MMFR2_EL1_CRn 0
#define ID_AA64MMFR1_EL1_PAN_MASK GENMASK(23, 20)
#define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU
#define _TIF_SECCOMP (1 << TIF_SECCOMP)
#define __NR_inotify_rm_watch 28
#define __smp_store_mb(var,value) do { WRITE_ONCE(var, value); __smp_mb(); } while (0)
#define SCHED_RESET_ON_FORK 0x40000000
#define _LINUX_LIVEPATCH_SCHED_H_ 
#define CAP_SYS_CHROOT 18
#define DCACHE_REFERENCED 0x00000040
#define LED_FUNCTION_MICMUTE "micmute"
#define CLOCKFD_MASK (CPUCLOCK_PERTHREAD_MASK|CPUCLOCK_CLOCK_MASK)
#define wait_event_cmd(wq_head,condition,cmd1,cmd2) do { if (condition) break; __wait_event_cmd(wq_head, condition, cmd1, cmd2); } while (0)
#define ESR_ELx_CM_SHIFT (8)
#define _LINUX_NOSPEC_H 
#define __ARCH_WANT_MEMFD_SECRET 
#define ID_AA64PFR0_EL1_AdvSIMD_NI UL(0b1111)
#define SYS_CONNECT 3
#define SLAB_RECLAIM_ACCOUNT ((slab_flags_t __force)0x00020000U)
#define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
#define CONFIG_DEBUG_RWSEMS 1
#define VM_MTE VM_NONE
#define ID_AA64PFR0_EL1_SVE_SHIFT 32
#define static_branch_dec_cpuslocked(x) static_key_slow_dec_cpuslocked(&(x)->key)
#define NLMSG_OVERRUN 0x4
#define ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
#define DEFINE_STATIC_KEY_TRUE_RO(name) struct static_key_true name __ro_after_init = STATIC_KEY_TRUE_INIT
#define arch_read_unlock(l) queued_read_unlock(l)
#define IPV6_TLV_PADN 1
#define __it(x,op) (x -= sizeof(u ##op))
#define arch_atomic_fetch_and_acquire arch_atomic_fetch_and_acquire
#define OSDTRTX_EL1_DTRTX_MASK GENMASK(31, 0)
#define skb_uarg(SKB) ((struct ubuf_info *)(skb_shinfo(SKB)->destructor_arg))
#define VM_LOCKED_MASK (VM_LOCKED | VM_LOCKONFAULT)
#define HDFGRTR_EL2_TRBBASER_EL1_WIDTH 1
#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001
#define SYS_ID_AA64PFR1_EL1_Op2 1
#define alloc_page(gfp_mask) alloc_pages(gfp_mask, 0)
#define this_cpu_and_4(pcp,val) _pcp_protect(__percpu_andnot_case_32, pcp, ~val)
#define ZCR_ELx_LEN GENMASK(3, 0)
#define ID_MMFR5_EL1_nTLBPA_NI UL(0b0000)
#define this_cpu_and_8(pcp,val) _pcp_protect(__percpu_andnot_case_64, pcp, ~val)
#define HDFGWTR_EL2_OSLAR_EL1_WIDTH 1
#define REG_CNTPOFF_EL2 S3_4_C14_C0_6
#define ID_AA64MMFR0_EL1_TGRAN64_2_TGRAN64 UL(0b0000)
#define __io_virt(x) ((void __force *)(x))
#define UUID_INIT(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) ((uuid_t) {{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, ((b) >> 8) & 0xff, (b) & 0xff, ((c) >> 8) & 0xff, (c) & 0xff, (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
#define ID_AA64ISAR2_EL1_BC_SHIFT 20
#define __HAVE_ARCH_MEMMOVE 
#define __SC_3264(_nr,_32,_64) __SYSCALL(_nr, _64)
#define HUGETLB_FLAG_ENCODE_2MB (21U << HUGETLB_FLAG_ENCODE_SHIFT)
#define REG_ID_ISAR1_EL1 S3_0_C0_C2_1
#define CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ 1
#define readb_poll_timeout_atomic(addr,val,cond,delay_us,timeout_us) readx_poll_timeout_atomic(readb, addr, val, cond, delay_us, timeout_us)
#define SO_SNDBUFFORCE 32
#define __diag_GCC(version,severity,s) __diag_GCC_ ## version(__diag_GCC_ ## severity s)
#define PMSG_ON ((struct pm_message){ .event = PM_EVENT_ON, })
#define MVFR1_EL1_FPDNaN_SIGNED false
#define __round_mask(x,y) ((__typeof__(x))((y)-1))
#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
#define ID_AA64PFR1_EL1_NMI_WIDTH 4
#define MII_CTRL1000 0x09
#define LOGLEVEL_NOTICE 5
#define IN6ADDR_INTERFACELOCAL_ALLROUTERS_INIT { { { 0xff,1,0,0,0,0,0,0,0,0,0,0,0,0,0,2 } } }
#define dma_wmb() do { kcsan_wmb(); __dma_wmb(); } while (0)
#define LOREA_EL1_RES1 (UL(0))
#define ID_AA64ISAR2_EL1_RPRFM_NI UL(0b0000)
#define ID_AA64PFR0_EL1_EL2_WIDTH 4
#define time_is_before_jiffies64(a) time_after64(get_jiffies_64(), a)
#define MDIO_PMA_10T1L_STAT_POLARITY 0x0004
#define ID_AA64PFR1_EL1_GCS_MASK GENMASK(47, 44)
#define _LINUX_DQBLK_V2_H 
#define IPV6_TLV_CALIPSO 7
#define LED_FUNCTION_USB "usb"
#define SYS_ID_ISAR3_EL1_CRm 2
#define SYS_ID_ISAR3_EL1_CRn 0
#define raw_cpu_add_return(pcp,val) __pcpu_size_call_return2(raw_cpu_add_return_, pcp, val)
#define SIGCONT 18
#define PCPF_FREE_HIGH_BATCH BIT(1)
#define SCTLR_EL1_EnRCTX_MASK GENMASK(10, 10)
#define NLM_F_REPLACE 0x100
#define LORSA_EL1_Valid_MASK GENMASK(0, 0)
#define CLONE_NEWTIME 0x00000080
#define SIOCDARP 0x8953
#define NL_SET_ERR_MSG_ATTR_FMT(extack,attr,msg,args...) NL_SET_ERR_MSG_ATTR_POL_FMT(extack, attr, NULL, msg, ##args)
#define CONFIG_DEBUG_WW_MUTEX_SLOWPATH 1
#define Elf_Shdr Elf64_Shdr
#define rename_region(region,newname) do { (region)->name = (newname); } while (0)
#define cond_resched_rwlock_read(lock) ({ __might_resched(__FILE__, __LINE__, PREEMPT_LOCK_RESCHED_OFFSETS); __cond_resched_rwlock_read(lock); })
#define HVC_STUB_ERR 0xbadca11
#define REG_DCZID_EL0 S3_3_C0_C0_7
#define SIGEV_THREAD_ID 4
#define JOBCTL_STOP_DEQUEUED (1UL << JOBCTL_STOP_DEQUEUED_BIT)
#define ETHTOOL_MAX_LANES 8
#define SHT_NULL 0
#define ID_MMFR1_EL1_L1HvdVA_CLEAN_AND_INVALIDATE UL(0b0001)
#define lock_map_release(l) lock_release(l, _THIS_IP_)
#define this_cpu_xchg_8(pcp,val) _pcp_protect_return(xchg_relaxed, pcp, val)
#define net_alert_ratelimited(fmt,...) net_ratelimited_function(pr_alert, fmt, ##__VA_ARGS__)
#define ID_AA64SMFR0_EL1_I8I32 GENMASK(39, 36)
#define CNTPOFF_EL2_PhysicalOffset_SHIFT 0
#define CONFIG_NET_VENDOR_ADI 1
#define ETH_P_LOCALTALK 0x0009
#define HDFGRTR_EL2_PMCCFILTR_EL0_MASK GENMASK(14, 14)
#define __NR_newfstatat __NR3264_fstatat
#define HDFGRTR_EL2_PMSLATFR_EL1_MASK GENMASK(32, 32)
#define MDSCR_EL1_KDE GENMASK(13, 13)
#define PMSIDR_EL1_FORMAT_SHIFT 20
#define DEFINE_RES_DMA(_dma) DEFINE_RES_DMA_NAMED((_dma), NULL)
#define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
#define __mb() dsb(sy)
#define ID_MMFR4_EL1_CnP_SHIFT 12
#define CONFIG_DCACHE_WORD_ACCESS 1
#define MVFR0_EL1_FPShVec_NI UL(0b0000)
#define MVFR1_EL1_FPHP_MASK GENMASK(27, 24)
#define ID_ISAR1_EL1_Jazelle GENMASK(31, 28)
#define ID_MMFR3_EL1_CMemSz_MASK GENMASK(27, 24)
#define MDIO_PMA_LASI_RXALARM 0x0004
#define NETIF_F_GSO_MASK (__NETIF_F_BIT(NETIF_F_GSO_LAST + 1) - __NETIF_F_BIT(NETIF_F_GSO_SHIFT))
#define ETH_P_TRAILER 0x001C
#define GMID_EL1_RES0 (UL(0) | GENMASK_ULL(63, 4))
#define GMID_EL1_RES1 (UL(0))
#define KERN_CONT KERN_SOH "c"
#define ID_AA64PFR1_EL1_SME_SHIFT 24
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
#define SECCOMP_IOCTL_NOTIF_ID_VALID SECCOMP_IOW(2, __u64)
#define register_sysctl(path,table) register_sysctl_sz(path, table, ARRAY_SIZE(table))
#define CONFIG_VIRTIO 1
#define ID_AA64MMFR1_EL1_HCX_IMP UL(0b0001)
#define MT_DEVICE_nGnRnE 3
#define TCP_V6_FLOW 0x05
#define xchg(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_mb(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_xchg(__ai_ptr, __VA_ARGS__); })
#define SUPPORTED_20000baseKR2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseKR2_Full)
#define EI_CLASS 4
#define ID_AA64PFR0_EL1_MPAM_WIDTH 4
#define local_add_unless(l,_a,u) atomic_long_add_unless((&(l)->a), (_a), (u))
#define SYS_ICC_NMIAR1_EL1 sys_reg(3, 0, 12, 9, 5)
#define SCTLR_EL1_nTWE_WIDTH 1
#define HFGxTR_EL2_nPIRE0_EL1_WIDTH 1
#define TRBSR_EL1_DAT_WIDTH 1
#define CALLER_ADDR6 ((unsigned long)ftrace_return_address(6))
#define HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT 52
#define CONFIG_FUNCTION_ALIGNMENT_4B 1
#define ESR_ELx_SME_ISS_SME_DISABLED 0
#define my_cpu_offset __my_cpu_offset
#define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling)
#define EM_FRV 0x5441
#define GUP_PIN_COUNTING_BIAS (1U << 10)
#define JOBCTL_LISTENING_BIT 22
#define SMPRIMAP_EL2_P15_MASK GENMASK(63, 60)
#define MVFR0_EL1_FPSqrt GENMASK(23, 20)
#define WAKE_PHY (1 << 0)
#define __GFP_ACCOUNT ((__force gfp_t)___GFP_ACCOUNT)
#define KERNEL_HWCAP_ILRCPC __khwcap_feature(ILRCPC)
#define DCACHE_WHITEOUT_TYPE 0x00100000
#define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
#define LOCK_WRITE 128
#define ID_AA64MMFR1_EL1_VH_SHIFT 8
#define NT_PPC_DSCR 0x105
#define SO_ATTACH_BPF 50
#define __or(x,y) ___or(x, y)
#define CONFIG_XZ_DEC_BCJ 1
#define ID_AA64MMFR3_EL1_SNERR GENMASK(43, 40)
#define NT_X86_SHSTK 0x204
#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE
#define PG_buddy 0x00000080
#define init_rwsem(sem) do { static struct lock_class_key __key; __init_rwsem((sem), #sem, &__key); } while (0)
#define ID_AA64MMFR1_EL1_TIDCP1 GENMASK(55, 52)
#define __SVE_ZREG_SIZE(vq) ((__u32)(vq) * __SVE_VQ_BYTES)
#define SHT_RELA 4
#define release_region(start,n) __release_region(&ioport_resource, (start), (n))
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define ID_ISAR0_EL1_Debug_WIDTH 4
#define PMBPTR_EL1_RES1 (UL(0))
#define ESR_MAGIC 0x45535201
#define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK
#define _LINUX_THREAD_INFO_H 
#define ID_PFR0_EL1_CSV2 GENMASK(19, 16)
#define ID_AA64PFR1_EL1_PFAR_SIGNED false
#define MDSCR_EL1_RXfull_SHIFT 30
#define WORK_DATA_INIT() ATOMIC_LONG_INIT((unsigned long)WORK_STRUCT_NO_POOL)
#define MDSCR_EL1_INTdis_MASK GENMASK(23, 22)
#define LOCK_MAND 32
#define KUNIT_ASSERT_NE(test,left,right) KUNIT_ASSERT_NE_MSG(test, left, right, NULL)
#define HCRX_EL2_TALLINT_SHIFT 6
#define CT_STATE_MASK (CONTEXT_MAX - 1)
#define PF_IB AF_IB
#define AT_ENTRY 9
#define SCTLR_EL1_TMT_MASK GENMASK(51, 51)
#define FS_XFLAG_HASATTR 0x80000000
#define IOPRIO_BE_NR IOPRIO_NR_LEVELS
#define CONFIG_FHANDLE 1
#define SIOCSIFADDR 0x8916
#define S_IFDIR 0040000
#define SYM_FUNC_START_WEAK_NOALIGN(name) SYM_START(name, SYM_L_WEAK, SYM_A_NONE) bti c ;
#define ID_AA64MMFR1_EL1_LO_MASK GENMASK(19, 16)
#define EBUSY 16
#define HCRX_EL2_CMOW_WIDTH 1
#define TRACE_IOCB_STRINGS { IOCB_HIPRI, "HIPRI" }, { IOCB_DSYNC, "DSYNC" }, { IOCB_SYNC, "SYNC" }, { IOCB_NOWAIT, "NOWAIT" }, { IOCB_APPEND, "APPEND" }, { IOCB_EVENTFD, "EVENTFD"}, { IOCB_DIRECT, "DIRECT" }, { IOCB_WRITE, "WRITE" }, { IOCB_WAITQ, "WAITQ" }, { IOCB_NOIO, "NOIO" }, { IOCB_ALLOC_CACHE, "ALLOC_CACHE" }, { IOCB_DIO_CALLER_COMP, "CALLER_COMP" }
#define F_OFD_SETLK 37
#define XA_MAX_MARKS 3
#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
#define HDFGWTR_EL2_PMEVTYPERn_EL0_WIDTH 1
#define raw_try_cmpxchg_local(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg_local((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define HFGITR_EL2_TLBIRVAAE1IS_MASK GENMASK(35, 35)
#define CONFIG_ARM64_ERRATUM_2441007 1
#define MDSCR_EL1_KDE_WIDTH 1
#define CONFIG_ARM64_ERRATUM_2441009 1
#define SCTLR_EL1_LSMAOE GENMASK(29, 29)
#define O_NDELAY O_NONBLOCK
#define RNDZAPENTCNT _IO( 'R', 0x04 )
#define smp_mb__before_atomic() do { kcsan_mb(); __smp_mb__before_atomic(); } while (0)
#define local_cmpxchg(l,o,n) atomic_long_cmpxchg((&(l)->a), (o), (n))
#define tracepoint_enabled(tp) static_key_false(&(__tracepoint_ ##tp).key)
#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
#define __ASM_GENERIC_CHECKSUM_H 
#define locking_selftest() do { } while (0)
#define MDIO_SPEED_10G 0x0001
#define MDIO_PMA_PMD_BT1 18
#define SOL_NETBEUI 267
#define writel_relaxed writel_relaxed
#define AT_SYMLINK_FOLLOW 0x400
#define console_initcall(fn) ___define_initcall(fn, con, .con_initcall)
#define set_p4d(p4dptr,p4dval) set_pud((pud_t *)(p4dptr), (pud_t) { p4dval })
#define ADVERTISED_40000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseSR4_Full)
#define compat_mode_t compat_mode_t
#define ID_AA64SMFR0_EL1_I16I32_SHIFT 44
#define REG_ID_AA64MMFR1_EL1 S3_0_C0_C7_1
#define PMSFCR_EL1_FE_MASK GENMASK(0, 0)
#define ELF_OSABI ELFOSABI_NONE
#define SYS_FAR_EL1_CRm 0
#define ID_AA64ISAR1_EL1_FCMA_IMP UL(0b0001)
#define ETOOSMALL 525
#define SYS_PMSIDR_EL1_Op1 0
#define SYS_PMSIDR_EL1_Op2 7
#define pm_generic_freeze_noirq NULL
#define __GFP_NOFAIL ((__force gfp_t)___GFP_NOFAIL)
#define ID_ISAR3_EL1_T32Copy_WIDTH 4
#define ID_ISAR5_EL1_SHA2_SHIFT 12
#define ID_AA64ISAR2_EL1_RES0 (UL(0) | GENMASK_ULL(63, 56) | GENMASK_ULL(47, 32))
#define ID_AA64ISAR2_EL1_RES1 (UL(0))
#define SIOCPROTOPRIVATE 0x89E0
#define CONFIG_HAVE_ARCH_STACKLEAK 1
#define ELF32_R_SYM(x) ((x) >> 8)
#define ID_ISAR0_EL1_CmpBranch_SHIFT 12
#define ID_DFR0_EL1_CopDbg_MASK GENMASK(3, 0)
#define pgd_val(x) ((x).pgd)
#define TRFCR_EL2_CX BIT(3)
#define HFGITR_EL2_TLBIVALE1IS GENMASK(32, 32)
#define MVFR2_EL1_SIMDMisc_SIMD_DIRECTED_ROUNDING UL(0b0001)
#define SB_I_VERSION BIT(23)
#define CONFIG_REGMAP 1
#define dma_unmap_single(d,a,s,r) dma_unmap_single_attrs(d, a, s, r, 0)
#define CLIDR_EL1_Ctype2_MASK GENMASK(5, 3)
#define FIXMAP_PAGE_RO PAGE_KERNEL_RO
#define BMAP_IOCTL 1
#define _UAPI_ASM_GENERIC_SIGINFO_H 
#define MASTER_SLAVE_STATE_UNSUPPORTED 0
#define set_cpu_numa_mem(cpu,node) 
#define SECCOMP_NOTIFY_ADDFD_SIZE_LATEST SECCOMP_NOTIFY_ADDFD_SIZE_VER0
#define ID_AA64ISAR1_EL1_GPI_MASK GENMASK(31, 28)
#define __exitused __used
#define ID_MMFR4_EL1_XNX_MASK GENMASK(11, 8)
#define ID_AA64MMFR0_EL1_TGRAN16_2_MASK GENMASK(35, 32)
#define _UAPI__ASM_GENERIC_BITS_PER_LONG 
#define HDFGRTR_EL2_PMBLIMITR_EL1 GENMASK(23, 23)
#define PTRACE_SYSEMU 31
#define KERNEL_HWCAP_HBC __khwcap2_feature(HBC)
#define raw_cpu_generic_add_return(pcp,val) ({ typeof(pcp) *__p = raw_cpu_ptr(&(pcp)); *__p += val; *__p; })
#define MVFR1_EL1_SIMDHP_MASK GENMASK(23, 20)
#define DQUOT_SUSPENDED (1 << _DQUOT_SUSPENDED * MAXQUOTAS)
#define PMBLIMITR_EL1_FM_SHIFT 1
#define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE)
#define PMSCR_EL1_CX_MASK GENMASK(3, 3)
#define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
#define __ASM_PERCPU_H 
#define __wait_event_exclusive_cmd(wq_head,condition,cmd1,cmd2) (void)___wait_event(wq_head, condition, TASK_UNINTERRUPTIBLE, 1, 0, cmd1; schedule(); cmd2)
#define ID_AA64MMFR2_EL1_CnP_WIDTH 4
#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
#define ARCH_TIMER_PHYS_ACCESS 0
#define EROFS 30
#define HDFGWTR_EL2_TRCOSLAR_MASK GENMASK(42, 42)
#define CONFIG_PCI_DOMAINS_GENERIC 1
#define ETH_ZLEN 60
#define xas_lock_irqsave(xas,flags) xa_lock_irqsave((xas)->xa, flags)
#define ID_ISAR5_EL1_SHA1_MASK GENMASK(11, 8)
#define S_IMA (1 << 10)
#define HFGITR_EL2_TLBIVAALE1IS_WIDTH 1
#define CONFIG_NET_VENDOR_AMD 1
#define LPA_SGMII_100HALF 0x0400
#define ARM_CPU_PART_CORTEX_X2 0xD48
#define ETH_RXFH_INDIR_NO_CHANGE 0xffffffff
#define AP_DEVICE_ID_MATCH_QUEUE_TYPE 0x02
#define DECLARE_PHY_INTERFACE_MASK(name) DECLARE_BITMAP(name, PHY_INTERFACE_MODE_MAX)
#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
#define SCTLR_EL1_TSCXT GENMASK(20, 20)
#define BUS_MCEERR_AR 4
#define SYS_PMSNEVFR_EL1_Op0 3
#define SYS_PMSNEVFR_EL1_Op1 0
#define SYS_PMSNEVFR_EL1_Op2 1
#define __GFP_FS ((__force gfp_t)___GFP_FS)
#define I_DIRTY_DATASYNC (1 << 1)
#define ID_AA64ZFR0_EL1_SVEver_SVE2p1 UL(0b0010)
#define SO_BUSY_POLL_BUDGET 70
#define __wait_event_freezable(wq_head,condition) ___wait_event(wq_head, condition, (TASK_INTERRUPTIBLE|TASK_FREEZABLE), 0, 0, schedule())
#define HDFGRTR_EL2_PMCCFILTR_EL0 GENMASK(14, 14)
#define SMCR_ELx_RES0 (UL(0) | GENMASK_ULL(63, 32) | GENMASK_ULL(29, 9))
#define SYS_MVFR0_EL1_CRn 0
#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT 4
#define MTREE_INIT_EXT(name,__flags,__lock) { .ma_external_lock = &(__lock).dep_map, .ma_flags = (__flags), .ma_root = NULL, }
#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
#define COMPAT_HWCAP_IDIV (COMPAT_HWCAP_IDIVA|COMPAT_HWCAP_IDIVT)
#define SYS_HFGRTR_EL2_Op0 3
#define DEFINE_LOCK_GUARD_0(_name,_lock,_unlock,...) __DEFINE_UNLOCK_GUARD(_name, void, _unlock, __VA_ARGS__) __DEFINE_LOCK_GUARD_0(_name, _lock)
#define SYS_HFGRTR_EL2_Op2 4
#define ID_AA64AFR0_EL1_IMPDEF1_MASK GENMASK(7, 4)
#define MDSCR_EL1_TDCC_MASK GENMASK(12, 12)
#define ID_AA64SMFR0_EL1_F32F32_MASK GENMASK(32, 32)
#define GENERIC_HDLC_VERSION 4
#define ID_ISAR4_EL1_WithShifts_LS UL(0b0011)
#define SIOCOUTQNSD 0x894B
#define SIOCADDMULTI 0x8931
#define ELIBACC 79
#define SA_ONESHOT SA_RESETHAND
#define PMSIRR_EL1_INTERVAL GENMASK(31, 8)
#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
#define PR_MPX_ENABLE_MANAGEMENT 43
#define TRBSR_EL1_DAT GENMASK(23, 23)
#define XA_ZERO_ENTRY xa_mk_internal(257)
#define fwnode_call_bool_op(fwnode,op,...) (fwnode_has_op(fwnode, op) ? (fwnode)->ops->op(fwnode, ## __VA_ARGS__) : false)
#define this_cpu_sub_return(pcp,val) this_cpu_add_return(pcp, -(typeof(pcp))(val))
#define MNT_NODIRATIME 0x10
#define ID_PFR1_EL1_GenTimer_MASK GENMASK(19, 16)
#define MDIO_MMD_DTEXS 5
#define DECLARE_PER_CPU_PAGE_ALIGNED(type,name) DECLARE_PER_CPU_SECTION(type, name, "..page_aligned") __aligned(PAGE_SIZE)
#define HUGE_MAX_HSTATE 4
#define ID_AA64PFR0_EL1_CSV3_WIDTH 4
#define PSTATE_Imm_shift CRm_shift
#define __NR_bpf 280
#define CONFIG_DEVMEM 1
#define DEFINE_CTL_TABLE_POLL(name) struct ctl_table_poll name = __CTL_TABLE_POLL_INITIALIZER(name)
#define VM_WARN_ON_ONCE_PAGE(cond,page) BUILD_BUG_ON_INVALID(cond)
#define MDIO_PMA_PMD_BT1_B100_ABLE 0x0001
#define RXH_L4_B_0_1 (1 << 6)
#define IORESOURCE_MEM_TYPE_MASK (3<<3)
#define ID_ISAR4_EL1_Unpriv GENMASK(3, 0)
#define MVFR0_EL1_SIMDReg_MASK GENMASK(3, 0)
#define TRAP_BRANCH 3
#define ID_ISAR4_EL1_Unpriv_NI UL(0b0000)
#define CONFIG_HAVE_REGS_AND_STACK_ACCESS_API 1
#define __ASM_GENERIC_RWONCE_H 
#define ID_AA64MMFR1_EL1_ECBHB_NI UL(0b0000)
#define SSAM_MATCH_FUNCTION 0x4
#define PMSIDR_EL1_FnE_WIDTH 1
#define node_set(node,dst) __node_set((node), &(dst))
#define _LINUX_INIT_H 
#define ID_ISAR4_EL1_WithShifts_NI UL(0b0000)
#define __GFP_IO ((__force gfp_t)___GFP_IO)
#define COND_SYSCALL(name) asmlinkage long __arm64_sys_ ##name(const struct pt_regs *regs); asmlinkage long __weak __arm64_sys_ ##name(const struct pt_regs *regs) { return sys_ni_syscall(); }
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define REG_ICC_NMIAR1_EL1 S3_0_C12_C9_5
#define R_AARCH64_ADR_PREL_LO21 274
#define __diag(s) _Pragma(__diag_str(GCC diagnostic s))
#define QUOTA_NL_BSOFTWARN 6
#define local64_add_negative(i,l) local_add_negative((i), (&(l)->a))
#define PM_EVENT_USER_RESUME (PM_EVENT_USER | PM_EVENT_RESUME)
#define clear_user_page(page,vaddr,pg) clear_page(page)
#define PR_SET_CHILD_SUBREAPER 36
#define HFGITR_EL2_TLBIVALE1OS GENMASK(22, 22)
#define _LINUX_ERROR_INJECTION_H 
#define ID_AA64ISAR2_EL1_RPRFM_SHIFT 48
#define p4d_free_tlb(tlb,x,a) do { } while (0)
#define USB_DEVICE_ID_MATCH_DEV_LO 0x0004
#define num_possible_cpus() cpumask_weight(cpu_possible_mask)
#define NETLINK_AUDIT 9
#define PAC_SET_ENABLED_KEYS(tsk,keys,enabled) ptrauth_set_enabled_keys(tsk, keys, enabled)
#define CONFIG_RTC_LIB 1
#define SKB_DROP_REASON_SUBSYS_SHIFT 16
#define ID_AA64ZFR0_EL1_SVEver_MASK GENMASK(3, 0)
#define SOL_DCCP 269
#define __ASM_GENERIC_POLL_H 
#define BIN_ATTRIBUTE_GROUPS(_name) static const struct attribute_group _name ##_group = { .bin_attrs = _name ##_attrs, }; __ATTRIBUTE_GROUPS(_name)
#define __HEAD .section ".head.text","ax"
#define FT_UNKNOWN 0
#define CONFIG_NET_VENDOR_ARC 1
#define PMSIDR_EL1_FE_SHIFT 0
#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | ESR_ELx_CP15_64_ISS_DIR_READ)
#define SO_TIMESTAMPNS_NEW 64
#define SIOCSIFMAP 0x8971
#define printk_index_subsys_emit(subsys_fmt_prefix,level,fmt,...) __printk_index_emit(fmt, level, subsys_fmt_prefix)
#define HDFGRTR_EL2_TRCAUTHSTATUS GENMASK(34, 34)
#define MAXFREQ_SCALED ((s64)MAXFREQ << NTP_SCALE_SHIFT)
#define SDF_SHARED_CHILD 0x1
#define PF_INET6 AF_INET6
#define __NR_keyctl 219
#define CLONE_SETTLS 0x00080000
#define ADVERTISE_NPAGE 0x8000
#define HFGITR_EL2_SVC_EL1_WIDTH 1
#define si_fd _sifields._sigpoll._fd
#define ID_ISAR2_EL1_MultS GENMASK(19, 16)
#define CONFIG_SND_SOC_PCM3168A_I2C 1
#define __NR_sched_getparam 121
#define SMIDR_EL1_REVISION_WIDTH 8
#define MA_WR_STATE(name,ma_state,wr_entry) struct ma_wr_state name = { .mas = ma_state, .content = NULL, .entry = wr_entry, }
#define TRBMAR_EL1_PAS_WIDTH 2
#define AF_IRDA 23
#define VM_ACCOUNT 0x00100000
#define MMF_HAS_MDWE_NO_INHERIT 29
#define SYSCTL_ONE ((void *)&sysctl_vals[1])
#define ID_AA64PFR0_EL1_GIC_V4P1 UL(0b0010)
#define ID_ISAR1_EL1_Except_AR_MASK GENMASK(11, 8)
#define PR_MDWE_NO_INHERIT (1UL << 1)
#define __cpu_to_le64s(x) do { (void)(x); } while (0)
#define IORESOURCE_DMA_COMPATIBLE (0<<6)
#define PR_SET_SECUREBITS 28
#define FW_INFO "[Firmware Info]: "
#define pm_generic_suspend_noirq NULL
#define lockdep_irq_work_enter(_flags) do { if (!((_flags) & IRQ_WORK_HARD_IRQ)) current->irq_config = 1; } while (0)
#define INIT_SCTLR_EL2_MMU_OFF (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
#define ID_AA64MMFR2_EL1_VARange_SHIFT 16
#define EM_NDS32 167
#define SIOCSIFPFLAGS 0x8934
#define TRBLIMITR_EL1_XE_SHIFT 6
#define SG_MAX_SINGLE_ALLOC (PAGE_SIZE / sizeof(struct scatterlist))
#define MDSCR_EL1_RXO_MASK GENMASK(27, 27)
#define arch_atomic_read(v) __READ_ONCE((v)->counter)
#define si_stime _sifields._sigchld._stime
#define MDIO_AN_T1_STAT 513
#define __RWSEM_OPT_INIT(lockname) .osq = OSQ_LOCK_UNLOCKED,
#define __HAVE_PHYS_MEM_ACCESS_PROT 
#define lockdep_assert_irqs_disabled() do { WARN_ON_ONCE(__lockdep_enabled && this_cpu_read(hardirqs_enabled)); } while (0)
#define SOCK_NONBLOCK O_NONBLOCK
#define AARCH32_BREAK_THUMB 0xde01
#define __ALIGN_STR ".balign " #CONFIG_FUNCTION_ALIGNMENT
#define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12))
#define MDIO_AN_C73_1_25GBASE_R BIT(15)
#define module_param_array(name,type,nump,perm) module_param_array_named(name, name, type, nump, perm)
#define SYS_HCRX_EL2_CRm 2
#define SYS_HCRX_EL2_CRn 1
#define irq_alloc_descs_from(from,cnt,node) irq_alloc_descs(-1, from, cnt, node)
#define NETIF_F_TSO_MANGLEID __NETIF_F(TSO_MANGLEID)
#define module_param_cb_unsafe(name,ops,arg,perm) __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1, KERNEL_PARAM_FL_UNSAFE)
#define __LINUX_SMP_H 
#define IOP_LOOKUP 0x0002
#define ID_AA64ISAR0_EL1_TME_SIGNED false
#define NETIF_F_HIGHDMA __NETIF_F(HIGHDMA)
#define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
#define PHY_ID_FMT "%s:%02x"
#define HFGxTR_EL2_MPIDR_EL1_WIDTH 1
#define __VDSO_PROCESSOR_H 
#define FASYNC_MAGIC 0x4601
#define HDFGRTR_EL2_OSECCR_EL1_MASK GENMASK(10, 10)
#define ID_PFR2_EL1_CSV3_SIGNED false
#define HFGxTR_EL2_SCTLR_EL1_WIDTH 1
#define NR_IRQS 64
#define ID_AA64MMFR2_EL1_NV_NV2 UL(0b0010)
#define tsb_csync() do { if (cpus_have_final_cap(ARM64_WORKAROUND_TSB_FLUSH_FAILURE)) __tsb_csync(); __tsb_csync(); } while (0)
#define get_cpu_ptr(var) ({ preempt_disable(); this_cpu_ptr(var); })
#define next_task(p) list_entry_rcu((p)->tasks.next, struct task_struct, tasks)
#define SMPRIMAP_EL2_P1_MASK GENMASK(7, 4)
#define SIOCSIFMEM 0x8920
#define ID_AA64MMFR1_EL1_LO_IMP UL(0b0001)
#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
#define HFGITR_EL2_TLBIVAE1OS GENMASK(19, 19)
#define MAXSEC 2048
#define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
#define PM_EVENT_SLEEP (PM_EVENT_SUSPEND | PM_EVENT_HIBERNATE)
#define DT_UNKNOWN 0
#define _UAPI__ASM_GENERIC_PARAM_H 
#define ADJ_SETOFFSET 0x0100
#define SVE_PT_SVE_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
#define CONFIG_HAVE_NMI 1
#define node_isset(node,nodemask) test_bit((node), (nodemask).bits)
#define PAGE_END (_PAGE_END(VA_BITS_MIN))
#define __raw_get_mem(ldr,x,ptr,err,type) do { unsigned long __gu_val; switch (sizeof(*(ptr))) { case 1: __get_mem_asm(ldr "b", "%w", __gu_val, (ptr), (err), type); break; case 2: __get_mem_asm(ldr "h", "%w", __gu_val, (ptr), (err), type); break; case 4: __get_mem_asm(ldr, "%w", __gu_val, (ptr), (err), type); break; case 8: __get_mem_asm(ldr, "%x", __gu_val, (ptr), (err), type); break; default: BUILD_BUG(); } (x) = (__force __typeof__(*(ptr)))__gu_val; } while (0)
#define SYS_TRBBASER_EL1_Op0 3
#define SYS_TRBBASER_EL1_Op1 0
#define arch_timer_reg_read_stable(reg) ({ erratum_handler(read_ ## reg)(); })
#define SYS_LOREA_EL1_CRm 4
#define SYS_LOREA_EL1_CRn 10
#define WOL_MODE_COUNT 8
#define folio_start_writeback_keepwrite(folio) __folio_start_writeback(folio, true)
#define IPV6_PRIORITY_10 0x0a00
#define LIST_HEAD(name) struct list_head name = LIST_HEAD_INIT(name)
#define HFGxTR_EL2_AIDR_EL1 GENMASK(2, 2)
#define _LINUX_KMSAN_TYPES_H 
#define ID_AA64PFR0_EL1_EL0 GENMASK(3, 0)
#define ID_AA64PFR0_EL1_EL1 GENMASK(7, 4)
#define ID_AA64PFR0_EL1_EL2 GENMASK(11, 8)
#define ID_AA64PFR0_EL1_EL3 GENMASK(15, 12)
#define CONFIG_HAVE_RSEQ 1
#define TRBIDR_EL1_P_MASK GENMASK(4, 4)
#define ADJ_NANO 0x2000
#define MAY_OPEN 0x00000020
#define MDSCR_EL1_TTA_SHIFT 33
#define _ASM_EXTABLE_UACCESS_ERR(insn,fixup,err) _ASM_EXTABLE_UACCESS_ERR_ZERO(insn, fixup, err, wzr)
#define Op0_shift 19
#define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3
#define rwlock_init(lock) do { static struct lock_class_key __key; __rwlock_init((lock), #lock, &__key); } while (0)
#define CSIGNAL 0x000000ff
#define ESP_V4_FLOW 0x0a
#define __ARCH_HAS_SA_RESTORER 
#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
#define idr_lock_irqsave(idr,flags) xa_lock_irqsave(&(idr)->idr_rt, flags)
#define __NR_semtimedop 192
#define preempt_count_dec_and_test() __preempt_count_dec_and_test()
#define SYS_FIELD_GET(reg,field,val) FIELD_GET(reg ##_ ##field ##_MASK, val)
#define __local_add(i,l) local_set((l), local_read(l) + (i))
#define PHY_EEE_CAP1_FEATURES ((unsigned long *)&phy_eee_cap1_features)
#define CONFIG_I2C_ALGOBIT 1
#define __NR_move_pages 239
#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
#define CONFIG_ARCH_KEEP_MEMBLOCK 1
#define ID_PFR1_EL1_Sec_frac_SHIFT 20
#define CONFIG_ARM64_PA_BITS_48 1
#define ntohl(x) ___ntohl(x)
#define SYS_ALLINT sys_reg(3, 0, 4, 3, 0)
#define copy_to_stopped_child_used_math(child) do { (child)->flags &= ~PF_USED_MATH, (child)->flags |= current->flags & PF_USED_MATH; } while (0)
#define ntohs(x) ___ntohs(x)
#define SVE_PT_SVE_FPCR_SIZE sizeof(__u32)
#define ITER_ALLOW_P2PDMA ((__force iov_iter_extraction_t)0x01)
#define TCR2_EL2_D128_WIDTH 1
#define ETH_P_BPQ 0x08FF
#define readsl readsl
#define VM_USERMAP 0x00000008
#define readsw readsw
#define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
#define ETHTOOL_GET_DUMP_DATA 0x00000040
#define SYS_PMSIRR_EL1_Op0 3
#define SYS_PMSIRR_EL1_Op1 0
#define SYS_PMSIRR_EL1_Op2 3
#define HCRX_EL2_MSCEn GENMASK(11, 11)
#define MDIO_AN_C73_1_100GBASE_CR4 BIT(13)
#define ID_AA64ISAR1_EL1_XS GENMASK(59, 56)
#define __BIN_ATTR(_name,_mode,_read,_write,_size) { .attr = { .name = __stringify(_name), .mode = _mode }, .read = _read, .write = _write, .size = _size, }
#define from_timer(var,callback_timer,timer_fieldname) container_of(callback_timer, typeof(*var), timer_fieldname)
#define S_IRWXU 00700
#define CONFIG_NET_VENDOR_TEHUTI 1
#define SCTLR_EL1_TWEDEn_SHIFT 45
#define ID_ISAR5_EL1_SHA1 GENMASK(11, 8)
#define ID_ISAR5_EL1_SHA2 GENMASK(15, 12)
#define iowrite16 iowrite16
#define Q_SYNC 0x800001
#define hlist_for_each(pos,head) for (pos = (head)->first; pos ; pos = pos->next)
#define FPE_FLTINV 7
#define KUNIT_EXPECT_STRNEQ_MSG(test,left,right,fmt,...) KUNIT_BINARY_STR_ASSERTION(test, KUNIT_EXPECTATION, left, !=, right, fmt, ##__VA_ARGS__)
#define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
#define LORSA_EL1_RES1 (UL(0))
#define PPM_SCALE_INV_SHIFT 19
#define HDFGRTR_EL2_RES0 (UL(0) | GENMASK_ULL(49, 49) | GENMASK_ULL(42, 42) | GENMASK_ULL(39, 38) | GENMASK_ULL(21, 20) | GENMASK_ULL(8, 8))
#define ID_AA64PFR1_EL1_MTE_frac_SHIFT 40
#define SB_SUBMOUNT BIT(26)
#define MMF_OOM_SKIP 21
#define node_set_online(node) node_set_state((node), N_ONLINE)
#define ETHTOOL_COALESCE_USE_CQE_RX BIT(22)
#define LPA_10FULL 0x0040
#define module_param_cb(name,ops,arg,perm) __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1, 0)
#define Q_GETINFO 0x800005
#define __ARG_PLACEHOLDER_1 0,
#define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
#define P_PIDFD 3
#define MII_DCOUNTER 0x12
#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
#define LED_SET_BRIGHTNESS_OFF 6
#define GENMASK(h,l) (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
#define ID_MMFR0_EL1_ShareLvl_SHIFT 12
#define DACR32_EL2_D9_WIDTH 2
#define HFGITR_EL2_DCCVAU_WIDTH 1
#define __ASM_PAGE_DEF_H 
#define MVFR0_EL1_FPTrap_SIGNED false
#define SYS_SCXTNUM_EL1_Op1 0
#define SYS_SCXTNUM_EL1_Op2 7
#define cap_valid(x) ((x) >= 0 && (x) <= CAP_LAST_CAP)
#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
#define SVE_SIG_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
#define ID_ISAR5_EL1_VCMA_SHIFT 28
#define SMPRIMAP_EL2_P7_SHIFT 28
#define ARM64_HAS_GENERIC_AUTH 25
#define access_ok access_ok
#define ID_AA64MMFR0_EL1_PARANGE GENMASK(3, 0)
#define __tlbi_user_level(op,arg,level) do { if (arm64_kernel_unmapped_at_el0()) __tlbi_level(op, (arg | USER_ASID_FLAG), level); } while (0)
#define MDIO_AN_T1_ADV_M_MST 0x0010
#define __ASM_GENERIC_IPCBUF_H 
#define ID_PFR1_EL1_Virt_frac_SHIFT 24
#define COMPAT_HWCAP_ASIMDBF16 (1 << 26)
#define MAY_CHDIR 0x00000040
#define EXPORT_PM_FN_NS_GPL(name,ns) EXPORT_SYMBOL_NS_GPL(name, ns)
#define NET_MAJOR 36
#define _LINUX_RANDOM_H 
#define __NR_uname 160
#define PTRACE_O_TRACECLONE (1 << PTRACE_EVENT_CLONE)
#define CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE 1
#define cond_resched() ({ __might_resched(__FILE__, __LINE__, 0); _cond_resched(); })
#define ETHTOOL_COALESCE_USE_CQE_TX BIT(23)
#define FS_XFLAG_NOATIME 0x00000040
#define __data_id_enumify(ENUM,dummy) LOADING_ ## ENUM,
#define OVERFLOW_STACK_SIZE SZ_4K
#define FMODE_NOREUSE ((__force fmode_t)0x800000)
#define CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN 1
#define ID_AA64PFR1_EL1_MTE_MTE2 UL(0b0010)
#define ID_AA64PFR1_EL1_MTE_MTE3 UL(0b0011)
#define FS_IOC32_SETFLAGS _IOW('f', 2, int)
#define folio_test_type(folio,flag) ((folio->page.page_type & (PAGE_TYPE_BASE | flag)) == PAGE_TYPE_BASE)
#define cpumask_of(cpu) (get_cpu_mask(cpu))
#define ID_MMFR4_EL1_HPDS GENMASK(19, 16)
#define ID_ISAR4_EL1_PSR_M_NI UL(0b0000)
#define IOPRIO_NR_LEVELS (1 << IOPRIO_LEVEL_NR_BITS)
#define pud_val(x) (p4d_val((x).p4d))
#define ACCESS_PRIVATE(p,member) ((p)->member)
#define ID_MMFR4_EL1_HPDS_SHIFT 16
#define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK
#define __NR_readahead 213
#define REG_ID_PFR2_EL1 S3_0_C0_C3_4
#define HFGITR_EL2_TLBIVMALLE1IS_SHIFT 28
#define ID_AA64MMFR1_EL1_TWED_WIDTH 4
#define ID_ISAR4_EL1_Writeback_WIDTH 4
#define TRBSR_EL1_MSS_WIDTH 16
#define lockdep_assert_in_softirq() do { WARN_ON_ONCE(__lockdep_enabled && (!in_softirq() || in_irq() || in_nmi())); } while (0)
#define LAST_CPUPID_WIDTH LAST_CPUPID_SHIFT
#define TRAP_PERF 6
#define get_cycles() arch_timer_read_counter()
#define PMSIDR_EL1_ERND_SHIFT 5
#define SYS_SMCR_EL1_CRm 2
#define __LINUX_PREEMPT_H 
#define HCRX_EL2_GCSEn GENMASK(22, 22)
#define __constant_cpu_to_le16(x) ((__force __le16)(__u16)(x))
#define HFGxTR_EL2_TPIDR_EL0_WIDTH 1
#define PF_IO_WORKER 0x00000010
#define __raw_put_user(x,ptr,err) do { __typeof__(*(ptr)) __user *__rpu_ptr = (ptr); __typeof__(*(ptr)) __rpu_val = (x); __chk_user_ptr(__rpu_ptr); uaccess_ttbr0_enable(); __raw_put_mem("sttr", __rpu_val, __rpu_ptr, err, U); uaccess_ttbr0_disable(); } while (0)
#define SYS_SMCR_EL1_CRn 1
#define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
#define AF_VSOCK 40
#define KERNEL_HWCAP_SME2 __khwcap2_feature(SME2)
#define S_CASEFOLD (1 << 15)
#define nmi_exit() do { instrumentation_begin(); ftrace_nmi_exit(); instrumentation_end(); ct_nmi_exit(); lockdep_hardirq_exit(); __nmi_exit(); } while (0)
#define ID_MMFR3_EL1_PAN_MASK GENMASK(19, 16)
#define GFP_KERNEL (__GFP_RECLAIM | __GFP_IO | __GFP_FS)
#define HFGxTR_EL2_APIBKey_SHIFT 8
#define HDFGWTR_EL2_PMCCNTR_EL0_WIDTH 1
#define printk_ratelimit() __printk_ratelimit(__func__)
#define ID_AA64SMFR0_EL1_I8I32_IMP UL(0b1111)
#define TCR2_EL2_DisCH0 GENMASK(14, 14)
#define TCR2_EL2_DisCH1 GENMASK(15, 15)
#define SEMCTL 3
#define CONFIG_ARCH_HAS_GIGANTIC_PAGE 1
#define SYS_ID_AA64SMFR0_EL1_Op0 3
#define SYS_ID_AA64SMFR0_EL1_Op1 0
#define SYS_ID_AA64SMFR0_EL1_Op2 5
#define LED_FUNCTION_POWER "power"
#define HFGITR_EL2_ICIALLUIS_MASK GENMASK(0, 0)
#define ID_AA64MMFR3_EL1_SNERR_SYNC UL(0b0001)
#define O_NONBLOCK 00004000
#define fs_high2lowgid(gid) ((gid) & ~0xFFFF ? (gid16_t)fs_overflowgid : (gid16_t)(gid))
#define MT_S2_NORMAL 0xf
#define SCHED_FIFO 1
#define insw_p insw_p
#define __PCPU_DUMMY_ATTRS __section(".discard") __attribute__((unused))
#define _BUGVERBOSE_LOCATION(file,line) __BUGVERBOSE_LOCATION(file, line)
#define ID_ISAR3_EL1_T32Copy_NI UL(0b0000)
#define devm_irq_alloc_desc(dev,node) devm_irq_alloc_descs(dev, -1, 1, 1, node)
#define DEVICE_BOOL_ATTR(_name,_mode,_var) struct dev_ext_attribute dev_attr_ ##_name = { __ATTR(_name, _mode, device_show_bool, device_store_bool), &(_var) }
#define SYS_TRBMAR_EL1_CRm 11
#define SYS_TRBMAR_EL1_CRn 9
#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x))
#define IS_REACHABLE(option) __or(IS_BUILTIN(option), __and(IS_MODULE(option), __is_defined(MODULE)))
#define RWF_DSYNC ((__force __kernel_rwf_t)0x00000002)
#define HFGxTR_EL2_AFSR1_EL1_SHIFT 1
#define AF_LOCAL 1
#define init_task_preempt_count(p) do { task_thread_info(p)->preempt_count = FORK_PREEMPT_COUNT; } while (0)
#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
#define minimum_console_loglevel (console_printk[2])
#define flowi_tun_key u.__fl_common.flowic_tun_key
#define SCTLR_EL1_EnALS_SHIFT 56
#define ID_MMFR0_EL1_TCM_MASK GENMASK(19, 16)
#define ID_AA64ISAR0_EL1_SM4_MASK GENMASK(43, 40)
#define MDIO_USXGMII_10GFULL 0x1600
#define SCTLR_EL1_M_WIDTH 1
#define arch_vmap_pud_supported arch_vmap_pud_supported
#define SYS_PMSEVFR_EL1_Op0 3
#define SYS_PMSEVFR_EL1_Op1 0
#define SYS_PMSEVFR_EL1_Op2 5
#define NLM_F_ROOT 0x100
#define PMSCR_EL2_CX_WIDTH 1
#define ID_AA64PFR1_EL1_SSBS GENMASK(7, 4)
#define HFGITR_EL2_TLBIVAAE1OS_SHIFT 21
#define PACKET_ROLLOVER_STATS 21
#define HFGxTR_EL2_APIAKey GENMASK(7, 7)
#define u64_to_user_ptr(x) ( { typecheck(u64, (x)); (void __user *)(uintptr_t)(x); } )
#define TCR2_EL1x_AIE_WIDTH 1
#define CONFIG_CGROUP_CPUACCT 1
#define readsb readsb
#define MDCR_EL2_HPMFZO (UL(1) << 29)
#define MVFR0_EL1_FPSP GENMASK(7, 4)
#define DQ_INODES_B 2
#define CONFIG_HAVE_GENERIC_VDSO 1
#define _LINUX_TRACE_CLOCK_H 
#define TRBIDR_EL1_EA_WIDTH 4
#define __constant_be32_to_cpu(x) ___constant_swab32((__force __u32)(__be32)(x))
#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
#define IS_IMA(inode) ((inode)->i_flags & S_IMA)
#define LPA_SGMII_100 0x0400
#define ID_AA64PFR0_EL1_DIT_NI UL(0b0000)
#define this_cpu_write_1(pcp,val) _pcp_protect(__percpu_write_8, pcp, (unsigned long)val)
#define this_cpu_write_2(pcp,val) _pcp_protect(__percpu_write_16, pcp, (unsigned long)val)
#define NTP_API 4
#define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU
#define AT_HWCAP 16
#define this_cpu_write_8(pcp,val) _pcp_protect(__percpu_write_64, pcp, (unsigned long)val)
#define SB_NOUSER BIT(31)
#define NWAYTEST_LOOPBACK 0x0100
#define ISR_EL1_I_MASK GENMASK(7, 7)
#define DCACHE_AUTODIR_TYPE 0x00300000
#define IPC_SET 1
#define pte_cont_addr_end(addr,end) ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; (__boundary - 1 < (end) - 1) ? __boundary : (end); })
#define FMODE_64BITHASH ((__force fmode_t)0x400)
#define RWF_SUPPORTED (RWF_HIPRI | RWF_DSYNC | RWF_SYNC | RWF_NOWAIT | RWF_APPEND)
#define ID_DFR0_EL1_CopDbg_SHIFT 0
#define bvec_iter_offset(bvec,iter) (mp_bvec_iter_offset((bvec), (iter)) % PAGE_SIZE)
#define GFP_NOFS (__GFP_RECLAIM | __GFP_IO)
#define ID_ISAR2_EL1_Reversal_MASK GENMASK(31, 28)
#define TRBIDR_EL1_EA_NON_DESC UL(0b0000)
#define LPA_SGMII_SPD_MASK 0x0c00
#define __constant_cpu_to_le64(x) ((__force __le64)(__u64)(x))
#define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
#define MDIO_AN_STAT1_PAGE 0x0040
#define SYS_PIR_EL1_CRm 2
#define SYS_PIR_EL1_CRn 10
#define ACC_MODE(x) ("\004\002\006\006"[(x)&O_ACCMODE])
#define __LINUX_LOCKDEP_TYPES_H 
#define PTRACE_O_TRACEFORK (1 << PTRACE_EVENT_FORK)
#define TCR2_EL2_E0POE_WIDTH 1
#define ID_AA64MMFR2_EL1_UNKN (UL(0))
#define CONFIG_WLAN_VENDOR_BROADCOM 1
#define PF_NFC AF_NFC
#define flowi6_l3mdev __fl_common.flowic_l3mdev
#define CAP_CHECKPOINT_RESTORE 40
#define PHY_RST_AFTER_CLK_EN 0x00000002
#define FS_IOC_FSSETXATTR _IOW('X', 32, struct fsxattr)
#define ID_ISAR2_EL1_PSR_AR_WIDTH 4
#define set_cpu_numa_node(cpu,node) 
#define __FPE_DECDIV 10
#define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP
#define ESR_ELx_SSE_SHIFT (21)
#define EM_TI_C6000 140
#define SCTLR_EL1_nTWE_MASK GENMASK(18, 18)
#define HCRX_EL2_CMOW_MASK GENMASK(9, 9)
#define COMPAT_HWCAP2_SB (1 << 5)
#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48
#define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
#define ET_REL 1
#define RLIMIT_RTTIME 15
#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE)
#define PR_SCHED_CORE_SHARE_TO 2
#define ID_MMFR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_MMFR1_EL1_RES1 (UL(0))
#define HFGxTR_EL2_REVIDR_EL1 GENMASK(28, 28)
#define EXEC_PAGESIZE 65536
#define MDSCR_EL1_RXfull_MASK GENMASK(30, 30)
#define DCACHE_MISS_TYPE 0x00000000
#define for_each_sg_dma_page(sglist,dma_iter,dma_nents,pgoffset) for (__sg_page_iter_start(&(dma_iter)->base, sglist, dma_nents, pgoffset); __sg_page_iter_dma_next(dma_iter);)
#define __NR_msync 227
#define DBG_ESR_EVT_BRK 0x6
#define ID_ISAR3_EL1_Saturate_IMP UL(0b0001)
#define HFGxTR_EL2_TTBR0_EL1_SHIFT 36
#define SECCOMP_IOC_MAGIC '!'
#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
#define CONFIG_ARM64 1
#define ESR_ELx_SET_SHIFT (11)
#define USEC_TO_HZ_MUL32 U64_C(0x83126E98)
#define SYS_LORSA_EL1_CRm 4
#define SYS_LORSA_EL1_CRn 10
#define ID_ISAR0_EL1_BitField GENMASK(11, 8)
#define MII_MMD_CTRL 0x0d
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1
#define IPV6_FL_S_EXCL 1
#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
#define CLONE_UNTRACED 0x00800000
#define SYS_SMCR_EL1 sys_reg(3, 0, 1, 2, 6)
#define SYS_SMCR_EL2 sys_reg(3, 4, 1, 2, 6)
#define LOGLEVEL_WARNING 4
#define ID_ISAR4_EL1_Writeback_IMP UL(0b0001)
#define __NR_getcwd 17
#define GFP_NOIO (__GFP_RECLAIM)
#define ID_AA64PFR1_EL1_RNDR_trap_SIGNED false
#define __PHY_H 
#define MAX_PID_NS_LEVEL 32
#define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
#define __ASM_CPUCAPS_H 
#define ID_AA64ZFR0_EL1_AES_SIGNED false
#define ID_MMFR0_EL1_PMSA_NI UL(0b0000)
#define __ASM_GENERIC_QRWLOCK_H 
#define CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE 1
#define ID_AA64PFR1_EL1_SME_WIDTH 4
#define pr_emerg_once(fmt,...) printk_once(KERN_EMERG pr_fmt(fmt), ##__VA_ARGS__)
#define _ASM_GENERIC_BITOPS_BUILTIN_FFS_H_ 
#define FW_BUG "[Firmware Bug]: "
#define ETHTOOL_PHY_GTUNABLE 0x0000004e
#define AF_QIPCRTR 42
#define TRBMAR_EL1_PAS_REALM UL(0b11)
#define ID_DFR0_EL1_MMapTrc GENMASK(19, 16)
#define ID_MMFR1_EL1_L1Uni GENMASK(23, 20)
#define LED_FUNCTION_SD "sd"
#define _CADDR_T 
#define netdev_level_once(level,dev,fmt,...) do { static bool __section(".data.once") __print_once; if (!__print_once) { __print_once = true; netdev_printk(level, dev, fmt, ##__VA_ARGS__); } } while (0)
#define ID_AA64PFR1_EL1_MTE_WIDTH 4
#define CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG 1
#define LED_COLOR_ID_MULTI 8
#define ID_AA64MMFR3_EL1_ANERR_SHIFT 44
#define MDIO_AN_C73_0_C2 BIT(12)
#define HFGxTR_EL2_ERXPFGCTL_EL1_MASK GENMASK(47, 47)
#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
#define CAP_SETPCAP 8
#define CONFIG_RTC_SYSTOHC_DEVICE "rtc0"
#define DCZID_EL0_RES1 (UL(0))
#define KMALLOC_MIN_SIZE (1 << KMALLOC_SHIFT_LOW)
#define register_ftrace_graph(ops) ({ -1; })
#define FAR_EL1_ADDR_SHIFT 0
#define arch_atomic_andnot arch_atomic_andnot
#define COMPAT_SYSCALL_DEFINE3(name,...) COMPAT_SYSCALL_DEFINEx(3, _ ##name, __VA_ARGS__)
#define ID_PFR1_EL1_Virt_frac_MASK GENMASK(27, 24)
#define ID_ISAR2_EL1_Reversal_RBIT UL(0b0010)
#define module_param_array_named(name,array,type,nump,perm) param_check_ ##type(name, &(array)[0]); static const struct kparam_array __param_arr_ ##name = { .max = ARRAY_SIZE(array), .num = nump, .ops = &param_ops_ ##type, .elemsize = sizeof(array[0]), .elem = array }; __module_param_call(MODULE_PARAM_PREFIX, name, &param_array_ops, .arr = &__param_arr_ ##name, perm, -1, 0); __MODULE_PARM_TYPE(name, "array of " #type)
#define read_lock(lock) _raw_read_lock(lock)
#define TIF_SVE_VL_INHERIT 24
#define raw_cpu_read_2(pcp) raw_cpu_generic_read(pcp)
#define SVE_VQ_BYTES __SVE_VQ_BYTES
#define THIS_MODULE ((struct module *)0)
#define F_SETFD 2
#define VM_KASAN 0x00000080
#define dma_unmap_len(PTR,LEN_NAME) ((PTR)->LEN_NAME)
#define VM_BUG_ON_PAGE(cond,page) VM_BUG_ON(cond)
#define FS_DQ_LIMIT_MASK (FS_DQ_ISOFT | FS_DQ_IHARD | FS_DQ_BSOFT | FS_DQ_BHARD | FS_DQ_RTBSOFT | FS_DQ_RTBHARD)
#define ADJ_TICK 0x4000
#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
#define S_ISSOCK(m) (((m) & S_IFMT) == S_IFSOCK)
#define LORID_EL1_LR_MASK GENMASK(7, 0)
#define __PAGETABLE_P4D_FOLDED 1
#define CPU_KILL_ME (1)
#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
#define ID_MMFR1_EL1_L1UniSW_CLEAN_AND_INVALIDATE UL(0b0010)
#define ID_PFR0_EL1_CSV2_SIGNED false
#define SO_PASSPIDFD 76
#define SHT_DYNSYM 11
#define SYS_MDCCINT_EL1_Op0 2
#define SYS_MDCCINT_EL1_Op1 0
#define SYS_MDCCINT_EL1_Op2 0
#define CONFIG_MUTEX_SPIN_ON_OWNER 1
#define KERN_WARNING KERN_SOH "4"
#define ID_DFR1_EL1_MTPMU_IMP UL(0b0001)
#define DEFINE_TIMER(_name,_function) struct timer_list _name = __TIMER_INITIALIZER(_function, 0)
#define CTR_EL0_RES0 (UL(0) | GENMASK_ULL(63, 38) | GENMASK_ULL(30, 30) | GENMASK_ULL(13, 4))
#define CTR_EL0_RES1 (UL(0) | GENMASK_ULL(31, 31))
#define S8_MAX ((s8)(U8_MAX >> 1))
#define WRITE_ONCE(x,val) do { compiletime_assert_rwonce_type(x); __WRITE_ONCE(x, val); } while (0)
#define update_mmu_cache(vma,addr,ptep) update_mmu_cache_range(NULL, vma, addr, ptep, 1)
#define HFGITR_EL2_DCISW_MASK GENMASK(4, 4)
#define ATOMIC_INIT_NOTIFIER_HEAD(name) do { spin_lock_init(&(name)->lock); (name)->head = NULL; } while (0)
#define DEFINE_GUARD(_name,_type,_lock,_unlock) DEFINE_CLASS(_name, _type, _unlock, ({ _lock; _T; }), _type _T)
#define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
#define ID_AA64MMFR1_EL1_XNX_SIGNED false
#define faulthandler_disabled() (pagefault_disabled() || in_atomic())
#define SYS_HDFGRTR_EL2_CRm 1
#define SYS_HDFGRTR_EL2_CRn 3
#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
#define CSSELR_EL1_TnD GENMASK(4, 4)
#define arch_read_trylock(l) queued_read_trylock(l)
#define ETH_P_QINQ1 0x9100
#define P_PID 1
#define ID_AA64ISAR0_EL1_TME_WIDTH 4
#define PHY_INTERRUPT_ENABLED true
#define SS_FLAG_BITS SS_AUTODISARM
#define preempt_check_resched() do { } while (0)
#define CCSIDR2_EL1_NumSets GENMASK(23, 0)
#define _UAPI_LINUX_MEI_UUID_H_ 
#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
#define set_ptes set_ptes
#define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
#define ETH_P_QINQ3 0x9300
#define SMPRIMAP_EL2_P11_SHIFT 44
#define ID_AA64PFR1_EL1_PFAR_MASK GENMASK(63, 60)
#define NOMMU_VMFLAGS (NOMMU_MAP_READ | NOMMU_MAP_WRITE | NOMMU_MAP_EXEC)
#define for_each_evictable_lru(lru) for (lru = 0; lru <= LRU_ACTIVE_FILE; lru++)
#define unreachable() do { annotate_unreachable(); barrier_before_unreachable(); __builtin_unreachable(); } while (0)
#define ICH_VTR_ID_BITS_SHIFT 23
#define arch_vmap_pmd_supported arch_vmap_pmd_supported
#define SHT_NUM 12
#define num_present_cpus() cpumask_weight(cpu_present_mask)
#define _IOC_TYPEBITS 8
#define PF_WQ_WORKER 0x00000020
#define ID_MMFR5_EL1_nTLBPA_MASK GENMASK(7, 4)
#define HFGxTR_EL2_nS2POR_EL1_SHIFT 61
#define node_end_pfn(nid) pgdat_end_pfn(NODE_DATA(nid))
#define SVE_SIG_CONTEXT_SIZE(vq) (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq))
#define HDFGWTR_EL2_PMSWINC_EL0_MASK GENMASK(20, 20)
#define ADVERTISED_Backplane __ETHTOOL_LINK_MODE_LEGACY_MASK(Backplane)
#define __PG_MLOCKED (1UL << PG_mlocked)
#define HFGITR_EL2_nGCSEPP GENMASK(59, 59)
#define irqs_disabled_flags(flags) raw_irqs_disabled_flags(flags)
#define for_each_clear_bitrange_from(b,e,addr,size) for (; (b) = find_next_zero_bit((addr), (size), (b)), (e) = find_next_bit((addr), (size), (b) + 1), (b) < (size); (b) = (e) + 1)
#define SCTLR_EL1_SA0_SHIFT 4
#define EM_MN10300 89
#define HFGITR_EL2_TLBIVAALE1_WIDTH 1
#define HWCAP_FPHP (1 << 9)
#define HDFGRTR_EL2_PMMIR_EL1_WIDTH 1
#define NSIGSEGV 10
#define LEDS_BOOST_OFF 0
#define PMSG_IS_AUTO(msg) (((msg).event & PM_EVENT_AUTO) != 0)
#define IF_IFACE_V24 0x1001
#define CONFIG_NET_VENDOR_ADAPTEC 1
#define CONFIG_ARCH_HAS_STRICT_KERNEL_RWX 1
#define NL_ASSERT_DUMP_CTX_FITS(type_name) BUILD_BUG_ON(sizeof(type_name) > sizeof_field(struct netlink_callback, ctx))
#define DEFINE_DYNAMIC_DEBUG_METADATA(name,fmt) 
#define INIT_SCTLR_EL2_MMU_ON (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
#define __KERN_LEVELS_H__ 
#define nodemask_pr_args(maskp) __nodemask_pr_numnodes(maskp), __nodemask_pr_bits(maskp)
#define hrtimer_resolution (unsigned int)LOW_RES_NSEC
#define _Q_TAIL_MASK (_Q_TAIL_IDX_MASK | _Q_TAIL_CPU_MASK)
#define MIN_KIMG_ALIGN SZ_2M
#define ID_MMFR0_EL1_ShareLvl_WIDTH 4
#define PR_SME_SET_VL_ONEXEC (1 << 18)
#define ID_MMFR3_EL1_BPMaint GENMASK(11, 8)
#define SCTLR_EL1_SA_MASK GENMASK(3, 3)
#define IF_IFACE_V35 0x1000
#define SYS_ID_ISAR0_EL1_Op0 3
#define SYS_ID_ISAR0_EL1_Op1 0
#define SYS_ID_ISAR0_EL1_Op2 0
#define ID_AA64SMFR0_EL1_B16F32 GENMASK(34, 34)
#define _LINUX_TIMER_H 
#define CONFIG_PCI_QUIRKS 1
#define ETH_P_IP 0x0800
#define ID_PFR0_EL1_RAS_RASv1p1 UL(0b0010)
#define le32_to_cpu __le32_to_cpu
#define key_serial(k) 0
#define __NR_prlimit64 261
#define FS_DQ_BSOFT (1<<2)
#define SYM_FUNC_START_LOCAL(name) SYM_START(name, SYM_L_LOCAL, SYM_A_ALIGN) bti c ;
#define SYS_PMBLIMITR_EL1_CRm 10
#define SYS_PMBLIMITR_EL1_CRn 9
#define CONFIG_ARCH_HAS_ELF_RANDOMIZE 1
#define ISR_EL1_IS_WIDTH 1
#define KERN_NOTICE KERN_SOH "5"
#define POLL_PRI 5
#define AT_PHDR 3
#define CONFIG_DRM_PANEL_ORIENTATION_QUIRKS 1
#define DACR32_EL2_D12_SHIFT 24
#define SECCOMP_IOCTL_NOTIF_ADDFD SECCOMP_IOW(3, struct seccomp_notif_addfd)
#define CONFIG_PCP_BATCH_SCALE_MAX 5
#define CONFIG_ZLIB_INFLATE 1
#define ID_AFR0_EL1_IMPDEF0_SHIFT 0
#define SYS_PIR_EL12_Op0 3
#define SYS_PIR_EL12_Op1 5
#define SYS_PIR_EL12_Op2 3
#define SYS_ZCR_EL1_CRm 2
#define SYS_ZCR_EL1_CRn 1
#define CCSIDR2_EL1_NumSets_MASK GENMASK(23, 0)
#define PMBLIMITR_EL1_RES0 (UL(0) | GENMASK_ULL(11, 6) | GENMASK_ULL(4, 3))
#define PMBLIMITR_EL1_RES1 (UL(0))
#define HWTSTAMP_FLAG_BONDED_PHC_INDEX HWTSTAMP_FLAG_BONDED_PHC_INDEX
#define ptrauth_suspend_exit() 
#define ID_ISAR4_EL1_PSR_M GENMASK(27, 24)
#define DACR32_EL2_D1_WIDTH 2
#define FOLIO_PF_NO_TAIL 0
#define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
#define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
#define BCMA_CORE(_manuf,_id,_rev,_class) { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
#define REG_TRBTRG_EL1 S3_0_C9_C11_6
#define IPV6_RECVPKTINFO 49
#define CLIDR_EL1_Ttypen_SHIFT 33
#define SMIDR_EL1_AFFINITY_SHIFT 0
#define __is_signed(x) __builtin_choose_expr(__is_constexpr(is_signed_type(typeof(x))), is_signed_type(typeof(x)), 0)
#define __AMEV_CRm(n,m) (n | ((m & 0x8) >> 3))
#define ID_AA64DFR0_EL1_UNKN (UL(0))
#define CSSELR_EL1_Level_MASK GENMASK(3, 1)
#define SVE_PT_SVE_ZREGS_OFFSET (SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
#define rethook_flush_task(tsk) do { } while (0)
#define SYNC_FILE_RANGE_WAIT_AFTER 4
#define irqs_priority_unmasked(regs) (system_uses_irq_prio_masking() ? (regs)->pmr_save == GIC_PRIO_IRQON : true)
#define PIRx_ELx_Perm1_SHIFT 4
#define SPEED_400000 400000
#define MDIO_CTRL1_LPOWER BMCR_PDOWN
#define arch_atomic_fetch_or arch_atomic_fetch_or
#define PMSIDR_EL1_FT_MASK GENMASK(1, 1)
#define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
#define lock_map_acquire_try(l) lock_acquire_exclusive(l, 0, 1, NULL, _THIS_IP_)
#define dev_emerg_once(dev,fmt,...) dev_level_once(dev_emerg, dev, fmt, ##__VA_ARGS__)
#define ID_ISAR0_EL1_UNKN (UL(0))
#define in_task() (!(preempt_count() & (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_OFFSET)))
#define ESR_ELx_Overlay_SHIFT (6)
#define AARCH64_DBG_REG_BVR 0
#define roundup_pow_of_two(n) ( __builtin_constant_p(n) ? ( ((n) == 1) ? 1 : (1UL << (ilog2((n) - 1) + 1)) ) : __roundup_pow_of_two(n) )
#define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX)
#define GMID_EL1_BS GENMASK(3, 0)
#define Elf_Half Elf64_Half
#define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
#define TRBSR_EL1_EA_MASK GENMASK(18, 18)
#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
#define PM_EVENT_SUSPEND 0x0002
#define ID_AA64DFR0_EL1_CTX_CMPs_WIDTH 4
#define CTR_EL0_IminLine_SHIFT 0
#define __this_cpu_sub_return(pcp,val) __this_cpu_add_return(pcp, -(typeof(pcp))(val))
#define TCR_TG0_SHIFT 14
#define SCHED_CAPACITY_SCALE (1L << SCHED_CAPACITY_SHIFT)
#define ID_ISAR0_EL1_Swap_WIDTH 4
#define SO_ATTACH_REUSEPORT_EBPF 52
#define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
#define _LINUX_KMSAN_H 
#define _LINUX_RCU_SYNC_H_ 
#define S8_MIN ((s8)(-S8_MAX - 1))
#define INPUT_DEVICE_ID_ABS_MAX 0x3f
#define kunit_warn(test,fmt,...) kunit_printk(KERN_WARNING, test, fmt, ##__VA_ARGS__)
#define O_RDONLY 00000000
#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | ESR_ELx_SYS64_ISS_DIR_READ)
#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
#define DACR32_EL2_D6_MASK GENMASK(13, 12)
#define PMBIDR_EL1_ALIGN_SHIFT 0
#define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
#define readsq readsq
#define NT_LOONGARCH_HW_WATCH 0xa06
#define PM_EVENT_THAW 0x0020
#define ID_AA64ISAR0_EL1_DP GENMASK(47, 44)
#define SO_RCVBUFFORCE 33
#define CONFIG_HAVE_FUNCTION_GRAPH_RETVAL 1
#define _Q_TAIL_CPU_BITS (32 - _Q_TAIL_CPU_OFFSET)
#define ifr_flags ifr_ifru.ifru_flags
#define PMSIDR_EL1_INTERVAL_1536 UL(0b0101)
#define ID_ISAR2_EL1_LoadStore_SHIFT 0
#define MVFR0_EL1_FPRound_SHIFT 28
#define PR_SET_VMA_ANON_NAME 0
#define ECONNREFUSED 111
#define SCHED_FIXEDPOINT_SHIFT 10
#define ETHTOOL_PHY_EDPD_DFLT_TX_MSECS 0xffff
#define PMD_TABLE_UXN (_AT(pmdval_t, 1) << 60)
#define __noreturn __attribute__((__noreturn__))
#define RB_CLEAR_NODE(node) ((node)->__rb_parent_color = (unsigned long)(node))
#define MDSCR_EL1_EnSPM_SHIFT 34
#define CONT_PMD_SHIFT (CONFIG_ARM64_CONT_PMD_SHIFT + PMD_SHIFT)
#define __ASM_POSIX_TYPES_H 
#define MVFR1_EL1_SIMDLS_SHIFT 8
#define SEEK_MAX SEEK_HOLE
#define pr_notice(fmt,...) printk(KERN_NOTICE pr_fmt(fmt), ##__VA_ARGS__)
#define wait_event(wq_head,condition) do { might_sleep(); if (condition) break; __wait_event(wq_head, condition); } while (0)
#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
#define ESPIPE 29
#define SOL_CAIF 278
#define TASK_DEAD 0x00000080
#define page_address(page) lowmem_page_address(page)
#define NETLINK_ISCSI 8
#define ID_AA64ZFR0_EL1_AES GENMASK(7, 4)
#define EXPORT_NS_GPL_SIMPLE_DEV_PM_OPS(name,suspend_fn,resume_fn,ns) EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(name, ns) = { SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) }
#define SIGPIPE 13
#define PR_SET_MM_START_DATA 3
#define dmi_device_id dmi_system_id
#define arch_nmi_enter() do { struct nmi_ctx *___ctx; u64 ___hcr; if (!is_kernel_in_hyp_mode()) break; ___ctx = this_cpu_ptr(&nmi_contexts); if (___ctx->cnt) { ___ctx->cnt++; break; } ___hcr = read_sysreg(hcr_el2); if (!(___hcr & HCR_TGE)) { write_sysreg(___hcr | HCR_TGE, hcr_el2); isb(); } barrier(); ___ctx->cnt = 1; barrier(); ___ctx->hcr = ___hcr; } while (0)
#define MDSCR_EL1_MDE_SHIFT 15
#define FMODE_CREATED ((__force fmode_t)0x100000)
#define raw_cmpxchg128_relaxed arch_cmpxchg128
#define si_call_addr _sifields._sigsys._call_addr
#define KLIST_INIT(_name,_get,_put) { .k_lock = __SPIN_LOCK_UNLOCKED(_name.k_lock), .k_list = LIST_HEAD_INIT(_name.k_list), .get = _get, .put = _put, }
#define ELF_ET_DYN_BASE (2 * DEFAULT_MAP_WINDOW_64 / 3)
#define ida_simple_remove(ida,id) ida_free(ida, id)
#define ID_PFR0_EL1_State1_SHIFT 4
#define ID_AA64MMFR0_EL1_TGRAN4_2_IMP UL(0b0010)
#define EFBIG 27
#define CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN 11
#define IPPROTO_NONE 59
#define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
#define MDIO_AN_10GBT_CTRL 32
#define ID_AA64MMFR1_EL1_LO_WIDTH 4
#define ID_ISAR5_EL1_CRC32 GENMASK(19, 16)
#define LPA_100BASE4 0x0200
#define NT_RISCV_CSR 0x900
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#define EM_486 6
#define HFGITR_EL2_TLBIVALE1_WIDTH 1
#define QIF_DQBLKSIZE (1 << QIF_DQBLKSIZE_BITS)
#define CONFIG_VIRTIO_MMIO 1
#define LORSA_EL1_RES0 (UL(0) | GENMASK_ULL(63, 52) | GENMASK_ULL(15, 1))
#define __constant_le64_to_cpu(x) ((__force __u64)(__le64)(x))
#define ID_AA64MMFR0_EL1_SNSMEM_NI UL(0b0000)
#define XA_MARK_0 ((__force xa_mark_t)0U)
#define LOGLEVEL_DEBUG 7
#define PTRACE_O_TRACEEXIT (1 << PTRACE_EVENT_EXIT)
#define SEGV_MAPERR 1
#define ID_AA64ZFR0_EL1_B16B16_SHIFT 24
#define LED_FUNCTION_INDICATOR "indicator"
#define PR_PAC_GET_ENABLED_KEYS 61
#define SME_SET_VL(arg) sme_set_current_vl(arg)
#define ARCH_TIMER_EVT_STREAM_PERIOD_US 100
#define HFGITR_EL2_DVPRCTX GENMASK(49, 49)
#define SEGCBLIST_RCU_CORE BIT(1)
#define MDIO_AN_C73_2_2500BASE_KX BIT(0)
#define ETHTOOL_GSET 0x00000001
#define PF_SNA AF_SNA
#define MDSCR_EL1_SS_WIDTH 1
#define ID_AA64MMFR1_EL1_VMIDBits_MASK GENMASK(7, 4)
#define LPA_1000LOCALRXOK 0x2000
#define SYS_RECV 10
#define ELFMAG0 0x7f
#define ELFMAG1 'E'
#define ELFMAG2 'L'
#define ELFMAG3 'F'
#define PIE_X_O 0x2
#define __initconst_or_module __initconst
#define in_irq() (hardirq_count())
#define HFGITR_EL2_ICIALLU_WIDTH 1
#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
#define IN6ADDR_SITELOCAL_ALLROUTERS_INIT { { { 0xff,5,0,0,0,0,0,0,0,0,0,0,0,0,0,2 } } }
#define DOWNSHIFT_DEV_DEFAULT_COUNT 0xff
#define HFGxTR_EL2_nS2POR_EL1_MASK GENMASK(61, 61)
#define try_cmpxchg128_relaxed(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg128_relaxed(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define ID_AA64ISAR2_EL1_WFxT_IMP UL(0b0010)
#define VM_NO_KHUGEPAGED (VM_SPECIAL | VM_HUGETLB)
#define EM_M32 1
#define VM_SOFTDIRTY 0
#define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
#define F_SETLKW 7
#define STACK_DEPOT_EXTRA_BITS 5
#define SYS_ID_AA64AFR0_EL1_Op1 0
#define HFGITR_EL2_TLBIVAE1_WIDTH 1
#define current_uid() (current_cred_xxx(uid))
#define NT_ARM_PACG_KEYS 0x408
#define DEFINE_PERCPU_RWSEM(name) __DEFINE_PERCPU_RWSEM(name, )
#define ID_ISAR0_EL1_Divide_xDIV_A32 UL(0b0010)
#define __MTE_PREAMBLE ARM64_ASM_PREAMBLE ".arch_extension memtag\n"
#define SYS_PIRE0_EL12 sys_reg(3, 5, 10, 2, 2)
#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
#define HCRX_EL2_EnASR_WIDTH 1
#define ID_MMFR1_EL1_L1TstCln_NOINVALIDATE UL(0b0001)
#define ALLOW_ERROR_INJECTION(fname,_etype) 
#define __CLKSOURCE_ARM_ARCH_TIMER_H 
#define PR_CAP_AMBIENT_LOWER 3
#define S16_MAX ((s16)(U16_MAX >> 1))
#define EHOSTDOWN 112
#define MAX_LFS_FILESIZE ((loff_t)LLONG_MAX)
#define MMF_DUMPABLE_MASK ((1 << MMF_DUMPABLE_BITS) - 1)
#define list_for_each_entry_continue_reverse(pos,head,member) for (pos = list_prev_entry(pos, member); !list_entry_is_head(pos, head, member); pos = list_prev_entry(pos, member))
#define SLAB_CACHE_DMA32 ((slab_flags_t __force)0x00008000U)
#define PTRACE_PEEKMTETAGS 33
#define _PAGE_SHARED (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
#define XA_STATE_ORDER(name,array,index,order) struct xa_state name = __XA_STATE(array, (index >> order) << order, order - (order % XA_CHUNK_SHIFT), (1U << (order % XA_CHUNK_SHIFT)) - 1)
#define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features)
#define RB_TREE_LATCH_H 
#define O_TRUNC 00001000
#define ID_AA64MMFR1_EL1_XNX_WIDTH 4
#define ZONES_PGSHIFT (ZONES_PGOFF * (ZONES_WIDTH != 0))
#define USER_PGTABLES_CEILING 0UL
#define ID_AFR0_EL1_IMPDEF0_MASK GENMASK(3, 0)
#define rcu_assign_pointer(p,v) do { uintptr_t _r_a_p__v = (uintptr_t)(v); rcu_check_sparse(p, __rcu); if (__builtin_constant_p(v) && (_r_a_p__v) == (uintptr_t)NULL) WRITE_ONCE((p), (typeof(p))(_r_a_p__v)); else smp_store_release(&p, RCU_INITIALIZER((typeof(p))_r_a_p__v)); } while (0)
#define KASAN_TAG_PGOFF (LAST_CPUPID_PGOFF - KASAN_TAG_WIDTH)
#define clamp(val,lo,hi) __careful_clamp(val, lo, hi)
#define CONFIG_WLAN_VENDOR_ATH 1
#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
#define HDFGWTR_EL2_UNKN (UL(0))
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
#define __builtin_warning(x,y...) (1)
#define _LINUX_KERNEL_VTIME_H 
#define HFGxTR_EL2_AIDR_EL1_MASK GENMASK(2, 2)
#define THP_FILE_MAPPED ({ BUILD_BUG(); 0; })
#define TLBI_TTL_TG_4K 1
#define AP_DEVICE_ID_MATCH_CARD_TYPE 0x01
#define HDFGRTR_EL2_RES1 (UL(0))
#define ESR_ELx_EC_IABT_CUR (0x21)
#define NETIF_F_GSO_SCTP __NETIF_F(GSO_SCTP)
#define test_thread_flag(flag) test_ti_thread_flag(current_thread_info(), flag)
#define DEFINE_XARRAY_ALLOC(name) DEFINE_XARRAY_FLAGS(name, XA_FLAGS_ALLOC)
#define devres_alloc(release,size,gfp) __devres_alloc_node(release, size, gfp, NUMA_NO_NODE, #release)
#define LSM_SETID_FS 8
#define IORESOURCE_DMA_TYPEA (1<<6)
#define IORESOURCE_DMA_TYPEB (2<<6)
#define IORESOURCE_DMA_TYPEF (3<<6)
#define HFGITR_EL2_TLBIRVAE1_WIDTH 1
#define STATX_ATTR_IMMUTABLE 0x00000010
#define _PAGE_EXECONLY (_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
#define DEVICE_ATTR_RO(_name) struct device_attribute dev_attr_ ##_name = __ATTR_RO(_name)
#define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
#define __NR_reboot 142
#define kcsan_check_read_write(ptr,size) kcsan_check_access(ptr, size, KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_WRITE)
#define MDIO_USXGMII_FULL_DUPLEX 0x1000
#define ENOTCONN 107
#define _UAPI__ASM_SVE_CONTEXT_H 
#define __NR_getpgid 155
#define srcu_dereference_notrace(p,ssp) srcu_dereference_check((p), (ssp), 1)
#define ID_AA64PFR0_EL1_AMU_SHIFT 44
#define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
#define SYS_ID_AA64ZFR0_EL1_CRn 0
#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
#define HDFGWTR_EL2_TRC_MASK GENMASK(33, 33)
#define ID_AA64DFR0_EL1_DebugVer_VHE UL(0b0111)
#define WARN_ON_ONCE(condition) ({ int __ret_warn_on = !!(condition); if (unlikely(__ret_warn_on)) __WARN_FLAGS(BUGFLAG_ONCE | BUGFLAG_TAINT(TAINT_WARN)); unlikely(__ret_warn_on); })
#define _LINUX_UUID_H_ 
#define VM_IOREMAP 0x00000001
#define __softirq_entry __section(".softirqentry.text")
#define KUNIT_ASSERT_GT_MSG(test,left,right,fmt,...) KUNIT_BINARY_INT_ASSERTION(test, KUNIT_ASSERTION, left, >, right, fmt, ##__VA_ARGS__)
#define ID_AA64ISAR0_EL1_ATOMIC_WIDTH 4
#define HDFGRTR_EL2_PMSEVFR_EL1_WIDTH 1
#define CONFIG_GENERIC_ALLOCATOR 1
#define OSECCR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define OSECCR_EL1_RES1 (UL(0))
#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
#define SMPRIMAP_EL2_P10 GENMASK(43, 40)
#define __NR_syscalls 457
#define wake_up_poll(x,m) __wake_up(x, TASK_NORMAL, 1, poll_to_key(m))
#define KRETPROBE_MAX_DATA_SIZE 4096
#define SOCK_BUF_LOCK_MASK (SOCK_SNDBUF_LOCK | SOCK_RCVBUF_LOCK)
#define ZONES_WIDTH ZONES_SHIFT
#define MVFR0_EL1_FPRound_NI UL(0b0000)
#define SYS_SCTLR_EL1_CRn 1
#define __annotate_jump_table 
#define ID_PFR0_EL1_State2_SHIFT 8
#define ELF_R_TYPE(X) ELF64_R_TYPE(X)
#define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
#define SYS_CCSIDR2_EL1_CRm 0
#define SYS_CCSIDR2_EL1_CRn 0
#define DEVICE_ATTR_RW(_name) struct device_attribute dev_attr_ ##_name = __ATTR_RW(_name)
#define SCTLR_EL1_DZE GENMASK(14, 14)
#define SYS_RECVFROM 12
#define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
#define ETHTOOL_SPAUSEPARAM 0x00000013
#define ESR_ELx_EC_DABT_CUR (0x25)
#define for_each_cpu(cpu,mask) for_each_set_bit(cpu, cpumask_bits(mask), small_cpumask_bits)
#define EPFNOSUPPORT 96
#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
#define set_pgd(pgdptr,pgdval) set_p4d((p4d_t *)(pgdptr), (p4d_t) { pgdval })
#define ID_AA64MMFR0_EL1_EXS_IMP UL(0b0001)
#define si_lower _sifields._sigfault._addr_bnd._lower
#define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE
#define ARM_CPU_IMP_BRCM 0x42
#define list_for_each_entry(pos,head,member) for (pos = list_first_entry(head, typeof(*pos), member); !list_entry_is_head(pos, head, member); pos = list_next_entry(pos, member))
#define ID_MMFR1_EL1_L1TstCln_WIDTH 4
#define ARM64_HAS_MOPS 35
#define ID_MMFR3_EL1_CMaintSW GENMASK(7, 4)
#define TRBLIMITR_EL1_nVM GENMASK(5, 5)
#define HFGITR_EL2_ATS1E0R_MASK GENMASK(14, 14)
#define ID_MMFR3_EL1_CMemSz_SHIFT 24
#define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
#define ESR_ELx_EC_MOPS (0x27)
#define GP_REG_BYTES (_GP_REGS * 8)
#define PAGE_S2_MEMATTR(attr,has_fwb) ({ u64 __val; if (has_fwb) __val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr); else __val = PTE_S2_MEMATTR(MT_S2_ ## attr); __val; })
#define TAINT_CRAP 10
#define HDFGWTR_EL2_PMCR_EL0_WIDTH 1
#define KERNEL_HWCAP_ASIMDDP __khwcap_feature(ASIMDDP)
#define pm_generic_resume_noirq NULL
#define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
#define PREEMPT_SHIFT 0
#define SYS_ID_AA64MMFR1_EL1_CRm 7
#define SYS_ID_AA64MMFR1_EL1_CRn 0
#define TASK_WAKING 0x00000200
#define HFGxTR_EL2_nACCDATA_EL1_WIDTH 1
#define PLIST_HEAD(head) struct plist_head head = PLIST_HEAD_INIT(head)
#define IPV6_RECVRTHDR 56
#define DBG_MDSCR_KDE (1 << 13)
#define MDIO_SUPPORTS_C22 1
#define FTR_SIGNED true
#define _SIZE_T 
#define XCVR_DUMMY2 0x03
#define SCTLR_EL1_CMOW_MASK GENMASK(32, 32)
#define TP_STATUS_VLAN_TPID_VALID (1 << 6)
#define get_current_groups() ({ struct group_info *__groups; const struct cred *__cred; __cred = current_cred(); __groups = get_group_info(__cred->group_info); __groups; })
#define CPU_BOOT_STATUS_MASK ((UL(1) << CPU_STUCK_REASON_SHIFT) - 1)
#define mutex_acquire(l,s,t,i) lock_acquire_exclusive(l, s, t, NULL, i)
#define SPEED_40000 40000
#define GFP_ZONES_SHIFT ZONES_SHIFT
#define MDIO_AN_CTRL2 64
#define TRBSR_EL1_MSS2_WIDTH 24
#define ETHTOOL_GRSSH 0x00000046
#define SIGQUEUE_PREALLOC 1
#define HPAGE_PUD_MASK ({ BUILD_BUG(); 0; })
#define ID_AA64MMFR2_EL1_CnP_SIGNED false
#define fl6_icmp_code uli.icmpt.code
#define CONFIG_GENERIC_BUG_RELATIVE_POINTERS 1
#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
#define ID_DFR0_EL1_CopTrc_NI UL(0b0000)
#define MAX_MEMBLOCK_ADDR U64_MAX
#define arch_vmap_pgprot_tagged arch_vmap_pgprot_tagged
#define ELFOSABI_LINUX 3
#define GFP_HIGHUSER_MOVABLE (GFP_HIGHUSER | __GFP_MOVABLE | __GFP_SKIP_KASAN)
#define MDIO_PMA_PMD_BT1_CTRL_STRAP 0x000F
#define ID_MMFR3_EL1_CMaintVA GENMASK(3, 0)
#define FS_DQ_RTBCOUNT (1<<14)
#define __PAGE_ALIGNED_BSS .section ".bss..page_aligned", "aw"
#define ESR_ELx_IL_SHIFT (25)
#define KUNIT_FAIL(test,fmt,...) KUNIT_FAIL_ASSERTION(test, KUNIT_EXPECTATION, fmt, ##__VA_ARGS__)
#define LED_FUNCTION_STANDBY "standby"
#define ID_MMFR3_EL1_MaintBcst_WIDTH 4
#define ESR_ELx_EC_SVC32 (0x11)
#define BLKFRASET _IO(0x12,100)
#define ID_DFR0_EL1_MMapDbg_MASK GENMASK(11, 8)
#define PACKET_COPY_THRESH 7
#define IOCB_FLAG_IOPRIO (1 << 1)
#define SEEK_END 2
#define MDSCR_EL1_EnSPM GENMASK(34, 34)
#define MDSCR_EL1_TFO_WIDTH 1
#define __diag_str(s) __diag_str1(s)
#define ID_AA64PFR1_EL1_BT_NI UL(0b0000)
#define PR_SET_MM_EXE_FILE 13
#define REG_ID_PFR0_EL1 S3_0_C0_C1_0
#define RECLAIM_DISTANCE 30
#define NETIF_F_HW_HSR_DUP __NETIF_F(HW_HSR_DUP)
#define MEI_CL_MODULE_PREFIX "mei:"
#define SYS_ID_ISAR2_EL1_CRm 2
#define SYS_ID_ISAR2_EL1_CRn 0
#define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
#define KASAN_VMALLOC_INIT ((__force kasan_vmalloc_flags_t)0x01u)
#define PIRx_ELx_Perm13_SHIFT 52
#define LED_FUNCTION_DISK_READ "disk-read"
#define CONFIG_GENERIC_NET_UTILS 1
#define PIRx_ELx_Perm3_MASK GENMASK(15, 12)
#define KERNEL_HWCAP_ASIMDHP __khwcap_feature(ASIMDHP)
#define QC_SPC_SOFT (1<<2)
#define ID_AA64ISAR0_EL1_TLB_WIDTH 4
#define ETHTOOL_SRINGPARAM 0x00000011
#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full)
#define CONFIG_I2C_XILINX 1
#define low_wmark_pages(z) (z->_watermark[WMARK_LOW] + z->watermark_boost)
#define _USER_CAP_HEADER_SIZE (sizeof(struct __user_cap_header_struct))
#define ID_AA64ISAR0_EL1_TS GENMASK(55, 52)
#define SIMPLE_DEV_PM_OPS(name,suspend_fn,resume_fn) const struct dev_pm_ops __maybe_unused name = { SET_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) }
#define CONFIG_NET_CORE 1
#define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while (0)
#define SCTLR_EL1_M_MASK GENMASK(0, 0)
#define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
#define MDIO_AN_T1_ADV_M_B10L 0x4000
#define IPV6_AUTOFLOWLABEL 70
#define HFGxTR_EL2_ERRSELR_EL1_MASK GENMASK(41, 41)
#define HDFGRTR_EL2_PMMIR_EL1_MASK GENMASK(22, 22)
#define ID_MMFR0_EL1_ShareLvl_MASK GENMASK(15, 12)
#define SPAN_NR_ENTRIES(vstart,vend,shift) ((((vend) - 1) >> (shift)) - ((vstart) >> (shift)) + 1)
#define SOL_ATALK 258
#define HCR_RW_SHIFT 31
#define __struct_size(p) __builtin_dynamic_object_size(p, 0)
#define ID_AA64PFR1_EL1_MTE_SHIFT 8
#define list_for_each_prev_safe(pos,n,head) for (pos = (head)->prev, n = pos->prev; !list_is_head(pos, (head)); pos = n, n = pos->prev)
#define __ATTR_NULL { .attr = { .name = NULL } }
#define TCR_SH0_SHIFT 12
#define PTRACE_MODE_NOAUDIT 0x04
#define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
#define __UINT32_C(c) c ## U
#define ID_AA64MMFR1_EL1_nTLBPA_SIGNED false
#define TIF_SME 27
#define __LINUX_LOGIC_PIO_H 
#define task_uid(task) (task_cred_xxx((task), uid))
#define ESR_ELx_EC_SVC64 (0x15)
#define HFGITR_EL2_TLBIVAE1IS_MASK GENMASK(29, 29)
#define ID_AA64PFR0_EL1_RME_IMP UL(0b0001)
#define HDFGRTR_EL2_PMOVS_MASK GENMASK(18, 18)
#define CONFIG_GCC11_NO_ARRAY_BOUNDS 1
#define PTRACE_GETREGSET 0x4204
#define CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY 1
#define ID_AA64PFR0_EL1_EL0_SHIFT 0
#define ID_AA64ISAR0_EL1_DP_SIGNED false
#define netdev_emerg_once(dev,fmt,...) netdev_level_once(KERN_EMERG, dev, fmt, ##__VA_ARGS__)
#define CONFIG_THREAD_INFO_IN_TASK 1
#define CONFIG_HAS_IOPORT_MAP 1
#define ID_AA64MMFR2_EL1_EVT_WIDTH 4
#define __LINUX_INSTRUMENTATION_H 
#define INPUT_DEVICE_ID_MATCH_ABSBIT 0x0080
#define XA_MARK_2 ((__force xa_mark_t)2U)
#define SG_MITER_ATOMIC (1 << 0)
#define BRK64_OPCODE_KPROBES_SS (AARCH64_BREAK_MON | (KPROBES_BRK_SS_IMM << 5))
#define ID_MMFR4_EL1_CCIDX_WIDTH 4
#define KUNIT_BINARY_INT_ASSERTION(test,assert_type,left,op,right,fmt,...) KUNIT_BASE_BINARY_ASSERTION(test, kunit_binary_assert, kunit_binary_assert_format, assert_type, left, op, right, fmt, ##__VA_ARGS__)
#define __no_sanitize_thread 
#define RLIMIT_STACK 3
#define KERN_DEBUG KERN_SOH "7"
#define HFGxTR_EL2_CSSELR_EL1_MASK GENMASK(13, 13)
#define ID_ISAR1_EL1_Except_SHIFT 4
#define ID_AA64AFR1_EL1_UNKN (UL(0))
#define IPV6_DONTFRAG 62
#define ETHTOOL_SEEPROM 0x0000000c
#define ASSERT_EXCLUSIVE_WRITER(var) __kcsan_check_access(&(var), sizeof(var), KCSAN_ACCESS_ASSERT)
#define PMSCR_EL1_E1SPE_MASK GENMASK(1, 1)
#define DT_SOCK 12
#define QUOTA_NL_ISOFTLONGWARN 2
#define LORN_EL1_RES0 (UL(0) | GENMASK_ULL(63, 8))
#define LORN_EL1_RES1 (UL(0))
#define ID_AA64MMFR2_EL1_ST_39 UL(0b0000)
#define CONFIG_HAVE_ARCH_KFENCE 1
#define CONFIG_NET_VENDOR_LITEX 1
#define VM_FAULT_SET_HINDEX(x) ((__force vm_fault_t)((x) << 16))
#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
#define DN_MODIFY 0x00000002
#define ID_AA64DFR0_EL1_PMUVer_WIDTH 4
#define AARCH64_BREAK_MON 0xd4200000
#define MVFR2_EL1_SIMDMisc_WIDTH 4
#define MDIO_PCS_CTRL2_TYPE 0x0003
#define ID_AA64MMFR2_EL1_TTL_SIGNED false
#define MVFR0_EL1_FPDP_SIGNED false
#define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name))
#define LOCK_STATE_HELD 1
#define COMPAT_PTRACE_GETREGS 12
#define lockdep_hardirq_threaded() do { current->hardirq_threaded = 1; } while (0)
#define BMSR_ANEGCOMPLETE 0x0020
#define HFGxTR_EL2_nACCDATA_EL1_MASK GENMASK(50, 50)
#define O_NOFOLLOW 0100000
#define __ARCH_WANT_NEW_STAT 
#define BMCR_CTST 0x0080
#define __NR_fchmodat 53
#define ioread64 ioread64
#define HCR_TTLB (UL(1) << 25)
#define EINTR 4
#define DUPLEX_UNKNOWN 0xff
#define NT_FILE 0x46494c45
#define VTCR_EL2_SH0_MASK TCR_SH0_MASK
#define F_SEAL_FUTURE_WRITE 0x0010
#define ID_AA64MMFR3_EL1_S2POE_SIGNED false
#define OPEN_HOW_SIZE_VER0 24
#define ID_MMFR3_EL1_CohWalk_WIDTH 4
#define SVE_VL_MAX __SVE_VL_MAX
#define AF_CAIF 37
#define ID_AA64SMFR0_EL1_B16F32_WIDTH 1
#define I_PINNING_FSCACHE_WB (1 << 18)
#define MII_LPA 0x05
#define POLL_IN 1
#define arch_atomic_add_return_acquire arch_atomic_add_return_acquire
#define _ASM_GENERIC_BITOPS_CONST_HWEIGHT_H_ 
#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
#define xa_lock_irq_nested(xa,subclass) spin_lock_irq_nested(&(xa)->xa_lock, subclass)
#define SET_UID(var,uid) do { (var) = __convert_uid(sizeof(var), (uid)); } while (0)
#define LOREA_EL1_EA_51_48 GENMASK(51, 48)
#define SECCOMP_SET_MODE_STRICT 0
#define ID_ISAR2_EL1_Reversal GENMASK(31, 28)
#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
#define HCRX_EL2_GCSEn_WIDTH 1
#define FS_IOC32_GETFLAGS _IOR('f', 1, int)
#define FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL BIT(1)
#define MDIO_AN_EEE_LPABLE 61
#define LORC_EL1_DS_SHIFT 2
#define ID_AA64ISAR0_EL1_ATOMIC_SIGNED false
#define HAVE_FUNCTION_GRAPH_FP_TEST 
#define ID_AA64MMFR3_EL1_ADERR_WIDTH 4
#define F_SET_FILE_RW_HINT (F_LINUX_SPECIFIC_BASE + 14)
#define ID_AA64ISAR0_EL1_FHM_SIGNED false
#define KASAN_VMALLOC_NONE ((__force kasan_vmalloc_flags_t)0x00u)
#define ICC_NMIAR1_EL1_UNKN (UL(0))
#define IDA_INIT(name) { .xa = XARRAY_INIT(name, IDA_INIT_FLAGS) }
#define S32_C(x) x
#define ETHTOOL_SRXFHINDIR 0x00000039
#define iowrite8 iowrite8
#define CLIDR_EL1_Ctype2_SHIFT 3
#define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
#define MNT_WRITE_HOLD 0x200
#define HFGITR_EL2_TLBIASIDE1_WIDTH 1
#define ID_AA64MMFR3_EL1_S1POE_IMP UL(0b0001)
#define KUNIT_TRUE_MSG_ASSERTION(test,assert_type,condition,fmt,...) KUNIT_UNARY_ASSERTION(test, assert_type, condition, true, fmt, ##__VA_ARGS__)
#define SO_SNDLOWAT 19
#define ID_MMFR3_EL1_BPMaint_NI UL(0b0000)
#define pmd_offset pmd_offset
#define NETIF_F_NETNS_LOCAL __NETIF_F(NETNS_LOCAL)
#define TCR2_EL1x_PIE_WIDTH 1
#define PIRx_ELx_Perm12_SHIFT 48
#define flowi_oif u.__fl_common.flowic_oif
#define __SWP_TYPE_SHIFT 3
#define HDFGRTR_EL2_PMUSERENR_EL0_WIDTH 1
#define __ARCH_SPIN_LOCK_UNLOCKED { { .val = ATOMIC_INIT(0) } }
#define PM_EVENT_USER 0x0100
#define ATOMIC_INIT(i) { (i) }
#define __NR_kexec_load 104
#define ID_MMFR2_EL1_HWAccFlg_NI UL(0b0000)
#define CONFIG_PROC_PAGE_MONITOR 1
#define compat_sp_svc regs[19]
#define LPA_LPACK 0x4000
#define _LINUX_MINMAX_H 
#define MA_TOPIARY(name,tree) struct ma_topiary name = { .head = NULL, .tail = NULL, .mtree = tree, }
#define SUPPORTED_56000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseLR4_Full)
#define __ASM_TIMEX_H 
#define ID_AA64SMFR0_EL1_I16I64_WIDTH 4
#define __bf_shf(x) (__builtin_ffsll(x) - 1)
#define TICK_NSEC ((NSEC_PER_SEC+HZ/2)/HZ)
#define tsk_used_math(p) ((p)->flags & PF_USED_MATH)
#define ID_MMFR5_EL1_nTLBPA_IMP UL(0b0001)
#define CPACR_EL1_FPEN_EL0EN (BIT(21))
#define SO_BINDTOIFINDEX 62
#define INPUT_DEVICE_ID_FF_MAX 0x7f
#define ID_AA64MMFR1_EL1_XNX GENMASK(31, 28)
#define EPOLLRDNORM (__force __poll_t)0x00000040
#define SYS_SCXTNUM_EL1_Op0 3
#define MVFR2_EL1_SIMDMisc_SIMD_MAX_MIN UL(0b0011)
#define LED_FUNCTION_DISK_ERR "disk-err"
#define _ASM_GENERIC_BITOPS_EXT2_ATOMIC_SETBIT_H_ 
#define MDCR_EL2_TTRF (UL(1) << 19)
#define SYS_CONTEXTIDR_EL12_CRm 0
#define MAX_NR_TIERS 4U
#define PER_CPU_SHARED_ALIGNED_SECTION "..shared_aligned"
#define MDIO_AN_C73_1_100GBASE_CR10 BIT(10)
#define MDIO_PMA_10GBT_TXPWR 131
#define VM_NO_GUARD 0x00000040
#define arch_atomic_fetch_or_acquire arch_atomic_fetch_or_acquire
#define ID_PFR2_EL1_SSBS_MASK GENMASK(7, 4)
#define MDIO_PKGID1 14
#define small_cpumask_bits nr_cpu_ids
#define CMSG_FIRSTHDR(msg) __CMSG_FIRSTHDR((msg)->msg_control, (msg)->msg_controllen)
#define __CMSG_FIRSTHDR(ctl,len) ((len) >= sizeof(struct cmsghdr) ? (struct cmsghdr *)(ctl) : (struct cmsghdr *)NULL)
#define WORK_STRUCT_FLAG_MASK ((1ul << WORK_STRUCT_FLAG_BITS) - 1)
#define ADVERTISED_2500baseX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(2500baseX_Full)
#define LED_SUSPENDED BIT(0)
#define WORK_DATA_STATIC_INIT() ATOMIC_LONG_INIT((unsigned long)(WORK_STRUCT_NO_POOL | WORK_STRUCT_STATIC))
#define __NR_shmctl 195
#define CFI_BRK_IMM_BASE 0x8000
#define TCR2_EL2_POE_MASK GENMASK(3, 3)
#define REG_TRBMAR_EL1 S3_0_C9_C11_4
#define USEC_TO_HZ_NUM 1
#define NT_ARM_SVE 0x405
#define RWF_WRITE_LIFE_NOT_SET RWH_WRITE_LIFE_NOT_SET
#define MMF_DUMP_MAPPED_SHARED 5
#define SO_GET_FILTER SO_ATTACH_FILTER
#define __raw_get_user(x,ptr,err) do { __typeof__(*(ptr)) __user *__rgu_ptr = (ptr); __typeof__(x) __rgu_val; __chk_user_ptr(ptr); uaccess_ttbr0_enable(); __raw_get_mem("ldtr", __rgu_val, __rgu_ptr, err, U); uaccess_ttbr0_disable(); (x) = __rgu_val; } while (0)
#define ID_ISAR4_EL1_SynchPrim_frac_IMP UL(0b0011)
#define HFGITR_EL2_TLBIVAAE1_MASK GENMASK(45, 45)
#define cpu_to_be64p __cpu_to_be64p
#define cpu_to_be64s __cpu_to_be64s
#define IFF_ECHO IFF_ECHO
#define ARM64_SME_FA64 56
#define SIOCGMIIREG 0x8948
#define hlist_for_each_entry_continue_rcu(pos,member) for (pos = hlist_entry_safe(rcu_dereference_raw(hlist_next_rcu( &(pos)->member)), typeof(*(pos)), member); pos; pos = hlist_entry_safe(rcu_dereference_raw(hlist_next_rcu( &(pos)->member)), typeof(*(pos)), member))
#define ESR_ELx_EC_FP_ASIMD (0x07)
#define HDFGRTR_EL2_TRC GENMASK(33, 33)
#define ETHTOOL_GSG 0x00000018
#define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
#define FS_EXTENT_FL 0x00080000
#define NT_S390_LAST_BREAK 0x306
#define pud_offset_kimg(dir,addr) ((pud_t *)dir)
#define ID_MMFR4_EL1_SpecSEI_WIDTH 4
#define ___swait_event(wq,condition,state,ret,cmd) ({ __label__ __out; struct swait_queue __wait; long __ret = ret; INIT_LIST_HEAD(&__wait.task_list); for (;;) { long __int = prepare_to_swait_event(&wq, &__wait, state); if (condition) break; if (___wait_is_interruptible(state) && __int) { __ret = __int; goto __out; } cmd; } finish_swait(&wq, &__wait); __out: __ret; })
#define arch_atomic_add_return_release arch_atomic_add_return_release
#define __NR_setrlimit 164
#define LORID_EL1_LD_WIDTH 8
#define sync_try_cmpxchg(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_mb(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_sync_try_cmpxchg(__ai_ptr, __VA_ARGS__); })
#define HDFGWTR_EL2_TRCSEQSTR_MASK GENMASK(45, 45)
#define ID_AA64ZFR0_EL1_BF16_WIDTH 4
#define HCR_TWE (UL(1) << 14)
#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
#define __set_bit(nr,addr) bitop(___set_bit, nr, addr)
#define topology_book_cpumask(cpu) cpumask_of(cpu)
#define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
#define IPV6_PRIORITY_8 0x0800
#define __BIN_ATTR_NULL __ATTR_NULL
#define SECCOMP_USER_NOTIF_FLAG_CONTINUE (1UL << 0)
#define _ASM_ARM64_VMALLOC_H 
#define seqcount_rwlock_init(s,lock) seqcount_LOCKNAME_init(s, lock, rwlock)
#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
#define va_end(v) __builtin_va_end(v)
#define KUNIT_SUBSUBTEST_INDENT "        "
#define MDIO_MODULE_PREFIX "mdio:"
#define MDIO_AN_C73_0_ACK BIT(14)
#define DT_ENCODING 32
#define FS_IOC_FIEMAP _IOWR('f', 11, struct fiemap)
#define BCMA_ANY_CLASS 0xFF
#define SMCR_ELx_LEN_WIDTH 4
#define _LINUX_ALARMTIMER_H 
#define SPI_NAME_SIZE 32
#define LORSA_EL1_SA_MASK GENMASK(51, 16)
#define SVE_VL_MIN __SVE_VL_MIN
#define HFGITR_EL2_TLBIVMALLE1_SHIFT 42
#define HDFGRTR_EL2_TRBIDR_EL1_SHIFT 51
#define printk_deferred_enter __printk_safe_enter
#define PR_ENDIAN_BIG 0
#define ID_AA64ISAR1_EL1_FCMA GENMASK(19, 16)
#define LOCKDEP_OFF (1U << LOCKDEP_RECURSION_BITS)
#define IOPRIO_PRIO_HINT(ioprio) (((ioprio) >> IOPRIO_HINT_SHIFT) & IOPRIO_HINT_MASK)
#define PR_PAC_APDBKEY (1UL << 3)
#define ID_AA64MMFR1_EL1_nTLBPA GENMASK(51, 48)
#define CONFIG_SPARSE_IRQ 1
#define raw_cpu_generic_xchg(pcp,nval) ({ typeof(pcp) *__p = raw_cpu_ptr(&(pcp)); typeof(pcp) __ret; __ret = *__p; *__p = nval; __ret; })
#define ELIBBAD 80
#define __LINUX_MDIO_H__ 
#define PIRx_ELx_Perm9_MASK GENMASK(39, 36)
#define CAP_CHOWN 0
#define HFGxTR_EL2_TCR_EL1_WIDTH 1
#define late_param_cb(name,ops,arg,perm) __level_param_cb(name, ops, arg, perm, 7)
#define _LINUX_LOCAL_LOCK_H 
#define HFGITR_EL2_TLBIRVAAE1_MASK GENMASK(39, 39)
#define PTRACE_ATTACH 16
#define PF_INET AF_INET
#define JOBCTL_STOP_PENDING (1UL << JOBCTL_STOP_PENDING_BIT)
#define pr_crit_ratelimited(fmt,...) printk_ratelimited(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__)
#define ID_ISAR3_EL1_SIMD_NI UL(0b0000)
#define CONFIG_XZ_DEC_ARM 1
#define PTRACE_SECCOMP_GET_FILTER 0x420c
#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | ESR_ELx_CP15_64_ISS_DIR_READ)
#define __ASM_PARAM_H 
#define INPUT_DEVICE_ID_MATCH_VENDOR 2
#define ETH_P_AARP 0x80F3
#define __INITRODATA .section ".init.rodata","a",%progbits
#define IRQF_MODIFY_MASK (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
#define __NR_setreuid 145
#define COMPAT_MINSIGSTKSZ MINSIGSTKSZ
#define ARM_CPU_IMP_AMPERE 0xC0
#define MVFR1_EL1_FPDNaN GENMASK(7, 4)
#define PR_GET_NAME 16
#define CONFIG_RTC_I2C_AND_SPI 1
#define _UAPI__ASM_SIGCONTEXT_H 
#define MNT_UNBINDABLE 0x2000
#define KERNEL_HWCAP_FRINT __khwcap2_feature(FRINT)
#define ID_MMFR1_EL1_L1Uni_SHIFT 20
#define DCACHE_DENTRY_KILLED 0x00008000
#define PMSICR_EL1_COUNT_MASK GENMASK(31, 0)
#define SO_ZEROCOPY 60
#define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
#define NETLINK_GENERIC 16
#define DT_MAX (S_DT_MASK + 1)
#define HFGITR_EL2_TLBIVAALE1OS_WIDTH 1
#define __ASM_BITSPERLONG_H 
#define TRBLIMITR_EL1_E_SHIFT 0
#define __NR_getsockopt 209
#define CONFIG_ARCH_HAS_KEEPINITRD 1
#define DEFINE_RES_IO_NAMED(_start,_size,_name) DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_IO)
#define SCTLR_EL1_TCF_SHIFT 40
#define DEVICE_ZONE(xx) 
#define ETH_P_CFM 0x8902
#define ARM64_ELF_BTI (1 << 0)
#define CONFIG_CC_HAS_ASM_INLINE 1
#define HFGxTR_EL2_PAR_EL1 GENMASK(27, 27)
#define ID_PFR0_EL1_State2_NI UL(0b0000)
#define mt_on_stack(mt) (mt).ma_external_lock = NULL
#define raw_spin_unlock_irqrestore(lock,flags) do { typecheck(unsigned long, flags); _raw_spin_unlock_irqrestore(lock, flags); } while (0)
#define ffs(x) __builtin_ffs(x)
#define INIT_SCTLR_EL1_MMU_OFF (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
#define ffz(x) __ffs(~(x))
#define SYSCALL_DISPATCH_FILTER_ALLOW 0
#define LED_BLINK_DISABLE 5
#define _LINUX_NS_COMMON_H 
#define PRINTK_INFO_DEVICE_LEN 48
#define SIG_IGN ((__force __sighandler_t)1)
#define ADVERTISED_TP __ETHTOOL_LINK_MODE_LEGACY_MASK(TP)
#define __NR_nanosleep 101
#define SCTLR_EL1_TMT_WIDTH 1
#define DEFINE_STATIC_PERCPU_RWSEM(name) __DEFINE_PERCPU_RWSEM(name, static)
#define HDFGRTR_EL2_TRCAUTHSTATUS_MASK GENMASK(34, 34)
#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
#define HPAGE_PMD_MASK ({ BUILD_BUG(); 0; })
#define MDIO_PMA_NG_EXTABLE 21
#define SYS_SMPRI_EL1_Op1 0
#define __MEMINITDATA .section ".meminit.data", "aw"
#define NT_PPC_PMU 0x107
#define ID_AA64ZFR0_EL1_BF16_NI UL(0b0000)
#define iter_iov_len(iter) (iter_iov(iter)->iov_len - (iter)->iov_offset)
#define EEXIST 17
#define Op0_mask 0x3
#define TAINT_LIVEPATCH 15
#define ID_AA64ZFR0_EL1_F32MM_NI UL(0b0000)
#define ETHTOOL_SUFO 0x00000022
#define QTYPE_MASK_USR (1 << USRQUOTA)
#define ID_AA64DFR0_EL1_TraceFilt_SIGNED false
#define PF_NETROM AF_NETROM
#define __BUG_FLAGS(flags) asm volatile (__stringify(ASM_BUG_FLAGS(flags)));
#define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
#define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
#define local64_sub_return(i,l) local_sub_return((i), (&(l)->a))
#define ID_AA64MMFR3_EL1_S2PIE_NI UL(0b0000)
#define DT_LNK 10
#define EX_TYPE_NONE 0
#define ETHTOOL_COALESCE_RX_MAX_FRAMES_HIGH BIT(18)
#define ID_MMFR0_EL1_OuterShr_IGNORED UL(0b1111)
#define HDFGRTR_EL2_TRC_MASK GENMASK(33, 33)
#define __kcsan_scoped_name(c,suffix) __kcsan_scoped_ ##c ##suffix
#define SYS_ALLINT_Op0 3
#define PMSG_RESUME ((struct pm_message){ .event = PM_EVENT_RESUME, })
#define CONFIG_NETDEVICES 1
#define ARM64_CB_SHIFT 15
#define __ARCH_SI_BAND_T long
#define ID_ISAR3_EL1_TabBranch_MASK GENMASK(19, 16)
#define CONFIG_ARCH_INLINE_READ_LOCK_IRQ 1
#define KUNIT_ASSERT_PTR_EQ(test,left,right) KUNIT_ASSERT_PTR_EQ_MSG(test, left, right, NULL)
#define MDIO_PMD_TXDIS_3 0x0010
#define KERNEL_HWCAP_SME_B16F32 __khwcap2_feature(SME_B16F32)
#define MDCCINT_EL1_RX_WIDTH 1
#define CONFIG_SSB_POSSIBLE 1
#define CONFIG_BASE_SMALL 0
#define HRTIMER_STATE_ENQUEUED 0x01
#define SB_NODIRATIME BIT(11)
#define ID_ISAR2_EL1_MultS_NI UL(0b0000)
#define get_random_once(buf,nbytes) DO_ONCE(get_random_bytes, (buf), (nbytes))
#define HDFGWTR_EL2_TRCAUXCTLR_MASK GENMASK(35, 35)
#define _LINUX_QUOTA_ 
#define SVE_SIG_PREGS_OFFSET(vq) (SVE_SIG_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
#define NT_MIPS_FP_MODE 0x801
#define AARCH64_DBG_READ(N,REG,VAL) do { VAL = read_sysreg(dbg ##REG ##N ##_el1);} while (0)
#define SEQCNT_WW_MUTEX_ZERO(name,lock) SEQCOUNT_LOCKNAME_ZERO(name, lock)
#define NT_S390_GS_BC 0x30c
#define wait_var_event_interruptible(var,condition) ({ int __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_var_event_interruptible(var, condition); __ret; })
#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
#define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
#define ID_AA64PFR1_EL1_GCS GENMASK(47, 44)
#define NT_PPC_PPR 0x104
#define STATIC_CALL_KEY_PREFIX_STR __stringify(STATIC_CALL_KEY_PREFIX)
#define ETHTOOL_SWOL 0x00000006
#define HZ CONFIG_HZ
#define ID_AA64SMFR0_EL1_SMEver_IMP UL(0b0000)
#define ID_AA64ISAR2_EL1_GPA3_SIGNED false
#define MAS_ROOT ((struct maple_enode *)5UL)
#define REG_ID_AA64MMFR0_EL1 S3_0_C0_C7_0
#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE UL(0b0101)
#define IDA_BITMAP_BITS (IDA_BITMAP_LONGS * sizeof(long) * 8)
#define TRBIDR_EL1_P_WIDTH 1
#define CONFIG_I2C 1
#define __NR_getrusage 165
#define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
#define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
#define ID_AA64MMFR0_EL1_BIGEND_SIGNED false
#define __PGTBL_P4D_MODIFIED 1
#define PMSLATFR_EL1_MINLAT GENMASK(15, 0)
#define NT_S390_GS_CB 0x30b
#define percpu_rwsem_is_held(sem) lockdep_is_held(sem)
#define MAS_WARN_ON(__mas,__x) WARN_ON(__x)
#define HFGITR_EL2_TLBIRVALE1OS GENMASK(26, 26)
#define IPC_INFO 3
#define PTRACE_SYSCALL_INFO_NONE 0
#define PR_FP_EXC_DIV 0x010000
#define FT_SYMLINK 7
#define ID_AA64AFR0_EL1_IMPDEF0_WIDTH 4
#define DECLARE_STATIC_CALL(name,func) extern struct static_call_key STATIC_CALL_KEY(name); extern typeof(func) STATIC_CALL_TRAMP(name);
#define HFGxTR_EL2_ERRIDR_EL1 GENMASK(40, 40)
#define ARCH_WANTS_GENERIC_PCI_IOUNMAP 
#define __GFP_WRITE ((__force gfp_t)___GFP_WRITE)
#define CONFIG_AF_UNIX_OOB 1
#define PMSCR_EL2_PCT_WIDTH 2
#define HDFGRTR_EL2_TRCSTATR_MASK GENMASK(47, 47)
#define ___GFP_COMP 0x40000u
#define __NR_socket 198
#define __SVE_NUM_PREGS 16
#define WQ_FLAG_DONE 0x08
#define UMH_FREEZABLE 0x08
#define _LINUX_BUG_H 
#define ET_CORE 4
#define _LINUX_AUXVEC_H 
#define pr_debug_once(fmt,...) no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
#define readx_poll_timeout(op,addr,val,cond,sleep_us,timeout_us) read_poll_timeout(op, val, cond, sleep_us, timeout_us, false, addr)
#define ID_MMFR0_EL1_FCSE_WIDTH 4
#define JOBCTL_TRAP_NOTIFY_BIT 20
#define ID_ISAR1_EL1_Immediate GENMASK(23, 20)
#define next_node_in(n,src) __next_node_in((n), &(src))
#define PR_TAGGED_ADDR_ENABLE (1UL << 0)
#define ID_AA64MMFR1_EL1_HCX_WIDTH 4
#define lockdep_posixtimer_exit() do { current->irq_config = 0; } while (0)
#define time_in_range_open(a,b,c) (time_after_eq(a,b) && time_before(a,c))
#define HDFGRTR_EL2_MDSCR_EL1_WIDTH 1
#define SECTIONS_PGOFF ((sizeof(unsigned long)*8) - SECTIONS_WIDTH)
#define TRBSR_EL1_WRAP_SHIFT 20
#define SYS_ID_AA64ISAR1_EL1_CRm 6
#define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD)
#define static_key_enable_cpuslocked(k) static_key_enable((k))
#define DECLARE_STATIC_KEY_MAYBE(cfg,name) __PASTE(_DECLARE_STATIC_KEY_, IS_ENABLED(cfg))(name)
#define CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI 1
#define CONFIG_UNIX98_PTYS 1
#define __counted_by(member) 
#define SYS_ID_AA64ISAR1_EL1_CRn 0
#define INIT_SCTLR_EL1_MMU_ON (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
#define SUPPORTED_MII __ETHTOOL_LINK_MODE_LEGACY_MASK(MII)
#define SO_SECURITY_ENCRYPTION_NETWORK 24
#define SIG_SETMASK 2
#define pm_generic_thaw NULL
#define ID_PFR1_EL1_ProgMod_IMP UL(0b0001)
#define FS_XFLAG_NOSYMLINKS 0x00000400
#define SCTLR_EL1_C GENMASK(2, 2)
#define __NR_finit_module 273
#define __data_id_stringify(dummy,str) #str,
#define KCSAN_SEQLOCK_REGION_MAX 1000
#define HFGxTR_EL2_ERXSTATUS_EL1_WIDTH 1
#define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
#define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7)
#define ID_ISAR5_EL1_RDM_IMP UL(0b0001)
#define EXPORT_SIMPLE_DEV_PM_OPS(name,suspend_fn,resume_fn) EXPORT_DEV_SLEEP_PM_OPS(name) = { SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) }
#define __AMEV_op2(m) (m & 0x7)
#define SCHED_FLAG_KEEP_POLICY 0x08
#define MODULE_ALIAS_CHARDEV_MAJOR(major) MODULE_ALIAS("char-major-" __stringify(major) "-*")
#define SEND_SIG_PRIV ((struct kernel_siginfo *) 1)
#define ID_AA64DFR0_EL1_TraceVer_IMP UL(0b0001)
#define MDIO_AN_EEE_ADV_1000T 0x0004
#define SYS_SVCR_Op1 3
#define instrumentation_end() do { } while(0)
#define ID_AA64ISAR1_EL1_APA_MASK GENMASK(7, 4)
#define node_distance(from,to) ((from) == (to) ? LOCAL_DISTANCE : REMOTE_DISTANCE)
#define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2
#define PR_CAP_AMBIENT 47
#define CCW_DEVICE_ID_MATCH_CU_MODEL 0x02
#define dev_dbg_once(dev,fmt,...) dev_level_once(dev_dbg, dev, fmt, ##__VA_ARGS__)
#define FS_IOC32_SETVERSION _IOW('v', 2, int)
#define AUXILIARY_NAME_SIZE 32
#define wait_event_idle_timeout(wq_head,condition,timeout) ({ long __ret = timeout; might_sleep(); if (!___wait_cond_timeout(condition)) __ret = __wait_event_idle_timeout(wq_head, condition, timeout); __ret; })
#define SOL_ROSE 260
#define ID_ISAR4_EL1_Writeback GENMASK(11, 8)
#define __ASM_CACHE_H 
#define LOREA_EL1_EA_47_16_SHIFT 16
#define PF_FORKNOEXEC 0x00000040
#define ID_ISAR3_EL1_T32EE_MASK GENMASK(31, 28)
#define TCR2_EL2_D128 GENMASK(5, 5)
#define __NR_mq_timedreceive 183
#define BUGFLAG_ONCE (1 << 1)
#define PTE_VALID (_AT(pteval_t, 1) << 0)
#define CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK 1
#define ID_AA64ISAR1_EL1_GPI_SHIFT 28
#define CONFIG_8139CP 1
#define IPV6_CHECKSUM 7
#define SYS_SENDMSG 16
#define printk_cpu_sync_put_irqrestore(flags) do { __printk_cpu_sync_put(); local_irq_restore(flags); } while (0)
#define CONFIG_HAVE_IOREMAP_PROT 1
#define ID_MMFR1_EL1_L1HvdVA_INVALIDATE_BP UL(0b0010)
#define SYS_ID_MMFR5_EL1_Op0 3
#define SYS_ID_MMFR5_EL1_Op1 0
#define SYS_ID_MMFR5_EL1_Op2 6
#define P4D_MASK (~(P4D_SIZE-1))
#define rwlock_acquire_read(l,s,t,i) do { if (read_lock_is_recursive()) lock_acquire_shared_recursive(l, s, t, NULL, i); else lock_acquire_shared(l, s, t, NULL, i); } while (0)
#define S_ISFIFO(m) (((m) & S_IFMT) == S_IFIFO)
#define WARN_TAINT_ONCE(condition,taint,format...) DO_ONCE_LITE_IF(condition, WARN_TAINT, 1, taint, format)
#define __NR_tgkill 131
#define FIELD_MAX(_mask) ({ __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_MAX: "); (typeof(_mask))((_mask) >> __bf_shf(_mask)); })
#define PTR_ALIGN(p,a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
#define CONFIG_I2C_BOARDINFO 1
#define _LRU_LIST_H 
#define DACR32_EL2_D7_SHIFT 14
#define CONFIG_ARM_GIC_V2M 1
#define HFGITR_EL2_ATS1E1RP_WIDTH 1
#define FASYNC 00020000
#define arch_atomic64_add_return arch_atomic64_add_return
#define __BUG_ENTRY(flags) .pushsection __bug_table,"aw"; .align 2; 14470: .long 14471f - .; _BUGVERBOSE_LOCATION(__FILE__, __LINE__) .short flags; .popsection; 14471:
#define COMPAT_HWCAP2_CRC32 (1 << 4)
#define ID_AA64MMFR3_EL1_SCTLRX_SHIFT 4
#define lockdep_assert_irqs_enabled() do { WARN_ON_ONCE(__lockdep_enabled && !this_cpu_read(hardirqs_enabled)); } while (0)
#define ETHTOOL_COALESCE_TX_AGGR_MAX_BYTES BIT(24)
#define HFGxTR_EL2_ERXMISCn_EL1 GENMASK(45, 45)
#define HCRX_EL2_SCTLR2En_SHIFT 15
#define NETIF_F_NEVER_CHANGE (NETIF_F_VLAN_CHALLENGED | NETIF_F_LLTX | NETIF_F_NETNS_LOCAL)
#define ID_AA64ISAR1_EL1_I8MM GENMASK(55, 52)
#define HDFGRTR_EL2_PMBPTR_EL1_MASK GENMASK(24, 24)
#define _UAPI_LINUX_WAIT_H 
#define __compiletime_error(msg) __attribute__((__error__(msg)))
#define dma_get_sgtable(d,t,v,h,s) dma_get_sgtable_attrs(d, t, v, h, s, 0)
#define ID_AA64SMFR0_EL1_B16B16_MASK GENMASK(43, 43)
#define ID_MMFR1_EL1_L1UniVA_INVALIDATE_BP UL(0b0010)
#define ID_AA64MMFR1_EL1_AFP_MASK GENMASK(47, 44)
#define ID_PFR0_EL1_RAS_WIDTH 4
#define ID_AA64MMFR2_EL1_IDS_MASK GENMASK(39, 36)
#define SWAPPER_RX_MMUFLAGS (SWAPPER_RW_MMUFLAGS | PMD_SECT_RDONLY)
#define MDIO_PMA_CTRL2_10GBKX4 0x000a
#define SCTLR_EL1_EOS GENMASK(11, 11)
#define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
#define EOPNOTSUPP 95
#define _QR_BIAS (1U << _QR_SHIFT)
#define __NR_add_key 217
#define NT_LOONGARCH_CPUCFG 0xa00
#define __flush_tlb_range_op(op,start,pages,stride,asid,tlb_level,tlbi_user) do { int num = 0; int scale = 0; unsigned long addr; while (pages > 0) { if (!system_supports_tlb_range() || pages % 2 == 1) { addr = __TLBI_VADDR(start, asid); __tlbi_level(op, addr, tlb_level); if (tlbi_user) __tlbi_user_level(op, addr, tlb_level); start += stride; pages -= stride >> PAGE_SHIFT; continue; } num = __TLBI_RANGE_NUM(pages, scale); if (num >= 0) { addr = __TLBI_VADDR_RANGE(start, asid, scale, num, tlb_level); __tlbi(r ##op, addr); if (tlbi_user) __tlbi_user(r ##op, addr); start += __TLBI_RANGE_PAGES(num, scale) << PAGE_SHIFT; pages -= __TLBI_RANGE_PAGES(num, scale); } scale++; } } while (0)
#define FS_QUOTA_GDQ_ENFD (1<<3)
#define ID_AA64SMFR0_EL1_BI32I32_SHIFT 33
#define FMODE_NOWAIT ((__force fmode_t)0x8000000)
#define _LINUX_FCNTL_H 
#define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
#define pr_warn_ratelimited(fmt,...) printk_ratelimited(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__)
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
#define SCTLR_EL1_nTWI GENMASK(16, 16)
#define SIOCSHWTSTAMP 0x89b0
#define __LINUX_IF_PACKET_H 
#define REG_ID_DFR1_EL1 S3_0_C0_C3_5
#define lockdep_is_held(lock) lock_is_held(&(lock)->dep_map)
#define SYSCTL_LONG_ZERO ((void *)&sysctl_long_vals[0])
#define NETIF_F_GSO_ENCAP_ALL (NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_IPXIP6 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM)
#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
#define SMPRIMAP_EL2_P10_MASK GENMASK(43, 40)
#define HDFGWTR_EL2_DBGPRCR_EL1 GENMASK(7, 7)
#define HWCAP2_SVESHA3 (1 << 5)
#define _LINUX_MEI_H 
#define FIXADDR_TOP (VMEMMAP_START - SZ_32M)
#define ID_PFR1_EL1_ProgMod_WIDTH 4
#define SIOCSIFHWBROADCAST 0x8937
#define TCR2_EL2_D128_MASK GENMASK(5, 5)
#define CONFIG_CGROUP_DEBUG 1
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
#define DACR32_EL2_D11_WIDTH 2
#define arch_atomic64_add_return_release arch_atomic64_add_return_release
#define PAGEFLAG_FALSE(uname,lname) TESTPAGEFLAG_FALSE(uname, lname) SETPAGEFLAG_NOOP(uname, lname) CLEARPAGEFLAG_NOOP(uname, lname)
#define SYS_TCR2_EL1_CRn 2
#define SCTLR_EL1_EPAN GENMASK(57, 57)
#define REG_TTBR0_EL1 S3_0_C2_C0_0
#define __UINT64_C(c) c ## UL
#define HDFGWTR_EL2_DBGBCRn_EL1_WIDTH 1
#define DEFAULT_RATELIMIT_INTERVAL (5 * HZ)
#define _LINUX_DMA_MAPPING_H 
#define TCR2_EL1x_D128_WIDTH 1
#define SYS_TTBR0_EL1_CRn 2
#define ID_AA64DFR0_EL1_PMUVer_MASK GENMASK(11, 8)
#define irq_gc_lock_irqsave(gc,flags) raw_spin_lock_irqsave(&(gc)->lock, flags)
#define ADVERTISED_1000baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Half)
#define CONFIG_MFD_CORE 1
#define HFGITR_EL2_nGCSPUSHM_EL1_WIDTH 1
#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
#define SMPRIMAP_EL2_P4_WIDTH 4
#define MDSCR_EL1_INTdis GENMASK(23, 22)
#define SYS_ZCR_EL2_CRn 1
#define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
#define XA_CHUNK_SHIFT (CONFIG_BASE_SMALL ? 4 : 6)
#define SB_POSIXACL BIT(16)
#define SCTLR_EL1_WXN_WIDTH 1
#define ID_AA64PFR0_EL1_AdvSIMD_IMP UL(0b0000)
#define _LINUX_ONCE_H 
#define __NR_dup3 24
#define PIRx_ELx_Perm6_WIDTH 4
#define MDIO_AN_C73_1_40GBASE_CR4 BIT(9)
#define cpumask_any(srcp) cpumask_first(srcp)
#define SECCOMP_FILTER_FLAG_SPEC_ALLOW (1UL << 2)
#define ID_MMFR2_EL1_UniTLB_BY_MATCH_ASID UL(0b0010)
#define arch_atomic_set(v,i) __WRITE_ONCE(((v)->counter), (i))
#define ET_DYN 3
#define APPLE_CPU_PART_M1_FIRESTORM 0x023
#define CONFIG_HAVE_FAST_GUP 1
#define CONFIG_XLNX_EVENT_MANAGER 1
#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
#define __NR_msgctl 187
#define __ASM_BYTEORDER_H 
#define ID_MMFR4_EL1_CnP_SIGNED false
#define wake_up_interruptible_nr(x,nr) __wake_up(x, TASK_INTERRUPTIBLE, nr, NULL)
#define netif_emerg(priv,type,dev,fmt,args...) netif_level(emerg, priv, type, dev, fmt, ##args)
#define ETHTOOL_COALESCE_TX_USECS BIT(4)
#define ID_ISAR0_EL1_Divide GENMASK(27, 24)
#define HDFGRTR_EL2_TRCCNTVRn_WIDTH 1
#define ID_AA64PFR1_EL1_BT_SIGNED false
#define ID_MMFR1_EL1_BPred_NI UL(0b0000)
#define PMBIDR_EL1_EA_NotDescribed UL(0b0000)
#define __UAPI_DEF_IF_IFMAP 1
#define HDFGWTR_EL2_DBGWCRn_EL1_WIDTH 1
#define ID_AA64ISAR1_EL1_DPB_IMP UL(0b0001)
#define SVE_SIG_ZREGS_SIZE(vq) __SVE_ZREGS_SIZE(vq)
#define per_cpu(var,cpu) (*per_cpu_ptr(&(var), cpu))
#define ID_AA64MMFR0_EL1_TGRAN16_WIDTH 4
#define this_cpu_or_1(pcp,val) _pcp_protect(__percpu_or_case_8, pcp, val)
#define this_cpu_or_2(pcp,val) _pcp_protect(__percpu_or_case_16, pcp, val)
#define this_cpu_or_4(pcp,val) _pcp_protect(__percpu_or_case_32, pcp, val)
#define NT_PPC_TM_CTAR 0x10d
#define net_info_ratelimited(fmt,...) net_ratelimited_function(pr_info, fmt, ##__VA_ARGS__)
#define this_cpu_or_8(pcp,val) _pcp_protect(__percpu_or_case_64, pcp, val)
#define SO_BPF_EXTENSIONS 48
#define CONFIG_FIX_EARLYCON_MEM 1
#define SSB_ANY_VENDOR 0xFFFF
#define HFGxTR_EL2_MPIDR_EL1 GENMASK(26, 26)
#define MT_WARN_ON(__tree,__x) WARN_ON(__x)
#define copy_siginfo_to_user32 __copy_siginfo_to_user32
#define __NR_connect 203
#define in_range(val,start,len) ((sizeof(start) | sizeof(len) | sizeof(val)) <= sizeof(u32) ? in_range32(val, start, len) : in_range64(val, start, len))
#define _KUNIT_FAILED(test,assert_type,assert_class,assert_format,INITIALIZER,fmt,...) do { static const struct kunit_loc __loc = KUNIT_CURRENT_LOC; const struct assert_class __assertion = INITIALIZER; __kunit_do_failed_assertion(test, &__loc, assert_type, &__assertion.assert, assert_format, fmt, ##__VA_ARGS__); if (assert_type == KUNIT_ASSERTION) __kunit_abort(test); } while (0)
#define KUNIT_ASSERT_EQ(test,left,right) KUNIT_ASSERT_EQ_MSG(test, left, right, NULL)
#define CONFIG_IRQ_WORK 1
#define NT_SIGINFO 0x53494749
#define IRQF_PROBE_SHARED 0x00000100
#define init_wait(wait) do { (wait)->private = current; (wait)->func = autoremove_wake_function; INIT_LIST_HEAD(&(wait)->entry); (wait)->flags = 0; } while (0)
#define rcu_dereference_raw_check(p) __rcu_dereference_check((p), __UNIQUE_ID(rcu), 1, __rcu)
#define __SWAIT_QUEUE_HEAD_INIT_ONSTACK(name) ({ init_swait_queue_head(&name); name; })
#define __local_unlock_irqrestore(lock,flags) do { local_lock_release(this_cpu_ptr(lock)); local_irq_restore(flags); } while (0)
#define CAP_SYS_BOOT 22
#define pgprot_device(prot) __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
#define ADVERTISED_1000baseKX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseKX_Full)
#define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
#define __constant_cpu_to_be32(x) ((__force __be32)___constant_swab32((x)))
#define HFGxTR_EL2_ERXPFGCTL_EL1_WIDTH 1
#define nodes_setall(dst) __nodes_setall(&(dst), MAX_NUMNODES)
#define _UAPI_LINUX_TIMEX_H 
#define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
#define VM_FAULT_RESULT_TRACE { VM_FAULT_OOM, "OOM" }, { VM_FAULT_SIGBUS, "SIGBUS" }, { VM_FAULT_MAJOR, "MAJOR" }, { VM_FAULT_HWPOISON, "HWPOISON" }, { VM_FAULT_HWPOISON_LARGE, "HWPOISON_LARGE" }, { VM_FAULT_SIGSEGV, "SIGSEGV" }, { VM_FAULT_NOPAGE, "NOPAGE" }, { VM_FAULT_LOCKED, "LOCKED" }, { VM_FAULT_RETRY, "RETRY" }, { VM_FAULT_FALLBACK, "FALLBACK" }, { VM_FAULT_DONE_COW, "DONE_COW" }, { VM_FAULT_NEEDDSYNC, "NEEDDSYNC" }, { VM_FAULT_COMPLETED, "COMPLETED" }
#define MVFR1_EL1_SIMDSP_NI UL(0b0000)
#define ID_AA64DFR0_EL1_BRBE_SHIFT 52
#define MII_MMD_CTRL_INCR_RDWT 0x8000
#define seqcount_release(l,i) lock_release(l, i)
#define PMD_SECT_CONT (_AT(pmdval_t, 1) << 52)
#define FS_NOCOMP_FL 0x00000400
#define hlist_next_rcu(node) (*((struct hlist_node __rcu **)(&(node)->next)))
#define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
#define PTRACE_GET_SYSCALL_INFO 0x420e
#define symbol_get(x) ({ extern typeof(x) x __attribute__((weak,visibility("hidden"))); &(x); })
#define NSEC_TO_HZ_NUM 1
#define INIT_CPU_TIMERBASE(b) { .nextevt = U64_MAX, }
#define __nmi_enter() do { lockdep_off(); arch_nmi_enter(); BUG_ON(in_nmi() == NMI_MASK); __preempt_count_add(NMI_OFFSET + HARDIRQ_OFFSET); } while (0)
#define TASK_FROZEN 0x00008000
#define KUNIT_ASSERT_GE(test,left,right) KUNIT_ASSERT_GE_MSG(test, left, right, NULL)
#define __constant_be64_to_cpu(x) ___constant_swab64((__force __u64)(__be64)(x))
#define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
#define FIDEDUPERANGE _IOWR(0x94, 54, struct file_dedupe_range)
#define DEFINE_STATIC_KEY_ARRAY_FALSE(name,count) struct static_key_false name[count] = { [0 ... (count) - 1] = STATIC_KEY_FALSE_INIT, }
#define cpumask_of_node(node) ((void)(node), cpu_online_mask)
#define KUNIT_ASSERT_GT(test,left,right) KUNIT_ASSERT_GT_MSG(test, left, right, NULL)
#define _UAPI_LINUX_STDDEF_H 
#define ID_MMFR2_EL1_MemBarr_MASK GENMASK(23, 20)
#define ID_ISAR2_EL1_MultU_UMULL UL(0b0001)
#define SUPPORTED_10000baseR_FEC __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseR_FEC)
#define ID_ISAR2_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_ISAR2_EL1_RES1 (UL(0))
#define BOOT_CPU_FLAG_E2H BIT_ULL(32)
#define try_cmpxchg64(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); kcsan_mb(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg64(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define CONFIG_IOMMU_IOVA 1
#define local_sub_and_test(i,l) atomic_long_sub_and_test((i), (&(l)->a))
#define __unsigned_scalar_typeof(x) typeof( _Generic((x), char: (unsigned char)0, __scalar_type_to_unsigned_cases(char), __scalar_type_to_unsigned_cases(short), __scalar_type_to_unsigned_cases(int), __scalar_type_to_unsigned_cases(long), __scalar_type_to_unsigned_cases(long long), default: (x)))
#define ID_AA64MMFR0_EL1_TGRAN16_IMP UL(0b0001)
#define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
#define V2_DEL_ALLOC QTREE_DEL_ALLOC
#define split_huge_pud(__vma,__pmd,__address) do { } while (0)
#define ID_DFR0_EL1_MProfDbg_SHIFT 20
#define __UAPI_DEF_IN_PKTINFO 1
#define BMSR_JCD 0x0002
#define CONT_PTE_SHIFT (CONFIG_ARM64_CONT_PTE_SHIFT + PAGE_SHIFT)
#define ELF32_ST_BIND(x) ELF_ST_BIND(x)
#define ID_MMFR4_EL1_XNX_SHIFT 8
#define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
#define noinline __attribute__((__noinline__))
#define ID_ISAR3_EL1_SIMD_MASK GENMASK(7, 4)
#define __clamp(val,lo,hi) ((val) >= (hi) ? (hi) : ((val) <= (lo) ? (lo) : (val)))
#define _LINUX_RADIX_TREE_H 
#define QC_LIMIT_MASK (QC_INO_SOFT | QC_INO_HARD | QC_SPC_SOFT | QC_SPC_HARD | QC_RT_SPC_SOFT | QC_RT_SPC_HARD)
#define KUNIT_ASSERT_NULL_MSG(test,ptr,fmt,...) KUNIT_BINARY_PTR_ASSERTION(test, KUNIT_ASSERTION, ptr, ==, NULL, fmt, ##__VA_ARGS__)
#define ID_AA64ISAR1_EL1_JSCVT_IMP UL(0b0001)
#define DCZID_EL0_DZP_MASK GENMASK(4, 4)
#define wake_up_interruptible_sync_poll_locked(x,m) __wake_up_locked_sync_key((x), TASK_INTERRUPTIBLE, poll_to_key(m))
#define SCTLR_EL1_TWEDEL_WIDTH 4
#define __NR_name_to_handle_at 264
#define PR_SCHED_CORE_SCOPE_THREAD 0
#define ARM64_CB_BIT BIT(ARM64_CB_SHIFT)
#define iowrite32_rep iowrite32_rep
#define device_pm_unlock() do {} while (0)
#define TCR2_EL1x_DisCH0 GENMASK(14, 14)
#define TCR2_EL1x_DisCH1 GENMASK(15, 15)
#define CONCATENATE(a,b) __CONCAT(a, b)
#define ID_ISAR1_EL1_Extend_MASK GENMASK(15, 12)
#define FORK_PREEMPT_COUNT (2*PREEMPT_DISABLE_OFFSET + PREEMPT_ENABLED)
#define ADVERTISE_1000XPAUSE 0x0080
#define is_special_task_state(state) ((state) & (__TASK_STOPPED | __TASK_TRACED | TASK_PARKED | TASK_DEAD))
#define LED_DEV_CAP_FLASH BIT(18)
#define skb_rbtree_walk_from_safe(skb,tmp) for (; tmp = skb ? skb_rb_next(skb) : NULL, (skb != NULL); skb = tmp)
#define memset_after(obj,v,member) ({ u8 *__ptr = (u8 *)(obj); typeof(v) __val = (v); memset(__ptr + offsetofend(typeof(*(obj)), member), __val, sizeof(*(obj)) - offsetofend(typeof(*(obj)), member)); })
#define PR_GET_FP_MODE 46
#define CONFIG_NET_VENDOR_ATHEROS 1
#define __HAVE_ARCH_STRCHR 
#define HCRX_EL2_EnIDCP128 GENMASK(21, 21)
#define FAR_EL12_RES0 (UL(0))
#define FAR_EL12_RES1 (UL(0))
#define X86_MODEL_ANY 0
#define LSM_UNSAFE_NO_NEW_PRIVS 4
#define LORID_EL1_LR_SHIFT 0
#define PR_PAC_RESET_KEYS 54
#define HCR_ATA (UL(1) << HCR_ATA_SHIFT)
#define PAGE_TYPE_BASE 0xf0000000
#define MAX_NR_ZONES 4
#define TP_STATUS_TS_SOFTWARE (1 << 29)
#define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
#define KUNIT_EXPECT_STREQ(test,left,right) KUNIT_EXPECT_STREQ_MSG(test, left, right, NULL)
#define MDIO_PMA_EXTABLE_1000BT 0x0020
#define TASK_INTERRUPTIBLE 0x00000001
#define ID_AA64MMFR2_EL1_TTL_MASK GENMASK(51, 48)
#define SYS_PMBSR_EL1_CRm 10
#define SYS_PMBSR_EL1_CRn 9
#define INPUT_DEVICE_ID_MATCH_LEDBIT 0x0200
#define COMPAT_PTRACE_GETVFPREGS 27
#define notrace __attribute__((__no_instrument_function__))
#define arch_phys_wc_add arch_phys_wc_add
#define CONFIG_NET_RX_BUSY_POLL 1
#define ETH_P_IEEEPUPAT 0x0a01
#define VM_WARN_ONCE(cond,format...) BUILD_BUG_ON_INVALID(cond)
#define ID_AA64DFR0_EL1_TraceBuffer_SIGNED false
#define FMODE_BUF_RASYNC ((__force fmode_t)0x40000000)
#define R_AARCH64_ABS32 258
#define Q_XGETQUOTA XQM_CMD(3)
#define DCZID_EL0_BS_MASK GENMASK(3, 0)
#define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
#define SMCR_ELx_FA64_SHIFT 31
#define CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC 1
#define subsys_param_cb(name,ops,arg,perm) __level_param_cb(name, ops, arg, perm, 4)
#define HDFGRTR_EL2_PMBLIMITR_EL1_MASK GENMASK(23, 23)
#define raw_spin_lock_irqsave_nested(lock,flags,subclass) do { typecheck(unsigned long, flags); flags = _raw_spin_lock_irqsave_nested(lock, subclass); } while (0)
#define SCTLR_EL1_TCF_ASYNC UL(0b10)
#define this_cpu_add_1(pcp,val) _pcp_protect(__percpu_add_case_8, pcp, val)
#define this_cpu_add_2(pcp,val) _pcp_protect(__percpu_add_case_16, pcp, val)
#define this_cpu_add_4(pcp,val) _pcp_protect(__percpu_add_case_32, pcp, val)
#define SIOCGIFADDR 0x8915
#define this_cpu_add_8(pcp,val) _pcp_protect(__percpu_add_case_64, pcp, val)
#define KUNIT_ASSERT_LE(test,left,right) KUNIT_ASSERT_LE_MSG(test, left, right, NULL)
#define CONFIG_APPLE_PMGR_PWRSTATE 1
#define ALARMTIMER_STATE_INACTIVE 0x00
#define KUNIT_ASSERT_LT(test,left,right) KUNIT_ASSERT_LT_MSG(test, left, right, NULL)
#define CLIDR_EL1_Ctype6_MASK GENMASK(17, 15)
#define fl6_sport uli.ports.sport
#define KUNIT_CASE(test_name) { .run_case = test_name, .name = #test_name, .module_name = KBUILD_MODNAME}
#define virt_to_phys virt_to_phys
#define HDFGWTR_EL2_TRCIMSPECn_SHIFT 41
#define ID_AA64PFR0_EL1_RME_SIGNED false
#define MAIR_ATTR_NORMAL UL(0xff)
#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
#define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
#define IPV6_PMTUDISC_INTERFACE 4
#define DEFINE_RWLOCK(x) rwlock_t x = __RW_LOCK_UNLOCKED(x)
#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8
#define PR_MTE_TAG_SHIFT 3
#define PAGE_MAPCOUNT_RESERVE -128
#define ARM_MAX_WRP 16
#define ID_MMFR3_EL1_BPMaint_ALL UL(0b0001)
#define arch_atomic64_fetch_and_release arch_atomic64_fetch_and_release
#define CONFIG_ARCH_HAS_KCOV 1
#define SHF_EXECINSTR 0x4
#define PR_TIMING_STATISTICAL 0
#define TCR2_EL1x_DisCH0_WIDTH 1
#define MVFR1_EL1_SIMDSP_MASK GENMASK(19, 16)
#define DT_WHT 14
#define DECLARE_WAIT_QUEUE_HEAD_ONSTACK(name) struct wait_queue_head name = __WAIT_QUEUE_HEAD_INIT_ONSTACK(name)
#define TRBPTR_EL1_PTR_SHIFT 0
#define ID_AA64MMFR1_EL1_VMIDBits GENMASK(7, 4)
#define CONFIG_COMMON_CLK 1
#define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
#define wait_event_lock_irq_timeout(wq_head,condition,lock,timeout) ({ long __ret = timeout; if (!___wait_cond_timeout(condition)) __ret = __wait_event_lock_irq_timeout( wq_head, condition, lock, timeout, TASK_UNINTERRUPTIBLE); __ret; })
#define lockdep_hardirq_context() (raw_cpu_read(hardirq_context))
#define __tag_reset(addr) (addr)
#define PFA_SPEC_SSB_DISABLE 3
#define HCR_VM (UL(1) << 0)
#define arch_atomic64_fetch_or arch_atomic64_fetch_or
#define SO_NO_CHECK 11
#define phydev_warn(_phydev,format,args...) dev_warn(&_phydev->mdio.dev, format, ##args)
#define NUM_TYPE_ARGS(eltype,...) (sizeof((eltype[]){__VA_ARGS__}) / sizeof(eltype))
#define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x))
#define insl_p insl_p
#define copy_to_user_page copy_to_user_page
#define _LINUX_DROPREASON_CORE_H 
#define __swahb32(x) (__builtin_constant_p((__u32)(x)) ? ___constant_swahb32(x) : __fswahb32(x))
#define R_AARCH64_ABS64 257
#define STATX_BASIC_STATS 0x000007ffU
#define LPA_SGMII_10HALF 0x0000
#define INIT_RCU_WORK_ONSTACK(_work,_func) INIT_WORK_ONSTACK(&(_work)->work, (_func))
#define ID_ISAR1_EL1_Extend_SXTB16 UL(0b0010)
#define SO_DETACH_FILTER 27
#define ID_AA64ISAR0_EL1_ATOMIC_IMP UL(0b0010)
#define HDFGRTR_EL2_PMCNTEN_SHIFT 16
#define lockdep_assert_held(l) lockdep_assert(lockdep_is_held(l) != LOCK_STATE_NOT_HELD)
#define NETLINK_CRYPTO 21
#define __HAVE_ARCH_STRCMP 
#define ID_ISAR2_EL1_MultiAccessInt GENMASK(11, 8)
#define ID_AA64ISAR2_EL1_APA3_PAuth UL(0b0001)
#define NETIF_F_SCTP_CRC __NETIF_F(SCTP_CRC)
#define HDFGWTR_EL2_PMSLATFR_EL1_SHIFT 32
#define __NR_setitimer 103
#define CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1
#define cmpxchg64_acquire(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg64_acquire(__ai_ptr, __VA_ARGS__); })
#define PMBSR_EL1_EC_WIDTH 6
#define FWNODE_FLAG_BEST_EFFORT BIT(4)
#define CONFIG_ARCH_INLINE_WRITE_LOCK_BH 1
#define HDFGRTR_EL2_TRCID_SHIFT 40
#define ID_AA64MMFR2_EL1_IESB_NI UL(0b0000)
#define SI_DETHREAD -7
#define S_ISVTX 0001000
#define MDCR_EL2_TPMS (UL(1) << 14)
#define clamp_t(type,val,lo,hi) __careful_clamp((type)(val), (type)(lo), (type)(hi))
#define _QR_SHIFT 9
#define RB_ROOT (struct rb_root) { NULL, }
#define REG_CSSELR_EL1 S3_2_C0_C0_0
#define MVFR0_EL1_FPSqrt_SIGNED false
#define DECLARE_DYNDBG_CLASSMAP(_var,_maptype,_base,...) static const char *_var ##_classnames[] = { __VA_ARGS__ }; static struct ddebug_class_map __aligned(8) __used __section("__dyndbg_classes") _var = { .mod = THIS_MODULE, .mod_name = KBUILD_MODNAME, .base = _base, .map_type = _maptype, .length = NUM_TYPE_ARGS(char*, __VA_ARGS__), .class_names = _var ##_classnames, }
#define bitop(op,nr,addr) ((__builtin_constant_p(nr) && __builtin_constant_p((uintptr_t)(addr) != (uintptr_t)NULL) && (uintptr_t)(addr) != (uintptr_t)NULL && __builtin_constant_p(*(const unsigned long *)(addr))) ? const ##op(nr, addr) : op(nr, addr))
#define GFP_ZONE_TABLE ( (ZONE_NORMAL << 0 * GFP_ZONES_SHIFT) | (OPT_ZONE_DMA << ___GFP_DMA * GFP_ZONES_SHIFT) | (OPT_ZONE_HIGHMEM << ___GFP_HIGHMEM * GFP_ZONES_SHIFT) | (OPT_ZONE_DMA32 << ___GFP_DMA32 * GFP_ZONES_SHIFT) | (ZONE_NORMAL << ___GFP_MOVABLE * GFP_ZONES_SHIFT) | (OPT_ZONE_DMA << (___GFP_MOVABLE | ___GFP_DMA) * GFP_ZONES_SHIFT) | (ZONE_MOVABLE << (___GFP_MOVABLE | ___GFP_HIGHMEM) * GFP_ZONES_SHIFT) | (OPT_ZONE_DMA32 << (___GFP_MOVABLE | ___GFP_DMA32) * GFP_ZONES_SHIFT))
#define FS_DQ_RTBSOFT (1<<4)
#define MVFR0_EL1_FPSP_SIGNED false
#define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
#define le32_to_cpup __le32_to_cpup
#define le32_to_cpus __le32_to_cpus
#define ENAMETOOLONG 36
#define WAKE_MAGICSECURE (1 << 6)
#define _LINUX_RHASHTABLE_TYPES_H 
#define SYS_SVCR_Op0 3
#define HDFGRTR_EL2_PMSCR_EL1_WIDTH 1
#define SYS_SVCR_Op2 2
#define RX_CLS_LOC_SPECIAL 0x80000000
#define for_each_node_with_cpus(node) for_each_online_node(node) if (nr_cpus_node(node))
#define DL_FLAG_AUTOREMOVE_CONSUMER BIT(1)
#define ID_MMFR4_EL1_AC2_WIDTH 4
#define __NR_fsmount 432
#define SUBCMDMASK 0x00ff
#define HFGxTR_EL2_LOREA_EL1_SHIFT 20
#define dma_map_page(d,p,o,s,r) dma_map_page_attrs(d, p, o, s, r, 0)
#define PF_MCE_PROCESS 0x00000080
#define AF_IB 27
#define SO_RCVMARK 75
#define L1_CACHE_ALIGN(x) __ALIGN_KERNEL(x, L1_CACHE_BYTES)
#define NETLINK_CONNECTOR 11
#define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
#define HAVE_FUNCTION_GRAPH_RET_ADDR_PTR 
#define RLIMIT_AS 9
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define CONFIG_POWER_SUPPLY 1
#define HFGITR_EL2_TLBIVAE1IS_WIDTH 1
#define KASAN_ABI_VERSION 5
#define ext2_clear_bit_atomic(l,nr,addr) test_and_clear_bit_le(nr, addr)
#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO)
#define AF_MCTP 45
#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
#define min_not_zero(x,y) ({ typeof(x) __x = (x); typeof(y) __y = (y); __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); })
#define CONFIG_CMDLINE "console=ttyAMA0 nokaslr rdinit=/sbin/init"
#define ID_AA64ZFR0_EL1_BitPerm GENMASK(19, 16)
#define SKB_MAX_HEAD(X) (SKB_MAX_ORDER((X), 0))
#define HVC_SOFT_RESTART 1
#define SYM_FUNC_START_LOCAL_NOALIGN(name) SYM_START(name, SYM_L_LOCAL, SYM_A_NONE) bti c ;
#define ID_MMFR0_EL1_FCSE GENMASK(27, 24)
#define key_fsgid_changed(c) do { } while(0)
#define ID_AA64ISAR1_EL1_GPA_SHIFT 24
#define HDFGWTR_EL2_TRBPTR_EL1 GENMASK(54, 54)
#define F_GETOWN_EX 16
#define SET_GID(var,gid) do { (var) = __convert_gid(sizeof(var), (gid)); } while (0)
#define BITS_TO_U64(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u64))
#define dev_warn(dev,fmt,...) dev_printk_index_wrap(_dev_warn, KERN_WARNING, dev, dev_fmt(fmt), ##__VA_ARGS__)
#define ID_MMFR0_EL1_PMSA_WIDTH 4
#define REFCOUNT_SATURATED (INT_MIN / 2)
#define PORT_BNC 0x04
#define __NR_fanotify_init 262
#define PMSIDR_EL1_FORMAT_MASK GENMASK(23, 20)
#define IPV6_FL_A_GET 0
#define IFF_MASTER IFF_MASTER
#define _ASM_EXTABLE_LOAD_UNALIGNED_ZEROPAD(insn,fixup,data,addr) __DEFINE_ASM_GPR_NUMS __ASM_EXTABLE_RAW(#insn, #fixup, __stringify(EX_TYPE_LOAD_UNALIGNED_ZEROPAD), "(" EX_DATA_REG(DATA, data) " | " EX_DATA_REG(ADDR, addr) ")")
#define REG_SVCR S3_3_C4_C2_2
#define DQ_BLKS_B 1
#define HFGxTR_EL2_LORN_EL1_WIDTH 1
#define task_is_stopped_or_traced(task) ((READ_ONCE(task->jobctl) & (JOBCTL_STOPPED | JOBCTL_TRACED)) != 0)
#define JBD2_POISON_FREE 0x5c
#define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
#define ID_MMFR4_EL1_HPDS_HPDS2 UL(0b0010)
#define SB_FREEZE_LEVELS (SB_FREEZE_COMPLETE - 1)
#define INIT_WORK_ONSTACK_KEY(_work,_func,_key) __INIT_WORK_KEY((_work), (_func), 1, _key)
#define ID_ISAR1_EL1_Except_AR_SHIFT 8
#define CONFIG_ARCH_SUPPORTS_CFI_CLANG 1
#define INITQFNAMES { "user", "group", "project", "undefined", };
#define __LINUX_RESTART_BLOCK_H 
#define FS_IOC_SETVERSION _IOW('v', 2, long)
#define be16_to_cpup __be16_to_cpup
#define be16_to_cpus __be16_to_cpus
#define ARG_MAX 131072
#define SCTLR_EL1_EPAN_MASK GENMASK(57, 57)
#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
#define UUID_LE(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) ((uuid_le) {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, (b) & 0xff, ((b) >> 8) & 0xff, (c) & 0xff, ((c) >> 8) & 0xff, (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
#define SCTLR_EL1_SPAN_SHIFT 23
#define HFGITR_EL2_ICIALLU_MASK GENMASK(1, 1)
#define TASK_TRACED __TASK_TRACED
#define __MODULE_STRING(x) __stringify(x)
#define FMODE_READ ((__force fmode_t)0x1)
#define IORESOURCE_IRQ_LOWEDGE (1<<1)
#define PT_GNU_STACK (PT_LOOS + 0x474e551)
#define Q_XGETQSTAT XQM_CMD(5)
#define ID_AA64ISAR0_EL1_SM3_NI UL(0b0000)
#define SIOCWANDEV 0x894A
#define HDFGRTR_EL2_DBGBCRn_EL1 GENMASK(0, 0)
#define TRBTRG_EL1_TRG GENMASK(31, 0)
#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
#define ID_ISAR3_EL1_TabBranch_SHIFT 16
#define KGDB_DYN_DBG_BRK_IMM 0x400
#define ID_AA64DFR0_EL1_BRBE GENMASK(55, 52)
#define DEVKMSG_STR_MAX_SIZE 10
#define SHM_W 0200
#define CSSELR_EL1_TnD_SHIFT 4
#define HFGxTR_EL2_nACCDATA_EL1_SHIFT 50
#define CONFIG_TRACING_SUPPORT 1
#define __local_dec(l) local_set((l), local_read(l) - 1)
#define PCMCIA_DEV_ID_MATCH_PROD_ID1 0x0010
#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
#define VM_HUGEPAGE 0x20000000
#define task_is_running(task) (READ_ONCE((task)->__state) == TASK_RUNNING)
#define HFGxTR_EL2_CTR_EL0_MASK GENMASK(14, 14)
#define HWEIGHT8(w) (BUILD_BUG_ON_ZERO(!__builtin_constant_p(w)) + __const_hweight8(w))
#define MDSCR_EL1_TXU GENMASK(26, 26)
#define __NR_swapon 224
#define CNTHCTL_EVNTEN (1 << 2)
#define MVFR1_EL1_SIMDHP_SHIFT 20
#define __ILL_BNDMOD 11
#define MDCCINT_EL1_RES1 (UL(0))
#define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
#define PT_TRACE_VFORK PT_EVENT_FLAG(PTRACE_EVENT_VFORK)
#define DQ_ACTIVE_B 5
#define ioremap_wc(addr,size) ioremap_prot((addr), (size), PROT_NORMAL_NC)
#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
#define dma_unmap_addr(PTR,ADDR_NAME) ((PTR)->ADDR_NAME)
#define LED_BLINK_INVERT 3
#define ID_AA64ISAR1_EL1_GPI_SIGNED false
#define ioremap_wt ioremap
#define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX)
#define ZONEID_SHIFT (NODES_SHIFT + ZONES_SHIFT)
#define PR_SPEC_DISABLE_NOEXEC (1UL << 4)
#define DEFINE_RATELIMIT_STATE(name,interval_init,burst_init) struct ratelimit_state name = RATELIMIT_STATE_INIT(name, interval_init, burst_init)
#define CONFIG_DMA_COHERENT_POOL 1
#define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM)
#define SYS_TRBMAR_EL1_Op1 0
#define arch_cmpxchg64_local arch_cmpxchg_local
#define __SYS_BARRIER_INSN(CRm,op2,Rt) __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
#define hlist_for_each_entry_srcu(pos,head,member,cond) for (__list_check_srcu(cond), pos = hlist_entry_safe(rcu_dereference_raw(hlist_first_rcu(head)), typeof(*(pos)), member); pos; pos = hlist_entry_safe(rcu_dereference_raw(hlist_next_rcu( &(pos)->member)), typeof(*(pos)), member))
#define swahb32p __swahb32p
#define swahb32s __swahb32s
#define SYNC_FILE_RANGE_WAIT_BEFORE 1
#define TRBBASER_EL1_RES0 (UL(0) | GENMASK_ULL(11, 0))
#define TRBBASER_EL1_RES1 (UL(0))
#define _UAPI__ASM_HWCAP_H 
#define PMSCR_EL2_E2SPE_WIDTH 1
#define KUNIT_ASSERT_STREQ_MSG(test,left,right,fmt,...) KUNIT_BINARY_STR_ASSERTION(test, KUNIT_ASSERTION, left, ==, right, fmt, ##__VA_ARGS__)
#define __PAGEFLAG(uname,lname,policy) TESTPAGEFLAG(uname, lname, policy) __SETPAGEFLAG(uname, lname, policy) __CLEARPAGEFLAG(uname, lname, policy)
#define __ARCH_SI_CLOCK_T __kernel_clock_t
#define __sme_clr(x) (x)
#define CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE 1
#define _COMPAT_NSIG_WORDS (_COMPAT_NSIG / _COMPAT_NSIG_BPW)
#define ILL_BADIADDR 9
#define CONFIG_VIRTIO_ANCHOR 1
#define __io_pbr() __io_br()
#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
#define compat_lr_svc regs[18]
#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
#define wake_up_all(x) __wake_up(x, TASK_NORMAL, 0, NULL)
#define NT_S390_VXRS_LOW 0x309
#define RADIX_TREE_MAX_PATH (DIV_ROUND_UP(RADIX_TREE_INDEX_BITS, RADIX_TREE_MAP_SHIFT))
#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
#define EOWNERDEAD 130
#define FS_NODUMP_FL 0x00000040
#define _EXPORT_DEV_PM_OPS(name,license,ns) _EXPORT_PM_OPS(name, license, ns)
#define __for_each_thread(signal,t) list_for_each_entry_rcu(t, &(signal)->thread_head, thread_node, lockdep_is_held(&tasklist_lock))
#define HCRX_EL2_CMOW GENMASK(9, 9)
#define TTBRx_EL1_RES0 (UL(0))
#define TTBRx_EL1_RES1 (UL(0))
#define _LINUX_RESOURCE_H 
#define VMEMMAP_RESERVE_NR 2
#define DT_FIFO 1
#define HDFGWTR_EL2_TRFCR_EL1_WIDTH 1
#define kprobe_busy_end() do {} while (0)
#define __BIN_ATTR_RO(_name,_size) { .attr = { .name = __stringify(_name), .mode = 0444 }, .read = _name ##_read, .size = _size, }
#define ID_AA64PFR1_EL1_MPAM_frac GENMASK(19, 16)
#define ID_AA64MMFR1_EL1_ECBHB_SIGNED false
#define ID_AA64MMFR0_EL1_BIGEND_MASK GENMASK(11, 8)
#define MSG_SPLICE_PAGES 0x8000000
#define ethtool_link_ksettings_add_link_mode(ptr,name,mode) __set_bit(ETHTOOL_LINK_MODE_ ## mode ## _BIT, (ptr)->link_modes.name)
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define __cacheline_group_end(GROUP) __u8 __cacheline_group_end__ ##GROUP[0]
#define _UAPI_ASM_GENERIC_RESOURCE_H 
#define mutex_lock_io(lock) mutex_lock_io_nested(lock, 0)
#define STT_NOTYPE 0
#define SIGUNUSED 31
#define module_put_and_kthread_exit(code) kthread_exit(code)
#define HWCAP2_SVEI8MM (1 << 9)
#define CONFIG_AS_HAS_NON_CONST_LEB128 1
#define SCTLR_EL1_C_SHIFT 2
#define LED_FUNCTION_WAN "wan"
#define HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT 62
#define STT_TLS 6
#define si_overrun _sifields._timer._overrun
#define __typecheck(x,y) (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
#define BLOCKING_NOTIFIER_HEAD(name) struct blocking_notifier_head name = BLOCKING_NOTIFIER_INIT(name)
#define __NR_removexattr 14
#define ID_AA64MMFR2_EL1_IESB_IMP UL(0b0001)
#define HFGxTR_EL2_MIDR_EL1 GENMASK(25, 25)
#define flowi6_secid __fl_common.flowic_secid
#define ID_AA64MMFR2_EL1_FWB_MASK GENMASK(43, 40)
#define DEBUG_LOCKS_WARN_ON(c) ({ int __ret = 0; if (!oops_in_progress && unlikely(c)) { instrumentation_begin(); if (debug_locks_off() && !debug_locks_silent) WARN(1, "DEBUG_LOCKS_WARN_ON(%s)", #c); instrumentation_end(); __ret = 1; } __ret; })
#define pfn_pte(pfn,prot) __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define MOD_TIMECONST ADJ_TIMECONST
#define REG_HFGITR_EL2 S3_4_C1_C1_6
#define ID_AA64PFR1_EL1_PFAR_SHIFT 60
#define ID_ISAR2_EL1_MultiAccessInt_MASK GENMASK(11, 8)
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define ELF64_ST_BIND(x) ELF_ST_BIND(x)
#define SVE_PT_REGS_MASK (1 << 0)
#define IS_NOATIME(inode) __IS_FLG(inode, SB_RDONLY|SB_NOATIME)
#define ID_AA64MMFR0_EL1_UNKN (UL(0))
#define pgd_offset_k(address) pgd_offset(&init_mm, (address))
#define DT_STRSZ 10
#define PMBPTR_EL1_PTR_MASK GENMASK(63, 0)
#define processor_mode(regs) ((regs)->pstate & PSR_MODE_MASK)
#define SO_NETNS_COOKIE 71
#define HFGxTR_EL2_ESR_EL1_MASK GENMASK(16, 16)
#define ESR_ELx_GCS_SHIFT (8)
#define MVFR0_EL1_FPDP_SHIFT 8
#define ID_DFR0_EL1_TraceFilt_SHIFT 28
#define PIRx_ELx_PERM(idx,perm) ((perm) << ((idx) * 4))
#define __NR_setregid 143
#define _copy_mc_to_iter _copy_to_iter
#define SOL_IRDA 266
#define REG_PMBPTR_EL1 S3_0_C9_C10_1
#define HFGxTR_EL2_ERRIDR_EL1_MASK GENMASK(40, 40)
#define LPA_1000MSFAIL 0x8000
#define VM_BUG_ON(cond) BUILD_BUG_ON_INVALID(cond)
#define STA_PPSERROR 0x0800
#define SHT_PROGBITS 1
#define pud_leaf(pud) (pud_present(pud) && !pud_table(pud))
#define time_after32(a,b) ((s32)((u32)(b) - (u32)(a)) < 0)
#define TCR2_EL2_UNKN (UL(0))
#define EADV 68
#define ERANGE 34
#define pud_clear_bad(p4d) do { } while (0)
#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
#define REG_OSECCR_EL1 S2_0_C0_C6_2
#define HDFGRTR_EL2_TRBPTR_EL1_MASK GENMASK(54, 54)
#define __HDFGWTR_EL2_RES0 (BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | BIT(22) | BIT(9) | BIT(6))
#define raw_xchg arch_xchg
#define ktime_add_ns(kt,nsval) ((kt) + (nsval))
#define HCRX_EL2_FGTnXS_MASK GENMASK(4, 4)
#define SCTLR_EL1_TIDCP_MASK GENMASK(63, 63)
#define TCR_ORGN1_SHIFT 26
#define CLS_BITS 6
#define NT_386_TLS 0x200
#define ID_AA64ISAR1_EL1_LRCPC_MASK GENMASK(23, 20)
#define VM_EVENT_ITEM_H_INCLUDED 
#define LOREA_EL1_EA_47_16 GENMASK(47, 16)
#define topology_book_id(cpu) ((void)(cpu), -1)
#define HWCAP2_HBC (1UL << 44)
#define tasklist_empty() list_empty(&init_task.tasks)
#define arch_thp_swp_supported arch_thp_swp_supported
#define MDIO_PHY_ID_DEVAD 0x001f
#define CLIDR_EL1_Ctype7_WIDTH 3
#define ID_AA64ISAR2_EL1_PAC_frac_IMP UL(0b0001)
#define ESR_ELx_FSC_MTE (0x11)
#define _LINUX_KCSAN_H 
#define CALLER_ADDR0 ((unsigned long)ftrace_return_address0)
#define PMSIDR_EL1_ERND_MASK GENMASK(5, 5)
#define HCRX_EL2_MSCEn_WIDTH 1
#define _LINUX_RCULIST_BL_H 
#define __HFGRTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51))
#define TCR_T0SZ_OFFSET 0
#define PR_SET_DUMPABLE 4
#define SMPRIMAP_EL2_P13_WIDTH 4
#define QTYPE_MASK_GRP (1 << GRPQUOTA)
#define SECTIONS_MASK ((1UL << SECTIONS_WIDTH) - 1)
#define DT_RELCOUNT 0x6ffffffa
#define CALLER_ADDR2 ((unsigned long)ftrace_return_address(2))
#define ID_AFR0_EL1_IMPDEF2_WIDTH 4
#define ETHTOOL_COALESCE_MAX_FRAMES_IRQ (ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ | ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ)
#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
#define wait_event_interruptible_locked(wq,condition) ((condition) ? 0 : __wait_event_interruptible_locked(wq, condition, 0, do_wait_intr))
#define raw_sync_cmpxchg arch_sync_cmpxchg
#define SOL_NETROM 259
#define SEQCNT_MUTEX_ZERO(name,lock) SEQCOUNT_LOCKNAME_ZERO(name, lock)
#define MMF_VM_HUGEPAGE 17
#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
#define SECTIONS_PER_ROOT (PAGE_SIZE / sizeof (struct mem_section))
#define arch_ptrace_stop_needed() (0)
#define seqprop_const_ptr(s) __seqprop(s, const_ptr)(s)
#define FS_USERNS_MOUNT 8
#define ID_AA64ISAR2_EL1_RPRES GENMASK(7, 4)
#define HDFGWTR_EL2_TRBLIMITR_EL1_MASK GENMASK(52, 52)
#define ETXTBSY 26
#define __HCRX_EL2_RES0 (GENMASK(63, 16) | GENMASK(13, 12))
#define __ASM_HW_BREAKPOINT_H 
#define HFGITR_EL2_nGCSSTR_EL1_SHIFT 58
#define HDFGWTR_EL2_PMUSERENR_EL0_SHIFT 57
#define SYS_CLIDR_EL1_Op0 3
#define SYS_CLIDR_EL1_Op1 1
#define SYS_CLIDR_EL1_Op2 1
#define STATIC_CALL_TRAMP_PREFIX_LEN (sizeof(STATIC_CALL_TRAMP_PREFIX_STR) - 1)
#define TRBLIMITR_EL1_TM_IGNR UL(0b11)
#define ID_AA64MMFR0_EL1_TGRAN64_WIDTH 4
#define ARM64_FEATURE_FIELD_BITS 4
#define ESR_ELx_EC_FP_EXC64 (0x2C)
#define pte_unmap_unlock(pte,ptl) do { spin_unlock(ptl); pte_unmap(pte); } while (0)
#define ID_AA64PFR1_EL1_CSV2_frac_SIGNED false
#define RWH_WRITE_LIFE_EXTREME 5
#define MIDR_REV_RANGE(m,v,r_min,r_max) MIDR_RANGE(m, v, r_min, v, r_max)
#define HFGxTR_EL2_SCXTNUM_EL0 GENMASK(31, 31)
#define HFGxTR_EL2_SCXTNUM_EL1 GENMASK(30, 30)
#define _LINUX_MNT_IDMAPPING_H 
#define SYS_ID_AA64MMFR0_EL1_CRm 7
#define SYS_ID_AA64MMFR0_EL1_CRn 0
#define __ptr_clear_bit(nr,addr) ({ typecheck_pointer(*(addr)); __clear_bit(nr, (unsigned long *)(addr)); })
#define SCTLR_EL1_NMI_SHIFT 61
#define ID_AA64ISAR2_EL1_RPRFM GENMASK(51, 48)
#define ioread64be(p) ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })
#define HFGITR_EL2_TLBIVAAE1IS_SHIFT 31
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define _LINUX_LIST_BL_H 
#define ID_AA64MMFR1_EL1_CMOW_WIDTH 4
#define CTR_EL0_L1Ip GENMASK(15, 14)
#define TRBLIMITR_EL1_FM_FILL UL(0b00)
#define SO_INCOMING_NAPI_ID 56
#define user_mode(regs) (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
#define HDFGWTR_EL2_PMCR_EL0_MASK GENMASK(21, 21)
#define HWCAP2_SME_F32F32 (1 << 29)
#define ESR_ELx_EC_IMP_DEF (0x1f)
#define IPPROTO_ROUTING 43
#define TRBSR_EL1_TRG GENMASK(21, 21)
#define KMALLOC_SHIFT_HIGH (PAGE_SHIFT + 1)
#define MSEC_PER_SEC 1000L
#define insl insl
#define _KOBJECT_H_ 
#define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
#define HDFGRTR_EL2_TRCCNTVRn_MASK GENMASK(37, 37)
#define ifr_slave ifr_ifru.ifru_slave
#define CONFIG_IOMMU_IO_PGTABLE_LPAE 1
#define page_to_pfn __page_to_pfn
#define POLLRDBAND 0x0080
#define strtomem(dest,src) do { const size_t _dest_len = __builtin_object_size(dest, 1); const size_t _src_len = __builtin_object_size(src, 1); BUILD_BUG_ON(!__builtin_constant_p(_dest_len) || _dest_len == (size_t)-1); memcpy(dest, src, strnlen(src, min(_src_len, _dest_len))); } while (0)
#define CONFIG_WLAN_VENDOR_INTEL 1
#define BLKRAGET _IO(0x12,99)
#define __scalar_type_to_unsigned_cases(type) unsigned type: (unsigned type)0, signed type: (unsigned type)0
#define iter_iov_addr(iter) (iter_iov(iter)->iov_base + (iter)->iov_offset)
#define __NR_map_shadow_stack 453
#define NETIF_F_GSO_ESP __NETIF_F(GSO_ESP)
#define phydev_err_probe(_phydev,err,format,args...) dev_err_probe(&_phydev->mdio.dev, err, format, ##args)
#define SYS_DCZID_EL0_Op0 3
#define CONFIG_TCP_CONG_CUBIC 1
#define SYS_DCZID_EL0_Op2 7
#define iowrite32 iowrite32
#define REG_ID_AA64ISAR1_EL1 S3_0_C0_C6_1
#define SCHED_IDLE 5
#define raw_spin_lock_bh(lock) _raw_spin_lock_bh(lock)
#define PR_SME_VL_INHERIT (1 << 17)
#define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
#define Q_XGETNEXTQUOTA XQM_CMD(9)
#define __NR_inotify_add_watch 27
#define OSDTRRX_EL1_DTRRX GENMASK(31, 0)
#define DBG_HMC_HYP (1 << 13)
#define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
#define ID_MMFR2_EL1_UNKN (UL(0))
#define ID_ISAR2_EL1_Mult_MASK GENMASK(15, 12)
#define PTRACE_MODE_READ_REALCREDS (PTRACE_MODE_READ | PTRACE_MODE_REALCREDS)
#define R_ARM_NONE 0
#define HDFGRTR_EL2_TRBPTR_EL1 GENMASK(54, 54)
#define _Q_TAIL_IDX_BITS 2
#define ID_AA64DFR0_EL1_PMSVer_IMP UL(0b0001)
#define overflows_type(n,T) __builtin_choose_expr(__is_constexpr(n), __overflows_type_constexpr(n, T), __overflows_type(n, T))
#define LOGLEVEL_CRIT 2
#define ID_ISAR2_EL1_MultS_WIDTH 4
#define BLKIOOPT _IO(0x12,121)
#define for_each_cpu_andnot(cpu,mask1,mask2) for_each_andnot_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
#define _LINUX_RATELIMIT_TYPES_H 
#define ID_AA64DFR0_EL1_TraceBuffer_NI UL(0b0000)
#define __LINUX_SMP_TYPES_H 
#define PTRACE_GETSIGMASK 0x420a
#define DT_VALRNGLO 0x6ffffd00
#define SYS_ID_ISAR1_EL1_CRn 0
#define le64_to_cpup __le64_to_cpup
#define raw_cpu_dec_return(pcp) raw_cpu_add_return(pcp, -1)
#define ID_AA64ISAR2_EL1_MOPS_WIDTH 4
#define ID_AFR0_EL1_IMPDEF1_WIDTH 4
#define task_pt_regs(p) ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
#define PMSCR_EL1_CX_SHIFT 3
#define ID_AA64MMFR3_EL1_SNERR_FEAT_ANERR UL(0b0010)
#define PN_XNUM 0xffff
#define _INCLUDE_GUARD_LATENCYTOP_H_ 
#define OLD_DT_HIOS 0x6fffffff
#define TASK_STOPPED (TASK_WAKEKILL | __TASK_STOPPED)
#define dev_alert(dev,fmt,...) dev_printk_index_wrap(_dev_alert, KERN_ALERT, dev, dev_fmt(fmt), ##__VA_ARGS__)
#define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
#define CPACR_ELx_FPEN GENMASK(21, 20)
#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
#define SECCOMP_MODE_DISABLED 0
#define ELF_HWCAP cpu_get_elf_hwcap()
#define sigmask(sig) (1UL << ((sig) - 1))
#define ETHTOOL_PHY_EDPD_DISABLE 0
#define ARCH_TIMER_EVT_TRIGGER_SHIFT (4)
#define __exit __section(".exit.text") __exitused __cold notrace
#define PSR_c 0x000000ff
#define CONFIG_CRC32 1
#define PSR_f 0xff000000
#define ID_AA64DFR0_EL1_BRPs GENMASK(15, 12)
#define HFGxTR_EL2_UNKN (UL(0))
#define raw_cpu_inc_return(pcp) raw_cpu_add_return(pcp, 1)
#define PSR_s 0x00ff0000
#define SB_SILENT BIT(15)
#define PSR_x 0x0000ff00
#define SEMMAP SEMMNS
#define __LITTLE_ENDIAN 1234
#define NETLINK_NO_ENOBUFS 5
#define __get_and_null_ptr(p) ({ __auto_type __ptr = &(p); __auto_type __val = *__ptr; *__ptr = NULL; __val; })
#define pmdp_clear_flush_young_notify pmdp_clear_flush_young
#define CONFIG_PM_GENERIC_DOMAINS_OF 1
#define XA_CHUNK_SIZE (1UL << XA_CHUNK_SHIFT)
#define ID_AA64PFR1_EL1_MTEX_SHIFT 52
#define SVE_MAGIC 0x53564501
#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
#define GRND_NONBLOCK 0x0001
#define QIF_BLIMITS (1 << QIF_BLIMITS_B)
#define aligned_byte_mask(n) ((1UL << 8*(n))-1)
#define NETIF_F_GSO_IPXIP6 __NETIF_F(GSO_IPXIP6)
#define ARM64_WORKAROUND_CAVIUM_27456 87
#define MVFR0_EL1_FPTrap_IMP UL(0b0001)
#define __fix_address noinline __noclone
#define __NR_epoll_pwait 22
#define si_tid _sifields._timer._tid
#define udelay(n) ({ if (__builtin_constant_p(n)) { if ((n) / 20000 >= 1) __bad_udelay(); else __const_udelay((n) * 0x10c7ul); } else { __udelay(n); } })
#define HCR_AMVOFFEN (UL(1) << 51)
#define PMSFCR_EL1_FnE_SHIFT 3
#define PMBPTR_EL1_PTR_SHIFT 0
#define HCR_PTW (UL(1) << 2)
#define IPV6_FL_S_NONE 0
#define ID_AA64MMFR3_EL1_MEC_MASK GENMASK(31, 28)
#define ENCODING_NRZI 2
#define __late_clear_fixmap(idx) __set_fixmap((idx), 0, FIXMAP_PAGE_CLEAR)
#define PR_SET_TIMERSLACK 29
#define this_cpu_add_return(pcp,val) __pcpu_size_call_return2(this_cpu_add_return_, pcp, val)
#define MDSCR_EL1_TXU_MASK GENMASK(26, 26)
#define MAPCOUNT_ELF_CORE_MARGIN (5)
#define CLOCK_MONOTONIC_COARSE 6
#define TRBTRG_EL1_UNKN (UL(0))
#define HFGxTR_EL2_CONTEXTIDR_EL1 GENMASK(11, 11)
#define _LINUX_U64_STATS_SYNC_H 
#define ID_ISAR3_EL1_SynchPrim_EXCLUSIVE UL(0b0001)
#define SCTLR_EL1_nTWI_MASK GENMASK(16, 16)
#define HDFGRTR_EL2_PMSIDR_EL1_SHIFT 30
#define CONFIG_COMMON_CLK_APPLE_NCO 1
#define ID_AA64ZFR0_EL1_SM4_SHIFT 40
#define VM_SHARED 0x00000008
#define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk)
#define PMSCR_EL1_E0SPE_MASK GENMASK(0, 0)
#define wake_up_nr(x,nr) __wake_up(x, TASK_NORMAL, nr, NULL)
#define ICH_LR_GROUP (1ULL << 60)
#define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800
#define ID_AA64ISAR1_EL1_APA GENMASK(7, 4)
#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
#define CONFIG_ARCH_SUPPORTS_LTO_CLANG 1
#define ID_AA64ISAR1_EL1_API GENMASK(11, 8)
#define SIGINT 2
#define PMBPTR_EL1_RES0 (UL(0))
#define ID_AA64PFR0_EL1_ELx_64BIT_ONLY 0x1
#define ID_AA64PFR1_EL1_RAS_frac_SHIFT 12
#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
#define HFGITR_EL2_DCIVAC GENMASK(3, 3)
#define CAP_MKNOD 27
#define HDFGWTR_EL2_PMSWINC_EL0 GENMASK(20, 20)
#define for_each_zone_zonelist(zone,z,zlist,highidx) for_each_zone_zonelist_nodemask(zone, z, zlist, highidx, NULL)
#define HWCAP_ASIMDHP (1 << 10)
#define low_16_bits(x) ((x) & 0xFFFF)
#define IPPROTO_ICMPV6 58
#define ID_ISAR5_EL1_CRC32_WIDTH 4
#define BPF_PTR_POISON ((void *)(0xeB9FUL + POISON_POINTER_DELTA))
#define IORESOURCE_DMA_8AND16BIT (1<<0)
#define CONFIG_UNMAP_KERNEL_AT_EL0 1
#define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT)
#define CONFIG_RCU_STALL_COMMON 1
#define SG_DMA_SWIOTLB (1 << 1)
#define HDFGRTR_EL2_TRCAUXCTLR_WIDTH 1
#define PMSICR_EL1_COUNT_SHIFT 0
#define SO_RCVBUF 8
#define HFGITR_EL2_DCCVAC_SHIFT 54
#define raw_cpu_try_cmpxchg64(pcp,ovalp,nval) raw_cpu_generic_try_cmpxchg(pcp, ovalp, nval)
#define PR_SME_GET_VL 64
#define ___test_and_change_bit arch___test_and_change_bit
#define raw_cmpxchg arch_cmpxchg
#define IOPRIO_BAD_VALUE(val,max) ((val) < 0 || (val) >= (max))
#define swahb32 __swahb32
#define PAGE_SHARED __pgprot(_PAGE_SHARED)
#define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
#define ID_AA64MMFR1_EL1_ETS_WIDTH 4
#define ID_AA64AFR0_EL1_IMPDEF6_SHIFT 24
#define ZT_SIG_CONTEXT_SIZE(n) (sizeof(struct zt_context) + ZT_SIG_REGS_SIZE(n))
#define PMSIDR_EL1_MAXSIZE_MASK GENMASK(15, 12)
#define __static_assert(expr,msg,...) _Static_assert(expr, msg)
#define NT_ARM_TLS 0x401
#define device_lock_set_class(dev,key) do { struct device *__d = dev; dev_WARN_ONCE(__d, !lockdep_match_class(&__d->mutex, &__lockdep_no_validate__), "overriding existing custom lock class\n"); __device_lock_set_class(__d, #key, key); } while (0)
#define __INITDATA .section ".init.data","aw",%progbits
#define dynamic_dev_dbg(dev,fmt,...) do { if (0) dev_printk(KERN_DEBUG, dev, fmt, ##__VA_ARGS__); } while (0)
#define ID_MMFR3_EL1_MaintBcst_NI UL(0b0000)
#define SCTLR_EL1_UCI_SHIFT 26
#define LED_FUNCTION_WPS "wps"
#define GFP_DMA32 __GFP_DMA32
#define TCR_TxSZ_WIDTH 6
#define try_cmpxchg64_local(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg64_local(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define Elf_Sym Elf64_Sym
#define HFGxTR_EL2_nAMAIR2_EL1_SHIFT 63
#define ID_ISAR5_EL1_RDM GENMASK(27, 24)
#define MSG_ERRQUEUE 0x2000
#define ID_ISAR5_EL1_VCMA_NI UL(0b0000)
#define PIRx_ELx_Perm10_WIDTH 4
#define elf_read_implies_exec(ex,have_pt_gnu_stack) 0
#define p4d_leaf_size(x) P4D_SIZE
#define PER_CPU_ATTRIBUTES 
#define REG_ALLINT S3_0_C4_C3_0
#define NETLINK_EXT_ACK 11
#define EXPORT_PER_CPU_SYMBOL(var) EXPORT_SYMBOL(var)
#define dev_notice_ratelimited(dev,fmt,...) dev_level_ratelimited(dev_notice, dev, fmt, ##__VA_ARGS__)
#define JOBCTL_TRAPPING_BIT 21
#define idr_unlock_bh(idr) xa_unlock_bh(&(idr)->idr_rt)
#define ioread8 ioread8
#define fl4_dport uli.ports.dport
#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
#define CONFIG_SND_TIMER 1
#define AT_MINSIGSTKSZ 51
#define NT_ARM_ZA 0x40c
#define ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ BIT(7)
#define CMSG_USER_DATA(cmsg) ((void __user *)(cmsg) + sizeof(struct cmsghdr))
#define __constant_cpu_to_be16(x) ((__force __be16)___constant_swab16((x)))
#define ENOTBLK 15
#define PMSCR_EL2_PA_SHIFT 4
#define SCTLR_ELx_WXN (BIT(19))
#define NR_OPEN_DEFAULT BITS_PER_LONG
#define ID_AA64MMFR2_EL1_UAO_IMP UL(0b0001)
#define PMBSR_EL1_EC_FAULT_GPC UL(0b011110)
#define task_cred_xxx(task,xxx) ({ __typeof__(((struct cred *)NULL)->xxx) ___val; rcu_read_lock(); ___val = __task_cred((task))->xxx; rcu_read_unlock(); ___val; })
#define STATIC_KEY_FALSE_INIT (struct static_key_false){ .key = STATIC_KEY_INIT_FALSE, }
#define SMP_DEBUG_LOCKS_WARN_ON(c) DEBUG_LOCKS_WARN_ON(c)
#define key_fsuid_changed(c) do { } while(0)
#define _LINUX_MM_H 
#define NETIF_F_NOCACHE_COPY __NETIF_F(NOCACHE_COPY)
#define unsafe_put_compat_sigset(compat,set,label) do { compat_sigset_t __user *__c = compat; const sigset_t *__s = set; unsafe_copy_to_user(__c, __s, sizeof(*__c), label); } while (0)
#define CONFIG_ARCH_STACKWALK 1
#define EPROTOTYPE 91
#define preempt_disable() do { preempt_count_inc(); barrier(); } while (0)
#define ID_AA64PFR1_EL1_CSV2_frac_SHIFT 32
#define ENCAP_TYPE_ETHER 0
#define raw_smp_processor_id() (*raw_cpu_ptr(&cpu_number))
#define TRBLIMITR_EL1_FM GENMASK(2, 1)
#define CONFIG_NET_VENDOR_TI 1
#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
#define SIOCBONDINFOQUERY 0x8994
#define printk(fmt,...) printk_index_wrap(_printk, fmt, ##__VA_ARGS__)
#define CONFIG_GPIO_CDEV_V1 1
#define SCTLR_EL1_nAA_MASK GENMASK(6, 6)
#define SYS_PIRE0_EL12_CRm 2
#define SYS_PIRE0_EL12_CRn 10
#define test_task_syscall_work(t,fl) test_ti_thread_flag(task_thread_info(t), TIF_ ##fl)
#define ID_AA64ZFR0_EL1_BF16 GENMASK(23, 20)
#define node_remap(oldbit,old,new) __node_remap((oldbit), &(old), &(new), MAX_NUMNODES)
#define _LINUX_SOCKET_H 
#define SOL_PNPIPE 275
#define F_SEAL_WRITE 0x0008
#define netif_alert(priv,type,dev,fmt,args...) netif_level(alert, priv, type, dev, fmt, ##args)
#define container_of_const(ptr,type,member) _Generic(ptr, const typeof(*(ptr)) *: ((const type *)container_of(ptr, type, member)), default: ((type *)container_of(ptr, type, member)) )
#define DCACHE_PAR_LOOKUP 0x10000000
#define SECTION_HAS_MEM_MAP BIT(SECTION_HAS_MEM_MAP_BIT)
#define SYS_ACCEPT4 18
#define ID_AA64MMFR1_EL1_LO_NI UL(0b0000)
#define ALIGN(x,a) __ALIGN_KERNEL((x), (a))
#define VM_DONTCOPY 0x00020000
#define AF_NETROM 6
#define ID_PFR1_EL1_GIC GENMASK(31, 28)
#define __ARCH_WANT_RENAMEAT 
#define SMPRI_EL1_RES0 (UL(0) | GENMASK_ULL(63, 4))
#define SMPRI_EL1_RES1 (UL(0))
#define HDFGWTR_EL2_nBRBDATA GENMASK(61, 61)
#define DEFINE_RES_IRQ(_irq) DEFINE_RES_IRQ_NAMED((_irq), NULL)
#define MMF_HAS_PINNED 27
#define EBADCOOKIE 523
#define CONFIG_EDAC_SUPPORT 1
#define ID_AA64MMFR0_EL1_TGRAN16 GENMASK(23, 20)
#define __member_size(p) __builtin_dynamic_object_size(p, 1)
#define KERN_SOH "\001"
#define dev_printk_index_wrap(_p_func,level,dev,fmt,...) ({ dev_printk_index_emit(level, fmt); _p_func(dev, fmt, ##__VA_ARGS__); })
#define htonl(x) ___htonl(x)
#define ID_ISAR4_EL1_SynchPrim_frac_NI UL(0b0000)
#define htons(x) ___htons(x)
#define MDSCR_EL1_MDE GENMASK(15, 15)
#define IPV6_MTU_DISCOVER 23
#define arch_read_lock(l) queued_read_lock(l)
#define __RWSEM_COUNT_INIT(name) .count = ATOMIC_LONG_INIT(RWSEM_UNLOCKED_VALUE)
#define MII_ESTATUS 0x0f
#define xa_for_each_range(xa,index,entry,start,last) for (index = start, entry = xa_find(xa, &index, last, XA_PRESENT); entry; entry = xa_find_after(xa, &index, last, XA_PRESENT))
#define HCRX_EL2_SCTLR2En GENMASK(15, 15)
#define HFGxTR_EL2_nMAIR2_EL1_SHIFT 62
#define ID_AA64SMFR0_EL1_F16F16 GENMASK(42, 42)
#define AH_V6_FLOW 0x0b
#define __SRCU_USAGE_INIT(name) { .lock = __SPIN_LOCK_UNLOCKED(name.lock), .srcu_gp_seq_needed = -1UL, .work = __DELAYED_WORK_INITIALIZER(name.work, NULL, 0), }
#define dev_warn_once(dev,fmt,...) dev_level_once(dev_warn, dev, fmt, ##__VA_ARGS__)
#define SH_DIV(NOM,DEN,LSH) ( (((NOM) / (DEN)) << (LSH)) + ((((NOM) % (DEN)) << (LSH)) + (DEN) / 2) / (DEN))
#define read_unlock_irqrestore(lock,flags) do { typecheck(unsigned long, flags); _raw_read_unlock_irqrestore(lock, flags); } while (0)
#define ID_DFR0_EL1_CopTrc_MASK GENMASK(15, 12)
#define PSR_AA32_DIT_BIT 0x01000000
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
#define SMPRIMAP_EL2_P10_WIDTH 4
#define IORESOURCE_IRQ_HIGHLEVEL (1<<2)
#define XA_PRESENT ((__force xa_mark_t)8U)
#define SYS_PMSCR_EL1_CRn 9
#define RADIX_TREE_TAG_LONGS XA_MARK_LONGS
#define PMSCR_EL1_E1SPE GENMASK(1, 1)
#define SIZE_MAX (~(size_t)0)
#define hashlen_len(hashlen) ((u32)((hashlen) >> 32))
#define ARM64_WORKAROUND_2064142 76
#define SO_REUSEADDR 2
#define ITER_SOURCE 1
#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000
#define ID_AA64MMFR3_EL1_S1POE_SIGNED false
#define __NR_msgsnd 189
#define pte_none(pte) (!pte_val(pte))
#define percpu_counter_init_many(fbc,value,gfp,nr_counters) ({ static struct lock_class_key __key; __percpu_counter_init_many(fbc, value, gfp, nr_counters, &__key); })
#define ID_MMFR2_EL1_MemBarr GENMASK(23, 20)
#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
#define PMSIDR_EL1_ERND GENMASK(5, 5)
#define PF_RDS AF_RDS
#define CONFIG_PROC_SYSCTL 1
#define NT_ARM_ZT 0x40d
#define ID_ISAR0_EL1_BitField_WIDTH 4
#define SHMMAX (ULONG_MAX - (1UL << 24))
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
#define ARCH_FTRACE_SHIFT_STACK_TRACER 1
#define HCRX_EL2_FnXS_WIDTH 1
#define PHYS_PFN(x) ((unsigned long)((x) >> PAGE_SHIFT))
#define BUS_ADRERR 2
#define __NR_clock_settime 112
#define param_check_ulong(name,p) __param_check(name, p, unsigned long)
#define MDIO_PMA_RXDET 10
#define NETLINK_XFRM 6
#define HFGxTR_EL2_AMAIR_EL1_SHIFT 3
#define IPV6_FLOWINFO_SEND 33
#define ID_AA64SMFR0_EL1_F16F32 GENMASK(35, 35)
#define PMSCR_EL2_E0HSPE_WIDTH 1
#define __constant_cpu_to_be64(x) ((__force __be64)___constant_swab64((x)))
#define SCTLR_EL1_TIDCP_WIDTH 1
#define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
#define ID_AA64MMFR2_EL1_UAO_SIGNED false
#define PMBLIMITR_EL1_FM_DISCARD UL(0b10)
#define FIXADDR_TOT_START (FIXADDR_TOP - FIXADDR_TOT_SIZE)
#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
#define SIOCSIFNAME 0x8923
#define compiletime_assert_rwonce_type(t) compiletime_assert(__native_word(t) || sizeof(t) == sizeof(long long), "Unsupported access size for {READ,WRITE}_ONCE().")
#define __types_ok(x,y) (__is_signed(x) == __is_signed(y) || __is_signed((x) + 0) == __is_signed((y) + 0) || __is_noneg_int(x) || __is_noneg_int(y))
#define kunmap_atomic(__addr) do { BUILD_BUG_ON(__same_type((__addr), struct page *)); __kunmap_atomic(__addr); } while (0)
#define ID_MMFR2_EL1_UniTLB_BY_VA UL(0b0001)
#define CONFIG_DECOMPRESS_ZSTD 1
#define ID_AA64MMFR2_EL1_NV_SHIFT 24
#define CONFIG_INIT_ENV_ARG_LIMIT 32
#define LED_COLOR_ID_CYAN 13
#define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
#define NT_PRPSINFO 3
#define PMSIDR_EL1_PBT_WIDTH 1
#define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
#define O_APPEND 00002000
#define ETHTOOL_GSTATS 0x0000001d
#define CONFIG_HAVE_EBPF_JIT 1
#define CLIDR_EL1_LoUU_WIDTH 3
#define ID_AA64ZFR0_EL1_F32MM_IMP UL(0b0001)
#define SCTLR_EL1_TMT0_MASK GENMASK(50, 50)
#define KERNEL_HWCAP_ASIMDRDM __khwcap_feature(ASIMDRDM)
#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
#define CONFIG_BITREVERSE 1
#define __NR_unshare 97
#define ID_ISAR1_EL1_Extend_NI UL(0b0000)
#define REG_ID_AA64SMFR0_EL1 S3_0_C0_C4_5
#define next_memory_node(nid) (MAX_NUMNODES)
#define CPACR_EL1_FPEN_EL1EN (BIT(20))
#define ID_AA64PFR0_EL1_RME_MASK GENMASK(55, 52)
#define IOCB_APPEND (__force int) RWF_APPEND
#define SYS_SENDTO 11
#define NL_SET_ERR_MSG_MOD(extack,msg) NL_SET_ERR_MSG((extack), KBUILD_MODNAME ": " msg)
#define __NR_lremovexattr 15
#define DT_RELA 7
#define VFS_CAP_U32_1 1
#define ID_AA64AFR0_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_AA64AFR0_EL1_RES1 (UL(0))
#define lock_map_sync(l) lock_sync(l, 0, 0, 1, NULL, _THIS_IP_)
#define ID_MMFR2_EL1_L1HvdFG_MASK GENMASK(3, 0)
#define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
#define ID_ISAR4_EL1_Barrier_IMP UL(0b0001)
#define ID_ISAR3_EL1_TrueNOP_WIDTH 4
#define CHECKSUM_PARTIAL 3
#define ID_AA64MMFR0_EL1_TGRAN64 GENMASK(27, 24)
#define CONFIG_IRQ_DOMAIN_HIERARCHY 1
#define I_WILL_FREE (1 << 4)
#define VFS_CAP_U32_3 2
#define QCOM_CPU_PART_FALKOR_V1 0x800
#define CONFIG_HAVE_IRQ_TIME_ACCOUNTING 1
#define pud_set_fixmap_offset(pgdp,addr) ((pud_t *)pgdp)
#define ID_ISAR4_EL1_Barrier GENMASK(19, 16)
#define ID_AA64ISAR0_EL1_SHA1_SHIFT 8
#define CONFIG_BINARY_PRINTF 1
#define CONFIG_RUST_OVERFLOW_CHECKS 1
#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
#define ID_ISAR3_EL1_SVC_MASK GENMASK(11, 8)
#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
#define CONFIG_CONTEXT_TRACKING 1
#define absolute_pointer(val) RELOC_HIDE((void *)(val), 0)
#define PAGE_KERNEL_ROX __pgprot(_PAGE_KERNEL_ROX)
#define for_each_andnot_bit(bit,addr1,addr2,size) for ((bit) = 0; (bit) = find_next_andnot_bit((addr1), (addr2), (size), (bit)), (bit) < (size); (bit)++)
#define __HFGITR_EL2_RES0 GENMASK(63, 57)
#define TCR2_EL1x_PnCH GENMASK(0, 0)
#define ENCODING_FM_MARK 3
#define SLAB_CONSISTENCY_CHECKS ((slab_flags_t __force)0x00000100U)
#define PTRACE_O_EXITKILL (1 << 20)
#define ID_AA64MMFR2_EL1_CCIDX GENMASK(23, 20)
#define MODULE_ALIAS_NET_PF_PROTO_NAME(pf,proto,name) MODULE_ALIAS("net-pf-" __stringify(pf) "-proto-" __stringify(proto) name)
#define current_cap() (current_cred_xxx(cap_effective))
#define CONFIG_XPS 1
#define SO_MARK 36
#define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
#define ENOPARAM 519
#define _LINUX_SWAB_H 
#define _ASM_GENERIC_BITOPS_ATOMIC_H_ 
#define CAP_NET_BROADCAST 11
#define __preempt_count_inc() __preempt_count_add(1)
#define ID_AA64ISAR0_EL1_RDM_IMP UL(0b0001)
#define MONOTONIC_RES_NSEC LOW_RES_NSEC
#define ID_ISAR5_EL1_SHA2_NI UL(0b0000)
#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
#define PUD_SHIFT P4D_SHIFT
#define ID_AA64DFR0_EL1_TraceBuffer_WIDTH 4
#define SIOCDELRT 0x890C
#define PRIO_PROCESS 0
#define CONFIG_OF_RESERVED_MEM 1
#define __convert_uid(size,uid) (uid)
#define flowi4_l3mdev __fl_common.flowic_l3mdev
#define EPOLLONESHOT ((__force __poll_t)(1U << 30))
#define __ASM_SECTIONS_H 
#define skb_queue_walk(queue,skb) for (skb = (queue)->next; skb != (struct sk_buff *)(queue); skb = skb->next)
#define __NR_setresuid 147
#define SIOCGIFDSTADDR 0x8917
#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
#define REG_FAR_EL12 S3_5_C6_C0_0
#define USHRT_MAX ((unsigned short)~0U)
#define EM_PERF_STATE_INEFFICIENT BIT(0)
#define ETIMEDOUT 110
#define node_set_offline(node) node_clear_state((node), N_ONLINE)
#define IPV6_PRIORITY_CONTROL 0x0700
#define PCMCIA_DEV_ID_MATCH_FUNCTION 0x0008
#define HFGxTR_EL2_nSMPRI_EL1_MASK GENMASK(54, 54)
#define readw_relaxed_poll_timeout(addr,val,cond,delay_us,timeout_us) readx_poll_timeout(readw_relaxed, addr, val, cond, delay_us, timeout_us)
#define ID_ISAR6_EL1_SB_SIGNED false
#define SIPHASH_PERMUTATION(a,b,c,d) ( (a) += (b), (b) = rol64((b), 13), (b) ^= (a), (a) = rol64((a), 32), (c) += (d), (d) = rol64((d), 16), (d) ^= (c), (a) += (d), (d) = rol64((d), 21), (d) ^= (a), (c) += (b), (b) = rol64((b), 17), (b) ^= (c), (c) = rol64((c), 32))
#define pr_info(fmt,...) printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__)
#define CONFIG_NEED_DMA_MAP_STATE 1
#define ESR_ELx_SME_ISS_ZA_DISABLED 3
#define DCACHE_MANAGE_TRANSIT 0x00040000
#define SEQCNT_RWLOCK_ZERO(name,lock) SEQCOUNT_LOCKNAME_ZERO(name, lock)
#define MVFR0_EL1_FPShVec GENMASK(27, 24)
#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
#define S_KERNEL_FILE (1 << 17)
#define PTRACE_SETREGSET 0x4205
#define IOPRIO_NR_CLASSES 8
#define ftrace_free_filter(ops) do { } while (0)
#define __pfn_to_page(pfn) (vmemmap + (pfn))
#define rb_to_skb(rb) rb_entry_safe(rb, struct sk_buff, rbnode)
#define ID_AA64ISAR1_EL1_SPECRES_WIDTH 4
#define ID_AA64PFR1_EL1_GCS_IMP UL(0b0001)
#define IORESOURCE_WINDOW 0x00200000
#define ID_AA64MMFR3_EL1_MEC_NI UL(0b0000)
#define ID_PFR1_EL1_Virtualization_MASK GENMASK(15, 12)
#define SYS_CPACR_EL12_Op0 3
#define SYS_CPACR_EL12_Op1 5
#define SYS_CPACR_EL12_Op2 2
#define _DYNAMIC_DEBUG_H 
#define readl readl
#define task_is_traced(task) ((READ_ONCE(task->jobctl) & JOBCTL_TRACED) != 0)
#define PTRACE_INTERRUPT 0x4207
#define readq readq
#define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
#define ARM64_HAS_GIC_CPUIF_SYSREGS 29
#define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
#define LOCK_SECTION_END ".previous\n\t"
#define ID_MMFR4_EL1_AC2_MASK GENMASK(7, 4)
#define SHN_COMMON 0xfff2
#define SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(suspend_fn,resume_fn) 
#define HWCAP_SHA1 (1 << 5)
#define HWCAP_SHA2 (1 << 6)
#define HWCAP_SHA3 (1 << 17)
#define AT_UID 11
#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
#define _LINUX_PERSONALITY_H 
#define ELF_PLATFORM ("aarch64")
#define NETIF_F_GSO_UDP_TUNNEL_CSUM __NETIF_F(GSO_UDP_TUNNEL_CSUM)
#define __NR_perf_event_open 241
#define set_pte_at(mm,addr,ptep,pte) set_ptes(mm, addr, ptep, pte, 1)
#define NLMSG_ERROR 0x2
#define CONFIG_GENERIC_CLOCKEVENTS 1
#define TRBSR_EL1_IRQ_MASK GENMASK(22, 22)
#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001
#define NETIF_F_GRO_UDP_FWD __NETIF_F(GRO_UDP_FWD)
#define FS_QSTATV_VERSION1 1
#define SHMMIN 1
#define FICLONERANGE _IOW(0x94, 13, struct file_clone_range)
#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
#define IN6ADDR_LINKLOCAL_ALLROUTERS_INIT { { { 0xff,2,0,0,0,0,0,0,0,0,0,0,0,0,0,2 } } }
#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
#define __NR_vhangup 58
#define HDFGRTR_EL2_PMSFCR_EL1 GENMASK(28, 28)
#define CONFIG_ARCH_HAS_TICK_BROADCAST 1
#define HDFGWTR_EL2_TRCSSCSRn_SHIFT 46
#define TRBMAR_EL1_Attr_MASK GENMASK(7, 0)
#define ELF_PLATFORM_SIZE 16
#define TRBSR_EL1_TRG_SHIFT 21
#define ID_ISAR4_EL1_Unpriv_SHIFT 0
#define PMBSR_EL1_EC_BUF UL(0b000000)
#define hlist_nulls_entry_safe(ptr,type,member) ({ typeof(ptr) ____ptr = (ptr); !is_a_nulls(____ptr) ? hlist_nulls_entry(____ptr, type, member) : NULL; })
#define MASTER_SLAVE_STATE_UNKNOWN 1
#define SYS_MPAMVPM6_EL2 __SYS__MPAMVPMx_EL2(6)
#define SVE_PT_FPSIMD_SIZE(vq,flags) (sizeof(struct user_fpsimd_state))
#define DQ_RELEASING_B 6
#define __BITS_PER_LONG 64
#define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
#define for_each_clear_bit(bit,addr,size) for ((bit) = 0; (bit) = find_next_zero_bit((addr), (size), (bit)), (bit) < (size); (bit)++)
#define EXPORT_NS_GPL_DEV_PM_OPS(name,ns) _EXPORT_DEV_PM_OPS(name, "GPL", #ns)
#define SMPRIMAP_EL2_P0_SHIFT 0
#define SYSCALL_ALIAS(alias,name) asm( ".globl " __stringify(alias) "\n\t" ".set   " __stringify(alias) "," __stringify(name))
#define SYS_TRBBASER_EL1_CRn 9
#define HDFGRTR_EL2_TRCIMSPECn_SHIFT 41
#define CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ 1
#define __releases(x) 
#define BLKSECTGET _IO(0x12,103)
#define ID_AA64ISAR1_EL1_APA_FPAC UL(0b0100)
#define get_pageblock_migratetype(page) get_pfnblock_flags_mask(page, page_to_pfn(page), MIGRATETYPE_MASK)
#define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
#define __ASM_TLBFLUSH_H 
#define PF_ALG AF_ALG
#define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
#define ID_ISAR3_EL1_T32EE_NI UL(0b0000)
#define PMBLIMITR_EL1_E GENMASK(0, 0)
#define PR_TSC_ENABLE 1
#define HFGxTR_EL2_ERXMISCn_EL1_WIDTH 1
#define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT)
#define VM_MERGEABLE 0x80000000
#define TIMER_CPUMASK 0x0003FFFF
#define ID_AA64ZFR0_EL1_F32MM GENMASK(55, 52)
#define HFGITR_EL2_nBRBINJ GENMASK(55, 55)
#define ENCODING_NRZ 1
#define PMSEVFR_EL1_E_SHIFT 0
#define TRBLIMITR_EL1_TM GENMASK(4, 3)
#define BLKSSZGET _IO(0x12,104)
#define PIRx_ELx_Perm9_SHIFT 36
#define HWCAP2_BTI (1 << 17)
#define DT_DEBUG 21
#define RCU_NEXT_TAIL 3
#define EX_DATA_REG_ZERO GENMASK(9, 5)
#define clamp_val(val,lo,hi) clamp_t(typeof(val), val, lo, hi)
#define IS_IMMUTABLE(inode) ((inode)->i_flags & S_IMMUTABLE)
#define QFMT_OCFS2 3
#define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define FS_COMPR_FL 0x00000004
#define __NR_clock_getres 114
#define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
#define PAGECACHE_TAG_DIRTY XA_MARK_0
#define ID_AA64ISAR1_EL1_FCMA_WIDTH 4
#define MDIO_PMA_CTRL2_10GBCX4 0x0000
#define ifr_bandwidth ifr_ifru.ifru_ivalue
#define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
#define SYS_PMBIDR_EL1_CRm 10
#define ID_AA64DFR0_EL1_PMSVer_SIGNED false
#define p4d_leaf(x) 0
#define HDFGRTR_EL2_TRCAUTHSTATUS_WIDTH 1
#define ETHTOOL_GTUNABLE 0x00000048
#define SYS_PMBIDR_EL1_CRn 9
#define __NR_timer_delete 111
#define DEFINE_SEQLOCK(sl) seqlock_t sl = __SEQLOCK_UNLOCKED(sl)
#define BMSR_ANEGCAPABLE 0x0008
#define __change_bit(nr,addr) bitop(___change_bit, nr, addr)
#define FS_DISALLOW_NOTIFY_PERM 16
#define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
#define DEFINE_STATIC_KEY_FALSE_RO(name) struct static_key_false name __ro_after_init = STATIC_KEY_FALSE_INIT
#define __LINUX_RCU_NODE_TREE_H 
#define SUBSECTION_ALIGN_DOWN(pfn) ((pfn) & PAGE_SUBSECTION_MASK)
#define pgprot_modify pgprot_modify
#define AF_INET6 10
#define ___wait_var_event(var,condition,state,exclusive,ret,cmd) ({ __label__ __out; struct wait_queue_head *__wq_head = __var_waitqueue(var); struct wait_bit_queue_entry __wbq_entry; long __ret = ret; init_wait_var_entry(&__wbq_entry, var, exclusive ? WQ_FLAG_EXCLUSIVE : 0); for (;;) { long __int = prepare_to_wait_event(__wq_head, &__wbq_entry.wq_entry, state); if (condition) break; if (___wait_is_interruptible(state) && __int) { __ret = __int; goto __out; } cmd; } finish_wait(__wq_head, &__wbq_entry.wq_entry); __out: __ret; })
#define HPAGE_PUD_SIZE ({ BUILD_BUG(); 0; })
#define ID_AA64PFR0_EL1_UNKN (UL(0))
#define PF_KCM AF_KCM
#define VM_BUG_ON_VMA(cond,vma) VM_BUG_ON(cond)
#define MMCF_AARCH32 0x1
#define FT_SOCK 6
#define SOL_NETLINK 270
#define copy_user_page(to,from,vaddr,pg) copy_page(to, from)
#define ET_LOPROC 0xff00
#define ID_AA64PFR0_EL1_GIC_SHIFT 24
#define might_sleep_if(cond) do { if (cond) might_sleep(); } while (0)
#define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
#define STA_CLOCKERR 0x1000
#define ID_AA64ISAR2_EL1_CLRBHB_SIGNED false
#define ID_AA64MMFR0_EL1_TGRAN16_2_WIDTH 4
#define LOCKDEP_RECURSION_MASK (LOCKDEP_OFF - 1)
#define ID_MMFR1_EL1_L1TstCln GENMASK(27, 24)
#define QTREE_INIT_ALLOC 4
#define SHMMNI 4096
#define COMPAT_HWCAP_JAVA (1 << 8)
#define QUOTA_NL_BHARDBELOW 9
#define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
#define CAP_AUDIT_CONTROL 30
#define ID_AA64ISAR1_EL1_BF16_SIGNED false
#define HDFGRTR_EL2_DBGWCRn_EL1 GENMASK(2, 2)
#define CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE 1
#define DECLARE_DEFERRABLE_WORK(n,f) struct delayed_work n = __DELAYED_WORK_INITIALIZER(n, f, TIMER_DEFERRABLE)
#define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000
#define ID_AA64MMFR2_EL1_UAO_NI UL(0b0000)
#define idr_for_each_entry_continue(idr,entry,id) for ((entry) = idr_get_next((idr), &(id)); entry; ++id, (entry) = idr_get_next((idr), &(id)))
#define NT_PPC_TM_CFPR 0x109
#define MMF_DUMP_HUGETLB_PRIVATE 7
#define SHRINKER_MEMCG_AWARE BIT(3)
#define ID_AA64PFR0_EL1_CSV3_MASK GENMASK(63, 60)
#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100
#define __NR_fsopen 430
#define CPP_ASMLINKAGE 
#define PF_UNIX AF_UNIX
#define CHECK_DATA_CORRUPTION(condition,fmt,...) check_data_corruption(({ bool corruption = unlikely(condition); if (corruption) { if (IS_ENABLED(CONFIG_BUG_ON_DATA_CORRUPTION)) { pr_err(fmt, ##__VA_ARGS__); BUG(); } else WARN(1, fmt, ##__VA_ARGS__); } corruption; }))
#define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr)
#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
#define TRBLIMITR_EL1_XE GENMASK(6, 6)
#define ID_MMFR1_EL1_L1Hvd GENMASK(19, 16)
#define SA_ONSTACK 0x08000000
#define ID_AA64ISAR2_EL1_WFxT_WIDTH 4
#define PMSCR_EL1_PA_WIDTH 1
#define atomic64_cond_read_acquire(v,c) smp_cond_load_acquire(&(v)->counter, (c))
#define ID_ISAR3_EL1_TabBranch_IMP UL(0b0001)
#define ID_AA64ISAR0_EL1_SM4_SHIFT 40
#define MDSCR_EL1_RXfull GENMASK(30, 30)
#define SYS_SOCKET 1
#define ETH_P_WCCP 0x883E
#define CONFIG_NOP_TRACER 1
#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
#define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
#define CONFIG_NET_VENDOR_ALTEON 1
#define AT_HANDLE_FID AT_REMOVEDIR
#define ID_AA64MMFR0_EL1_BIGEND_IMP UL(0b0001)
#define __ASM_FTRACE_H 
#define SYS_ID_MMFR4_EL1_Op0 3
#define SYS_ID_MMFR4_EL1_Op1 0
#define SYS_ID_MMFR4_EL1_Op2 6
#define COMPAT_USER_HZ 100
#define MNT_EXPIRE 0x00000004
#define ID_ISAR2_EL1_LoadStore_WIDTH 4
#define ID_ISAR0_EL1_Coproc_MRC UL(0b0001)
#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
#define CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS 14
#define ID_AA64MMFR2_EL1_NV_NI UL(0b0000)
#define SYS_PMSIDR_EL1_CRm 9
#define SYS_PMSIDR_EL1_CRn 9
#define hlist_entry(ptr,type,member) container_of(ptr,type,member)
#define preempt_fold_need_resched() do { if (tif_need_resched()) set_preempt_need_resched(); } while (0)
#define MDIO_AN_T1_LP_L_FORCE_MS 0x1000
#define SVCR_ZA GENMASK(1, 1)
#define __ASM_ARCH_TIMER_H 
#define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
#define NT_PRSTATUS 1
#define TRBSR_EL1_TRG_WIDTH 1
#define ID_AA64PFR1_EL1_THE_SIGNED false
#define SCTLR_EL1_EnIA_MASK GENMASK(31, 31)
#define virt_wmb() do { kcsan_wmb(); __smp_wmb(); } while (0)
#define node_page_state(node,item) global_node_page_state(item)
#define CONFIG_GENERIC_SMP_IDLE_THREAD 1
#define SYS_CSSELR_EL1_Op0 3
#define SYS_CSSELR_EL1_Op1 2
#define SYS_CSSELR_EL1_Op2 0
#define MVFR1_EL1_FPFtZ GENMASK(3, 0)
#define HWCAP_FCMA (1 << 14)
#define SPARC_ETH_GSET ETHTOOL_GSET
#define HDFGWTR_EL2_DBGWVRn_EL1_MASK GENMASK(3, 3)
#define ID_MMFR1_EL1_L1UniSW_CLEAN UL(0b0001)
#define __SWP_TYPE_BITS 5
#define PR_UNALIGN_NOPRINT 1
#define ID_AA64MMFR3_EL1_AIE_SIGNED false
#define MDSCR_EL1_TTA_MASK GENMASK(33, 33)
#define __gnu_inline __attribute__((__gnu_inline__))
#define lockdep_assert_held_once(l) lockdep_assert_once(lockdep_is_held(l) != LOCK_STATE_NOT_HELD)
#define CONFIG_DEBUG_SPINLOCK 1
#define param_check_charp(name,p) __param_check(name, p, char *)
#define MDIO_USXGMII_10G 0x0600
#define WQ_FLAG_EXCLUSIVE 0x01
#define PR_SET_MDWE 65
#define __le64_to_cpus(x) do { (void)(x); } while (0)
#define CONFIG_WLAN_VENDOR_MICROCHIP 1
#define HCRX_EL2_VFNMI_SHIFT 8
#define SIOCSIFFLAGS 0x8914
#define ID_MMFR2_EL1_HvdTLB GENMASK(15, 12)
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define PHY_FORCE_TIMEOUT 10
#define ARM_KERNEL_STEP_NONE 0
#define __dma_mb() dmb(osh)
#define HDFGRTR_EL2_PMMIR_EL1_SHIFT 22
#define poll_to_key(m) ((void *)(__force uintptr_t)(__poll_t)(m))
#define typeof_member(T,m) typeof(((T*)0)->m)
#define asmlinkage_protect(n,ret,args...) do { } while (0)
#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000
#define PTRACE_PEEKUSR 3
#define SEGMENT_ALIGN SZ_64K
#define EPERM 1
#define ID_AA64ISAR0_EL1_TS_FLAGM UL(0b0001)
#define PSR_AA32_MODE_SVC 0x00000013
#define preempt_disable_notrace() do { __preempt_count_inc(); barrier(); } while (0)
#define smp_mb() do { kcsan_mb(); __smp_mb(); } while (0)
#define NT_VMCOREDD 0x700
#define stop_critical_timings() do { } while (0)
#define SECCOMP_SET_MODE_FILTER 1
#define SYS_PMSNEVFR_EL1_CRm 9
#define SYS_PMSNEVFR_EL1_CRn 9
#define IPV6_PRIORITY_BULK 0x0400
#define KUNIT_ASSERT_NE_MSG(test,left,right,fmt,...) KUNIT_BINARY_INT_ASSERTION(test, KUNIT_ASSERTION, left, !=, right, fmt, ##__VA_ARGS__)
#define HFGxTR_EL2_MAIR_EL1_WIDTH 1
#define NETIF_F_GSO_PARTIAL __NETIF_F(GSO_PARTIAL)
#define read_sysreg_s(r) ({ u64 __val; u32 __maybe_unused __check_r = (u32)(r); asm volatile(__mrs_s("%0", r) : "=r" (__val)); __val; })
#define HFGITR_EL2_DCISW_SHIFT 4
#define SHRINKER_NUMA_AWARE BIT(2)
#define XA_CHUNK_MASK (XA_CHUNK_SIZE - 1)
#define topology_cluster_cpumask(cpu) (&cpu_topology[cpu].cluster_sibling)
#define MNT_SHRINKABLE 0x100
#define SYS_HFGRTR_EL2_CRm 1
#define SYS_HFGRTR_EL2_CRn 1
#define ID_AA64MMFR3_EL1_SDERR_SIGNED false
#define CPTR_EL2_TSM (1 << 12)
#define __NR_kexec_file_load 294
#define ID_MMFR0_EL1_VMSA_MASK GENMASK(3, 0)
#define EXPORT_DEV_PM_OPS(name) _EXPORT_DEV_PM_OPS(name, "", "")
#define HZ_TO_MSEC_SHR32 29
#define ARM64_LSE_ATOMIC_INSN(llsc,lse) ALTERNATIVE(llsc, __LSE_PREAMBLE lse, ARM64_HAS_LSE_ATOMICS)
#define SUBSECTION_SIZE (1UL << SUBSECTION_SHIFT)
#define TRBPTR_EL1_RES0 (UL(0))
#define CONFIG_ARCH_INLINE_SPIN_TRYLOCK 1
#define SO_DETACH_BPF SO_DETACH_FILTER
#define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
#define HFGxTR_EL2_CTR_EL0_SHIFT 14
#define CONFIG_RD_BZIP2 1
#define _UAPI__ASM_PTRACE_H 
#define DECLARE_SWAIT_QUEUE_HEAD(name) struct swait_queue_head name = __SWAIT_QUEUE_HEAD_INITIALIZER(name)
#define ADJ_OFFSET_SINGLESHOT 0x0001
#define PIRx_ELx_Perm7_MASK GENMASK(31, 28)
#define SCTLR_EL1_CP15BEN_SHIFT 5
#define preempt_count_dec() preempt_count_sub(1)
#define __UINT16_C(c) c
#define DACR32_EL2_D10_MASK GENMASK(21, 20)
#define IS_SETLK(cmd) (IS_SETLK32(cmd) || IS_SETLK64(cmd))
#define IORESOURCE_READONLY 0x00004000
#define HDFGWTR_EL2_PMSIRR_EL1_MASK GENMASK(31, 31)
#define __inline_maybe_unused __maybe_unused
#define QTREE_DEL_REWRITE 6
#define SLAB_HWCACHE_ALIGN ((slab_flags_t __force)0x00002000U)
#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
#define DACR32_EL2_D15_SHIFT 30
#define DCACHE_NOKEY_NAME 0x02000000
#define HFGxTR_EL2_nRCWMASK_EL1 GENMASK(56, 56)
#define ARM_CPU_IMP_CAVIUM 0x43
#define PR_ENDIAN_PPC_LITTLE 2
#define CONFIG_SERIO_LIBPS2 1
#define __ASM_MODULE_H 
#define SCTLR_EL1_EOS_MASK GENMASK(11, 11)
#define PSR_AA32_MODE_SYS 0x0000001f
#define NT_ARM_PAC_MASK 0x406
#define ID_PFR1_EL1_Security_WIDTH 4
#define RX_CLS_LOC_ANY 0xffffffff
#define ___GFP_FS 0x80u
#define pstate_field(op1,op2) ((op1) << Op1_shift | (op2) << Op2_shift)
#define IS_ROOT(x) ((x) == (x)->d_parent)
#define UEVENT_HELPER_PATH_LEN 256
#define __SVE_VQ_BYTES 16
#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1,crm) (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
#define PMSIDR_EL1_MAXSIZE GENMASK(15, 12)
#define NETIF_F_FRAGLIST __NETIF_F(FRAGLIST)
#define skb_rb_prev(skb) rb_to_skb(rb_prev(&(skb)->rbnode))
#define ICACHEF_ALIASING 0
#define ETH_P_DSA 0x001B
#define TIF_SSBD 25
#define DACR32_EL2_D4_WIDTH 2
#define AF_CAN 29
#define HFGITR_EL2_DCCVAP_WIDTH 1
#define STA_FREQHOLD 0x0080
#define O_WRONLY 00000001
#define SMPRIMAP_EL2_P2_SHIFT 8
#define ID_AA64PFR0_EL1_GIC_WIDTH 4
#define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
#define MODULE_ALIAS_NET_PF_PROTO(pf,proto) MODULE_ALIAS("net-pf-" __stringify(pf) "-proto-" __stringify(proto))
#define NT_LOONGARCH_LBT 0xa04
#define ID_MMFR0_EL1_InnerShr_HW UL(0b0001)
#define PTRACE_SYSCALL_INFO_ENTRY 1
#define LORC_EL1_EN_SHIFT 0
#define SEEK_SET 0
#define O_EXCL 00000200
#define DCACHE_MAY_FREE 0x00800000
#define CLOCK_TXFROMRX 4
#define ____cacheline_internodealigned_in_smp __attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))
#define PIRx_ELx_Perm4_SHIFT 16
#define RWH_WRITE_LIFE_LONG 4
#define CTR_EL0_CWG_SHIFT 24
#define COMPAT_HWCAP_VFP (1 << 6)
#define SOL_IP 0
#define __NR_fstat __NR3264_fstat
#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
#define SPEED_14000 14000
#define __LINUX_MII_H__ 
#define __TASK_STOPPED 0x00000004
#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
#define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
#define CONFIG_I2C_SLAVE 1
#define SECTION_ALIGN_UP(pfn) (((pfn) + PAGES_PER_SECTION - 1) & PAGE_SECTION_MASK)
#define current_euid_egid(_euid,_egid) do { const struct cred *__cred; __cred = current_cred(); *(_euid) = __cred->euid; *(_egid) = __cred->egid; } while(0)
#define ID_PFR1_EL1_GIC_GICv4p1 UL(0b0010)
#define ID_AA64ZFR0_EL1_SHA3 GENMASK(35, 32)
#define DT_TEXTREL 22
#define MMU_NOTIFIER_RANGE_BLOCKABLE (1 << 0)
#define CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS 1
#define _LINUX_XARRAY_H 
#define IF_GET_PROTO 0x0002
#define PTRACE_MODE_READ 0x01
#define ftrace_vprintk(fmt,vargs) do { if (__builtin_constant_p(fmt)) { static const char *trace_printk_fmt __used __section("__trace_printk_fmt") = __builtin_constant_p(fmt) ? fmt : NULL; __ftrace_vbprintk(_THIS_IP_, trace_printk_fmt, vargs); } else __ftrace_vprintk(_THIS_IP_, fmt, vargs); } while (0)
#define HDFGWTR_EL2_TRCVICTLR_WIDTH 1
#define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
#define ALARMTIMER_STATE_ENQUEUED 0x01
#define SCTLR_EL1_TIDCP GENMASK(63, 63)
#define PAGEFLAGS_MASK ((1UL << NR_PAGEFLAGS) - 1)
#define ___GFP_IO 0x40u
#define CPACR_ELx_SMEN_SHIFT 24
#define CONFIG_LOCKDEP_CHAINS_BITS 16
#define HWCAP_FLAGM (1 << 27)
#define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000
#define CPU_MASK_NONE (cpumask_t) { { [0 ... BITS_TO_LONGS(NR_CPUS)-1] = 0UL } }
#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
#define IN6ADDR_LOOPBACK_INIT { { { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1 } } }
#define CONFIG_NET_VENDOR_RDC 1
#define ET_HIPROC 0xffff
#define NODEMASK_SCRATCH(x) NODEMASK_ALLOC(struct nodemask_scratch, x, GFP_KERNEL | __GFP_NORETRY)
#define ICH_VMCR_ACK_CTL_SHIFT 2
#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200
#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
#define HFGITR_EL2_SVC_EL0 GENMASK(52, 52)
#define HFGITR_EL2_SVC_EL1 GENMASK(53, 53)
#define MDIO_AN_C73_0_PAUSE BIT(10)
#define VM_UFFD_MISSING 0x00000200
#define SO_BINDTODEVICE 25
#define NO_SYSCALL (-1)
#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
#define SCTLR_EL1_TMT0_WIDTH 1
#define hlist_bl_entry(ptr,type,member) container_of(ptr,type,member)
#define NR_MEM_SECTIONS (1UL << SECTIONS_SHIFT)
#define CNTHCTL_ECV (1 << 12)
#define FTR_UNSIGNED false
#define MIDR_VARIANT_SHIFT 20
#define OPT_ZONE_DMA ZONE_DMA
#define __smp_load_acquire(p) ({ union { __unqual_scalar_typeof(*p) __val; char __c[1]; } __u; typeof(p) __p = (p); compiletime_assert_atomic_type(*p); kasan_check_read(__p, sizeof(*p)); switch (sizeof(*p)) { case 1: asm volatile ("ldarb %w0, %1" : "=r" (*(__u8 *)__u.__c) : "Q" (*__p) : "memory"); break; case 2: asm volatile ("ldarh %w0, %1" : "=r" (*(__u16 *)__u.__c) : "Q" (*__p) : "memory"); break; case 4: asm volatile ("ldar %w0, %1" : "=r" (*(__u32 *)__u.__c) : "Q" (*__p) : "memory"); break; case 8: asm volatile ("ldar %0, %1" : "=r" (*(__u64 *)__u.__c) : "Q" (*__p) : "memory"); break; } (typeof(*p))__u.__val; })
#define wmb() do { kcsan_wmb(); __wmb(); } while (0)
#define ifr_hwaddr ifr_ifru.ifru_hwaddr
#define _LINUX_TIMERQUEUE_H 
#define MAY_ACCESS 0x00000010
#define HDFGWTR_EL2_PMUSERENR_EL0_MASK GENMASK(57, 57)
#define ID_AA64PFR1_EL1_THE_SHIFT 48
#define __NR_clock_adjtime 266
#define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
#define A32_RT2_OFFSET 0
#define EJUKEBOX 528
#define SVE_SIG_REGS_SIZE(vq) (__SVE_FFR_OFFSET(vq) + __SVE_FFR_SIZE(vq))
#define TRACE_CONTEXT_MASK ((1 << (TRACE_LIST_START + TRACE_CONTEXT_BITS)) - 1)
#define IORESOURCE_ROM_SHADOW (1<<1)
#define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description)
#define COMPAT_USER_SZ 296
#define __sve_vq_from_vl(vl) ((vl) / __SVE_VQ_BYTES)
#define AT_REMOVEDIR 0x200
#define TCR_IRGN0_SHIFT 8
#define KUNIT_EXPECT_MEMNEQ_MSG(test,left,right,size,fmt,...) KUNIT_MEM_ASSERTION(test, KUNIT_EXPECTATION, left, !=, right, size, fmt, ##__VA_ARGS__)
#define HFGITR_EL2_TLBIVAALE1IS_SHIFT 33
#define FS_FL_USER_VISIBLE 0x0003DFFF
#define ADVERTISE_1000HALF 0x0100
#define RPMSG_NAME_SIZE 32
#define CONFIG_KALLSYMS 1
#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
#define IFF_LOWER_UP IFF_LOWER_UP
#define ID_AA64MMFR2_EL1_ST_SHIFT 28
#define CONFIG_NET_VENDOR_MICROCHIP 1
#define LEDS_GPIO_DEFSTATE_OFF LEDS_DEFSTATE_OFF
#define CLIDR_EL1_ICB GENMASK(32, 30)
#define __this_cpu_and(pcp,val) ({ __this_cpu_preempt_check("and"); raw_cpu_and(pcp, val); })
#define O_RDWR 00000002
#define TIMER_BASEMASK (TIMER_CPUMASK | TIMER_MIGRATING)
#define flowi6_proto __fl_common.flowic_proto
#define SHRINKER_NONSLAB BIT(4)
#define task_thread_info(task) (&(task)->thread_info)
#define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM
#define MDIO_PMA_LASI_TXCTRL 0x9001
#define LED_FUNCTION_DEBUG "debug"
#define MVFR0_EL1_FPRound_IMP UL(0b0001)
#define IPV6_2292PKTINFO 2
#define ID_AA64MMFR3_EL1_S2POE_IMP UL(0b0001)
#define NVIDIA_CPU_PART_DENVER 0x003
#define CONFIG_NET_VENDOR_NETRONOME 1
#define LPA_10HALF 0x0020
#define SYS_TRBBASER_EL1_CRm 11
#define wake_up_interruptible(x) __wake_up(x, TASK_INTERRUPTIBLE, 1, NULL)
#define SIOCGSTAMP_NEW _IOR(SOCK_IOC_TYPE, 0x06, long long[2])
#define PER_CPU_BASE_SECTION ".data..percpu"
#define TCP_V4_FLOW 0x01
#define HISI_CPU_PART_TSV110 0xD01
#define NL_SET_BAD_ATTR(extack,attr) NL_SET_BAD_ATTR_POLICY(extack, attr, NULL)
#define postcore_param_cb(name,ops,arg,perm) __level_param_cb(name, ops, arg, perm, 2)
#define __NR_read 63
#define CONFIG_ARCH_HAS_GCOV_PROFILE_ALL 1
#define ID_MMFR0_EL1_InnerShr_NC UL(0b0000)
#define SHN_ABS 0xfff1
#define CONFIG_DMA_ENGINE_RAID 1
#define CLONE_FILES 0x00000400
#define MDIO_PCS_10T1L_CTRL_LB 0x4000
#define get_random_sleepable_once(buf,nbytes) DO_ONCE_SLEEPABLE(get_random_bytes, (buf), (nbytes))
#define __LINUX_FILE_H 
#define compat_sp_fiq regs[29]
#define __randomize_layout __designated_init
#define ID_AA64ISAR0_EL1_CRC32 GENMASK(19, 16)
#define TRBTRG_EL1_TRG_WIDTH 32
#define HDFGRTR_EL2_PMOVS_WIDTH 1
#define _LINUX_IN6_H 
#define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
#define skb_queue_reverse_walk_safe(queue,skb,tmp) for (skb = (queue)->prev, tmp = skb->prev; skb != (struct sk_buff *)(queue); skb = tmp, tmp = skb->prev)
#define PHY_INTERRUPT_DISABLED false
#define ARM_CPU_PART_CORTEX_A57 0xD07
#define PMSFCR_EL1_ST_WIDTH 1
#define ICH_VMCR_ENG0_SHIFT 0
#define ALLINT_ALLINT_MASK GENMASK(13, 13)
#define this_cpu_and(pcp,val) __pcpu_size_call(this_cpu_and_, pcp, val)
#define __SWAITQUEUE_INITIALIZER(name) { .task = current, .task_list = LIST_HEAD_INIT((name).task_list), }
#define CONFIG_OF_RESOLVE 1
#define LED_COLOR_ID_BLUE 3
#define __NR_memfd_secret 447
#define START_THREAD(elf_ex,regs,elf_entry,start_stack) start_thread(regs, elf_entry, start_stack)
#define TCR2_EL1x_D128_MASK GENMASK(5, 5)
#define CONFIG_DQL 1
#define for_each_thread(p,t) __for_each_thread((p)->signal, t)
#define mt_lock_is_held(mt) (!(mt)->ma_external_lock || lock_is_held((mt)->ma_external_lock))
#define arch_cmpxchg_relaxed(...) __cmpxchg_wrapper( , __VA_ARGS__)
#define ENOTSYNC 522
#define ID_MMFR4_EL1_LSM GENMASK(23, 20)
#define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
#define PACKET_FANOUT_FLAG_IGNORE_OUTGOING 0x4000
#define CRn_shift 12
#define HDFGWTR_EL2_TRCCNTVRn_SHIFT 37
#define V1_DEL_ALLOC 0
#define __aligned_u64 __u64 __attribute__((aligned(8)))
#define HCR_TID3 (UL(1) << 18)
#define SYS_ID_AA64MMFR1_EL1_Op2 1
#define HCR_BSU (3 << 10)
#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
#define ESR_ELx_EC_UNKNOWN (0x00)
#define SECCOMP_RET_LOG 0x7ffc0000U
#define SYS_PMSIRR_EL1_CRm 9
#define SYS_PMSIRR_EL1_CRn 9
#define SUBSECTION_SHIFT 21
#define HCR_TID4 (UL(1) << 49)
#define ID_PFR1_EL1_Security_MASK GENMASK(7, 4)
#define DECLARE_COMPLETION_ONSTACK_MAP(work,map) struct completion work = COMPLETION_INITIALIZER_ONSTACK_MAP(work, map)
#define RCU_WAIT_TAIL 1
#define _LINUX_PANIC_H 
#define IORESOURCE_SIZEALIGN 0x00040000
#define LED_SET_BRIGHTNESS 7
#define kunit_err(test,fmt,...) kunit_printk(KERN_ERR, test, fmt, ##__VA_ARGS__)
#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
#define HDFGWTR_EL2_PMOVS GENMASK(18, 18)
#define compat_lr_abt regs[20]
#define set_mask_bits(ptr,mask,bits) ({ const typeof(*(ptr)) mask__ = (mask), bits__ = (bits); typeof(*(ptr)) old__, new__; old__ = READ_ONCE(*(ptr)); do { new__ = (old__ & ~mask__) | bits__; } while (!try_cmpxchg(ptr, &old__, new__)); old__; })
#define ID_AA64MMFR1_EL1_HAFDBS_AF UL(0b0001)
#define HDFGWTR_EL2_TRCAUXCTLR GENMASK(35, 35)
#define trace_puts(str) ({ static const char *trace_printk_fmt __used __section("__trace_printk_fmt") = __builtin_constant_p(str) ? str : NULL; if (__builtin_constant_p(str)) __trace_bputs(_THIS_IP_, trace_printk_fmt); else __trace_puts(_THIS_IP_, str, strlen(str)); })
#define HCR_VSE (UL(1) << 8)
#define SCHED_FLAG_RESET_ON_FORK 0x01
#define NL_SET_ERR_MSG_FMT_MOD(extack,fmt,args...) NL_SET_ERR_MSG_FMT((extack), KBUILD_MODNAME ": " fmt, ##args)
#define ID_MMFR1_EL1_BPred_BP_ASID_AWARE UL(0b0010)
#define CONFIG_HAVE_RUST 1
#define EXPORT_SYMBOL(sym) _EXPORT_SYMBOL(sym, "")
#define CAP_SYS_RAWIO 17
#define LED_FUNCTION_ALARM "alarm"
#define EM_SH 42
#define SCTLR_USER_MASK (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | SCTLR_EL1_TCF0_MASK)
#define AT_RANDOM 25
#define SCTLR_EL1_TCF0_ASYMM UL(0b11)
#define ELNRNG 48
#define MDIO_PCS_1000BT1_STAT 2305
#define ID_AA64DFR0_EL1_DebugVer_IMP UL(0b0110)
#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
#define PIRx_ELx_Perm13_MASK GENMASK(55, 52)
#define RNDCLEARPOOL _IO( 'R', 0x06 )
#define ETH_P_MCTP 0x00FA
#define CAP_EMPTY_SET ((kernel_cap_t) { 0 })
#define raw_check_bogus_irq_restore() do { } while (0)
#define MLOCK_LIMIT (8*1024*1024)
#define AF_ROUTE AF_NETLINK
#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
#define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
#define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
#define __NR_write 64
#define SYS_SCXTNUM_EL1_CRm 0
#define SYS_SCXTNUM_EL1_CRn 13
#define TRBIDR_EL1_F_SHIFT 5
#define __ASM_GENERIC_STAT_H 
#define SCTLR_EL1_TCF0_ASYNC UL(0b10)
#define TRBMAR_EL1_SH_SHIFT 8
#define COMPAT_PTRACE_SET_SYSCALL 23
#define ETHTOOL_COALESCE_PKT_RATE_RX_USECS (ETHTOOL_COALESCE_USE_ADAPTIVE_RX | ETHTOOL_COALESCE_RX_USECS_LOW | ETHTOOL_COALESCE_RX_USECS_HIGH | ETHTOOL_COALESCE_PKT_RATE_LOW | ETHTOOL_COALESCE_PKT_RATE_HIGH | ETHTOOL_COALESCE_RATE_SAMPLE_INTERVAL)
#define raw_cmpxchg64_relaxed arch_cmpxchg64_relaxed
#define ID_AA64DFR0_EL1_DoubleLock_NI UL(0b1111)
#define wait_event_interruptible_exclusive_locked_irq(wq,condition) ((condition) ? 0 : __wait_event_interruptible_locked(wq, condition, 1, do_wait_intr_irq))
#define WARN_ON(condition) ({ int __ret_warn_on = !!(condition); if (unlikely(__ret_warn_on)) __WARN(); unlikely(__ret_warn_on); })
#define NOIRQ_SYSTEM_SLEEP_PM_OPS(suspend_fn,resume_fn) .suspend_noirq = pm_sleep_ptr(suspend_fn), .resume_noirq = pm_sleep_ptr(resume_fn), .freeze_noirq = pm_sleep_ptr(suspend_fn), .thaw_noirq = pm_sleep_ptr(resume_fn), .poweroff_noirq = pm_sleep_ptr(suspend_fn), .restore_noirq = pm_sleep_ptr(resume_fn),
#define PACKET_FASTROUTE 6
#define PAGE_IS_PRESENT (1 << 3)
#define CONFIG_NET_VENDOR_DAVICOM 1
#define ETHTOOL_COALESCE_USECS_LOW_HIGH (ETHTOOL_COALESCE_RX_USECS_LOW | ETHTOOL_COALESCE_TX_USECS_LOW | ETHTOOL_COALESCE_RX_USECS_HIGH | ETHTOOL_COALESCE_TX_USECS_HIGH)
#define RESOLVE_CACHED 0x20
#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
#define VM_WRITE 0x00000002
#define xchg_acquire(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_xchg_acquire(__ai_ptr, __VA_ARGS__); })
#define idr_unlock_irqrestore(idr,flags) xa_unlock_irqrestore(&(idr)->idr_rt, flags)
#define __DQUOT_VERSION__ "dquot_6.6.0"
#define ARM64_CPUCAP_PANIC_ON_CONFLICT ((u16)BIT(6))
#define for_each_wakeup_source(ws) for ((ws) = wakeup_sources_walk_start(); (ws); (ws) = wakeup_sources_walk_next((ws)))
#define ID_AA64ISAR1_EL1_API_SHIFT 8
#define __NR_lseek __NR3264_lseek
#define XATTR_CAPS_SZ_1 (sizeof(__le32)*(1 + 2*VFS_CAP_U32_1))
#define CONFIG_SND_CTL_FAST_LOOKUP 1
#define XATTR_CAPS_SZ_3 (sizeof(__le32)*(2 + 2*VFS_CAP_U32_3))
#define MSG_DONTROUTE 4
#define ID_MMFR4_EL1_LSM_IMP UL(0b0001)
#define CONFIG_SND_HDA_PREALLOC_SIZE 64
#define POOL_POISON_FREED 0xa7
#define irq_alloc_desc_from(from,node) irq_alloc_descs(-1, from, 1, node)
#define NETIF_F_RXALL __NETIF_F(RXALL)
#define raw_cpu_try_cmpxchg_1(pcp,ovalp,nval) raw_cpu_generic_try_cmpxchg(pcp, ovalp, nval)
#define raw_cpu_try_cmpxchg_2(pcp,ovalp,nval) raw_cpu_generic_try_cmpxchg(pcp, ovalp, nval)
#define raw_cpu_try_cmpxchg_4(pcp,ovalp,nval) raw_cpu_generic_try_cmpxchg(pcp, ovalp, nval)
#define lockdep_pin_lock(l) lock_pin_lock(&(l)->dep_map)
#define _DEFINE_STATIC_KEY_1(name) DEFINE_STATIC_KEY_TRUE(name)
#define CPTR_EL2_TTA (1 << 20)
#define raw_cpu_try_cmpxchg_8(pcp,ovalp,nval) raw_cpu_generic_try_cmpxchg(pcp, ovalp, nval)
#define NLA_F_NET_BYTEORDER (1 << 14)
#define ARM64_HAS_LDAPR 33
#define list_for_each_entry_safe_reverse(pos,n,head,member) for (pos = list_last_entry(head, typeof(*pos), member), n = list_prev_entry(pos, member); !list_entry_is_head(pos, head, member); pos = n, n = list_prev_entry(n, member))
#define ID_AA64SMFR0_EL1_F16F32_SIGNED false
#define ID_AA64SMFR0_EL1_UNKN (UL(0))
#define KUNIT_CASE_SLOW(test_name) { .run_case = test_name, .name = #test_name, .attr.speed = KUNIT_SPEED_SLOW, .module_name = KBUILD_MODNAME}
#define PMSIRR_EL1_INTERVAL_SHIFT 8
#define GFP_TRANSHUGE_LIGHT ((GFP_HIGHUSER_MOVABLE | __GFP_COMP | __GFP_NOMEMALLOC | __GFP_NOWARN) & ~__GFP_RECLAIM)
#define cpumask_bits(maskp) ((maskp)->bits)
#define might_fault() __might_fault(__FILE__, __LINE__)
#define __overflows_type_constexpr(x,T) ( is_unsigned_type(typeof(x)) ? (x) > type_max(typeof(T)) : is_unsigned_type(typeof(T)) ? (x) < 0 || (x) > type_max(typeof(T)) : (x) < type_min(typeof(T)) || (x) > type_max(typeof(T)))
#define CONFIG_SIGNALFD 1
#define NT_S390_PV_CPU_DATA 0x30e
#define TESTCLEARFLAG_FALSE(uname,lname) static inline bool folio_test_clear_ ##lname(struct folio *folio) { return 0; } static inline int TestClearPage ##uname(struct page *page) { return 0; }
#define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000
#define NR_syscalls (__NR_syscalls)
#define debug_rtlock_wait_set_state() do { } while (0)
#define UDP_V4_FLOW 0x02
#define MDSCR_EL1_TDA_SHIFT 21
#define PMBSR_EL1_EA_SHIFT 18
#define _LINUX_MMZONE_H 
#define ID_AA64PFR1_EL1_MTEX_MTE UL(0b0000)
#define NR_PCP_THP 0
#define SOCK_PASSCRED 3
#define __exitcall(fn) static exitcall_t __exitcall_ ##fn __exit_call = fn
#define SYS_PMSLATFR_EL1_Op0 3
#define TESTSCFLAG(uname,lname,policy) TESTSETFLAG(uname, lname, policy) TESTCLEARFLAG(uname, lname, policy)
#define lock_map_acquire_tryread(l) lock_acquire_shared_recursive(l, 0, 1, NULL, _THIS_IP_)
#define ESR_ELx_Xs_SHIFT (0)
#define TIF_SYSCALL_TRACEPOINT 10
#define rwsem_acquire_read(l,s,t,i) lock_acquire_shared(l, s, t, NULL, i)
#define VM_ACCESS_FLAGS (VM_READ | VM_WRITE | VM_EXEC)
#define sg_dma_address(sg) ((sg)->dma_address)
#define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
#define raw_write_seqcount_end(s) do { do_raw_write_seqcount_end(seqprop_ptr(s)); if (seqprop_preemptible(s)) preempt_enable(); } while (0)
#define ID_PFR0_EL1_AMU_AMUv1 UL(0b0001)
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
#define RANDOM_KMALLOC_CACHES_NR 0
#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
#define arch_scale_freq_invariant topology_scale_freq_invariant
#define HDFGWTR_EL2_TRBBASER_EL1_MASK GENMASK(50, 50)
#define work_data_bits(work) ((unsigned long *)(&(work)->data))
#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
#define HDFGRTR_EL2_PMBIDR_EL1_SHIFT 63
#define read_unlock_bh(lock) _raw_read_unlock_bh(lock)
#define R_AARCH64_MOVW_PREL_G0_NC 288
#define ECOMM 70
#define HDFGWTR_EL2_PMINTEN_WIDTH 1
#define CONFIG_NET_VENDOR_EZCHIP 1
#define __RW_LOCK_UNLOCKED(lockname) (rwlock_t) { .raw_lock = __ARCH_RW_LOCK_UNLOCKED, .magic = RWLOCK_MAGIC, .owner = SPINLOCK_OWNER_INIT, .owner_cpu = -1, RW_DEP_MAP_INIT(lockname) }
#define lockdep_off() do { current->lockdep_recursion += LOCKDEP_OFF; } while (0)
#define ID_AA64PFR1_EL1_SME_SIGNED false
#define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
#define CONFIG_MSDOS_PARTITION 1
#define USB_DEVICE_ID_MATCH_INT_SUBCLASS 0x0100
#define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
#define __NR_pidfd_getfd 438
#define WORKINGSET_FILE 1
#define ID_AA64MMFR2_EL1_LSM_NI UL(0b0000)
#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
#define BLKTRACESTOP _IO(0x12,117)
#define SB_ENC_STRICT_MODE_FL (1 << 0)
#define __kcsan_cleanup_scoped __maybe_unused
#define _LINUX_FTRACE_H 
#define _ASM_GENERIC_BITOPS_INSTRUMENTED_ATOMIC_H 
#define ID_AA64PFR1_EL1_PFAR_IMP UL(0b0001)
#define early_param(str,fn) __setup_param(str, fn, fn, 1)
#define MVFR2_EL1_SIMDMisc_SIMD_ROUNDING UL(0b0010)
#define ARM64_HAS_GIC_PRIO_RELAXED_SYNC 31
#define rcuwait_wait_event_timeout(w,condition,state,timeout) ({ long __ret = timeout; if (!___wait_cond_timeout(condition)) __ret = __rcuwait_wait_event_timeout(w, condition, state, timeout); __ret; })
#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
#define __INIT_WORK(_work,_func,_onstack) do { static __maybe_unused struct lock_class_key __key; __INIT_WORK_KEY(_work, _func, _onstack, &__key); } while (0)
#define __COMPAT_ADDR_BND_PKEY_PAD (__alignof__(compat_uptr_t) < sizeof(short) ? sizeof(short) : __alignof__(compat_uptr_t))
#define TRBLIMITR_EL1_E GENMASK(0, 0)
#define EXPANSION_NWAY 0x0001
#define ID_AA64ISAR0_EL1_RNDR GENMASK(63, 60)
#define SYS_CTR_EL0_Op1 3
#define SYS_CTR_EL0_Op2 1
#define PSR_AA32_ENDSTATE 0
#define late_initcall(fn) __define_initcall(fn, 7)
#define ZT_SIG_REGS_OFFSET sizeof(struct zt_context)
#define HUGETLB_FLAG_ENCODE_MASK 0x3f
#define CAP_SYS_TIME 25
#define SHM_HUGE_64KB HUGETLB_FLAG_ENCODE_64KB
#define IOPRIO_PRIO_DATA(ioprio) ((ioprio) & IOPRIO_PRIO_MASK)
#define ID_ISAR5_EL1_AES_WIDTH 4
#define __NR_mlock2 284
#define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16)
#define ETH_P_DNA_RC 0x6002
#define ID_ISAR5_EL1_SHA1_NI UL(0b0000)
#define _ASM_GENERIC_RESOURCE_H 
#define SYS_PMSEVFR_EL1_CRm 9
#define SYS_PMSEVFR_EL1_CRn 9
#define IF_IFACE_X21 0x1002
#define raw_try_cmpxchg128_relaxed(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg128_relaxed((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define MODULES_VADDR (_PAGE_END(VA_BITS_MIN))
#define CONTEXTIDR_ELx_PROCID_WIDTH 32
#define ID_PFR1_EL1_GenTimer_ECV UL(0b0010)
#define list_for_each_entry_safe_from(pos,n,head,member) for (n = list_next_entry(pos, member); !list_entry_is_head(pos, head, member); pos = n, n = list_next_entry(n, member))
#define V1_INIT_ALLOC 1
#define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000
#define __const_hweight8(w) ((unsigned int) ((!!((w) & (1ULL << 0))) + (!!((w) & (1ULL << 1))) + (!!((w) & (1ULL << 2))) + (!!((w) & (1ULL << 3))) + (!!((w) & (1ULL << 4))) + (!!((w) & (1ULL << 5))) + (!!((w) & (1ULL << 6))) + (!!((w) & (1ULL << 7)))))
#define raw_cpu_read(pcp) __pcpu_size_call_return(raw_cpu_read_, pcp)
#define IPV6_ORIGDSTADDR 74
#define CONFIG_GENERIC_CSUM 1
#define compat_r8_fiq regs[24]
#define ID_AA64MMFR3_EL1_SNERR_MASK GENMASK(43, 40)
#define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
#define WARN_ON_RATELIMIT(condition,state) ({ bool __rtn_cond = !!(condition); WARN_ON(__rtn_cond && __ratelimit(state)); __rtn_cond; })
#define HCRX_EL2_TCR2En_SHIFT 14
#define ID_AA64ISAR1_EL1_JSCVT_SIGNED false
#define PMBSR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32) | GENMASK_ULL(25, 20))
#define __BP_HARDEN_HYP_VECS_SZ ((BP_HARDEN_EL2_SLOTS - 1) * SZ_2K)
#define PMBSR_EL1_EC_IMP_DEF UL(0b011111)
#define MDSCR_EL1_RXO_SHIFT 27
#define SCTLR_EL1_ITFSB_SHIFT 37
#define ID_AA64PFR1_EL1_BT_SHIFT 0
#define __NR_ioprio_set 30
#define ID_ISAR3_EL1_SynchPrim GENMASK(15, 12)
#define ID_AA64MMFR3_EL1_D128_2_MASK GENMASK(39, 36)
#define __NR3264_fstat 80
#define CONFIG_INPUT_KEYBOARD 1
#define swait_event_interruptible_exclusive(wq,condition) ({ int __ret = 0; if (!(condition)) __ret = __swait_event_interruptible(wq, condition); __ret; })
#define __UAPI_DEF_IN6_PKTINFO 1
#define CAP_KILL 5
#define HFGxTR_EL2_LORSA_EL1 GENMASK(23, 23)
#define ZA_SIG_ZAV_OFFSET(vq,n) (ZA_SIG_REGS_OFFSET + (SVE_SIG_ZREG_SIZE(vq) * n))
#define ID_MMFR4_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_MMFR4_EL1_RES1 (UL(0))
#define KERNEL_HWCAP_SME_F16F32 __khwcap2_feature(SME_F16F32)
#define NLM_F_DUMP (NLM_F_ROOT|NLM_F_MATCH)
#define ISR_EL1_FS_WIDTH 1
#define CTR_EL0_IDC_MASK GENMASK(28, 28)
#define PM_SCAN_CHECK_WPASYNC (1 << 1)
#define ID_AA64ZFR0_EL1_F32MM_MASK GENMASK(55, 52)
#define IRQF_FORCE_RESUME 0x00008000
#define SCTLR_EL1_EnRCTX GENMASK(10, 10)
#define ID_AA64ISAR0_EL1_AES_NI UL(0b0000)
#define EISA_SIG_LEN 8
#define ID_MMFR3_EL1_CMaintSW_IMP UL(0b0001)
#define SKBFL_ZEROCOPY_FRAG (SKBFL_ZEROCOPY_ENABLE | SKBFL_SHARED_FRAG)
#define set_thread_flag(flag) set_ti_thread_flag(current_thread_info(), flag)
#define has_erratum_handler(h) false
#define DPM_FLAG_SMART_SUSPEND BIT(2)
#define HFGITR_EL2_nBRBIALL_SHIFT 56
#define QFMT_VFS_V0 2
#define ID_AA64ISAR2_EL1_CLRBHB GENMASK(31, 28)
#define __ARCH_UAPI_SA_FLAGS SA_RESTORER
#define TCR_TG1_SHIFT 30
#define net_ratelimited_function(function,...) do { if (net_ratelimit()) function(__VA_ARGS__); } while (0)
#define inb _inb
#define MAJOR(dev) ((unsigned int) ((dev) >> MINORBITS))
#define ETH_MODULE_EEPROM_PAGE_LEN 128
#define SOCK_TXREHASH_DISABLED 0
#define page_to_virt(x) ({ __typeof__(x) __page = x; u64 __idx = ((u64)__page - VMEMMAP_START) / sizeof(struct page); u64 __addr = PAGE_OFFSET + (__idx * PAGE_SIZE); (void *)__tag_set((const void *)__addr, page_kasan_tag(__page));})
#define DL_FLAG_PM_RUNTIME BIT(2)
#define ID_ISAR3_EL1_SVC_WIDTH 4
#define CONFIG_GPIO_SYSFS 1
#define KERN_ERR KERN_SOH "3"
#define PR_SPEC_DISABLE (1UL << 2)
#define ETHTOOL_COALESCE_TX_USECS_HIGH BIT(19)
#define SB_SYNCHRONOUS BIT(4)
#define P4D_SIZE (1UL << P4D_SHIFT)
#define PPM_SCALE_INV ((1LL << (PPM_SCALE_INV_SHIFT + NTP_SCALE_SHIFT)) / PPM_SCALE + 1)
#define RAW_INIT_NOTIFIER_HEAD(name) do { (name)->head = NULL; } while (0)
#define swait_event_idle_timeout_exclusive(wq,condition,timeout) ({ long __ret = timeout; if (!___wait_cond_timeout(condition)) __ret = __swait_event_idle_timeout(wq, condition, timeout); __ret; })
#define ID_DFR0_EL1_PerfMon_SIGNED false
#define ID_ISAR6_EL1_SPECRES GENMASK(19, 16)
#define PAGE_MAPPING_FLAGS (PAGE_MAPPING_ANON | PAGE_MAPPING_MOVABLE)
#define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
#define KBD_KEYSYM 0x0004
#define struct_size(p,member,count) __builtin_choose_expr(__is_constexpr(count), sizeof(*(p)) + flex_array_size(p, member, count), size_add(sizeof(*(p)), flex_array_size(p, member, count)))
#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
#define __irq_enter_raw() do { preempt_count_add(HARDIRQ_OFFSET); lockdep_hardirq_enter(); } while (0)
#define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
#define ID_AA64ISAR1_EL1_JSCVT_NI UL(0b0000)
#define LOCK_STATE_NOT_HELD 0
#define PACKET_FANOUT_FLAG_ROLLOVER 0x1000
#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | ESR_ELx_SYS64_ISS_DIR_READ)
#define ID_AA64ISAR1_EL1_SB_SHIFT 36
#define SRCU_STATE_SCAN1 1
#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES), __section__(".data..cacheline_aligned")))
#define HDFGWTR_EL2_PMSCR_EL1_SHIFT 26
#define TPACKET3_HDRLEN (TPACKET_ALIGN(sizeof(struct tpacket3_hdr)) + sizeof(struct sockaddr_ll))
#define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
#define TIMER_MIGRATING 0x00040000
#define REG_ZCR_EL12 S3_5_C1_C2_0
#define si_trapno _sifields._sigfault._trapno
#define TRBLIMITR_EL1_FM_WIDTH 2
#define ID_AA64PFR1_EL1_NMI_MASK GENMASK(39, 36)
#define LED_FUNCTION_BLUETOOTH "bluetooth"
#define __define_initcall_stub(__stub,fn) __ADDRESSABLE(fn)
#define _UAPI_LINUX_RANDOM_H 
#define __SEQLOCK_UNLOCKED(lockname) { .seqcount = SEQCNT_SPINLOCK_ZERO(lockname, &(lockname).lock), .lock = __SPIN_LOCK_UNLOCKED(lockname) }
#define SRCU_STATE_SCAN2 2
#define ID_AA64PFR0_EL1_EL3_SHIFT 12
#define CONFIG_CRC16 1
#define WAKE_MAGIC (1 << 5)
#define smp_cond_load_relaxed(ptr,cond_expr) ({ typeof(ptr) __PTR = (ptr); __unqual_scalar_typeof(*ptr) VAL; for (;;) { VAL = READ_ONCE(*__PTR); if (cond_expr) break; __cmpwait_relaxed(__PTR, VAL); } (typeof(*ptr))VAL; })
#define hlist_for_each_entry_rcu(pos,head,member,cond...) for (__list_check_rcu(dummy, ## cond, 0), pos = hlist_entry_safe(rcu_dereference_raw(hlist_first_rcu(head)), typeof(*(pos)), member); pos; pos = hlist_entry_safe(rcu_dereference_raw(hlist_next_rcu( &(pos)->member)), typeof(*(pos)), member))
#define _DPRINTK_FLAGS_DEFAULT 0
#define dma_unmap_sg(d,s,n,r) dma_unmap_sg_attrs(d, s, n, r, 0)
#define SSB_ANY_ID 0xFFFF
#define F_GET_RW_HINT (F_LINUX_SPECIFIC_BASE + 11)
#define __wait_event_lock_irq_timeout(wq_head,condition,lock,timeout,state) ___wait_event(wq_head, ___wait_cond_timeout(condition), state, 0, timeout, spin_unlock_irq(&lock); __ret = schedule_timeout(__ret); spin_lock_irq(&lock));
#define ID_PFR0_EL1_DIT_SHIFT 24
#define TRBSR_EL1_S GENMASK(17, 17)
#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
#define EPOLLET ((__force __poll_t)(1U << 31))
#define FS_PROJINHERIT_FL 0x20000000
#define CONFIG_CC_VERSION_TEXT "gcc (Debian 12.2.0-14) 12.2.0"
#define __meminit __section(".meminit.text") __cold notrace __latent_entropy
#define ID_AA64ISAR0_EL1_AES GENMASK(7, 4)
#define DCZID_EL0_BS GENMASK(3, 0)
#define KUNIT_ASSERT_LT_MSG(test,left,right,fmt,...) KUNIT_BINARY_INT_ASSERTION(test, KUNIT_ASSERTION, left, <, right, fmt, ##__VA_ARGS__)
#define __no_sanitize_or_inline __always_inline
#define ID_AA64MMFR1_EL1_HAFDBS_NI UL(0b0000)
#define ID_AA64MMFR1_EL1_TIDCP1_WIDTH 4
#define _IOC_NRSHIFT 0
#define CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 1
#define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
#define ID_AA64ISAR1_EL1_LRCPC_IMP UL(0b0001)
#define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
#define HDFGWTR_EL2_DBGWCRn_EL1_MASK GENMASK(2, 2)
#define BMCR_RESET 0x8000
#define S_IWUGO (S_IWUSR|S_IWGRP|S_IWOTH)
#define HWCAP2_SME_I8I32 (1 << 26)
#define ___GFP_DMA32 0x04u
#define __ASM_SHMPARAM_H 
#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
#define ID_AA64ISAR0_EL1_RNDR_SHIFT 60
#define __convert_gid(size,gid) (gid)
#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
#define TIME_UPTIME_SEC_MAX (30LL * 365 * 24 *3600)
#define EXPORT_NS_SIMPLE_DEV_PM_OPS(name,suspend_fn,resume_fn,ns) EXPORT_NS_DEV_SLEEP_PM_OPS(name, ns) = { SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) }
#define CPUCLOCK_WHICH(clock) ((clock) & (clockid_t) CPUCLOCK_CLOCK_MASK)
#define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0)
#define DEFINE_SEMAPHORE(_name,_n) struct semaphore _name = __SEMAPHORE_INITIALIZER(_name, _n)
#define HFGITR_EL2_nBRBINJ_WIDTH 1
#define __NR_setresgid 149
#define __LINUX_RCUPDATE_H 
#define ID_AA64ISAR2_EL1_BC_WIDTH 4
#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
#define ___wait_event(wq_head,condition,state,exclusive,ret,cmd) ({ __label__ __out; struct wait_queue_entry __wq_entry; long __ret = ret; init_wait_entry(&__wq_entry, exclusive ? WQ_FLAG_EXCLUSIVE : 0); for (;;) { long __int = prepare_to_wait_event(&wq_head, &__wq_entry, state); if (condition) break; if (___wait_is_interruptible(state) && __int) { __ret = __int; goto __out; } cmd; } finish_wait(&wq_head, &__wq_entry); __out: __ret; })
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE 
#define REG_PIR_EL1 S3_0_C10_C2_3
#define REG_PIR_EL2 S3_4_C10_C2_3
#define cmpxchg_acquire(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg_acquire(__ai_ptr, __VA_ARGS__); })
#define EM_CYGNUS_MN10300 0xbeef
#define HFGxTR_EL2_LORID_EL1 GENMASK(21, 21)
#define ID_AA64DFR0_EL1_HPMN0_UNPREDICTABLE UL(0b0000)
#define SHT_NOBITS 8
#define CONFIG_QUEUED_RWLOCKS 1
#define VTCR_EL2_TG0_MASK TCR_TG0_MASK
#define ETH_P_QINQ2 0x9200
#define IPV6_ROUTER_ALERT_ISOLATE 30
#define TCR2_EL2_HAFT_SHIFT 11
#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1) << _Q_ ## type ## _OFFSET)
#define __NR_mremap 216
#define SRCU_NMI_SAFE 0x2
#define SUPPORTED_100baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Half)
#define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
#define IOP_FASTPERM 0x0001
#define __NR_futex_requeue 456
#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008
#define CONFIG_HAVE_C_RECORDMCOUNT 1
#define devm_irq_alloc_descs(dev,irq,from,cnt,node) __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
#define SYS_MDCCINT_EL1_CRn 0
#define ESR_ELx_EC_PC_ALIGN (0x22)
#define PSR_PAN_BIT 0x00400000
#define Q_QUOTAOFF 0x800003
#define _struct_page_alignment __aligned(2 * sizeof(unsigned long))
#define ETHTOOL_COALESCE_TX_AGGR (ETHTOOL_COALESCE_TX_AGGR_MAX_BYTES | ETHTOOL_COALESCE_TX_AGGR_MAX_FRAMES | ETHTOOL_COALESCE_TX_AGGR_TIME_USECS)
#define ftrace_direct_func_count 0
#define si_sys_private _sifields._timer._sys_private
#define PAGE_SHARED_EXEC __pgprot(_PAGE_SHARED_EXEC)
#define UNIVERSAL_DEV_PM_OPS(name,suspend_fn,resume_fn,idle_fn) const struct dev_pm_ops __maybe_unused name = { SET_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) SET_RUNTIME_PM_OPS(suspend_fn, resume_fn, idle_fn) }
#define V1_DEL_REWRITE 2
#define MDIO_AN_C73_1_1000BASE_KX BIT(5)
#define AT_GID 13
#define ETHTOOL_FEC_BASER (1 << ETHTOOL_FEC_BASER_BIT)
#define TASK_SIZE TASK_SIZE_64
#define ID_AA64ISAR2_EL1_CSSC_SHIFT 52
#define MDIO_AN_T1_LP_L 517
#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
#define ARM_BREAKPOINT_EXECUTE 0
#define SHRINKER_UNIT_BITS BITS_PER_LONG
#define F_GET_FILE_RW_HINT (F_LINUX_SPECIFIC_BASE + 13)
#define PR_SCHED_CORE_CREATE 1
#define IPV6_PRIORITY_12 0x0c00
#define IPV6_PRIORITY_13 0x0d00
#define ioread16_rep ioread16_rep
#define lock_map_acquire_read(l) lock_acquire_shared_recursive(l, 0, 0, NULL, _THIS_IP_)
#define ID_AA64ISAR1_EL1_APA_SIGNED false
#define HZ_TO_NSEC_NUM 4000000
#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
#define ID_AA64MMFR3_EL1_SCTLRX_SIGNED false
#define EREMOTE 66
#define ID_ISAR1_EL1_Except_AR GENMASK(11, 8)
#define PF_ISDN AF_ISDN
#define PMSIDR_EL1_FORMAT_WIDTH 4
#define try_cmpxchg_relaxed(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg_relaxed(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define LED_INIT_DEFAULT_TRIGGER BIT(23)
#define irq_alloc_desc_at(at,node) irq_alloc_descs(at, at, 1, node)
#define TCR_EPD1_SHIFT 23
#define ID_MMFR4_EL1_CnP_WIDTH 4
#define PACKET_MR_PROMISC 1
#define SYS_PIR_EL12 sys_reg(3, 5, 10, 2, 3)
#define __FMODE_EXEC ((__force int) FMODE_EXEC)
#define ID_MMFR4_EL1_SpecSEI_NI UL(0b0000)
#define MDIO_MMD_VEND2 31
#define ID_AA64ISAR1_EL1_XS_MASK GENMASK(59, 56)
#define ID_AA64SMFR0_EL1_B16B16_SIGNED false
#define ID_AA64ISAR1_EL1_XS_SHIFT 56
#define PG_offline 0x00000100
#define ID_AA64ISAR0_EL1_RNDR_MASK GENMASK(63, 60)
#define device_initcall_sync(fn) __define_initcall(fn, 6s)
#define SUPPORTED_BNC __ETHTOOL_LINK_MODE_LEGACY_MASK(BNC)
#define plist_for_each_entry(pos,head,mem) list_for_each_entry(pos, &(head)->node_list, mem.node_list)
#define ELF64_GNU_PROPERTY_ALIGN 8
#define dynamic_pr_debug(fmt,...) do { if (0) printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__); } while (0)
#define PACKET_LOSS 14
#define device_pm_lock() do {} while (0)
#define _STK_LIM (8*1024*1024)
#define PR_SET_FPEMU 10
#define HDFGRTR_EL2_TRCCNTVRn GENMASK(37, 37)
#define __wait_event_cmd(wq_head,condition,cmd1,cmd2) (void)___wait_event(wq_head, condition, TASK_UNINTERRUPTIBLE, 0, 0, cmd1; schedule(); cmd2)
#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
#define HCRX_EL2_TMEA_MASK GENMASK(19, 19)
#define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0))
#define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
#define HDFGRTR_EL2_TRBLIMITR_EL1_WIDTH 1
#define BLKRRPART _IO(0x12,95)
#define HDFGRTR_EL2_DBGBVRn_EL1 GENMASK(1, 1)
#define HDFGRTR_EL2_PMINTEN GENMASK(17, 17)
#define ETH_P_RARP 0x8035
#define PACKET_FANOUT_RND 4
#define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
#define NT_X86_XSTATE 0x202
#define _UAPI_LINUX_NET_H 
#define __NR_io_getevents 4
#define HCR_TTLBOS (UL(1) << 55)
#define wake_up_locked_poll(x,m) __wake_up_locked_key((x), TASK_NORMAL, poll_to_key(m))
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 
#define IRQF_TRIGGER_FALLING 0x00000002
#define ADVERTISED_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Pause)
#define mutex_lock_killable(lock) mutex_lock_killable_nested(lock, 0)
#define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
#define _ASM_GENERIC_BITOPS_ARCH_HWEIGHT_H_ 
#define SMPRIMAP_EL2_P14_MASK GENMASK(59, 56)
#define CONFIG_ARCH_SUPPORTS_UPROBES 1
#define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
#define pr_crit_once(fmt,...) printk_once(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__)
#define SYS_ID_ISAR0_EL1_CRm 2
#define SYS_ID_ISAR0_EL1_CRn 0
#define TCR_HA (UL(1) << 39)
#define TCR_HD (UL(1) << 40)
#define MTE_TAG_SHIFT 56
#define HDFGWTR_EL2_PMBLIMITR_EL1 GENMASK(23, 23)
#define SYS_OSLAR_EL1_Op0 2
#define SYS_OSLAR_EL1_Op1 0
#define SYS_OSLAR_EL1_Op2 4
#define ID_AA64MMFR3_EL1_AIE GENMASK(27, 24)
#define EPOLLRDBAND (__force __poll_t)0x00000080
#define S_SYNC (1 << 0)
#define ifr_metric ifr_ifru.ifru_ivalue
#define X86_STEPPING_ANY 0
#define HCRX_EL2_TALLINT_WIDTH 1
#define __ASM_PROCESSOR_H 
#define ID_AA64MMFR2_EL1_LSM GENMASK(11, 8)
#define ID_ISAR3_EL1_UNKN (UL(0))
#define PF_MEMALLOC 0x00000800
#define SYS_PIR_EL12_CRm 2
#define SYS_PIR_EL12_CRn 10
#define ID_AA64MMFR0_EL1_ECV_NI UL(0b0000)
#define SHF_ALLOC 0x2
#define STATX_ATTR_ENCRYPTED 0x00000800
#define __NR3264_fcntl 25
#define MDIO_PCS_STAT2_10GBR 0x0001
#define __SETPAGEFLAG(uname,lname,policy) static __always_inline void __folio_set_ ##lname(struct folio *folio) { __set_bit(PG_ ##lname, folio_flags(folio, FOLIO_ ##policy)); } static __always_inline void __SetPage ##uname(struct page *page) { __set_bit(PG_ ##lname, &policy(page, 1)->flags); }
#define ID_PFR1_EL1_MProgMod_MASK GENMASK(11, 8)
#define MVFR1_EL1_SIMDInt_MASK GENMASK(15, 12)
#define AF_RDS 21
#define numa_map_to_online_node(node) numa_nearest_node(node, N_ONLINE)
#define KERNEL_HWCAP_JSCVT __khwcap_feature(JSCVT)
#define mt_set_external_lock(mt,lock) (mt)->ma_external_lock = &(lock)->dep_map
#define in_compat_syscall in_compat_syscall
#define _copy_from_iter_flushcache _copy_from_iter_nocache
#define __UAPI_DEF_IPX_CONFIG_DATA 1
#define SYS_ID_PFR2_EL1_Op1 0
#define cap_lower(c,flag) ((c).val &= ~BIT_ULL(flag))
#define IF_IFACE_X21D 0x1006
#define netif_dbg(priv,type,dev,format,args...) ({ if (0) netif_printk(priv, type, KERN_DEBUG, dev, format, ##args); 0; })
#define __aligned_largest __attribute__((__aligned__))
#define wait_event_exclusive_cmd(wq_head,condition,cmd1,cmd2) do { if (condition) break; __wait_event_exclusive_cmd(wq_head, condition, cmd1, cmd2); } while (0)
#define delay_group_leader(p) (thread_group_leader(p) && !thread_group_empty(p))
#define struct_size_t(type,member,count) struct_size((type *)NULL, member, count)
#define VTCR_EL2_TG0_4K TCR_TG0_4K
#define ID_AA64ISAR1_EL1_SPECRES_IMP UL(0b0001)
#define em_span_cpus(em) (to_cpumask((em)->cpus))
#define ID_DFR0_EL1_MMapTrc_MASK GENMASK(19, 16)
#define RCU_INIT_POINTER(p,v) do { rcu_check_sparse(p, __rcu); WRITE_ONCE(p, RCU_INITIALIZER(v)); } while (0)
#define current_uid_gid(_uid,_gid) do { const struct cred *__cred; __cred = current_cred(); *(_uid) = __cred->uid; *(_gid) = __cred->gid; } while(0)
#define set_pud_safe(pudp,pud) ({ WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); set_pud(pudp, pud); })
#define ID_PFR1_EL1_Sec_frac GENMASK(23, 20)
#define DMA32_ZONE(xx) xx ##_DMA32,
#define task_user_tls(t) (&(t)->thread.uw.tp_value)
#define raw_try_cmpxchg128(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg128((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define RADIX_TREE_INTERNAL_NODE 2UL
#define raw_spin_is_locked(lock) arch_spin_is_locked(&(lock)->raw_lock)
#define mtree_unlock(mt) spin_unlock((&(mt)->ma_lock))
#define VM_MAP_PUT_PAGES 0x00000200
#define SHN_UNDEF 0
#define IS_CASEFOLDED(inode) ((inode)->i_flags & S_CASEFOLD)
#define key_remove_domain(d) do { } while(0)
#define ADVERTISE_RFAULT 0x2000
#define pgprot_mhp pgprot_tagged
#define __NR_mprotect 226
#define ID_AA64ZFR0_EL1_AES_SHIFT 4
#define SIG_BLOCK 0
#define local_add_return(i,l) atomic_long_add_return((i), (&(l)->a))
#define ID_AA64DFR0_EL1_TraceVer_SHIFT 4
#define BLOCK_SIZE_BITS 10
#define PACKET_HDRLEN 11
#define ID_AA64SMFR0_EL1_I16I32_WIDTH 4
#define MDIO_AN_C73_0_NP BIT(15)
#define ID_AA64ISAR0_EL1_SM4_SIGNED false
#define __NR_getpriority 141
#define ETH_P_AF_IUCV 0xFBFB
#define PAGE_IS_PFNZERO (1 << 5)
#define clear_used_math() clear_stopped_child_used_math(current)
#define HDFGWTR_EL2_DBGPRCR_EL1_SHIFT 7
#define node_possible(node) node_state((node), N_POSSIBLE)
#define NETLINK_DNRTMSG 14
#define PT_TLS 7
#define PTRACE_EVENT_VFORK_DONE 5
#define KUNIT_SUBTEST_INDENT "    "
#define radix_tree_root xarray
#define KERNEL_HWCAP_CRC32 __khwcap_feature(CRC32)
#define ID_ISAR0_EL1_CmpBranch_WIDTH 4
#define I3C_MATCH_MANUF 0x2
#define __sb_writers_release(sb,lev) percpu_rwsem_release(&(sb)->s_writers.rw_sem[(lev)-1], 1, _THIS_IP_)
#define ESR_ELx_EC_CP14_MR (0x05)
#define CONFIG_HAVE_MOVE_PMD 1
#define IPV6_RECVDSTOPTS 58
#define MSG_WAITFORONE 0x10000
#define local_add_negative(i,l) atomic_long_add_negative((i), (&(l)->a))
#define SYSCTL_THREE_THOUSAND ((void *)&sysctl_vals[8])
#define SHF_RO_AFTER_INIT 0x00200000
#define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX
#define __NR_init_module 105
#define PSR_BTYPE_MASK 0x00000c00
#define VM_RAND_READ 0x00010000
#define VFS_CAP_FLAGS_MASK ~VFS_CAP_REVISION_MASK
#define __TLBI_RANGE_NUM(pages,scale) ((((pages) >> (5 * (scale) + 1)) & TLBI_RANGE_MASK) - 1)
#define __NR_getpid 172
#define time_before64(a,b) time_after64(b,a)
#define EXPORT_GPL_DEV_SLEEP_PM_OPS(name) _EXPORT_DEV_SLEEP_PM_OPS(name, "GPL", "")
#define PAGE_ALIGN(addr) ALIGN(addr, PAGE_SIZE)
#define CONFIG_SBITMAP 1
#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
#define ARM64_HAS_CRC32 14
#define PMSICR_EL1_ECOUNT_SHIFT 56
#define HFGITR_EL2_RES0 (UL(0) | GENMASK_ULL(63, 61))
#define HFGITR_EL2_RES1 (UL(0))
#define ID_AA64PFR0_EL1_CSV2_IMP UL(0b0001)
#define SPI_MODULE_PREFIX "spi:"
#define dev_printk_index_emit(level,fmt,...) printk_index_subsys_emit("%s %s: ", level, fmt)
#define sys_reg(op0,op1,crn,crm,op2) (((op0) << Op0_shift) | ((op1) << Op1_shift) | ((crn) << CRn_shift) | ((crm) << CRm_shift) | ((op2) << Op2_shift))
#define F_SETLEASE (F_LINUX_SPECIFIC_BASE + 0)
#define SHM_HUGE_16MB HUGETLB_FLAG_ENCODE_16MB
#define NT_LOONGARCH_HW_BREAK 0xa05
#define MAX_LOCKDEP_KEYS (1UL << MAX_LOCKDEP_KEYS_BITS)
#define O_PATH 010000000
#define AT_PHENT 4
#define PMBLIMITR_EL1_FM_WIDTH 2
#define ID_AA64SMFR0_EL1_F16F32_NI UL(0b0)
#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
#define TAINT_WARN 9
#define TCR2_EL2_PTTWI GENMASK(10, 10)
#define PR_MCE_KILL_CLEAR 0
#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
#define flush_icache_range flush_icache_range
#define HCRX_EL2_D128En_WIDTH 1
#define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
#define S_IWUSR 00200
#define MDSCR_EL1_HDE_WIDTH 1
#define HDFGWTR_EL2_TRCOSLAR_SHIFT 42
#define ID_AA64SMFR0_EL1_I16I64_SIGNED false
#define MDSCR_EL1_TDA_MASK GENMASK(21, 21)
#define TCR_EL2_TG0_MASK TCR_TG0_MASK
#define MII_ADVERTISE 0x04
#define PMSG_USER_SUSPEND ((struct pm_message) { .event = PM_EVENT_USER_SUSPEND, })
#define HFGxTR_EL2_CCSIDR_EL1_SHIFT 9
#define ID_ISAR2_EL1_LoadStore GENMASK(3, 0)
#define ARM64_WORKAROUND_1542419 72
#define MODULES_VSIZE (SZ_2G)
#define __INIT_WORK_KEY(_work,_func,_onstack,_key) do { __init_work((_work), _onstack); (_work)->data = (atomic_long_t) WORK_DATA_INIT(); lockdep_init_map(&(_work)->lockdep_map, "(work_completion)"#_work, (_key), 0); INIT_LIST_HEAD(&(_work)->entry); (_work)->func = (_func); } while (0)
#define KUNIT_INIT_ASSERT(initializers...) { initializers }
#define HCRX_EL2_UNKN (UL(0))
#define CLIDR_EL1_LoC_MASK GENMASK(26, 24)
#define ADJ_TAI 0x0080
#define ID_AA64MMFR0_EL1_TGRAN16_2_TGRAN16 UL(0b0000)
#define EARLY_PMDS(vstart,vend,add) (0)
#define LORC_EL1_RES0 (UL(0) | GENMASK_ULL(63, 10) | GENMASK_ULL(1, 1))
#define ID_AA64PFR0_EL1_RME_WIDTH 4
#define _LINUX_RATELIMIT_H 
#define RCU_NODE_NAME_INIT { "rcu_node_0", "rcu_node_1" }
#define ID_MMFR0_EL1_OuterShr_WIDTH 4
#define __IRQF_TIMER 0x00000200
#define __kcsan_check_read_write(ptr,size) __kcsan_check_access(ptr, size, KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_WRITE)
#define ID_MMFR3_EL1_CMaintSW_NI UL(0b0000)
#define MDCR_EL2_TPM (UL(1) << 6)
#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_MASK GENMASK(6, 6)
#define _UAPI_LINUX_PERSONALITY_H 
#define __NR3264_lseek 62
#define register_sysctl_init(path,table) __register_sysctl_init(path, table, #table, ARRAY_SIZE(table))
#define LED_FUNCTION_TX "tx"
#define LORID_EL1_LD_MASK GENMASK(23, 16)
#define SMCR_ELx_LEN_MASK GENMASK(3, 0)
#define F_UNLCK 2
#define HFGxTR_EL2_TCR_EL1_MASK GENMASK(32, 32)
#define S_ISBLK(m) (((m) & S_IFMT) == S_IFBLK)
#define ___set_bit arch___set_bit
#define SUPPORTED_10000baseKR_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKR_Full)
#define CONSOLE_LOGLEVEL_DEFAULT CONFIG_CONSOLE_LOGLEVEL_DEFAULT
#define IORESOURCE_MEM_WRITEABLE (1<<0)
#define FIXMAP_PAGE_NORMAL PAGE_KERNEL
#define printk_ratelimited(fmt,...) ({ static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); if (__ratelimit(&_rs)) printk(fmt, ##__VA_ARGS__); })
#define THREAD_SIZE (UL(1) << THREAD_SHIFT)
#define DEFINE_RES_DMA_NAMED(_dma,_name) DEFINE_RES_NAMED((_dma), 1, (_name), IORESOURCE_DMA)
#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE - __ARCH_SIGEV_PREAMBLE_SIZE) / sizeof(int))
#define BRK64_OPCODE_UPROBES (AARCH64_BREAK_MON | (UPROBES_BRK_IMM << 5))
#define SCHED_NORMAL 0
#define EOPENSTALE 518
#define HDFGWTR_EL2_TRFCR_EL1_MASK GENMASK(49, 49)
#define BTF_TYPE_TAG(value) 
#define SYS_DACR32_EL2_Op0 3
#define SYS_DACR32_EL2_Op1 4
#define SYS_DACR32_EL2_Op2 0
#define SCTLR_EL1_EnDA_SHIFT 27
#define HFGxTR_EL2_VBAR_EL1_MASK GENMASK(38, 38)
#define F_SETPIPE_SZ (F_LINUX_SPECIFIC_BASE + 7)
#define __NR_cachestat 451
#define ID_MMFR0_EL1_AuxReg_AIFSR UL(0b0010)
#define CAP_FS_MASK (BIT_ULL(CAP_CHOWN) | BIT_ULL(CAP_MKNOD) | BIT_ULL(CAP_DAC_OVERRIDE) | BIT_ULL(CAP_DAC_READ_SEARCH) | BIT_ULL(CAP_FOWNER) | BIT_ULL(CAP_FSETID) | BIT_ULL(CAP_MAC_OVERRIDE))
#define PR_SET_FPEXC 12
#define S32_MAX ((s32)(U32_MAX >> 1))
#define SYS_GMID_EL1_Op0 3
#define SYS_GMID_EL1_Op1 1
#define SYS_GMID_EL1_Op2 4
#define SOL_IUCV 277
#define ID_AA64MMFR3_EL1_D128_2_IMP UL(0b0001)
#define FMODE_BACKING ((__force fmode_t)0x2000000)
#define ID_AA64PFR1_EL1_SME_SME2 UL(0b0010)
#define MSEC_TO_HZ_SHR32 33
#define ESR_ELx_COND_SHIFT (20)
#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
#define MHI_NAME_SIZE 32
#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
#define ESR_ELx_EC_SERROR (0x2F)
#define move_pte(pte,prot,old_addr,new_addr) (pte)
#define compat_sp_und regs[23]
#define MSG_RST 0x1000
#define HDFGRTR_EL2_TRCID_MASK GENMASK(40, 40)
#define MII_RESV1 0x17
#define HFGxTR_EL2_APIBKey_MASK GENMASK(8, 8)
#define ID_ISAR1_EL1_Except_NI UL(0b0000)
#define __NR_sched_getattr 275
#define TCR2_EL1x_PIE_SHIFT 1
#define ID_AA64ISAR2_EL1_RPRFM_WIDTH 4
#define __HAVE_ARCH_STRNCMP 
#define ID_AA64MMFR3_EL1_ADERR_SIGNED false
#define ID_AA64PFR1_EL1_BT_IMP UL(0b0001)
#define PACKET_FANOUT_LB 1
#define ID_AA64ISAR2_EL1_PAC_frac_SHIFT 24
#define IORESOURCE_DMA_BYTE (1<<3)
#define INPUT_DEVICE_ID_EV_MAX 0x1f
#define ID_ISAR2_EL1_LoadStore_MASK GENMASK(3, 0)
#define ETHTOOL_GRXCLSRLALL 0x00000030
#define skb_rb_next(skb) rb_to_skb(rb_next(&(skb)->rbnode))
#define KBUILD_MODNAME "bindings_generated"
#define HCRX_EL2_EnAS0_SHIFT 0
#define MVFR1_EL1_SIMDHP GENMASK(23, 20)
#define p4d_val(x) (pgd_val((x).pgd))
#define PMSIDR_EL1_FE_WIDTH 1
#define ID_AA64SMFR0_EL1_FA64_IMP UL(0b1)
#define devm_request_region(dev,start,n,name) __devm_request_region(dev, &ioport_resource, (start), (n), (name))
#define _K_SS_MAXSIZE 128
#define ID_AA64MMFR1_EL1_SpecSEI_SHIFT 24
#define __NR_msgrcv 188
#define SHM_R 0400
#define PR_SPEC_STORE_BYPASS 0
#define TCR2_EL1x_HAFT_MASK GENMASK(11, 11)
#define __ratelimit(state) ___ratelimit(state, __func__)
#define ARCH_TIMER_TYPE_MEM BIT(1)
#define PACKET_MR_UNICAST 3
#define MII_RESV2 0x1a
#define __get_free_page(gfp_mask) __get_free_pages((gfp_mask), 0)
#define STA_PPSSIGNAL 0x0100
#define INPUT_DEVICE_ID_MATCH_BUS 1
#define INIT_LOCAL_LOCK(lockname) { LOCAL_LOCK_DEBUG_INIT(lockname) }
#define EM_MIPS_RS4_BE 10
#define IFF_NOARP IFF_NOARP
#define rcu_pointer_handoff(p) (p)
#define PMSCR_EL2_TS_SHIFT 5
#define HFGITR_EL2_TLBIRVAALE1OS_MASK GENMASK(27, 27)
#define NETIF_F_NTUPLE __NETIF_F(NTUPLE)
#define SUPPORTED_100baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Full)
#define ID_AA64AFR0_EL1_IMPDEF3_WIDTH 4
#define NR_CPUS_BITS 8
#define this_cpu_ptr(ptr) raw_cpu_ptr(ptr)
#define CONFIG_HAVE_MOVE_PUD 1
#define ID_AA64ISAR1_EL1_APA_NI UL(0b0000)
#define ID_ISAR2_EL1_Mult_MLS UL(0b0010)
#define flowi4_scope __fl_common.flowic_scope
#define this_cpu_write_4(pcp,val) _pcp_protect(__percpu_write_32, pcp, (unsigned long)val)
#define KERNEL_HWCAP_MTE __khwcap2_feature(MTE)
#define F_CANCELLK (F_LINUX_SPECIFIC_BASE + 5)
#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
#define ID_AA64PFR1_EL1_DF2_SHIFT 56
#define STATIC_KEY_INIT STATIC_KEY_INIT_FALSE
#define HCRX_EL2_SMPME_SHIFT 5
#define dma_map_sg(d,s,n,r) dma_map_sg_attrs(d, s, n, r, 0)
#define LORC_EL1_RES1 (UL(0))
#define preempt_count_sub(val) __preempt_count_sub(val)
#define HFGxTR_EL2_CSSELR_EL1_WIDTH 1
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
#define subsys_initcall(fn) __define_initcall(fn, 4)
#define HFGxTR_EL2_nPIRE0_EL1 GENMASK(57, 57)
#define ID_AA64MMFR1_EL1_VMIDBits_WIDTH 4
#define HFGITR_EL2_TLBIVAALE1IS GENMASK(33, 33)
#define arch_initcall(fn) __define_initcall(fn, 3)
#define ID_AA64ISAR1_EL1_FCMA_MASK GENMASK(19, 16)
#define VFS_CAP_REVISION VFS_CAP_REVISION_3
#define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000
#define ID_AA64MMFR0_EL1_FGT_SIGNED false
#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32
#define ___ntohs(x) __be16_to_cpu(x)
#define CONT_PTES (1 << (CONT_PTE_SHIFT - PAGE_SHIFT))
#define __FPE_INVASC 12
#define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
#define MDIO_PMA_CTRL2_10GBLX4 0x0004
#define ARCH_SLAB_MINALIGN __alignof__(unsigned long long)
#define TAINT_TEST 18
#define ARM64_HAS_32BIT_EL0_DO_NOT_USE 3
#define HFGITR_EL2_SVC_EL0_WIDTH 1
#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
#define _SRCU_NOTIFIER_HEAD(name,mod) static DEFINE_PER_CPU(struct srcu_data, name ##_head_srcu_data); mod struct srcu_notifier_head name = SRCU_NOTIFIER_INIT(name, name ##_head_srcu_data)
#define ID_AA64PFR0_EL1_EL0_WIDTH 4
#define _LINUX_TIMECOUNTER_H 
#define ID_PFR2_EL1_RAS_frac GENMASK(11, 8)
#define CLONE_ARGS_SIZE_VER1 80
#define nodes_fold(dst,orig,sz) __nodes_fold(&(dst), &(orig), sz, MAX_NUMNODES)
#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
#define __is_noneg_int(x) (__builtin_choose_expr(__is_constexpr(x) && __is_signed(x), x, -1) >= 0)
#define arch_needs_pgtable_deposit() (false)
#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35
#define XCVR_DUMMY3 0x04
#define PAGEMAP_SCAN _IOWR('f', 16, struct pm_scan_arg)
#define _LINUX_SCHED_RT_H 
#define IFF_BROADCAST IFF_BROADCAST
#define CONFIG_ARCH_WANTS_THP_SWAP 1
#define HDFGWTR_EL2_PMSICR_EL1_MASK GENMASK(29, 29)
#define ID_PFR0_EL1_State2_NO_CV UL(0b0001)
#define dev_warn_ratelimited(dev,fmt,...) dev_level_ratelimited(dev_warn, dev, fmt, ##__VA_ARGS__)
#define EM_ADV_DATA_CB(_active_power_cb,_cost_cb) { }
#define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
#define const___test_and_set_bit generic___test_and_set_bit
#define HFGITR_EL2_ERET_MASK GENMASK(51, 51)
#define ___GFP_KSWAPD_RECLAIM 0x800u
#define PACKET_RX_RING 5
#define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32))
#define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
#define PA_SECTION_SHIFT (SECTION_SIZE_BITS)
#define POLLNVAL 0x0020
#define xas_trylock(xas) xa_trylock((xas)->xa)
#define VM_NONE 0x00000000
#define NLA_TYPE_MASK ~(NLA_F_NESTED | NLA_F_NET_BYTEORDER)
#define KUNIT_EXPECT_LT_MSG(test,left,right,fmt,...) KUNIT_BINARY_INT_ASSERTION(test, KUNIT_EXPECTATION, left, <, right, fmt, ##__VA_ARGS__)
#define MT_FLAGS_LOCK_BH 0x200
#define DECLARE_FLEX_ARRAY(TYPE,NAME) __DECLARE_FLEX_ARRAY(TYPE, NAME)
#define CONFIG_NET_VENDOR_DEC 1
#define wait_event_killable_exclusive(wq,condition) ({ int __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_event_killable_exclusive(wq, condition); __ret; })
#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
#define HFGITR_EL2_TLBIVAE1_SHIFT 43
#define DEFINE_STATIC_KEY_MAYBE_RO(cfg,name) __PASTE(_DEFINE_STATIC_KEY_RO_, IS_ENABLED(cfg))(name)
#define set_fixmap_offset_io(idx,phys) __set_fixmap_offset(idx, phys, FIXMAP_PAGE_IO)
#define CONFIG_GENERIC_PHY 1
#define raw_try_cmpxchg_release(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg_release((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define CONFIG_RD_GZIP 1
#define __NR_pwritev 70
#define si_uid _sifields._kill._uid
#define IN6ADDR_INTERFACELOCAL_ALLNODES_INIT { { { 0xff,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1 } } }
#define PR_GET_IO_FLUSHER 58
#define GENMASK_ULL(h,l) (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l))
#define COMPLETION_INITIALIZER(work) { 0, __SWAIT_QUEUE_HEAD_INITIALIZER((work).wait) }
#define IPV6_MULTICAST_IF 17
#define try_cmpxchg(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); kcsan_mb(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define arch_cmpxchg_local arch_cmpxchg_relaxed
#define __ASM__VIRT_H 
#define CONFIG_PANIC_TIMEOUT 0
#define SSB_DEVICE(_vendor,_coreid,_revision) { .vendor = _vendor, .coreid = _coreid, .revision = _revision, }
#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
#define FS_JOURNAL_DATA_FL 0x00004000
#define MDSCR_EL1_TTA_WIDTH 1
#define KUNIT_EXPECT_PTR_EQ_MSG(test,left,right,fmt,...) KUNIT_BINARY_PTR_ASSERTION(test, KUNIT_EXPECTATION, left, ==, right, fmt, ##__VA_ARGS__)
#define write_unlock_irq(lock) _raw_write_unlock_irq(lock)
#define COMPAT_HWCAP_NEON (1 << 12)
#define I2C_NAME_SIZE 20
#define CCSIDR_EL1_NumSets_SHIFT 13
#define PMSIDR_EL1_MAXSIZE_WIDTH 4
#define ID_PFR2_EL1_CSV3_SHIFT 0
#define CONFIG_GRO_CELLS 1
#define KERNEL_HWCAP_SME_I16I32 __khwcap2_feature(SME_I16I32)
#define PLATFORM_NAME_SIZE 20
#define NETLINK_SCSITRANSPORT 18
#define HFGITR_EL2_TLBIRVALE1IS GENMASK(36, 36)
#define HFGITR_EL2_TLBIASIDE1IS GENMASK(30, 30)
#define check_add_overflow(a,b,d) __must_check_overflow(__builtin_add_overflow(a, b, d))
#define __NR_sched_get_priority_max 125
#define ID_PFR1_EL1_Sec_frac_WIDTH 4
#define rcu_check_sparse(p,space) 
#define HDFGRTR_EL2_TRCOSLSR_SHIFT 43
#define SIGTRAP 5
#define CSSELR_EL1_Level_SHIFT 1
#define ISR_EL1_F_MASK GENMASK(6, 6)
#define ID_MMFR4_EL1_LSM_SIGNED false
#define DIV64_U64_ROUND_UP(ll,d) ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); })
#define CONFIG_ARCH_USE_GNU_PROPERTY 1
#define ID_AA64MMFR2_EL1_IDS_0x18 UL(0b0001)
#define CPUCLOCK_PID(clock) ((pid_t) ~((clock) >> 3))
#define CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE 1
#define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
#define TRFCR_ELx_TS_SHIFT 5
#define SUPPORTED_40000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseSR4_Full)
#define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
#define __WARN_FLAGS(flags) __BUG_FLAGS(BUGFLAG_WARNING|(flags))
#define F_GETSIG 11
#define ARM64_UNMAP_KERNEL_AT_EL0 64
#define HWCAP2_SME_FA64 (1 << 30)
#define IPV6_PREFER_SRC_HOME 0x0400
#define PR_SET_TSC 26
#define __const_hweight16(w) (__const_hweight8(w) + __const_hweight8((w) >> 8 ))
#define CLIDR_EL1_LoUU GENMASK(29, 27)
#define __SPIN_LOCK_INITIALIZER(lockname) { { .rlock = ___SPIN_LOCK_INITIALIZER(lockname) } }
#define pgd_populate_safe(mm,pgd,p4d) do { } while (0)
#define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
#define ADVERTISED_BNC __ETHTOOL_LINK_MODE_LEGACY_MASK(BNC)
#define ioread32_rep ioread32_rep
#define PSR_IL_BIT (1 << 20)
#define ID_PFR0_EL1_State0 GENMASK(3, 0)
#define ID_PFR0_EL1_State1 GENMASK(7, 4)
#define ID_PFR0_EL1_State2 GENMASK(11, 8)
#define ID_PFR0_EL1_State3 GENMASK(15, 12)
#define O_DSYNC 00010000
#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c)
#define __NR_acct 89
#define prandom_init_once(pcpu_state) DO_ONCE(prandom_seed_full_state, (pcpu_state))
#define ID_AA64MMFR1_EL1_XNX_NI UL(0b0000)
#define HFGITR_EL2_TLBIVAALE1OS GENMASK(23, 23)
#define IORESOURCE_DISABLED 0x10000000
#define MIN_FDT_ALIGN 8
#define MDIO_ID_ARGS(_id) ((_id)>>31) & 1, ((_id)>>30) & 1, ((_id)>>29) & 1, ((_id)>>28) & 1, ((_id)>>27) & 1, ((_id)>>26) & 1, ((_id)>>25) & 1, ((_id)>>24) & 1, ((_id)>>23) & 1, ((_id)>>22) & 1, ((_id)>>21) & 1, ((_id)>>20) & 1, ((_id)>>19) & 1, ((_id)>>18) & 1, ((_id)>>17) & 1, ((_id)>>16) & 1, ((_id)>>15) & 1, ((_id)>>14) & 1, ((_id)>>13) & 1, ((_id)>>12) & 1, ((_id)>>11) & 1, ((_id)>>10) & 1, ((_id)>>9) & 1, ((_id)>>8) & 1, ((_id)>>7) & 1, ((_id)>>6) & 1, ((_id)>>5) & 1, ((_id)>>4) & 1, ((_id)>>3) & 1, ((_id)>>2) & 1, ((_id)>>1) & 1, (_id) & 1
#define CONFIG_FRAME_WARN 2048
#define __NR_epoll_create1 20
#define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
#define ICH_LR_PENDING_BIT (1ULL << 62)
#define FS_ENCRYPT_FL 0x00000800
#define XCVR_EXTERNAL 0x01
#define __disable_sanitizer_instrumentation 
#define ID_ISAR3_EL1_T32Copy_IMP UL(0b0001)
#define CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS 1
#define ID_AA64PFR1_EL1_MTE_frac_WIDTH 4
#define lockdep_assert(cond) do { WARN_ON(debug_locks && !(cond)); } while (0)
#define __NR_quotactl 60
#define SIOCGSTAMPNS_NEW _IOR(SOCK_IOC_TYPE, 0x07, long long[2])
#define HFGxTR_EL2_APDBKey GENMASK(5, 5)
#define PR_SET_TIMING 14
#define SB_NOEXEC BIT(3)
#define CAP_MAC_ADMIN 33
#define ELF_CORE_COPY_REGS(dest,regs) *(struct user_pt_regs *)&(dest) = (regs)->user_regs;
#define KERNEL_HWCAP_SME_I16I64 __khwcap2_feature(SME_I16I64)
#define DEFINE_KLIST(_name,_get,_put) struct klist _name = KLIST_INIT(_name, _get, _put)
#define PMBSR_EL1_COLL_SHIFT 16
#define ID_AA64ISAR0_EL1_SM3_SHIFT 36
#define ETH_P_BATMAN 0x4305
#define raw_spin_trylock(lock) __cond_lock(lock, _raw_spin_trylock(lock))
#define __const_hweight32(w) (__const_hweight16(w) + __const_hweight16((w) >> 16))
#define DEVICE_ATTR_WO(_name) struct device_attribute dev_attr_ ##_name = __ATTR_WO(_name)
#define MMF_HAS_MDWE_MASK (1 << MMF_HAS_MDWE)
#define XA_FLAGS_LOCK_IRQ ((__force gfp_t)XA_LOCK_IRQ)
#define ID_ISAR5_EL1_VCMA_WIDTH 4
#define SB_BORN BIT(29)
#define SMPRIMAP_EL2_P7_WIDTH 4
#define RLIMIT_MSGQUEUE 12
#define HFGxTR_EL2_TPIDR_EL1_SHIFT 33
#define CLIDR_EL1_Ctype1_SHIFT 0
#define SHM_HUGE_512KB HUGETLB_FLAG_ENCODE_512KB
#define MDSCR_EL1_SC2_SHIFT 19
#define ID_AA64PFR1_EL1_MTE GENMASK(11, 8)
#define ID_PFR1_EL1_Virt_frac_WIDTH 4
#define raw_cpu_write_1(pcp,val) raw_cpu_generic_to_op(pcp, val, =)
#define raw_cpu_write_2(pcp,val) raw_cpu_generic_to_op(pcp, val, =)
#define cpu_online_mask ((const struct cpumask *)&__cpu_online_mask)
#define raw_cpu_write_4(pcp,val) raw_cpu_generic_to_op(pcp, val, =)
#define raw_cpu_write_8(pcp,val) raw_cpu_generic_to_op(pcp, val, =)
#define PIRx_ELx_Perm9_WIDTH 4
#define MAX_ZONES_PER_ZONELIST (MAX_NUMNODES * MAX_NR_ZONES)
#define HFGxTR_EL2_ERXFR_EL1_SHIFT 42
#define Elf_Rela Elf64_Rela
#define offsetofend(TYPE,MEMBER) (offsetof(TYPE, MEMBER) + sizeof_field(TYPE, MEMBER))
#define __NETIF_F(name) __NETIF_F_BIT(NETIF_F_ ##name ##_BIT)
#define CurrentEL_EL1 (1 << 2)
#define HDFGWTR_EL2_PMSFCR_EL1_MASK GENMASK(28, 28)
#define CONFIG_RESET_CONTROLLER 1
#define ETHTOOL_F_COMPAT (1 << ETHTOOL_F_COMPAT__BIT)
#define clear_fixmap(idx) __set_fixmap(idx, 0, FIXMAP_PAGE_CLEAR)
#define SECTION_NID_SHIFT SECTION_MAP_LAST_BIT
#define HFGITR_EL2_TLBIRVAALE1IS_WIDTH 1
#define __NR_mlock 228
#define compat_user_mode(regs) (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == (PSR_MODE32_BIT | PSR_MODE_EL0t))
#define FS_TOPDIR_FL 0x00020000
#define ID_ISAR2_EL1_MultiAccessInt_NI UL(0b0000)
#define SMCR_ELx_FA64_WIDTH 1
#define raw_try_cmpxchg64(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg64((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
#define PR_SYS_DISPATCH_OFF 0
#define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
#define ID_ISAR1_EL1_Extend_SXTB UL(0b0001)
#define __NR_userfaultfd 282
#define ID_AA64MMFR1_EL1_XNX_MASK GENMASK(31, 28)
#define INIT_DELAYED_WORK_ONSTACK(_work,_func) __INIT_DELAYED_WORK_ONSTACK(_work, _func, 0)
#define HDFGRTR_EL2_TRCID_WIDTH 1
#define SYS_ID_AA64MMFR3_EL1 sys_reg(3, 0, 0, 7, 3)
#define VM_SPECIAL (VM_IO | VM_DONTEXPAND | VM_PFNMAP | VM_MIXEDMAP)
#define ID_MMFR4_EL1_HPDS_WIDTH 4
#define FS_REQUIRES_DEV 1
#define arch_atomic_fetch_xor_acquire arch_atomic_fetch_xor_acquire
#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
#define STA_INS 0x0010
#define HDFGRTR_EL2_PMSEVFR_EL1_MASK GENMASK(27, 27)
#define ETHTOOL_COALESCE_STATS_BLOCK_USECS BIT(8)
#define MAX_PRIO (MAX_RT_PRIO + NICE_WIDTH)
#define ID_AA64MMFR0_EL1_FGT_NI UL(0b0000)
#define DT_PLTREL 20
#define FOLIO_PF_HEAD 0
#define local_inc(l) atomic_long_inc(&(l)->a)
#define _LINUX_SRCU_H 
#define ID_ISAR6_EL1_BF16_SHIFT 20
#define BP_HARDEN_EL2_SLOTS 4
#define CAP_TO_INDEX(x) ((x) >> 5)
#define set_pmd_safe(pmdp,pmd) ({ WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); set_pmd(pmdp, pmd); })
#define __const_hweight64(w) (__const_hweight32(w) + __const_hweight32((w) >> 32))
#define HFGITR_EL2_TLBIASIDE1OS GENMASK(20, 20)
#define __NR_fspick 433
#define COMPAT_PT_TEXT_END_ADDR 0x10008
#define HCRX_EL2_EnASR_SHIFT 2
#define ETH_P_MPLS_UC 0x8847
#define ATM_POISON 0xdeadbeef
#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16
#define BUILD_ID_SIZE_MAX 20
#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
#define QIF_TIMES (QIF_BTIME | QIF_ITIME)
#define XA_FLAGS_ALLOC_WRAPPED ((__force gfp_t)16U)
#define _LINUX_LOG2_H 
#define PM_EVENT_ON 0x0000
#define LAST_CPUPID_PGOFF (ZONES_PGOFF - LAST_CPUPID_WIDTH)
#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
#define __VDSO_KTIME_H 
#define ID_MMFR0_EL1_VMSA_SHIFT 0
#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
#define current_real_cred() rcu_dereference_protected(current->real_cred, 1)
#define ETH_P_PREAUTH 0x88C7
#define is_unsigned_type(type) (!is_signed_type(type))
#define PAGES_PER_SECTION (1UL << PFN_SECTION_SHIFT)
#define CPTR_NVHE_EL2_RES1 0x000032ff
#define update_mmu_cache_pmd(vma,address,pmd) do { } while (0)
#define ID_AA64MMFR2_EL1_VARange_52 UL(0b0001)
#define VTTBR_CNP_BIT (UL(1))
#define __LINUX_KERNFS_H 
#define ptrauth_strip_kernel_insn_pac(ptr) (ptr)
#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
#define OSDTRTX_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define OSDTRTX_EL1_RES1 (UL(0))
#define __diag_ignore_all(option,comment) __diag(__diag_GCC_ignore option)
#define __UAPI_DEF_IPPROTO_V6 1
#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(int) * 2 + sizeof(sigval_t))
#define NT_MIPS_DSP 0x800
#define PTE_USER (_AT(pteval_t, 1) << 6)
#define DECLARE_WAITQUEUE(name,tsk) struct wait_queue_entry name = __WAITQUEUE_INITIALIZER(name, tsk)
#define VTCR_EL2_SH0_INNER TCR_SH0_INNER
#define NETLINK_ECRYPTFS 19
#define ESR_ELx_ISS_MASK (GENMASK(24, 0))
#define SOFTIRQ_OFFSET (1UL << SOFTIRQ_SHIFT)
#define SECTION_SIZE_BITS 27
#define special_file(m) (S_ISCHR(m)||S_ISBLK(m)||S_ISFIFO(m)||S_ISSOCK(m))
#define pud_free_tlb(tlb,x,a) do { } while (0)
#define ESR_ELx_FSC_EXTABT (0x10)
#define __NR_flistxattr 13
#define MAPLE_NODE_MASK 255UL
#define TIF_SIGPENDING 0
#define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
#define SCTLR_EL1_SPAN_MASK GENMASK(23, 23)
#define _LINUX_POLL_H 
#define ID_MMFR1_EL1_L1UniVA GENMASK(7, 4)
#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
#define SCTLR_EL1_EnALS_WIDTH 1
#define SCTLR_EL1_UCI_MASK GENMASK(26, 26)
#define DEFINE_MUTEX(mutexname) struct mutex mutexname = __MUTEX_INITIALIZER(mutexname)
#define __ASM_CACHEFLUSH_H 
#define CONFIG_WLAN_VENDOR_RSI 1
#define SYS_LORC_EL1_Op0 3
#define SYS_LORC_EL1_Op1 0
#define SYS_LORC_EL1_Op2 3
#define S_ISLNK(m) (((m) & S_IFMT) == S_IFLNK)
#define HFGxTR_EL2_LORN_EL1_MASK GENMASK(22, 22)
#define JOBCTL_TRAP_FREEZE_BIT 23
#define MINORBITS 20
#define struct_group(NAME,MEMBERS...) __struct_group( , NAME, , MEMBERS)
#define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
#define format_dev_t(buffer,dev) ({ sprintf(buffer, "%u:%u", MAJOR(dev), MINOR(dev)); buffer; })
#define PT_DYNAMIC 2
#define SYS_ID_MMFR3_EL1_Op1 0
#define SYS_ID_MMFR3_EL1_Op2 7
#define for_each_sg_page(sglist,piter,nents,pgoffset) for (__sg_page_iter_start((piter), (sglist), (nents), (pgoffset)); __sg_page_iter_next(piter);)
#define HDFGWTR_EL2_TRCCLAIM GENMASK(36, 36)
#define PT_TRACESYSGOOD PT_EVENT_FLAG(0)
#define GOLDEN_RATIO_PRIME GOLDEN_RATIO_64
#define ID_AA64DFR0_EL1_TraceFilt_NI UL(0b0000)
#define flowi4_tos __fl_common.flowic_tos
#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
#define LOCKDEP_RECURSION_BITS 16
#define test_bit_acquire(nr,addr) bitop(_test_bit_acquire, nr, addr)
#define SECCOMP_MODE_STRICT 1
#define __LINUX__AIO_ABI_H 
#define arch_atomic_fetch_and arch_atomic_fetch_and
#define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
#define IOCTL_MEI_NOTIFY_GET _IOR('H', 0x03, __u32)
#define MDIO_PMA_LASI_TXALARM 0x0002
#define MDIO_PCS_CTRL2_10GBR 0x0000
#define INVALID_PROJID KPROJIDT_INIT(-1)
#define MOD_OFFSET ADJ_OFFSET
#define __cpu_to_be64s(x) __swab64s((x))
#define MDIO_PCS_1000BT1_CTRL_DISABLE_TX 0x4000
#define ID_DFR0_EL1_CopDbg_WIDTH 4
#define ID_AA64DFR0_EL1_TraceFilt GENMASK(43, 40)
#define IPC_DIPC 00010000
#define _QW_LOCKED 0x0ff
#define PG_guard 0x00000400
#define MII_BUS_ID_SIZE 61
#define F_GET_SEALS (F_LINUX_SPECIFIC_BASE + 10)
#define PER_CLEAR_ON_SETID (READ_IMPLIES_EXEC | ADDR_NO_RANDOMIZE | ADDR_COMPAT_LAYOUT | MMAP_PAGE_ZERO)
#define _LINUX_NETDEV_FEATURES_H 
#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
#define PMSNEVFR_EL1_E_MASK GENMASK(63, 0)
#define CONFIG_DUMMY_CONSOLE_ROWS 25
#define _LINUX_JIFFIES_H 
#define NODES_MASK ((1UL << NODES_WIDTH) - 1)
#define PR_SCHED_CORE_MAX 4
#define ARM64_HAS_E0PD 18
#define time_is_before_eq_jiffies(a) time_after_eq(jiffies, a)
#define DCACHE_DIRECTORY_TYPE 0x00200000
#define MDIO_PMA_10T1L_CTRL_TX_DIS 0x4000
#define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_KERNEL_EXEC_CONT)
#define ID_ISAR6_EL1_BF16_MASK GENMASK(23, 20)
#define SYS_MPAMVPM2_EL2 __SYS__MPAMVPMx_EL2(2)
#define CONFIG_HZ 250
#define _LINUX_ONCE_LITE_H 
#define MT_NORMAL_NC 2
#define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
#define HCR_BSU_IS (UL(1) << 10)
#define MDIO_PMA_STAT2_10GBLR 0x0040
#define ETHTOOL_GCHANNELS 0x0000003c
#define CONFIG_ARCH_APPLE 1
#define NT_PPC_TM_CGPR 0x108
#define PMSNEVFR_EL1_E GENMASK(63, 0)
#define ID_AA64SMFR0_EL1_F16F16_IMP UL(0b1)
#define HWCAP2_LSE128 (1UL << 47)
#define HFGxTR_EL2_TTBR0_EL1_WIDTH 1
#define for_each_or_bit(bit,addr1,addr2,size) for ((bit) = 0; (bit) = find_next_or_bit((addr1), (addr2), (size), (bit)), (bit) < (size); (bit)++)
#define SKB_LIST_POISON_NEXT ((void *)(0x800 + POISON_POINTER_DELTA))
#define PR_SET_MM_ENV_START 10
#define PMSCR_EL2_E0HSPE_MASK GENMASK(0, 0)
#define ID_AA64DFR0_EL1_PMSVer_MASK GENMASK(35, 32)
#define TRBPTR_EL1_RES1 (UL(0))
#define netdev_vdbg(dev,format,args...) ({ if (0) netdev_printk(KERN_DEBUG, dev, format, ##args); 0; })
#define MIDR_PARTNUM_SHIFT 4
#define SECTIONS_PGSHIFT (SECTIONS_PGOFF * (SECTIONS_WIDTH != 0))
#define SPEED_100000 100000
#define VM_LOCKONFAULT 0x00080000
#define FIFREEZE _IOWR('X', 119, int)
#define INIT_PREEMPT_COUNT PREEMPT_OFFSET
#define ETH_DATA_LEN 1500
#define SCHED_FLAG_ALL (SCHED_FLAG_RESET_ON_FORK | SCHED_FLAG_RECLAIM | SCHED_FLAG_DL_OVERRUN | SCHED_FLAG_KEEP_ALL | SCHED_FLAG_UTIL_CLAMP)
#define _LINUX_SWAIT_H 
#define ID_AA64MMFR3_EL1_MEC_SIGNED false
#define HFGxTR_EL2_ISR_EL1_SHIFT 18
#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
#define TASK_REPORT (TASK_RUNNING | TASK_INTERRUPTIBLE | TASK_UNINTERRUPTIBLE | __TASK_STOPPED | __TASK_TRACED | EXIT_DEAD | EXIT_ZOMBIE | TASK_PARKED)
#define REG_TRBBASER_EL1 S3_0_C9_C11_2
#define DT_FLAGS_1 0x6ffffffb
#define PTR_IF(cond,ptr) ((cond) ? (ptr) : NULL)
#define CONFIG_PCI_SYSCALL 1
#define __NR_recvmsg 212
#define PTRACE_PEEKSIGINFO_SHARED (1 << 0)
#define ID_ISAR0_EL1_BitCount GENMASK(7, 4)
#define PACKET_FANOUT_FLAG_DEFRAG 0x8000
#define NETLINK_FIB_LOOKUP 10
#define ID_AA64MMFR2_EL1_CCIDX_32 UL(0b0000)
#define KERNEL_END _end
#define ID_MMFR0_EL1_InnerShr_SHIFT 28
#define wait_event_idle_exclusive(wq_head,condition) do { might_sleep(); if (!(condition)) ___wait_event(wq_head, condition, TASK_IDLE, 1, 0, schedule()); } while (0)
#define ID_AA64MMFR3_EL1_TCRX_SIGNED false
#define __phys_to_pfn(paddr) PHYS_PFN(paddr)
#define HFGxTR_EL2_LORID_EL1_SHIFT 21
#define SHM_LOCK 11
#define ID_AA64ISAR0_EL1_DP_SHIFT 44
#define ID_MMFR0_EL1_VMSA GENMASK(3, 0)
#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK(19, 16)
#define PR_RISCV_V_VSTATE_CTRL_DEFAULT 0
#define _LINUX_PLIST_H_ 
#define MDIO_PMA_EXTABLE_10GBKR 0x0010
#define MDIO_PMA_TXDIS 9
#define for_each_sgtable_page(sgt,piter,pgoffset) for_each_sg_page((sgt)->sgl, piter, (sgt)->orig_nents, pgoffset)
#define cpu_none_mask to_cpumask(cpu_bit_bitmap[0])
#define PMSCR_EL1_E1SPE_WIDTH 1
#define F_OFD_GETLK 36
#define PMSEVFR_EL1_RES0_IMP (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) | BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
#define __KBUILD_MODNAME kmod_bindings_generated
#define ID_AA64ISAR2_EL1_RPRES_IMP UL(0b0001)
#define __NR_munlockall 231
#define DACR32_EL2_D3_MASK GENMASK(7, 6)
#define FAR_EL1_ADDR_WIDTH 64
#define cmpxchg_local(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg_local(__ai_ptr, __VA_ARGS__); })
#define __NR_getitimer 102
#define HDFGWTR_EL2_TRFCR_EL1_SHIFT 49
#define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
#define __INTMAX_C(c) c ## L
#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
#define LED_UNREGISTERING BIT(1)
#define PR_GET_TIMING 13
#define ID_AA64MMFR3_EL1_S2PIE_MASK GENMASK(15, 12)
#define ID_ISAR5_EL1_AES_MASK GENMASK(7, 4)
#define SD_ATTR_INIT (struct sched_domain_attr) { .relax_domain_level = -1, }
#define LEDS_GPIO_DEFSTATE_KEEP LEDS_DEFSTATE_KEEP
#define ESR_ELx_TagAccess_SHIFT (9)
#define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
#define lockdep_hardirq_enter() do { if (__this_cpu_inc_return(hardirq_context) == 1) current->hardirq_threaded = 0; } while (0)
#define QCI_SYSFILE (1 << 0)
#define _LINUX_STDARG_H 
#define _LINUX_PTRACE_H 
#define cond_resched_lock(lock) ({ __might_resched(__FILE__, __LINE__, PREEMPT_LOCK_RESCHED_OFFSETS); __cond_resched_lock(lock); })
#define ESR_ELx_SME_ISS_ILL 1
#define TCR2_EL2_PnCH_SHIFT 0
#define arch_atomic64_fetch_andnot_acquire arch_atomic64_fetch_andnot_acquire
#define __NR_sendmmsg 269
#define ID_AA64MMFR0_EL1_RES0 (UL(0) | GENMASK_ULL(55, 48))
#define ID_AA64MMFR0_EL1_RES1 (UL(0))
#define try_then_request_module(x,mod...) (x)
#define ID_AA64ISAR1_EL1_DPB_MASK GENMASK(3, 0)
#define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1
#define AS_KUIDT(val) (kuid_t){ __vfsuid_val(val) }
#define OPEN_FMODE(flag) ((__force fmode_t)(((flag + 1) & O_ACCMODE) | (flag & __FMODE_NONOTIFY)))
#define ETH_P_PROFINET 0x8892
#define SOL_X25 262
#define NLMSG_DONE 0x3
#define _LINUX_KEY_H 
#define flowi_flags u.__fl_common.flowic_flags
#define ID_AA64PFR0_EL1_GIC_SIGNED false
#define lockdep_assert_preemption_enabled() do { WARN_ON_ONCE(IS_ENABLED(CONFIG_PREEMPT_COUNT) && __lockdep_enabled && (preempt_count() != 0 || !this_cpu_read(hardirqs_enabled))); } while (0)
#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))
#define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
#define I3C_MATCH_DCR 0x1
#define OSDTRRX_EL1_DTRRX_MASK GENMASK(31, 0)
#define arch_test_bit_acquire generic_test_bit_acquire
#define __ATTR_RW_MODE(_name,_mode) { .attr = { .name = __stringify(_name), .mode = VERIFY_OCTAL_PERMISSIONS(_mode) }, .show = _name ##_show, .store = _name ##_store, }
#define EM_X86_64 62
#define xa_for_each_marked(xa,index,entry,filter) for (index = 0, entry = xa_find(xa, &index, ULONG_MAX, filter); entry; entry = xa_find_after(xa, &index, ULONG_MAX, filter))
#define ID_AA64MMFR2_EL1_CCIDX_64 UL(0b0001)
#define EM_BLACKFIN 106
#define ID_AA64DFR0_EL1_DebugVer_SHIFT 0
#define DPM_FLAG_SMART_PREPARE BIT(1)
#define ETH_P_ATMMPOA 0x884c
#define POISON_END 0xa5
#define ID_ISAR6_EL1_SPECRES_MASK GENMASK(19, 16)
#define __NR_futex_waitv 449
#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
#define TCR_EL2_RES1 ((1U << 31) | (1 << 23))
#define set_handle_irq set_handle_irq
#define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
#define ptep_clear_flush_young_notify ptep_clear_flush_young
#define FPE_INTOVF 2
#define BMSR_100HALF 0x2000
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
#define preempt_enable_no_resched_notrace() do { barrier(); __preempt_count_dec(); } while (0)
#define CONFIG_ARM64_VA_BITS 39
#define local_unlock_irq(lock) __local_unlock_irq(lock)
#define PMSIDR_EL1_ARCHINST GENMASK(3, 3)
#define ID_ISAR0_EL1_Divide_SHIFT 24
#define CONFIG_BUILDTIME_TABLE_SORT 1
#define _UAPI__ASM_GENERIC_SIGNAL_H 
#define CONFIG_VIRTIO_BLK 1
#define __NR_landlock_create_ruleset 444
#define kunit_log(lvl,test_or_suite,fmt,...) do { printk(lvl fmt, ##__VA_ARGS__); kunit_log_append((test_or_suite)->log, fmt, ##__VA_ARGS__); } while (0)
#define CONFIG_OF 1
#define DCACHE_MOUNTED 0x00010000
#define TBSVC_MATCH_PROTOCOL_ID 0x0002
#define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP 93
#define MVFR0_EL1_FPSP_VFPv2 UL(0b0001)
#define MDSCR_EL1_EMBWE_SHIFT 32
#define SIGPROF 27
#define __tlbi_level(op,addr,level) do { u64 arg = addr; if (alternative_has_cap_unlikely(ARM64_HAS_ARMv8_4_TTL) && level) { u64 ttl = level & 3; ttl |= get_trans_granule() << 2; arg &= ~TLBI_TTL_MASK; arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); } __tlbi(op, arg); } while(0)
#define sector_div(a,b) do_div(a, b)
#define __INIT .section ".init.text","ax"
#define IORESOURCE_IRQ_OPTIONAL (1<<5)
#define ID_AA64PFR1_EL1_NMI_SHIFT 36
#define ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3 26
#define ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5 27
#define DT_HIPROC 0x7fffffff
#define PF_TIPC AF_TIPC
#define HFGxTR_EL2_nS2POR_EL1_WIDTH 1
#define EXPORT_PM_FN_GPL(name) EXPORT_SYMBOL_GPL(name)
#define PUD_TYPE_SECT (_AT(pudval_t, 1) << 0)
#define COMPAT_SYSCALL_DEFINE1(name,...) COMPAT_SYSCALL_DEFINEx(1, _ ##name, __VA_ARGS__)
#define TIF_FREEZE 19
#define MDIO_AN_10GBT_STAT_MS 0x4000
#define PMSNEVFR_EL1_RES1 (UL(0))
#define __LINUX_BIT_SPINLOCK_H 
#define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS)
#define node_present_pages(nid) (NODE_DATA(nid)->node_present_pages)
#define DACR32_EL2_D2_SHIFT 4
#define PAGE_FLAGS_CHECK_AT_FREE (1UL << PG_lru | 1UL << PG_locked | 1UL << PG_private | 1UL << PG_private_2 | 1UL << PG_writeback | 1UL << PG_reserved | 1UL << PG_slab | 1UL << PG_active | 1UL << PG_unevictable | __PG_MLOCKED | LRU_GEN_MASK)
#define HDFGRTR_EL2_nBRBDATA_WIDTH 1
#define MAX_NON_LFS ((1UL<<31) - 1)
#define SOL_IPX 256
#define CONFIG_PM 1
#define __compiletime_warning(msg) __attribute__((__warning__(msg)))
#define CTR_EL0_L1Ip_SHIFT 14
#define ETHTOOL_SRXCLSRLDEL 0x00000031
#define HDFGRTR_EL2_DBGWVRn_EL1 GENMASK(3, 3)
#define __atomic_pre_full_fence smp_mb__before_atomic
#define ID_AA64ISAR2_EL1_PAC_frac GENMASK(27, 24)
#define MTREE_INIT(name,__flags) { .ma_lock = __SPIN_LOCK_UNLOCKED((name).ma_lock), .ma_flags = __flags, .ma_root = NULL, }
#define ID_ISAR6_EL1_DP_NI UL(0b0000)
#define MDIO_USXGMII_SPD_MASK 0x0e00
#define ID_MMFR3_EL1_BPMaint_SHIFT 8
#define pr_alert_ratelimited(fmt,...) printk_ratelimited(KERN_ALERT pr_fmt(fmt), ##__VA_ARGS__)
#define mdelay(n) ( (__builtin_constant_p(n) && (n)<=MAX_UDELAY_MS) ? udelay((n)*1000) : ({unsigned long __ms=(n); while (__ms--) udelay(1000);}))
#define SVE_PT_SVE_FPSR_OFFSET(vq) ((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
#define HFGITR_EL2_TLBIRVAAE1OS_MASK GENMASK(25, 25)
#define __ATTR_RO_MODE(_name,_mode) { .attr = { .name = __stringify(_name), .mode = VERIFY_OCTAL_PERMISSIONS(_mode) }, .show = _name ##_show, }
#define _UAPI_ASM_GENERIC_TYPES_H 
#define ID_AA64MMFR2_EL1_E0PD_SHIFT 60
#define SYS_TRBLIMITR_EL1_Op0 3
#define SYS_TRBLIMITR_EL1_Op2 0
#define CLEARPAGEFLAG(uname,lname,policy) static __always_inline void folio_clear_ ##lname(struct folio *folio) { clear_bit(PG_ ##lname, folio_flags(folio, FOLIO_ ##policy)); } static __always_inline void ClearPage ##uname(struct page *page) { clear_bit(PG_ ##lname, &policy(page, 1)->flags); }
#define TIME64_MAX ((s64)~((u64)1 << 63))
#define ETHTOOL_FWVERS_LEN 32
#define CONFIG_HAVE_DEBUG_KMEMLEAK 1
#define PORT_TP 0x00
#define NETIF_F_GSO_ROBUST __NETIF_F(GSO_ROBUST)
#define __ARM64_ASM_SIGNAL_H 
#define SECTION_ALIGN_DOWN(pfn) ((pfn) & PAGE_SECTION_MASK)
#define CONFIG_CLANG_VERSION 0
#define __fid_enumify(ENUM,dummy) READING_ ## ENUM,
#define MDIO_PMA_CTRL2_100BTX 0x000e
#define ID_MMFR2_EL1_MemBarr_SHIFT 20
#define __must_check __attribute__((__warn_unused_result__))
#define PAGE_IS_HUGE (1 << 6)
#define SYS_ICC_NMIAR1_EL1_Op1 0
#define CAP_DAC_READ_SEARCH 2
#define IFF_MULTICAST IFF_MULTICAST
#define ETH_P_LOOPBACK 0x9000
#define arch_atomic_fetch_andnot arch_atomic_fetch_andnot
#define DACR32_EL2_D12_WIDTH 2
#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
#define MDSCR_EL1_EnSPM_MASK GENMASK(34, 34)
#define HDFGWTR_EL2_TRC GENMASK(33, 33)
#define arch_atomic_sub_return_acquire arch_atomic_sub_return_acquire
#define SECCOMP_GET_NOTIF_SIZES 3
#define IEEE1394_MATCH_VERSION 0x0008
#define Elf_Phdr Elf64_Phdr
#define lock_set_novalidate_class(l,n,i) lock_set_class(l, n, &__lockdep_no_validate__, 0, i)
#define KUNIT_SUCCEED(test) do {} while (0)
#define KERNEL_HWCAP_SVE_B16B16 __khwcap2_feature(SVE_B16B16)
#define __initconst __section(".init.rodata")
#define SYS_CONTEXTIDR_EL1_Op0 3
#define SYS_CONTEXTIDR_EL1_Op1 0
#define SYS_CONTEXTIDR_EL1_Op2 1
#define CLOCK_SGI_CYCLE 10
#define SIOCGMIIPHY 0x8947
#define ptep_modify_prot_start ptep_modify_prot_start
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
#define HDFGRTR_EL2_PMBSR_EL1_SHIFT 25
#define LOCK_PADSIZE (offsetof(struct raw_spinlock, dep_map))
#define CLIDR_EL1_Ttypen_WIDTH 14
#define SMIDR_EL1_AFFINITY_WIDTH 12
#define hlist_for_each_entry(pos,head,member) for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member); pos; pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
#define HDFGRTR_EL2_TRBBASER_EL1 GENMASK(50, 50)
#define dev_err_once(dev,fmt,...) dev_level_once(dev_err, dev, fmt, ##__VA_ARGS__)
#define MDIO_DEVS2 6
#define LORSA_EL1_Valid_WIDTH 1
#define __le32_to_cpus(x) do { (void)(x); } while (0)
#define try_cmpxchg128_local(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg128_local(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define TIF_UPROBE 4
#define P4D_SECT_RDONLY (_AT(p4dval_t, 1) << 7)
#define _LINUX_SCHED_CPUFREQ_H 
#define HDFGWTR_EL2_PMBPTR_EL1_SHIFT 24
#define DN_ATTRIB 0x00000020
#define FLOW_KEYS_DIGEST_LEN 16
#define HDFGWTR_EL2_TRCCNTVRn_MASK GENMASK(37, 37)
#define PSR_MODE_MASK 0x0000000f
#define ID_AA64ISAR0_EL1_SHA1_NI UL(0b0000)
#define TCR2_EL2_HAFT_MASK GENMASK(11, 11)
#define CPUMAP_FILE_MAX_BYTES (((NR_CPUS * 9)/32 > PAGE_SIZE) ? (NR_CPUS * 9)/32 - 1 : PAGE_SIZE)
#define CONFIG_MAILBOX 1
#define CONFIG_CLONE_BACKWARDS 1
#define MDIO_PCS_10GBX_STAT1 24
#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4]
#define HDFGWTR_EL2_OSDLR_EL1_WIDTH 1
#define ID_MMFR5_EL1_ETS_SHIFT 0
#define pte_val(x) ((x).pte)
#define list_for_each_entry_continue_rcu(pos,head,member) for (pos = list_entry_rcu(pos->member.next, typeof(*pos), member); &pos->member != (head); pos = list_entry_rcu(pos->member.next, typeof(*pos), member))
#define ID_MMFR4_EL1_CCIDX GENMASK(27, 24)
#define SMIDR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32) | GENMASK_ULL(14, 12))
#define SMIDR_EL1_RES1 (UL(0))
#define raw_write_seqcount_begin(s) do { if (seqprop_preemptible(s)) preempt_disable(); do_raw_write_seqcount_begin(seqprop_ptr(s)); } while (0)
#define PTRACE_EVENT_EXIT 6
#define SPEED_25000 25000
#define CONTEXTIDR_ELx_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define CONTEXTIDR_ELx_RES1 (UL(0))
#define SCTLR_EL1_UCT_MASK GENMASK(15, 15)
#define __local_lock(lock) do { preempt_disable(); local_lock_acquire(this_cpu_ptr(lock)); } while (0)
#define arch_spin_value_unlocked(l) queued_spin_value_unlocked(l)
#define CTR_EL0_IminLine_WIDTH 4
#define UMH_KILLABLE 0x04
#define ETHTOOL_COALESCE_RX_USECS_LOW BIT(12)
#define MODULES_END (MODULES_VADDR + MODULES_VSIZE)
#define PMBSR_EL1_EC_FAULT_S1 UL(0b100100)
#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
#define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
#define SB_I_SKIP_SYNC 0x00000100
#define CONFIG_OF_KOBJ 1
#define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
#define MMF_MULTIPROCESS 26
#define __atomic_acquire_fence smp_mb__after_atomic
#define pgd_page(pgd) (p4d_page((p4d_t){ pgd }))
#define ISAPNP_ANY_ID 0xffff
#define PMBLIMITR_EL1_FM GENMASK(2, 1)
#define PMBIDR_EL1_ALIGN_WIDTH 4
#define IPV6_JOIN_ANYCAST 27
#define TIME_OOP 3
#define __PG_HWPOISON 0
#define ATTR_TOUCH (1 << 17)
#define SPARC_ETH_SSET ETHTOOL_SSET
#define PTRACE_CONT 7
#define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54
#define MNT_LOCK_ATIME 0x040000
#define div64_ul(x,y) div64_u64((x), (y))
#define SCTLR_EL1_DZE_WIDTH 1
#define CONFIG_VT 1
#define IOPRIO_DEFAULT IOPRIO_PRIO_VALUE(IOPRIO_CLASS_NONE, 0)
#define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
#define MVFR0_EL1_FPRound_WIDTH 4
#define DEFINE_LED_TRIGGER(x) static struct led_trigger *x;
#define INR_OPEN_MAX 4096
#define NUM_ACTIVE_RCU_POLL_FULL_OLDSTATE 4
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
#define ETHTOOL_COALESCE_USE_ADAPTIVE (ETHTOOL_COALESCE_USE_ADAPTIVE_RX | ETHTOOL_COALESCE_USE_ADAPTIVE_TX)
#define ptrauth_enable() 
#define CMSG_DATA(cmsg) ((void *)(cmsg) + sizeof(struct cmsghdr))
#define ICH_VMCR_FIQ_EN_SHIFT 3
#define HDFGWTR_EL2_PMSELR_EL0_SHIFT 19
#define ENOKEY 126
#define MVFR1_EL1_SIMDLS_WIDTH 4
#define ID_AA64ISAR0_EL1_CRC32_SHIFT 16
#define HFGxTR_EL2_CLIDR_EL1_SHIFT 10
#define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
#define __be16_to_cpus(x) __swab16s((x))
#define CTR_EL0_DminLine_SHIFT 16
#define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
#define __khwcap_feature(x) const_ilog2(HWCAP_ ## x)
#define HDFGWTR_EL2_PMEVCNTRn_EL0 GENMASK(12, 12)
#define HID_ANY_ID (~0)
#define io_wait_event(wq_head,condition) do { might_sleep(); if (condition) break; __io_wait_event(wq_head, condition); } while (0)
#define ARM64_SW_FEATURE_OVERRIDE_NOKASLR 0
#define DN_DELETE 0x00000008
#define S_IWGRP 00020
#define _ASM_GENERIC_KPROBES_H 
#define CONFIG_NET_VENDOR_DLINK 1
#define __compat_uid_t __compat_uid_t
#define TTBRx_EL1_BADDR_MASK GENMASK(47, 1)
#define XXX_LOCK_USAGE_STATES 2
#define SOL_UDPLITE 136
#define PSR_MODE_EL0t 0x00000000
#define SIOCBONDSETHWADDR 0x8992
#define IORESOURCE_MEM_RANGELENGTH (1<<2)
#define SIOCSMIIREG 0x8949
#define __ASM_BARRIER_H 
#define ID_PFR0_EL1_State1_WIDTH 4
#define PT_TRACE_VFORK_DONE PT_EVENT_FLAG(PTRACE_EVENT_VFORK_DONE)
#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
#define KCSAN_ACCESS_COMPOUND (1 << 1)
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0
#define pmd_cont(pmd) pte_cont(pmd_pte(pmd))
#define ID_ISAR1_EL1_Endian_NI UL(0b0000)
#define MDIO_EEE_40GR_DS 0x0200
#define _LINUX_IPC_H 
#define TRFCR_ELx_ExTRE BIT(1)
#define PAGE_MASK (~(PAGE_SIZE-1))
#define LED_FUNCTION_PLAYER2 "player-2"
#define LED_FUNCTION_PLAYER3 "player-3"
#define LED_FUNCTION_PLAYER5 "player-5"
#define ID_AA64MMFR3_EL1_AIE_IMP UL(0b0001)
#define S_IRUGO (S_IRUSR|S_IRGRP|S_IROTH)
#define TIME64_MIN (-TIME64_MAX - 1)
#define ID_AA64ZFR0_EL1_AES_NI UL(0b0000)
#define PSR_MODE_EL1t 0x00000004
#define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200
#define arch_nmi_exit() do { struct nmi_ctx *___ctx; u64 ___hcr; if (!is_kernel_in_hyp_mode()) break; ___ctx = this_cpu_ptr(&nmi_contexts); ___hcr = ___ctx->hcr; barrier(); ___ctx->cnt--; barrier(); if (!___ctx->cnt && !(___hcr & HCR_TGE)) write_sysreg(___hcr, hcr_el2); } while (0)
#define CONFIG_NET_VENDOR_SIS 1
#define HFGITR_EL2_TLBIRVAALE1IS_SHIFT 37
#define skb_list_walk_safe(first,skb,next_skb) for ((skb) = (first), (next_skb) = (skb) ? (skb)->next : NULL; (skb); (skb) = (next_skb), (next_skb) = (skb) ? (skb)->next : NULL)
#define local_irq_disable() do { bool was_disabled = raw_irqs_disabled(); raw_local_irq_disable(); if (!was_disabled) trace_hardirqs_off(); } while (0)
#define IS_RDONLY(inode) sb_rdonly((inode)->i_sb)
#define kunit_test_init_section_suites(__suites...) __kunit_test_suites(CONCATENATE(__UNIQUE_ID(array), _probe), ##__suites)
#define CONFIG_CC_HAS_INT128 1
#define HCRX_EL2_PTTWI GENMASK(16, 16)
#define _Q_LOCKED_VAL (1U << _Q_LOCKED_OFFSET)
#define CONFIG_DST_CACHE 1
#define FAR_EL12_ADDR_MASK GENMASK(63, 0)
#define TYPEC_ANY_MODE 0x7
#define ID_AA64ZFR0_EL1_B16B16_WIDTH 4
#define __NR_geteuid 175
#define ESHUTDOWN 108
#define SYS_ID_MMFR5_EL1_CRm 3
#define SYS_ID_MMFR5_EL1_CRn 0
#define local64_sub_and_test(i,l) local_sub_and_test((i), (&(l)->a))
#define __stringify(x...) __stringify_1(x)
#define PSR_MODE_EL2h 0x00000009
#define RLIM_NLIMITS 16
#define SO_SNDTIMEO_NEW 67
#define PM_EVENT_REMOTE_RESUME (PM_EVENT_REMOTE | PM_EVENT_RESUME)
#define KUNIT_EXPECT_NULL_MSG(test,ptr,fmt,...) KUNIT_BINARY_PTR_ASSERTION(test, KUNIT_EXPECTATION, ptr, ==, NULL, fmt, ##__VA_ARGS__)
#define spin_trylock_irqsave(lock,flags) ({ raw_spin_trylock_irqsave(spinlock_check(lock), flags); })
#define __UAPI_DEF_IN6_ADDR 1
#define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC)
#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04)
#define HWCAP2_RNG (1 << 16)
#define ETH_P_DIAG 0x6005
#define SPMI_NAME_SIZE 32
#define ___GFP_RECLAIMABLE 0x10u
#define SYSCTL_ONE_THOUSAND ((void *)&sysctl_vals[7])
#define MDCR_EL2_E2TB_MASK (UL(0x3))
#define ID_AA64ISAR0_EL1_SM3_SIGNED false
#define p4d_page(p4d) (pud_page((pud_t){ p4d }))
#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
#define IORESOURCE_MEM_NONPOSTED (1<<7)
#define __VDSO_LIMITS_H 
#define PIRx_ELx_Perm7_WIDTH 4
#define PR_MTE_TCF_MASK (PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC)
#define QCI_ROOT_SQUASH (1 << 1)
#define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
#define POLLWRBAND 0x0200
#define PSR_MODE_EL3h 0x0000000d
#define CONFIG_HAVE_PREEMPT_DYNAMIC 1
#define PSR_MODE_EL3t 0x0000000c
#define LPA_SGMII 0x0001
#define F_SETOWN 8
#define PIRx_ELx_Perm0_MASK GENMASK(3, 0)
#define VM_SYNC 0x00800000
#define TCR_EL2_TBI (1 << 20)
#define __ro_after_init __section(".data..ro_after_init")
#define XA_MARK_MAX XA_MARK_2
#define XATTR_LIST_MAX 65536
#define _LINUX_RWSEM_H 
#define FT_FIFO 5
#define PMSFCR_EL1_FE GENMASK(0, 0)
#define dev_fmt(fmt) fmt
#define PMSFCR_EL1_FL GENMASK(2, 2)
#define TLBI_TTL_TG_64K 3
#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
#define PMSFCR_EL1_FT GENMASK(1, 1)
#define CONFIG_GENERIC_ARCH_TOPOLOGY 1
#define NR_CPUS CONFIG_NR_CPUS
#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
#define DCACHE_OP_HASH 0x00000001
#define RXH_IP_DST (1 << 5)
#define HDFGWTR_EL2_PMOVS_SHIFT 18
#define ADVERTISE_PAUSE_CAP 0x0400
#define NT_ARC_V2 0x600
#define ID_ISAR3_EL1_Saturate GENMASK(3, 0)
#define HCRX_EL2_TMEA_SHIFT 19
#define COMPAT_PSR_DIT_BIT 0x00200000
#define HZ_TO_USEC_MUL32 U64_C(0xFA000000)
#define MODULE_SOFTDEP(_softdep) MODULE_INFO(softdep, _softdep)
#define CONFIG_CONSOLE_LOGLEVEL_DEFAULT 7
#define ETH_P_8021Q 0x8100
#define CONFIG_RD_XZ 1
#define CONFIG_DMATEST 1
#define HDFGWTR_EL2_DBGBVRn_EL1_SHIFT 1
#define ESR_ELx_FSC_LEVEL (0x03)
#define xa_for_each(xa,index,entry) xa_for_each_start(xa, index, entry, 0)
#define SET_LATE_SYSTEM_SLEEP_PM_OPS(suspend_fn,resume_fn) 
#define MDIO_SPEED 4
#define ID_AA64MMFR1_EL1_SpecSEI_IMP UL(0b0001)
#define SCXTNUM_EL1_SoftwareContextNumber_MASK GENMASK(63, 0)
#define ID_AA64ISAR0_EL1_TLB_MASK GENMASK(59, 56)
#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
#define ID_MMFR1_EL1_L1UniSW_MASK GENMASK(15, 12)
#define LORID_EL1_UNKN (UL(0))
#define ENOMEDIUM 123
#define SI_TKILL -6
#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
#define HFGxTR_EL2_CONTEXTIDR_EL1_SHIFT 11
#define CLIDR_EL1_UNKN (UL(0))
#define DL_FLAG_RPM_ACTIVE BIT(3)
#define _LINUX_KALLSYMS_H 
#define _LINUX_SCHED_TOPOLOGY_H 
#define HDFGRTR_EL2_PMSELR_EL0 GENMASK(19, 19)
#define S8_C(x) x
#define GMID_EL1_BS_WIDTH 4
#define ETH_P_TEB 0x6558
#define ftrace_set_filter(ops,buf,len,reset) ({ -ENODEV; })
#define ESR_ELx_EC_SHIFT (26)
#define this_cpu_cpumask_var_ptr(x) this_cpu_ptr(x)
#define __NR_timer_getoverrun 109
#define ID_ISAR3_EL1_SynchPrim_SHIFT 12
#define SRCU_NOTIFIER_HEAD_STATIC(name) _SRCU_NOTIFIER_HEAD(name, static)
#define IPV6_ADD_MEMBERSHIP 20
#define __GFP_THISNODE ((__force gfp_t)___GFP_THISNODE)
#define __NR_mknodat 33
#define kunit_suite_for_each_test_case(suite,test_case) for (test_case = suite->test_cases; test_case->run_case; test_case++)
#define COMPAT_PTRACE_SETHBPREGS 30
#define IORESOURCE_DMA 0x00000800
#define CONFIG_ELF_CORE 1
#define PRINTK_INFO_SUBSYSTEM_LEN 16
#define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
#define PF_NETLINK AF_NETLINK
#define DECLARE_PER_CPU_ALIGNED(type,name) DECLARE_PER_CPU_SECTION(type, name, PER_CPU_ALIGNED_SECTION) ____cacheline_aligned
#define __this_cpu_generic_read_noirq(pcp) ({ typeof(pcp) ___ret; unsigned long ___flags; raw_local_irq_save(___flags); ___ret = raw_cpu_generic_read(pcp); raw_local_irq_restore(___flags); ___ret; })
#define is_non_negative(a) ((a) > 0 || (a) == 0)
#define __ASM_GENERIC_IRQ_H 
#define HDFGWTR_EL2_DBGWVRn_EL1_SHIFT 3
#define ELIBSCN 81
#define RADIX_TREE_MAP_SIZE (1UL << RADIX_TREE_MAP_SHIFT)
#define ID_AA64MMFR0_EL1_BIGENDEL0_NI UL(0b0000)
#define wfe() asm volatile("wfe" : : : "memory")
#define wfi() asm volatile("wfi" : : : "memory")
#define ID_AA64PFR0_EL1_AMU_WIDTH 4
#define swab16p __swab16p
#define CLONE_NEWIPC 0x08000000
#define swab16s __swab16s
#define ID_ISAR3_EL1_TrueNOP GENMASK(27, 24)
#define SRCU_NOTIFIER_HEAD(name) _SRCU_NOTIFIER_HEAD(name, )
#define __SVE_ZREGS_OFFSET 0
#define _UAPI_LINUX_AUXVEC_H 
#define IOPRIO_CLASS_SHIFT 13
#define MMF_VM_MERGE_ANY 30
#define IOCTL_MEI_CONNECT_CLIENT _IOWR('H' , 0x01, struct mei_connect_client_data)
#define compat_lr_und regs[22]
#define write_unlock(lock) _raw_write_unlock(lock)
#define PT_SUSPEND_SECCOMP (PTRACE_O_SUSPEND_SECCOMP << PT_OPT_FLAG_SHIFT)
#define ETHTOOL_GPFLAGS 0x00000027
#define key_init() do { } while(0)
#define ITIMER_REAL 0
#define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
#define DCACHE_NORCU 0x40000000
#define CPUCLOCK_SCHED 2
#define __HDFGRTR_EL2_MASK ~__HDFGRTR_EL2_nMASK
#define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
#define sig_kernel_stop(sig) siginmask(sig, SIG_KERNEL_STOP_MASK)
#define PM_EVENT_REMOTE 0x0200
#define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
#define RADIX_TREE(name,mask) struct radix_tree_root name = RADIX_TREE_INIT(name, mask)
#define ID_MMFR2_EL1_HvdTLB_NI UL(0b0000)
#define set_pte_safe(ptep,pte) ({ WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); set_pte(ptep, pte); })
#define ID_ISAR5_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32) | GENMASK_ULL(23, 20))
#define ID_ISAR5_EL1_RES1 (UL(0))
#define COMPAT_HWCAP_THUMB (1 << 2)
#define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
#define NT_PPC_TM_CVMX 0x10a
#define AH_V4_FLOW 0x09
#define ID_AA64MMFR1_EL1_HAFDBS_MASK GENMASK(3, 0)
#define ZONES_PGOFF (NODES_PGOFF - ZONES_WIDTH)
#define pm_generic_suspend NULL
#define ID_AA64ZFR0_EL1_B16B16_MASK GENMASK(27, 24)
#define SUPPORTED_10000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseT_Full)
#define PARITY_CRC16_PR0 2
#define ID_MMFR3_EL1_CMemSz_WIDTH 4
#define kmalloc_node_track_caller(size,flags,node) __kmalloc_node_track_caller(size, flags, node, _RET_IP_)
#define TTBRx_EL1_CnP_SHIFT 0
#define R_AARCH64_JUMP26 282
#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define PMSIDR_EL1_INTERVAL GENMASK(11, 8)
#define __SC_DELOUSE(t,v) ((__force t)(unsigned long)(v))
#define ID_AA64MMFR3_EL1_S2PIE GENMASK(15, 12)
#define PMSFCR_EL1_LD GENMASK(17, 17)
#define HDFGWTR_EL2_nBRBCTL_WIDTH 1
#define __UAPI_DEF_IF_IFREQ 1
#define REG_PIRE0_EL1 S3_0_C10_C2_2
#define ID_AA64MMFR0_EL1_TGRAN4_NI UL(0b1111)
#define HFGITR_EL2_CPPRCTX GENMASK(50, 50)
#define FIELD_PREP(_mask,_val) ({ __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); })
#define BUS_ADRALN 1
#define ID_AA64MMFR0_EL1_BIGENDEL0_IMP UL(0b0001)
#define EPROTO 71
#define SCTLR_EL1_ATA GENMASK(43, 43)
#define mm_zero_struct_page(pp) __mm_zero_struct_page(pp)
#define __NR_openat2 437
#define R_AARCH64_MOVW_UABS_G2_NC 268
#define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
#define pm_sleep_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM_SLEEP), (_ptr))
#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE)
#define ID_AA64MMFR1_EL1_PAN_SHIFT 20
#define local64_add(i,l) local_add((i),(&(l)->a))
#define ETH_P_LOOP 0x0060
#define pmd_write(pmd) pte_write(pmd_pte(pmd))
#define CLOCK_MONOTONIC_RAW 4
#define trace_recursion_test(bit) ((current)->trace_recursion & (1<<(bit)))
#define SYM_FUNC_START(name) SYM_START(name, SYM_L_GLOBAL, SYM_A_ALIGN) bti c ;
#define skb_checksum_init_zero_check(skb,proto,check,compute_pseudo) __skb_checksum_validate(skb, proto, false, true, check, compute_pseudo)
#define IPV6_PREFER_SRC_PUBTMP_DEFAULT 0x0100
#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
#define CONFIG_SERIAL_AMBA_PL011_CONSOLE 1
#define ID_ISAR5_EL1_SEVL_SIGNED false
#define CONFIG_NET_VENDOR_BROCADE 1
#define HFGxTR_EL2_LORID_EL1_MASK GENMASK(21, 21)
#define EPOLL_CTL_DEL 2
#define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT)
#define HFGxTR_EL2_ERXPFGF_EL1_SHIFT 46
#define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
#define PTRACE_EVENT_CLONE 3
#define HFGxTR_EL2_CLIDR_EL1_MASK GENMASK(10, 10)
#define CONFIG_COMMON_CLK_ZYNQMP 1
#define HFGxTR_EL2_CSSELR_EL1 GENMASK(13, 13)
#define _LINUX_KASAN_H 
#define __atomic_release_fence smp_mb__before_atomic
#define ID_ISAR3_EL1_TabBranch GENMASK(19, 16)
#define CONFIG_XZ_DEC_SPARC 1
#define MDIO_USXGMII_10HALF 0x0000
#define SO_PREFER_BUSY_POLL 69
#define CTR_EL0_L1Ip_VIPT UL(0b10)
#define CLOCK_EXT 1
#define elfhdr elf64_hdr
#define elf_check_arch(x) ((x)->e_machine == EM_AARCH64)
#define MII_MMD_DATA 0x0e
#define TCR_NFD0 (UL(1) << 53)
#define TCR_NFD1 (UL(1) << 54)
#define SUPPORTED_10baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Half)
#define __pa_nodebug(x) __virt_to_phys_nodebug((unsigned long)(x))
#define SYS_TRBSR_EL1_Op2 3
#define XQM_GRPQUOTA 1
#define __SVE_PREGS_SIZE(vq) (__SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - __SVE_PREGS_OFFSET(vq))
#define SCTLR_EL1_TME_SHIFT 53
#define CONFIG_ARCH_WANT_HUGE_PMD_SHARE 1
#define MDIO_PMA_LASI_STAT 0x9005
#define ID_AA64PFR1_EL1_SSBS_NI UL(0b0000)
#define LPA_100HALF 0x0080
#define ID_ISAR1_EL1_IfThen GENMASK(19, 16)
#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
#define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
#define ETHTOOL_GREGS 0x00000004
#define ID_AA64PFR0_EL1_SEL2_SHIFT 36
#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | ESR_ELx_SYS64_ISS_DIR_MASK)
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
#define iowrite64_rep iowrite64_rep
#define EOVERFLOW 75
#define S_IRUSR 00400
#define CONFIG_NET_VENDOR_SUN 1
#define ID_AA64MMFR1_EL1_HPDS_MASK GENMASK(15, 12)
#define HFGxTR_EL2_REVIDR_EL1_MASK GENMASK(28, 28)
#define __HFGWTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50))
#define CONFIG_HAVE_ARCH_KASAN 1
#define PIRx_ELx_Perm13_WIDTH 4
#define ID_AA64MMFR0_EL1_FGT_IMP UL(0b0001)
#define _THIS_IP_ ({ __label__ __here; __here: (unsigned long)&&__here; })
#define _ASM_GENERIC_BUG_H 
#define ptrauth_get_enabled_keys(tsk) (-EINVAL)
#define EX_TYPE_KACCESS_ERR_ZERO 3
#define ESR_ELx_SYS64_ISS_RT(esr) (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
#define bitmap_from_arr64(bitmap,buf,nbits) bitmap_copy_clear_tail((unsigned long *)(bitmap), (const unsigned long *)(buf), (nbits))
#define HFGxTR_EL2_nRCWMASK_EL1_SHIFT 56
#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
#define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX)
#define HDFGWTR_EL2_DBGBVRn_EL1 GENMASK(1, 1)
#define compat_need_64bit_alignment_fixup() false
#define ID_ISAR6_EL1_FHM GENMASK(11, 8)
#define TASK_KILLABLE (TASK_WAKEKILL | TASK_UNINTERRUPTIBLE)
#define I_REFERENCED (1 << 8)
#define ID_PFR0_EL1_State2_MASK GENMASK(11, 8)
#define ID_AA64MMFR1_EL1_TWED_SIGNED false
#define this_cpu_generic_read(pcp) ({ typeof(pcp) __ret; if (__native_word(pcp)) __ret = __this_cpu_generic_read_nopreempt(pcp); else __ret = __this_cpu_generic_read_noirq(pcp); __ret; })
#define __NR_utimensat 88
#define __be32_to_cpus(x) __swab32s((x))
#define ARM64_WORKAROUND_834220 65
#define NT_PPC_TM_CVSX 0x10b
#define HWCAP2_SME_B16B16 (1UL << 41)
#define ID_AA64MMFR2_EL1_CnP_IMP UL(0b0001)
#define ID_AA64ISAR0_EL1_RNDR_SIGNED false
#define _LINUX_BYTEORDER_GENERIC_H 
#define FS_IOC_SETFSLABEL _IOW(0x94, 50, char[FSLABEL_MAX])
#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
#define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
#define __cmpxchg_wrapper(sfx,ptr,o,n) ({ __typeof__(*(ptr)) __ret; __ret = (__typeof__(*(ptr))) __cmpxchg ##sfx((ptr), (unsigned long)(o), (unsigned long)(n), sizeof(*(ptr))); __ret; })
#define KUNIT_PARAM_DESC_SIZE 128
#define ID_AA64ISAR2_EL1_APA3_NI UL(0b0000)
#define ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
#define SKB_WITH_OVERHEAD(X) ((X) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
#define CONFIG_ARM64_USE_LSE_ATOMICS 1
#define HDFGWTR_EL2_TRCCNTVRn GENMASK(37, 37)
#define NT_GNU_PROPERTY_TYPE_0 5
#define HCRX_EL2_EnSDERR GENMASK(20, 20)
#define nodes_and(dst,src1,src2) __nodes_and(&(dst), &(src1), &(src2), MAX_NUMNODES)
#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
#define SVE_PT_SVE_FPCR_OFFSET(vq) (SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
#define ID_ISAR4_EL1_PSR_M_MASK GENMASK(27, 24)
#define NLA_ALIGN(len) (((len) + NLA_ALIGNTO - 1) & ~(NLA_ALIGNTO - 1))
#define CONFIG_ARCH_HAS_STRICT_MODULE_RWX 1
#define VM_STARTGAP_FLAGS (VM_GROWSDOWN | VM_SHADOW_STACK)
#define FDPUT_POS_UNLOCK 2
#define ID_AA64MMFR3_EL1_S2POE GENMASK(23, 20)
#define CLOCK_TAI 11
#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
#define AS_KGIDT(val) (kgid_t){ __vfsgid_val(val) }
#define ESR_ELx_EC_WFx (0x01)
#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
#define R_AARCH64_LDST32_ABS_LO12_NC 285
#define ESR_ELx_EC_CP14_LS (0x06)
#define TASK_FREEZABLE 0x00002000
#define _LINUX_POISON_H 
#define __flush_s2_tlb_range_op(op,start,pages,stride,tlb_level) __flush_tlb_range_op(op, start, pages, stride, 0, tlb_level, false)
#define ID_AA64MMFR1_EL1_ECBHB_MASK GENMASK(63, 60)
#define SEMUME SEMOPM
#define _DPRINTK_FLAGS_INCL_ANY (_DPRINTK_FLAGS_INCL_MODNAME | _DPRINTK_FLAGS_INCL_FUNCNAME | _DPRINTK_FLAGS_INCL_LINENO | _DPRINTK_FLAGS_INCL_TID | _DPRINTK_FLAGS_INCL_SOURCENAME)
#define HFGITR_EL2_TLBIRVALE1_WIDTH 1
#define MIDR_REVISION_MASK 0xf
#define IOCB_EVENTFD (1 << 16)
#define PSR_AA32_MODE_FIQ 0x00000011
#define HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT 12
#define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
#define ID_ISAR5_EL1_AES_NI UL(0b0000)
#define R_AARCH64_TSTBR14 279
#define SEQCNT_RAW_SPINLOCK_ZERO(name,lock) SEQCOUNT_LOCKNAME_ZERO(name, lock)
#define copy_from_user_page(vma,page,vaddr,dst,src,len) do { instrument_copy_from_user_before(dst, (void __user *)src, len); memcpy(dst, src, len); instrument_copy_from_user_after(dst, (void __user *)src, len, 0); } while (0)
#define NL_CFG_F_NONROOT_SEND (1 << 1)
#define HDFGRTR_EL2_DBGBVRn_EL1_MASK GENMASK(1, 1)
#define ID_ISAR1_EL1_Except_WIDTH 4
#define __printf(a,b) __attribute__((__format__(printf, a, b)))
#define PMSFCR_EL1_ST GENMASK(18, 18)
#define NETIF_F_GSO_FRAGLIST __NETIF_F(GSO_FRAGLIST)
#define _LINUX_WAIT_H 
#define SECTION_IS_ONLINE BIT(SECTION_IS_ONLINE_BIT)
#define ID_MMFR4_EL1_EVT_NO_TLBIS UL(0b0001)
#define HFGITR_EL2_TLBIASIDE1OS_SHIFT 20
#define PR_SET_MM_ARG_END 9
#define PR_FP_EXC_UND 0x040000
#define __irq_exit_raw() do { lockdep_hardirq_exit(); preempt_count_sub(HARDIRQ_OFFSET); } while (0)
#define flowi6_oif __fl_common.flowic_oif
#define ID_ISAR1_EL1_Immediate_IMP UL(0b0001)
#define ETHTOOL_NWAY_RST 0x00000009
#define SYS_ID_ISAR1_EL1_Op1 0
#define VM_DATA_DEFAULT_FLAGS (VM_DATA_FLAGS_TSK_EXEC | VM_MTE_ALLOWED)
#define __ASM_MTE_H 
#define in_softirq() (softirq_count())
#define __this_cpu_cmpxchg(pcp,oval,nval) ({ __this_cpu_preempt_check("cmpxchg"); raw_cpu_cmpxchg(pcp, oval, nval); })
#define timer_setup(timer,callback,flags) __init_timer((timer), (callback), (flags))
#define ETH_MODULE_SFF_8436_MAX_LEN 640
#define CONFIG_HAS_IOMEM 1
#define TCR2_EL2_PnCH_MASK GENMASK(0, 0)
#define module_param_hw(name,type,hwtype,perm) module_param_hw_named(name, name, type, hwtype, perm)
#define ID_AA64AFR0_EL1_IMPDEF2_MASK GENMASK(11, 8)
#define TPACKET_HDRLEN (TPACKET_ALIGN(sizeof(struct tpacket_hdr)) + sizeof(struct sockaddr_ll))
#define ID_AA64DFR0_EL1_DebugVer_SIGNED false
#define CT_DYNTICKS_MASK (~CT_STATE_MASK)
#define DECLARE_TASKLET_DISABLED_OLD(name,_func) struct tasklet_struct name = { .count = ATOMIC_INIT(1), .func = _func, }
#define ID_PFR2_EL1_RAS_frac_WIDTH 4
#define REG_CPACR_EL1 S3_0_C1_C0_2
#define MDIO_EEE_100GR_FW 0x1000
#define DQUOT_QUOTA_SYS_FILE (1 << DQUOT_STATE_LAST)
#define HDFGRTR_EL2_DBGBCRn_EL1_SHIFT 0
#define CONFIG_GPIO_ZYNQMP_MODEPIN 1
#define __this_cpu_dec(pcp) __this_cpu_sub(pcp, 1)
#define COMPAT_HWCAP_ASIMDDP (1 << 24)
#define SG_PAGE_LINK_MASK (SG_CHAIN | SG_END)
#define REG_LORSA_EL1 S3_0_C10_C4_0
#define ID_AA64ISAR1_EL1_APA_PAuth2 UL(0b0011)
#define SECCOMP_RET_ERRNO 0x00050000U
#define ETHTOOL_SGRO 0x0000002c
#define SYS_SVCR_CRm 2
#define SYS_SVCR_CRn 4
#define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT)
#define VTCR_EL2_T0SZ(x) TCR_T0SZ(x)
#define __wait_var_event(var,condition) ___wait_var_event(var, condition, TASK_UNINTERRUPTIBLE, 0, 0, schedule())
#define SCTLR_EL1_TCF0_SHIFT 38
#define ETH_P_DDCMP 0x0006
#define __ASM_LINKAGE_H 
#define __GENMASK_ULL(h,l) (((~ULL(0)) - (ULL(1) << (l)) + 1) & (~ULL(0) >> (BITS_PER_LONG_LONG - 1 - (h))))
#define INT_MAX ((int)(~0U >> 1))
#define CONFIG_ARCH_MMAP_RND_BITS_MAX 24
#define likely(x) __builtin_expect(!!(x), 1)
#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
#define ETH_P_TSN 0x22F0
#define ULLONG_MAX (~0ULL)
#define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
#define MVFR0_EL1_FPRound_SIGNED false
#define ARM64_MTE 53
#define MVFR1_EL1_SIMDInt GENMASK(15, 12)
#define _PAGE_END(va) (-(UL(1) << ((va) - 1)))
#define x86cpu_device_id x86_cpu_id
#define IDA_CHUNK_SIZE 128
#define SYS_TRBTRG_EL1_Op0 3
#define ID_AA64SMFR0_EL1_I16I64 GENMASK(55, 52)
#define SYS_TRBTRG_EL1_Op2 6
#define nodes_complement(dst,src) __nodes_complement(&(dst), &(src), MAX_NUMNODES)
#define LORC_EL1_DS_WIDTH 8
#define __ASM_IRQFLAGS_H 
#define CONFIG_SYSCTL_EXCEPTION_TRACE 1
#define this_cpu_dec_return(pcp) this_cpu_add_return(pcp, -1)
#define F_NOTIFY (F_LINUX_SPECIFIC_BASE+2)
#define high_wmark_pages(z) (z->_watermark[WMARK_HIGH] + z->watermark_boost)
#define IOCB_NOIO (1 << 20)
#define KERNEL_HWCAP_ASIMD __khwcap_feature(ASIMD)
#define CLIDR_EL1_Ctype2_WIDTH 3
#define HDFGRTR_EL2_DBGWCRn_EL1_SHIFT 2
#define ID_MMFR0_EL1_PMSA_PMSAv7 UL(0b0011)
#define IS_SETLKW(cmd) (IS_SETLKW32(cmd) || IS_SETLKW64(cmd))
#define CONFIG_INPUT_EVDEV 1
#define HCRX_EL2_VINMI_MASK GENMASK(7, 7)
#define CONFIG_REGMAP_I2C 1
#define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
#define DEFINE_SPINLOCK(x) spinlock_t x = __SPIN_LOCK_UNLOCKED(x)
#define CPTR_EL2_TFP_SHIFT 10
#define PMBSR_EL1_EC_MASK GENMASK(31, 26)
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
#define TCR2_EL2_DisCH0_MASK GENMASK(14, 14)
#define SCTLR_EL1_BT0_SHIFT 35
#define TASK_STATE_MAX 0x00010000
#define this_cpu_inc_return(pcp) this_cpu_add_return(pcp, 1)
#define ptep_clear_flush_notify ptep_clear_flush
#define MDIO_PCS_1000BT1_STAT_LINK 0x0004
#define raw_cpu_xchg_4(pcp,nval) raw_cpu_generic_xchg(pcp, nval)
#define _ASM_GENERIC_BITOPS_BUILTIN___FLS_H_ 
#define ID_AA64ISAR2_EL1_GPA3 GENMASK(11, 8)
#define ID_AA64ISAR2_EL1_WFxT_MASK GENMASK(3, 0)
#define ESR_ELx_FSC_SECC_TTW2 (0x1e)
#define ESR_ELx_FSC_SECC_TTW3 (0x1f)
#define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT
#define xa_lock_nested(xa,subclass) spin_lock_nested(&(xa)->xa_lock, subclass)
#define __untagged_addr(addr) ((__force __typeof__(addr))sign_extend64((__force u64)(addr), 55))
#define SCTLR_EL1_EPAN_WIDTH 1
#define force_irqthreads() (static_branch_unlikely(&force_irqthreads_key))
#define __SRCU_DEP_MAP_INIT(srcu_name) .dep_map = { .name = #srcu_name },
#define SEMUSZ 20
#define _LINUX_PERCPU_REFCOUNT_H 
#define LINUX_MM_DEBUG_H 1
#define MMF_DUMPABLE_BITS 2
#define MDIO_B10L_PMA_CTRL 2294
#define SA_NOCLDWAIT 0x00000002
#define FAR_EL2_ADDR_SHIFT 0
#define ID_ISAR0_EL1_CmpBranch_MASK GENMASK(15, 12)
#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
#define seqcount_init(s) do { static struct lock_class_key __key; __seqcount_init((s), #s, &__key); } while (0)
#define __LINUX_GUARDS_H 
#define COMPAT_HWCAP_ASIMDHP (1 << 23)
#define BLKZEROOUT _IO(0x12,127)
#define SCTLR_EL1_ITD_SHIFT 7
#define CONFIG_GENERIC_BUG 1
#define ___GFP_THISNODE 0x200000u
#define va_copy(d,s) __builtin_va_copy(d, s)
#define ID_PFR0_EL1_DIT_NI UL(0b0000)
#define MVFR1_EL1_FPFtZ_IMP UL(0b0001)
#define MSEC_TO_HZ_NUM 1
#define raw_cmpxchg64 arch_cmpxchg64
#define PTRACE_POKEUSR 6
#define for_each_bvec(bvl,bio_vec,iter,start) for (iter = (start); (iter).bi_size && ((bvl = bvec_iter_bvec((bio_vec), (iter))), 1); bvec_iter_advance_single((bio_vec), &(iter), (bvl).bv_len))
#define _LINUX_SCHED_JOBCTL_H 
#define PHY_MAX_ADDR 32
#define KUNIT_ARRAY_PARAM(name,array,get_desc) static const void *name ##_gen_params(const void *prev, char *desc) { typeof((array)[0]) *__next = prev ? ((typeof(__next)) prev) + 1 : (array); if (__next - (array) < ARRAY_SIZE((array))) { void (*__get_desc)(typeof(__next), char *) = get_desc; if (__get_desc) __get_desc(__next, desc); return __next; } return NULL; }
#define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED)
#define FS_DQ_RTBHARD (1<<5)
#define U32_C(x) x ## U
#define NETLINK_RDMA 20
#define pgd_leaf(x) 0
#define MDIO_USXGMII_1000HALF 0x0400
#define SCTLR_EL1_NMI_MASK GENMASK(61, 61)
#define ID_DFR0_EL1_TraceFilt_MASK GENMASK(31, 28)
#define ID_ISAR0_EL1_BitField_NI UL(0b0000)
#define ptrauth_thread_switch_user(tsk) 
#define PREEMPT_OFFSET (1UL << PREEMPT_SHIFT)
#define QIF_BTIME (1 << QIF_BTIME_B)
#define KERN_CRIT KERN_SOH "2"
#define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x))
#define SYS_SMIDR_EL1_Op0 3
#define DECLARE_PER_CPU(type,name) DECLARE_PER_CPU_SECTION(type, name, "")
#define SYS_SMIDR_EL1_Op2 6
#define ACL_NOT_CACHED ((void *)(-1))
#define KCSAN_ACCESS_ASSERT (1 << 3)
#define ID_PFR0_EL1_CSV2_IMP UL(0b0001)
#define pfn_to_page __pfn_to_page
#define ID_AA64MMFR2_EL1_TTL_NI UL(0b0000)
#define HFGxTR_EL2_nGCS_EL0_MASK GENMASK(52, 52)
#define trace_recursion_set_depth(depth) do { current->trace_recursion &= ~(3 << TRACE_GRAPH_DEPTH_START_BIT); current->trace_recursion |= ((depth) & 3) << TRACE_GRAPH_DEPTH_START_BIT; } while (0)
#define DACR32_EL2_UNKN (UL(0))
#define dev_crit_ratelimited(dev,fmt,...) dev_level_ratelimited(dev_crit, dev, fmt, ##__VA_ARGS__)
#define PR_SCHED_CORE 62
#define NT_ARM_VFP 0x400
#define HFGITR_EL2_TLBIVALE1OS_SHIFT 22
#define ___GFP_RETRY_MAYFAIL 0x4000u
#define unsafe_get_compat_sigset(set,compat,label) do { const compat_sigset_t __user *__c = compat; sigset_t *__s = set; unsafe_copy_from_user(__s, __c, sizeof(*__c), label); } while (0)
#define ID_AA64MMFR3_EL1_S1PIE_WIDTH 4
#define MAX_LINKS 32
#define APPLE_CPU_PART_M1_ICESTORM 0x022
#define LEDS_BOOST_FIXED 2
#define SYS_TRBPTR_EL1_Op0 3
#define SYS_TRBPTR_EL1_Op1 0
#define SYS_TRBPTR_EL1_Op2 1
#define CONFIG_NET_VENDOR_ASIX 1
#define PSR_F_BIT 0x00000040
#define SCM_MAX_FD 253
#define E2BIG 7
#define LED_COLOR_ID_WHITE 0
#define SIGRTMAX _NSIG
#define time_is_after_eq_jiffies64(a) time_before_eq64(get_jiffies_64(), a)
#define SO_SECURITY_AUTHENTICATION 22
#define TOTAL_FIX_BTMAPS (NR_FIX_BTMAPS * FIX_BTMAPS_SLOTS)
#define HFGITR_EL2_TLBIVMALLE1_WIDTH 1
#define HDFGRTR_EL2_PMSICR_EL1 GENMASK(29, 29)
#define REG_ZCR_EL2 S3_4_C1_C2_0
#define HDFGRTR_EL2_TRBIDR_EL1_WIDTH 1
#define MDIO_PMA_STAT2_10GBEW 0x0002
#define COMPAT_HWCAP2_AES (1 << 0)
#define HFGxTR_EL2_APIAKey_MASK GENMASK(7, 7)
#define nth_page(page,n) ((page) + (n))
#define SCHED_FLAG_KEEP_PARAMS 0x10
#define PR_GET_SPECULATION_CTRL 52
#define SSAM_MATCH_INSTANCE 0x2
#define CONFIG_NAMESPACES 1
#define PA_SVERSION_ANY_ID 0xffffffff
#define INT_MIN (-INT_MAX - 1)
#define ID_AA64ISAR1_EL1_LRCPC_LRCPC2 UL(0b0010)
#define kvfree_rcu_arg_2(ptr,rhf) do { typeof (ptr) ___p = (ptr); if (___p) { BUILD_BUG_ON(!__is_kvfree_rcu_offset(offsetof(typeof(*(ptr)), rhf))); kvfree_call_rcu(&((___p)->rhf), (void *) (___p)); } } while (0)
#define AT_RSEQ_ALIGN 28
#define HDFGWTR_EL2_PMSELR_EL0_WIDTH 1
#define SYS_ID_AA64PFR1_EL1_Op1 0
#define _ARCH_ARM64_TLBBATCH_H 
#define CONFIG_KCMP 1
#define PR_SET_FP_MODE 45
#define MM_MT_FLAGS (MT_FLAGS_ALLOC_RANGE | MT_FLAGS_LOCK_EXTERN | MT_FLAGS_USE_RCU)
#define list_for_each_entry_from_rcu(pos,head,member) for (; &(pos)->member != (head); pos = list_entry_rcu(pos->member.next, typeof(*(pos)), member))
#define __wait_event_killable_exclusive(wq,condition) ___wait_event(wq, condition, TASK_KILLABLE, 1, 0, schedule())
#define ID_PFR1_EL1_Sec_frac_NI UL(0b0000)
#define AF_RXRPC 33
#define EM_PERF_DOMAIN_SKIP_INEFFICIENCIES BIT(1)
#define DECLARE_TASKLET_DISABLED(name,_callback) struct tasklet_struct name = { .count = ATOMIC_INIT(1), .callback = _callback, .use_callback = true, }
#define ID_AA64PFR1_EL1_MPAM_frac_SIGNED false
#define ID_ISAR4_EL1_Barrier_MASK GENMASK(19, 16)
#define REG_PMSCR_EL1 S3_0_C9_C9_0
#define REG_PMSCR_EL2 S3_4_C9_C9_0
#define SOL_RAW 255
#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
#define CONFIG_BUFFER_HEAD 1
#define SCTLR_EL1_CMOW GENMASK(32, 32)
#define ID_MMFR1_EL1_L1Uni_WIDTH 4
#define HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT 23
#define ID_AA64DFR0_EL1_PMUVer_IMP UL(0b0001)
#define ID_AA64ISAR2_EL1_APA3_SHIFT 12
#define __atomic_op_release(op,args...) ({ __atomic_release_fence(); op ##_relaxed(args); })
#define write_seqcount_invalidate(s) do_write_seqcount_invalidate(seqprop_ptr(s))
#define SVE_SIG_ZREG_OFFSET(vq,n) (SVE_SIG_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
#define REG_FAR_EL1 S3_0_C6_C0_0
#define REG_FAR_EL2 S3_4_C6_C0_0
#define ID_DFR1_EL1_HPMN0_SHIFT 4
#define _STATIC_CALL_TYPES_H 
#define SOL_KCM 281
#define PTRACE_O_TRACEVFORKDONE (1 << PTRACE_EVENT_VFORK_DONE)
#define SCTLR_EL1_TCF_WIDTH 2
#define __read_seqcount_retry(s,start) do___read_seqcount_retry(seqprop_const_ptr(s), start)
#define MDIO_PMD_RXDET_1 0x0004
#define ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 85
#define ETHTOOL_COALESCE_PKT_RATE_LOW BIT(11)
#define __ASM_KASAN_H 
#define _LINUX_ATOMIC_H 
#define CONFIG_SPARSEMEM_VMEMMAP 1
#define __initcall(fn) device_initcall(fn)
#define REFCOUNT_MAX INT_MAX
#define __XA_STATE(array,index,shift,sibs) { .xa = array, .xa_index = index, .xa_shift = shift, .xa_sibs = sibs, .xa_offset = 0, .xa_pad = 0, .xa_node = XAS_RESTART, .xa_alloc = NULL, .xa_update = NULL, .xa_lru = NULL, }
#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL)
#define IFF_VOLATILE (IFF_LOOPBACK|IFF_POINTOPOINT|IFF_BROADCAST|IFF_ECHO| IFF_MASTER|IFF_SLAVE|IFF_RUNNING|IFF_LOWER_UP|IFF_DORMANT)
#define ID_ISAR0_EL1_Debug GENMASK(23, 20)
#define ID_AA64MMFR1_EL1_VMIDBits_8 UL(0b0000)
#define NETIF_F_FCOE_CRC __NETIF_F(FCOE_CRC)
#define KMEM_CACHE_USERCOPY(__struct,__flags,__field) kmem_cache_create_usercopy(#__struct, sizeof(struct __struct), __alignof__(struct __struct), (__flags), offsetof(struct __struct, __field), sizeof_field(struct __struct, __field), NULL)
#define MDIO_PMA_10T1L_CTRL_EEE_EN 0x0400
#define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
#define ENOTDIR 20
#define NETIF_F_RXHASH __NETIF_F(RXHASH)
#define ID_PFR2_EL1_CSV3_IMP UL(0b0001)
#define HFGITR_EL2_TLBIRVAE1IS_MASK GENMASK(34, 34)
#define CHECKSUM_NONE 0
#define SO_DEBUG 1
#define first_unset_node(mask) __first_unset_node(&(mask))
#define used_math() tsk_used_math(current)
#define PMSIDR_EL1_LDS_MASK GENMASK(4, 4)
#define list_last_entry(ptr,type,member) list_entry((ptr)->prev, type, member)
#define TIMER_ABSTIME 0x01
#define __io_ar(v) ({ unsigned long tmp; dma_rmb(); asm volatile("eor	%0, %1, %1\n" "cbnz	%0, ." : "=r" (tmp) : "r" ((unsigned long)(v)) : "memory"); })
#define ID_AA64MMFR3_EL1_MEC_SHIFT 28
#define NT_PPC_TM_SPR 0x10c
#define FIXADDR_SIZE (__end_of_permanent_fixed_addresses << PAGE_SHIFT)
#define MT_FLAGS_HEIGHT_MASK 0x7C
#define TCR2_EL1x_POE_MASK GENMASK(3, 3)
#define ESERVERFAULT 526
#define _LINUX_SCHED_PRIO_H 
#define HDFGRTR_EL2_TRCSEQSTR GENMASK(45, 45)
#define AF_SMC 43
#define AF_NETBEUI 13
#define DACR32_EL2_D14_MASK GENMASK(29, 28)
#define ID_AA64MMFR2_EL1_NV_IMP UL(0b0001)
#define MDIO_PMA_CTRL2_10GBT 0x0009
#define ECONNRESET 104
#define I_SYNC_QUEUED (1 << 17)
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
#define non_block_end() do { } while (0)
#define ID_ISAR6_EL1_DP_IMP UL(0b0001)
#define CLONE_VFORK 0x00004000
#define SCTLR_EL1_ATA_MASK GENMASK(43, 43)
#define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
#define ___constant_swab32(x) ((__u32)( (((__u32)(x) & (__u32)0x000000ffUL) << 24) | (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | (((__u32)(x) & (__u32)0xff000000UL) >> 24)))
#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
#define CONFIG_DECOMPRESS_LZ4 1
#define do_each_pid_task(pid,type,task) do { if ((pid) != NULL) hlist_for_each_entry_rcu((task), &(pid)->tasks[type], pid_links[type]) {
#define ID_AA64AFR0_EL1_IMPDEF1_SHIFT 4
#define ID_MMFR0_EL1_VMSA_NI UL(0b0000)
#define do_each_pid_thread(pid,type,task) do_each_pid_task(pid, type, task) { struct task_struct *tg___ = task; for_each_thread(tg___, task) {
#define param_check_bool_enable_only param_check_bool
#define COMPAT_SYSCALL_DEFINE5(name,...) COMPAT_SYSCALL_DEFINEx(5, _ ##name, __VA_ARGS__)
#define ID_ISAR3_EL1_T32EE_IMP UL(0b0001)
#define CONFIG_DECOMPRESS_LZO 1
#define HDFGRTR_EL2_PMINTEN_MASK GENMASK(17, 17)
#define SYSCTL_TWO_HUNDRED ((void *)&sysctl_vals[6])
#define PF__HOLE__00800000 0x00800000
#define SYS_TCR2_EL2_Op0 3
#define SYS_TCR2_EL2_Op1 4
#define SYS_TCR2_EL2_Op2 3
#define NTP_PHASE_LIMIT ((MAXPHASE / NSEC_PER_USEC) << 5)
#define SYS_PAR_EL1_F BIT(0)
#define _LINUX_CONTEXT_TRACKING_IRQ_H 
#define devm_irq_alloc_desc_from(dev,from,node) devm_irq_alloc_descs(dev, -1, from, 1, node)
#define write_unlock_irqrestore(lock,flags) do { typecheck(unsigned long, flags); _raw_write_unlock_irqrestore(lock, flags); } while (0)
#define CTR_EL0_DIC_MASK GENMASK(29, 29)
#define SYS_CLIDR_EL1_CRm 0
#define SYS_CLIDR_EL1_CRn 0
#define _ASM_GENERIC_LOCAL_H 
#define ARM64_CPUCAP_LOCAL_CPU_ERRATUM (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
#define ID_MMFR3_EL1_Supersec_WIDTH 4
#define ID_AA64PFR0_EL1_CSV3_SIGNED false
#define ID_PFR0_EL1_UNKN (UL(0))
#define CSSELR_EL1_UNKN (UL(0))
#define pmdp_huge_clear_flush_notify pmdp_huge_clear_flush
#define HWCAP_JSCVT (1 << 13)
#define MTE_PAGE_TAG_STORAGE (MTE_GRANULES_PER_PAGE * MTE_TAG_SIZE / 8)
#define QIF_USAGE (QIF_SPACE | QIF_INODES)
#define ID_MMFR1_EL1_L1HvdVA_WIDTH 4
#define ___SPIN_LOCK_INITIALIZER(lockname) { .raw_lock = __ARCH_SPIN_LOCK_UNLOCKED, SPIN_DEBUG_INIT(lockname) SPIN_DEP_MAP_INIT(lockname) }
#define PMBLIMITR_EL1_LIMIT GENMASK(63, 12)
#define CHRDEV_MAJOR_DYN_EXT_START 511
#define ID_AA64MMFR2_EL1_AT GENMASK(35, 32)
#define __ASM_SPINLOCK_TYPES_H 
#define EI_MAG1 1
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define KUNIT_EXPECT_GE(test,left,right) KUNIT_EXPECT_GE_MSG(test, left, right, NULL)
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
#define KERNEL_HWCAP_CPUID __khwcap_feature(CPUID)
#define mutex_lock(lock) mutex_lock_nested(lock, 0)
#define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
#define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
#define FT_REG_FILE 1
#define ID_MMFR5_EL1_UNKN (UL(0))
#define ID_AA64PFR1_EL1_THE GENMASK(51, 48)
#define INPUT_DEVICE_ID_KEY_MIN_INTERESTING 0x71
#define __ASM_CHECKSUM_H 
#define SUID_DUMP_ROOT 2
#define CTL1000_PREFER_MASTER 0x0400
#define raw_cpu_add_return_8(pcp,val) raw_cpu_generic_add_return(pcp, val)
#define DMA_ZONE(xx) xx ##_DMA,
#define QUOTA_NL_NOWARN 0
#define KERNEL_HWCAP_LSE128 __khwcap2_feature(LSE128)
#define raw_spin_is_contended(lock) arch_spin_is_contended(&(lock)->raw_lock)
#define NETLINK_CREDS(skb) (&NETLINK_CB((skb)).creds)
#define __diag_GCC_warn warning
#define _outw _outw
#define ID_DFR0_EL1_TraceFilt_IMP UL(0b0001)
#define KERN_ALERT KERN_SOH "1"
#define MDIO_AN_C73_0_RF BIT(13)
#define NETIF_F_GRO_FRAGLIST __NETIF_F(GRO_FRAGLIST)
#define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
#define SYS_OSDTRRX_EL1_CRm 0
#define ID_ISAR4_EL1_SynchPrim_frac_SHIFT 20
#define VA_BITS_MIN (VA_BITS)
#define for_each_clear_bitrange(b,e,addr,size) for ((b) = 0; (b) = find_next_zero_bit((addr), (size), (b)), (e) = find_next_bit((addr), (size), (b) + 1), (b) < (size); (b) = (e) + 1)
#define nodes_subset(src1,src2) __nodes_subset(&(src1), &(src2), MAX_NUMNODES)
#define INIT_HLIST_NULLS_HEAD(ptr,nulls) ((ptr)->first = (struct hlist_nulls_node *) NULLS_MARKER(nulls))
#define HDFGRTR_EL2_PMSFCR_EL1_SHIFT 28
#define CONFIG_ARCH_INLINE_READ_UNLOCK_BH 1
#define XA_LIMIT(_min,_max) (struct xa_limit) { .min = _min, .max = _max }
#define em_is_artificial(em) ((em)->flags & EM_PERF_DOMAIN_ARTIFICIAL)
#define TRBIDR_EL1_Align_MASK GENMASK(3, 0)
#define arch_ptrace_stop() do { } while (0)
#define rcu_dereference_protected(p,c) __rcu_dereference_protected((p), __UNIQUE_ID(rcu), (c), __rcu)
#define ID_AA64ISAR1_EL1_SB_WIDTH 4
#define HWCAP2_DGH (1 << 15)
#define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
#define SCTLR_EL1_TME0 GENMASK(52, 52)
#define PMSEVFR_EL1_RES0_V1P1 (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
#define SYS_DCZID_EL0_CRn 0
#define __NR_mkdirat 34
#define PMSEVFR_EL1_RES0_V1P2 (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
#define kmalloc_index(s) __kmalloc_index(s, true)
#define CMSG_SPACE(len) (sizeof(struct cmsghdr) + CMSG_ALIGN(len))
#define psb_csync() asm volatile("hint #17" : : : "memory")
#define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc
#define CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU 1
#define __initcall_section(__sec,__iid) #__sec ".init"
#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
#define CLONE_SYSVSEM 0x00040000
#define HCRX_EL2_SMPME GENMASK(5, 5)
#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
#define RWSEM_UNLOCKED_VALUE 0L
#define ICC_NMIAR1_EL1_INTID GENMASK(23, 0)
#define PF_CAN AF_CAN
#define ID_ISAR4_EL1_SMC GENMASK(15, 12)
#define __LINUX_STACKTRACE_H 
#define _LINUX_MII_TIMESTAMPER_H 
#define SRCU_NMI_UNKNOWN 0x0
#define CTR_EL0_IminLine GENMASK(3, 0)
#define SHM_HUGE_32MB HUGETLB_FLAG_ENCODE_32MB
#define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
#define ETH_P_IBOE 0x8915
#define DN_ACCESS 0x00000001
#define IPV6_RECVFRAGSIZE 77
#define __NR_seccomp 277
#define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE)
#define HFGITR_EL2_DVPRCTX_SHIFT 49
#define CONFIG_INET_TCP_DIAG 1
#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
#define CLOCKS_MASK (CLOCK_REALTIME | CLOCK_MONOTONIC)
#define WMI_MODULE_PREFIX "wmi:"
#define CLIDR_EL1_Ttypen_MASK GENMASK(46, 33)
#define ADVERTISED_100baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Full)
#define ICH_HCR_NPIE (1 << 3)
#define HDFGWTR_EL2_OSDLR_EL1_MASK GENMASK(11, 11)
#define MVFR0_EL1_FPSqrt_NI UL(0b0000)
#define FLOW_DIS_FIRST_FRAG BIT(1)
#define skb_rbtree_walk_from(skb) for (; skb != NULL; skb = skb_rb_next(skb))
#define __ASM_FP_H 
#define SVE_SIG_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
#define PROT_DEFAULT (_PROT_DEFAULT | PTE_MAYBE_NG)
#define DL_FLAG_CYCLE BIT(9)
#define SIOCSRARP 0x8962
#define CONFIG_CC_HAS_SANCOV_TRACE_PC 1
#define TCR_TBID1 (UL(1) << 52)
#define MMF_DISABLE_THP_MASK (1 << MMF_DISABLE_THP)
#define conditional_used_math(condition) conditional_stopped_child_used_math(condition, current)
#define __INCLUDE_LINUX_RCU_SEGCBLIST_H 
#define KUNIT_EXPECT_LE(test,left,right) KUNIT_EXPECT_LE_MSG(test, left, right, NULL)
#define POLL_HUP 6
#define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT
#define ETH_ALEN 6
#define pte_accessible(mm,pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
#define HFGITR_EL2_nBRBINJ_MASK GENMASK(55, 55)
#define __page_aligned_bss __section(".bss..page_aligned") __aligned(PAGE_SIZE)
#define LOREA_EL1_EA_47_16_WIDTH 32
#define CAP_NET_BIND_SERVICE 10
#define SIMPLE_TRANSACTION_LIMIT (PAGE_SIZE - sizeof(struct simple_transaction_argresp))
#define __noinitretpoline 
#define CONFIG_ARCH_HAS_SET_MEMORY 1
#define SCXTNUM_EL1_SoftwareContextNumber_SHIFT 0
#define PF_IDLE 0x00000002
#define ICH_VMCR_CBPR_SHIFT 4
#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
#define RLIMIT_NOFILE 7
#define _DEVICE_DRIVER_H_ 
#define NR_FTRACE_PLTS 1
#define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
#define TRBIDR_EL1_F_MASK GENMASK(5, 5)
#define ESR_ELx_FSC_ACCESS (0x08)
#define STATIC_CALL_TRAMP(name) __PASTE(STATIC_CALL_TRAMP_PREFIX, name)
#define ID_AA64MMFR2_EL1_AT_NI UL(0b0000)
#define CONFIG_MFD_SYSCON 1
#define ID_AA64ISAR1_EL1_GPI_WIDTH 4
#define SCTLR_EL1_DSSBS_WIDTH 1
#define __this_cpu_read(pcp) ({ __this_cpu_preempt_check("read"); raw_cpu_read(pcp); })
#define CLONE_PTRACE 0x00002000
#define REG_DACR32_EL2 S3_4_C3_C0_0
#define ID_AA64SMFR0_EL1_F16F32_MASK GENMASK(35, 35)
#define _LINUX_KOBJECT_NS_H 
#define ID_AA64PFR0_EL1_EL3_IMP UL(0b0001)
#define HFGITR_EL2_TLBIRVAE1OS_SHIFT 24
#define SYS_MPAMVPM0_EL2 __SYS__MPAMVPMx_EL2(0)
#define DECLARE_PER_CPU_FIRST(type,name) DECLARE_PER_CPU_SECTION(type, name, PER_CPU_FIRST_SECTION)
#define EM_NONE 0
#define ETH_P_DSA_A5PSW 0xE001
#define DACR32_EL2_D7_WIDTH 2
#define RELOC_HIDE(ptr,off) ({ unsigned long __ptr; __asm__ ("" : "=r"(__ptr) : "0"(ptr)); (typeof(ptr)) (__ptr + (off)); })
#define KUNIT_EXPECT_NE(test,left,right) KUNIT_EXPECT_NE_MSG(test, left, right, NULL)
#define INPUT_DEVICE_ID_MATCH_KEYBIT 0x0020
#define __constant_le16_to_cpu(x) ((__force __u16)(__le16)(x))
#define __LINUX_UMH_H__ 
#define HFGxTR_EL2_nRCWMASK_EL1_MASK GENMASK(56, 56)
#define ID_MMFR5_EL1_nTLBPA_SHIFT 4
#define __NR_setfsuid 151
#define ID_AA64MMFR3_EL1_SCTLRX_WIDTH 4
#define MDIO_PMA_NG_EXTABLE_5GBT 0x0002
#define SMPRIMAP_EL2_P5_SHIFT 20
#define ID_AA64ISAR2_EL1_CLRBHB_MASK GENMASK(31, 28)
#define first_online_node 0
#define RXH_L3_PROTO (1 << 3)
#define DCACHE_DISCONNECTED 0x00000020
#define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
#define HDFGWTR_EL2_OSECCR_EL1_MASK GENMASK(10, 10)
#define ATOMIC_LONG_INIT(i) ATOMIC64_INIT(i)
#define MVFR1_EL1_SIMDFMAC_NI UL(0b0000)
#define _LINUX_SEM_H 
#define PIRx_ELx_Perm7_SHIFT 28
#define _LINUX_IOCTL_H 
#define BUILD_BUG_ON_INVALID(e) ((void)(sizeof((__force long)(e))))
#define IF_PROTO_RAW 0x200C
#define __trace_printk_check_format(fmt,args...) do { if (0) ____trace_printk_check_format(fmt, ##args); } while (0)
#define HARDIRQ_OFFSET (1UL << HARDIRQ_SHIFT)
#define __NR_gettimeofday 169
#define BLKTRACESTART _IO(0x12,116)
#define HWCAP2_SVE2P1 (1UL << 36)
#define ID_AA64MMFR2_EL1_EVT_SHIFT 56
#define _LINUX_EXPORT_H 
#define Q_GETQUOTA 0x800007
#define ADVERTISED_56000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseLR4_Full)
#define CCSIDR2_EL1_RES0 (UL(0) | GENMASK_ULL(63, 24))
#define CCSIDR2_EL1_RES1 (UL(0))
#define __virt_to_phys(x) __virt_to_phys_nodebug(x)
#define TP_STATUS_WRONG_FORMAT (1 << 2)
#define wait_event_freezable(wq_head,condition) ({ int __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_event_freezable(wq_head, condition); __ret; })
#define ID_AA64SMFR0_EL1_BI32I32_WIDTH 1
#define FAR_EL2_UNKN (UL(0))
#define VM_ARM64_BTI VM_ARCH_1
#define HDFGRTR_EL2_PMMIR_EL1 GENMASK(22, 22)
#define TPIDR2_MAGIC 0x54504902
#define HDFGWTR_EL2_OSECCR_EL1_SHIFT 10
#define FS_IOC_SETFLAGS _IOW('f', 2, long)
#define ID_MMFR4_EL1_CCIDX_MASK GENMASK(27, 24)
#define local_inc_and_test(l) atomic_long_inc_and_test(&(l)->a)
#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
#define ETH_MODULE_SFF_8079_LEN 256
#define ICC_NMIAR1_EL1_INTID_SHIFT 0
#define COUNT_ARGS(X...) __COUNT_ARGS(, ##X, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
#define NETLINK_DROP_MEMBERSHIP 2
#define ID_AA64MMFR3_EL1_ANERR_NI UL(0b0000)
#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1)))
#define _ULL(x) (_AC(x, ULL))
#define HFGITR_EL2_CPPRCTX_SHIFT 50
#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
#define __NR_io_cancel 3
#define ID_AA64ISAR1_EL1_LS64_LS64_ACCDATA UL(0b0011)
#define PSR_V_BIT 0x10000000
#define SB_KERNMOUNT BIT(22)
#define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
#define read_lock_bh(lock) _raw_read_lock_bh(lock)
#define ID_DFR1_EL1_MTPMU GENMASK(3, 0)
#define CLIDR_EL1_Ctype3_MASK GENMASK(8, 6)
#define DO_ONCE_LITE_IF(condition,func,...) ({ bool __ret_do_once = !!(condition); if (__ONCE_LITE_IF(__ret_do_once)) func(__VA_ARGS__); unlikely(__ret_do_once); })
#define TRBLIMITR_EL1_XE_MASK GENMASK(6, 6)
#define INIT_PASID 0
#define NOMMU_MAP_EXEC VM_MAYEXEC
#define KERNFS_USER_XATTR_SIZE_LIMIT (128 << 10)
#define wake_up_interruptible_poll(x,m) __wake_up(x, TASK_INTERRUPTIBLE, 1, poll_to_key(m))
#define ID_AA64ISAR1_EL1_API_MASK GENMASK(11, 8)
#define SKB_MONO_DELIVERY_TIME_MASK (1 << 0)
#define SYS_ID_MMFR2_EL1_Op0 3
#define SYS_ID_MMFR2_EL1_Op1 0
#define SYS_ID_MMFR2_EL1_Op2 6
#define WRITE 1
#define ID_PFR0_EL1_State0_IMP UL(0b0001)
#define CTR_EL0_DIC_WIDTH 1
#define _CLOCK_T 
#define lockdep_irq_work_exit(_flags) do { if (!((_flags) & IRQ_WORK_HARD_IRQ)) current->irq_config = 0; } while (0)
#define dereference_function_descriptor(p) ((void *)(p))
#define ETHTOOL_SPFLAGS 0x00000028
#define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
#define __ASM_GENERIC_PARAM_H 
#define SECTION_MARKED_PRESENT BIT(SECTION_MARKED_PRESENT_BIT)
#define __this_cpu_add(pcp,val) ({ __this_cpu_preempt_check("add"); raw_cpu_add(pcp, val); })
#define PT_EXITKILL (PTRACE_O_EXITKILL << PT_OPT_FLAG_SHIFT)
#define IRQF_TRIGGER_HIGH 0x00000004
#define ESR_ELx_SYS64_ISS_DIR_READ 0x1
#define _SYSFS_H_ 
#define SYS_ID_PFR2_EL1_Op0 3
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
#define SYS_ID_PFR2_EL1_Op2 4
#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7)
#define hrtimers_cpu_dying NULL
#define NETIF_F_HW_HSR_FWD __NETIF_F(HW_HSR_FWD)
#define HZ_TO_NSEC_DEN 1
#define ID_MMFR1_EL1_L1TstCln_NI UL(0b0000)
#define HWCAP2_MOPS (1UL << 43)
#define nodes_clear(dst) __nodes_clear(&(dst), MAX_NUMNODES)
#define __define_initcall(fn,id) ___define_initcall(fn, id, .initcall ##id)
#define PCI_IO_SIZE SZ_16M
#define ICH_LR_PHYS_ID_SHIFT 32
#define ID_MMFR0_EL1_FCSE_SIGNED false
#define ENCAP_TYPE_IPPROTO 1
#define INPUT_DEVICE_ID_MATCH_EVBIT 0x0010
#define __NR_timer_create 107
#define ID_AA64SMFR0_EL1_BI32I32_SIGNED false
#define time_after(a,b) (typecheck(unsigned long, a) && typecheck(unsigned long, b) && ((long)((b) - (a)) < 0))
#define ID_MMFR4_EL1_CCIDX_NI UL(0b0000)
#define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001
#define MIDR_ARCHITECTURE_SHIFT 16
#define ID_AA64MMFR3_EL1_Spec_FPACC_SIGNED false
#define HCR_RW (UL(1) << HCR_RW_SHIFT)
#define ARM64_HAS_32BIT_EL1 4
#define AF_ALG 38
#define HUGETLB_FLAG_ENCODE_256MB (28U << HUGETLB_FLAG_ENCODE_SHIFT)
#define EM_ALPHA 0x9026
#define __HAVE_ARCH_MEMCHR 
#define flowi4_uid __fl_common.flowic_uid
#define ID_AA64MMFR2_EL1_NV GENMASK(27, 24)
#define ETHTOOL_FEC_OFF (1 << ETHTOOL_FEC_OFF_BIT)
#define UEVENT_BUFFER_SIZE 2048
#define ID_DFR0_EL1_PerfMon_SHIFT 24
#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
#define ICH_VTR_SEIS_SHIFT 22
#define kobj_to_dev(__kobj) container_of_const(__kobj, struct device, kobj)
#define PMSIDR_EL1_PBT GENMASK(24, 24)
#define ATTR_FORCE (1 << 9)
#define DEFINE_XARRAY_FLAGS(name,flags) struct xarray name = XARRAY_INIT(name, flags)
#define ID_ISAR2_EL1_LoadStore_ACQUIRE UL(0b0010)
#define CSSELR_EL1_InD GENMASK(0, 0)
#define CONFIG_DMADEVICES 1
#define ELF_PLAT_INIT(_r,load_addr) (_r)->regs[0] = 0
#define TTBRx_EL1_ASID_WIDTH 16
#define ADVERTISED_1000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Full)
#define ID_AA64MMFR3_EL1_TCRX_SHIFT 0
#define ID_AA64DFR0_EL1_BRBE_WIDTH 4
#define SLUB_RED_INACTIVE 0xbb
#define F_GETFD 1
#define __UAPI_DEF_ETHHDR 1
#define NSIGPOLL 6
#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
#define __UAPI_DEF_IN_CLASS 1
#define TCR2_EL2_DisCH1_SHIFT 15
#define pr_devel_ratelimited(fmt,...) no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
#define FLOW_DIS_IS_FRAGMENT BIT(0)
#define EXPANSION_LCWP 0x0002
#define rwsem_acquire(l,s,t,i) lock_acquire_exclusive(l, s, t, NULL, i)
#define HCRX_EL2_MCE2_SHIFT 10
#define TASK_FREEZABLE_UNSAFE (TASK_FREEZABLE | __TASK_FREEZABLE_UNSAFE)
#define ID_AA64ISAR0_EL1_ATOMIC_NI UL(0b0000)
#define __UAPI_DEF_SOCKADDR_IPX 1
#define _LINUX_SECCOMP_H 
#define SEMGET 2
#define KUNIT_EXPECT_NOT_NULL_MSG(test,ptr,fmt,...) KUNIT_BINARY_PTR_ASSERTION(test, KUNIT_EXPECTATION, ptr, !=, NULL, fmt, ##__VA_ARGS__)
#define HFGITR_EL2_DCCIVAC_SHIFT 10
#define ID_AA64ISAR1_EL1_LS64_NI UL(0b0000)
#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
#define ID_MMFR2_EL1_WFIStall_MASK GENMASK(27, 24)
#define ID_ISAR1_EL1_Immediate_SHIFT 20
#define PTRACE_MODE_REALCREDS 0x10
#define aligned_u64 __aligned_u64
#define TCR_EL2_PS_SHIFT 16
#define MM_CP_UFFD_WP_ALL (MM_CP_UFFD_WP | MM_CP_UFFD_WP_RESOLVE)
#define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
#define VTTBR_VMID_SHIFT (UL(48))
#define SI_ASYNCNL -60
#define SOCK_CLOEXEC O_CLOEXEC
#define SO_TIMESTAMPING_OLD 37
#define SCTLR_EL1_IESB GENMASK(21, 21)
#define raw_cpu_add_2(pcp,val) raw_cpu_generic_to_op(pcp, val, +=)
#define _LINUX_KLIST_H 
#define ID_AA64DFR0_EL1_HPMN0 GENMASK(63, 60)
#define __ALIGN_KERNEL_MASK(x,mask) (((x) + (mask)) & ~(mask))
#define PF_AX25 AF_AX25
#define ID_DFR0_EL1_MProfDbg_WIDTH 4
#define LLONG_MAX ((long long)(~0ULL >> 1))
#define KERNEL_HWCAP_RPRES __khwcap2_feature(RPRES)
#define ID_MMFR4_EL1_XNX_WIDTH 4
#define ptrauth_set_enabled_keys(tsk,keys,enabled) (-EINVAL)
#define ETH_P_FIP 0x8914
#define RR_TIMESLICE (100 * HZ / 1000)
#define MMF_DUMP_ANON_SHARED 3
#define CONFIG_SND_PROC_FS 1
#define ID_ISAR3_EL1_SVC_NI UL(0b0000)
#define __no_randomize_layout 
#define ID_ISAR6_EL1_I8MM GENMASK(27, 24)
#define PTRS_PER_P4D 1
#define interrupts_enabled(regs) (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
#define CLONED_MASK 1
#define ID_AA64MMFR3_EL1_S1PIE_MASK GENMASK(11, 8)
#define SYS_CPACR_EL1_Op0 3
#define SYS_CPACR_EL1_Op1 0
#define SYS_CPACR_EL1_Op2 2
#define PMBSR_EL1_MSS GENMASK(15, 0)
#define ETH_P_TR_802_2 0x0011
#define KERNEL_HWCAP_RPRFM __khwcap2_feature(RPRFM)
#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
#define FIELD_PREP_CONST(_mask,_val) ( BUILD_BUG_ON_ZERO((_mask) == 0) + BUILD_BUG_ON_ZERO(~((_mask) >> __bf_shf(_mask)) & (_val)) + __BF_CHECK_POW2((_mask) + (1ULL << __bf_shf(_mask))) + (((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask)) )
#define CLD_STOPPED 5
#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 89
#define __ASM_PGTABLE_TYPES_H 
#define FMODE_STREAM ((__force fmode_t)0x200000)
#define RLIMIT_RTPRIO 14
#define nodes_equal(src1,src2) __nodes_equal(&(src1), &(src2), MAX_NUMNODES)
#define for_each_process(p) for (p = &init_task ; (p = next_task(p)) != &init_task ; )
#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
#define NT_PPC_SPE 0x101
#define MOD_STATUS ADJ_STATUS
#define FOR_ALL_ZONES(xx) DMA_ZONE(xx) DMA32_ZONE(xx) xx ##_NORMAL, HIGHMEM_ZONE(xx) xx ##_MOVABLE, DEVICE_ZONE(xx)
#define ID_AA64ZFR0_EL1_SM4 GENMASK(43, 40)
#define MDIO_PHY_ID_PRTAD 0x03e0
#define ID_AA64PFR1_EL1_MTE_NI UL(0b0000)
#define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
#define guard(_name) CLASS(_name, __UNIQUE_ID(guard))
#define PSR_MODE_THREAD_BIT (1 << 0)
#define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 0x0001
#define dev_alert_once(dev,fmt,...) dev_level_once(dev_alert, dev, fmt, ##__VA_ARGS__)
#define __GFP_MOVABLE ((__force gfp_t)___GFP_MOVABLE)
#define DQ_FAKE_B 3
#define __HAVE_ARCH_MEMCMP 
#define HFGITR_EL2_DCCVAP_MASK GENMASK(8, 8)
#define __tlbi_user(op,arg) do { if (arm64_kernel_unmapped_at_el0()) __tlbi(op, (arg) | USER_ASID_FLAG); } while (0)
#define LORID_EL1_LR_WIDTH 8
#define MDIO_PMA_CTRL2_10GBLRM 0x0008
#define TCR2_EL1x_DisCH1_SHIFT 15
#define PMBSR_EL1_S_WIDTH 1
#define array3_size(a,b,c) size_mul(size_mul(a, b), c)
#define ID_AA64MMFR2_EL1_ST GENMASK(31, 28)
#define MDIO_PCS_STAT2_TXFLTABLE 0x2000
#define PG_dcache_clean PG_arch_1
#define SEGCBLIST_LOCKING BIT(2)
#define CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX 16
#define RCU_FANOUT 64
#define PMSIDR_EL1_UNKN (UL(0))
#define CONFIG_NET_VENDOR_REALTEK 1
#define S_IRGRP 00040
#define SO_SNDTIMEO_OLD 21
#define CONFIG_GENERIC_TIME_VSYSCALL 1
#define SHM_NORESERVE 010000
#define ESR_ELx_ERET_ISS_ERET 0x2
#define EPOLLOUT (__force __poll_t)0x00000004
#define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
#define HFGITR_EL2_TLBIVAAE1OS_MASK GENMASK(21, 21)
#define DT_VERNEED 0x6ffffffe
#define __EXPORT_SYMBOL_REF(sym) .balign 8 ASM_NL .quad sym
#define __ASM_GPR_NUM_H 
#define TCR_EL2_T0SZ_MASK 0x3f
#define PIDNS_ADDING (1U << 31)
#define SYS_FAR_EL12_Op0 3
#define SYS_FAR_EL12_Op2 0
#define SYS_PMSICR_EL1_Op0 3
#define SYS_PMSICR_EL1_Op2 2
#define PF_PACKET AF_PACKET
#define HCRX_EL2_EnAS0_MASK GENMASK(0, 0)
#define ID_AA64ISAR1_EL1_RES0 (UL(0))
#define ID_AA64ISAR1_EL1_RES1 (UL(0))
#define flowi4_oif __fl_common.flowic_oif
#define HFGITR_EL2_CFPRCTX GENMASK(48, 48)
#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
#define PSR_AA32_MODE_USR 0x00000010
#define MDCCINT_EL1_UNKN (UL(0))
#define JOBCTL_TRAP_FREEZE (1UL << JOBCTL_TRAP_FREEZE_BIT)
#define __NR_chdir 49
#define ID_MMFR3_EL1_CohWalk GENMASK(23, 20)
#define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
#define STATIC_KEY_INIT_TRUE { .enabled = ATOMIC_INIT(1) }
#define arch_spin_lock(l) queued_spin_lock(l)
#define HDFGWTR_EL2_PMSWINC_EL0_SHIFT 20
#define NL_CFG_F_NONROOT_RECV (1 << 0)
#define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
#define IS_SETLK32(cmd) (0)
#define ID_AA64MMFR0_EL1_PARANGE_32 UL(0b0000)
#define HDFGWTR_EL2_PMCCFILTR_EL0 GENMASK(14, 14)
#define ICC_NMIAR1_EL1_RES1 (UL(0))
#define NETIF_F_HW_TLS_RECORD __NETIF_F(HW_TLS_RECORD)
#define EDQUOT 122
#define pte_access_permitted(pte,write) (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
#define CONFIG_CACHESTAT_SYSCALL 1
#define F_SEAL_GROW 0x0004
#define CONFIG_TRACEPOINTS 1
#define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
#define CLOCK_TXINT 3
#define __cpuidle __noinstr_section(".cpuidle.text")
#define mmu_notifier_range_init(range,event,flags,mm,start,end) _mmu_notifier_range_init(range, start, end)
#define list_first_or_null_rcu(ptr,type,member) ({ struct list_head *__ptr = (ptr); struct list_head *__next = READ_ONCE(__ptr->next); likely(__ptr != __next) ? list_entry_rcu(__next, type, member) : NULL; })
#define IS_SETLKW32(cmd) (0)
#define __late_set_fixmap __set_fixmap
#define IOPRIO_PRIO_MASK ((1UL << IOPRIO_CLASS_SHIFT) - 1)
#define __HAVE_ARCH_MEMCPY 
#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
#define _ASM_EXTABLE_UACCESS(insn,fixup) _ASM_EXTABLE_UACCESS_ERR_ZERO(insn, fixup, wzr, wzr)
#define NR_PAGEFLAGS 22
#define PR_SPEC_PRCTL (1UL << 0)
#define PMSG_THAW ((struct pm_message){ .event = PM_EVENT_THAW, })
#define TRBPTR_EL1_PTR_WIDTH 64
#define DACR32_EL2_D10_WIDTH 2
#define MAPLE_ALLOC_SLOTS (MAPLE_NODE_SLOTS - 1)
#define TCR2_EL2_SKL1_WIDTH 2
#define ID_AA64MMFR0_EL1_PARANGE_40 UL(0b0010)
#define ID_AA64MMFR0_EL1_PARANGE_44 UL(0b0100)
#define ID_AA64MMFR0_EL1_PARANGE_48 UL(0b0101)
#define V2_INIT_REWRITE QTREE_INIT_REWRITE
#define inl _inl
#define CONFIG_HAVE_ARCH_BITREVERSE 1
#define spin_lock_irqsave_nested(lock,flags,subclass) do { raw_spin_lock_irqsave_nested(spinlock_check(lock), flags, subclass); } while (0)
#define CONFIG_HAVE_FTRACE_MCOUNT_RECORD 1
#define list_for_each_entry_from(pos,head,member) for (; !list_entry_is_head(pos, head, member); pos = list_next_entry(pos, member))
#define HCR_VF (UL(1) << 6)
#define HWCAP2_BF16 (1 << 14)
#define __wait_var_event_interruptible(var,condition) ___wait_var_event(var, condition, TASK_INTERRUPTIBLE, 0, 0, schedule())
#define SYS_CPACR_EL12_CRn 1
#define DT_LOOS 0x6000000d
#define ARM64_HAS_AMU_EXTN 9
#define __ASM_COMPILER_H 
#define KERNEL_HWCAP_SVEBF16 __khwcap2_feature(SVEBF16)
#define ID_MMFR2_EL1_WFIStall_IMP UL(0b0001)
#define MASTER_SLAVE_STATE_ERR 4
#define ETHTOOL_STSO 0x0000001f
#define ID_AA64MMFR0_EL1_PARANGE_52 UL(0b0110)
#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
#define ID_AA64MMFR0_EL1_SNSMEM_IMP UL(0b0001)
#define TCR2_EL2_POE GENMASK(3, 3)
#define IPACK_ANY_ID (~0)
#define SPEED_50000 50000
#define CONFIG_SND_CTL_INPUT_VALIDATION 1
#define arch_scale_cpu_capacity topology_get_cpu_scale
#define AT_STATX_DONT_SYNC 0x4000
#define PF_NETBEUI AF_NETBEUI
#define HDFGRTR_EL2_PMCNTEN_WIDTH 1
#define __LINUX_OSQ_LOCK_H 
#define TRBSR_EL1_S_SHIFT 17
#define CONFIG_SCHED_MM_CID 1
#define HDFGWTR_EL2_PMSLATFR_EL1_WIDTH 1
#define REG_HCRX_EL2 S3_4_C1_C2_2
#define ARM64_HAS_NESTED_VIRT 36
#define EM_SPARC 2
#define ptrauth_prctl_reset_keys(tsk,arg) (-EINVAL)
#define HFGITR_EL2_nGCSEPP_MASK GENMASK(59, 59)
#define PMSIDR_EL1_INTERVAL_2048 UL(0b0110)
#define NETIF_F_LRO __NETIF_F(LRO)
#define KMALLOC_MAX_SIZE (1UL << KMALLOC_SHIFT_MAX)
#define arch_atomic64_fetch_or_release arch_atomic64_fetch_or_release
#define IS_SETLK64(cmd) ((cmd) == F_SETLK)
#define PMBIDR_EL1_EA_MASK GENMASK(11, 8)
#define SHRINKER_REGISTERED BIT(0)
#define ALLINT_ALLINT_WIDTH 1
#define nr_cpus_node(node) cpumask_weight(cpumask_of_node(node))
#define __LINUX_UACCESS_H__ 
#define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) }
#define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
#define DUPLEX_FULL 0x01
#define xa_lock(xa) spin_lock(&(xa)->xa_lock)
#define seqlock_init(sl) do { spin_lock_init(&(sl)->lock); seqcount_spinlock_init(&(sl)->seqcount, &(sl)->lock); } while (0)
#define LLONG_MIN (-LLONG_MAX - 1)
#define PREEMPT_MASK (__IRQ_MASK(PREEMPT_BITS) << PREEMPT_SHIFT)
#define PORT_AUI 0x01
#define MDIO_PMA_EXTABLE_10GBKX4 0x0008
#define PACKET_FANOUT_QM 5
#define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
#define HDFGWTR_EL2_PMSIRR_EL1_SHIFT 31
#define ID_MMFR0_EL1_PMSA_PMSAv6 UL(0b0010)
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)
#define NETIF_F_HW_ESP_TX_CSUM __NETIF_F(HW_ESP_TX_CSUM)
#define MVFR1_EL1_SIMDLS_SIGNED false
#define HFGxTR_EL2_LOREA_EL1_WIDTH 1
#define HDFGWTR_EL2_PMCCNTR_EL0_SHIFT 15
#define ET_EXEC 2
#define ID_AA64MMFR1_EL1_HAFDBS_DBM UL(0b0010)
#define IPV6_ADDR_PREFERENCES 72
#define ID_ISAR0_EL1_BitCount_SHIFT 4
#define ARCH_HAS_RELATIVE_EXTABLE 
#define CONFIG_POWER_RESET 1
#define ID_DFR0_EL1_MMapTrc_NI UL(0b0000)
#define outw _outw
#define NETIF_F_ALL_TSO (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN | NETIF_F_TSO_MANGLEID)
#define ICC_NMIAR1_EL1_INTID_MASK GENMASK(23, 0)
#define __cacheline_aligned_in_smp __cacheline_aligned
#define for_each_cpu_wrap(cpu,mask,start) for_each_set_bit_wrap(cpu, cpumask_bits(mask), small_cpumask_bits, start)
#define PMSCR_EL1_E1SPE_SHIFT 1
#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_TABLE)
#define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
#define __NR_semctl 191
#define ID_ISAR3_EL1_SIMD_SHIFT 4
#define S_PRIVATE (1 << 9)
#define ID_AA64ZFR0_EL1_I8MM_MASK GENMASK(47, 44)
#define ID_AA64PFR1_EL1_MTE_IMP UL(0b0001)
#define HFGITR_EL2_TLBIASIDE1IS_MASK GENMASK(30, 30)
#define ID_AA64MMFR1_EL1_HAFDBS GENMASK(3, 0)
#define DACR32_EL2_D10_SHIFT 20
#define SECCOMP_RET_ALLOW 0x7fff0000U
#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
#define ID_AA64ISAR1_EL1_GPA_WIDTH 4
#define _LINUX_IF_H 
#define isb() asm volatile("isb" : : : "memory")
#define PIRx_ELx_RES0 (UL(0))
#define PIRx_ELx_RES1 (UL(0))
#define raw_cpu_or_2(pcp,val) raw_cpu_generic_to_op(pcp, val, |=)
#define raw_cpu_or_4(pcp,val) raw_cpu_generic_to_op(pcp, val, |=)
#define raw_cpu_or_8(pcp,val) raw_cpu_generic_to_op(pcp, val, |=)
#define __NR_fchmod 52
#define read_sysreg_par() ({ u64 par; asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); par = read_sysreg(par_el1); asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); par; })
#define CONFIG_RTC_HCTOSYS 1
#define sysfs_match_string(_a,_s) __sysfs_match_string(_a, ARRAY_SIZE(_a), _s)
#define HDFGRTR_EL2_PMOVS_SHIFT 18
#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
#define SIOCSIFBR 0x8941
#define split_huge_pmd(__vma,__pmd,__address) do { } while (0)
#define SHM_RDONLY 010000
#define ptrauth_kernel_pac_mask() GENMASK_ULL(63, vabits_actual)
#define SMCR_ELx_EZT0_MASK GENMASK(30, 30)
#define p4d_ERROR(p4d) (pgd_ERROR((p4d).pgd))
#define KUNIT_ASSERT_PTR_NE(test,left,right) KUNIT_ASSERT_PTR_NE_MSG(test, left, right, NULL)
#define BLKDISCARD _IO(0x12,119)
#define HDFGRTR_EL2_PMCNTEN GENMASK(16, 16)
#define MODULE_ALIAS_FS(NAME) MODULE_ALIAS("fs-" NAME)
#define PMSIDR_EL1_LDS GENMASK(4, 4)
#define __io_par(v) __io_ar(v)
#define IDA_INIT_FLAGS (XA_FLAGS_LOCK_IRQ | XA_FLAGS_ALLOC)
#define ID_ISAR1_EL1_Except_AR_WIDTH 4
#define __diag_error(compiler,version,option,comment) __diag_ ## compiler(version, error, option)
#define HFGITR_EL2_TLBIVAE1OS_MASK GENMASK(19, 19)
#define ESR_ELx_EC_ILL (0x0E)
#define HDFGRTR_EL2_DBGCLAIM_MASK GENMASK(5, 5)
#define SIGKILL 9
#define pmd_access_permitted(pmd,write) (pte_access_permitted(pmd_pte(pmd), (write)))
#define virt_mb__before_atomic() do { kcsan_mb(); __smp_mb__before_atomic(); } while (0)
#define PSR_MODE32_BIT 0x00000010
#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
#define KERNEL_HWCAP_SVEPMULL __khwcap2_feature(SVEPMULL)
#define MDIO_PMD_TXDIS_GLOBAL 0x0001
#define SCTLR_EL1_SPAN_WIDTH 1
#define MAX_PHYSMEM_BITS CONFIG_ARM64_PA_BITS
#define init_waitqueue_head(wq_head) do { static struct lock_class_key __key; __init_waitqueue_head((wq_head), #wq_head, &__key); } while (0)
#define CONFIG_HAVE_SYSCALL_TRACEPOINTS 1
#define ID_MMFR2_EL1_UniTLB_BROADCAST UL(0b0101)
#define ECHRNG 44
#define CONFIG_ZYNQMP_POWER 1
#define TCR2_EL2_AMEC0_SHIFT 12
#define ARCH_HAS_GENERIC_IOPORT_MAP 
#define PSR_D_BIT 0x00000200
#define ID_ISAR3_EL1_TabBranch_WIDTH 4
#define lock_acquired(lockdep_map,ip) do {} while (0)
#define ID_AA64PFR1_EL1_CSV2_frac GENMASK(35, 32)
#define HFGxTR_EL2_ICC_IGRPENn_EL1_WIDTH 1
#define CONFIG_AS_HAS_CFI_NEGATE_RA_STATE 1
#define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS)
#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
#define DCZID_EL0_RES0 (UL(0) | GENMASK_ULL(63, 5))
#define HDFGRTR_EL2_TRC_SHIFT 33
#define HDFGWTR_EL2_TRCPRGCTLR_SHIFT 44
#define ETHTOOL_COALESCE_ALL_PARAMS GENMASK(26, 0)
#define NETIF_F_RXFCS __NETIF_F(RXFCS)
#define OSECCR_EL1_EDECCR_SHIFT 0
#define MVFR1_EL1_SIMDHP_WIDTH 4
#define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
#define ID_AA64MMFR3_EL1_D128_NI UL(0b0000)
#define PRIO_TO_NICE(prio) ((prio) - DEFAULT_PRIO)
#define __ALIGN_KERNEL(x,a) __ALIGN_KERNEL_MASK(x, (__typeof__(x))(a) - 1)
#define _LINUX_SYSINFO_H 
#define _UAPI_LINUX_SCHED_H 
#define ADVERTISED_40000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseKR4_Full)
#define __init_timer_on_stack(_timer,_fn,_flags) do { static struct lock_class_key __key; init_timer_on_stack_key((_timer), (_fn), (_flags), #_timer, &__key); } while (0)
#define __WAIT_QUEUE_HEAD_INIT_ONSTACK(name) ({ init_waitqueue_head(&name); name; })
#define WARN(condition,format...) ({ int __ret_warn_on = !!(condition); if (unlikely(__ret_warn_on)) __WARN_printf(TAINT_WARN, format); unlikely(__ret_warn_on); })
#define TCR2_EL1x_HAFT_SHIFT 11
#define ELF32_R_TYPE(x) ((x) & 0xff)
#define HFGITR_EL2_CPPRCTX_WIDTH 1
#define __is_lm_address(addr) (((u64)(addr) - PAGE_OFFSET) < (PAGE_END - PAGE_OFFSET))
#define __nmi_exit() do { BUG_ON(!in_nmi()); __preempt_count_sub(NMI_OFFSET + HARDIRQ_OFFSET); arch_nmi_exit(); lockdep_on(); } while (0)
#define ENOLCK 37
#define __io_paw() __io_aw()
#define seqcount_raw_spinlock_init(s,lock) seqcount_LOCKNAME_init(s, lock, raw_spinlock)
#define HFGxTR_EL2_nGCS_EL1_WIDTH 1
#define writew_relaxed writew_relaxed
#define HCR_SWIO (UL(1) << 1)
#define CONFIG_ARCH_INLINE_READ_LOCK 1
#define WHITEOUT_DEV 0
#define HCRX_EL2_VINMI_SHIFT 7
#define __set_current_state(state_value) do { debug_normal_state_change((state_value)); WRITE_ONCE(current->__state, (state_value)); } while (0)
#define ID_ISAR5_EL1_SHA1_SHIFT 8
#define PR_GET_ENDIAN 19
#define HWCAP2_SME_BI32I32 (1UL << 40)
#define dma_unmap_addr_set(PTR,ADDR_NAME,VAL) (((PTR)->ADDR_NAME) = (VAL))
#define CAP_OPT_INSETID BIT(2)
#define SYS_ID_MMFR4_EL1_CRm 2
#define SYS_ID_MMFR4_EL1_CRn 0
#define ID_AA64ISAR1_EL1_SPECRES_SIGNED false
#define MDSCR_EL1_TXU_SHIFT 26
#define TAINT_FLAGS_COUNT 19
#define VMALLOC_END (VMEMMAP_START - SZ_256M)
#define ID_AA64PFR0_EL1_CSV2_NI UL(0b0000)
#define IF_PROTO_FR_ADD_ETH_PVC 0x2008
#define RADIX_TREE_INDEX_BITS (8 * sizeof(unsigned long))
#define __aligned_be64 __be64 __attribute__((aligned(8)))
#define HDFGRTR_EL2_TRCSTATR_SHIFT 47
#define ID_PFR0_EL1_State3_SIGNED false
#define __my_cpu_offset __kern_my_cpu_offset()
#define PT_PTRACED 0x00000001
#define IRQF_TRIGGER_NONE 0x00000000
#define RX_CLS_FLOW_DISC 0xffffffffffffffffULL
#define NLMSG_PAYLOAD(nlh,len) ((nlh)->nlmsg_len - NLMSG_SPACE((len)))
#define SCTLR_EL1_nTWI_SHIFT 16
#define CONFIG_LD_VERSION 24000
#define ID_PFR1_EL1_Virtualization_SHIFT 12
#define HDFGWTR_EL2_PMOVS_WIDTH 1
#define procedure_link_pointer(regs) ((regs)->regs[30])
#define TCR2_EL1x_DisCH0_MASK GENMASK(14, 14)
#define SYS_CSSELR_EL1_CRm 0
#define SYS_CSSELR_EL1_CRn 0
#define __LINUX_LOCKDEP_H 
#define PSR_AA32_MODE_UND 0x0000001b
#define PREEMPT_NEED_RESCHED BIT(32)
#define FWNODE_FLAG_NOT_DEVICE BIT(1)
#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
#define ETH_P_PUPAT 0x0201
#define ESTATUS_1000_XHALF 0x4000
#define ID_ISAR6_EL1_DP_SHIFT 4
#define PSEC_PER_SEC 1000000000000LL
#define AT_EXECFD 2
#define ETHTOOL_FORCED_SPEED_MAP(prefix,value) { .speed = SPEED_ ##value, .cap_arr = prefix ##_ ##value, .arr_size = ARRAY_SIZE(prefix ##_ ##value), }
#define CPACR_ELx_TTA GENMASK(28, 28)
#define AT_EXECFN 31
#define LRU_REFS_WIDTH min(__LRU_REFS_WIDTH, BITS_PER_LONG - NR_PAGEFLAGS - ZONES_WIDTH - LRU_GEN_WIDTH - SECTIONS_WIDTH - NODES_WIDTH - KASAN_TAG_WIDTH - LAST_CPUPID_WIDTH)
#define __RAW_SPIN_LOCK_UNLOCKED(lockname) (raw_spinlock_t) __RAW_SPIN_LOCK_INITIALIZER(lockname)
#define ID_AA64ZFR0_EL1_F32MM_SIGNED false
#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
#define _LINUX_FTRACE_IRQ_H 
#define HDFGWTR_EL2_PMCCNTR_EL0_MASK GENMASK(15, 15)
#define PTE_ADDR_MASK PTE_ADDR_LOW
#define SYS_LORSA_EL1_Op1 0
#define CONFIG_ARCH_SUPPORTS_HUGETLBFS 1
#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
#define SCTLR_EL1_C_WIDTH 1
#define __read_mostly __section(".data..read_mostly")
#define CONTEXTIDR_ELx_PROCID GENMASK(31, 0)
#define lockdep_assert_held_read(l) lockdep_assert(lockdep_is_held_type(l, 1))
#define HDFGWTR_EL2_nPMSNEVFR_EL1_WIDTH 1
#define SUBCMDSHIFT 8
#define MASTER_SLAVE_CFG_UNSUPPORTED 0
#define NL_SET_ERR_MSG_WEAK_MOD(extack,msg) do { if ((extack) && !(extack)->_msg) NL_SET_ERR_MSG_MOD((extack), msg); } while (0)
#define HZ_TO_USEC_NUM 4000
#define SYS_TRBIDR_EL1_Op0 3
#define SYS_TRBIDR_EL1_Op1 0
#define SYS_TRBIDR_EL1_Op2 7
#define SYS_LORSA_EL1_Op2 0
#define PMBIDR_EL1_UNKN (UL(0))
#define SLAB_RED_ZONE ((slab_flags_t __force)0x00000400U)
#define SCTLR_EL1_NMI GENMASK(61, 61)
#define PMSIRR_EL1_UNKN (UL(0))
#define MAPLE_RESERVED_RANGE 4096
#define _Q_TAIL_OFFSET _Q_TAIL_IDX_OFFSET
#define SMPRIMAP_EL2_P14_SHIFT 56
#define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
#define ID_AA64PFR1_EL1_PFAR_WIDTH 4
#define P4D_TYPE_SECT (_AT(p4dval_t, 1) << 0)
#define HDFGRTR_EL2_nBRBCTL_MASK GENMASK(60, 60)
#define ID_AFR0_EL1_IMPDEF3_SHIFT 12
#define CONFIG_HAVE_ARCH_KGDB 1
#define time_is_after_jiffies64(a) time_before64(get_jiffies_64(), a)
#define _KUNIT_TRY_CATCH_H 
#define HZ_TO_USEC_ADJ32 U64_C(0x0)
#define SUPPORTED_1000baseKX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseKX_Full)
#define BUG_GET_TAINT(bug) ((bug)->flags >> 8)
#define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
#define arch_atomic_sub_return_release arch_atomic_sub_return_release
#define GFP_ZONE_BAD ( 1 << (___GFP_DMA | ___GFP_HIGHMEM) | 1 << (___GFP_DMA | ___GFP_DMA32) | 1 << (___GFP_DMA32 | ___GFP_HIGHMEM) | 1 << (___GFP_DMA | ___GFP_DMA32 | ___GFP_HIGHMEM) | 1 << (___GFP_MOVABLE | ___GFP_HIGHMEM | ___GFP_DMA) | 1 << (___GFP_MOVABLE | ___GFP_DMA32 | ___GFP_DMA) | 1 << (___GFP_MOVABLE | ___GFP_DMA32 | ___GFP_HIGHMEM) | 1 << (___GFP_MOVABLE | ___GFP_DMA32 | ___GFP_DMA | ___GFP_HIGHMEM) )
#define DT_SYMTAB 6
#define ZERO_SIZE_PTR ((void *)16)
#define HWCAP2_SME (1 << 23)
#define CNTPOFF_EL2_UNKN (UL(0))
#define IORESOURCE_MEM_8BIT (0<<3)
#define HDFGRTR_EL2_nBRBCTL_SHIFT 60
#define MVFR0_EL1_FPDP_WIDTH 4
#define MVFR1_EL1_SIMDHP_SIMDHP UL(0b0001)
#define ID_DFR0_EL1_TraceFilt_WIDTH 4
#define IRQF_COND_SUSPEND 0x00040000
#define SCTLR_EL1_SED_SHIFT 8
#define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == PTE_ATTRINDX(MT_NORMAL_TAGGED))
#define ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE128 UL(0b0011)
#define __initcall_name(prefix,__iid,id) __PASTE(__, __PASTE(prefix, __PASTE(__, __PASTE(__iid, id))))
#define AF_X25 9
#define PMSFCR_EL1_FL_MASK GENMASK(2, 2)
#define ID_AA64ZFR0_EL1_BF16_IMP UL(0b0001)
#define MSG_TRYHARD 4
#define MAX_INT64_SECONDS (((s64)(~((u64)0)>>1)/HZ)-1)
#define ID_AA64ISAR2_EL1_CLRBHB_SHIFT 28
#define HFGITR_EL2_TLBIVAALE1IS_MASK GENMASK(33, 33)
#define NODEMASK_SCRATCH_FREE(x) NODEMASK_FREE(x)
#define SCTLR_EL1_EnIB_SHIFT 30
#define KPROBE_FLAG_ON_FUNC_ENTRY 16
#define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT)
#define _LINUX_LIST_NULLS_H 
#define ELFDATANONE 0
#define IF_IFACE_E1 0x1004
#define ID_MMFR4_EL1_LSM_NI UL(0b0000)
#define SCM_CREDENTIALS 0x02
#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT))
#define ID_DFR0_EL1_CopDbg GENMASK(3, 0)
#define CPU_MMU_OFF (-1)
#define fl4_icmp_code uli.icmpt.code
#define HDFGRTR_EL2_PMSELR_EL0_SHIFT 19
#define local64_add_return(i,l) local_add_return((i), (&(l)->a))
#define ID_ISAR3_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define __kernel_old_uid_t __kernel_old_uid_t
#define VMEMMAP_END (VMEMMAP_START + VMEMMAP_SIZE)
#define QC_RT_SPC_HARD (1<<5)
#define ID_MMFR0_EL1_VMSA_IMPDEF UL(0b0001)
#define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
#define HDFGWTR_EL2_PMSCR_EL1_WIDTH 1
#define seqprop_sequence(s) __seqprop(s, sequence)(s)
#define CONFIG_GENERIC_STRNCPY_FROM_USER 1
#define lockdep_set_novalidate_class(lock) lockdep_set_class_and_name(lock, &__lockdep_no_validate__, #lock)
#define REG_ID_AA64ZFR0_EL1 S3_0_C0_C4_4
#define __packed __attribute__((__packed__))
#define smp_processor_id() __smp_processor_id()
#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
#define HDFGWTR_EL2_PMEVCNTRn_EL0_MASK GENMASK(12, 12)
#define KBD_KEYCODE 0x0001
#define compat_ptr_ioctl NULL
#define MASTER_SLAVE_CFG_MASTER_FORCE 4
#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
#define BRCM_CPU_PART_BRAHMA_B53 0x100
#define __safe 
#define MDCR_EL2_TDOSA (UL(1) << 10)
#define SETPAGEFLAG(uname,lname,policy) static __always_inline void folio_set_ ##lname(struct folio *folio) { set_bit(PG_ ##lname, folio_flags(folio, FOLIO_ ##policy)); } static __always_inline void SetPage ##uname(struct page *page) { set_bit(PG_ ##lname, &policy(page, 1)->flags); }
#define TCR2_EL2_AIE GENMASK(4, 4)
#define EDEADLOCK EDEADLK
#define CONFIG_CC_NO_ARRAY_BOUNDS 1
#define CLD_DUMPED 3
#define HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT 14
#define __pa_symbol_nodebug(x) __kimg_to_phys((phys_addr_t)(x))
#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
#define SIGEV_SIGNAL 0
#define ID_DFR0_EL1_MMapDbg_Armv7 UL(0b0100)
#define PSR_AA32_Q_BIT 0x08000000
#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
#define __cmp_once(op,x,y,unique_x,unique_y) ({ typeof(x) unique_x = (x); typeof(y) unique_y = (y); static_assert(__types_ok(x, y), #op "(" #x ", " #y ") signedness error, fix types or consider u" #op "() before " #op "_t()"); __cmp(op, unique_x, unique_y); })
#define __init __section(".init.text") __cold __latent_entropy __noinitretpoline
#define EXIT_TRACE (EXIT_ZOMBIE | EXIT_DEAD)
#define HFGITR_EL2_nGCSSTR_EL1_WIDTH 1
#define VFS_CAP_U32 VFS_CAP_U32_3
#define _LINUX_BH_H 
#define this_cpu_cmpxchg64(pcp,o,n) this_cpu_cmpxchg_8(pcp, o, n)
#define cpumask_pr_args(maskp) nr_cpu_ids, cpumask_bits(maskp)
#define flush_icache_user_range flush_icache_range
#define asmlinkage CPP_ASMLINKAGE
#define arch_write_lock(l) queued_write_lock(l)
#define NTP_SCALE_SHIFT 32
#define ETH_P_1588 0x88F7
#define HDFGRTR_EL2_PMBPTR_EL1 GENMASK(24, 24)
#define CLONE_CHILD_CLEARTID 0x00200000
#define QIF_ALL (QIF_LIMITS | QIF_USAGE | QIF_TIMES)
#define SCTLR_EL1_NMI_WIDTH 1
#define ID_DFR1_EL1_HPMN0 GENMASK(7, 4)
#define ID_MMFR3_EL1_CohWalk_MASK GENMASK(23, 20)
#define NETIF_F_GSO __NETIF_F(GSO)
#define QC_INO_WARNS (1<<10)
#define ID_PFR2_EL1_RES0 (UL(0) | GENMASK_ULL(63, 12))
#define ID_PFR2_EL1_RES1 (UL(0))
#define SYS_TRBSR_EL1_Op0 3
#define SYS_TRBSR_EL1_Op1 0
#define wait_event_interruptible_lock_irq(wq_head,condition,lock) ({ int __ret = 0; if (!(condition)) __ret = __wait_event_interruptible_lock_irq(wq_head, condition, lock,); __ret; })
#define BITS_TO_COMPAT_LONGS(bits) DIV_ROUND_UP(bits, BITS_PER_COMPAT_LONG)
#define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN)
#define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO)
#define CONFIG_SYSFS 1
#define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
#define MDIO_STAT1 MII_BMSR
#define __initcall_id(fn) __PASTE(__KBUILD_MODNAME, __PASTE(__, __PASTE(__COUNTER__, __PASTE(_, __PASTE(__LINE__, __PASTE(_, fn))))))
#define PMSFCR_EL1_B_MASK GENMASK(16, 16)
#define POISON_FREE 0x6b
#define __NR_fchownat 54
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define CONFIG_ARCH_INLINE_SPIN_UNLOCK 1
#define ID_ISAR0_EL1_Debug_SIGNED false
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define NETIF_F_TSO6 __NETIF_F(TSO6)
#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
#define IRQF_NO_AUTOEN 0x00080000
#define SLIMBUS_NAME_SIZE 32
#define CONFIG_ARM64_VA_BITS_39 1
#define __page_to_pfn(page) (unsigned long)((page) - vmemmap)
#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
#define IOCTL_MEI_NOTIFY_SET _IOW('H', 0x02, __u32)
#define MII_NWAYTEST 0x14
#define MDIO_DEVICE_IS_PHY 0x80000000
#define HFGxTR_EL2_APIAKey_SHIFT 7
#define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
#define net_crit_ratelimited(fmt,...) net_ratelimited_function(pr_crit, fmt, ##__VA_ARGS__)
#define MVFR0_EL1_FPTrap_SHIFT 12
#define SKBFL_ALL_ZEROCOPY (SKBFL_ZEROCOPY_FRAG | SKBFL_PURE_ZEROCOPY | SKBFL_DONT_ORPHAN | SKBFL_MANAGED_FRAG_REFS)
#define ETHTOOL_STUNABLE 0x00000049
#define SIGPWR 30
#define list_for_each_reverse(pos,head) for (pos = (head)->prev; pos != (head); pos = pos->prev)
#define next_node(n,src) __next_node((n), &(src))
#define STATX_CTIME 0x00000080U
#define HFGITR_EL2_DCCSW_MASK GENMASK(5, 5)
#define DCACHE_OP_PRUNE 0x00000010
#define ID_AA64MMFR0_EL1_ASIDBITS GENMASK(7, 4)
#define HFGxTR_EL2_AFSR0_EL1_SHIFT 0
#define MDIO_AN_STAT1_XNP 0x0080
#define PTE_SHARED (_AT(pteval_t, 3) << 8)
#define PIDS_PER_CPU_MIN 8
#define TPIDR_EL1_ThreadID_SHIFT 0
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
#define devm_release_region(dev,start,n) __devm_release_region(dev, &ioport_resource, (start), (n))
#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
#define SET_PERSONALITY2(ex,state) SET_PERSONALITY(ex)
#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; })
#define PTRS_PER_PMD (1 << (PAGE_SHIFT - 3))
#define DT_REL 17
#define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
#define ID_AA64MMFR3_EL1_TCRX_NI UL(0b0000)
#define UPROBE_HANDLER_REMOVE 1
#define ARM_CPU_IMP_FUJITSU 0x46
#define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2)
#define ID_ISAR5_EL1_SHA2_IMP UL(0b0001)
#define SYS_SHUTDOWN 13
#define ETH_RSS_HASH_XOR __ETH_RSS_HASH(XOR)
#define PMSCR_EL1_CX_WIDTH 1
#define MDIO_PMA_STAT2_EXTABLE 0x0200
#define SMPRIMAP_EL2_RES0 (UL(0))
#define SMPRIMAP_EL2_RES1 (UL(0))
#define MTE_GRANULE_MASK (~(MTE_GRANULE_SIZE - 1))
#define rcu_dereference_check_fdtable(files,fdtfd) rcu_dereference_check((fdtfd), lockdep_is_held(&(files)->file_lock))
#define CAP_SYS_ADMIN 21
#define PTRACE_EVENT_FORK 1
#define REG_ID_AA64DFR0_EL1 S3_0_C0_C5_0
#define SB_I_NOUMASK 0x00001000
#define ID_AA64PFR0_EL1_EL1_IMP UL(0b0001)
#define ETHTOOL_SGSO 0x00000024
#define WARN_ON_SMP(x) WARN_ON(x)
#define DT_HASH 4
#define FMODE_32BITHASH ((__force fmode_t)0x200)
#define ID_MMFR1_EL1_L1Hvd_MASK GENMASK(19, 16)
#define ASSERT_EXCLUSIVE_ACCESS(var) __kcsan_check_access(&(var), sizeof(var), KCSAN_ACCESS_WRITE | KCSAN_ACCESS_ASSERT)
#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
#define GETZCNT 15
#define TCR2_EL2_POE_WIDTH 1
#define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
#define ID_AA64ISAR2_EL1_MOPS_MASK GENMASK(19, 16)
#define read_poll_timeout_atomic(op,val,cond,delay_us,timeout_us,delay_before_read,args...) ({ u64 __timeout_us = (timeout_us); s64 __left_ns = __timeout_us * NSEC_PER_USEC; unsigned long __delay_us = (delay_us); u64 __delay_ns = __delay_us * NSEC_PER_USEC; if (delay_before_read && __delay_us) { udelay(__delay_us); if (__timeout_us) __left_ns -= __delay_ns; } for (;;) { (val) = op(args); if (cond) break; if (__timeout_us && __left_ns < 0) { (val) = op(args); break; } if (__delay_us) { udelay(__delay_us); if (__timeout_us) __left_ns -= __delay_ns; } cpu_relax(); if (__timeout_us) __left_ns--; } (cond) ? 0 : -ETIMEDOUT; })
#define RESOLVE_NO_XDEV 0x01
#define ARM64_SPECTRE_BHB 61
#define TP_STATUS_BLK_TMO (1 << 5)
#define HFGxTR_EL2_nACCDATA_EL1 GENMASK(50, 50)
#define _LINUX_IRQDESC_H 
#define sig_kernel_coredump(sig) siginmask(sig, SIG_KERNEL_COREDUMP_MASK)
#define XA_STATE(name,array,index) struct xa_state name = __XA_STATE(array, index, 0, 0)
#define NSIGBUS 5
#define SYM_TYPED_FUNC_START(name) SYM_TYPED_START(name, SYM_L_GLOBAL, SYM_A_ALIGN) bti c ;
#define TRBMAR_EL1_SH_NON_SHAREABLE UL(0b00)
#define nodes_shift_left(dst,src,n) __nodes_shift_left(&(dst), &(src), (n), MAX_NUMNODES)
#define KERNEL_HWCAP_EVTSTRM __khwcap_feature(EVTSTRM)
#define this_cpu_write(pcp,val) __pcpu_size_call(this_cpu_write_, pcp, val)
#define TIMER_INIT_FLAGS (TIMER_DEFERRABLE | TIMER_PINNED | TIMER_IRQSAFE)
#define HDFGRTR_EL2_PMBIDR_EL1 GENMASK(63, 63)
#define ATM_POISON_FREE 0x12
#define SKB_MAX_ALLOC (SKB_MAX_ORDER(0, 2))
#define pmd_young(pmd) pte_young(pmd_pte(pmd))
#define ID_AA64MMFR2_EL1_E0PD_MASK GENMASK(63, 60)
#define INVALID_VFSUID VFSUIDT_INIT(INVALID_UID)
#define assert_spin_locked(lock) assert_raw_spin_locked(&(lock)->rlock)
#define CONFIG_NET_VENDOR_HISILICON 1
#define PMBLIMITR_EL1_LIMIT_WIDTH 52
#define IORESOURCE_IO_16BIT_ADDR (1<<0)
#define fl6_mh_type uli.mht.type
#define phy_read_poll_timeout(phydev,regnum,val,cond,sleep_us,timeout_us,sleep_before_read) ({ int __ret, __val; __ret = read_poll_timeout(__val = phy_read, val, __val < 0 || (cond), sleep_us, timeout_us, sleep_before_read, phydev, regnum); if (__val < 0) __ret = __val; if (__ret) phydev_err(phydev, "%s failed: %d\n", __func__, __ret); __ret; })
#define ID_AA64PFR0_EL1_CSV2_SIGNED false
#define TP_STATUS_SENDING (1 << 1)
#define key_invalidate(k) do { } while(0)
#define CONFIG_CONTEXT_TRACKING_IDLE 1
#define ID_AA64MMFR1_EL1_UNKN (UL(0))
#define ID_AA64DFR0_EL1_PMSVer_V1P2 UL(0b0011)
#define _inw _inw
#define PMSFCR_EL1_FnE_WIDTH 1
#define PMBSR_EL1_DL_SHIFT 19
#define seqcount_mutex_init(s,lock) seqcount_LOCKNAME_init(s, lock, mutex)
#define NET_SKBUFF_DATA_USES_OFFSET 1
#define MII_LBRERROR 0x18
#define MDIO_PCS_1000BT1_CTRL 2304
#define STA_PPSJITTER 0x0200
#define ID_AA64MMFR2_EL1_FWB_SIGNED false
#define SMCR_ELx_EZT0_WIDTH 1
#define SECCOMP_GET_ACTION_AVAIL 2
#define PIRx_ELx_Perm11_SHIFT 44
#define __ASM_GENERIC_SIGNAL_DEFS_H 
#define struct_group_tagged(TAG,NAME,MEMBERS...) __struct_group(TAG, NAME, , MEMBERS)
#define KUNIT_EXPECT_NOT_ERR_OR_NULL(test,ptr) KUNIT_EXPECT_NOT_ERR_OR_NULL_MSG(test, ptr, NULL)
#define ID_AA64ZFR0_EL1_SM4_WIDTH 4
#define ID_MMFR0_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_MMFR0_EL1_RES1 (UL(0))
#define SCTLR_EL1_WXN_MASK GENMASK(19, 19)
#define XA_NODE_BUG_ON(node,x) do { } while (0)
#define ID_AA64MMFR2_EL1_FWB_IMP UL(0b0001)
#define NT_LOONGARCH_CSR 0xa01
#define STATIC_CALL_KEY_PREFIX __SCK__
#define _DPRINTK_FLAGS_INCL_MODNAME (1<<1)
#define ENOPROTOOPT 92
#define FMODE_WRITER ((__force fmode_t)0x10000)
#define flowi4_iif __fl_common.flowic_iif
#define MDSCR_EL1_RXfull_WIDTH 1
#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
#define for_each_node_mask(node,mask) for ((node) = 0; (node) < 1 && !nodes_empty(mask); (node)++)
#define PANIC_CPU_INVALID -1
#define __LINUX_PAGE_EXT_H 
#define __assume_slab_alignment __assume_aligned(ARCH_SLAB_MINALIGN)
#define start_critical_timings() do { } while (0)
#define CAP_LAST_CAP CAP_CHECKPOINT_RESTORE
#define ___ntohl(x) __be32_to_cpu(x)
#define __overflows_type(x,T) ({ typeof(T) v = 0; check_add_overflow((x), v, &v); })
#define PMSICR_EL1_COUNT_WIDTH 32
#define _LINUX_LIST_H 
#define ID_MMFR0_EL1_TCM_IMPDEF UL(0b0001)
#define __NR_io_uring_enter 426
#define HFGITR_EL2_DCCVAC_WIDTH 1
#define SYS_ID_ISAR5_EL1_CRm 2
#define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED)
#define SHM_RND 020000
#define ATOMIC_NOTIFIER_HEAD(name) struct atomic_notifier_head name = ATOMIC_NOTIFIER_INIT(name)
#define PMBLIMITR_EL1_FM_MASK GENMASK(2, 1)
#define SYS_CONTEXTIDR_EL12_Op2 1
#define list_for_each_prev(pos,head) for (pos = (head)->prev; !list_is_head(pos, (head)); pos = pos->prev)
#define PIE_E1 ( PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_NONE_O) | PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R) | PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RW) | PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R) | PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW) | PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX), PIE_RX) | PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC), PIE_RWX) | PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO), PIE_R) | PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL), PIE_RW))
#define ID_MMFR0_EL1_OuterShr_MASK GENMASK(11, 8)
#define UPROBES_BRK_IMM 0x005
#define ID_AA64AFR0_EL1_IMPDEF6_WIDTH 4
#define __ARM_KGDB_H 
#define ARM64_WORKAROUND_2077057 77
#define DL_FLAG_STATELESS BIT(0)
#define LSM_SETID_ID 1
#define REG_ISR_EL1 S3_0_C12_C1_0
#define EMFILE 24
#define LSM_PRLIMIT_READ 1
#define node_possible_map node_states[N_POSSIBLE]
#define NUMA_NO_NODE (-1)
#define SCTLR_EL1_UCI_WIDTH 1
#define ALLINT_UNKN (UL(0))
#define SIOCSIFTXQLEN 0x8943
#define __NR3264_mmap 222
#define SYS_LOREA_EL1_Op2 1
#define HFGxTR_EL2_nAMAIR2_EL1_WIDTH 1
#define CONFIG_MEMORY_ISOLATION 1
#define wait_event_lock_irq(wq_head,condition,lock) do { if (condition) break; __wait_event_lock_irq(wq_head, condition, lock, ); } while (0)
#define ID_ISAR1_EL1_Except_MASK GENMASK(7, 4)
#define HFGxTR_EL2_ERXPFGF_EL1_MASK GENMASK(46, 46)
#define __NR_listen 201
#define SA_NODEFER 0x40000000
#define ID_AA64ISAR1_EL1_DGH_SHIFT 48
#define HDFGWTR_EL2_TRBPTR_EL1_WIDTH 1
#define swap_ex_entry_fixup(a,b,tmp,delta) do { (a)->fixup = (b)->fixup + (delta); (b)->fixup = (tmp).fixup - (delta); (a)->type = (b)->type; (b)->type = (tmp).type; (a)->data = (b)->data; (b)->data = (tmp).data; } while (0)
#define DACR32_EL2_D7_MASK GENMASK(15, 14)
#define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3))
#define MAX_ORDER CONFIG_ARCH_FORCE_MAX_ORDER
#define __NR_ppoll 73
#define UINT_MAX (~0U)
#define CONFIG_RTC_NVMEM 1
#define CONFIG_LOCKDEP_STACK_TRACE_BITS 19
#define SCTLR_EL1_C_MASK GENMASK(2, 2)
#define MASTER_SLAVE_STATE_MASTER 2
#define compat_sp_hyp regs[15]
#define MVFR1_EL1_FPHP_SHIFT 24
#define SECCOMP_IOCTL_NOTIF_SEND SECCOMP_IOWR(1, struct seccomp_notif_resp)
#define for_each_netdev_feature(mask_addr,bit) for ((bit) = find_next_netdev_feature((mask_addr), NETDEV_FEATURE_COUNT); (bit) >= 0; (bit) = find_next_netdev_feature((mask_addr), (bit)))
#define SYS_USER_DISPATCH 2
#define PR_SPEC_L1D_FLUSH 2
#define NSEC_TO_HZ_DEN 4000000
#define CFI_BRK_IMM_TYPE GENMASK(9, 5)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
#define REG_PMBSR_EL1 S3_0_C9_C10_3
#define ifr_broadaddr ifr_ifru.ifru_broadaddr
#define __set_fixmap_offset(idx,phys,flags) ({ unsigned long ________addr; __set_fixmap(idx, phys, flags); ________addr = fix_to_virt(idx) + ((phys) & (PAGE_SIZE - 1)); ________addr; })
#define MSG_EOR 0x80
#define lockdep_assert_RT_in_threaded_ctx() do { } while (0)
#define PTRS_PER_PUD 1
#define SECCOMP_FILTER_FLAG_LOG (1UL << 1)
#define unsafe_memcpy(dst,src,bytes,justification) memcpy(dst, src, bytes)
#define ID_AA64ZFR0_EL1_SM4_NI UL(0b0000)
#define ID_PFR1_EL1_ProgMod GENMASK(3, 0)
#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
#define CONFIG_RTC_CLASS 1
#define SEMVMX 32767
#define KERNEL_HWCAP_ASIMDFHM __khwcap_feature(ASIMDFHM)
#define offset_in_thp(page,p) ((unsigned long)(p) & (thp_size(page) - 1))
#define RCU_FANOUT_2 (RCU_FANOUT_1 * RCU_FANOUT)
#define IORESOURCE_IRQ_HIGHEDGE (1<<0)
#define ID_AA64PFR1_EL1_CSV2_frac_WIDTH 4
#define PMSIDR_EL1_FE GENMASK(0, 0)
#define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER)
#define compat_statfs compat_statfs
#define PMSIDR_EL1_FL GENMASK(2, 2)
#define IF_IFACE_T1 0x1003
#define PMSIDR_EL1_FT GENMASK(1, 1)
#define PF_IEEE802154 AF_IEEE802154
#define ID_AA64ISAR1_EL1_SB_NI UL(0b0000)
#define IPV6_FL_S_ANY 255
#define ID_DFR0_EL1_CopDbg_NI UL(0b0000)
#define ICH_VMCR_PMR_SHIFT 24
#define REG_ID_MMFR4_EL1 S3_0_C0_C2_6
#define HDFGWTR_EL2_PMOVS_MASK GENMASK(18, 18)
#define pr_devel(fmt,...) no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
#define SYS_PMSCR_EL1_Op0 3
#define SYS_PMSCR_EL1_Op1 0
#define SYS_PMSCR_EL1_Op2 0
#define __UAPI_DEF_IN_IPPROTO 1
#define CONFIG_64BIT 1
#define AT_EACCESS 0x200
#define XA_FLAGS_TRACK_FREE ((__force gfp_t)4U)
#define CONFIG_XZ_DEC_ARMTHUMB 1
#define HCR_TERR (UL(1) << 36)
#define CONFIG_LSM "landlock,lockdown,yama,loadpin,safesetid,integrity,bpf"
#define Op2_mask 0x7
#define SEC_CONVERSION ((unsigned long)((((u64)NSEC_PER_SEC << SEC_JIFFIE_SC) + TICK_NSEC -1) / (u64)TICK_NSEC))
#define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
#define CONFIG_LOCKDEP_BITS 15
#define ID_MMFR1_EL1_L1HvdSW GENMASK(11, 8)
#define __ASM_SYSCALL_WRAPPER_H 
#define PM_EVENT_HIBERNATE 0x0004
#define SYS_GETSOCKNAME 6
#define PIRx_ELx_Perm0 GENMASK(3, 0)
#define PIRx_ELx_Perm1 GENMASK(7, 4)
#define PIRx_ELx_Perm2 GENMASK(11, 8)
#define __INIT_DELAYED_WORK(_work,_func,_tflags) do { INIT_WORK(&(_work)->work, (_func)); __init_timer(&(_work)->timer, delayed_work_timer_fn, (_tflags) | TIMER_IRQSAFE); } while (0)
#define PIRx_ELx_Perm4 GENMASK(19, 16)
#define PIRx_ELx_Perm5 GENMASK(23, 20)
#define PIRx_ELx_Perm6 GENMASK(27, 24)
#define PIRx_ELx_Perm7 GENMASK(31, 28)
#define PIRx_ELx_Perm8 GENMASK(35, 32)
#define PIRx_ELx_Perm9 GENMASK(39, 36)
#define SCXTNUM_EL1_UNKN (UL(0))
#define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
#define _UAPI__LINUX_MDIO_H__ 
#define FS_PROJ_QUOTA (1<<1)
#define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
#define arch_scale_freq_capacity topology_get_freq_scale
#define QUOTA_NL_ISOFTWARN 3
#define softirq_count() (preempt_count() & SOFTIRQ_MASK)
#define ETHTOOL_RX_FLOW_SPEC_RING 0x00000000FFFFFFFFLL
#define MMF_RECALC_UPROBES 20
#define CONFIG_EVENT_TRACING 1
#define SYSCTL_PERM_EMPTY_DIR (1 << 0)
#define read_lock_irqsave(lock,flags) do { typecheck(unsigned long, flags); flags = _raw_read_lock_irqsave(lock); } while (0)
#define ETH_P_ERSPAN2 0x22EB
#define lock_acquire_exclusive(l,s,t,n,i) lock_acquire(l, s, t, 0, 1, n, i)
#define MODULE_ALIAS_NET_PF_PROTO_TYPE(pf,proto,type) MODULE_ALIAS("net-pf-" __stringify(pf) "-proto-" __stringify(proto) "-type-" __stringify(type))
#define ETH_P_PRP 0x88FB
#define init_srcu_struct(ssp) ({ static struct lock_class_key __srcu_key; __init_srcu_struct((ssp), #ssp, &__srcu_key); })
#define ID_AA64ZFR0_EL1_SHA3_SIGNED false
#define CONFIG_ARCH_USE_SYM_ANNOTATIONS 1
#define S_IRWXG 00070
#define FS_IMMUTABLE_FL 0x00000010
#define AT_VECTOR_SIZE_BASE 22
#define ___constant_swahw32(x) ((__u32)( (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | (((__u32)(x) & (__u32)0xffff0000UL) >> 16)))
#define SYS_CTR_EL0_CRn 0
#define HDFGWTR_EL2_PMCNTEN_MASK GENMASK(16, 16)
#define DISR_EL1_IDS (UL(1) << 24)
#define flowi4_mark __fl_common.flowic_mark
#define TIF_32BIT 22
#define R_AARCH64_RELATIVE 1027
#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
#define INIT_IDMAP_DIR_SIZE ((INIT_IDMAP_DIR_PAGES + 2) * PAGE_SIZE)
#define LSM_SETID_RES 4
#define QIF_DQBLKSIZE_BITS 10
#define SCTLR_ELx_EE_SHIFT 25
#define __INIT_OR_MODULE __INIT
#define MVFR0_EL1_UNKN (UL(0))
#define pud_ERROR(pud) (p4d_ERROR((pud).p4d))
#define GFP_HIGHUSER (GFP_USER | __GFP_HIGHMEM)
#define sigev_notify_function _sigev_un._sigev_thread._function
#define ID_MMFR1_EL1_L1UniVA_MASK GENMASK(7, 4)
#define mt_write_lock_is_held(mt) (!(mt)->ma_external_lock || lock_is_held_type((mt)->ma_external_lock, 0))
#define to_phy_driver(d) container_of(to_mdio_common_driver(d), struct phy_driver, mdiodrv)
#define IIF_BGRACE 1
#define CAP_SYS_MODULE 16
#define PMSCR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 8) | GENMASK_ULL(2, 2))
#define ID_ISAR6_EL1_I8MM_MASK GENMASK(27, 24)
#define PTRACE_PEEKDATA 2
#define HDFGRTR_EL2_PMEVCNTRn_EL0 GENMASK(12, 12)
#define HFGxTR_EL2_AMAIR_EL1_WIDTH 1
#define FILE_LINE __FILE__ ":" __stringify(__LINE__)
#define sve_vl_valid(vl) __sve_vl_valid(vl)
#define PMSNEVFR_EL1_E_SHIFT 0
#define ID_AA64ISAR1_EL1_DGH GENMASK(51, 48)
#define FIX_BTMAPS_SLOTS 7
#define write_sysreg(v,r) do { u64 __val = (u64)(v); asm volatile("msr " __stringify(r) ", %x0" : : "rZ" (__val)); } while (0)
#define ADVERTISE_100FULL 0x0100
#define Q_QUOTAON 0x800002
#define HDFGRTR_EL2_OSLSR_EL1_MASK GENMASK(9, 9)
#define _LINUX_HUGE_MM_H 
#define CONFIG_WLAN_VENDOR_ATMEL 1
#define ID_MMFR4_EL1_SpecSEI GENMASK(3, 0)
#define CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH 1
#define ID_AA64MMFR2_EL1_NV_WIDTH 4
#define ILL_PRVOPC 5
#define pud_user_exec(pud) pte_user_exec(pud_pte(pud))
#define RESOLVE_BENEATH 0x08
#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
#define NLM_F_MATCH 0x200
#define SHMALL (ULONG_MAX - (1UL << 24))
#define HDFGWTR_EL2_TRCOSLAR_WIDTH 1
#define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
#define ETH_P_HDLC 0x0019
#define CONFIG_VIRTIO_MENU 1
#define net_err_ratelimited(fmt,...) net_ratelimited_function(pr_err, fmt, ##__VA_ARGS__)
#define flowi4_secid __fl_common.flowic_secid
#define ID_AFR0_EL1_IMPDEF1_MASK GENMASK(7, 4)
#define PMSIRR_EL1_INTERVAL_WIDTH 24
#define ID_AA64MMFR1_EL1_LO GENMASK(19, 16)
#define EMEDIUMTYPE 124
#define TRBPTR_EL1_PTR_MASK GENMASK(63, 0)
#define HFGITR_EL2_nBRBIALL_WIDTH 1
#define IPV6_PRIORITY_UNATTENDED 0x0200
#define __ASM_DEBUG_MONITORS_H 
#define PMSCR_EL2_PCT GENMASK(7, 6)
#define ID_AA64MMFR1_EL1_PAN_PAN3 UL(0b0011)
#define insw insw
#define __UAPI_DEF_IPV6_OPTIONS 1
#define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
#define __pa_symbol(x) __phys_addr_symbol(RELOC_HIDE((unsigned long)(x), 0))
#define __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO 1
#define KMOD_PATH_LEN 256
#define MEMFD_NOEXEC_SCOPE_NOEXEC_ENFORCED 2
#define PREEMPT_ENABLED (PREEMPT_NEED_RESCHED)
#define PageType(page,flag) ((page->page_type & (PAGE_TYPE_BASE | flag)) == PAGE_TYPE_BASE)
#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
#define ifr_newname ifr_ifru.ifru_newname
#define ndelay(n) ({ if (__builtin_constant_p(n)) { if ((n) / 20000 >= 1) __bad_ndelay(); else __const_udelay((n) * 5ul); } else { __ndelay(n); } })
#define IRQF_NO_DEBUG 0x00100000
#define TIME_BAD TIME_ERROR
#define key_lookup(k) NULL
#define ID_AA64ISAR1_EL1_BF16_IMP UL(0b0001)
#define bits_per(n) ( __builtin_constant_p(n) ? ( ((n) == 0 || (n) == 1) ? 1 : ilog2(n) + 1 ) : __bits_per(n) )
#define TRBSR_EL1_WRAP GENMASK(20, 20)
#define _LINUX_PATH_H 
#define ETH_P_ATMFATE 0x8884
#define SYM_FUNC_START_NOALIGN(name) SYM_START(name, SYM_L_GLOBAL, SYM_A_NONE) bti c ;
#define REG_PMSEVFR_EL1 S3_0_C9_C9_5
#define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
#define lockdep_assert_held_write(l) lockdep_assert(lockdep_is_held_type(l, 0))
#define PSTATE_TCO pstate_field(3, 4)
#define __raw_put_mem(str,x,ptr,err,type) do { __typeof__(*(ptr)) __pu_val = (x); switch (sizeof(*(ptr))) { case 1: __put_mem_asm(str "b", "%w", __pu_val, (ptr), (err), type); break; case 2: __put_mem_asm(str "h", "%w", __pu_val, (ptr), (err), type); break; case 4: __put_mem_asm(str, "%w", __pu_val, (ptr), (err), type); break; case 8: __put_mem_asm(str, "%x", __pu_val, (ptr), (err), type); break; default: BUILD_BUG(); } } while (0)
#define HDFGRTR_EL2_TRCID GENMASK(40, 40)
#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
#define preempt_enable() do { barrier(); preempt_count_dec(); } while (0)
#define MDIO_PMA_LASI_RXSTAT 0x9003
#define hlist_for_each_entry_continue_rcu_bh(pos,member) for (pos = hlist_entry_safe(rcu_dereference_bh(hlist_next_rcu( &(pos)->member)), typeof(*(pos)), member); pos; pos = hlist_entry_safe(rcu_dereference_bh(hlist_next_rcu( &(pos)->member)), typeof(*(pos)), member))
#define EI_PAD 8
#define netdev_crit_once(dev,fmt,...) netdev_level_once(KERN_CRIT, dev, fmt, ##__VA_ARGS__)
#define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define VM_SEQ_READ 0x00008000
#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
#define ID_AA64ISAR1_EL1_SB_SIGNED false
#define raw_spin_lock_irq(lock) _raw_spin_lock_irq(lock)
#define SYS_TRBLIMITR_EL1_Op1 0
#define CLONE_ARGS_SIZE_VER2 88
#define TRBIDR_EL1_Align_SHIFT 0
#define INPUT_DEVICE_ID_SW_MAX 0x10
#define UNDEFINE_MRS_S "	.purgem	mrs_s\n"
#define VM_FAULT_GET_HINDEX(x) (((__force unsigned int)(x) >> 16) & 0xf)
#define IIF_ALL (IIF_BGRACE | IIF_IGRACE | IIF_FLAGS)
#define TCR2_EL1x_PnCH_MASK GENMASK(0, 0)
#define scoped_guard(_name,args...) for (CLASS(_name, scope)(args), *done = NULL; !done; done = (void *)1)
#define _compiletime_assert(condition,msg,prefix,suffix) __compiletime_assert(condition, msg, prefix, suffix)
#define PMSCR_EL2_CX GENMASK(3, 3)
#define HDFGWTR_EL2_PMSICR_EL1_SHIFT 29
#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE UL(0b0101)
#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
#define ARM64_CPUCAP_BOOT_CPU_FEATURE (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
#define hard_irq_disable() do { } while(0)
#define SCTLR_EL1_EOS_SHIFT 11
#define ___or(x,y) ____or(__ARG_PLACEHOLDER_ ##x, y)
#define BLOCKING_NOTIFIER_INIT(name) { .rwsem = __RWSEM_INITIALIZER((name).rwsem), .head = NULL }
#define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == PUD_TYPE_SECT)
#define __NR_setns 268
#define __nops(n) ".rept	" #n "\nnop\n.endr\n"
#define HDFGRTR_EL2_DBGPRCR_EL1 GENMASK(7, 7)
#define CONFIG_SND_DEBUG 1
#define CONFIG_ADVISE_SYSCALLS 1
#define folio_migratetype(folio) get_pfnblock_flags_mask(&folio->page, folio_pfn(folio), MIGRATETYPE_MASK)
#define ETHTOOL_PHY_STUNABLE 0x0000004f
#define CLIDR_EL1_LoUIS_SHIFT 21
#define ID_AA64PFR1_EL1_CSV2_frac_NI UL(0b0000)
#define __NR_shmget 194
#define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
#define HDFGWTR_EL2_TRCSEQSTR GENMASK(45, 45)
#define ID_AA64ISAR0_EL1_TLB_SIGNED false
#define CONFIG_SND_SIMPLE_CARD_UTILS 1
#define _TIF_MTE_ASYNC_FAULT (1 << TIF_MTE_ASYNC_FAULT)
#define COMPAT_HWCAP_IWMMXT (1 << 9)
#define TCR_IRGN1_SHIFT 24
#define CONFIG_FUTEX_PI 1
#define __NR_faccessat2 439
#define timer_setup_on_stack(timer,callback,flags) __init_timer_on_stack((timer), (callback), (flags))
#define PM_EVENT_AUTO 0x0400
#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
#define LPA_SGMII_10FULL 0x1000
#define list_entry_lockless(ptr,type,member) container_of((typeof(ptr))READ_ONCE(ptr), type, member)
#define FS_DQ_BCOUNT (1<<12)
#define LED_COLOR_ID_YELLOW 6
#define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
#define MMF_UNSTABLE 22
#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
#define PMSCR_EL2_E2SPE_MASK GENMASK(1, 1)
#define LORSA_EL1_SA GENMASK(51, 16)
#define __NR_tkill 130
#define __NR_fgetxattr 10
#define PIE_RW 0xc
#define PIE_RX 0xa
#define ID_AA64DFR0_EL1_MTPMU GENMASK(51, 48)
#define outl_p outl_p
#define ID_AA64MMFR1_EL1_HPDS_SHIFT 12
#define DEFINE_SIMPLE_ATTRIBUTE(__fops,__get,__set,__fmt) DEFINE_SIMPLE_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, false)
#define TRBIDR_EL1_UNKN (UL(0))
#define CONFIG_ZONE_DMA32 1
#define PMSIDR_EL1_INTERVAL_256 UL(0b0000)
#define arch_update_thermal_pressure topology_update_thermal_pressure
#define PR_CAP_AMBIENT_CLEAR_ALL 4
#define EX_DATA_REG_ERR GENMASK(4, 0)
#define ARM_CPU_PART_AEM_V8 0xD0F
#define GIC_PRIO_PSR_I_SET (1 << 4)
#define ID_PFR0_EL1_DIT_SIGNED false
#define CONSOLE_LOGLEVEL_DEBUG 10
#define local64_inc_return(l) local_inc_return(&(l)->a)
#define unsafe_put_user(x,p,e) unsafe_op_wrap(__put_user(x,p),e)
#define mp_bvec_iter_len(bvec,iter) min((iter).bi_size, __bvec_iter_bvec((bvec), (iter))->bv_len - (iter).bi_bvec_done)
#define ID_AA64PFR0_EL1_EL3_SIGNED false
#define LOREA_EL1_EA_51_48_SHIFT 48
#define EX_DATA_REG_ADDR GENMASK(9, 5)
#define HDFGWTR_EL2_TRCSSCSRn_WIDTH 1
#define MDIO_ID_FMT "%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u"
#define ID_ISAR4_EL1_Unpriv_WIDTH 4
#define EX_DATA_REG_ERR_SHIFT 0
#define SCTLR_EL1_EnALS_MASK GENMASK(56, 56)
#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
#define DQUOT_STATE_FLAGS (DQUOT_USAGE_ENABLED | DQUOT_LIMITS_ENABLED | DQUOT_SUSPENDED)
#define __WRITE_ONCE(x,val) do { *(volatile typeof(x) *)&(x) = (val); } while (0)
#define devm_request_mem_region(dev,start,n,name) __devm_request_region(dev, &iomem_resource, (start), (n), (name))
#define ID_ISAR5_EL1_SHA1_WIDTH 4
#define MNT_INTERNAL 0x4000
#define SRCU_NOTIFIER_INIT(name,pcpu) { .mutex = __MUTEX_INITIALIZER(name.mutex), .head = NULL, .srcuu = __SRCU_USAGE_INIT(name.srcuu), .srcu = __SRCU_STRUCT_INIT(name.srcu, name.srcuu, pcpu), }
#define ID_AA64DFR0_EL1_BRBE_NI UL(0b0000)
#define SIGTERM 15
#define STB_GLOBAL 1
#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
#define HDFGWTR_EL2_nBRBCTL_MASK GENMASK(60, 60)
#define MDIO_PMA_EXTABLE_NBT 0x4000
#define HDFGRTR_EL2_TRCCLAIM_SHIFT 36
#define round_up(x,y) ((((x)-1) | __round_mask(x, y))+1)
#define ___GFP_NOLOCKDEP 0x4000000u
#define pgprot_decrypted(prot) (prot)
#define POISON_INUSE 0x5a
#define CPU_BOOT_SUCCESS (0)
#define HDFGRTR_EL2_TRCIMSPECn_WIDTH 1
#define EKEYREVOKED 128
#define CAP_WAKE_ALARM 35
#define STA_RONLY (STA_PPSSIGNAL | STA_PPSJITTER | STA_PPSWANDER | STA_PPSERROR | STA_CLOCKERR | STA_NANO | STA_MODE | STA_CLK)
#define ETHTOOL_SLINKSETTINGS 0x0000004d
#define _DEVICE_H_ 
#define skb_queue_walk_from_safe(queue,skb,tmp) for (tmp = skb->next; skb != (struct sk_buff *)(queue); skb = tmp, tmp = skb->next)
#define CONFIG_ARCH_HAS_FAST_MULTIPLIER 1
#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
#define MVFR1_EL1_FPHP GENMASK(27, 24)
#define MDIO_AN_10BT1_AN_STAT 527
#define ID_AA64PFR1_EL1_MTEX_MASK GENMASK(55, 52)
#define __local64_dec(l) local64_set((l), local64_read(l) - 1)
#define TCR2_EL2_PIE GENMASK(1, 1)
#define KERNEL_HWCAP_CSSC __khwcap2_feature(CSSC)
#define SRCU_NMI_UNSAFE 0x1
#define set_task_syscall_work(t,fl) set_ti_thread_flag(task_thread_info(t), TIF_ ##fl)
#define trace_recursion_clear(bit) do { (current)->trace_recursion &= ~(1<<(bit)); } while (0)
#define irq_gc_unlock_irqrestore(gc,flags) raw_spin_unlock_irqrestore(&(gc)->lock, flags)
#define PIRx_ELx_Perm4_MASK GENMASK(19, 16)
#define LOCK_UN 8
#define PMSEVFR_EL1_E_WIDTH 64
#define _Q_TAIL_IDX_OFFSET (_Q_PENDING_OFFSET + _Q_PENDING_BITS)
#define CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT 1
#define _UAPI_LIBC_COMPAT_H 
#define sigev_notify_attributes _sigev_un._sigev_thread._attribute
#define work_on_cpu_safe(_cpu,_fn,_arg) ({ static struct lock_class_key __key; work_on_cpu_safe_key(_cpu, _fn, _arg, &__key); })
#define ID_ISAR6_EL1_UNKN (UL(0))
#define IOMEM_ERR_PTR(err) (__force void __iomem *)ERR_PTR(err)
#define DCACHE_OP_DELETE 0x00000008
#define VM_UNMAPPED_AREA_TOPDOWN 1
#define __latent_entropy 
#define HWCAP2_ECV (1 << 19)
#define MNT_NOSUID 0x01
#define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
#define SEGCBLIST_ENABLED BIT(0)
#define SYS_PMBPTR_EL1_Op0 3
#define SYS_PMBPTR_EL1_Op1 0
#define SYS_PMBPTR_EL1_Op2 1
#define PAGE_IS_WRITTEN (1 << 1)
#define ETHTOOL_PHY_FAST_LINK_DOWN_ON 0
#define STATX_TYPE 0x00000001U
#define ID_AA64MMFR1_EL1_TWED GENMASK(35, 32)
#define IS_NOQUOTA(inode) ((inode)->i_flags & S_NOQUOTA)
#define insb_p insb_p
#define SYS_TRBTRG_EL1_Op1 0
#define for_each_populated_zone(zone) for (zone = (first_online_pgdat())->node_zones; zone; zone = next_zone(zone)) if (!populated_zone(zone)) ; else
#define ID_AA64MMFR1_EL1_VH GENMASK(11, 8)
#define __be64_to_cpu(x) __swab64((__force __u64)(__be64)(x))
#define skb_checksum_try_convert(skb,proto,compute_pseudo) do { if (__skb_checksum_convert_check(skb)) __skb_checksum_convert(skb, compute_pseudo(skb, proto)); } while (0)
#define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
#define CONFIG_RT_MUTEXES 1
#define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
#define arch_atomic_fetch_add_release arch_atomic_fetch_add_release
#define SMPRIMAP_EL2_F9 GENMASK(39, 36)
#define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define ID_AA64MMFR1_EL1_CMOW_NI UL(0b0000)
#define SYS_OSLAR_EL1_CRm 0
#define SYS_OSLAR_EL1_CRn 1
#define SEGV_ACCERR 2
#define ___PASTE(a,b) a ##b
#define _LINUX_SIGNAL_TYPES_H 
#define _KERNEL_CAPABILITY_VERSION _LINUX_CAPABILITY_VERSION_3
#define TPIDR_EL1_ThreadID_MASK GENMASK(63, 0)
#define local_lock_irq(lock) __local_lock_irq(lock)
#define AT_HWCAP2 26
#define SYS_FAR_EL2_Op2 0
#define static_branch_maybe(config,x) (IS_ENABLED(config) ? static_branch_likely(x) : static_branch_unlikely(x))
#define spin_lock_nest_lock(lock,nest_lock) do { raw_spin_lock_nest_lock(spinlock_check(lock), nest_lock); } while (0)
#define __NR_munlock 229
#define ID_AA64SMFR0_EL1_BI32I32_IMP UL(0b1)
#define PR_SET_VMA 0x53564d41
#define GETVAL 12
#define __moduleparam_const const
#define PMSG_INVALID ((struct pm_message){ .event = PM_EVENT_INVALID, })
#define SCTLR_EL1_EnTP2_SHIFT 60
#define EPOLLWRNORM (__force __poll_t)0x00000100
#define CONFIG_PCIEASPM_DEFAULT 1
#define arch_xchg_release(...) __xchg_wrapper(_rel, __VA_ARGS__)
#define CONFIG_SPLIT_PTLOCK_CPUS 4
#define HDFGRTR_EL2_PMSIDR_EL1 GENMASK(30, 30)
#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
#define list_for_each_entry_rcu(pos,head,member,cond...) for (__list_check_rcu(dummy, ## cond, 0), pos = list_entry_rcu((head)->next, typeof(*pos), member); &pos->member != (head); pos = list_entry_rcu(pos->member.next, typeof(*pos), member))
#define ESR_ELx_EC_SVE (0x19)
#define HFGITR_EL2_DCIVAC_MASK GENMASK(3, 3)
#define __NR_capget 90
#define _ASM_GENERIC_PERCPU_H_ 
#define MDIO_PMD_TXDIS_1 0x0004
#define TCR2_EL1x_PTTWI GENMASK(10, 10)
#define RCU_FQS_NAME_INIT { "rcu_node_fqs_0", "rcu_node_fqs_1" }
#define HCR_E2H (UL(1) << 34)
#define compat_jiffies_to_clock_t(x) (((unsigned long)(x) * COMPAT_USER_HZ) / HZ)
#define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
#define SOL_MCTP 285
#define ELF64_R_SYM(i) ((i) >> 32)
#define SUPPORTED_10000baseKX4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKX4_Full)
#define PF_VSOCK AF_VSOCK
#define swab16 __swab16
#define ID_PFR1_EL1_GenTimer_WIDTH 4
#define pmd_none(pmd) (!pmd_val(pmd))
#define ID_AA64MMFR1_EL1_nTLBPA_IMP UL(0b0001)
#define HDFGRTR_EL2_nBRBIDR_SHIFT 59
#define might_lock_read(lock) do { typecheck(struct lockdep_map *, &(lock)->dep_map); lock_acquire(&(lock)->dep_map, 0, 0, 1, 1, NULL, _THIS_IP_); lock_release(&(lock)->dep_map, _THIS_IP_); } while (0)
#define CAP_OPT_NOAUDIT BIT(1)
#define fs_initcall(fn) __define_initcall(fn, 5)
#define IPV6_FL_F_CREATE 1
#define PMSFCR_EL1_LD_SHIFT 17
#define PMD_PRESENT_INVALID (_AT(pteval_t, 1) << 59)
#define task_is_stopped(task) ((READ_ONCE(task->jobctl) & JOBCTL_STOPPED) != 0)
#define CONFIG_VGA_ARB_MAX_GPUS 16
#define __struct_group(TAG,NAME,ATTRS,MEMBERS...) union { struct { MEMBERS } ATTRS; struct TAG { MEMBERS } ATTRS NAME; } ATTRS
#define list_lru_init_memcg(lru,shrinker) __list_lru_init((lru), true, NULL, shrinker)
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 
#define xa_unlock_bh(xa) spin_unlock_bh(&(xa)->xa_lock)
#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
#define ID_AA64MMFR2_EL1_EVT_IMP UL(0b0001)
#define __PGTBL_PMD_MODIFIED 3
#define NT_PPC_TAR 0x103
#define arch___set_bit generic___set_bit
#define CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 1
#define MDIO_AN_LPA 19
#define ARM64_HAS_WFXT 48
#define VM_ALLOW_HUGE_VMAP 0x00000400
#define TPACKET_ALIGNMENT 16
#define __NR_set_robust_list 99
#define ID_AA64MMFR3_EL1_S2POE_SHIFT 20
#define KASAN_TAG_INVALID 0xFE
#define PF_LOCAL AF_LOCAL
#define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK)
#define INPUT_DEVICE_ID_MSC_MAX 0x07
#define ETH_P_CANXL 0x000E
#define S_IFIFO 0010000
#define si_upper _sifields._sigfault._addr_bnd._upper
#define percpu_rwsem_assert_held(sem) lockdep_assert_held(sem)
#define CPU_MASK_ALL (cpumask_t) { { [0 ... BITS_TO_LONGS(NR_CPUS)-2] = ~0UL, [BITS_TO_LONGS(NR_CPUS)-1] = BITMAP_LAST_WORD_MASK(NR_CPUS) } }
#define COMPAT_PTRACE_GETHBPREGS 29
#define HCRX_EL2_VFNMI_WIDTH 1
#define __lm_to_phys(addr) (((addr) - PAGE_OFFSET) + PHYS_OFFSET)
#define arch_cmpxchg64_release arch_cmpxchg_release
#define __DEFINE_SRCU(name,is_static) static DEFINE_PER_CPU(struct srcu_data, name ##_srcu_data); static struct srcu_usage name ##_srcu_usage = __SRCU_USAGE_INIT(name ##_srcu_usage); is_static struct srcu_struct name = __SRCU_STRUCT_INIT(name, name ##_srcu_usage, name ##_srcu_data)
#define __clamp_once(val,lo,hi,unique_val,unique_lo,unique_hi) ({ typeof(val) unique_val = (val); typeof(lo) unique_lo = (lo); typeof(hi) unique_hi = (hi); static_assert(__builtin_choose_expr(__is_constexpr((lo) > (hi)), (lo) <= (hi), true), "clamp() low limit " #lo " greater than high limit " #hi); static_assert(__types_ok(val, lo), "clamp() 'lo' signedness error"); static_assert(__types_ok(val, hi), "clamp() 'hi' signedness error"); __clamp(unique_val, unique_lo, unique_hi); })
#define ESR_ELx_EC_CP15_32 (0x03)
#define ETH_P_CONTROL 0x0016
#define PIE_R 0x8
#define CONFIG_MULTIUSER 1
#define PTE_CONT (_AT(pteval_t, 1) << 52)
#define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
#define SOL_LLC 268
#define __kcsan_check_write(ptr,size) __kcsan_check_access(ptr, size, KCSAN_ACCESS_WRITE)
#define SLAB_ACCOUNT 0
#define ID_AA64MMFR0_EL1_BIGENDEL0_MASK GENMASK(19, 16)
#define F_GETLEASE (F_LINUX_SPECIFIC_BASE + 1)
#define SYS_CCSIDR_EL1_Op0 3
#define SCTLR_EL1_EnAS0_MASK GENMASK(55, 55)
#define SYS_CCSIDR_EL1_Op2 0
#define DBG_HOOK_ERROR 1
#define ioport_map ioport_map
#define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight"
#define PMSIRR_EL1_RND_SHIFT 0
#define SI_LOAD_SHIFT 16
#define DIV_ROUND_CLOSEST(x,divisor) ( { typeof(x) __x = x; typeof(divisor) __d = divisor; (((typeof(x))-1) > 0 || ((typeof(divisor))-1) > 0 || (((__x) > 0) == ((__d) > 0))) ? (((__x) + ((__d) / 2)) / (__d)) : (((__x) - ((__d) / 2)) / (__d)); } )
#define __wait_event(wq_head,condition) (void)___wait_event(wq_head, condition, TASK_UNINTERRUPTIBLE, 0, 0, schedule())
#define xas_lock(xas) xa_lock((xas)->xa)
#define ID_AA64DFR0_EL1_PMUVer_NI UL(0b0000)
#define FRONTEND_STACK_ALLOC 256
#define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
#define IRQ_RETVAL(x) ((x) ? IRQ_HANDLED : IRQ_NONE)
#define RPMSG_DEVICE_MODALIAS_FMT "rpmsg:%s"
#define _LINUX_RBTREE_H 
#define AARCH64_ESR_ACCESS_MASK (1 << 6)
#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
#define CONFIG_APPLE_SART 1
#define CPU_PANIC_KERNEL (3)
#define EMULTIHOP 72
#define HFGITR_EL2_DCZVA_MASK GENMASK(11, 11)
#define PF_SUSPEND_TASK 0x80000000
#define arch___test_and_change_bit generic___test_and_change_bit
#define HCRX_EL2_CMOW_SHIFT 9
#define PHY_INIT_TIMEOUT 100000
#define HFGITR_EL2_DCISW_WIDTH 1
#define MSGCTL 14
#define SYNC_FILE_RANGE_WRITE_AND_WAIT (SYNC_FILE_RANGE_WRITE | SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WAIT_AFTER)
#define NL_SET_ERR_MSG(extack,msg) do { static const char __msg[] = msg; struct netlink_ext_ack *__extack = (extack); do_trace_netlink_extack(__msg); if (__extack) __extack->_msg = __msg; } while (0)
#define SIG_KTHREAD ((__force __sighandler_t)2)
#define SYS_ID_MMFR1_EL1_Op0 3
#define SYS_ID_MMFR1_EL1_Op1 0
#define SYS_ID_MMFR1_EL1_Op2 5
#define ICH_LR_STATE (3ULL << 62)
#define REG_CONTEXTIDR_EL1 S3_0_C13_C0_1
#define REG_CONTEXTIDR_EL2 S3_4_C13_C0_1
#define IS_MODULE(option) __is_defined(option ##_MODULE)
#define FS_DQ_ICOUNT (1<<13)
#define VTCR_EL2_HD (1 << 22)
#define PRIO_MIN (-20)
#define CONFIG_LOCKDEP 1
#define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
#define MDIO_AN_T1_LP_M_MST 0x0010
#define SYS_ID_PFR1_EL1_Op1 0
#define SYS_ID_PFR1_EL1_Op2 1
#define __UAPI_DEF_SOCKADDR_IN6 1
#define LED_FUNCTION_WLAN "wlan"
#define PMSIDR_EL1_FnE_MASK GENMASK(6, 6)
#define ID_AA64ISAR0_EL1_RDM GENMASK(31, 28)
#define F_SET_RW_HINT (F_LINUX_SPECIFIC_BASE + 12)
#define ID_ISAR2_EL1_MemHint_WIDTH 4
#define SCTLR_EL1_IESB_MASK GENMASK(21, 21)
#define min_array(array,len) __minmax_array(min, array, len)
#define HFGxTR_EL2_CTR_EL0_WIDTH 1
#define order_base_2(n) ( __builtin_constant_p(n) ? ( ((n) == 0 || (n) == 1) ? 0 : ilog2((n) - 1) + 1) : __order_base_2(n) )
#define NLMSG_LENGTH(len) ((len) + NLMSG_HDRLEN)
#define LED_FUNCTION_BOOT "boot"
#define this_cpu_generic_to_op(pcp,val,op) do { unsigned long __flags; raw_local_irq_save(__flags); raw_cpu_generic_to_op(pcp, val, op); raw_local_irq_restore(__flags); } while (0)
#define SCTLR_EL1_CP15BEN_WIDTH 1
#define ZONES_MASK ((1UL << ZONES_WIDTH) - 1)
#define ID_ISAR0_EL1_Swap_MASK GENMASK(3, 0)
#define ID_AA64PFR0_EL1_RAS_SHIFT 28
#define rwlock_acquire(l,s,t,i) lock_acquire_exclusive(l, s, t, NULL, i)
#define CONFIG_LZO_DECOMPRESS 1
#define ID_ISAR3_EL1_SVC GENMASK(11, 8)
#define SYS_DACR32_EL2_CRm 0
#define SYS_DACR32_EL2_CRn 3
#define _EXPORT_SYMBOL(sym,license) __EXPORT_SYMBOL(sym, license, "")
#define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
#define __SVE_ZREGS_SIZE(vq) (__SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - __SVE_ZREGS_OFFSET)
#define DACR32_EL2_D15_WIDTH 2
#define CONFIG_IRQ_MSI_IOMMU 1
#define SYS_GMID_EL1_CRm 0
#define SB_ACTIVE BIT(30)
#define xas_lock_irq(xas) xa_lock_irq((xas)->xa)
#define __NR_exit_group 94
#define XQM_MAXQUOTAS 3
#define SYSCTL_TWO ((void *)&sysctl_vals[2])
#define HDFGWTR_EL2_MDSCR_EL1_WIDTH 1
#define SHN_LORESERVE 0xff00
#define in_interrupt() (irq_count())
#define writeb writeb
#define PMSCR_EL2_TS GENMASK(5, 5)
#define PIRx_ELx_Perm10_MASK GENMASK(43, 40)
#define raw_cmpxchg128_acquire arch_cmpxchg128
#define for_each_clear_bit_from(bit,addr,size) for (; (bit) = find_next_zero_bit((addr), (size), (bit)), (bit) < (size); (bit)++)
#define MVFR1_EL1_SIMDFMAC_WIDTH 4
#define SMPRIMAP_EL2_P0 GENMASK(3, 0)
#define SMPRIMAP_EL2_P1 GENMASK(7, 4)
#define SMPRIMAP_EL2_P2 GENMASK(11, 8)
#define SMPRIMAP_EL2_P3 GENMASK(15, 12)
#define SMPRIMAP_EL2_P4 GENMASK(19, 16)
#define SMPRIMAP_EL2_P5 GENMASK(23, 20)
#define SMPRIMAP_EL2_P6 GENMASK(27, 24)
#define SMPRIMAP_EL2_P7 GENMASK(31, 28)
#define SMPRIMAP_EL2_P8 GENMASK(35, 32)
#define TCR2_EL1x_HAFT GENMASK(11, 11)
#define ID_AA64MMFR1_EL1_HAFDBS_SIGNED false
#define __module_param_call(prefix,name,ops,arg,perm,level,flags) static const char __param_str_ ##name[] = prefix #name; static struct kernel_param __moduleparam_const __param_ ##name __used __section("__param") __aligned(__alignof__(struct kernel_param)) = { __param_str_ ##name, THIS_MODULE, ops, VERIFY_OCTAL_PERMISSIONS(perm), level, flags, { arg } }
#define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
#define ARM64_SPECTRE_V2 58
#define ARM64_SPECTRE_V4 60
#define SMPRIMAP_EL2_P2_WIDTH 4
#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
#define PMSEVFR_EL1_RES0 (UL(0))
#define PMSEVFR_EL1_RES1 (UL(0))
#define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
#define PMBSR_EL1_MSS_SHIFT 0
#define pmd_huge_pte(mm,pmd) (pmd_ptdesc(pmd)->pmd_huge_pte)
#define local64_xchg(l,n) local_xchg((&(l)->a), (n))
#define LORC_EL1_EN_WIDTH 1
#define DT_VERDEF 0x6ffffffc
#define ID_AA64PFR1_EL1_CSV2_frac_MASK GENMASK(35, 32)
#define AT_IGNORE 1
#define _ASM_GENERIC_IOCTL_H 
#define PIRx_ELx_Perm4_WIDTH 4
#define VM_IO 0x00004000
#define __ASM_ASM_BUG_H 
#define ID_AA64MMFR2_EL1_IESB_SIGNED false
#define SEQCNT_ZERO(name) { .sequence = 0, SEQCOUNT_DEP_MAP_INIT(name) }
#define SCM_PIDFD 0x04
#define _EXPORT_PM_OPS(name,license,ns) const struct dev_pm_ops name; __EXPORT_SYMBOL(name, license, ns); const struct dev_pm_ops name
#define ID_MMFR3_EL1_MaintBcst_NO_TLB UL(0b0001)
#define SLAB_STORE_USER ((slab_flags_t __force)0x00010000U)
#define __LINUX_KMOD_H__ 
#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT
#define si_arch _sifields._sigsys._arch
#define LORC_EL1_DS_MASK GENMASK(9, 2)
#define PAGE_IS_WPALLOWED (1 << 0)
#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
#define net_dbg_ratelimited(fmt,...) do { if (0) no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__); } while (0)
#define this_cpu_and_1(pcp,val) _pcp_protect(__percpu_andnot_case_8, pcp, ~val)
#define ID_MMFR2_EL1_HvdTLB_SHIFT 12
#define R_AARCH64_ADR_PREL_PG_HI21 275
#define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
#define anon_vma_interval_tree_foreach(avc,root,start,last) for (avc = anon_vma_interval_tree_iter_first(root, start, last); avc; avc = anon_vma_interval_tree_iter_next(avc, start, last))
#define PR_SET_IO_FLUSHER 57
#define MDSCR_EL1_KDE_SHIFT 13
#define SECTION_MAP_MASK (~(BIT(SECTION_MAP_LAST_BIT) - 1))
#define __BIN_ATTR_ADMIN_RO(_name,_size) { .attr = { .name = __stringify(_name), .mode = 0400 }, .read = _name ##_read, .size = _size, }
#define __BIN_ATTR_ADMIN_RW(_name,_size) __BIN_ATTR(_name, 0600, _name ##_read, _name ##_write, _size)
#define CPACR_ELx_SMEN_WIDTH 2
#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | _TIF_SYSCALL_EMU)
#define VM_LOCKED 0x00002000
#define SIGBUS 7
#define SIPHASH_CONST_3 0x7465646279746573ULL
#define try_cmpxchg128_acquire(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg128_acquire(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define SIOCSIFHWADDR 0x8924
#define HFGITR_EL2_ERET_SHIFT 51
#define SYNC_FILE_RANGE_WRITE 2
#define ID_DFR0_EL1_UNKN (UL(0))
#define SYS_PIRE0_EL1 sys_reg(3, 0, 10, 2, 2)
#define CONFIG_SERIAL_CORE 1
#define LORC_EL1_EN_MASK GENMASK(0, 0)
#define __ptr_test_bit(nr,addr) ({ typecheck_pointer(*(addr)); test_bit(nr, (unsigned long *)(addr)); })
#define this_cpu_cmpxchg_1(pcp,o,n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
#define this_cpu_cmpxchg_2(pcp,o,n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
#define ID_AA64ISAR0_EL1_SHA2 GENMASK(15, 12)
#define ID_AA64ISAR0_EL1_SHA3 GENMASK(35, 32)
#define LED_PANIC_INDICATOR BIT(20)
#define this_cpu_cmpxchg_8(pcp,o,n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
#define MTE_TAG_MASK GENMASK((MTE_TAG_SHIFT + (MTE_TAG_SIZE - 1)), MTE_TAG_SHIFT)
#define trace_printk(fmt,...) do { char _______STR[] = __stringify((__VA_ARGS__)); if (sizeof(_______STR) > 3) do_trace_printk(fmt, ##__VA_ARGS__); else trace_puts(fmt); } while (0)
#define CONFIG_INPUT_VIVALDIFMAP 1
#define LPA_SGMII_DPX_SPD_MASK 0x1C00
#define MAPLE_RANGE64_SLOTS 16
#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
#define _outb _outb
#define ID_AA64MMFR2_EL1_IESB GENMASK(15, 12)
#define __NR_timerfd_settime 86
#define PUD_TABLE_PXN (_AT(pudval_t, 1) << 59)
#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 92
#define ID_ISAR6_EL1_FHM_SHIFT 8
#define FT_DIR 2
#define ID_AA64PFR1_EL1_THE_WIDTH 4
#define __HFGRTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50))
#define atomic_dec_and_raw_lock_irqsave(atomic,lock,flags) __cond_lock(lock, _atomic_dec_and_raw_lock_irqsave(atomic, lock, &(flags)))
#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
#define HDFGWTR_EL2_PMBPTR_EL1_MASK GENMASK(24, 24)
#define MDIO_USXGMII_100FULL 0x1200
#define raw_cmpxchg128_local arch_cmpxchg128_local
#define SHRT_MAX ((short)(USHRT_MAX >> 1))
#define EREMCHG 78
#define IPC_CREAT 00001000
#define ARM_CPU_PART_CORTEX_X1 0xD44
#define PM_EVENT_RECOVER 0x0080
#define CAP_PERFMON 38
#define HCR_TID0 (UL(1) << 15)
#define S_SWAPFILE (1 << 8)
#define SIGTTIN 21
#define cant_sleep() do { } while (0)
#define PMBIDR_EL1_EA_SHIFT 8
#define ID_AA64MMFR2_EL1_ST_WIDTH 4
#define HCR_TID1 (UL(1) << 16)
#define HDFGRTR_EL2_TRCOSLSR GENMASK(43, 43)
#define EACCES 13
#define default_console_loglevel (console_printk[3])
#define DQ_LASTSET_B 7
#define ID_AA64MMFR3_EL1_SDERR_FEAT_ADERR_IND UL(0b0011)
#define TIF_FOREIGN_FPSTATE 3
#define PMBSR_EL1_DL_MASK GENMASK(19, 19)
#define _UAPI_LINUX_IF_ETHER_H 
#define PF_XDP AF_XDP
#define TRBLIMITR_EL1_TM_SHIFT 3
#define GETNCNT 14
#define IPV6_PREFER_SRC_TMP 0x0001
#define LED_COLOR_ID_PURPLE 10
#define CONFIG_NET_VENDOR_RENESAS 1
#define R_AARCH64_MOVW_PREL_G2_NC 292
#define ID_AA64MMFR2_EL1_UAO_SHIFT 4
#define raw_cpu_read_1(pcp) raw_cpu_generic_read(pcp)
#define HFGxTR_EL2_FAR_EL1 GENMASK(17, 17)
#define raw_cpu_read_4(pcp) raw_cpu_generic_read(pcp)
#define SB_I_NODEV 0x00000004
#define __SVE_FFR_OFFSET(vq) (__SVE_PREGS_OFFSET(vq) + __SVE_PREGS_SIZE(vq))
#define ID_MMFR4_EL1_AC2_NI UL(0b0000)
#define SHM_HUGE_8MB HUGETLB_FLAG_ENCODE_8MB
#define __cond_acquires(x) 
#define xa_limit_32b XA_LIMIT(0, UINT_MAX)
#define Op1_mask 0x7
#define OSDTRRX_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define OSDTRRX_EL1_RES1 (UL(0))
#define lock_acquire_shared_recursive(l,s,t,n,i) lock_acquire(l, s, t, 2, 1, n, i)
#define CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 1
#define SVE_GET_VL() sve_get_current_vl()
#define HCR_AMO (UL(1) << 5)
#define ID_ISAR4_EL1_WithShifts_REG UL(0b0100)
#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
#define CAP_AUDIT_READ 37
#define HCRX_EL2_SCTLR2En_MASK GENMASK(15, 15)
#define ID_DFR1_EL1_MTPMU_MASK GENMASK(3, 0)
#define __ETHTOOL_DECLARE_LINK_MODE_MASK(name) DECLARE_BITMAP(name, __ETHTOOL_LINK_MODE_MASK_NBITS)
#define CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE 1
#define PROT_SECT_DEFAULT (_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
#define UPROBE_HANDLER_MASK 1
#define CAP_SYS_PTRACE 19
#define BMSR_100HALF2 0x0200
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
#define CONFIG_SND_DRIVERS 1
#define raw_cpu_cmpxchg_8(pcp,oval,nval) raw_cpu_generic_cmpxchg(pcp, oval, nval)
#define HDFGRTR_EL2_TRCSEQSTR_SHIFT 45
#define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME
#define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
#define FILE_DEDUPE_RANGE_DIFFERS 1
#define kcsan_release() do { } while (0)
#define KUNIT_EXPECT_GE_MSG(test,left,right,fmt,...) KUNIT_BINARY_INT_ASSERTION(test, KUNIT_EXPECTATION, left, >=, right, fmt, ##__VA_ARGS__)
#define ID_AA64PFR0_EL1_SEL2 GENMASK(39, 36)
#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
#define __ASM_BOOT_H 
#define KUNIT_ASSERT_PTR_NE_MSG(test,left,right,fmt,...) KUNIT_BINARY_PTR_ASSERTION(test, KUNIT_ASSERTION, left, !=, right, fmt, ##__VA_ARGS__)
#define MVFR1_EL1_FPDNaN_SHIFT 4
#define TCR2_EL2_PnCH GENMASK(0, 0)
#define MAPLE_NODE_TYPE_MASK 0x0F
#define va_start(v,l) __builtin_va_start(v, l)
#define HDFGRTR_EL2_TRCVICTLR_SHIFT 48
#define TRBLIMITR_EL1_LIMIT_SHIFT 12
#define SG_CHUNK_SIZE 128
#define MAPLE_ARANGE64_SLOTS 10
#define HDFGWTR_EL2_TRBBASER_EL1_SHIFT 50
#define ADVERTISE_1000FULL 0x0200
#define __NR_ioprio_get 31
#define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000
#define CONFIG_NET_VENDOR_QUALCOMM 1
#define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
#define SYSCTL_LONG_ONE ((void *)&sysctl_long_vals[1])
#define __NR_setpriority 140
#define pm_generic_thaw_early NULL
#define ID_DFR1_EL1_HPMN0_NI UL(0b0000)
#define SYS_SMCR_EL1_Op1 0
#define REG_PMSIDR_EL1 S3_0_C9_C9_7
#define TIME_ERROR 5
#define PF_DECnet AF_DECnet
#define IF_PROTO_PPP 0x2001
#define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
#define _UAPI_LINUX_LIMITS_H 
#define MDIO_AN_10BT1_AN_CTRL 526
#define PR_GET_PDEATHSIG 2
#define ETH_P_PHONET 0x00F5
#define SYS_OSDTRRX_EL1_Op0 2
#define SYS_OSDTRRX_EL1_Op1 0
#define SYS_OSDTRRX_EL1_Op2 2
#define __NR_pkey_alloc 289
#define ESR_ELx_EC_BKPT32 (0x38)
#define APM_CPU_PART_XGENE 0x000
#define AARCH64_DBG_REG_NAME_BCR bcr
#define ID_AA64DFR0_EL1_BRPs_MASK GENMASK(15, 12)
#define _ASM_GENERIC_SECTIONS_H_ 
#define CONFIG_BASE_FULL 1
#define CONFIG_PREEMPT_COUNT 1
#define MDIO_PMA_EXTABLE_10GBLRM 0x0002
#define __cpu_fallback_try_cmpxchg(pcp,ovalp,nval,_cmpxchg) ({ typeof(pcp) __val, __old = *(ovalp); __val = _cmpxchg(pcp, __old, nval); if (__val != __old) *(ovalp) = __val; __val == __old; })
#define __ASM_GENERIC_COMPAT_H 
#define HFGxTR_EL2_SCXTNUM_EL1_WIDTH 1
#define R_AARCH64_MOVW_PREL_G0 287
#define R_AARCH64_MOVW_PREL_G1 289
#define R_AARCH64_MOVW_PREL_G2 291
#define R_AARCH64_MOVW_PREL_G3 293
#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1,op2,crn,crm) (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
#define _COMPAT_NSIG _NSIG
#define set_special_state(state_value) do { unsigned long flags; raw_spin_lock_irqsave(&current->pi_lock, flags); debug_special_state_change((state_value)); WRITE_ONCE(current->__state, (state_value)); raw_spin_unlock_irqrestore(&current->pi_lock, flags); } while (0)
#define ID_AA64ISAR1_EL1_BF16_SHIFT 44
#define mmu_notifier_range_init_owner(range,event,flags,mm,start,end,owner) _mmu_notifier_range_init(range, start, end)
#define __NR_pidfd_send_signal 424
#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
#define SUPPORTED_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Pause)
#define pmd_cont_addr_end(addr,end) ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; (__boundary - 1 < (end) - 1) ? __boundary : (end); })
#define CLONE_NEWUTS 0x04000000
#define _PAGE_KERNEL_EXEC_CONT ((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)
#define ID_ISAR2_EL1_MultU_NI UL(0b0000)
#define REG_CTR_EL0 S3_3_C0_C0_1
#define CONFIG_IRQCHIP 1
#define PMSICR_EL1_UNKN (UL(0))
#define TRBIDR_EL1_F_WIDTH 1
#define ID_AA64MMFR1_EL1_ETS_SIGNED false
#define REG_ID_MMFR2_EL1 S3_0_C0_C1_6
#define ID_PFR0_EL1_State1_THUMB UL(0b0001)
#define ID_ISAR1_EL1_Extend_SHIFT 12
#define outb_p outb_p
#define ID_AA64PFR1_EL1_NMI_SIGNED false
#define ARM_CPU_PART_CORTEX_A35 0xD04
#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
#define __GFP_HIGH ((__force gfp_t)___GFP_HIGH)
#define elf_shdr elf64_shdr
#define round_down(x,y) ((x) & ~__round_mask(x, y))
#define PCMCIA_DEV_ID_MATCH_PROD_ID4 0x0080
#define MMF_DUMP_FILTER_SHIFT MMF_DUMPABLE_BITS
#define CONFIG_DMA_DIRECT_REMAP 1
#define ID_AA64DFR0_EL1_TraceBuffer_IMP UL(0b0001)
#define kvm_arm_exception_class ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET)
#define ID_ISAR2_EL1_MemHint_PLD UL(0b0001)
#define ID_AA64MMFR0_EL1_TGRAN16_NI UL(0b0000)
#define SLAB_SKIP_KFENCE 0
#define MIDR_CPU_MODEL(imp,partnum) ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | (0xf << MIDR_ARCHITECTURE_SHIFT) | ((partnum) << MIDR_PARTNUM_SHIFT))
#define ID_ISAR2_EL1_MemHint_PLI UL(0b0011)
#define ADVERTISE_1000XHALF 0x0040
#define ARM64_WORKAROUND_SPECULATIVE_AT 96
#define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
#define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
#define CONFIG_NET_VENDOR_ENGLEDER 1
#define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
#define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
#define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
#define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
#define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
#define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
#define PAGE_SECTION_MASK (~(PAGES_PER_SECTION-1))
#define fwnode_call_ptr_op(fwnode,op,...) (fwnode_has_op(fwnode, op) ? (fwnode)->ops->op(fwnode, ## __VA_ARGS__) : NULL)
#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
#define SVE_PT_SVE_PREG_OFFSET(vq,n) (SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
#define SYS_TFSR_EL1_TF0_SHIFT 0
#define ID_ISAR2_EL1_MultU_SHIFT 20
#define _NSIG_BPW __BITS_PER_LONG
#define ID_PFR1_EL1_Virt_frac_IMP UL(0b0001)
#define ID_AA64PFR1_EL1_PFAR GENMASK(63, 60)
#define ETH_P_MPLS_MC 0x8848
#define ifr_qlen ifr_ifru.ifru_ivalue
#define CONFIG_DECOMPRESS_LZMA 1
#define NUMA_NO_MEMBLK (-1)
#define SET_SYSTEM_SLEEP_PM_OPS(suspend_fn,resume_fn) 
#define ETHTOOL_COALESCE_USE_ADAPTIVE_RX BIT(9)
#define clear_syscall_work(fl) clear_ti_thread_flag(current_thread_info(), TIF_ ##fl)
#define RESOLVE_IN_ROOT 0x10
#define ARM_CPU_PART_CORTEX_A53 0xD03
#define ARM_CPU_PART_CORTEX_A55 0xD05
#define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
#define ID_AA64MMFR2_EL1_LSM_SHIFT 8
#define PMBSR_EL1_EA_WIDTH 1
#define HDFGRTR_EL2_PMEVTYPERn_EL0 GENMASK(13, 13)
#define ID_ISAR0_EL1_Coproc_SHIFT 16
#define IPV6_PMTUDISC_PROBE 3
#define ID_AA64MMFR2_EL1_LSM_SIGNED false
#define BITS_PER_LONG_LONG 64
#define ID_AA64MMFR1_EL1_AFP_IMP UL(0b0001)
#define ARM64_HAS_TCR2 44
#define erratum_handler(h) (arch_timer_ ##h)
#define __NR_eventfd2 19
#define SCM_SECURITY 0x03
#define HFGITR_EL2_DCCSW GENMASK(5, 5)
#define HFGxTR_EL2_nPOR_EL0_SHIFT 59
#define __ARCH_RW_LOCK_UNLOCKED { { .cnts = ATOMIC_INIT(0), }, .wait_lock = __ARCH_SPIN_LOCK_UNLOCKED, }
#define HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT 62
#define arch_has_single_step() (1)
#define ETH_P_8021AD 0x88A8
#define ID_AA64ISAR0_EL1_FHM_WIDTH 4
#define SEGV_BNDERR 3
#define CONFIG_ARCH_HAS_RELR 1
#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
#define NT_PPC_EBB 0x106
#define NT_PRFPREG 2
#define HDFGRTR_EL2_PMBIDR_EL1_WIDTH 1
#define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
#define CONFIG_HAVE_FUNCTION_GRAPH_TRACER 1
#define SHM_HUGE_16GB HUGETLB_FLAG_ENCODE_16GB
#define ARM_CPU_PART_CORTEX_A72 0xD08
#define ARM_CPU_PART_CORTEX_A73 0xD09
#define ARM_CPU_PART_CORTEX_A75 0xD0A
#define ARM_CPU_PART_CORTEX_A76 0xD0B
#define ARM_CPU_PART_CORTEX_A77 0xD0D
#define ARM_CPU_PART_CORTEX_A78 0xD41
#define ID_AA64MMFR1_EL1_HCX_SIGNED false
#define HDFGWTR_EL2_TRC_SHIFT 33
#define HFGxTR_EL2_LORC_EL1 GENMASK(19, 19)
#define IPV6_UNICAST_IF 76
#define SCTLR_EL1_TSCXT_SHIFT 20
#define __NR_setgroups 159
#define CONFIG_MIGRATION 1
#define ETHTOOL_EROMVERS_LEN 32
#define HPAGE_SHIFT PMD_SHIFT
#define CONFIG_GCC_VERSION 120200
#define HDFGRTR_EL2_TRBLIMITR_EL1 GENMASK(52, 52)
#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
#define ID_PFR0_EL1_State1_THUMB2 UL(0b0010)
#define CONFIG_SND_SOC 1
#define this_cpu_dec(pcp) this_cpu_sub(pcp, 1)
#define _ASM_GENERIC_PGTABLE_UFFD_H 
#define __SVE_VL_MAX (__SVE_VQ_MAX * __SVE_VQ_BYTES)
#define kunit_skip(test_or_suite,fmt,...) do { kunit_mark_skipped((test_or_suite), fmt, ##__VA_ARGS__); kunit_try_catch_throw(&((test_or_suite)->try_catch)); } while (0)
#define SYS_SMPRI_EL1_Op0 3
#define CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS 1
#define SYS_SMPRI_EL1_Op2 4
#define to_cpumask(bitmap) ((struct cpumask *)(1 ? (bitmap) : (void *)sizeof(__check_is_bitmap(bitmap))))
#define raw_cmpxchg_release arch_cmpxchg_release
#define SO_REUSEPORT 15
#define SEMMNI 32000
#define local64_dec_and_test(l) local_dec_and_test(&(l)->a)
#define TRBLIMITR_EL1_E_MASK GENMASK(0, 0)
#define SYS_PIR_EL2_Op0 3
#define SYS_PIR_EL2_Op1 4
#define SYS_PIR_EL2_Op2 3
#define FMODE_EXEC ((__force fmode_t)0x20)
#define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
#define SYS_LORC_EL1_CRm 4
#define SYS_LORC_EL1_CRn 10
#define S_DEAD (1 << 4)
#define ID_ISAR1_EL1_Except_IMP UL(0b0001)
#define CONFIG_HAVE_FUNCTION_ARG_ACCESS_API 1
#define _PAGE_OFFSET(va) (-(UL(1) << (va)))
#define MAX_RT_PRIO 100
#define DEFINE_LED_TRIGGER_GLOBAL(x) struct led_trigger *x;
#define _ASM_GENERIC_ERRNO_BASE_H 
#define SYS_ID_MMFR3_EL1_CRm 1
#define SYS_ID_MMFR3_EL1_CRn 0
#define SYS_OSECCR_EL1_Op0 2
#define SYS_OSECCR_EL1_Op1 0
#define SYS_OSECCR_EL1_Op2 2
#define MDIO_PMA_10GBT_SNR 133
#define PMSFCR_EL1_UNKN (UL(0))
#define KUNIT_ASSERT_FALSE(test,condition) KUNIT_ASSERT_FALSE_MSG(test, condition, NULL)
#define PR_FP_EXC_RES 0x080000
#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS 0x0020
#define MDSCR_EL1_RXO_WIDTH 1
#define SCTLR_EL1_ITFSB_WIDTH 1
#define ID_AA64PFR1_EL1_BT_WIDTH 4
#define MVFR0_EL1_SIMDReg_SHIFT 0
#define ID_AA64MMFR0_EL1_TGRAN16_2 GENMASK(35, 32)
#define ID_MMFR2_EL1_UniTLB_OTHER_TLBS UL(0b0100)
#define SMPRIMAP_EL2_P11_MASK GENMASK(47, 44)
#define raw_cpu_xchg_1(pcp,nval) raw_cpu_generic_xchg(pcp, nval)
#define raw_cpu_xchg_2(pcp,nval) raw_cpu_generic_xchg(pcp, nval)
#define __diagnose_as(builtin...) 
#define raw_cpu_xchg_8(pcp,nval) raw_cpu_generic_xchg(pcp, nval)
#define PMSG_FREEZE ((struct pm_message){ .event = PM_EVENT_FREEZE, })
#define TIF_NEED_RESCHED 1
#define RESOLVE_NO_MAGICLINKS 0x02
#define pte_alloc(mm,pmd) (unlikely(pmd_none(*(pmd))) && __pte_alloc(mm, pmd))
#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | ESR_ELx_SYS64_ISS_DIR_READ)
#define VERIFY_OCTAL_PERMISSIONS(perms) (BUILD_BUG_ON_ZERO((perms) < 0) + BUILD_BUG_ON_ZERO((perms) > 0777) + BUILD_BUG_ON_ZERO((((perms) >> 6) & 4) < (((perms) >> 3) & 4)) + BUILD_BUG_ON_ZERO((((perms) >> 3) & 4) < ((perms) & 4)) + BUILD_BUG_ON_ZERO((((perms) >> 6) & 2) < (((perms) >> 3) & 2)) + BUILD_BUG_ON_ZERO((perms) & 2) + (perms))
#define ERESTARTNOINTR 513
#define read_trylock(lock) __cond_lock(lock, _raw_read_trylock(lock))
#define QCI_LIMITS_ENFORCED (1 << 3)
#define SIOCDELDLCI 0x8981
#define ID_MMFR0_EL1_OuterShr_HW UL(0b0001)
#define wake_up_locked(x) __wake_up_locked((x), TASK_NORMAL, 1)
#define module_exit(x) __exitcall(x);
#define CONFIG_EXPERT 1
#define ID_MMFR0_EL1_InnerShr_MASK GENMASK(31, 28)
#define raw_cpu_add_return_1(pcp,val) raw_cpu_generic_add_return(pcp, val)
#define raw_cpu_add_return_2(pcp,val) raw_cpu_generic_add_return(pcp, val)
#define raw_cpu_add_return_4(pcp,val) raw_cpu_generic_add_return(pcp, val)
#define SMIDR_EL1_SMPS GENMASK(15, 15)
#define pr_emerg(fmt,...) printk(KERN_EMERG pr_fmt(fmt), ##__VA_ARGS__)
#define ID_AA64MMFR1_EL1_HPDS_NI UL(0b0000)
#define ISR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 11) | GENMASK_ULL(5, 0))
#define ISR_EL1_RES1 (UL(0))
#define SYS_TTBR1_EL1_Op0 3
#define SYS_TTBR1_EL1_Op1 0
#define SYS_TTBR1_EL1_Op2 1
#define ftrace_regex_open(ops,flag,inod,file) ({ -ENODEV; })
#define __KERNEL_PRINTK__ 
#define MDIO_STAT2_DEVPRST_VAL 0x8000
#define div64_long(x,y) div64_s64((x), (y))
#define ID_AA64DFR0_EL1_DoubleLock GENMASK(39, 36)
#define ID_AA64MMFR2_EL1_AT_SIGNED false
#define SUPPORTED_AUI __ETHTOOL_LINK_MODE_LEGACY_MASK(AUI)
#define SYS_SMIDR_EL1_Op1 1
#define MIN_THREAD_SHIFT (14 + KASAN_THREAD_SHIFT)
#define raw_xchg_acquire arch_xchg_acquire
#define PF_RANDOMIZE 0x00400000
#define COMPAT_HWCAP_I8MM (1 << 27)
#define AF_NETLINK 16
#define __stringify_1(x...) #x
#define ID_AA64DFR0_EL1_DoubleLock_MASK GENMASK(39, 36)
#define from_tasklet(var,callback_tasklet,tasklet_fieldname) container_of(callback_tasklet, typeof(*var), tasklet_fieldname)
#define MAX_JIFFY_OFFSET ((LONG_MAX >> 1)-1)
#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
#define MVFR0_EL1_FPDP_NI UL(0b0000)
#define _PAGE_KERNEL_ROX ((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
#define _ASM_GENERIC_BITOPS_BUILTIN___FFS_H_ 
#define ETH_P_IEEEPUP 0x0a00
#define HDFGRTR_EL2_TRBTRG_EL1_WIDTH 1
#define readl_relaxed_poll_timeout(addr,val,cond,delay_us,timeout_us) readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, timeout_us)
#define _KUNIT_TEST_H 
#define devres_alloc_node(release,size,gfp,nid) __devres_alloc_node(release, size, gfp, nid, #release)
#define SCTLR_EL1_IESB_SHIFT 21
#define fl6_gre_key uli.gre_key
#define ID_AA64ZFR0_EL1_BF16_MASK GENMASK(23, 20)
#define CAP_FULL_SET ((kernel_cap_t) { CAP_VALID_MASK })
#define ARM64_HAS_S1PIE 39
#define PMSIRR_EL1_RND_MASK GENMASK(0, 0)
#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
#define __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H 
#define CONFIG_CC_HAS_KASAN_GENERIC 1
#define VM_STACK VM_GROWSDOWN
#define IPV6_HOPOPTS 54
#define ID_PFR1_EL1_Virtualization GENMASK(15, 12)
#define ID_AA64MMFR2_EL1_LSM_MASK GENMASK(11, 8)
#define __NR_execveat 281
#define ID_AA64ISAR0_EL1_RDM_MASK GENMASK(31, 28)
#define CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG 1
#define for_each_cpu_and(cpu,mask1,mask2) for_each_and_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
#define __WARN_printf(taint,arg...) do { instrumentation_begin(); __warn_printk(arg); __WARN_FLAGS(BUGFLAG_NO_CUT_HERE | BUGFLAG_TAINT(taint)); instrumentation_end(); } while (0)
#define local64_inc_not_zero(l) local_inc_not_zero(&(l)->a)
#define HFGITR_EL2_ATS1E1W_SHIFT 13
#define NETIF_F_GSO_GRE_CSUM __NETIF_F(GSO_GRE_CSUM)
#define HWCAP_CRC32 (1 << 7)
#define core_initcall(fn) __define_initcall(fn, 1)
#define ID_AA64ISAR0_EL1_RDM_SHIFT 28
#define ID_AA64PFR0_EL1_EL3_WIDTH 4
#define OSLSR_EL1_OSLK BIT(1)
#define ___clear_bit arch___clear_bit
#define slab_dead_cpu NULL
#define TRBSR_EL1_IRQ GENMASK(22, 22)
#define module_driver(__driver,__register,__unregister,...) static int __init __driver ##_init(void) { return __register(&(__driver) , ##__VA_ARGS__); } module_init(__driver ##_init); static void __exit __driver ##_exit(void) { __unregister(&(__driver) , ##__VA_ARGS__); } module_exit(__driver ##_exit);
#define CMSG_OK(mhdr,cmsg) ((cmsg)->cmsg_len >= sizeof(struct cmsghdr) && (cmsg)->cmsg_len <= (unsigned long) ((mhdr)->msg_controllen - ((char *)(cmsg) - (char *)(mhdr)->msg_control)))
#define PCMCIA_DEV_ID_MATCH_FUNC_ID 0x0004
#define ID_AA64SMFR0_EL1_SMEver GENMASK(59, 56)
#define compiletime_assert(condition,msg) _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
#define FMODE_UNSIGNED_OFFSET ((__force fmode_t)0x2000)
#define MSG_NOSIGNAL 0x4000
#define topology_llc_cpumask(cpu) (&cpu_topology[cpu].llc_sibling)
#define CONFIG_GENERIC_IDLE_POLL_SETUP 1
#define ID_PFR0_EL1_DIT_WIDTH 4
#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
#define NICE_TO_PRIO(nice) ((nice) + DEFAULT_PRIO)
#define ID_AA64MMFR3_EL1_D128_2 GENMASK(39, 36)
#define ipv6mr_acaddr ipv6mr_multiaddr
#define devm_irq_alloc_desc_at(dev,at,node) devm_irq_alloc_descs(dev, at, at, 1, node)
#define HCRX_EL2_TMEA_WIDTH 1
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL)
#define ID_AA64MMFR3_EL1_RES0 (UL(0) | GENMASK_ULL(51, 48))
#define ID_AA64MMFR3_EL1_RES1 (UL(0))
#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
#define TBSVC_MATCH_PROTOCOL_REVISION 0x0008
#define WQUEUES_STACK_ALLOC (MAX_STACK_ALLOC - FRONTEND_STACK_ALLOC)
#define ID_ISAR2_EL1_Reversal_NI UL(0b0000)
#define SB_NOSEC BIT(28)
#define REG_SCTLR_EL1 S3_0_C1_C0_0
#define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
#define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
#define pud_alloc_one(mm,address) NULL
#define MAS_START ((struct maple_enode *)1UL)
#define ID_AA64SMFR0_EL1_F64F64 GENMASK(48, 48)
#define get_dev_from_fwnode(fwnode) get_device((fwnode)->dev)
#define SOCK_CUSTOM_SOCKOPT 6
#define __rcuwait_wait_event_timeout(w,condition,state,timeout) ___rcuwait_wait_event(w, ___wait_cond_timeout(condition), state, timeout, __ret = schedule_timeout(__ret))
#define ENOMEM 12
#define SIOCSIFNETMASK 0x891c
#define SCTLR_EL1_A_SHIFT 1
#define DECLARE_STATIC_KEY_TRUE(name) extern struct static_key_true name
#define local64_inc_and_test(l) local_inc_and_test(&(l)->a)
#define DMI_MATCH(a,b) { .slot = a, .substr = b }
#define ID_AA64MMFR2_EL1_BBM_0 UL(0b0000)
#define ID_AA64MMFR2_EL1_BBM_1 UL(0b0001)
#define ID_AA64MMFR2_EL1_BBM_2 UL(0b0010)
#define ID_AA64ISAR2_EL1_CLRBHB_IMP UL(0b0001)
#define HFGxTR_EL2_CPACR_EL1_MASK GENMASK(12, 12)
#define FMODE_PWRITE ((__force fmode_t)0x10)
#define LOCK_TRACE_STATES (XXX_LOCK_USAGE_STATES*4 + 2)
#define ID_PFR0_EL1_AMU_MASK GENMASK(23, 20)
#define PACKET_FANOUT_EBPF 7
#define LED_FUNCTION_DISK_WRITE "disk-write"
#define __VDSO_JIFFIES_H 
#define FS_DQ_TIMER_MASK (FS_DQ_BTIMER | FS_DQ_ITIMER | FS_DQ_RTBTIMER)
#define ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
#define CONFIG_APPLE_AIC 1
#define __SVE_VL_MIN (__SVE_VQ_MIN * __SVE_VQ_BYTES)
#define CONFIG_HW_CONSOLE 1
#define typecheck_pointer(x) ({ typeof(x) __dummy; (void)sizeof(*__dummy); 1; })
#define MVFR0_EL1_FPSqrt_SHIFT 20
#define TCR2_EL2_HAFT_WIDTH 1
#define for_each_set_bitrange_from(b,e,addr,size) for (; (b) = find_next_bit((addr), (size), (b)), (e) = find_next_zero_bit((addr), (size), (b) + 1), (b) < (size); (b) = (e) + 1)
#define __NR_mq_unlink 181
#define ID_MMFR0_EL1_OuterShr_NC UL(0b0000)
#define SB_I_RETIRED 0x00000800
#define PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), PAGE_SIZE)
#define TLBI_TTL_TG_16K 2
#define arch_atomic_fetch_sub_release arch_atomic_fetch_sub_release
#define LPA_1000XPAUSE 0x0080
#define HFGITR_EL2_nBRBIALL GENMASK(56, 56)
#define CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED 1
#define SPEED_1000 1000
#define SYS_LORID_EL1_Op1 0
#define TESTSCFLAG_FALSE(uname,lname) TESTSETFLAG_FALSE(uname, lname) TESTCLEARFLAG_FALSE(uname, lname)
#define __always_inline inline __attribute__((__always_inline__))
#define NT_ARM_HW_BREAK 0x402
#define SIOCBONDSLAVEINFOQUERY 0x8993
#define ID_AA64ISAR1_EL1_JSCVT GENMASK(15, 12)
#define _LINUX_MOUNT_H 
#define test_and_set_thread_flag(flag) test_and_set_ti_thread_flag(current_thread_info(), flag)
#define arch_atomic64_fetch_add arch_atomic64_fetch_add
#define DECLARE_BITMAP(name,bits) unsigned long name[BITS_TO_LONGS(bits)]
#define __ASM_SMP_H 
#define non_block_start() do { } while (0)
#define MT_BUG_ON(__tree,__x) BUG_ON(__x)
#define _LINUX_IRQ_H 
#define FAULT_BRK_IMM 0x100
#define SYS_ID_DFR1_EL1_Op0 3
#define SYS_ID_DFR1_EL1_Op1 0
#define rb_for_each(node,key,tree,cmp) for ((node) = rb_find_first((key), (tree), (cmp)); (node); (node) = rb_next_match((key), (node), (cmp)))
#define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
#define CONFIG_WLAN_VENDOR_PURELIFI 1
#define NLM_F_REQUEST 0x01
#define __function_aligned __aligned(CONFIG_FUNCTION_ALIGNMENT)
#define CONFIG_PCI_DOMAINS 1
#define LPA_SGMII_10 0x0000
#define TCR_IPS_SHIFT 32
#define CLIDR_EL1_Ctype5_WIDTH 3
#define MDIO_PMA_10T1L_STAT 2295
#define S_IXOTH 00001
#define HFGxTR_EL2_nPIR_EL1_MASK GENMASK(58, 58)
#define ID_AFR0_EL1_IMPDEF2_MASK GENMASK(11, 8)
#define _Q_PENDING_MASK _Q_SET_MASK(PENDING)
#define BMCR_PDOWN 0x0800
#define ETH_P_802_2 0x0004
#define free_page(addr) free_pages((addr), 0)
#define IPV6_ROUTER_ALERT 22
#define _LINUX_RCUWAIT_H_ 
#define spin_release(l,i) lock_release(l, i)
#define ID_AA64ISAR1_EL1_XS_WIDTH 4
#define HFGxTR_EL2_APDBKey_SHIFT 5
#define ID_MMFR0_EL1_AuxReg_NI UL(0b0000)
#define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
#define SA_NOMASK SA_NODEFER
#define hlist_bl_for_each_entry_safe(tpos,pos,n,head,member) for (pos = hlist_bl_first(head); pos && ({ n = pos->next; 1; }) && ({ tpos = hlist_bl_entry(pos, typeof(*tpos), member); 1;}); pos = n)
#define ARM64_HAS_CACHE_DIC 11
#define page_folio(p) (_Generic((p), const struct page *: (const struct folio *)_compound_head(p), struct page *: (struct folio *)_compound_head(p)))
#define MVFR0_EL1_FPTrap_NI UL(0b0000)
#define lm_alias(x) __va(__pa_symbol(x))
#define IOCTL_MEI_CONNECT_CLIENT_VTAG _IOWR('H', 0x04, struct mei_connect_client_data_vtag)
#define __ASM_AUXVEC_H 
#define ID_AFR0_EL1_IMPDEF0_WIDTH 4
#define kvm_mode_names { PSR_MODE_EL0t, "EL0t" }, { PSR_MODE_EL1t, "EL1t" }, { PSR_MODE_EL1h, "EL1h" }, { PSR_MODE_EL2t, "EL2t" }, { PSR_MODE_EL2h, "EL2h" }, { PSR_MODE_EL3t, "EL3t" }, { PSR_MODE_EL3h, "EL3h" }, { PSR_AA32_MODE_USR, "32-bit USR" }, { PSR_AA32_MODE_FIQ, "32-bit FIQ" }, { PSR_AA32_MODE_IRQ, "32-bit IRQ" }, { PSR_AA32_MODE_SVC, "32-bit SVC" }, { PSR_AA32_MODE_ABT, "32-bit ABT" }, { PSR_AA32_MODE_HYP, "32-bit HYP" }, { PSR_AA32_MODE_UND, "32-bit UND" }, { PSR_AA32_MODE_SYS, "32-bit SYS" }
#define IPV6_PREFER_SRC_CGA 0x0008
#define ID_ISAR4_EL1_Barrier_NI UL(0b0000)
#define SYS_ZCR_EL2_Op0 3
#define SYS_ZCR_EL2_Op2 0
#define VMEMMAP_SHIFT (PAGE_SHIFT - STRUCT_PAGE_MAX_SHIFT)
#define ARM_CPU_IMP_APPLE 0x61
#define SZ_16 0x00000010
#define xa_lock_irq(xa) spin_lock_irq(&(xa)->xa_lock)
#define zone_idx(zone) ((zone) - (zone)->zone_pgdat->node_zones)
#define swab32p __swab32p
#define IF_PROTO_FR_ETH_PVC 0x200B
#define swab32s __swab32s
#define GMID_EL1_UNKN (UL(0))
#define SIGSTKFLT 16
#define NETIF_F_HW_VLAN_CTAG_FILTER __NETIF_F(HW_VLAN_CTAG_FILTER)
#define _PGTABLE_NOP4D_H 
#define __HAVE_ARCH_MEMSET 
#define ID_AA64ZFR0_EL1_SHA3_NI UL(0b0000)
#define ID_PFR1_EL1_Security_NI UL(0b0000)
#define TRBLIMITR_EL1_nVM_MASK GENMASK(5, 5)
#define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
#define SA_RESTORER 0x04000000
#define HDFGRTR_EL2_PMSIRR_EL1 GENMASK(31, 31)
#define MVFR2_EL1_SIMDMisc_MASK GENMASK(3, 0)
#define OPEN_HOW_SIZE_LATEST OPEN_HOW_SIZE_VER0
#define set_softirq_pending(x) (__this_cpu_write(local_softirq_pending_ref, (x)))
#define AARCH64_DBG_REG_NAME_BVR bvr
#define __sb_writers_acquired(sb,lev) percpu_rwsem_acquire(&(sb)->s_writers.rw_sem[(lev)-1], 1, _THIS_IP_)
#define ADVERTISED_20000baseMLD2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseMLD2_Full)
#define SYS_TRBLIMITR_EL1_CRm 11
#define SYS_TRBLIMITR_EL1_CRn 9
#define RUNTIME_PM_OPS(suspend_fn,resume_fn,idle_fn) .runtime_suspend = suspend_fn, .runtime_resume = resume_fn, .runtime_idle = idle_fn,
#define CLASS_ATTR_RW(_name) struct class_attribute class_attr_ ##_name = __ATTR_RW(_name)
#define ADVERTISED_10000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseT_Full)
#define QCI_ACCT_ENABLED (1 << 2)
#define PGDIR_MASK (~(PGDIR_SIZE-1))
#define NAME_MAX 255
#define files_fdtable(files) rcu_dereference_check_fdtable((files), (files)->fdt)
#define SKB_MAX_CSUM_LEVEL 3
#define DPM_FLAG_NO_DIRECT_COMPLETE BIT(0)
#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
#define PACKET_MR_MULTICAST 0
#define PUD_TABLE_BIT (_AT(pudval_t, 1) << 1)
#define RCU_POINTER_INITIALIZER(p,v) .p = RCU_INITIALIZER(v)
#define _LINUX_THREADS_H 
#define PF_SECURITY AF_SECURITY
#define PUD_SECT_RDONLY (_AT(pudval_t, 1) << 7)
#define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
#define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
#define fallthrough __attribute__((__fallthrough__))
#define ARM64_HAS_TIDCP1 45
#define VM_MAYSHARE 0x00000080
#define PIE_RW_O 0x5
#define IF_PROTO_FR 0x2003
#define CONFIG_ARM64_CONT_PMD_SHIFT 4
#define pageblock_aligned(pfn) IS_ALIGNED((pfn), pageblock_nr_pages)
#define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
#define ID_AA64MMFR3_EL1_S2PIE_IMP UL(0b0001)
#define SYS_PMBIDR_EL1_Op1 0
#define SYS_PMBIDR_EL1_Op2 7
#define EXPORT_GPL_DEV_PM_OPS(name) _EXPORT_DEV_PM_OPS(name, "GPL", "")
#define user_access_begin(ptr,len) access_ok(ptr, len)
#define ESR_ELx_FSC_SECC_TTW1 (0x1d)
#define SYS_CONTEXTIDR_EL1_CRm 0
#define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd))
#define WAKE_BCAST (1 << 3)
#define ID_AA64PFR1_EL1_MTE_SIGNED false
#define SYS_SMPRIMAP_EL2_Op0 3
#define SYS_SMPRIMAP_EL2_Op1 4
#define SYS_SMPRIMAP_EL2_Op2 5
#define SVCR_RES1 (UL(0))
#define ETH_P_PUP 0x0200
#define instrument_get_user(to) ({ u64 __tmp = (u64)(to); kmsan_unpoison_memory(&__tmp, sizeof(__tmp)); to = __tmp; })
#define KMALLOC_MAX_CACHE_SIZE (1UL << KMALLOC_SHIFT_HIGH)
#define ID_AA64PFR0_EL1_EL2_SIGNED false
#define MVFR2_EL1_RES0 (UL(0) | GENMASK_ULL(63, 8))
#define MVFR2_EL1_RES1 (UL(0))
#define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
#define CONFIG_WLAN_VENDOR_RALINK 1
#define LATE_SYSTEM_SLEEP_PM_OPS(suspend_fn,resume_fn) .suspend_late = pm_sleep_ptr(suspend_fn), .resume_early = pm_sleep_ptr(resume_fn), .freeze_late = pm_sleep_ptr(suspend_fn), .thaw_early = pm_sleep_ptr(resume_fn), .poweroff_late = pm_sleep_ptr(suspend_fn), .restore_early = pm_sleep_ptr(resume_fn),
#define const___test_and_change_bit generic___test_and_change_bit
#define _LINUX_MATH64_H 
#define ID_AA64ZFR0_EL1_AES_WIDTH 4
#define irq_alloc_desc(node) irq_alloc_descs(-1, 1, 1, node)
#define HFGxTR_EL2_LOREA_EL1_MASK GENMASK(20, 20)
#define PAGE_FLAGS_SECOND (0xffUL | 1UL << PG_has_hwpoisoned | 1UL << PG_hugetlb | 1UL << PG_large_rmappable)
#define si_int _sifields._rt._sigval.sival_int
#define ID_AA64DFR0_EL1_TraceVer_WIDTH 4
#define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
#define ICH_MISR_U (1 << 1)
#define HCRX_EL2_EnSDERR_SHIFT 20
#define PUD_MASK (~(PUD_SIZE-1))
#define ETH_MODULE_SFF_8472 0x2
#define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
#define MVFR0_EL1_FPDivide_NI UL(0b0000)
#define ID_ISAR5_EL1_SEVL_NI UL(0b0000)
#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
#define __WORK_INIT_LOCKDEP_MAP(n,k) .lockdep_map = STATIC_LOCKDEP_MAP_INIT(n, k),
#define HWCAP2_FLAGM2 (1 << 7)
#define MAXPHASE 500000000L
#define HDFGWTR_EL2_DBGPRCR_EL1_WIDTH 1
#define __LINUX_BITS_H 
#define CONFIG_MII 1
#define __LINUX_SPINLOCK_H 
#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
#define ARM64_HAS_PAN 38
#define HFGxTR_EL2_TTBR1_EL1_WIDTH 1
#define SYSCTL_LONG_MAX ((void *)&sysctl_long_vals[2])
#define this_cpu_xchg(pcp,nval) __pcpu_size_call_return2(this_cpu_xchg_, pcp, nval)
#define xa_for_each_start(xa,index,entry,start) xa_for_each_range(xa, index, entry, start, ULONG_MAX)
#define MSG_CMSG_CLOEXEC 0x40000000
#define CCSIDR_EL1_NumSets_MASK GENMASK(27, 13)
#define ID_AA64PFR1_EL1_RAS_frac_WIDTH 4
#define CAP_SETGID 6
#define ID_ISAR2_EL1_MultS_SMLABB UL(0b0010)
#define TTBR_ASID_MASK (UL(0xffff) << 48)
#define RWF_HIPRI ((__force __kernel_rwf_t)0x00000001)
#define MDSCR_EL1_ERR_MASK GENMASK(6, 6)
#define ID_ISAR3_EL1_SIMD_WIDTH 4
#define CONFIG_RING_BUFFER 1
#define PMSICR_EL1_ECOUNT_WIDTH 8
#define ID_AA64ISAR2_EL1_UNKN (UL(0))
#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
#define outw_p outw_p
#define ID_PFR1_EL1_GenTimer_SIGNED false
#define ID_AA64DFR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 0))
#define ID_AA64DFR1_EL1_RES1 (UL(0))
#define HDFGRTR_EL2_TRBSR_EL1_MASK GENMASK(55, 55)
#define HDFGRTR_EL2_DBGPRCR_EL1_MASK GENMASK(7, 7)
#define rcu_sleep_check() do { rcu_preempt_sleep_check(); if (!IS_ENABLED(CONFIG_PREEMPT_RT)) RCU_LOCKDEP_WARN(lock_is_held(&rcu_bh_lock_map), "Illegal context switch in RCU-bh read-side critical section"); RCU_LOCKDEP_WARN(lock_is_held(&rcu_sched_lock_map), "Illegal context switch in RCU-sched read-side critical section"); } while (0)
#define CONFIG_ARCH_HAS_DMA_PREP_COHERENT 1
#define MT_DEVICE_nGnRE 4
#define ID_MMFR3_EL1_CohWalk_NI UL(0b0000)
#define IPC_STAT 2
#define ID_ISAR4_EL1_Barrier_SHIFT 16
#define EM_M32R 88
#define ID_ISAR0_EL1_BitCount_MASK GENMASK(7, 4)
#define ID_ISAR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_ISAR1_EL1_RES1 (UL(0))
#define ID_AA64DFR0_EL1_BRBE_IMP UL(0b0001)
#define HWCAP_EVTSTRM (1 << 2)
#define ID_ISAR2_EL1_MultS_SMLAD UL(0b0011)
#define MSG_FIN 0x200
#define ID_AA64ISAR0_EL1_RNDR_WIDTH 4
#define CLIDR_EL1_LoUIS_MASK GENMASK(23, 21)
#define SHM_HUGETLB 04000
#define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
#define LOGLEVEL_INFO 6
#define HFGxTR_EL2_CCSIDR_EL1_WIDTH 1
#define ID_AFR0_EL1_IMPDEF0 GENMASK(3, 0)
#define ID_AFR0_EL1_IMPDEF1 GENMASK(7, 4)
#define ID_AFR0_EL1_IMPDEF2 GENMASK(11, 8)
#define ID_AFR0_EL1_IMPDEF3 GENMASK(15, 12)
#define TRBLIMITR_EL1_LIMIT_MASK GENMASK(63, 12)
#define ERESTART 85
#define arch_atomic64_fetch_and arch_atomic64_fetch_and
#define NETIF_F_HW_HSR_TAG_RM __NETIF_F(HW_HSR_TAG_RM)
#define RLIMIT_LOCKS 10
#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
#define DISTANCE_BITS 8
#define EISNAM 120
#define __GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80)
#define ID_MMFR0_EL1_VMSA_VMSAv7 UL(0b0011)
#define MESSAGE_LOGLEVEL_DEFAULT CONFIG_MESSAGE_LOGLEVEL_DEFAULT
#define xa_unlock_irqrestore(xa,flags) spin_unlock_irqrestore(&(xa)->xa_lock, flags)
#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
#define in_atomic() (preempt_count() != 0)
#define IOP_XATTR 0x0008
#define MAX_NR_GENS 4U
#define BCMA_ANY_ID 0xFFFF
#define static_branch_inc_cpuslocked(x) static_key_slow_inc_cpuslocked(&(x)->key)
#define CONFIG_MMU 1
#define try_cmpxchg64_release(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); kcsan_release(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg64_release(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define MVFR2_EL1_SIMDMisc_NI UL(0b0000)
#define SMCR_ELx_UNKN (UL(0))
#define ID_AA64PFR0_EL1_AdvSIMD_SHIFT 20
#define VM_DATA_FLAGS_EXEC (VM_READ | VM_WRITE | VM_EXEC | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#define ENOMSG 42
#define raw_spin_unlock_irq(lock) _raw_spin_unlock_irq(lock)
#define QIF_LIMITS (QIF_BLIMITS | QIF_ILIMITS)
#define KUNIT_MEM_ASSERTION(test,assert_type,left,op,right,size_,fmt,...) do { const void *__left = (left); const void *__right = (right); const size_t __size = (size_); static const struct kunit_binary_assert_text __text = { .operation = #op, .left_text = #left, .right_text = #right, }; if (likely(__left && __right)) if (likely(memcmp(__left, __right, __size) op 0)) break; _KUNIT_FAILED(test, assert_type, kunit_mem_assert, kunit_mem_assert_format, KUNIT_INIT_ASSERT(.text = &__text, .left_value = __left, .right_value = __right, .size = __size), fmt, ##__VA_ARGS__); } while (0)
#define force_successful_syscall_return() do { } while (0)
#define PM_EVENT_USER_SUSPEND (PM_EVENT_USER | PM_EVENT_SUSPEND)
#define __swait_event_idle_timeout(wq,condition,timeout) ___swait_event(wq, ___wait_cond_timeout(condition), TASK_IDLE, timeout, __ret = schedule_timeout(__ret))
#define DEFINE_STATIC_KEY_FALSE(name) struct static_key_false name = STATIC_KEY_FALSE_INIT
#define ID_AA64PFR0_EL1_AdvSIMD_FP16 UL(0b0001)
#define ETH_P_802_EX1 0x88B5
#define CONFIG_IO_WQ 1
#define SCTLR_EL1_EnDA_WIDTH 1
#define ID_AA64AFR0_EL1_IMPDEF4_SHIFT 16
#define nmi_count() (preempt_count() & NMI_MASK)
#define ID_AA64PFR1_EL1_MTEX_WIDTH 4
#define PT_EVENT_FLAG(event) (1 << (PT_OPT_FLAG_SHIFT + (event)))
#define PACKET_VERSION 10
#define __NR_nfsservctl 42
#define HCR_TEA (UL(1) << 37)
#define EM_HEXAGON 164
#define TAINT_FORCED_MODULE 1
#define SHIFT_FLL 2
#define ID_AA64MMFR1_EL1_VH_IMP UL(0b0001)
#define CONFIG_NET_VENDOR_CHELSIO 1
#define USB_DEVICE_ID_MATCH_VENDOR 0x0001
#define __swait_event_timeout(wq,condition,timeout) ___swait_event(wq, ___wait_cond_timeout(condition), TASK_UNINTERRUPTIBLE, timeout, __ret = schedule_timeout(__ret))
#define spin_lock_irqsave(lock,flags) do { raw_spin_lock_irqsave(spinlock_check(lock), flags); } while (0)
#define ETH_TP_MDI_X 0x02
#define NT_LOONGARCH_LASX 0xa03
#define ID_AA64ISAR2_EL1_PAC_frac_WIDTH 4
#define HFGITR_EL2_ATS1E1RP GENMASK(16, 16)
#define __INT64_C(c) c ## L
#define SWAPPER_BLOCK_SIZE PMD_SIZE
#define HCR_ENSCXT (UL(1) << 53)
#define in_nmi() (nmi_count())
#define SOPASS_MAX 6
#define MDIO_PMA_CTRL2_TYPE 0x000f
#define __NR_prctl 167
#define CLONED_OFFSET offsetof(struct sk_buff, __cloned_offset)
#define SMPRIMAP_EL2_P6_MASK GENMASK(27, 24)
#define INPUT_DEVICE_ID_MATCH_PROPBIT 0x2000
#define HCRX_EL2_EnAS0_WIDTH 1
#define readw readw
#define PR_MCE_KILL_SET 1
#define I_DIO_WAKEUP (1 << __I_DIO_WAKEUP)
#define time_before_eq(a,b) time_after_eq(b,a)
#define arch_kasan_set_tag(addr,tag) __tag_set(addr, tag)
#define __NR_rt_sigpending 136
#define ID_AA64MMFR1_EL1_SpecSEI_WIDTH 4
#define TRBSR_EL1_EC_SHIFT 26
#define FLOW_DIS_CFM_MDL_MASK GENMASK(7, 5)
#define inline inline __gnu_inline __inline_maybe_unused notrace
#define upper_16_bits(n) ((u16)((n) >> 16))
#define MMF_DUMP_FILTER_BITS 9
#define ETHTOOL_COALESCE_RATE_SAMPLE_INTERVAL BIT(21)
#define AF_DECnet 12
#define OSLAR_EL1_OSLK_SHIFT 0
#define pte_alloc_map_lock(mm,pmd,address,ptlp) (pte_alloc(mm, pmd) ? NULL : pte_offset_map_lock(mm, pmd, address, ptlp))
#define LOREA_EL1_UNKN (UL(0))
#define HCR_TGE (UL(1) << 27)
#define PMSCR_EL2_TS_WIDTH 1
#define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
#define ID_ISAR4_EL1_SWP_frac_MASK GENMASK(31, 28)
#define __SO_ACCEPTCON (1 << 16)
#define JOBCTL_STOPPED_BIT 26
#define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
#define PSR_AA32_SSBS_BIT 0x00800000
#define DEFINE_FREE(_name,_type,_free) static inline void __free_ ##_name(void *p) { _type _T = *(_type *)p; _free; }
#define MDIO_PMA_STAT2_10GBER 0x0020
#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_SECT)
#define CONFIG_LLD_VERSION 0
#define ID_MMFR3_EL1_MaintBcst_SHIFT 12
#define S64_MAX ((s64)(U64_MAX >> 1))
#define ID_AA64DFR0_EL1_TraceVer_SIGNED false
#define ID_ISAR2_EL1_MultS_SMULL UL(0b0001)
#define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
#define MNT_MARKED 0x4000000
#define QC_FLAGS (1<<15)
#define LED_FUNCTION_TORCH "torch"
#define MDCCINT_EL1_TX_MASK GENMASK(29, 29)
#define __init_or_module __init
#define _LINUX_INTERVAL_TREE_H 
#define ID_DFR1_EL1_HPMN0_IMP UL(0b0001)
#define ID_AA64SMFR0_EL1_F32F32_WIDTH 1
#define ICH_VMCR_BPR0_SHIFT 21
#define U64_C(x) x ## ULL
#define EV_NONE 0
#define DEFAULT_FS_OVERFLOWUID 65534
#define ID_AA64MMFR2_EL1_IESB_SHIFT 12
#define page_ref_tracepoint_active(t) false
#define EADDRINUSE 98
#define CONFIG_SND_VERBOSE_PROCFS 1
#define S_IRWXO 00007
#define OFFT_OFFSET_MAX type_max(off_t)
#define ID_AA64MMFR1_EL1_HCX_SHIFT 40
#define CCSIDR_EL1_LineSize GENMASK(2, 0)
#define Op1_shift 16
#define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
#define MDIO_EEE_40GR_FW 0x0100
#define HFGxTR_EL2_AMAIR_EL1 GENMASK(3, 3)
#define MDSCR_EL1_SS GENMASK(0, 0)
#define SCXTNUM_EL1_SoftwareContextNumber GENMASK(63, 0)
#define __NR3264_ftruncate 46
#define si_addr _sifields._sigfault._addr
#define INPUT_DEVICE_ID_KEY_MAX 0x2ff
#define SCTLR_EL1_EPAN_SHIFT 57
#define FMODE_OPENED ((__force fmode_t)0x80000)
#define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
#define SCTLR_EL1_BT1_WIDTH 1
#define S_IFMT 00170000
#define MII_FCSCOUNTER 0x13
#define CLOCK_REALTIME 0
#define KUNIT_EXPECT_TRUE(test,condition) KUNIT_EXPECT_TRUE_MSG(test, condition, NULL)
#define WARN_RATELIMIT(condition,format,...) ({ static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); int rtn = !!(condition); if (unlikely(rtn && __ratelimit(&_rs))) WARN(rtn, format, ##__VA_ARGS__); rtn; })
#define FS_UNRM_FL 0x00000002
#define __FMODE_NONOTIFY ((__force int) FMODE_NONOTIFY)
#define STT_COMMON 5
#define cmpxchg(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_mb(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg(__ai_ptr, __VA_ARGS__); })
#define SO_LOCK_FILTER 44
#define MAX_DA_NAME_LEN 24
#define CONFIG_ARCH_SPARSEMEM_ENABLE 1
#define __ASM_VDSO_PROCESSOR_H 
#define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
#define ID_PFR0_EL1_State1_SIGNED false
#define ICH_HCR_EN (1 << 0)
#define COMPAT_HWCAP_HALF (1 << 1)
#define XA_FLAGS_LOCK_BH ((__force gfp_t)XA_LOCK_BH)
#define PTE_WRITE (PTE_DBM)
#define F_SETLKW64 14
#define TRBSR_EL1_IRQ_SHIFT 22
#define ID_AA64MMFR0_EL1_SNSMEM GENMASK(15, 12)
#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m)
#define __NR_fremovexattr 16
#define SYS_ID_MMFR2_EL1_CRn 0
#define MDSCR_EL1_HDE_SHIFT 14
#define ARM64_WORKAROUND_CLEAN_CACHE 91
#define DEVICE_ULONG_ATTR(_name,_mode,_var) struct dev_ext_attribute dev_attr_ ##_name = { __ATTR(_name, _mode, device_show_ulong, device_store_ulong), &(_var) }
#define CCSIDR_EL1_NumSets_WIDTH 15
#define pr_warn_once(fmt,...) printk_once(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__)
#define ID_PFR2_EL1_CSV3_WIDTH 4
#define NETLINK_ADD_MEMBERSHIP 1
#define __NR_process_vm_readv 270
#define ETHTOOL_COALESCE_RX_MAX_FRAMES BIT(1)
#define ____or(arg1_or_junk,y) __take_second_arg(arg1_or_junk 1, y)
#define BLKBSZSET _IOW(0x12,113,size_t)
#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
#define AH_ESP_V4_FLOW 0x04
#define ID_AA64ISAR1_EL1_GPA GENMASK(27, 24)
#define ID_AA64PFR0_EL1_EL2_MASK GENMASK(11, 8)
#define HDFGRTR_EL2_TRCOSLSR_WIDTH 1
#define SMPRIMAP_EL2_P8_SHIFT 32
#define REG_ID_MMFR0_EL1 S3_0_C0_C1_4
#define MNT_LOCK_READONLY 0x400000
#define pageblock_nr_pages (1UL << pageblock_order)
#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
#define static_key_disable_cpuslocked(k) static_key_disable((k))
#define ID_PFR1_EL1_GIC_NI UL(0b0000)
#define _LINUX_KASAN_ENABLED_H 
#define __irq_enter() do { preempt_count_add(HARDIRQ_OFFSET); lockdep_hardirq_enter(); account_hardirq_enter(current); } while (0)
#define ID_AA64ISAR0_EL1_RNDR_NI UL(0b0000)
#define readx_poll_timeout_atomic(op,addr,val,cond,delay_us,timeout_us) read_poll_timeout_atomic(op, val, cond, delay_us, timeout_us, false, addr)
#define _IOC_TYPECHECK(t) ((sizeof(t) == sizeof(t[1]) && sizeof(t) < (1 << _IOC_SIZEBITS)) ? sizeof(t) : __invalid_size_argument_for_IOC)
#define ARM64_HAS_EPAN 21
#define QUOTA_NL_IHARDBELOW 7
#define P4D_TABLE_PXN (_AT(p4dval_t, 1) << 59)
#define mas_for_each(__mas,__entry,__max) while (((__entry) = mas_find((__mas), (__max))) != NULL)
#define DCACHE_OP_REVALIDATE 0x00000004
#define REG_PMBLIMITR_EL1 S3_0_C9_C10_0
#define LPA_1000XHALF 0x0040
#define PT_TRACE_SECCOMP PT_EVENT_FLAG(PTRACE_EVENT_SECCOMP)
#define SYS_ID_DFR1_EL1_Op2 5
#define max3(x,y,z) max((typeof(x))max(x, y), z)
#define ETH_P_MOBITEX 0x0015
#define __REF .section ".ref.text", "ax"
#define HWCAP2_SVEPMULL (1 << 3)
#define DT_VERSYM 0x6ffffff0
#define SZ_256K 0x00040000
#define SZ_256M 0x10000000
#define MDIO_PMA_STAT2_10GBLW 0x0004
#define HFGxTR_EL2_AFSR1_EL1_MASK GENMASK(1, 1)
#define STATIC_KEY_INIT_FALSE { .enabled = ATOMIC_INIT(0) }
#define dma_mmap_coherent(d,v,c,h,s) dma_mmap_attrs(d, v, c, h, s, 0)
#define arch_spin_is_contended(l) queued_spin_is_contended(l)
#define SYS_CNTPOFF_EL2 sys_reg(3, 4, 14, 0, 6)
#define ID_PFR0_EL1_DIT_IMP UL(0b0001)
#define ETHTOOL_COALESCE_TX_MAX_FRAMES BIT(5)
#define ID_DFR1_EL1_HPMN0_MASK GENMASK(7, 4)
#define readq_relaxed readq_relaxed
#define BUS_OBJERR 3
#define ETH_MODULE_SFF_8472_LEN 512
#define AF_ATMPVC 8
#define IOPRIO_LEVEL_MASK (IOPRIO_NR_LEVELS - 1)
#define IPC_NOWAIT 00004000
#define DCACHE_ENTRY_TYPE 0x00700000
#define DQ_READ_B 4
#define EM_S390 22
#define PMBSR_EL1_COLL_WIDTH 1
#define MVFR1_EL1_UNKN (UL(0))
#define ID_MMFR4_EL1_AC2 GENMASK(7, 4)
#define ID_AA64ISAR0_EL1_SM3_WIDTH 4
#define ETHTOOL_COALESCE_TX_MAX_FRAMES_LOW BIT(15)
#define ESR_ELx_WNR_SHIFT (6)
#define USB_DEVICE_ID_MATCH_INT_NUMBER 0x0400
#define ID_AA64SMFR0_EL1_FA64_NI UL(0b0)
#define FMODE_BUF_WASYNC ((__force fmode_t)0x80000000)
#define HDFGRTR_EL2_UNKN (UL(0))
#define ID_AA64SMFR0_EL1_SMEver_SME2p1 UL(0b0010)
#define DT_FINI 13
#define ADVERTISE_10FULL 0x0040
#define HFGxTR_EL2_TPIDR_EL1_WIDTH 1
#define SEC_JIFFIE_SC (32 - SHIFT_HZ)
#define HDFGRTR_EL2_nBRBIDR_MASK GENMASK(59, 59)
#define ID_AA64MMFR1_EL1_TWED_NI UL(0b0000)
#define cap_raised(c,flag) (((c).val & BIT_ULL(flag)) != 0)
#define I_DIRTY_SYNC (1 << 0)
#define SHM_HUGE_256MB HUGETLB_FLAG_ENCODE_256MB
#define si_status _sifields._sigchld._status
#define local64_dec(l) local_dec(&(l)->a)
#define ESR_ELx_EC_CP15_64 (0x04)
#define HFGxTR_EL2_ERXFR_EL1_WIDTH 1
#define CAP_SYS_PACCT 20
#define PR_SET_MM_END_DATA 4
#define lockdep_softirqs_enabled(p) ((p)->softirqs_enabled)
#define compat_r9_fiq regs[25]
#define PTRACE_LISTEN 0x4208
#define PMBLIMITR_EL1_PMFZ GENMASK(5, 5)
#define __smp_store_release(p,v) do { typeof(p) __p = (p); union { __unqual_scalar_typeof(*p) __val; char __c[1]; } __u = { .__val = (__force __unqual_scalar_typeof(*p)) (v) }; compiletime_assert_atomic_type(*p); kasan_check_write(__p, sizeof(*p)); switch (sizeof(*p)) { case 1: asm volatile ("stlrb %w1, %0" : "=Q" (*__p) : "rZ" (*(__u8 *)__u.__c) : "memory"); break; case 2: asm volatile ("stlrh %w1, %0" : "=Q" (*__p) : "rZ" (*(__u16 *)__u.__c) : "memory"); break; case 4: asm volatile ("stlr %w1, %0" : "=Q" (*__p) : "rZ" (*(__u32 *)__u.__c) : "memory"); break; case 8: asm volatile ("stlr %x1, %0" : "=Q" (*__p) : "rZ" (*(__u64 *)__u.__c) : "memory"); break; } } while (0)
#define KERNEL_HWCAP_SME2P1 __khwcap2_feature(SME2P1)
#define REG_HDFGWTR_EL2 S3_4_C3_C1_5
#define __noinstr_section(section) noinline notrace __attribute((__section__(section))) __no_kcsan __no_sanitize_address __no_profile __no_sanitize_coverage __no_sanitize_memory
#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
#define CTR_EL0_L1Ip_MASK GENMASK(15, 14)
#define ID_AA64PFR1_EL1_RNDR_trap_NI UL(0b0000)
#define ID_MMFR3_EL1_PAN GENMASK(19, 16)
#define SZ_2K 0x00000800
#define hex_asc_upper_lo(x) hex_asc_upper[((x) & 0x0f)]
#define ID_AA64SMFR0_EL1_F64F64_IMP UL(0b1)
#define KERNFS_MAX_USER_XATTRS 128
#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a) - 1)) == 0)
#define __NR_lsetxattr 6
#define irq_alloc_domain_generic_chips(d,irqs_per_chip,num_ct,name,handler,clr,set,flags) ({ MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, handler, clr, set, flags); })
#define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
#define REG_TRBPTR_EL1 S3_0_C9_C11_1
#define SZ_2M 0x00200000
#define SS_DISABLE 2
#define HDFGWTR_EL2_DBGBCRn_EL1 GENMASK(0, 0)
#define DACR32_EL2_D0_MASK GENMASK(1, 0)
#define _LINUX_KASAN_CHECKS_H 
#define MDIO_PMA_EXTABLE_10BT 0x0100
#define ETH_HLEN 14
#define CONFIG_ARCH_WANTS_NO_INSTR 1
#define NETIF_F_HW_VLAN_STAG_FILTER __NETIF_F(HW_VLAN_STAG_FILTER)
#define ID_DFR0_EL1_MProfDbg GENMASK(23, 20)
#define PMD_MASK (~(PMD_SIZE-1))
#define AF_WANPIPE 25
#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
#define PMSIDR_EL1_INTERVAL_MASK GENMASK(11, 8)
#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
#define mp_bvec_iter_page(bvec,iter) (__bvec_iter_bvec((bvec), (iter))->bv_page)
#define pgprot_writecombine(prot) __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
#define pmdp_collapse_flush pmdp_collapse_flush
#define PR_SET_MM_START_CODE 1
#define __PMEV_op2(n) ((n) & 0x7)
#define ADVERTISED_FIBRE __ETHTOOL_LINK_MODE_LEGACY_MASK(FIBRE)
#define current_egid() (current_cred_xxx(egid))
#define FMODE_NOCMTIME ((__force fmode_t)0x800)
#define MDSCR_EL1_ERR_SHIFT 6
#define __NR_delete_module 106
#define HCR_TSC (UL(1) << 19)
#define __GFP_SKIP_ZERO ((__force gfp_t)___GFP_SKIP_ZERO)
#define ID_MMFR4_EL1_LSM_MASK GENMASK(23, 20)
#define ARCH_HAS_PREFETCHW 
#define __alias(symbol) __attribute__((__alias__(#symbol)))
#define ID_MMFR1_EL1_L1HvdVA_SHIFT 0
#define ID_AA64ZFR0_EL1_BitPerm_WIDTH 4
#define ZA_PT_ZA_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
#define HCR_TSW (UL(1) << 22)
#define _LINUX_SCATTERLIST_H 
#define virt_store_release(p,v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
#define _LINUX_ASSOC_ARRAY_H 
#define topology_die_id(cpu) ((void)(cpu), -1)
#define PR_CAP_AMBIENT_RAISE 2
#define PF_PPPOX AF_PPPOX
#define ID_MMFR0_EL1_VMSA_WIDTH 4
#define SB_I_IMA_UNVERIFIABLE_SIGNATURE 0x00000020
#define TCR2_EL1x_PTTWI_MASK GENMASK(10, 10)
#define IFF_PROMISC IFF_PROMISC
#define __NR_mount 40
#define CPTR_EL2_TCPAC (1U << 31)
#define __RWSEM_DEBUG_INIT(lockname) .magic = &lockname,
#define ETH_P_SNAP 0x0005
#define RADIX_TREE_MAP_MASK (RADIX_TREE_MAP_SIZE-1)
#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
#define ID_ISAR1_EL1_Jazelle_IMP UL(0b0001)
#define SIOCGIFPFLAGS 0x8935
#define SYS_CONTEXTIDR_EL12_Op0 3
#define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
#define IPV6_HOPLIMIT 52
#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
#define SYS_CONTEXTIDR_EL12_Op1 5
#define ID_ISAR1_EL1_Jazelle_SHIFT 28
#define ID_ISAR6_EL1_SB_SHIFT 12
#define MODULE_LICENSE(_license) MODULE_FILE MODULE_INFO(license, _license)
#define TRBIDR_EL1_EA_SERROR UL(0b0010)
#define HCR_TRVM (UL(1) << 30)
#define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
#define SIOCBRDELBR 0x89a1
#define ID_AA64PFR1_EL1_RAS_frac GENMASK(15, 12)
#define __WAIT_BIT_KEY_INITIALIZER(word,bit) { .flags = word, .bit_nr = bit, }
#define CONFIG_PACKET 1
#define hlist_for_each_safe(pos,n,head) for (pos = (head)->first; pos && ({ n = pos->next; 1; }); pos = n)
#define HDFGRTR_EL2_TRBSR_EL1_SHIFT 55
#define HFGxTR_EL2_SCXTNUM_EL0_WIDTH 1
#define CONFIG_CRYPTO_LIB_UTILS 1
#define SCTLR_EL1_SA_SHIFT 3
#define INIT_RLIMITS { [RLIMIT_CPU] = { RLIM_INFINITY, RLIM_INFINITY }, [RLIMIT_FSIZE] = { RLIM_INFINITY, RLIM_INFINITY }, [RLIMIT_DATA] = { RLIM_INFINITY, RLIM_INFINITY }, [RLIMIT_STACK] = { _STK_LIM, RLIM_INFINITY }, [RLIMIT_CORE] = { 0, RLIM_INFINITY }, [RLIMIT_RSS] = { RLIM_INFINITY, RLIM_INFINITY }, [RLIMIT_NPROC] = { 0, 0 }, [RLIMIT_NOFILE] = { INR_OPEN_CUR, INR_OPEN_MAX }, [RLIMIT_MEMLOCK] = { MLOCK_LIMIT, MLOCK_LIMIT }, [RLIMIT_AS] = { RLIM_INFINITY, RLIM_INFINITY }, [RLIMIT_LOCKS] = { RLIM_INFINITY, RLIM_INFINITY }, [RLIMIT_SIGPENDING] = { 0, 0 }, [RLIMIT_MSGQUEUE] = { MQ_BYTES_MAX, MQ_BYTES_MAX }, [RLIMIT_NICE] = { 0, 0 }, [RLIMIT_RTPRIO] = { 0, 0 }, [RLIMIT_RTTIME] = { RLIM_INFINITY, RLIM_INFINITY }, }
#define __GFP_DMA32 ((__force gfp_t)___GFP_DMA32)
#define CONFIG_CGROUP_PIDS 1
#define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
#define SIOCGIFCOUNT 0x8938
#define REG_ZCR_EL1 S3_0_C1_C2_0
#define NTP_INTERVAL_LENGTH (NSEC_PER_SEC/NTP_INTERVAL_FREQ)
#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
#define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
#define SCTLR_EL1_MSCEn_SHIFT 33
#define MDIO_PMA_STAT2_10GBSR 0x0080
#define ID_MMFR1_EL1_L1Hvd_NI UL(0b0000)
#define KUNIT_EXPECT_FALSE_MSG(test,condition,fmt,...) KUNIT_FALSE_MSG_ASSERTION(test, KUNIT_EXPECTATION, condition, fmt, ##__VA_ARGS__)
#define MDIO_PMA_STAT2_10GBSW 0x0008
#define ID_MMFR3_EL1_CMaintVA_IMP UL(0b0001)
#define PTRACE_POKETEXT 4
#define ___htonl(x) __cpu_to_be32(x)
#define KASAN_BRK_IMM 0x900
#define HFGxTR_EL2_LORSA_EL1_MASK GENMASK(23, 23)
#define CONFIG_DMA_OPS 1
#define POLL_STACK_ALLOC FRONTEND_STACK_ALLOC
#define CONFIG_PREEMPT_NONE_BUILD 1
#define IPC_OLD 0
#define FS_DIRSYNC_FL 0x00010000
#define DECLARE_WAIT_QUEUE_HEAD(name) struct wait_queue_head name = __WAIT_QUEUE_HEAD_INITIALIZER(name)
#define cmpxchg128_release(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_release(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg128_release(__ai_ptr, __VA_ARGS__); })
#define SYS_TRBTRG_EL1_CRm 11
#define SYS_TRBTRG_EL1_CRn 9
#define MAX_SKB_FRAGS CONFIG_MAX_SKB_FRAGS
#define SCTLR_EL1_DSSBS GENMASK(44, 44)
#define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d)
#define CONFIG_GENERIC_VDSO_TIME_NS 1
#define __ATTR_RW(_name) __ATTR(_name, 0644, _name ##_show, _name ##_store)
#define DCACHE_FALLTHRU 0x01000000
#define CONFIG_DMADEVICES_VDEBUG 1
#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
#define mm_forbids_zeropage(X) (0)
#define ID_PFR1_EL1_Virtualization_SIGNED false
#define SUPPORTED_Autoneg __ETHTOOL_LINK_MODE_LEGACY_MASK(Autoneg)
#define __DEBUG_MUTEX_INITIALIZER(lockname) , .magic = &lockname
#define __LINUX_BVEC_H 
#define HCR_TWI (UL(1) << 13)
#define CONFIG_SERIO 1
#define CONFIG_STACKTRACE 1
#define REG_TRBIDR_EL1 S3_0_C9_C11_7
#define HDFGWTR_EL2_PMCNTEN_SHIFT 16
#define CONFIG_HAVE_MOD_ARCH_SPECIFIC 1
#define PSR_AA32_MODE_HYP 0x0000001a
#define rcu_dereference_bh_check(p,c) __rcu_dereference_check((p), __UNIQUE_ID(rcu), (c) || rcu_read_lock_bh_held(), __rcu)
#define NT_ARM_PACA_KEYS 0x407
#define DECLARE_DELAYED_WORK(n,f) struct delayed_work n = __DELAYED_WORK_INITIALIZER(n, f, 0)
#define MPIDR_AFFINITY_LEVEL(mpidr,level) ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
#define MIGHT_RESCHED_RCU_SHIFT 8
#define CONFIG_ARM_ARCH_TIMER 1
#define IORESOURCE_DMA_8BIT (0<<0)
#define WARN_ONCE(condition,format...) DO_ONCE_LITE_IF(condition, WARN, 1, format)
#define DEFINE_MRS_S __DEFINE_ASM_GPR_NUMS "	.macro	mrs_s, rt, sreg\n" __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) "	.endm\n"
#define PTRACE_POKEMTETAGS 34
#define module_param_call(name,_set,_get,arg,perm) static const struct kernel_param_ops __param_ops_ ##name = { .flags = 0, .set = _set, .get = _get }; __module_param_call(MODULE_PARAM_PREFIX, name, &__param_ops_ ##name, arg, perm, -1, 0)
#define SO_ACCEPTCONN 30
#define HCR_DC (UL(1) << 12)
#define ETHTOOL_SCHANNELS 0x0000003d
#define HDFGRTR_EL2_TRBTRG_EL1_SHIFT 56
#define SCTLR_EL1_TWEDEL_MASK GENMASK(49, 46)
#define _UAPI_LINUX_STRING_H_ 
#define __no_caller_saved_registers 
#define personality(pers) (pers & PER_MASK)
#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
#define HFGxTR_EL2_ISR_EL1 GENMASK(18, 18)
#define __LITTLE_ENDIAN_BITFIELD 
#define HUGETLB_FLAG_ENCODE_8MB (23U << HUGETLB_FLAG_ENCODE_SHIFT)
#define __ASM_THREAD_INFO_H 
#define TAINT_BAD_PAGE 5
#define R_AARCH64_MOVW_PREL_G1_NC 290
#define flowi_scope u.__fl_common.flowic_scope
#define FWLINK_FLAG_CYCLE BIT(0)
#define NL_REQ_ATTR_CHECK(extack,nest,tb,type) ({ struct nlattr **__tb = (tb); u32 __attr = (type); int __retval; __retval = !__tb[__attr]; if (__retval) NL_SET_ERR_ATTR_MISS((extack), (nest), __attr); __retval; })
#define PR_ENDIAN_LITTLE 1
#define ID_AA64ISAR0_EL1_FHM_MASK GENMASK(51, 48)
#define CPU_STUCK_REASON_52_BIT_VA (UL(1) << CPU_STUCK_REASON_SHIFT)
#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
#define SO_RESERVE_MEM 73
#define this_cpu_sub(pcp,val) this_cpu_add(pcp, -(typeof(pcp))(val))
#define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
#define SVE_PT_VL_ONEXEC ((1 << 18) >> 16)
#define CTR_EL0_L1Ip_RESERVED UL(0b01)
#define _DECLARE_STATIC_KEY_0(name) DECLARE_STATIC_KEY_FALSE(name)
#define _DECLARE_STATIC_KEY_1(name) DECLARE_STATIC_KEY_TRUE(name)
#define raw_seqcount_begin(s) ({ raw_read_seqcount(s) & ~1; })
#define VTCR_EL2_T0SZ_MASK 0x3f
#define sysreg_clear_set(sysreg,clear,set) do { u64 __scs_val = read_sysreg(sysreg); u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); if (__scs_new != __scs_val) write_sysreg(__scs_new, sysreg); } while (0)
#define CONFIG_ARCH_DMA_ADDR_T_64BIT 1
#define ACL_DONT_CACHE ((void *)(-3))
#define cond_syscall(x) asm( ".weak " __stringify(x) "\n\t" ".set  " __stringify(x) "," __stringify(sys_ni_syscall))
#define HPAGE_PMD_SHIFT ({ BUILD_BUG(); 0; })
#define ICH_HCR_TC (1 << 10)
#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
#define __NR_syslog 116
#define ETHTOOL_GRXCLSRULE 0x0000002f
#define IPC_EXCL 00002000
#define dereference_kernel_function_descriptor(p) ((void *)(p))
#define VM_DONTEXPAND 0x00040000
#define SYS_ID_MMFR0_EL1_Op0 3
#define SYS_ID_MMFR0_EL1_Op1 0
#define SYS_ID_MMFR0_EL1_Op2 4
#define PR_SET_MM_AUXV 12
#define ID_MMFR1_EL1_UNKN (UL(0))
#define MSG_INTERNAL_SENDMSG_FLAGS (MSG_SPLICE_PAGES | MSG_SENDPAGE_NOPOLICY | MSG_SENDPAGE_DECRYPTED)
#define HWCAP2_AFP (1 << 20)
#define NWAYTEST_RESV2 0xfe00
#define SYS_SMIDR_EL1_CRm 0
#define SYS_SMIDR_EL1_CRn 0
#define task_ucounts(task) (task_cred_xxx((task), ucounts))
#define SYS_ID_PFR0_EL1_Op0 3
#define SYS_ID_PFR0_EL1_Op1 0
#define SYS_ID_PFR0_EL1_Op2 0
#define ID_AA64ISAR2_EL1_MOPS_IMP UL(0b0001)
#define ID_MMFR0_EL1_TCM_TCM_DMA UL(0b0011)
#define ID_AA64ISAR0_EL1_AES_SIGNED false
#define ID_MMFR0_EL1_InnerShr_WIDTH 4
#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
#define CONFIG_LZ4_DECOMPRESS 1
#define HFGxTR_EL2_LORID_EL1_WIDTH 1
#define _LINUX_CAPABILITY_VERSION_1 0x19980330
#define ID_AA64ISAR0_EL1_DP_WIDTH 4
#define ID_AA64PFR1_EL1_RAS_frac_MASK GENMASK(15, 12)
#define HFGITR_EL2_ERET GENMASK(51, 51)
#define BMSR_100FULL 0x4000
#define ID_AA64ISAR0_EL1_SHA3_NI UL(0b0000)
#define ID_DFR1_EL1_RES1 (UL(0))
#define F_DUPFD 0
#define ID_AA64DFR0_EL1_PMSVer GENMASK(35, 32)
#define hash_64 hash_64_generic
#define CONFIG_DECOMPRESS_GZIP 1
#define SS_AUTODISARM (1U << 31)
#define EARLY_PUDS(vstart,vend,add) (0)
#define SYS_TRBPTR_EL1_CRm 11
#define SYS_TRBPTR_EL1_CRn 9
#define S_VERITY (1 << 16)
#define __NR_close 57
#define HFGxTR_EL2_TPIDRRO_EL0_WIDTH 1
#define PMSICR_EL1_ECOUNT_MASK GENMASK(63, 56)
#define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT))
#define MVFR2_EL1_FPMisc_FP UL(0b0001)
#define HDFGRTR_EL2_TRCOSLSR_MASK GENMASK(43, 43)
#define DCZID_EL0_UNKN (UL(0))
#define ID_PFR1_EL1_Security GENMASK(7, 4)
#define TRBBASER_EL1_BASE GENMASK(63, 12)
#define ID_AA64MMFR3_EL1_TCRX GENMASK(3, 0)
#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 8
#define PMSIDR_EL1_COUNTSIZE_SHIFT 16
#define KERNEL_HWCAP_SME_F64F64 __khwcap2_feature(SME_F64F64)
#define ID_PFR2_EL1_SSBS_SHIFT 4
#define MVFR0_EL1_FPSP_MASK GENMASK(7, 4)
#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
#define __HDFGRTR_EL2_nMASK GENMASK(62, 59)
#define SYS_ALLINT_Op1 0
#define SYS_ALLINT_Op2 0
#define ID_ISAR0_EL1_BitCount_NI UL(0b0000)
#define OSECCR_EL1_EDECCR GENMASK(31, 0)
#define AF_ASH 18
#define _SSIZE_T 
#define PSTATE_SSBS pstate_field(3, 1)
#define write_seqlock_irqsave(lock,flags) do { flags = __write_seqlock_irqsave(lock); } while (0)
#define ID_PFR1_EL1_GenTimer_SHIFT 16
#define ID_PFR1_EL1_GenTimer_NI UL(0b0000)
#define FPSIMD_MAGIC 0x46508001
#define ID_AA64MMFR3_EL1_SCTLRX_IMP UL(0b0001)
#define HSIPHASH_CONST_3 0x74656462U
#define HFGxTR_EL2_ERXPFGCDN_EL1 GENMASK(48, 48)
#define SMPRIMAP_EL2_F9_WIDTH 4
#define __NR_futex_wake 454
#define PR_MTE_TCF_SYNC (1UL << 1)
#define ID_ISAR3_EL1_SynchPrim_NI UL(0b0000)
#define ID_ISAR0_EL1_Debug_IMP UL(0b0001)
#define ARM64_WORKAROUND_2645198 79
#define CONFIG_ELFCORE 1
#define ID_AA64ISAR2_EL1_BC_NI UL(0b0000)
#define PR_SET_THP_DISABLE 41
#define PMBSR_EL1_MSS_MASK GENMASK(15, 0)
#define FS_DQ_ISOFT (1<<0)
#define MVFR1_EL1_SIMDLS_MASK GENMASK(11, 8)
#define ID_AA64ISAR1_EL1_DPB_DPB2 UL(0b0010)
#define ID_DFR1_EL1_MTPMU_SHIFT 0
#define NR_LOCKDEP_CACHING_CLASSES 2
#define _Q_TAIL_CPU_OFFSET (_Q_TAIL_IDX_OFFSET + _Q_TAIL_IDX_BITS)
#define SUPPORTED_40000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseCR4_Full)
#define ADJ_MICRO 0x1000
#define sym_to_pfn(x) __phys_to_pfn(__pa_symbol(x))
#define CTR_EL0_UNKN (UL(0))
#define CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 1
#define DEVICE_ATTR_PREALLOC(_name,_mode,_show,_store) struct device_attribute dev_attr_ ##_name = __ATTR_PREALLOC(_name, _mode, _show, _store)
#define raw_cmpxchg128 arch_cmpxchg128
#define ID_ISAR0_EL1_Divide_WIDTH 4
#define __UAPI_DEF_IF_IFNAMSIZ 1
#define phys_to_ttbr(addr) (addr)
#define ID_AA64ZFR0_EL1_BitPerm_IMP UL(0b0001)
#define DBG_ARCH_ID_RESERVED 0
#define DACR32_EL2_D13_SHIFT 26
#define VM_FLAGS_CLEAR (ARCH_VM_PKEY_FLAGS | VM_ARCH_CLEAR)
#define local_unlock(lock) __local_unlock(lock)
#define DCACHE_COOKIE 0x00002000
#define PR_CAP_AMBIENT_IS_SET 1
#define IPV6_TLV_PAD1 0
#define MDSCR_EL1_EMBWE_WIDTH 1
#define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
#define __attribute_const__ __attribute__((__const__))
#define __atomic_op_fence(op,args...) ({ typeof(op ##_relaxed(args)) __ret; __atomic_pre_full_fence(); __ret = op ##_relaxed(args); __atomic_post_full_fence(); __ret; })
#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
#define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long))
#define __LINUX_FIND_H_ 
#define __NR_capset 91
#define ARCH_KMALLOC_MINALIGN (8)
#define FLOW_DIS_ENCAPSULATION BIT(2)
#define STRUCT_PAGE_MAX_SHIFT (order_base_2(sizeof(struct page)))
#define SKB_BF_MONO_TC_OFFSET offsetof(struct sk_buff, __mono_tc_offset)
#define NOMMU_MAP_DIRECT 0x00000008
#define MDIO_AN_STAT1_LPABLE 0x0001
#define LPA_1000REMRXOK 0x1000
#define REG_PMSLATFR_EL1 S3_0_C9_C9_6
#define REG_CPACR_EL12 S3_5_C1_C0_2
#define ID_AA64MMFR0_EL1_ASIDBITS_16 UL(0b0010)
#define HFGITR_EL2_ATS1E0W_SHIFT 15
#define DACR32_EL2_D2_WIDTH 2
#define PACKET_OUTGOING 4
#define ID_MMFR0_EL1_AuxReg_MASK GENMASK(23, 20)
#define ID_AA64ZFR0_EL1_B16B16_NI UL(0b0000)
#define aligned_le64 __aligned_le64
#define BLKGETDISKSEQ _IOR(0x12,128,__u64)
#define _ASM_ARM64_FIXMAP_H 
#define ID_ISAR5_EL1_AES_SIGNED false
#define SUBSECTIONS_PER_SECTION (1UL << (SECTION_SIZE_BITS - SUBSECTION_SHIFT))
#define ID_MMFR2_EL1_HWAccFlg_WIDTH 4
#define ethtool_link_ksettings_del_link_mode(ptr,name,mode) __clear_bit(ETHTOOL_LINK_MODE_ ## mode ## _BIT, (ptr)->link_modes.name)
#define ID_AA64ISAR2_EL1_CSSC_WIDTH 4
#define __xchg_wrapper(sfx,ptr,x) ({ __typeof__(*(ptr)) __ret; __ret = (__typeof__(*(ptr))) __arch_xchg ##sfx((unsigned long)(x), (ptr), sizeof(*(ptr))); __ret; })
#define LPA_PAUSE_CAP 0x0400
#define FS_COMPRBLK_FL 0x00000200
#define CLIDR_EL1_LoC GENMASK(26, 24)
#define ID_ISAR5_EL1_AES_VMULL UL(0b0010)
#define ID_MMFR3_EL1_BPMaint_WIDTH 4
#define IPX_TYPE 1
#define CONFIG_RWSEM_SPIN_ON_OWNER 1
#define ID_AA64ISAR0_EL1_DP_NI UL(0b0000)
#define PIRx_ELx_Perm2_SHIFT 8
#define swab __swab
#define swait_event_idle_exclusive(wq,condition) do { if (condition) break; __swait_event_idle(wq, condition); } while (0)
#define REG_LOREA_EL1 S3_0_C10_C4_1
#define SCTLR_EL1_UCT_WIDTH 1
#define kvfree_rcu_arg_1(ptr) do { typeof(ptr) ___p = (ptr); if (___p) kvfree_call_rcu(NULL, (void *) (___p)); } while (0)
#define swap(a,b) do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
#define HCR_TIDCP (UL(1) << 20)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define ID_AA64ISAR1_EL1_LRCPC_LRCPC3 UL(0b0011)
#define _LINUX_UIDGID_H 
#define ID_MMFR2_EL1_MemBarr_WIDTH 4
#define ktime_to_timespec64(kt) ns_to_timespec64((kt))
#define might_lock(lock) do { typecheck(struct lockdep_map *, &(lock)->dep_map); lock_acquire(&(lock)->dep_map, 0, 0, 0, 1, NULL, _THIS_IP_); lock_release(&(lock)->dep_map, _THIS_IP_); } while (0)
#define STATIC_CALL_SITE_TAIL 1UL
#define ILL_BADSTK 8
#define ID_MMFR1_EL1_BPred_BP_NOSNOOP UL(0b0011)
#define ID_AA64DFR0_EL1_CTX_CMPs GENMASK(31, 28)
#define TOPOLOGY_CLUSTER_SYSFS 
#define CONFIG_WLAN_VENDOR_ST 1
#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
#define EM_XTENSA 94
#define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
#define __CONCAT(a,b) a ## b
#define CONFIG_INET_DIAG 1
#define ETHTOOL_BUSINFO_LEN 32
#define CPACR_ELx_SMEN_MASK GENMASK(25, 24)
#define SYS_TCR2_EL2_CRm 0
#define SYS_TCR2_EL2_CRn 2
#define wait_event_interruptible_locked_irq(wq,condition) ((condition) ? 0 : __wait_event_interruptible_locked(wq, condition, 0, do_wait_intr_irq))
#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
#define EPOLLHUP (__force __poll_t)0x00000010
#define AT_NOTELF 10
#define SMPRIMAP_EL2_P11_WIDTH 4
#define CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL 1
#define CONFIG_WLAN_VENDOR_TI 1
#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
#define HFGxTR_EL2_DCZID_EL0_MASK GENMASK(15, 15)
#define SOL_IPV6 41
#define MDIO_DEVICE_FLAG_PHY 1
#define __nonstring __attribute__((__nonstring__))
#define ID_AA64ISAR0_EL1_AES_AES UL(0b0001)
#define HDFGRTR_EL2_PMBSR_EL1_WIDTH 1
#define ID_AA64MMFR1_EL1_HPDS_HPDS2 UL(0b0010)
#define first_node(src) __first_node(&(src))
#define flowi_tos u.__fl_common.flowic_tos
#define CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK 1
#define __maybe_unused __attribute__((__unused__))
#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
#define DRIVER_ATTR_RO(_name) struct driver_attribute driver_attr_ ##_name = __ATTR_RO(_name)
#define HCRX_EL2_TCR2En GENMASK(14, 14)
#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
#define __SEQ_RT IS_ENABLED(CONFIG_PREEMPT_RT)
#define ID_DFR0_EL1_CopTrc GENMASK(15, 12)
#define ID_MMFR0_EL1_TCM_NI UL(0b0000)
#define __cmp(op,x,y) ((x) __cmp_op_ ##op (y) ? (x) : (y))
#define KUNIT_BINARY_PTR_ASSERTION(test,assert_type,left,op,right,fmt,...) KUNIT_BASE_BINARY_ASSERTION(test, kunit_binary_ptr_assert, kunit_binary_ptr_assert_format, assert_type, left, op, right, fmt, ##__VA_ARGS__)
#define PMBLIMITR_EL1_UNKN (UL(0))
#define _NET_FLOW_DISSECTOR_H 
#define GOLDEN_RATIO_32 0x61C88647
#define __NR_unlinkat 35
#define le16_to_cpu __le16_to_cpu
#define ARM64_VECTOR_TABLE_LEN SZ_2K
#define TCR_ASID16 (UL(1) << 36)
#define MVFR2_EL1_FPMisc_NI UL(0b0000)
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 
#define HDFGWTR_EL2_PMBPTR_EL1_WIDTH 1
#define MSG_CTRUNC 8
#define __NR_pivot_root 41
#define DBG_ESR_EVT_HWWP 0x2
#define HWCAP2_SME_B16F32 (1 << 28)
#define QC_INO_TIMER (1<<7)
#define _LINUX_FS_H 
#define ID_AA64SMFR0_EL1_SMEver_MASK GENMASK(59, 56)
#define ID_MMFR5_EL1_ETS_WIDTH 4
#define __NR_socketpair 199
#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
#define VM_ALLOC 0x00000002
#define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
#define U8_C(x) x ## U
#define COMPAT_SYSCALL_DEFINE0(name) asmlinkage long compat_sys_ ##name(void); ALLOW_ERROR_INJECTION(compat_sys_ ##name, ERRNO); asmlinkage long compat_sys_ ##name(void)
#define COMPAT_SYSCALL_DEFINE2(name,...) COMPAT_SYSCALL_DEFINEx(2, _ ##name, __VA_ARGS__)
#define COMPAT_SYSCALL_DEFINE4(name,...) COMPAT_SYSCALL_DEFINEx(4, _ ##name, __VA_ARGS__)
#define CONFIG_INIT_STACK_NONE 1
#define COMPAT_SYSCALL_DEFINE6(name,...) COMPAT_SYSCALL_DEFINEx(6, _ ##name, __VA_ARGS__)
#define REG_MVFR1_EL1 S3_0_C0_C3_1
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK)
#define AF_UNSPEC 0
#define MDIO_PMA_LASI_CTRL 0x9002
#define ETH_TP_MDI 0x01
#define HWCAP2_DCPODP (1 << 0)
#define FIXMAP_PAGE_NOCACHE PAGE_KERNEL_NOCACHE
#define L1_CACHE_SHIFT (6)
#define flowi4_proto __fl_common.flowic_proto
#define le16_to_cpup __le16_to_cpup
#define le16_to_cpus __le16_to_cpus
#define STATX_DIOALIGN 0x00002000U
#define ID_AA64MMFR1_EL1_TWED_MASK GENMASK(35, 32)
#define FS_DQ_ACCT_MASK (FS_DQ_BCOUNT | FS_DQ_ICOUNT | FS_DQ_RTBCOUNT)
#define ID_MMFR1_EL1_L1Uni_NI UL(0b0000)
#define MDSCR_EL1_INTdis_SHIFT 22
#define FS_USER_QUOTA (1<<0)
#define TIMER_PINNED 0x00100000
#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
#define SYS_AM_EL0(crm,op2) sys_reg(3, 3, 13, (crm), (op2))
#define CNTPOFF_EL2_PhysicalOffset GENMASK(63, 0)
#define ID_ISAR5_EL1_CRC32_SIGNED false
#define ID_AA64SMFR0_EL1_FA64 GENMASK(63, 63)
#define PR_SME_SET_VL 63
#define ID_MMFR2_EL1_MemBarr_IMP UL(0b0010)
#define HFGxTR_EL2_nSMPRI_EL1_WIDTH 1
#define ID_DFR0_EL1_CopSDbg_SHIFT 4
#define REG_TPIDR_EL1 S3_0_C13_C0_4
#define EM_ALTERA_NIOS2 113
#define HUGETLB_FLAG_ENCODE_16MB (24U << HUGETLB_FLAG_ENCODE_SHIFT)
#define lockdep_depth(tsk) (debug_locks ? (tsk)->lockdep_depth : 0)
#define CONFIG_HAVE_FUNCTION_TRACER 1
#define ID_MMFR5_EL1_nTLBPA_SIGNED false
#define sysfs_attr_init(attr) do { static struct lock_class_key __key; (attr)->key = &__key; } while (0)
#define HDFGRTR_EL2_PMSIDR_EL1_WIDTH 1
#define try_cmpxchg_acquire(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg_acquire(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define __meminitdata __section(".meminit.data")
#define __IRQ_MASK(x) ((1UL << (x))-1)
#define GOLDEN_RATIO_64 0x61C8864680B583EBull
#define IPV6_PRIORITY_UNCHARACTERIZED 0x0000
#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
#define __ASM_STACK_POINTER_H 
#define ID_AA64ISAR0_EL1_CRC32_WIDTH 4
#define IORESOURCE_BUSY 0x80000000
#define HFGxTR_EL2_CLIDR_EL1_WIDTH 1
#define pud_index pud_index
#define CTR_EL0_DminLine_WIDTH 4
#define wait_event_idle_exclusive_timeout(wq_head,condition,timeout) ({ long __ret = timeout; might_sleep(); if (!___wait_cond_timeout(condition)) __ret = __wait_event_idle_exclusive_timeout(wq_head, condition, timeout); __ret; })
#define _UAPI__LINUX_NETLINK_H 
#define thp_get_unmapped_area NULL
#define HFGITR_EL2_DCIVAC_SHIFT 3
#define HFGxTR_EL2_nGCS_EL0 GENMASK(52, 52)
#define HFGxTR_EL2_nGCS_EL1 GENMASK(53, 53)
#define ID_AA64SMFR0_EL1_F64F64_SIGNED false
#define AF_SECURITY 14
#define PMBSR_EL1_COLL GENMASK(16, 16)
#define HW_ERR "[Hardware Error]: "
#define STA_PPSTIME 0x0004
#define ID_AA64ISAR0_EL1_SM3 GENMASK(39, 36)
#define ID_AA64ISAR0_EL1_SM4 GENMASK(43, 40)
#define si_perf_flags _sifields._sigfault._perf._flags
#define __TASK_FREEZABLE_UNSAFE (0x00004000 * IS_ENABLED(CONFIG_LOCKDEP))
#define NT_MIPS_MSA 0x802
#define CONFIG_DEBUG_KERNEL 1
#define TRBLIMITR_EL1_nVM_SHIFT 5
#define PMSFCR_EL1_FnE GENMASK(3, 3)
#define FSLABEL_MAX 256
#define write_unlock_bh(lock) _raw_write_unlock_bh(lock)
#define wait_event_lock_irq_cmd(wq_head,condition,lock,cmd) do { if (condition) break; __wait_event_lock_irq(wq_head, condition, lock, cmd); } while (0)
#define SI_QUEUE -1
#define REMAP_FILE_ADVISORY (REMAP_FILE_CAN_SHORTEN)
#define ID_MMFR0_EL1_ShareLvl GENMASK(15, 12)
#define SYS_ZCR_EL2_Op1 4
#define CONSOLE_LOGLEVEL_MIN 1
#define SRCU_SIZE_WAIT_CBS1 4
#define SRCU_SIZE_WAIT_CBS2 5
#define SRCU_SIZE_WAIT_CBS3 6
#define SRCU_SIZE_WAIT_CBS4 7
#define PR_TASK_PERF_EVENTS_DISABLE 31
#define CONFIG_HAVE_PCI 1
#define FMODE_ATOMIC_POS ((__force fmode_t)0x8000)
#define HDFGRTR_EL2_PMSLATFR_EL1 GENMASK(32, 32)
#define ETH_P_IEEE802154 0x00F6
#define ID_AA64MMFR3_EL1_S1PIE_IMP UL(0b0001)
#define _HAVE_ARCH_IPV6_CSUM 
#define ETH_P_SLOW 0x8809
#define ID_PFR1_EL1_MProgMod_SHIFT 8
#define CONFIG_GENERIC_PCI_IOMAP 1
#define SO_PEERSEC 31
#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
#define ID_AA64PFR1_EL1_RNDR_trap_SHIFT 28
#define WORK_OFFQ_CANCELING (1ul << __WORK_OFFQ_CANCELING)
#define __raw_readb __raw_readb
#define CONFIG_POSIX_CPU_TIMERS_TASK_WORK 1
#define HFGITR_EL2_COSPRCTX_SHIFT 60
#define MDIO_AN_10GBT_STAT 33
#define ID_AA64DFR0_EL1_PMSVer_V1P1 UL(0b0010)
#define ID_AA64DFR0_EL1_PMSVer_V1P3 UL(0b0100)
#define S_DAX 0
#define CONFIG_SAMPLES 1
#define ID_AA64PFR0_EL1_EL1_SIGNED false
#define SUBSECTION_ALIGN_UP(pfn) ALIGN((pfn), PAGES_PER_SUBSECTION)
#define SCTLR_ELx_SA (BIT(3))
#define PMBIDR_EL1_P_SHIFT 4
#define TPACKET_ALIGN(x) (((x)+TPACKET_ALIGNMENT-1)&~(TPACKET_ALIGNMENT-1))
#define ID_MMFR2_EL1_L1HvdFG_SHIFT 0
#define compat_lr_irq regs[16]
#define ID_AA64PFR0_EL1_RAS_NI UL(0b0000)
#define is_negative(a) (!(is_non_negative(a)))
#define ID_AA64PFR0_EL1_EL3_MASK GENMASK(15, 12)
#define ktime_sub_ns(kt,nsval) ((kt) - (nsval))
#define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
#define CLONE_NEWNS 0x00020000
#define REG_CCSIDR_EL1 S3_1_C0_C0_0
#define ID_MMFR3_EL1_PAN_SHIFT 16
#define __LINUX_DEBUG_LOCKING_H 
#define NETIF_F_ETHTOOL_BITS ((__NETIF_F_BIT(NETDEV_FEATURE_COUNT - 1) | (__NETIF_F_BIT(NETDEV_FEATURE_COUNT - 1) - 1)) & ~NETIF_F_NEVER_CHANGE)
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
#define __tag_get(addr) 0
#define VMALLOC_TOTAL (VMALLOC_END - VMALLOC_START)
#define TP_STATUS_TS_SYS_HARDWARE (1 << 30)
#define raw_spin_unlock_bh(lock) _raw_spin_unlock_bh(lock)
#define CONFIG_BINDGEN_VERSION_TEXT "bindgen 0.65.1"
#define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT)
#define HWCAP2_SVE2 (1 << 1)
#define ID_MMFR2_EL1_HWAccFlg_MASK GENMASK(31, 28)
#define ETH_P_DEC 0x6000
#define __ASM_DEVICE_H 
#define for_each_migratetype_order(order,type) for (order = 0; order <= MAX_ORDER; order++) for (type = 0; type < MIGRATE_TYPES; type++)
#define ETHTOOL_SRXCSUM 0x00000015
#define Elf_Addr Elf64_Addr
#define SHN_LIVEPATCH 0xff20
#define CTR_EL0_TminLine_SHIFT 32
#define list_prev_entry(pos,member) list_entry((pos)->member.prev, typeof(*(pos)), member)
#define CONFIG_MESSAGE_LOGLEVEL_DEFAULT 4
#define NETIF_F_GSO_SOFTWARE (NETIF_F_ALL_TSO | NETIF_F_GSO_SCTP | NETIF_F_GSO_UDP_L4 | NETIF_F_GSO_FRAGLIST)
#define RCU_LOCKDEP_WARN(c,s) do { static bool __section(".data.unlikely") __warned; if (debug_lockdep_rcu_enabled() && (c) && debug_lockdep_rcu_enabled() && !__warned) { __warned = true; lockdep_rcu_suspicious(__FILE__, __LINE__, s); } } while (0)
#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
#define ID_AA64PFR1_EL1_THE_NI UL(0b0000)
#define S64_C(x) x ## LL
#define CLONE_SIGHAND 0x00000800
#define IORESOURCE_ROM_ENABLE (1<<0)
#define FS_DQ_WARNS_MASK (FS_DQ_BWARNS | FS_DQ_IWARNS | FS_DQ_RTBWARNS)
#define ENOSYS 38
#define MIDR_PARTNUM(midr) (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
#define TCR2_EL2_AMEC0_MASK GENMASK(12, 12)
#define ETHTOOL_COALESCE_RX_USECS BIT(0)
#define CONFIG_BCMA_POSSIBLE 1
#define EPIPE 32
#define CONFIG_HAVE_ARCH_KCSAN 1
#define PT_SHLIB 5
#define MVFR1_EL1_SIMDFMAC GENMASK(31, 28)
#define this_cpu_try_cmpxchg128(pcp,ovalp,nval) __cpu_fallback_try_cmpxchg(pcp, ovalp, nval, this_cpu_cmpxchg128)
#define PM_SCAN_WP_MATCHING (1 << 0)
#define SCTLR_EL1_EnIB_MASK GENMASK(30, 30)
#define HDFGWTR_EL2_DBGBVRn_EL1_WIDTH 1
#define ESR_ELx_ISV_SHIFT (24)
#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H 
#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK
#define CONFIG_AMPERE_ERRATUM_AC03_CPU_38 1
#define PTRACE_EVENT_VFORK 2
#define PTRACE_GETSIGINFO 0x4202
#define flush_dcache_folio flush_dcache_folio
#define GFP_USER (__GFP_RECLAIM | __GFP_IO | __GFP_FS | __GFP_HARDWALL)
#define SECCOMP_FILTER_FLAG_WAIT_KILLABLE_RECV (1UL << 5)
#define readl_relaxed readl_relaxed
#define HFGxTR_EL2_CONTEXTIDR_EL1_WIDTH 1
#define ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
#define __FD_SETSIZE 1024
#define _LINUX_ERRNO_H 
#define ARM64_ALWAYS_BOOT 0
#define __NR_rt_sigreturn 139
#define NSEC_PER_USEC 1000L
#define FIXADDR_TOT_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define SYS_ID_MMFR2_EL1_CRm 1
#define SCTLR_EL1_nTLSMD_SHIFT 28
#define PTRACE_EVENTMSG_SYSCALL_EXIT 2
#define ESR_ELx_EC_WIDTH (6)
#define ALLINT_ALLINT GENMASK(13, 13)
#define USEC_TO_HZ_ADJ32 U64_C(0x7FF7CED9168)
#define ID_ISAR3_EL1_SynchPrim_WIDTH 4
#define MVFR1_EL1_SIMDInt_SHIFT 12
#define SYS_TPIDR_EL1_Op0 3
#define SYS_TPIDR_EL1_Op1 0
#define SYS_TPIDR_EL1_Op2 4
#define _LINUX_TRACE_RECURSION_H 
#define CONFIG_SYSCTL 1
#define CONFIG_I2C_COMPAT 1
#define NVHE_STACKTRACE_SIZE ((OVERFLOW_STACK_SIZE + PAGE_SIZE) / 2 + sizeof(long))
#define SYS_ID_PFR2_EL1_CRm 3
#define SYS_ID_PFR2_EL1_CRn 0
#define HFGxTR_EL2_AFSR1_EL1_WIDTH 1
#define __diag_str1(s) #s
#define CONFIG_GPIO_CDEV 1
#define SI_USER 0
#define R_AARCH64_LDST16_ABS_LO12_NC 284
#define CONFIG_PM_GENERIC_DOMAINS 1
#define HDFGWTR_EL2_DBGWVRn_EL1_WIDTH 1
#define SIOCGIFBR 0x8940
#define LPA_1000XPAUSE_ASYM 0x0100
#define arch_has_block_step() (0)
#define _LINUX_KASAN_TAGS_H 
#define CONFIG_ARM64_ERRATUM_2966298 1
#define CONFIG_ARM64_CONT_PTE_SHIFT 4
#define EBADMSG 74
#define MDIO_USXGMII_5000 0x0a00
#define CONFIG_NET_VENDOR_GOOGLE 1
#define __SIGINFO struct { int si_signo; int si_errno; int si_code; union __sifields _sifields; }
#define SMIDR_EL1_AFFINITY GENMASK(11, 0)
#define SYS_TTBR0_EL1_Op0 3
#define SYS_TTBR0_EL1_Op1 0
#define SYS_TTBR0_EL1_Op2 0
#define DEFAULT_OVERFLOWGID 65534
#define KERNEL_HWCAP_FLAGM2 __khwcap2_feature(FLAGM2)
#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
#define KUNIT_ASSERT_FAILURE(test,fmt,...) KUNIT_FAIL_ASSERTION(test, KUNIT_ASSERTION, fmt, ##__VA_ARGS__)
#define ID_PFR0_EL1_CSV2_CSV2p1 UL(0b0010)
#define IIF_FLAGS 4
#define PR_TIMING_TIMESTAMP 1
#define ID_AA64MMFR2_EL1_TTL_SHIFT 48
#define EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(name,ns) _EXPORT_DEV_SLEEP_PM_OPS(name, "GPL", #ns)
#define Q_GETNEXTQUOTA 0x800009
#define PR_FP_EXC_INV 0x100000
#define _UAPI_LINUX_STAT_H 
#define ftrace_return_address0 __builtin_return_address(0)
#define ID_ISAR2_EL1_Reversal_REV UL(0b0001)
#define SMIDR_EL1_SMPS_MASK GENMASK(15, 15)
#define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
#define NLMSG_DEFAULT_SIZE (NLMSG_GOODSIZE - NLMSG_HDRLEN)
#define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
#define DEFAULT_FS_OVERFLOWGID 65534
#define SCTLR_EL1_E0E_MASK GENMASK(24, 24)
#define MVFR0_EL1_FPSP_SHIFT 4
#define pageblock_end_pfn(pfn) ALIGN((pfn) + 1, pageblock_nr_pages)
#define SVE_PT_REGS_OFFSET ((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
#define CLOCKFD CPUCLOCK_MAX
#define list_next_entry_circular(pos,head,member) (list_is_last(&(pos)->member, head) ? list_first_entry(head, typeof(*(pos)), member) : list_next_entry(pos, member))
#define HCR_TICAB (UL(1) << 50)
#define OSECCR_EL1_UNKN (UL(0))
#define ID_AA64ISAR1_EL1_FCMA_SIGNED false
#define FMODE_WRITE ((__force fmode_t)0x2)
#define QC_RT_SPACE (1<<14)
#define _LINUX_IF_ETHER_H 
#define _DPRINTK_FLAGS_INCL_FUNCNAME (1<<2)
#define IS_VERITY(inode) ((inode)->i_flags & S_VERITY)
#define PIRx_ELx_Perm8_MASK GENMASK(35, 32)
#define LOGLEVEL_DEFAULT -1
#define ID_PFR2_EL1_CSV3 GENMASK(3, 0)
#define PF_W 0x2
#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
#define CLONE_PARENT 0x00008000
#define BITMAP_MEM_ALIGNMENT 8
#define TTBRx_EL1_CnP_WIDTH 1
#define DACR32_EL2_D11_MASK GENMASK(23, 22)
#define HWCAP_ASIMD (1 << 1)
#define for_each_active_irq(irq) for (irq = irq_get_next_irq(0); irq < nr_irqs; irq = irq_get_next_irq(irq + 1))
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
#define MAS_BUG_ON(__mas,__x) BUG_ON(__x)
#define arch_atomic64_fetch_sub_acquire arch_atomic64_fetch_sub_acquire
#define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l))
#define CONFIG_DECOMPRESS_BZIP2 1
#define ZERO_OR_NULL_PTR(x) ((unsigned long)(x) <= (unsigned long)ZERO_SIZE_PTR)
#define EBFONT 59
#define CONFIG_ARM64_ERRATUM_2658417 1
#define SETVAL 16
#define ID_PFR1_EL1_GIC_MASK GENMASK(31, 28)
#define HFGxTR_EL2_VBAR_EL1_WIDTH 1
#define FMODE_LSEEK ((__force fmode_t)0x4)
#define ID_AA64DFR0_EL1_PMUVer_V3P1 UL(0b0100)
#define ID_ISAR5_EL1_SEVL_SHIFT 0
#define ID_AA64DFR0_EL1_PMUVer_V3P4 UL(0b0101)
#define ID_AA64DFR0_EL1_PMUVer_V3P5 UL(0b0110)
#define ID_AA64DFR0_EL1_PMUVer_V3P7 UL(0b0111)
#define ID_AA64DFR0_EL1_PMUVer_V3P8 UL(0b1000)
#define esr_cp15_to_sysreg(e) sys_reg(3, (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> ESR_ELx_SYS64_ISS_OP1_SHIFT), (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> ESR_ELx_SYS64_ISS_CRN_SHIFT), (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT), (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> ESR_ELx_SYS64_ISS_OP2_SHIFT))
#define EUNATCH 49
#define CONFIG_STRICT_KERNEL_RWX 1
#define __p4d(x) ((p4d_t) { __pgd(x) })
#define SOL_ATM 264
#define KERNEL_HWCAP_SSBS __khwcap_feature(SSBS)
#define KERNEL_HWCAP_PACG __khwcap_feature(PACG)
#define KBD_UNBOUND_KEYCODE 0x0002
#define ESR_ELx_FSC_TYPE (0x3C)
#define clear_stopped_child_used_math(child) do { (child)->flags &= ~PF_USED_MATH; } while (0)
#define virt_addr_valid(addr) ({ __typeof__(addr) __addr = __tag_reset(addr); __is_lm_address(__addr) && pfn_is_map_memory(virt_to_pfn(__addr)); })
#define DACR32_EL2_D14_WIDTH 2
#define NLMSG_GOODSIZE SKB_WITH_OVERHEAD(PAGE_SIZE)
#define PSR_AA32_V_BIT 0x10000000
#define HFGxTR_EL2_ERXPFGF_EL1_WIDTH 1
#define ID_AA64ISAR1_EL1_API_SIGNED false
#define FS_HUGE_FILE_FL 0x00040000
#define TCR_SH1_SHIFT 28
#define SYS_CPACR_EL1_CRm 0
#define SYS_CPACR_EL1_CRn 1
#define KMALLOC_SHIFT_LOW 3
#define ID_AA64ISAR0_EL1_TME_MASK GENMASK(27, 24)
#define QUOTA_NL_IHARDWARN 1
#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
#define DL_FLAG_AUTOPROBE_CONSUMER BIT(5)
#define IS_NOCMTIME(inode) ((inode)->i_flags & S_NOCMTIME)
#define SCTLR_ELx_ENTP2 (BIT(60))
#define SCTLR_EL1_TME_WIDTH 1
#define HCR_FMO (UL(1) << 3)
#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
#define max_array(array,len) __minmax_array(max, array, len)
#define folio_page(folio,n) nth_page(&(folio)->page, n)
#define KERN_DEFAULT ""
#define _LINUX_ALIGN_H 
#define SIOCBONDRELEASE 0x8991
#define CLONE_PIDFD 0x00001000
#define I3C_MATCH_EXTRA_INFO 0x8
#define KERNEL_HWCAP_EBF16 __khwcap2_feature(EBF16)
#define ID_AA64PFR0_EL1_EL1_SHIFT 4
#define SZ_4M 0x00400000
#define DECLARE_TASKLET_OLD(name,_func) struct tasklet_struct name = { .count = ATOMIC_INIT(0), .func = _func, }
#define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
#define IPPROTO_HOPOPTS 0
#define PMSIDR_EL1_MAXSIZE_SHIFT 12
#define topology_physical_package_id(cpu) (cpu_topology[cpu].package_id)
#define MSG_DONTWAIT 0x40
#define GIC_PRIO_IRQOFF ({ extern struct static_key_false gic_nonsecure_priorities; u8 __prio = __GIC_PRIO_IRQOFF; if (static_branch_unlikely(&gic_nonsecure_priorities)) __prio = __GIC_PRIO_IRQOFF_NS; __prio; })
#define HFGxTR_EL2_nRCWMASK_EL1_WIDTH 1
#define _IOC_DIRBITS 2
#define CONFIG_BLK_DEV 1
#define PTE_DEVMAP (_AT(pteval_t, 1) << 57)
#define ID_AA64MMFR2_EL1_CCIDX_WIDTH 4
#define _Q_PENDING_VAL (1U << _Q_PENDING_OFFSET)
#define SYS_ID_DFR0_EL1_Op0 3
#define SYS_ID_DFR0_EL1_Op1 0
#define SYS_ID_DFR0_EL1_Op2 2
#define INPUT_DEVICE_ID_MATCH_MSCIT 0x0100
#define ESR_ELx_FSC_SECC_TTW0 (0x1c)
#define SYS_FAR_EL12_CRm 0
#define SYS_FAR_EL12_CRn 6
#define SYS_PMSICR_EL1_CRm 9
#define SYS_PMSICR_EL1_CRn 9
#define postcore_initcall(fn) __define_initcall(fn, 2)
#define ID_DFR0_EL1_PerfMon GENMASK(27, 24)
#define LOCAL64_INIT(i) { LOCAL_INIT(i) }
#define SIGNAL_CLD_STOPPED 0x00000010
#define ID_AA64PFR1_EL1_GCS_SHIFT 44
#define CONFIG_IOMMU_API 1
#define SIOCDELMULTI 0x8932
#define __NR_process_mrelease 448
#define ID_ISAR2_EL1_MemHint_PLD2 UL(0b0010)
#define HDFGRTR_EL2_OSLSR_EL1 GENMASK(9, 9)
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
#define for_each_sg(sglist,sg,nr,__i) for (__i = 0, sg = (sglist); __i < (nr); __i++, sg = sg_next(sg))
#define PR_RISCV_V_GET_CONTROL 70
#define ID_PFR2_EL1_RAS_frac_SIGNED false
#define unregister_ftrace_graph(ops) do { } while (0)
#define ID_AA64MMFR1_EL1_HAFDBS_WIDTH 4
#define __NR_preadv 69
#define QFMT_SHMEM 5
#define __wait_event_interruptible_lock_irq(wq_head,condition,lock,cmd) ___wait_event(wq_head, condition, TASK_INTERRUPTIBLE, 0, 0, spin_unlock_irq(&lock); cmd; schedule(); spin_lock_irq(&lock))
#define SLAB_NO_USER_FLAGS ((slab_flags_t __force)0x10000000U)
#define ID_PFR0_EL1_State0_SIGNED false
#define TRBMAR_EL1_Attr_SHIFT 0
#define SCTLR_EL1_TCF_MASK GENMASK(41, 40)
#define __constant_be16_to_cpu(x) ___constant_swab16((__force __u16)(__be16)(x))
#define CCSIDR_EL1_Associativity_SHIFT 3
#define ID_AA64PFR0_EL1_AMU_IMP UL(0b0001)
#define MSG_ZEROCOPY 0x4000000
#define OSLAR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 1))
#define OSLAR_EL1_RES1 (UL(0))
#define CONFIG_MODULES_USE_ELF_RELA 1
#define arch_spin_is_locked(l) queued_spin_is_locked(l)
#define ADVERTISED_10000baseKR_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKR_Full)
#define RADIX_TREE_INIT(name,mask) XARRAY_INIT(name, mask)
#define TASK_NOLOAD 0x00000400
#define _Q_PENDING_BITS 8
#define ETHTOOL_SFLAGS 0x00000026
#define ENONET 64
#define REG_ID_PFR1_EL1 S3_0_C0_C1_1
#define FPE_FLTOVF 4
#define EXFULL 54
#define CONFIG_SOFTIRQ_ON_OWN_STACK 1
#define HDFGWTR_EL2_DBGWCRn_EL1 GENMASK(2, 2)
#define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT)
#define HDFGRTR_EL2_TRBSR_EL1 GENMASK(55, 55)
#define GFP_KERNEL_ACCOUNT (GFP_KERNEL | __GFP_ACCOUNT)
#define SO_PASSCRED 16
#define REG_TCR2_EL1 S3_0_C2_C0_3
#define HFGITR_EL2_nBRBIALL_MASK GENMASK(56, 56)
#define DQUOT_DEL_REWRITE max(V1_DEL_REWRITE, V2_DEL_REWRITE)
#define HDFGWTR_EL2_PMEVCNTRn_EL0_WIDTH 1
#define mutex_init(mutex) do { static struct lock_class_key __key; __mutex_init((mutex), #mutex, &__key); } while (0)
#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
#define KUNIT_EXPECT_STRNEQ(test,left,right) KUNIT_EXPECT_STRNEQ_MSG(test, left, right, NULL)
#define AUTONEG_DISABLE 0x00
#define SA_IMMUTABLE 0x00800000
#define __wait_event_killable(wq,condition) ___wait_event(wq, condition, TASK_KILLABLE, 0, 0, schedule())
#define SI_SIGIO -5
#define SYS_ID_AA64PFR0_EL1_CRn 0
#define HFGxTR_EL2_ISR_EL1_WIDTH 1
#define CPUCLOCK_CLOCK_MASK 3
#define TP_STATUS_LOSING (1 << 2)
#define HFGITR_EL2_TLBIASIDE1OS_WIDTH 1
#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
#define ETHTOOL_COALESCE_USECS_IRQ (ETHTOOL_COALESCE_RX_USECS_IRQ | ETHTOOL_COALESCE_TX_USECS_IRQ)
#define REG_ID_ISAR4_EL1 S3_0_C0_C2_4
#define MAXHOSTNAMELEN 64
#define LIST_BL_BUG_ON(x) 
#define xlate_dev_mem_ptr xlate_dev_mem_ptr
#define HFGxTR_EL2_ISR_EL1_MASK GENMASK(18, 18)
#define CLIDR_EL1_Ctype3_SHIFT 6
#define MDIO_AN_10GBT_STAT_LP5G 0x0040
#define MTE_TAG_SIZE 4
#define arch_atomic64_fetch_xor_release arch_atomic64_fetch_xor_release
#define PF_EXITING 0x00000004
#define ESR_ELx_SAS_SHIFT (22)
#define CONFIG_NET_VENDOR_VIA 1
#define ifr_map ifr_ifru.ifru_map
#define LORN_EL1_UNKN (UL(0))
#define ID_MMFR2_EL1_L1HvdFG_NI UL(0b0000)
#define TTBRx_EL1_BADDR_SHIFT 1
#define PFA_SPEC_IB_FORCE_DISABLE 6
#define pm_generic_resume NULL
#define HCRX_EL2_MSCEn_SHIFT 11
#define __UAPI_DEF_IF_IFCONF 1
#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
#define SCTLR_EL1_DSSBS_SHIFT 44
#define ARM64_MISMATCHED_CACHE_TYPE 52
#define DOWNSHIFT_DEV_DISABLE 0
#define HDFGRTR_EL2_DBGBCRn_EL1_WIDTH 1
#define _LINUX_HRTIMER_DEFS_H 
#define HDFGWTR_EL2_TRCCLAIM_SHIFT 36
#define CONFIG_SND_SIMPLE_CARD 1
#define LOCK_SECTION_NAME ".text..lock."KBUILD_BASENAME
#define __get_user(x,ptr) ({ int __gu_err = 0; __get_user_error((x), (ptr), __gu_err); __gu_err; })
#define arch___change_bit generic___change_bit
#define ADJ_ADJTIME 0x8000
#define TRBMAR_EL1_PAS GENMASK(11, 10)
#define CONFIG_GENERIC_IRQ_PROBE 1
#define ID_ISAR2_EL1_MultU_MASK GENMASK(23, 20)
#define SCTLR_EL1_TCF0_WIDTH 2
#define SOFTIRQ_HOTPLUG_SAFE_MASK (BIT(TIMER_SOFTIRQ) | BIT(IRQ_POLL_SOFTIRQ) | BIT(HRTIMER_SOFTIRQ) | BIT(RCU_SOFTIRQ))
#define CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS 1
#define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
#define CONFIG_IOMMU_IO_PGTABLE 1
#define __designated_init __attribute__((__designated_init__))
#define kcsan_check_read(ptr,size) kcsan_check_access(ptr, size, 0)
#define CONFIG_IRQ_DOMAIN 1
#define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features)
#define PIRx_ELx_Perm14_MASK GENMASK(59, 56)
#define HFGxTR_EL2_REVIDR_EL1_SHIFT 28
#define ID_AA64MMFR2_EL1_NV_SIGNED false
#define outsw outsw
#define SVCR_SM_MASK GENMASK(0, 0)
#define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
#define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
#define RCUREF_INIT(i) { .refcnt = ATOMIC_INIT(i - 1) }
#define SYS_ID_AFR0_EL1_Op0 3
#define HDFGRTR_EL2_DBGWCRn_EL1_WIDTH 1
#define SYS_ID_AFR0_EL1_Op2 3
#define HFGxTR_EL2_LORC_EL1_SHIFT 19
#define ARM64_SW_FEATURE_OVERRIDE_HVHE 4
#define ID_ISAR1_EL1_Endian_IMP UL(0b0001)
#define param_check_short(name,p) __param_check(name, p, short)
#define TCR2_EL1x_HAFT_WIDTH 1
#define LPA_SGMII_FULL_DUPLEX 0x1000
#define __ARCH_WANT_SYS_CLONE 
#define ID_ISAR2_EL1_MultiAccessInt_CONTINUABLE UL(0b0010)
#define raw_spin_unlock(lock) _raw_spin_unlock(lock)
#define CLIDR_LOUU_SHIFT 27
#define HFGITR_EL2_TLBIVAALE1 GENMASK(47, 47)
#define UINTPTR_MAX ULONG_MAX
#define SCTLR_EL1_BT0_WIDTH 1
#define NT_S390_TDB 0x308
#define ID_AA64ISAR1_EL1_FCMA_NI UL(0b0000)
#define ETHTOOL_GSSET_INFO 0x00000037
#define put_cpu() preempt_enable()
#define ID_AA64MMFR0_EL1_EXS_SIGNED false
#define ID_AA64PFR0_EL1_SVE_MASK GENMASK(35, 32)
#define EXPORT_NS_DEV_SLEEP_PM_OPS(name,ns) _EXPORT_DEV_SLEEP_PM_OPS(name, "", #ns)
#define __NR_shutdown 210
#define _FP_REGS 32
#define writesl writesl
#define writesq writesq
#define HWCAP_CPUID (1 << 11)
#define UNDEFINE_MSR_S "	.purgem	msr_s\n"
#define writesw writesw
#define HFGxTR_EL2_CTR_EL0 GENMASK(14, 14)
#define MSG_CMSG_COMPAT 0
#define ID_MMFR2_EL1_L1HvdRng_IMP UL(0b0001)
#define PT_LOPROC 0x70000000
#define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
#define __ASM_GENERIC_POSIX_TYPES_H 
#define SMPRIMAP_EL2_P13_SHIFT 52
#define HDFGRTR_EL2_TRBSR_EL1_WIDTH 1
#define SCTLR_EL1_ITD_WIDTH 1
#define CONFIG_SND_PCM 1
#define ID_DFR0_EL1_MProfDbg_NI UL(0b0000)
#define ID_AA64MMFR2_EL1_BBM GENMASK(55, 52)
#define SIOCGARP 0x8954
#define local_irq_restore(flags) do { if (!raw_irqs_disabled_flags(flags)) trace_hardirqs_on(); raw_local_irq_restore(flags); } while (0)
#define SIOCSIFSLAVE 0x8930
#define MDIO_MMD_PCS 3
#define TLB_FLUSH_VMA(mm,flags) { .vm_mm = (mm), .vm_flags = (flags) }
#define console_loglevel (console_printk[0])
#define ID_AA64DFR0_EL1_PMSVer_SHIFT 32
#define pud_page(pud) phys_to_page(__pud_to_phys(pud))
#define SOF_TIMESTAMPING_TX_RECORD_MASK (SOF_TIMESTAMPING_TX_HARDWARE | SOF_TIMESTAMPING_TX_SOFTWARE | SOF_TIMESTAMPING_TX_SCHED | SOF_TIMESTAMPING_TX_ACK)
#define LOGLEVEL_EMERG 0
#define TASK_WAKEKILL 0x00000100
#define KUNIT_EXPECT_MEMNEQ(test,left,right,size) KUNIT_EXPECT_MEMNEQ_MSG(test, left, right, size, NULL)
#define _TIF_32BIT (1 << TIF_32BIT)
#define HFGITR_EL2_ATS1E1WP_MASK GENMASK(17, 17)
#define KERNEL_HWCAP_SME_FA64 __khwcap2_feature(SME_FA64)
#define WEXITED 0x00000004
#define EPOLLMSG (__force __poll_t)0x00000400
#define IPV6_V6ONLY 26
#define _IOC_WRITE 1U
#define STAT_HAVE_NSEC 1
#define __NR_chroot 51
#define sig_kernel_ignore(sig) siginmask(sig, SIG_KERNEL_IGNORE_MASK)
#define noinline_for_stack noinline
#define PERCPU_DYNAMIC_SIZE_SHIFT 10
#define TRBLIMITR_EL1_E_WIDTH 1
#define ID_ISAR0_EL1_Divide_NI UL(0b0000)
#define __noclone __attribute__((__noclone__))
#define PAGE_SUBSECTION_MASK (~(PAGES_PER_SUBSECTION-1))
#define __ASM_GENERIC_GETORDER_H 
#define ID_DFR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 8))
#define ID_MMFR1_EL1_L1UniSW_INVALIDATE UL(0b0011)
#define CONFIG_PROVE_LOCKING 1
#define seqprop_assert(s) __seqprop(s, assert)(s)
#define ETHTOOL_GFECPARAM 0x00000050
#define PIRx_ELx_Perm12_WIDTH 4
#define CONFIG_GENERIC_IOREMAP 1
#define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
#define writel writel
#define __NR_msgget 186
#define arch_cmpxchg64_relaxed arch_cmpxchg_relaxed
#define writew writew
#define FWNODE_FLAG_INITIALIZED BIT(2)
#define DMI_EXACT_MATCH(a,b) { .slot = a, .substr = b, .exact_match = 1 }
#define PMSCR_EL2_E0HSPE_SHIFT 0
#define PG_head_mask ((1UL << PG_head))
#define __ASM_CPUCAP_DEFS_H 
#define devm_irq_alloc_descs_from(dev,from,cnt,node) devm_irq_alloc_descs(dev, -1, from, cnt, node)
#define __sve_vl_valid(vl) ((vl) % __SVE_VQ_BYTES == 0 && (vl) >= __SVE_VL_MIN && (vl) <= __SVE_VL_MAX)
#define ID_MMFR2_EL1_UniTLB_MASK GENMASK(19, 16)
#define HDFGRTR_EL2_TRBMAR_EL1_MASK GENMASK(53, 53)
#define PTRACE_SETSIGINFO 0x4203
#define __seqprop_case(s,lockname,prop) seqcount_ ##lockname ##_t: __seqprop_ ##lockname ##_ ##prop
#define HFGITR_EL2_TLBIVALE1OS_WIDTH 1
#define CLIDR_LOUIS_SHIFT 21
#define DEVICE_ATTR_IGNORE_LOCKDEP(_name,_mode,_show,_store) struct device_attribute dev_attr_ ##_name = __ATTR_IGNORE_LOCKDEP(_name, _mode, _show, _store)
#define ID_AA64PFR0_EL1_CSV2_SHIFT 56
#define hlist_for_each_entry_rcu_bh(pos,head,member) for (pos = hlist_entry_safe(rcu_dereference_bh(hlist_first_rcu(head)), typeof(*(pos)), member); pos; pos = hlist_entry_safe(rcu_dereference_bh(hlist_next_rcu( &(pos)->member)), typeof(*(pos)), member))
#define SCTLR_EL1_nTLSMD GENMASK(28, 28)
#define EKEYREJECTED 129
#define USER_HZ 100
#define PF_ASH AF_ASH
#define VM_WARN_ON_IRQS_ENABLED() do { } while (0)
#define HFGxTR_EL2_APGAKey_SHIFT 6
#define current_thread_info() ((struct thread_info *)current)
#define AF_INET 2
#define REG_ID_AA64AFR0_EL1 S3_0_C0_C5_4
#define __ASM_CPUTYPE_H 
#define ETH_MODULE_SFF_8636_MAX_LEN 640
#define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED)
#define FOLIO_PF_NO_COMPOUND 0
#define HDFGWTR_EL2_DBGCLAIM_SHIFT 5
#define REMAP_FILE_CAN_SHORTEN (1 << 1)
#define SCM_WIFI_STATUS SO_WIFI_STATUS
#define ID_AA64ISAR2_EL1_CSSC_NI UL(0b0000)
#define _UAPI_LINUX_TIME_H 
#define ifr_mtu ifr_ifru.ifru_mtu
#define __HCRX_EL2_nMASK (GENMASK(15, 14) | GENMASK(4, 0))
#define __NR_fchdir 50
#define PMSCR_EL2_PCT_VIRT UL(0b00)
#define IS_GETLK32(cmd) (0)
#define arch_cmpxchg128_local(ptr,o,n) ({ __cmpxchg128((ptr), (o), (n)); })
#define _NSIG 64
#define _PAGE_IOREMAP PROT_DEVICE_nGnRE
#define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
#define swait_event_exclusive(wq,condition) do { if (condition) break; __swait_event(wq, condition); } while (0)
#define ETHTOOL_COALESCE_USECS (ETHTOOL_COALESCE_RX_USECS | ETHTOOL_COALESCE_TX_USECS)
#define EARLY_PGDS(vstart,vend,add) (EARLY_ENTRIES(vstart, vend, PGDIR_SHIFT, add))
#define NLMSG_HDRLEN ((int) NLMSG_ALIGN(sizeof(struct nlmsghdr)))
#define CONFIG_SOCK_RX_QUEUE_MAPPING 1
#define ID_ISAR2_EL1_LoadStore_DOUBLE UL(0b0001)
#define KASAN_VMALLOC_PROT_NORMAL ((__force kasan_vmalloc_flags_t)0x04u)
#define SVCR_SM_SHIFT 0
#define SCTLR_ELx_TSCXT (BIT(20))
#define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS)
#define SIGEMT_MASK 0
#define ATTR_TIMES_SET (1 << 16)
#define SYS_TRBIDR_EL1_CRm 11
#define CONFIG_HAVE_DMA_CONTIGUOUS 1
#define ID_MMFR1_EL1_L1UniVA_SHIFT 4
#define memset_io(c,v,l) __memset_io((c),(v),(l))
#define ARCH_TIMER_MEM_VIRT_ACCESS 3
#define ID_AA64MMFR2_EL1_AT_MASK GENMASK(35, 32)
#define _UAPI_LINUX_SHM_H_ 
#define IPV6_PRIORITY_INTERACTIVE 0x0600
#define CONFIG_CRYPTO_HW 1
#define wake_up_all_locked(x) __wake_up_locked((x), TASK_NORMAL, 0)
#define arch___test_and_set_bit generic___test_and_set_bit
#define ID_MMFR0_EL1_ShareLvl_TWO UL(0b0001)
#define HWCAP2_EBF16 (1UL << 32)
#define HFGxTR_EL2_VBAR_EL1_SHIFT 38
#define MDIO_AN_C73_1_100GBASE_KR4 BIT(12)
#define raw_irqs_disabled_flags(flags) ({ typecheck(unsigned long, flags); arch_irqs_disabled_flags(flags); })
#define __NR_getsockname 204
#define SECCOMP_IOW(nr,type) _IOW(SECCOMP_IOC_MAGIC, nr, type)
#define ID_DFR1_EL1_HPMN0_WIDTH 4
#define AF_PACKET 17
#define ID_AA64MMFR1_EL1_ECBHB_IMP UL(0b0001)
#define arch_atomic64_fetch_add_acquire arch_atomic64_fetch_add_acquire
#define VM_FLUSH_RESET_PERMS 0x00000100
#define SO_BUSY_POLL 46
#define CONFIG_FUNCTION_ALIGNMENT 4
#define PACKET_AUXDATA 8
#define __PERCPU_RWSEM_DEP_MAP_INIT(lockname) .dep_map = { .name = #lockname },
#define ID_ISAR1_EL1_Jazelle_NI UL(0b0000)
#define this_cpu_generic_cmpxchg(pcp,oval,nval) ({ typeof(pcp) __ret; unsigned long __flags; raw_local_irq_save(__flags); __ret = raw_cpu_generic_cmpxchg(pcp, oval, nval); raw_local_irq_restore(__flags); __ret; })
#define ALTINSTR_ENTRY_CB(cpucap,cb) " .word 661b - .\n" " .word " __stringify(cb) "- .\n" " .hword " __stringify(cpucap) "\n" " .byte 662b-661b\n" " .byte 664f-663f\n"
#define ARCH_TIMER_MEM_MAX_FRAMES 8
#define CLONE_CLEAR_SIGHAND 0x100000000ULL
#define REG_HFGRTR_EL2 S3_4_C1_C1_4
#define LED_BRIGHT_HW_CHANGED BIT(21)
#define IPV6_MTU 24
#define PENALTY_FOR_NODE_WITH_CPUS (1)
#define ID_DFR0_EL1_CopDbg_VHE UL(0b0111)
#define ETHTOOL_TEST 0x0000001a
#define PTRACE_GETEVENTMSG 0x4201
#define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
#define ZORRO_WILDCARD (0xffffffff)
#define PARITY_CRC16_PR1 3
#define HFGITR_EL2_ICIALLUIS_SHIFT 0
#define ETH_FW_DUMP_DISABLE 0
#define be64_to_cpu __be64_to_cpu
#define AT_EUID 12
#define pgprot_noncached(prot) __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
#define CLONE_ARGS_SIZE_VER0 64
#define PSR_AA32_I_BIT 0x00000080
#define PF_UNSPEC AF_UNSPEC
#define BLKGETSIZE64 _IOR(0x12,114,size_t)
#define MSG_NO_SHARED_FRAGS 0x80000
#define P4D_TABLE_BIT (_AT(p4dval_t, 1) << 1)
#define __pci_ioport_map(dev,port,nr) ioport_map((port), (nr))
#define ID_AA64MMFR3_EL1_MEC_WIDTH 4
#define ID_AA64DFR0_EL1_DoubleLock_IMP UL(0b0000)
#define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
#define IPV6_FL_F_EXCL 2
#define TIF_SME_VL_INHERIT 28
#define CONFIG_ARCH_INLINE_SPIN_LOCK 1
#define CLD_TRAPPED 4
#define __ASM_GENERIC_SOCKET_H 
#define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
#define FT_CHRDEV 3
#define BLKFRAGET _IO(0x12,101)
#define kunit_test_suite(suite) kunit_test_suites(&suite)
#define R_AARCH64_PREL16 262
#define PF_R 0x4
#define HCRX_EL2_VFNMI GENMASK(8, 8)
#define readq_relaxed_poll_timeout(addr,val,cond,delay_us,timeout_us) readx_poll_timeout(readq_relaxed, addr, val, cond, delay_us, timeout_us)
#define CRn_mask 0xf
#define ID_AA64AFR0_EL1_IMPDEF1_WIDTH 4
#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
#define __no_sanitize_memory 
#define APR_MODULE_PREFIX "apr:"
#define readw_poll_timeout_atomic(addr,val,cond,delay_us,timeout_us) readx_poll_timeout_atomic(readw, addr, val, cond, delay_us, timeout_us)
#define ID_AA64MMFR1_EL1_HPDS_SIGNED false
#define array_index_nospec(index,size) ({ typeof(index) _i = (index); typeof(size) _s = (size); unsigned long _mask = array_index_mask_nospec(_i, _s); BUILD_BUG_ON(sizeof(_i) > sizeof(long)); BUILD_BUG_ON(sizeof(_s) > sizeof(long)); (typeof(_i)) (_i & _mask); })
#define MII_STAT1000 0x0a
#define CLIDR_EL1_Ctype7_MASK GENMASK(20, 18)
#define CLOCK_REALTIME_ALARM 8
#define ID_AA64MMFR2_EL1_VARange_WIDTH 4
#define ID_AA64PFR0_EL1_MPAM_0 UL(0b0000)
#define ID_AA64PFR0_EL1_MPAM_1 UL(0b0001)
#define CONFIG_ARCH_SUSPEND_POSSIBLE 1
#define MDSCR_EL1_EMBWE GENMASK(32, 32)
#define SYS_MVFR2_EL1_Op0 3
#define SYS_MVFR2_EL1_Op1 0
#define SYS_MVFR2_EL1_Op2 2
#define ID_ISAR0_EL1_BitField_IMP UL(0b0001)
#define DEFINE_RES_MEM_NAMED(_start,_size,_name) DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_MEM)
#define ID_AA64MMFR0_EL1_TGRAN4_IMP UL(0b0000)
#define REG_OSDTRTX_EL1 S2_0_C0_C3_2
#define CPACR_ELx_RES0 (UL(0) | GENMASK_ULL(63, 29) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | GENMASK_ULL(19, 18) | GENMASK_ULL(15, 0))
#define CPACR_ELx_RES1 (UL(0))
#define PF_X 0x1
#define __NR_getcpu 168
#define PAGE_FLAGS_LAYOUT_H 
#define ID_ISAR4_EL1_SWP_frac_SHIFT 28
#define ID_ISAR4_EL1_SMC_SHIFT 12
#define ID_AA64MMFR3_EL1_S2POE_MASK GENMASK(23, 20)
#define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
#define KERN_INFO KERN_SOH "6"
#define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
#define _UAPI_LINUX_FS_H 
#define SYS_TRBSR_EL1_CRm 11
#define SYS_TRBSR_EL1_CRn 9
#define CLIDR_EL1_Ttypen GENMASK(46, 33)
#define CONFIG_TREE_SRCU 1
#define RADIX_TREE_MAX_TAGS XA_MAX_MARKS
#define IPV6_FLOWINFO_PRIORITY 0x0ff00000
#define ID_ISAR5_EL1_VCMA GENMASK(31, 28)
#define __hrtimer_clock_base_align ____cacheline_aligned
#define EX_TYPE_BPF 1
#define _LINUX_ENERGY_MODEL_H 
#define _ASM_GENERIC_BITOPS_SCHED_H_ 
#define TRACEPOINT_DEFS_H 1
#define ID_AA64ISAR0_EL1_SHA2_SIGNED false
#define CLEARPAGEFLAG_NOOP(uname,lname) static inline void folio_clear_ ##lname(struct folio *folio) { } static inline void ClearPage ##uname(struct page *page) { }
#define FPE_CONDTRAP 15
#define POLLHUP 0x0010
#define CONFIG_HAVE_STACKPROTECTOR 1
#define local_add(i,l) atomic_long_add((i),(&(l)->a))
#define HDFGRTR_EL2_PMSFCR_EL1_WIDTH 1
#define ID_AA64PFR0_EL1_EL1_MASK GENMASK(7, 4)
#define list_lru_init(lru) __list_lru_init((lru), false, NULL, NULL)
#define pud_addr_end(addr,end) (end)
#define __raw_readl __raw_readl
#define USHORT_CMP_GE(a,b) (USHRT_MAX / 2 >= (unsigned short)((a) - (b)))
#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
#define FPE_INTDIV 1
#define SEEK_DATA 3
#define ID_AA64ISAR0_EL1_FHM_NI UL(0b0000)
#define SIOCGIFHWADDR 0x8927
#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
#define CONFIG_HAVE_ARM_SMCCC 1
#define MDSCR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 36) | GENMASK_ULL(28, 28) | GENMASK_ULL(25, 24) | GENMASK_ULL(20, 20) | GENMASK_ULL(18, 16) | GENMASK_ULL(11, 7) | GENMASK_ULL(5, 1))
#define MDSCR_EL1_RES1 (UL(0))
#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
#define TASK_NEW 0x00000800
#define IF_PROTO_X25 0x2006
#define U16_MAX ((u16)~0U)
#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
#define SYS_LISTEN 4
#define __NR_fsync 82
#define for_each_online_pgdat(pgdat) for (pgdat = first_online_pgdat(); pgdat; pgdat = next_online_pgdat(pgdat))
#define BMCR_ANENABLE 0x1000
#define HDFGRTR_EL2_nBRBCTL GENMASK(60, 60)
#define __refconst __section(".ref.rodata")
#define TRBMAR_EL1_SH_WIDTH 2
#define FS_XFLAG_APPEND 0x00000010
#define TP_STATUS_COPY (1 << 1)
#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
#define DEFINE_SRCU(name) __DEFINE_SRCU(name, )
#define IPV6_MINHOPCOUNT 73
#define ID_AA64MMFR3_EL1_SNERR_SIGNED false
#define TBSVC_MATCH_PROTOCOL_KEY 0x0001
#define _ARCH_ARM64_ASM_BUG_H 
#define DCACHE_OP_REAL 0x04000000
#define __setup_param(str,unique_id,fn,early) static const char __setup_str_ ##unique_id[] __initconst __aligned(1) = str; static struct obs_kernel_param __setup_ ##unique_id __used __section(".init.setup") __aligned(__alignof__(struct obs_kernel_param)) = { __setup_str_ ##unique_id, fn, early }
#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
#define key_to_poll(m) ((__force __poll_t)(uintptr_t)(void *)(m))
#define pmd_bad(pmd) (!pmd_table(pmd))
#define for_each_vma_range(__vmi,__vma,__end) while (((__vma) = vma_find(&(__vmi), (__end))) != NULL)
#define _LINUX_PID_NS_H 
#define _IOC(dir,type,nr,size) (((dir) << _IOC_DIRSHIFT) | ((type) << _IOC_TYPESHIFT) | ((nr) << _IOC_NRSHIFT) | ((size) << _IOC_SIZESHIFT))
#define call_rcu_tasks call_rcu
#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
#define ARCH_SUPPORTS_FTRACE_OPS 0
#define readb_poll_timeout(addr,val,cond,delay_us,timeout_us) readx_poll_timeout(readb, addr, val, cond, delay_us, timeout_us)
#define MDSCR_EL1_SC2_WIDTH 1
#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
#define HDFGWTR_EL2_PMINTEN GENMASK(17, 17)
#define X86_FAMILY_ANY 0
#define CONFIG_DEBUG_BUGVERBOSE 1
#define fl6_dport uli.ports.dport
#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
#define CONFIG_XZ_DEC 1
#define asm_volatile_goto(x...) asm goto(x)
#define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | GENMASK(29, 21) | GENMASK(19, 14) | BIT(11))
#define ASID(mm) (atomic64_read(&(mm)->context.id) & 0xffff)
#define CONFIG_TMPFS 1
#define SO_PROTOCOL 38
#define LED_COLOR_ID_RGB 9
#define MVFR1_EL1_FPFtZ_SHIFT 0
#define INIT_DEFERRABLE_WORK_ONSTACK(_work,_func) __INIT_DELAYED_WORK_ONSTACK(_work, _func, TIMER_DEFERRABLE)
#define TRAP_HWBKPT 4
#define HDFGWTR_EL2_OSDLR_EL1_SHIFT 11
#define ARM64_HAS_STAGE2_FWB 43
#define compat_lr_fiq regs[30]
#define KPROBE_FLAG_DISABLED 2
#define HFGITR_EL2_DVPRCTX_WIDTH 1
#define __REGISTER_PREFIX__ 
#define R_AARCH64_ADR_PREL_PG_HI21_NC 276
#define INLINE_COPY_FROM_USER 
#define DACR32_EL2_D8_SHIFT 16
#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
#define _DISCARD_PM_OPS(name,license,ns) static __maybe_unused const struct dev_pm_ops __static_ ##name
#define ID_ISAR6_EL1_DP_SIGNED false
#define MVFR0_EL1_FPDivide GENMASK(19, 16)
#define _LINUX_MODULE_PARAMS_H 
#define ID_MMFR1_EL1_BPred GENMASK(31, 28)
#define ETHTOOL_COALESCE_TX_AGGR_TIME_USECS BIT(26)
#define IOCB_HIPRI (__force int) RWF_HIPRI
#define AT_GETATTR_NOSEC 0x80000000
#define INPUT_DEVICE_ID_MATCH_PRODUCT 4
#define ID_AA64ISAR1_EL1_LRCPC GENMASK(23, 20)
#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
#define MDIO_STAT2 8
#define inl_p inl_p
#define __NR_statfs __NR3264_statfs
#define DACR32_EL2_D3_SHIFT 6
#define MAX_STACK_ALLOC 832
#define SCTLR_EL1_DZE_MASK GENMASK(14, 14)
#define _LINUX_HEX_H 
#define SYS_SMPRIMAP_EL2 sys_reg(3, 4, 1, 2, 5)
#define MODULE_ALIAS_CHARDEV(major,minor) MODULE_ALIAS("char-major-" __stringify(major) "-" __stringify(minor))
#define ID_MMFR3_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_MMFR3_EL1_RES1 (UL(0))
#define ___GFP_SKIP_KASAN 0
#define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
#define ALTERNATIVE(oldinstr,newinstr,...) _ALTERNATIVE_CFG(oldinstr, newinstr, __VA_ARGS__, 1)
#define HFGITR_EL2_TLBIRVAALE1 GENMASK(41, 41)
#define KERN_EMERG KERN_SOH "0"
#define PR_SET_PDEATHSIG 1
#define SCXTNUM_EL1_SoftwareContextNumber_WIDTH 64
#define HDFGRTR_EL2_nBRBDATA GENMASK(61, 61)
#define KERNEL_HWCAP_SVESHA3 __khwcap2_feature(SVESHA3)
#define IPV6_FL_F_REFLECT 4
#define __HDFGRTR_EL2_RES0 (BIT(49) | BIT(42) | GENMASK(39, 38) | GENMASK(21, 20) | BIT(8))
#define TASK_PFA_SET(name,func) static inline void task_set_ ##func(struct task_struct *p) { set_bit(PFA_ ##name, &p->atomic_flags); }
#define TIMER_TRACE_FLAGMASK (TIMER_MIGRATING | TIMER_DEFERRABLE | TIMER_PINNED | TIMER_IRQSAFE)
#define ID_AA64PFR1_EL1_RES1 (UL(0))
#define CLONE_CHILD_SETTID 0x01000000
#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
#define REG_LORC_EL1 S3_0_C10_C4_3
#define HFGITR_EL2_TLBIRVALE1 GENMASK(40, 40)
#define SYS_SMCR_EL2_Op0 3
#define SYS_SMCR_EL2_Op1 4
#define SYS_SMCR_EL2_Op2 6
#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
#define CONFIG_UNIX_SCM 1
#define readb_relaxed_poll_timeout_atomic(addr,val,cond,delay_us,timeout_us) readx_poll_timeout_atomic(readb_relaxed, addr, val, cond, delay_us, timeout_us)
#define USHORT_CMP_LT(a,b) (USHRT_MAX / 2 < (unsigned short)((a) - (b)))
#define CONFIG_SYSFS_SYSCALL 1
#define COMPAT_PT_DATA_ADDR 0x10004
#define HFGITR_EL2_TLBIRVAE1OS_WIDTH 1
#define SI_EXPANSION_SIZE (sizeof(struct siginfo) - sizeof(struct kernel_siginfo))
#define hlist_for_each_entry_from(pos,member) for (; pos; pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
#define CONFIG_APPLE_MAILBOX 1
#define get_user __get_user
#define ID_AA64MMFR2_EL1_FWB_SHIFT 40
#define PACKET_TX_TIMESTAMP 16
#define QC_ACCT_MASK (QC_SPACE | QC_INO_COUNT | QC_RT_SPACE)
#define DECLARE_PER_CPU_SECTION(type,name,sec) extern __PCPU_ATTRS(sec) __typeof__(type) name
#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
#define LAST_CPUPID_MASK ((1UL << LAST_CPUPID_SHIFT) - 1)
#define __NR3264_sendfile 71
#define ID_MMFR5_EL1_nTLBPA_WIDTH 4
#define HDFGRTR_EL2_DBGBVRn_EL1_WIDTH 1
#define SMPRIMAP_EL2_P5_WIDTH 4
#define subsys_initcall_sync(fn) __define_initcall(fn, 4s)
#define ID_PFR2_EL1_SSBS_IMP UL(0b0001)
#define SIGNAL_GROUP_EXIT 0x00000004
#define DEFINE_PER_CPU_PAGE_ALIGNED(type,name) DEFINE_PER_CPU_SECTION(type, name, "..page_aligned") __aligned(PAGE_SIZE)
#define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features)
#define HFGITR_EL2_TLBIVAE1_MASK GENMASK(43, 43)
#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
#define LPA_SGMII_100FULL 0x1400
#define const___change_bit generic___change_bit
#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
#define MVFR1_EL1_SIMDSP_IMP UL(0b0001)
#define ID_ISAR2_EL1_Mult GENMASK(15, 12)
#define __and(x,y) ___and(x, y)
#define NLMSG_OK(nlh,len) ((len) >= (int)sizeof(struct nlmsghdr) && (nlh)->nlmsg_len >= sizeof(struct nlmsghdr) && (nlh)->nlmsg_len <= (len))
#define _DEFINE_FLEX(type,name,member,count,initializer) _Static_assert(__builtin_constant_p(count), "onstack flex array members require compile-time const count"); union { u8 bytes[struct_size_t(type, member, count)]; type obj; } name ##_u initializer; type *name = (type *)&name ##_u
#define __NR_rt_sigprocmask 135
#define CONFIG_CGROUP_DEVICE 1
#define DQUOT_USAGE_ENABLED (1 << _DQUOT_USAGE_ENABLED * MAXQUOTAS)
#define ID_AA64MMFR0_EL1_TGRAN16_MASK GENMASK(23, 20)
#define MVFR2_EL1_FPMisc_MASK GENMASK(7, 4)
#define MDCCINT_EL1_RX_MASK GENMASK(30, 30)
#define HDFGRTR_EL2_PMSCR_EL1_MASK GENMASK(26, 26)
#define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
#define smp_rmb() do { kcsan_rmb(); __smp_rmb(); } while (0)
#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
#define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
#define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
#define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
#define SYS_CONTEXTIDR_EL12_CRn 13
#define DT_RPATH 15
#define HDFGWTR_EL2_OSECCR_EL1_WIDTH 1
#define PSR_AA32_MODE_IRQ 0x00000012
#define REG_CONTEXTIDR_EL12 S3_5_C13_C0_1
#define NLMSG_NOOP 0x1
#define ETHTOOL_COALESCE_USE_ADAPTIVE_TX BIT(10)
#define ID_ISAR1_EL1_Except GENMASK(7, 4)
#define IRQF_ONESHOT 0x00002000
#define ISR_EL1_FS_MASK GENMASK(9, 9)
#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
#define MDSCR_EL1_TDCC_WIDTH 1
#define __LINUX_SPINLOCK_TYPES_H 
#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
#define pmd_pgtable(pmd) pmd_page(pmd)
#define WQ_FLAG_CUSTOM 0x04
#define R_AARCH64_ABS16 259
#define arch_cmpxchg_acquire(...) __cmpxchg_wrapper(_acq, __VA_ARGS__)
#define kfree_rcu_mightsleep(ptr) kvfree_rcu_arg_1(ptr)
#define ID_ISAR0_EL1_Coproc_MRRC UL(0b0011)
#define VTCR_EL2_SL0_SHIFT 6
#define nodes_weight(nodemask) __nodes_weight(&(nodemask), MAX_NUMNODES)
#define MMF_HAS_UPROBES 19
#define __is_kvfree_rcu_offset(offset) ((offset) < 4096)
#define KERNEL_HWCAP_USCAT __khwcap_feature(USCAT)
#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)
#define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
#define INPUT_DEVICE_ID_MATCH_SWBIT 0x1000
#define HDFGWTR_EL2_PMSFCR_EL1 GENMASK(28, 28)
#define ID_ISAR5_EL1_VCMA_MASK GENMASK(31, 28)
#define __NR_pkey_free 290
#define ID_AA64ZFR0_EL1_F64MM_IMP UL(0b0001)
#define I_DIRTY_ALL (I_DIRTY | I_DIRTY_TIME)
#define CONFIG_NET_VENDOR_SMSC 1
#define __le16_to_cpus(x) do { (void)(x); } while (0)
#define __LINUX_STRINGIFY_H 
#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
#define PIE_NONE_O 0x0
#define CONFIG_ZYNQMP_IPI_MBOX 1
#define CONFIG_SND_PCM_TIMER 1
#define CONFIG_SLUB_DEBUG 1
#define RENAME_WHITEOUT (1 << 2)
#define __NR_ptrace 117
#define ___GFP_ACCOUNT 0x400000u
#define flowi4_multipath_hash __fl_common.flowic_multipath_hash
#define READ_ONCE(x) ({ compiletime_assert_rwonce_type(x); __READ_ONCE(x); })
#define CONFIG_RD_LZMA 1
#define HDFGWTR_EL2_DBGPRCR_EL1_MASK GENMASK(7, 7)
#define ESR_ELx_EC_HVC32 (0x12)
#define HUGETLB_FLAG_ENCODE_SHIFT 26
#define HCRX_EL2_SCTLR2En_WIDTH 1
#define _LINUX_HIGHUID_H 
#define SYS_HFGRTR_EL2_Op1 4
#define TIME_DEL 2
#define ETH_P_IFE 0xED3E
#define HDFGWTR_EL2_PMEVTYPERn_EL0 GENMASK(13, 13)
#define key_ref_put(k) do { } while(0)
#define XA_FLAGS_ALLOC (XA_FLAGS_TRACK_FREE | XA_FLAGS_MARK(XA_FREE_MARK))
#define NLM_F_DUMP_FILTERED 0x20
#define STATX_ATTR_VERITY 0x00100000
#define ETHTOOL_GRXNTUPLE 0x00000036
#define CAP_TO_MASK(x) (1U << ((x) & 31))
#define ID_PFR1_EL1_MProgMod_IMP UL(0b0001)
#define HCR_CD (UL(1) << 32)
#define MDIO_PMD_TXDIS_2 0x0008
#define MVFR1_EL1_FPHP_NI UL(0b0000)
#define ID_DFR0_EL1_MMapTrc_SHIFT 16
#define ID_MMFR1_EL1_L1HvdSW_INVALIDATE_DSIDE_ONLY UL(0b0010)
#define STB_WEAK 2
#define ID_PFR0_EL1_DIT_MASK GENMASK(27, 24)
#define SYS_PMSCR_EL1_CRm 9
#define __NR_sched_yield 124
#define si_pkey _sifields._sigfault._addr_pkey._pkey
#define _LINUX_ATOMIC_INSTRUMENTED_H 
#define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM
#define ID_AA64PFR0_EL1_EL0_SIGNED false
#define PUD_SIZE (1UL << PUD_SHIFT)
#define MDIO_DEVS1 5
#define raw_cmpxchg64_acquire arch_cmpxchg64_acquire
#define MAX_ERRNO 4095
#define netif_crit(priv,type,dev,fmt,args...) netif_level(crit, priv, type, dev, fmt, ##args)
#define _ASM_GENERIC_BITOPS_HWEIGHT_H_ 
#define __EXPORT_SYMBOL(sym,license,ns) extern typeof(sym) sym; __ADDRESSABLE(sym) asm(__stringify(___EXPORT_SYMBOL(sym, license, ns)))
#define ID_AA64ISAR0_EL1_CRC32_NI UL(0b0000)
#define SYS_FAR_EL12_Op1 5
#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME 
#define SYS_CCSIDR2_EL1 sys_reg(3, 1, 0, 0, 2)
#define ID_PFR0_EL1_RAS_NI UL(0b0000)
#define ID_DFR0_EL1_PerfMon_WIDTH 4
#define SWAPPER_RW_MMUFLAGS (PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS | PTE_WRITE)
#define ETH_P_LAT 0x6004
#define BRK64_OPCODE_KPROBES (AARCH64_BREAK_MON | (KPROBES_BRK_IMM << 5))
#define __bitwise 
#define SHMCTL 24
#define ETH_TLEN 2
#define NLM_F_ATOMIC 0x400
#define MDIO_PMA_LASI_TXSTAT 0x9004
#define ENOTSOCK 88
#define likely_notrace(x) likely(x)
#define HDFGRTR_EL2_MDSCR_EL1 GENMASK(4, 4)
#define ID_MMFR0_EL1_AuxReg_SHIFT 20
#define ID_AA64ISAR2_EL1_CSSC_IMP UL(0b0001)
#define TRBBASER_EL1_BASE_WIDTH 52
#define __swait_event_interruptible(wq,condition) ___swait_event(wq, condition, TASK_INTERRUPTIBLE, 0, schedule())
#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0
#define ID_AA64MMFR3_EL1_TCRX_WIDTH 4
#define __LINUX_CPUMASK_H 
#define NT_ARM_SSVE 0x40b
#define IOREMAP_MAX_ORDER (PUD_SHIFT)
#define MDSCR_EL1_TXU_WIDTH 1
#define outsw_p outsw_p
#define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC)
#define _LINUX_IRQHANDLER_H 
#define lockdep_softirq_exit() do { current->softirq_context--; } while (0)
#define SYS_PMSLATFR_EL1_Op1 0
#define SYS_PMSLATFR_EL1_Op2 6
#define PUD_TYPE_MASK (_AT(pudval_t, 3) << 0)
#define kvfree_rcu_mightsleep(ptr) kvfree_rcu_arg_1(ptr)
#define ifc_buf ifc_ifcu.ifcu_buf
#define CCSIDR2_EL1_NumSets_SHIFT 0
#define TCR2_EL2_DisCH1_WIDTH 1
#define AF_ECONET 19
#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
#define ID_ISAR1_EL1_IfThen_SHIFT 16
#define local64_read(l) local_read(&(l)->a)
#define HCRX_EL2_MCE2_WIDTH 1
#define BLKRASET _IO(0x12,98)
#define PACKET_ADD_MEMBERSHIP 1
#define NR_OPEN_MAX ~0U
#define ARCH_TRACE_CLOCKS 
#define for_each_node_state(node,__state) for ( (node) = 0; (node) == 0; (node) = 1)
#define ID_AA64MMFR3_EL1_SNERR_FEAT_ANERR_IND UL(0b0011)
#define HFGITR_EL2_DCCIVAC_WIDTH 1
#define SUPPORTED_2500baseX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(2500baseX_Full)
#define ETHTOOL_SRXNTUPLE 0x00000035
#define CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 1
#define HFGxTR_EL2_ERXPFGCDN_EL1_SHIFT 48
#define ID_ISAR1_EL1_Immediate_WIDTH 4
#define count_vm_numa_events(x,y) do { (void)(y); } while (0)
#define PIE_RWX_O 0x7
#define _LINUX_SCHED_H 
#define MAXTC 10
#define SEGV_CPERR 10
#define ID_AA64MMFR2_EL1_IDS_SHIFT 36
#define CONFIG_CC_CAN_LINK_STATIC 1
#define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200
#define OSLAR_EL1_OSLK_WIDTH 1
#define CONFIG_AS_VERSION 24000
#define preempt_enable_notrace() do { barrier(); __preempt_count_dec(); } while (0)
#define KSTAT_ATTR_FS_IOC_FLAGS (STATX_ATTR_COMPRESSED | STATX_ATTR_IMMUTABLE | STATX_ATTR_APPEND | STATX_ATTR_NODUMP | STATX_ATTR_ENCRYPTED | STATX_ATTR_VERITY )
#define CONFIG_DECOMPRESS_XZ 1
#define ID_AA64DFR0_EL1_MTPMU_IMP UL(0b0001)
#define ETHTOOL_STAT_NOT_SET (~0ULL)
#define SIGPOLL SIGIO
#define SOL_NFC 280
#define _COMPAT_NSIG_BPW 32
#define NODE_MASK_LAST_WORD BITMAP_LAST_WORD_MASK(MAX_NUMNODES)
#define RNDGETPOOL _IOR( 'R', 0x02, int [2] )
#define SZ_8M 0x00800000
#define HDFGWTR_EL2_TRBMAR_EL1_SHIFT 53
#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
#define ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
#define CMSG_ALIGN(len) ( ((len)+sizeof(long)-1) & ~(sizeof(long)-1) )
#define key_free_user_ns(ns) do { } while(0)
#define MUTEX_POISON_WW_CTX ((void *) 0x500 + POISON_POINTER_DELTA)
#define memcat_p(a,b) ({ BUILD_BUG_ON_MSG(!__same_type(*(a), *(b)), "type mismatch in memcat_p()"); (typeof(*a) *)__memcat_p((void **)(a), (void **)(b)); })
#define PR_SPEC_NOT_AFFECTED 0
#define TAIL_MAPPING ((void *) 0x400 + POISON_POINTER_DELTA)
#define HDFGWTR_EL2_TRCAUXCTLR_SHIFT 35
#define lockdep_unpin_lock(l,c) lock_unpin_lock(&(l)->dep_map, (c))
#define PMSICR_EL1_ECOUNT GENMASK(63, 56)
#define ID_ISAR2_EL1_UNKN (UL(0))
#define TCR2_EL2_DisCH0_WIDTH 1
#define ID_AA64MMFR1_EL1_TIDCP1_IMP UL(0b0001)
#define MAX_UDELAY_MS 5
#define HFGITR_EL2_TLBIRVAALE1_MASK GENMASK(41, 41)
#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
#define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED)
#define CONFIG_HID_SUPPORT 1
#define ESR_ELx_DirtyBit_SHIFT (5)
#define __RWSEM_DEP_MAP_INIT(lockname) .dep_map = { .name = #lockname, .wait_type_inner = LD_WAIT_SLEEP, },
#define FS_SECRM_FL 0x00000001
#define TRAP_TRACE 2
#define MNT_SHARED_MASK (MNT_UNBINDABLE)
#define SC_ARM64_REGS_TO_ARGS(x,...) __MAP(x,__SC_ARGS ,,regs->regs[0],,regs->regs[1],,regs->regs[2] ,,regs->regs[3],,regs->regs[4],,regs->regs[5])
#define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
#define CPACR_EL1_ZEN_EL0EN (BIT(17))
#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
#define SZ_128M 0x08000000
#define MVFR0_EL1_FPDivide_IMP UL(0b0001)
#define CONFIG_RUST_IS_AVAILABLE 1
#define SVE_VQ_MAX __SVE_VQ_MAX
#define EARLY_PAGES(vstart,vend,add) ( 1 + EARLY_PGDS((vstart), (vend), add) + EARLY_PUDS((vstart), (vend), add) + EARLY_PMDS((vstart), (vend), add))
#define ID_MMFR1_EL1_L1HvdSW_NI UL(0b0000)
#define arch_atomic64_fetch_andnot arch_atomic64_fetch_andnot
#define __sve_vl_from_vq(vq) ((vq) * __SVE_VQ_BYTES)
#define TCR2_EL1x_DisCH1_WIDTH 1
#define __SEQ_LOCK(expr) expr
#define CONFIG_ARCH_HAS_PTE_DEVMAP 1
#define ETH_P_FCOE 0x8906
#define ID_AA64ISAR0_EL1_SHA3_IMP UL(0b0001)
#define DEFINE_SIMPLE_ATTRIBUTE_SIGNED(__fops,__get,__set,__fmt) DEFINE_SIMPLE_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, true)
#define SECCOMP_FILTER_FLAG_NEW_LISTENER (1UL << 3)
#define PAGE_OFFSET (_PAGE_OFFSET(VA_BITS))
#define IEEE1394_MATCH_VENDOR_ID 0x0001
#define hardirq_count() (preempt_count() & HARDIRQ_MASK)
#define FS_XFLAG_DAX 0x00008000
#define raw_try_cmpxchg128_acquire(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg128_acquire((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define CONFIG_RSEQ 1
#define EXPANSION_NPCAPABLE 0x0008
#define ID_ISAR1_EL1_Interwork_A32_BX UL(0b0011)
#define TCR2_EL2_SKL0_MASK GENMASK(7, 6)
#define BIN_ATTR_RO(_name,_size) struct bin_attribute bin_attr_ ##_name = __BIN_ATTR_RO(_name, _size)
#define FAR_EL12_UNKN (UL(0))
#define ID_ISAR0_EL1_Divide_xDIV_T32 UL(0b0001)
#define PF_POSTCOREDUMP 0x00000008
#define STATIC_CALL_TRAMP_PREFIX_STR __stringify(STATIC_CALL_TRAMP_PREFIX)
#define PMSIDR_EL1_INTERVAL_4096 UL(0b1000)
#define ETHTOOL_GRINGPARAM 0x00000010
#define CONFIG_PTP_1588_CLOCK_OPTIONAL 1
#define DT_VALRNGHI 0x6ffffdff
#define F_DUPFD_CLOEXEC (F_LINUX_SPECIFIC_BASE + 6)
#define IRQF_IRQPOLL 0x00001000
#define IRQF_TRIGGER_LOW 0x00000008
#define SYS_ID_AA64ISAR2_EL1_Op0 3
#define SYS_ID_AA64ISAR2_EL1_Op1 0
#define SYS_ID_AA64ISAR2_EL1_Op2 2
#define si_value _sifields._rt._sigval
#define WHITEOUT_MODE 0
#define R_AARCH64_PREL64 260
#define REG_ID_ISAR2_EL1 S3_0_C0_C2_2
#define PMSCR_EL2_PA_MASK GENMASK(4, 4)
#define PIRx_ELx_Perm14_SHIFT 56
#define ___change_bit arch___change_bit
#define XQM_USRQUOTA 0
#define CONFIG_CRYPTO_CRC32C 1
#define O_DIRECTORY 040000
#define __ASM_GENERIC_ACCESS_OK_H__ 
#define HDFGRTR_EL2_PMEVTYPERn_EL0_WIDTH 1
#define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
#define ARM64_WORKAROUND_1742098 73
#define ID_AA64ISAR1_EL1_GPA_SIGNED false
#define ID_ISAR5_EL1_SEVL_IMP UL(0b0001)
#define kfree_rcu(ptr,rhf) kvfree_rcu_arg_2(ptr, rhf)
#define ID_AA64SMFR0_EL1_I16I32_SIGNED false
#define MII_NCONFIG 0x1c
#define GPIO_LED_NO_BLINK_HIGH 1
#define CTR_EL0_CWG GENMASK(27, 24)
#define SOCKWQ_ASYNC_NOSPACE 0
#define FS_QUOTA_UDQ_ACCT (1<<0)
#define BMCR_RESV 0x003f
#define QC_SPC_HARD (1<<3)
#define HDFGRTR_EL2_MDSCR_EL1_MASK GENMASK(4, 4)
#define dev_crit(dev,fmt,...) dev_printk_index_wrap(_dev_crit, KERN_CRIT, dev, dev_fmt(fmt), ##__VA_ARGS__)
#define PROT_NORMAL_TAGGED (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
#define PACKET_FANOUT_ROLLOVER 3
#define ID_AA64DFR0_EL1_DoubleLock_WIDTH 4
#define SMPRI_EL1_PRIORITY_MASK GENMASK(3, 0)
#define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
#define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
#define ELF_ARCH EM_AARCH64
#define CONFIG_AUDIT_ARCH_COMPAT_GENERIC 1
#define virt_mb__after_atomic() do { kcsan_mb(); __smp_mb__after_atomic(); } while (0)
#define CONFIG_NET_VENDOR_HUAWEI 1
#define BITOP_LE_SWIZZLE 0
#define module_phy_driver(__phy_drivers) phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers))
#define CONFIG_ARCH_INLINE_READ_UNLOCK 1
#define MDIO_AN_10GBT_STAT_REMOK 0x1000
#define ID_ISAR0_EL1_Debug_MASK GENMASK(23, 20)
#define __FINIT .previous
#define ID_AA64ISAR2_EL1_RPRES_WIDTH 4
#define release_mem_region(start,n) __release_region(&iomem_resource, (start), (n))
#define PTRACE_O_TRACEEXEC (1 << PTRACE_EVENT_EXEC)
#define MDIO_PMA_10GBR_FECABLE 170
#define CONFIG_MAX_SKB_FRAGS 17
#define CONFIG_CC_HAVE_SHADOW_CALL_STACK 1
#define NODEMASK_ALLOC(type,name,gfp_flags) type _ ##name, *name = &_ ##name
#define min3(x,y,z) min((typeof(x))min(x, y), z)
#define mmu_notifier_range_update_to_read_only(r) false
#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG)
#define ID_MMFR2_EL1_L1HvdBG GENMASK(7, 4)
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
#define flowi_uid u.__fl_common.flowic_uid
#define ELOOP 40
#define local64_set(l,i) local_set((&(l)->a),(i))
#define S_DT(mode) (((mode) & S_IFMT) >> S_DT_SHIFT)
#define PF_MCE_EARLY 0x08000000
#define AF_NFC 39
#define IORESOURCE_MEM_32BIT (3<<3)
#define HFGxTR_EL2_CPACR_EL1 GENMASK(12, 12)
#define TRBSR_EL1_S_WIDTH 1
#define ID_ISAR6_EL1_SB GENMASK(15, 12)
#define _LINUX_SCHED_SIGNAL_H 
#define LED_BLINK_BRIGHTNESS_CHANGE 4
#define MDIO_PMA_LASI_RX_WISLFLT 0x0200
#define SIOCDEVPRIVATE 0x89F0
#define LED_COLOR_ID_MAX 15
#define SZ_128 0x00000080
#define ID_AA64MMFR1_EL1_PAN_WIDTH 4
#define ID_AA64MMFR2_EL1_CnP_NI UL(0b0000)
#define F_SETFL 4
#define smp_cond_load_acquire(ptr,cond_expr) ({ typeof(ptr) __PTR = (ptr); __unqual_scalar_typeof(*ptr) VAL; for (;;) { VAL = smp_load_acquire(__PTR); if (cond_expr) break; __cmpwait_relaxed(__PTR, VAL); } (typeof(*ptr))VAL; })
#define SCTLR_EL1_A GENMASK(1, 1)
#define CONFIG_ARM64_ERRATUM_843419 1
#define KSTAT_ATTR_VFS_FLAGS (STATX_ATTR_IMMUTABLE | STATX_ATTR_APPEND )
#define HDFGWTR_EL2_PMSWINC_EL0_WIDTH 1
#define MDIO_AN_10GBT_STAT_LP2_5G 0x0020
#define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
#define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT)
#define SYS_CONTEXTIDR_EL1_CRn 13
#define VM_ARCH_1 0x01000000
#define CONFIG_PAHOLE_VERSION 0
#define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
#define DACR32_EL2_D0_SHIFT 0
#define HDFGWTR_EL2_PMSIRR_EL1_WIDTH 1
#define SIOCGSTAMPNS SIOCGSTAMPNS_OLD
#define ARCH_TIMER_EVT_STREAM_FREQ (USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US)
#define __INT32_C(c) c
#define ID_ISAR1_EL1_Extend GENMASK(15, 12)
#define HFGITR_EL2_TLBIRVAALE1_SHIFT 41
#define DT_ADDRRNGHI 0x6ffffeff
#define XQM_COMMAND(x) (((x) & (0xff<<8)) == ('X'<<8))
#define ELFCLASSNONE 0
#define kvfree_rcu(ptr,rhf) kvfree_rcu_arg_2(ptr, rhf)
#define CONFIG_LOG_BUF_SHIFT 17
#define HFGITR_EL2_TLBIRVAAE1OS_WIDTH 1
#define CONFIG_DUMMY_CONSOLE_COLUMNS 80
#define ID_MMFR4_EL1_HPDS_MASK GENMASK(19, 16)
#define HFGITR_EL2_ATS1E0R GENMASK(14, 14)
#define NSIGSYS 2
#define HFGITR_EL2_ATS1E0W GENMASK(15, 15)
#define sockaddr_storage __kernel_sockaddr_storage
#define ID_AA64ZFR0_EL1_B16B16_SIGNED false
#define ID_AA64ISAR0_EL1_RDM_NI UL(0b0000)
#define ID_ISAR0_EL1_BitCount_WIDTH 4
#define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
#define MDIO_PMA_EXTABLE_10GBT 0x0004
#define HFGxTR_EL2_PAR_EL1_WIDTH 1
#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
#define VM_UNINITIALIZED 0x00000020
#define LAST_CPUPID_PGSHIFT (LAST_CPUPID_PGOFF * (LAST_CPUPID_WIDTH != 0))
#define CPACR_ELx_TTA_SHIFT 28
#define SVE_VQ_MIN __SVE_VQ_MIN
#define SCTLR_EL1_nAA GENMASK(6, 6)
#define ID_MMFR2_EL1_MemBarr_NI UL(0b0000)
#define BUILD_BUG_ON_NOT_POWER_OF_2(n) BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
#define HFGITR_EL2_ATS1E1R GENMASK(12, 12)
#define HFGITR_EL2_ATS1E1W GENMASK(13, 13)
#define rounddown(x,y) ( { typeof(x) __x = (x); __x - (__x % (y)); } )
#define ID_MMFR0_EL1_VMSA_VMSAv6 UL(0b0010)
#define PR_PAC_APIBKEY (1UL << 1)
#define TRACE_LIST_START TRACE_INTERNAL_BIT
#define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
#define PF_ROUTE AF_ROUTE
#define ENCODING_MANCHESTER 5
#define Q_XSETQLIM XQM_CMD(4)
#define CONFIG_FILE_LOCKING 1
#define ID_MMFR2_EL1_L1HvdFG GENMASK(3, 0)
#define CONFIG_HAVE_ARCH_TRACEHOOK 1
#define __NR_mq_timedsend 182
#define HFGxTR_EL2_TTBR0_EL1 GENMASK(36, 36)
#define const___test_and_clear_bit generic___test_and_clear_bit
#define SYS_PMBPTR_EL1_CRm 10
#define SYS_PMBPTR_EL1_CRn 9
#define __NR_fcntl __NR3264_fcntl
#define SCTLR_EL1_CP15BEN_MASK GENMASK(5, 5)
#define IOCB_WAITQ (1 << 19)
#define ID_MMFR3_EL1_CMaintVA_SHIFT 0
#define __ATTR_RO(_name) { .attr = { .name = __stringify(_name), .mode = 0444 }, .show = _name ##_show, }
#define CONFIG_HAVE_KVM 1
#define CLONE_NEWPID 0x20000000
#define NETIF_F_HW_TLS_RX __NETIF_F(HW_TLS_RX)
#define NT_RISCV_VECTOR 0x901
#define ID_AA64ISAR2_EL1_GPA3_NI UL(0b0000)
#define _NET_FLOW_H 
#define node_clear(node,dst) __node_clear((node), &(dst))
#define EXPORT_SYMBOL_NS_GPL(sym,ns) __EXPORT_SYMBOL(sym, "GPL", __stringify(ns))
#define SZ_16G _AC(0x400000000, ULL)
#define ID_AA64SMFR0_EL1_SMEver_SME UL(0b0000)
#define PMSCR_EL1_TS_SHIFT 5
#define SZ_16K 0x00004000
#define CONFIG_EVENTFD 1
#define SZ_16M 0x01000000
#define fl4_icmp_type uli.icmpt.type
#define O_ACCMODE 00000003
#define FTR_NONSTRICT false
#define SMPRIMAP_EL2_F9_MASK GENMASK(39, 36)
#define DCACHE_GENOCIDE 0x00000200
#define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
#define KMALLOC_SHIFT_MAX (MAX_ORDER + PAGE_SHIFT)
#define SCTLR_EL1_nTLSMD_MASK GENMASK(28, 28)
#define CONFIG_HAVE_ARCH_MMAP_RND_BITS 1
#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
#define HDFGRTR_EL2_TRCPRGCTLR GENMASK(44, 44)
#define atomic_cond_read_relaxed(v,c) smp_cond_load_relaxed(&(v)->counter, (c))
#define XAS_BOUNDS ((struct xa_node *)1UL)
#define PMBSR_EL1_COLL_MASK GENMASK(16, 16)
#define REG_ID_AA64MMFR2_EL1 S3_0_C0_C7_2
#define PR_PAC_APDAKEY (1UL << 2)
#define PARITY_CRC32_PR0_CCITT 6
#define __pgd(x) ((pgd_t) { (x) } )
#define ID_AA64MMFR1_EL1_nTLBPA_WIDTH 4
#define SYS_FAR_EL2_CRm 0
#define SYS_FAR_EL2_CRn 6
#define __diag_warn(compiler,version,option,comment) __diag_ ## compiler(version, warn, option)
#define USB_DEVICE_ID_MATCH_PRODUCT 0x0002
#define HUGETLB_FLAG_ENCODE_2GB (31U << HUGETLB_FLAG_ENCODE_SHIFT)
#define TCR2_EL2_AMEC0_WIDTH 1
#define sizeof_field(TYPE,MEMBER) sizeof((((TYPE *)0)->MEMBER))
#define DT_ADDRRNGLO 0x6ffffe00
#define ETHTOOL_GCOALESCE 0x0000000e
#define param_check_byte(name,p) __param_check(name, p, unsigned char)
#define RWH_WRITE_LIFE_MEDIUM 3
#define CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK 1
#define CONSOLE_LOGLEVEL_QUIET CONFIG_CONSOLE_LOGLEVEL_QUIET
#define HWCAP2_I8MM (1 << 13)
#define ID_AA64MMFR1_EL1_AFP GENMASK(47, 44)
#define ID_AA64ISAR1_EL1_API_FPACCOMBINE UL(0b0101)
#define HDFGRTR_EL2_TRC_WIDTH 1
#define HDFGWTR_EL2_TRCPRGCTLR_WIDTH 1
#define __NR_mq_open 180
#define OSECCR_EL1_EDECCR_WIDTH 32
#define __NR_pkey_mprotect 288
#define KERNEL_HWCAP_SVEI8MM __khwcap2_feature(SVEI8MM)
#define JOBCTL_STOP_CONSUME_BIT 18
#define F_SETLK 6
#define LORN_EL1_Num GENMASK(7, 0)
#define CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN 1
#define ID_DFR1_EL1_MTPMU_WIDTH 4
#define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
#define VA_BITS (CONFIG_ARM64_VA_BITS)
#define MDIO_USXGMII_100HALF 0x0200
#define __NR_futex 98
#define ID_ISAR6_EL1_FHM_MASK GENMASK(11, 8)
#define CONFIG_SPI_BITBANG 1
#define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
#define HDFGRTR_EL2_TRCVICTLR_MASK GENMASK(48, 48)
#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
#define swahw32p __swahw32p
#define swahw32s __swahw32s
#define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001
#define CONFIG_NVMEM_SYSFS 1
#define AF_KEY 15
#define __raw_readq __raw_readq
#define ID_ISAR2_EL1_MultiAccessInt_SHIFT 8
#define __raw_readw __raw_readw
#define PIE_E0 ( PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_X_O) | PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX) | PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RWX) | PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R) | PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW))
#define ID_AA64MMFR3_EL1_SNERR_NI UL(0b0000)
#define ID_AA64PFR1_EL1_RES0 (UL(0) | GENMASK_ULL(23, 20))
#define SCTLR_EL1_MSCEn_MASK GENMASK(33, 33)
#define HCRX_EL2_VINMI_WIDTH 1
#define inb_p inb_p
#define raw_cpu_add(pcp,val) __pcpu_size_call(raw_cpu_add_, pcp, val)
#define IPV6_LEAVE_ANYCAST 28
#define MMF_DUMP_ELF_HEADERS 6
#define HCRX_EL2_D128En_SHIFT 17
#define ID_PFR0_EL1_State1_NI UL(0b0000)
#define KERNEL_HWCAP_PACA __khwcap_feature(PACA)
#define TRBMAR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 12))
#define TRBMAR_EL1_RES1 (UL(0))
#define ZONEID_PGOFF ((NODES_PGOFF < ZONES_PGOFF) ? NODES_PGOFF : ZONES_PGOFF)
#define CONFIG_DEVPORT 1
#define SCTLR_EL1_BT0 GENMASK(35, 35)
#define SCTLR_EL1_BT1 GENMASK(36, 36)
#define SSB_ANY_REV 0xFF
#define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
#define trace_warn_on_no_rcu(ip) ({ bool __ret = !rcu_is_watching(); if (__ret && !trace_recursion_test(TRACE_RECORD_RECURSION_BIT)) { trace_recursion_set(TRACE_RECORD_RECURSION_BIT); WARN_ONCE(true, "RCU not on for: %pS\n", (void *)ip); trace_recursion_clear(TRACE_RECORD_RECURSION_BIT); } __ret; })
#define __exit_call __used __section(".exitcall.exit")
#define HDFGRTR_EL2_TRCSTATR_WIDTH 1
#define NT_S390_RI_CB 0x30d
#define CHRDEV_MAJOR_DYN_END 234
#define DEFINE_MTREE(name) struct maple_tree name = MTREE_INIT(name, 0)
#define llist_entry(ptr,type,member) container_of(ptr, type, member)
#define ID_ISAR4_EL1_SMC_MASK GENMASK(15, 12)
#define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
#define GSO_BY_FRAGS 0xFFFF
#define _LINUX_HASH_H 
#define HFGITR_EL2_nBRBINJ_SHIFT 55
#define AT_PLATFORM 15
#define _PAGE_READONLY (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
#define SCTLR_EL1_nTWI_WIDTH 1
#define ID_PFR1_EL1_Virtualization_WIDTH 4
#define PMSG_AUTO_SUSPEND ((struct pm_message) { .event = PM_EVENT_AUTO_SUSPEND, })
#define TRBBASER_EL1_UNKN (UL(0))
#define ID_AA64MMFR0_EL1_SNSMEM_MASK GENMASK(15, 12)
#define PMSIDR_EL1_ARCHINST_MASK GENMASK(3, 3)
#define ICACHEF_VPIPT 1
#define CONFIG_COREDUMP 1
#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
#define arch_atomic64_sub_return_release arch_atomic64_sub_return_release
#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
#define MNT_CURSOR 0x10000000
#define ID_ISAR6_EL1_DP_WIDTH 4
#define ID_AA64MMFR2_EL1_ST_MASK GENMASK(31, 28)
#define ARM64_HAS_CACHE_IDC 12
#define UBSAN_BRK_IMM 0x5500
#define HFGITR_EL2_TLBIVAAE1IS_WIDTH 1
#define ETH_P_PPP_SES 0x8864
#define ID_MMFR0_EL1_ShareLvl_ONE UL(0b0000)
#define array_size(a,b) size_mul(a, b)
#define __ARCH_WANT_SET_GET_RLIMIT 
#define LOGLEVEL_SCHED -2
#define ____cacheline_aligned_in_smp ____cacheline_aligned
#define CONFIG_HAVE_ARCH_COMPILER_H 1
#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
#define Q_SETINFO 0x800006
#define arch_atomic_fetch_and_release arch_atomic_fetch_and_release
#define VM_STACK_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS
#define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
#define KUNIT_CASE_ATTR(test_name,attributes) { .run_case = test_name, .name = #test_name, .attr = attributes, .module_name = KBUILD_MODNAME}
#define TTBRx_EL1_UNKN (UL(0))
#define __count_zid_vm_events(item,zid,delta) __count_vm_events(item ##_NORMAL - ZONE_NORMAL + zid, delta)
#define BITS_TO_LONGS(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(long))
#define SVCR_RES0 (UL(0) | GENMASK_ULL(63, 2))
#define HSIPHASH_PERMUTATION(a,b,c,d) ( (a) += (b), (b) = rol32((b), 5), (b) ^= (a), (a) = rol32((a), 16), (c) += (d), (d) = rol32((d), 8), (d) ^= (c), (a) += (d), (d) = rol32((d), 7), (d) ^= (a), (c) += (b), (b) = rol32((b), 13), (b) ^= (c), (c) = rol32((c), 16))
#define KERNFS_TYPE_MASK 0x000f
#define SCTLR_EL1_EnRCTX_SHIFT 10
#define SYS_CCSIDR_EL1_CRm 0
#define SYS_CCSIDR_EL1_CRn 0
#define MDIO_PMA_STAT2_TXFLTABLE 0x2000
#define current_pt_regs() task_pt_regs(current)
#define ID_AA64ISAR0_EL1_TME GENMASK(27, 24)
#define MNT_READONLY 0x40
#define SIOCGSTAMP_OLD 0x8906
#define __phys_to_kimg(x) ((unsigned long)((x) + kimage_voffset))
#define IFF_LOOPBACK IFF_LOOPBACK
#define AARCH64_DBG_WRITE(N,REG,VAL) do { write_sysreg(VAL, dbg ##REG ##N ##_el1);} while (0)
#define ID_AA64MMFR3_EL1_SDERR_MASK GENMASK(55, 52)
#define CONFIG_KALLSYMS_BASE_RELATIVE 1
#define ID_ISAR3_EL1_TrueNOP_NI UL(0b0000)
#define PARITY_CRC16_PR0_CCITT 4
#define HFGITR_EL2_TLBIVMALLE1IS_WIDTH 1
#define SMPRIMAP_EL2_P14_WIDTH 4
#define HDFGWTR_EL2_PMBSR_EL1_SHIFT 25
#define MVFR1_EL1_SIMDLS_NI UL(0b0000)
#define ADVERTISE_LPACK 0x4000
#define ID_AFR0_EL1_IMPDEF3_WIDTH 4
#define TLBI_TTL_MASK GENMASK_ULL(47, 44)
#define __pmd(x) ((pmd_t) { (x) } )
#define this_cpu_xchg_2(pcp,val) _pcp_protect_return(xchg_relaxed, pcp, val)
#define RCU_DONE_TAIL 0
#define ID_MMFR1_EL1_L1Hvd_INVALIDATE UL(0b0010)
#define ID_AA64ISAR1_EL1_APA_SHIFT 4
#define CPULIST_FILE_MAX_BYTES (((NR_CPUS * 7)/2 > PAGE_SIZE) ? (NR_CPUS * 7)/2 : PAGE_SIZE)
#define DCZID_EL0_DZP_SHIFT 4
#define compat_usr(x) regs[(x)]
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
#define CONFIG_ARCH_HAS_ZONE_DMA_SET 1
#define VTCR_EL2_RES1 (1U << 31)
#define _TIF_SVE (1 << TIF_SVE)
#define SYS_ID_MMFR1_EL1_CRm 1
#define SYS_ID_MMFR1_EL1_CRn 0
#define O_NOATIME 01000000
#define this_cpu_xchg_4(pcp,val) _pcp_protect_return(xchg_relaxed, pcp, val)
#define R_AARCH64_MOVW_SABS_G0 270
#define R_AARCH64_MOVW_SABS_G1 271
#define R_AARCH64_MOVW_SABS_G2 272
#define IS_AUTOMOUNT(inode) ((inode)->i_flags & S_AUTOMOUNT)
#define ___htons(x) __cpu_to_be16(x)
#define SCTLR_EL1_SED_WIDTH 1
#define SO_RXQ_OVFL 40
#define FTR_HIDDEN false
#define HDFGRTR_EL2_TRBTRG_EL1 GENMASK(56, 56)
#define SYS_ID_PFR1_EL1_CRm 1
#define SYS_ID_PFR1_EL1_CRn 0
#define CONFIG_CONSOLE_LOGLEVEL_QUIET 4
#define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
#define HFGxTR_EL2_nMAIR2_EL1_WIDTH 1
#define CONFIG_GENERIC_SCHED_CLOCK 1
#define __local64_sub(i,l) local64_set((l), local64_read(l) - (i))
#define _PAGE_KERNEL_EXEC (PROT_NORMAL & ~PTE_PXN)
#define CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ 1
#define DT_NEEDED 1
#define SHM_HUGE_512MB HUGETLB_FLAG_ENCODE_512MB
#define __UINTMAX_C(c) c ## UL
#define ESTATUS_1000_XFULL 0x8000
#define TRACE_FTRACE_START TRACE_FTRACE_BIT
#define ID_AA64MMFR2_EL1_BBM_MASK GENMASK(55, 52)
#define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
#define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
#define pm_generic_resume_early NULL
#define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
#define __ATTR_WO(_name) { .attr = { .name = __stringify(_name), .mode = 0200 }, .store = _name ##_store, }
#define __ALIGN .balign CONFIG_FUNCTION_ALIGNMENT
#define ID_AA64ISAR2_EL1_GPA3_MASK GENMASK(11, 8)
#define PR_GET_TAGGED_ADDR_CTRL 56
#define MAY_READ 0x00000004
#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
#define MDIO_MMD_PHYXS 4
#define __TIMER_INITIALIZER(_function,_flags) { .entry = { .next = TIMER_ENTRY_STATIC }, .function = (_function), .flags = (_flags), __TIMER_LOCKDEP_MAP_INITIALIZER(FILE_LINE) }
#define VFS_CAP_REVISION_SHIFT 24
#define SO_PEERPIDFD 77
#define SIGWINCH 28
#define ID_AA64PFR1_EL1_PFAR_NI UL(0b0000)
#define IPV6_2292RTHDR 5
#define FWNODE_FLAG_NEEDS_CHILD_BOUND_ON_ADD BIT(3)
#define _PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
#define ID_AA64ISAR1_EL1_SPECRES_NI UL(0b0000)
#define __NR_sched_rr_get_interval 127
#define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
#define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
#define write_lock(lock) _raw_write_lock(lock)
#define ETH_P_X25 0x0805
#define AT_EGID 14
#define ETH_P_CANFD 0x000D
#define ID_AA64MMFR0_EL1_TGRAN64_2 GENMASK(39, 36)
#define HDFGWTR_EL2_PMCCFILTR_EL0_WIDTH 1
#define arch_wants_old_prefaulted_pte cpu_has_hw_af
#define fl4_gre_key uli.gre_key
#define ENAVAIL 119
#define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
#define MAPLE_NODE_TYPE_SHIFT 0x03
#define arch_update_cpu_topology topology_update_cpu_topology
#define PMBLIMITR_EL1_LIMIT_MASK GENMASK(63, 12)
#define HFGITR_EL2_nGCSEPP_SHIFT 59
#define HDFGWTR_EL2_DBGBCRn_EL1_MASK GENMASK(0, 0)
#define __NR_rt_sigsuspend 133
#define ETHTOOL_GLINK 0x0000000a
#define CONFIG_SWIOTLB 1
#define CONFIG_WLAN_VENDOR_ADMTEK 1
#define NUM_ACTIVE_RCU_POLL_OLDSTATE 2
#define SKB_ALLOC_FCLONE 0x01
#define NT_PPC_VSX 0x102
#define SECTION_NR_TO_ROOT(sec) ((sec) / SECTIONS_PER_ROOT)
#define SHT_LOPROC 0x70000000
#define plist_for_each_entry_continue(pos,head,m) list_for_each_entry_continue(pos, &(head)->node_list, m.node_list)
#define pud_access_permitted(pud,write) (pte_access_permitted(pud_pte(pud), (write)))
#define SB_I_USERNS_VISIBLE 0x00000010
#define DACR32_EL2_D4_MASK GENMASK(9, 8)
#define NOMMU_MAP_COPY 0x00000001
#define _LINUX_ARGS_H 
#define ID_ISAR4_EL1_PSR_M_SHIFT 24
#define ARM64_HAS_RAS_EXTN 40
#define PFC_STORM_PREVENTION_AUTO 0xffff
#define printk_index_wrap(_p_func,_fmt,...) ({ __printk_index_emit(_fmt, NULL, NULL); _p_func(_fmt, ##__VA_ARGS__); })
#define BUS_ATTR_RO(_name) struct bus_attribute bus_attr_ ##_name = __ATTR_RO(_name)
#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800
#define MDIO_USXGMII_DPX_SPD_MASK 0x1e00
#define SYS_FIELD_PREP(reg,field,val) FIELD_PREP(reg ##_ ##field ##_MASK, val)
#define __IDR_H__ 
#define BUS_ATTR_RW(_name) struct bus_attribute bus_attr_ ##_name = __ATTR_RW(_name)
#define NUM_RCU_LVL_0 1
#define NUM_RCU_LVL_1 DIV_ROUND_UP(NR_CPUS, RCU_FANOUT_1)
#define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
#define OBJPOOL_NR_OBJECT_MAX (1UL << 24)
#define __GFP_MEMALLOC ((__force gfp_t)___GFP_MEMALLOC)
#define NMI_SHIFT (HARDIRQ_SHIFT + HARDIRQ_BITS)
#define TTBRx_EL1_ASID GENMASK(63, 48)
#define MINOR(dev) ((unsigned int) ((dev) & MINORMASK))
#define CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 1
#define ID_ISAR1_EL1_Endian GENMASK(3, 0)
#define ID_AA64ISAR0_EL1_SHA3_SIGNED false
#define lockdep_assert_in_irq() do { WARN_ON_ONCE(__lockdep_enabled && !this_cpu_read(hardirq_context)); } while (0)
#define RATE_MATCH_NONE 0
#define SYS_ID_ISAR6_EL1_Op2 7
#define HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT 12
#define O_SYNC (__O_SYNC|O_DSYNC)
#define KUNIT_EXPECT_EQ(test,left,right) KUNIT_EXPECT_EQ_MSG(test, left, right, NULL)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
#define F_SETSIG 10
#define __NR_getxattr 8
#define CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC 1
#define MDSCR_EL1_RXO GENMASK(27, 27)
#define SCTLR_EL1_ITFSB GENMASK(37, 37)
#define SYS_PMSFCR_EL1_Op2 4
#define HFGxTR_EL2_APIAKey_WIDTH 1
#define PMSIDR_EL1_INTERVAL_SHIFT 8
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
#define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
#define XA_FLAGS_MARK(mark) ((__force gfp_t)((1U << __GFP_BITS_SHIFT) << (__force unsigned)(mark)))
#define PMSIDR_EL1_ARCHINST_SHIFT 3
#define MVFR0_EL1_FPTrap_WIDTH 4
#define ID_AA64MMFR3_EL1_SCTLRX_MASK GENMASK(7, 4)
#define MDIO_PMA_10T1L_CTRL_LB_EN 0x0001
#define ID_ISAR6_EL1_JSCVT_NI UL(0b0000)
#define HDFGWTR_EL2_PMSELR_EL0 GENMASK(19, 19)
#define ID_MMFR3_EL1_PAN_PAN UL(0b0001)
#define cpu_present_mask ((const struct cpumask *)&__cpu_present_mask)
#define SCTLR_EL1_EnIA_WIDTH 1
#define __DEFINE_ASM_GPR_NUMS "	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" "	.equ	.L__gpr_num_x\\num, \\num\n" "	.equ	.L__gpr_num_w\\num, \\num\n" "	.endr\n" "	.equ	.L__gpr_num_xzr, 31\n" "	.equ	.L__gpr_num_wzr, 31\n"
#define ETH_P_IPX 0x8137
#define NT_PPC_TM_CDSCR 0x10f
#define IPC_PRIVATE ((__kernel_key_t) 0)
#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII)
#define raw_local_irq_disable() arch_local_irq_disable()
#define HFGxTR_EL2_AFSR0_EL1_WIDTH 1
#define time_before(a,b) time_after(b,a)
#define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
#define _ARM_KPROBES_H 
#define time_is_after_jiffies(a) time_before(jiffies, a)
#define hweight16(w) (__builtin_constant_p(w) ? __const_hweight16(w) : __arch_hweight16(w))
#define XA_FREE_MARK XA_MARK_0
#define pr_info_once(fmt,...) printk_once(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__)
#define wake_up(x) __wake_up(x, TASK_NORMAL, 1, NULL)
#define TPIDR_EL1_ThreadID_WIDTH 64
#define ioremap ioremap
#define CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE 1
#define raw_spin_lock_nested(lock,subclass) _raw_spin_lock_nested(lock, subclass)
#define arch_phys_wc_index arch_phys_wc_index
#define ID_AA64ISAR2_EL1_CSSC_MASK GENMASK(55, 52)
#define Q_XQUOTARM XQM_CMD(6)
#define LMI_DEFAULT 0
#define TESTSETFLAG(uname,lname,policy) static __always_inline bool folio_test_set_ ##lname(struct folio *folio) { return test_and_set_bit(PG_ ##lname, folio_flags(folio, FOLIO_ ##policy)); } static __always_inline int TestSetPage ##uname(struct page *page) { return test_and_set_bit(PG_ ##lname, &policy(page, 1)->flags); }
#define print_hex_dump_bytes(prefix_str,prefix_type,buf,len) print_hex_dump_debug(prefix_str, prefix_type, 16, 1, buf, len, true)
#define MODULE_INFO(tag,info) __MODULE_INFO(tag, tag, info)
#define SPEED_100 100
#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1 GENMASK(6, 6)
#define __pud(x) ((pud_t) { __p4d(x) })
#define __diag_GCC_ignore ignored
#define ID_ISAR4_EL1_WithShifts_LSL3 UL(0b0001)
#define __LINUX_COMPILER_TYPES_H 
#define ID_AA64ISAR0_EL1_TLB GENMASK(59, 56)
#define ID_AA64ISAR0_EL1_TME_IMP UL(0b0001)
#define ID_AA64ISAR2_EL1_CLRBHB_WIDTH 4
#define ID_AA64ISAR2_EL1_APA3_SIGNED false
#define ID_MMFR5_EL1_ETS_MASK GENMASK(3, 0)
#define ID_ISAR6_EL1_SPECRES_NI UL(0b0000)
#define TTBRx_EL1_CnP_MASK GENMASK(0, 0)
#define ARM_CPU_PART_NEOVERSE_V1 0xD40
#define this_cpu_add(pcp,val) __pcpu_size_call(this_cpu_add_, pcp, val)
#define list_for_each_entry_reverse(pos,head,member) for (pos = list_last_entry(head, typeof(*pos), member); !list_entry_is_head(pos, head, member); pos = list_prev_entry(pos, member))
#define CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN 1
#define ID_AA64DFR0_EL1_WRPs GENMASK(23, 20)
#define MT_FLAGS_LOCK_MASK 0x300
#define wait_event_interruptible(wq_head,condition) ({ int __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_event_interruptible(wq_head, condition); __ret; })
#define SHT_LOUSER 0x80000000
#define HFGITR_EL2_TLBIRVALE1IS_WIDTH 1
#define hweight32(w) (__builtin_constant_p(w) ? __const_hweight32(w) : __arch_hweight32(w))
#define HFGITR_EL2_TLBIRVAE1OS_MASK GENMASK(24, 24)
#define IPV6_RECVPATHMTU 60
#define ID_MMFR1_EL1_L1UniSW GENMASK(15, 12)
#define uarg_to_msgzc(ubuf_ptr) container_of((ubuf_ptr), struct ubuf_info_msgzc, ubuf)
#define CONFIG_AS_HAS_ARMV8_2 1
#define CONFIG_AS_HAS_ARMV8_3 1
#define CONFIG_AS_HAS_ARMV8_4 1
#define lock_map_acquire(l) lock_acquire_exclusive(l, 0, 0, NULL, _THIS_IP_)
#define CTR_EL0_DminLine GENMASK(19, 16)
#define CLONE_LEGACY_FLAGS 0xffffffffULL
#define EAFNOSUPPORT 97
#define BUS_ATTR_WO(_name) struct bus_attribute bus_attr_ ##_name = __ATTR_WO(_name)
#define barrier() __asm__ __volatile__("": : :"memory")
#define PR_PAC_ENABLED_KEYS_MASK (PR_PAC_APIAKEY | PR_PAC_APIBKEY | PR_PAC_APDAKEY | PR_PAC_APDBKEY)
#define DN_CREATE 0x00000004
#define PIE_RX_O 0x3
#define ARM64_BTI 2
#define ISR_EL1_FS_SHIFT 9
#define __NR_getsid 156
#define ID_AA64ISAR1_EL1_FRINTTS GENMASK(35, 32)
#define CLD_CONTINUED 6
#define CONFIG_ARCH_HAS_FORTIFY_SOURCE 1
#define skb_checksum_validate(skb,proto,compute_pseudo) __skb_checksum_validate(skb, proto, true, false, 0, compute_pseudo)
#define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
#define suspend_report_result(dev,fn,ret) do {} while (0)
#define ID_MMFR3_EL1_MaintBcst_ALL UL(0b0010)
#define ID_AA64AFR0_EL1_IMPDEF7_SHIFT 28
#define CPACR_EL1_TTA (1 << 28)
#define HDFGWTR_EL2_TRBSR_EL1 GENMASK(55, 55)
#define __LINUX_SEQLOCK_H 
#define TTBRx_EL1_CnP GENMASK(0, 0)
#define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
#define STATIC_LOCKDEP_MAP_INIT(_name,_key) { .name = (_name), .key = (void *)(_key), }
#define HDFGRTR_EL2_OSLSR_EL1_SHIFT 9
#define ARM64_HAS_CNP 13
#define file_count(x) atomic_long_read(&(x)->f_count)
#define HFGITR_EL2_ATS1E0W_MASK GENMASK(15, 15)
#define TAINT_AUX 16
#define PMBSR_EL1_DL_WIDTH 1
#define ELFCLASS64 2
#define for_each_online_cpu(cpu) for_each_cpu((cpu), cpu_online_mask)
#define __notrace_funcgraph 
#define RATELIMIT_MSG_ON_RELEASE BIT(0)
#define PIRx_ELx_Perm11_WIDTH 4
#define PAR_TO_HPFAR(par) (((par) & GENMASK_ULL(52 - 1, 12)) >> 8)
#define HDFGWTR_EL2_TRBMAR_EL1_WIDTH 1
#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36
#define NETIF_F_GSO_UDP_L4 __NETIF_F(GSO_UDP_L4)
#define ID_ISAR3_EL1_SIMD_PKHBT UL(0b0011)
#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
#define IRQF_NO_THREAD 0x00010000
#define EX_DATA_REG_ADDR_SHIFT 5
#define DCZID_EL0_BS_SHIFT 0
#define __NR_shmat 196
#define hweight64(w) (__builtin_constant_p(w) ? __const_hweight64(w) : __arch_hweight64(w))
#define static_branch_enable(x) static_key_enable(&(x)->key)
#define __msr_s(r,v) DEFINE_MSR_S "	msr_s " __stringify(r) ", " v "\n" UNDEFINE_MSR_S
#define PF_MEMALLOC_NOIO 0x00080000
#define MDIO_DEVID2 MII_PHYSID2
#define ETHTOOL_GMSGLVL 0x00000007
#define SYS_OSDTRRX_EL1_CRn 0
#define CONFIG_APPLE_DART 1
#define PR_FPEMU_SIGFPE 2
#define ID_AA64ISAR0_EL1_SHA2_MASK GENMASK(15, 12)
#define CONFIG_I2C_HELPER_AUTO 1
#define HFGxTR_EL2_AFSR0_EL1 GENMASK(0, 0)
#define ID_ISAR3_EL1_Saturate_MASK GENMASK(3, 0)
#define NETLINK_PKTINFO 3
#define I_WB_SWITCH (1 << 13)
#define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
#define __raw_writeb __raw_writeb
#define CSSELR_EL1_InD_SHIFT 0
#define CONFIG_CMA_SIZE_MBYTES 128
#define CONFIG_VGA_ARB 1
#define module_param_hw_named(name,value,type,hwtype,perm) param_check_ ##type(name, &(value)); __module_param_call(MODULE_PARAM_PREFIX, name, &param_ops_ ##type, &value, perm, -1, KERNEL_PARAM_FL_HWPARAM | (hwparam_ ##hwtype & 0)); __MODULE_PARM_TYPE(name, #type)
#define _LINUX_MATH_H 
#define IRQ_STACK_SIZE THREAD_SIZE
#define LED_BLINK_SW 0
#define IOPRIO_PRIO_CLASS(ioprio) (((ioprio) >> IOPRIO_CLASS_SHIFT) & IOPRIO_CLASS_MASK)
#define MHI_EP_DEVICE_MODALIAS_FMT "mhi_ep:%s"
#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)
#define ID_AA64MMFR0_EL1_TGRAN64_IMP UL(0b0000)
#define PMBPTR_EL1_UNKN (UL(0))
#define HFGITR_EL2_DCCISW_MASK GENMASK(6, 6)
#define PAGE_SHIFT CONFIG_ARM64_PAGE_SHIFT
#define HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT 13
#define timers_dead_cpu NULL
#define CONFIG_GENERIC_CPU_VULNERABILITIES 1
#define PR_RISCV_V_VSTATE_CTRL_CUR_MASK 0x3
#define atomic_dec_and_lock(atomic,lock) __cond_lock(lock, _atomic_dec_and_lock(atomic, lock))
#define wait_event_freezable_timeout(wq_head,condition,timeout) ({ long __ret = timeout; might_sleep(); if (!___wait_cond_timeout(condition)) __ret = __wait_event_freezable_timeout(wq_head, condition, timeout); __ret; })
#define CAP_OPT_NONE 0x0
#define iowrite8_rep iowrite8_rep
#define this_cpu_add_return_1(pcp,val) _pcp_protect_return(__percpu_add_return_case_8, pcp, val)
#define this_cpu_add_return_2(pcp,val) _pcp_protect_return(__percpu_add_return_case_16, pcp, val)
#define this_cpu_add_return_4(pcp,val) _pcp_protect_return(__percpu_add_return_case_32, pcp, val)
#define this_cpu_add_return_8(pcp,val) _pcp_protect_return(__percpu_add_return_case_64, pcp, val)
#define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
#define unregister_ftrace_function(ops) ({ 0; })
#define ETHTOOL_GDRVINFO 0x00000003
#define time_before32(b,a) time_after32(a, b)
#define CONFIG_DNOTIFY 1
#define compat_r11_fiq regs[27]
#define SIOCSPGRP 0x8902
#define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
#define PMSCR_EL1_E0SPE_WIDTH 1
#define ID_AA64SMFR0_EL1_B16F32_NI UL(0b0)
#define mp_bvec_iter_page_idx(bvec,iter) (mp_bvec_iter_offset((bvec), (iter)) / PAGE_SIZE)
#define NT_PPC_VMX 0x100
#define SYS_CTR_EL0_CRm 0
#define ID_AA64ISAR1_EL1_DGH_WIDTH 4
#define MDIO_PMA_SPEED_1000 0x0010
#define ADJ_FREQUENCY 0x0002
#define skb_checksum_simple_validate(skb) __skb_checksum_validate(skb, 0, true, false, 0, null_compute_pseudo)
#define pgd_offset_gate(mm,addr) pgd_offset(mm, addr)
#define NULL ((void *)0)
#define PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
#define SO_BSDCOMPAT 14
#define p4d_free(mm,x) do { } while (0)
#define pr_debug_ratelimited(fmt,...) no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
#define __this_cpu_write(pcp,val) ({ __this_cpu_preempt_check("write"); raw_cpu_write(pcp, val); })
#define __put_mem_asm(store,reg,x,addr,err,type) asm volatile( "1:	" store "	" reg "1, [%2]\n" "2:\n" _ASM_EXTABLE_ ##type ##ACCESS_ERR(1b, 2b, %w0) : "+r" (err) : "rZ" (x), "r" (addr))
#define IPV6_PMTUDISC_DO 2
#define IPV6_RTHDRDSTOPTS 55
#define __NR_io_pgetevents 292
#define SYS_SETSOCKOPT 14
#define MDIO_PHY_ID_C45 0x8000
#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
#define mutex_lock_interruptible(lock) mutex_lock_interruptible_nested(lock, 0)
#define KERNEL_HWCAP_BF16 __khwcap2_feature(BF16)
#define ID_AA64PFR0_EL1_AMU_V1P1 UL(0b0010)
#define CONFIG_SOUND 1
#define SCHED_FLAG_DL_OVERRUN 0x04
#define TAINT_RANDSTRUCT 17
#define CONFIG_ARCH_SUPPORTS_INT128 1
#define EM_CYGNUS_M32R 0x9041
#define HFGITR_EL2_TLBIVMALLE1OS_MASK GENMASK(18, 18)
#define DEFAULT_POLLMASK (EPOLLIN | EPOLLOUT | EPOLLRDNORM | EPOLLWRNORM)
#define ID_AA64PFR1_EL1_SSBS_MASK GENMASK(7, 4)
#define __NR_sched_setaffinity 122
#define MDIO_PCS_STAT2_10GBX 0x0002
#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
#define ID_AA64PFR0_EL1_RAS_MASK GENMASK(31, 28)
#define raw_spin_trylock_bh(lock) __cond_lock(lock, _raw_spin_trylock_bh(lock))
#define SEGCBLIST_OFFLOADED BIT(5)
#define time_between32(t,l,h) ((u32)(h) - (u32)(l) >= (u32)(t) - (u32)(l))
#define NR_KERNFS_LOCKS (1 << NR_KERNFS_LOCK_BITS)
#define ID_AA64MMFR1_EL1_PAN GENMASK(23, 20)
#define DIV64_U64_ROUND_CLOSEST(dividend,divisor) ({ u64 _tmp = (divisor); div64_u64((dividend) + _tmp / 2, _tmp); })
#define TRBSR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 56) | GENMASK_ULL(25, 24) | GENMASK_ULL(19, 19) | GENMASK_ULL(16, 16))
#define TRBSR_EL1_RES1 (UL(0))
#define read_seqcount_begin(s) ({ seqcount_lockdep_reader_access(seqprop_const_ptr(s)); raw_read_seqcount_begin(s); })
#define SHT_HIPROC 0x7fffffff
#define DEFINE_PER_CPU_FIRST(type,name) DEFINE_PER_CPU_SECTION(type, name, PER_CPU_FIRST_SECTION)
#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32
#define JBD_POISON_FREE 0x5b
#define d_lock d_lockref.lock
#define ADVERTISED_56000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseKR4_Full)
#define __HDFGWTR_EL2_MASK ~__HDFGWTR_EL2_nMASK
#define MHI_DEVICE_MODALIAS_FMT "mhi:%s"
#define PACKET_TIMESTAMP 17
#define ID_DFR0_EL1_PerfMon_PMUv3p1 UL(0b0100)
#define PR_FP_MODE_FR (1 << 0)
#define ID_DFR0_EL1_PerfMon_PMUv3p4 UL(0b0101)
#define ID_DFR0_EL1_PerfMon_PMUv3p5 UL(0b0110)
#define preempt_count_inc() preempt_count_add(1)
#define ID_DFR0_EL1_PerfMon_PMUv3p8 UL(0b1000)
#define __no_stack_protector __attribute__((__no_stack_protector__))
#define IRQF_NO_SUSPEND 0x00004000
#define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
#define CONFIG_RCU_TRACE 1
#define in_atomic_preempt_off() (preempt_count() != PREEMPT_DISABLE_OFFSET)
#define ETH_MIN_MTU 68
#define CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE 1
#define KUNIT_FAIL_ASSERTION(test,assert_type,fmt,...) _KUNIT_FAILED(test, assert_type, kunit_fail_assert, kunit_fail_assert_format, {}, fmt, ##__VA_ARGS__)
#define ESTATUS_1000_TFULL 0x2000
#define MDSCR_EL1_EHBWE GENMASK(35, 35)
#define ARM64_WORKAROUND_1902691 74
#define ARCH_PAGE_TABLE_SYNC_MASK 0
#define AF_SNA 22
#define MDIO_PMA_CTRL2_10BT 0x000f
#define ALTERNATIVE_CB(oldinstr,cpucap,cb) __ALTERNATIVE_CFG_CB(oldinstr, (1 << ARM64_CB_SHIFT) | (cpucap), 1, cb)
#define HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT 23
#define pgoff_t unsigned long
#define HFGxTR_EL2_ERXADDR_EL1_WIDTH 1
#define P4D_TYPE_MASK (_AT(p4dval_t, 3) << 0)
#define CONFIG_WLAN_VENDOR_QUANTENNA 1
#define SMPRI_EL1_UNKN (UL(0))
#define PTE_PXN (_AT(pteval_t, 1) << 53)
#define ID_PFR2_EL1_RAS_frac_SHIFT 8
#define REG_SMCR_EL1 S3_0_C1_C2_6
#define REG_SMCR_EL2 S3_4_C1_C2_6
#define CLOCK_INT 2
#define _LINUX_INSTRUCTION_POINTER_H 
#define ID_MMFR3_EL1_MaintBcst GENMASK(15, 12)
#define ID_ISAR0_EL1_BitField_MASK GENMASK(11, 8)
#define READ 0
#define ETHTOOL_GEEE 0x00000044
#define MMF_VM_MERGEABLE 16
#define ID_ISAR2_EL1_MemHint_SHIFT 4
#define HDFGRTR_EL2_PMCCNTR_EL0 GENMASK(15, 15)
#define __I_DIO_WAKEUP 9
#define ADVERTISED_40000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseLR4_Full)
#define COMPAT_HWCAP_EVTSTRM (1 << 21)
#define ID_AA64ISAR0_EL1_RNDR_IMP UL(0b0001)
#define CONFIG_NET_VENDOR_CADENCE 1
#define KTIME_MAX ((s64)~((u64)1 << 63))
#define CONSOLE_LOGLEVEL_SILENT 0
#define TRBLIMITR_EL1_RES0 (UL(0) | GENMASK_ULL(11, 7))
#define TRBLIMITR_EL1_RES1 (UL(0))
#define SYS_SMPRI_EL1_CRm 2
#define ID_AA64AFR0_EL1_IMPDEF6_MASK GENMASK(27, 24)
#define _DPRINTK_CLASS_DFLT ((1 << CLS_BITS) - 1)
#define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
#define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
#define XA_FLAGS_ACCOUNT ((__force gfp_t)32U)
#define ESR_ELx_SRT_SHIFT (16)
#define SYS_PIR_EL2_CRn 10
#define TIF_MEMDIE 18
#define POLLRDNORM 0x0040
#define F_SEAL_EXEC 0x0020
#define CONFIG_RTC_HCTOSYS_DEVICE "rtc0"
#define SYS_LORN_EL1_Op0 3
#define SYS_LORN_EL1_Op1 0
#define SYS_LORN_EL1_Op2 2
#define ESR_ELx_FSC_SECC (0x18)
#define raw_cpu_inc(pcp) raw_cpu_add(pcp, 1)
#define ID_AA64ISAR0_EL1_SHA2_SHIFT 12
#define PIRx_ELx_Perm1_MASK GENMASK(7, 4)
#define TTBRx_EL1_ASID_SHIFT 48
#define ID_AA64PFR0_EL1_SEL2_SIGNED false
#define __NR_signalfd4 74
#define USB_DEVICE_ID_MATCH_INT_CLASS 0x0080
#define write_lock_nested(lock,subclass) _raw_write_lock_nested(lock, subclass)
#define raw_cmpxchg64_local arch_cmpxchg64_local
#define write_seqcount_begin(s) do { seqprop_assert(s); if (seqprop_preemptible(s)) preempt_disable(); do_write_seqcount_begin(seqprop_ptr(s)); } while (0)
#define ID_AA64ISAR0_EL1_FHM_IMP UL(0b0001)
#define MT_FLAGS_USE_RCU 0x02
#define PMSNEVFR_EL1_E_WIDTH 64
#define INVALID_VFSGID VFSGIDT_INIT(INVALID_GID)
#define PCPU_MIN_ALLOC_SIZE (1 << PCPU_MIN_ALLOC_SHIFT)
#define PF_ECONET AF_ECONET
#define FS_XFLAG_NODEFRAG 0x00002000
#define SYS_OSECCR_EL1_CRm 6
#define SYS_OSECCR_EL1_CRn 0
#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
#define IS_APPEND(inode) ((inode)->i_flags & S_APPEND)
#define TCR_E0PD0 (UL(1) << 55)
#define TCR_E0PD1 (UL(1) << 56)
#define HCRX_EL2_TALLINT GENMASK(6, 6)
#define container_of(ptr,type,member) ({ void *__mptr = (void *)(ptr); static_assert(__same_type(*(ptr), ((type *)0)->member) || __same_type(*(ptr), void), "pointer type mismatch in container_of()"); ((type *)(__mptr - offsetof(type, member))); })
#define __ASM_PTRACE_H 
#define SYS_PAR_EL1_FST GENMASK(6, 1)
#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44
#define list_next_entry(pos,member) list_entry((pos)->member.next, typeof(*(pos)), member)
#define ID_ISAR2_EL1_PSR_AR GENMASK(27, 24)
#define XATTR_CAPS_SZ XATTR_CAPS_SZ_3
#define HWCAP2_SME_F16F16 (1UL << 42)
#define _LINUX_SCHED_TYPES_H 
#define REG_ID_ISAR0_EL1 S3_0_C0_C2_0
#define EDEADLK 35
#define SLAB_CACHE_DMA ((slab_flags_t __force)0x00004000U)
#define SHT_HIUSER 0xffffffff
#define STATX_MODE 0x00000002U
#define HDFGRTR_EL2_TRCIMSPECn_MASK GENMASK(41, 41)
#define TCR_TBI0 (UL(1) << 37)
#define TCR_TBI1 (UL(1) << 38)
#define ptrauth_strip_user_insn_pac(ptr) (ptr)
#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
#define MNT_DETACH 0x00000002
#define wait_event_interruptible_lock_irq_timeout(wq_head,condition,lock,timeout) ({ long __ret = timeout; if (!___wait_cond_timeout(condition)) __ret = __wait_event_lock_irq_timeout( wq_head, condition, lock, timeout, TASK_INTERRUPTIBLE); __ret; })
#define key_get(k) ({ NULL; })
#define SPEED_5000 5000
#define core_param_cb(name,ops,arg,perm) __level_param_cb(name, ops, arg, perm, 1)
#define SO_TIMESTAMPING_NEW 65
#define CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1
#define SYS_TTBR1_EL1_CRm 0
#define SYS_TTBR1_EL1_CRn 2
#define _PAGE_KERNEL (PROT_NORMAL)
#define ID_MMFR2_EL1_L1HvdBG_NI UL(0b0000)
#define UUID_STRING_LEN 36
#define TRBIDR_EL1_P GENMASK(4, 4)
#define _LINUX_ERR_H 
#define SCTLR_ELx_ENIA_SHIFT 31
#define ___GFP_MEMALLOC 0x20000u
#define _LINUX_SOCKIOS_H 
#define ICH_VTR_TDS_SHIFT 19
#define list_entry_is_head(pos,head,member) (&pos->member == (head))
#define SIGCHLD 17
#define MODULE_IMPORT_NS(ns) MODULE_INFO(import_ns, __stringify(ns))
#define NETLINK_CAP_ACK 10
#define _UAPI__LINUX_MII_H__ 
#define ID_AA64SMFR0_EL1_FA64_SHIFT 63
#define SECCOMP_FILTER_FLAG_MASK (SECCOMP_FILTER_FLAG_TSYNC | SECCOMP_FILTER_FLAG_LOG | SECCOMP_FILTER_FLAG_SPEC_ALLOW | SECCOMP_FILTER_FLAG_NEW_LISTENER | SECCOMP_FILTER_FLAG_TSYNC_ESRCH | SECCOMP_FILTER_FLAG_WAIT_KILLABLE_RECV)
#define ID_AA64MMFR2_EL1_EVT GENMASK(59, 56)
#define PMSCR_EL2_PCT_GUEST UL(0b11)
#define MII_TPISTATUS 0x1b
#define local_dec_and_test(l) atomic_long_dec_and_test(&(l)->a)
#define PID_MAX_DEFAULT (CONFIG_BASE_SMALL ? 0x1000 : 0x8000)
#define _LINUX_JUMP_LABEL_H 
#define SIGSTOP 19
#define ktime_add(lhs,rhs) ((lhs) + (rhs))
#define EPOLLNVAL (__force __poll_t)0x00000020
#define LED_COLOR_ID_RED 1
#define __exit_p(x) NULL
#define HDFGWTR_EL2_DBGWVRn_EL1 GENMASK(3, 3)
#define LEDS_TRIG_TYPE_EDGE 0
#define EM_SPARC32PLUS 18
#define ISHTP_MODULE_PREFIX "ishtp:"
#define ID_AA64AFR0_EL1_UNKN (UL(0))
#define __NR_umount2 39
#define RCU_FANOUT_1 (RCU_FANOUT_LEAF)
#define ID_MMFR1_EL1_L1UniVA_CLEAN_AND_INVALIDATE UL(0b0001)
#define RCU_FANOUT_3 (RCU_FANOUT_2 * RCU_FANOUT)
#define RCU_FANOUT_4 (RCU_FANOUT_3 * RCU_FANOUT)
#define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2)
#define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
#define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
#define CONFIG_SLUB 1
#define VM_UFFD_MINOR VM_NONE
#define ID_AA64PFR0_EL1_RAS_IMP UL(0b0001)
#define EXTEND_CLASS(_name,ext,_init,_init_args...) typedef class_ ##_name ##_t class_ ##_name ##ext ##_t; static inline void class_ ##_name ##ext ##_destructor(class_ ##_name ##_t *p){ class_ ##_name ##_destructor(p); } static inline class_ ##_name ##_t class_ ##_name ##ext ##_constructor(_init_args) { class_ ##_name ##_t t = _init; return t; }
#define REG_TCR2_EL12 S3_5_C2_C0_3
#define per_cpu_offset(x) (__per_cpu_offset[x])
#define CONFIG_GPIOLIB_FASTPATH_LIMIT 512
#define HZ_TO_MSEC_MUL32 U64_C(0x80000000)
#define XAS_RESTART ((struct xa_node *)3UL)
#define CONFIG_HAS_DMA 1
#define SUID_DUMP_USER 1
#define PMBIDR_EL1_EA_Ignored UL(0b0001)
#define PTRACE_MODE_READ_FSCREDS (PTRACE_MODE_READ | PTRACE_MODE_FSCREDS)
#define pm_generic_thaw_noirq NULL
#define __ATTR_PREALLOC(_name,_mode,_show,_store) { .attr = {.name = __stringify(_name), .mode = SYSFS_PREALLOC | VERIFY_OCTAL_PERMISSIONS(_mode) }, .show = _show, .store = _store, }
#define ADVERTISED_10baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Full)
#define HDFGWTR_EL2_PMSICR_EL1_WIDTH 1
#define __ASM_PGTABLE_PROT_H 
#define F_WRLCK 1
#define MDIO_PMA_EXTABLE 11
#define __NR_preadv2 286
#define ID_MMFR1_EL1_L1HvdSW_CLEAN_AND_INVALIDATE UL(0b0001)
#define SCTLR_EL1_EOS_WIDTH 1
#define EM_TILEGX 191
#define ID_AA64PFR0_EL1_AdvSIMD_MASK GENMASK(23, 20)
#define ID_AA64MMFR1_EL1_VH_SIGNED false
#define CONFIG_PAGE_SIZE_LESS_THAN_64KB 1
#define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
#define NR_FILE 8192
#define ARCH_TRACE_IGNORE_COMPAT_SYSCALLS 
#define ID_MMFR2_EL1_HWAccFlg GENMASK(31, 28)
#define ID_AA64MMFR3_EL1_ADERR_DEV_ASYNC UL(0b0001)
#define large_cpumask_bits ((unsigned int)NR_CPUS)
#define module_param_unsafe(name,type,perm) module_param_named_unsafe(name, name, type, perm)
#define SIGSYS 31
#define CLIDR_EL1_LoUIS_WIDTH 3
#define PMSCR_EL1_E0SPE_SHIFT 0
#define __CLEARPAGEFLAG_NOOP(uname,lname) static inline void __folio_clear_ ##lname(struct folio *folio) { } static inline void __ClearPage ##uname(struct page *page) { }
#define SECCOMP_RET_ACTION_FULL 0xffff0000U
#define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
#define fwnode_call_int_op(fwnode,op,...) (fwnode_has_op(fwnode, op) ? (fwnode)->ops->op(fwnode, ## __VA_ARGS__) : (IS_ERR_OR_NULL(fwnode) ? -EINVAL : -ENXIO))
#define QSTR_INIT(n,l) { { { .len = l } }, .name = n }
#define DCACHE_SPECIAL_TYPE 0x00500000
#define NETIF_F_LOOPBACK __NETIF_F(LOOPBACK)
#define DT_LOPROC 0x70000000
#define ENXIO 6
#define ADJ_OFFSET_READONLY 0x2000
#define MVFR0_EL1_FPShVec_SIGNED false
#define MDIO_AN_EEE_LPABLE2 63
#define SA_NOCLDSTOP 0x00000001
#define FS_XFLAG_FILESTREAM 0x00004000
#define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
#define __cacheline_group_begin(GROUP) __u8 __cacheline_group_begin__ ##GROUP[0]
#define RX_CLS_LOC_LAST 0xfffffffd
#define LPA_RFAULT 0x2000
#define VM_HUGETLB 0x00400000
#define SECCOMP_IOCTL_NOTIF_SET_FLAGS SECCOMP_IOW(4, __u64)
#define COMPAT_ELF_PLATFORM ("v8l")
#define IS_I_VERSION(inode) __IS_FLG(inode, SB_I_VERSION)
#define CONFIG_SPARSEMEM 1
#define ARM_CPU_PART_CORTEX_A510 0xD46
#define __RCUWAIT_INITIALIZER(name) { .task = NULL, }
#define IORESOURCE_IRQ_WAKECAPABLE (1<<6)
#define KTIME_MIN (-KTIME_MAX - 1)
#define _Q_LOCKED_OFFSET 0
#define ID_PFR0_EL1_CSV2_SHIFT 16
#define ID_AA64MMFR1_EL1_HPDS_WIDTH 4
#define ID_ISAR6_EL1_I8MM_NI UL(0b0000)
#define ETH_P_TDLS 0x890D
#define ID_AA64MMFR3_EL1_S1PIE_SIGNED false
#define ILL_PRVREG 6
#define ID_AA64ISAR1_EL1_JSCVT_MASK GENMASK(15, 12)
#define TPIDR_EL1_RES0 (UL(0))
#define TPIDR_EL1_RES1 (UL(0))
#define SIOCADDDLCI 0x8980
#define __jiffy_arch_data 
#define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
#define SEQCOUNT_DEP_MAP_INIT(lockname) .dep_map = { .name = #lockname }
#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
#define OSDTRTX_EL1_DTRTX_WIDTH 32
#define raw_copy_to_user(to,from,n) ({ unsigned long __actu_ret; uaccess_ttbr0_enable(); __actu_ret = __arch_copy_to_user(__uaccess_mask_ptr(to), (from), (n)); uaccess_ttbr0_disable(); __actu_ret; })
#define CONFIG_DEBUG_RT_MUTEXES 1
#define CONFIG_HAVE_ARCH_HUGE_VMAP 1
#define HDFGWTR_EL2_PMSICR_EL1 GENMASK(29, 29)
#define ID_MMFR2_EL1_L1HvdBG_IMP UL(0b0001)
#define ARM_CPU_PART_CORTEX_A520 0xD80
#define xas_unlock_irqrestore(xas,flags) xa_unlock_irqrestore((xas)->xa, flags)
#define SYS_MVFR1_EL1_Op0 3
#define SYS_MVFR1_EL1_Op1 0
#define SYS_MVFR1_EL1_Op2 1
#define LOREA_EL1_EA_51_48_WIDTH 4
#define __NR_kill 129
#define SMPRIMAP_EL2_P8_MASK GENMASK(35, 32)
#define list_for_each_entry_safe(pos,n,head,member) for (pos = list_first_entry(head, typeof(*pos), member), n = list_next_entry(pos, member); !list_entry_is_head(pos, head, member); pos = n, n = list_next_entry(n, member))
#define ETHTOOL_SRSSH 0x00000047
#define CONFIG_NET_VENDOR_CORTINA 1
#define INVALID_UID KUIDT_INIT(-1)
#define ID_AA64ISAR0_EL1_TS_MASK GENMASK(55, 52)
#define PSR_AA32_PAN_BIT 0x00400000
#define PM_EVENT_FREEZE 0x0001
#define pmd_ERROR(e) pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
#define ARM64_WORKAROUND_2457168 78
#define wait_event_state(wq_head,condition,state) ({ int __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_event_state(wq_head, condition, state); __ret; })
#define FS_DQ_BTIMER (1<<6)
#define pm_generic_freeze NULL
#define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
#define ID_AA64MMFR3_EL1_S1POE_MASK GENMASK(19, 16)
#define SB_I_PERSB_BDI 0x00000200
#define SYS_ID_DFR1_EL1_CRm 3
#define SYS_ID_DFR1_EL1_CRn 0
#define ID_AA64MMFR0_EL1_TGRAN4_MASK GENMASK(31, 28)
#define HDFGRTR_EL2_TRCCLAIM_WIDTH 1
#define TRBSR_EL1_MSS2 GENMASK(55, 32)
#define IORESOURCE_REG 0x00000300
#define ID_MMFR0_EL1_OuterShr GENMASK(11, 8)
#define aligned_be64 __aligned_be64
#define LPA_SGMII_1000FULL 0x1800
#define HWCAP_AES (1 << 3)
#define ID_AA64MMFR1_EL1_HCX_NI UL(0b0000)
#define _ASM_EXTABLE_UACCESS_ERR_ZERO(insn,fixup,err,zero) __DEFINE_ASM_GPR_NUMS __ASM_EXTABLE_RAW(#insn, #fixup, __stringify(EX_TYPE_UACCESS_ERR_ZERO), "(" EX_DATA_REG(ERR, err) " | " EX_DATA_REG(ZERO, zero) ")")
#define ID_DFR0_EL1_PerfMon_NI UL(0b0000)
#define ID_AA64PFR0_EL1_SEL2_WIDTH 4
#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
#define ADVERTISE_SLCT 0x001f
#define SCTLR_EL2_BT (BIT(36))
#define __aligned(x) __attribute__((__aligned__(x)))
#define seqcount_acquire_read(l,s,t,i) lock_acquire_shared_recursive(l, s, t, NULL, i)
#define KUNIT_EXPECT_FALSE(test,condition) KUNIT_EXPECT_FALSE_MSG(test, condition, NULL)
#define ID_AA64ISAR1_EL1_I8MM_SIGNED false
#define ID_ISAR4_EL1_Writeback_NI UL(0b0000)
#define MDIO_PMA_STAT2_10GBLX4 0x0010
#define LRU_FILE 2
#define HCRX_EL2_EnSNERR GENMASK(18, 18)
#define SCTLR_EL1_EnASR_WIDTH 1
#define EM_386 3
#define netif_printk(priv,type,level,dev,fmt,args...) do { if (netif_msg_ ##type(priv)) netdev_printk(level, (dev), fmt, ##args); } while (0)
#define list_prev_entry_circular(pos,head,member) (list_is_first(&(pos)->member, head) ? list_last_entry(head, typeof(*(pos)), member) : list_prev_entry(pos, member))
#define srcu_dereference_check(p,ssp,c) __rcu_dereference_check((p), __UNIQUE_ID(rcu), (c) || srcu_read_lock_held(ssp), __rcu)
#define __LINUX_RWLOCK_TYPES_H 
#define PACKET_TX_RING 13
#define __cmpwait_relaxed(ptr,val) __cmpwait((ptr), (unsigned long)(val), sizeof(*(ptr)))
#define SYS_ZCR_EL2_CRm 2
#define ID_MMFR1_EL1_BPred_BP_INVISIBLE UL(0b0100)
#define ID_MMFR1_EL1_L1HvdVA GENMASK(3, 0)
#define HDFGRTR_EL2_TRBMAR_EL1 GENMASK(53, 53)
#define HVC_FINALISE_EL2 3
#define fl6_icmp_type uli.icmpt.type
#define HFGITR_EL2_TLBIASIDE1 GENMASK(44, 44)
#define TCR2_EL2_AIE_MASK GENMASK(4, 4)
#define RB_EMPTY_NODE(node) ((node)->__rb_parent_color == (unsigned long)(node))
#define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
#define FS_DQ_IWARNS (1<<10)
#define ID_AA64SMFR0_EL1_SMEver_SIGNED false
#define CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS 1
#define __release(x) (void)0
#define HFGxTR_EL2_PAR_EL1_SHIFT 27
#define BIN_ATTR(_name,_mode,_read,_write,_size) struct bin_attribute bin_attr_ ##_name = __BIN_ATTR(_name, _mode, _read, _write, _size)
#define SYS_ISR_EL1_Op0 3
#define SYS_ISR_EL1_Op1 0
#define SYS_ISR_EL1_Op2 0
#define DT_HIOS 0x6ffff000
#define ID_PFR0_EL1_State3_MASK GENMASK(15, 12)
#define ID_AA64ZFR0_EL1_SVEver_IMP UL(0b0000)
#define VM_GROWSDOWN 0x00000100
#define PMBPTR_EL1_PTR_WIDTH 64
#define HDFGRTR_EL2_TRBBASER_EL1_MASK GENMASK(50, 50)
#define PORT_OTHER 0xff
#define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
#define CONFIG_NR_CPUS 256
#define NETIF_F_GRO_HW __NETIF_F(GRO_HW)
#define MODULE_NAME_LEN MAX_PARAM_PREFIX_LEN
#define __LINUX_MUTEX_H 
#define ETH_P_HSR 0x892F
#define raw_spin_lock_init(lock) do { static struct lock_class_key __key; __raw_spin_lock_init((lock), #lock, &__key, LD_WAIT_SPIN); } while (0)
#define DT_RELASZ 8
#define I_NEW (1 << __I_NEW)
#define ID_AA64ZFR0_EL1_F64MM_SIGNED false
#define CONFIG_GLOB 1
#define PR_SPEC_ENABLE (1UL << 1)
#define ELFOSABI_NONE 0
#define ETH_P_80221 0x8917
#define SPIN_DEP_MAP_INIT(lockname) .dep_map = { .name = #lockname, .wait_type_inner = LD_WAIT_CONFIG, }
#define FS_XFLAG_RTINHERIT 0x00000100
#define ID_AA64MMFR0_EL1_ECV_CNTPOFF UL(0b0010)
#define ETH_MDIO_SUPPORTS_C22 1
#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
#define EPOLL_CTL_MOD 3
#define RNDGETENTCNT _IOR( 'R', 0x00, int )
#define ID_AA64ISAR1_EL1_LS64_SIGNED false
#define pud_same pud_same
#define ID_AA64MMFR2_EL1_TTL_IMP UL(0b0001)
#define ESR_ELx_SYS64_ISS_SYS_VAL(op0,op1,op2,crn,crm) (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
#define CONFIG_ARCH_SUPPORTS_KEXEC_SIG 1
#define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
#define ID_ISAR6_EL1_JSCVT_MASK GENMASK(3, 0)
#define list_entry(ptr,type,member) container_of(ptr, type, member)
#define ELF_DATA ELFDATA2LSB
#define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
#define NETIF_F_GSO_UDP __NETIF_F(GSO_UDP)
#define __BF_FIELD_CHECK(_mask,_reg,_val,_pfx) ({ BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), _pfx "mask is not constant"); BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, _pfx "value too large for the field"); BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > __bf_cast_unsigned(_reg, ~0ull), _pfx "type of reg too small for mask"); __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + (1ULL << __bf_shf(_mask))); })
#define ICH_HCR_TALL0 (1 << 11)
#define NT_PPC_PKEY 0x110
#define SI_MAX_SIZE 128
#define TIMER_IRQSAFE 0x00200000
#define pmdp_clear_young_notify pmdp_test_and_clear_young
#define __iomb() dma_mb()
#define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
#define ID_AA64ISAR2_EL1_MOPS_SIGNED false
#define _LINUX_KERNEL_SPRINTF_H_ 
#define __kunit_test_suites(unique_array,...) static struct kunit_suite *unique_array[] __aligned(sizeof(struct kunit_suite *)) __used __section(".kunit_test_suites") = { __VA_ARGS__ }
#define SCTLR_EL1_EnTP2_WIDTH 1
#define idr_for_each_entry_continue_ul(idr,entry,tmp,id) for (tmp = id; ((entry) = tmp <= id ? idr_get_next_ul(idr, &(id)) : NULL) != NULL; tmp = id, ++id)
#define SEQCOUNT_LOCKNAME(lockname,locktype,preemptible,lockbase) typedef struct seqcount_ ##lockname { seqcount_t seqcount; __SEQ_LOCK(locktype *lock); } seqcount_ ##lockname ##_t; static __always_inline seqcount_t * __seqprop_ ##lockname ##_ptr(seqcount_ ##lockname ##_t *s) { return &s->seqcount; } static __always_inline const seqcount_t * __seqprop_ ##lockname ##_const_ptr(const seqcount_ ##lockname ##_t *s) { return &s->seqcount; } static __always_inline unsigned __seqprop_ ##lockname ##_sequence(const seqcount_ ##lockname ##_t *s) { unsigned seq = READ_ONCE(s->seqcount.sequence); if (!IS_ENABLED(CONFIG_PREEMPT_RT)) return seq; if (preemptible && unlikely(seq & 1)) { __SEQ_LOCK(lockbase ##_lock(s->lock)); __SEQ_LOCK(lockbase ##_unlock(s->lock)); seq = READ_ONCE(s->seqcount.sequence); } return seq; } static __always_inline bool __seqprop_ ##lockname ##_preemptible(const seqcount_ ##lockname ##_t *s) { if (!IS_ENABLED(CONFIG_PREEMPT_RT)) return preemptible; return false; } static __always_inline void __seqprop_ ##lockname ##_assert(const seqcount_ ##lockname ##_t *s) { __SEQ_LOCK(lockdep_assert_held(s->lock)); }
#define __NR_ftruncate __NR3264_ftruncate
#define FS_RESERVED_FL 0x80000000
#define SYS_SMPRIMAP_EL2_CRm 2
#define SYS_SMPRIMAP_EL2_CRn 1
#define FAR_EL1_ADDR GENMASK(63, 0)
#define TCR2_EL1x_RES0 (UL(0) | GENMASK_ULL(63, 16) | GENMASK_ULL(13, 12) | GENMASK_ULL(9, 6))
#define ID_PFR1_EL1_Virt_frac_NI UL(0b0000)
#define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
#define HFGITR_EL2_TLBIASIDE1IS_SHIFT 30
#define ETH_MDIO_SUPPORTS_C45 2
#define ID_ISAR0_EL1_CmpBranch_SIGNED false
#define ID_AA64ISAR2_EL1_RPRFM_MASK GENMASK(51, 48)
#define __NR_clone3 435
#define SUPPORTED_56000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseKR4_Full)
#define ESOCKTNOSUPPORT 94
#define ID_AA64ISAR0_EL1_FHM GENMASK(51, 48)
#define LED_BLINK_ONESHOT_STOP 2
#define SUPPORTED_40000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseLR4_Full)
#define CONFIG_PANIC_ON_OOPS_VALUE 0
#define MAX_PTRS_PER_PMD PTRS_PER_PMD
#define MAPLE_NODE_SLOTS 31
#define ID_PFR1_EL1_MProgMod_NI UL(0b0000)
#define time_after64(a,b) (typecheck(__u64, a) && typecheck(__u64, b) && ((__s64)((b) - (a)) < 0))
#define PSR_AA32_E_BIT 0x00000200
#define GMID_EL1_BS_MASK GENMASK(3, 0)
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
#define CONFIG_CGROUP_NET_PRIO 1
#define PR_SET_NAME 15
#define p4d_populate(mm,p4d,pud) do { } while (0)
#define PMSFCR_EL1_LD_WIDTH 1
#define CONFIG_NETWORK_FILESYSTEMS 1
#define __NR_truncate __NR3264_truncate
#define HCR_ATA_SHIFT 56
#define CONFIG_HAVE_CLK_PREPARE 1
#define APPLE_CPU_PART_M2_AVALANCHE 0x033
#define ID_AA64ISAR2_EL1_MOPS_NI UL(0b0000)
#define HFGITR_EL2_TLBIRVALE1OS_SHIFT 26
#define ID_AA64ISAR2_EL1_GPA3_IMP UL(0b0001)
#define SOL_SMC 286
#define ID_AA64ZFR0_EL1_I8MM_IMP UL(0b0001)
#define ID_AA64ZFR0_EL1_RES0 (UL(0) | GENMASK_ULL(63, 60) | GENMASK_ULL(51, 48) | GENMASK_ULL(39, 36) | GENMASK_ULL(31, 28) | GENMASK_ULL(15, 8))
#define ID_AA64ZFR0_EL1_RES1 (UL(0))
#define SYS_ID_AA64ISAR0_EL1_Op0 3
#define ID_ISAR4_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_ISAR4_EL1_RES1 (UL(0))
#define ID_AA64DFR0_EL1_BRBE_MASK GENMASK(55, 52)
#define ID_DFR0_EL1_MProfDbg_MASK GENMASK(23, 20)
#define HFGxTR_EL2_nGCS_EL1_MASK GENMASK(53, 53)
#define HDFGWTR_EL2_nPMSNEVFR_EL1_MASK GENMASK(62, 62)
#define ID_MMFR0_EL1_UNKN (UL(0))
#define REG_MDCCINT_EL1 S2_0_C0_C2_0
#define SB_I_CGROUPWB 0x00000001
#define dev_dbg(dev,fmt,...) ({ if (0) dev_printk(KERN_DEBUG, dev, dev_fmt(fmt), ##__VA_ARGS__); })
#define THREAD_ALIGN THREAD_SIZE
#define current_save_and_set_rtlock_wait_state() do { lockdep_assert_irqs_disabled(); raw_spin_lock(&current->pi_lock); current->saved_state = current->__state; debug_rtlock_wait_set_state(); WRITE_ONCE(current->__state, TASK_RTLOCK_WAIT); raw_spin_unlock(&current->pi_lock); } while (0);
#define ID_AA64MMFR1_EL1_AFP_SIGNED false
#define MNT_LOCK_NOSUID 0x100000
#define ID_AA64MMFR3_EL1_S2POE_WIDTH 4
#define __ARM64_KVM_ARM_H__ 
#define ASYNC_AND_SYNC 2
#define SCTLR_EL1_EnIB_WIDTH 1
#define NLM_F_ECHO 0x08
#define __CLEARPAGEFLAG(uname,lname,policy) static __always_inline void __folio_clear_ ##lname(struct folio *folio) { __clear_bit(PG_ ##lname, folio_flags(folio, FOLIO_ ##policy)); } static __always_inline void __ClearPage ##uname(struct page *page) { __clear_bit(PG_ ##lname, &policy(page, 1)->flags); }
#define PTRACE_SYSEMU_SINGLESTEP 32
#define V1_INIT_REWRITE 1
#define CONFIG_STRICT_DEVMEM 1
#define INLINE_COPY_TO_USER 
#define ETOOMANYREFS 109
#define PCI_IO_END (VMEMMAP_START - SZ_8M)
#define MDIO_PMA_EXTABLE_BT1 0x0800
#define CONFIG_INET_TABLE_PERTURB_ORDER 16
#define ___and(x,y) ____and(__ARG_PLACEHOLDER_ ##x, y)
#define compat_elf_read_implies_exec(ex,stk) (stk == EXSTACK_DEFAULT)
#define CONFIG_HAVE_ALIGNED_STRUCT_PAGE 1
#define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
#define KERNEL_HWCAP_AES __khwcap_feature(AES)
#define CONFIG_SPI_SPIDEV 1
#define MDSCR_EL1_EMBWE_MASK GENMASK(32, 32)
#define SIOCGIFINDEX 0x8933
#define netdev_alert_once(dev,fmt,...) netdev_level_once(KERN_ALERT, dev, fmt, ##__VA_ARGS__)
#define ioremap_np(addr,size) ioremap_prot((addr), (size), PROT_DEVICE_nGnRnE)
#define EDOTDOT 73
#define ARM64_HAS_RNG 41
#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001
#define SYS_ICC_NMIAR1_EL1_Op0 3
#define HFGxTR_EL2_CONTEXTIDR_EL1_MASK GENMASK(11, 11)
#define SYS_ICC_NMIAR1_EL1_Op2 5
#define PF_MEMALLOC_PIN 0x10000000
#define MDIO_AN_ADVERTISE 16
#define __VDSO_MATH64_H 
#define EI_MAG2 2
#define HFGITR_EL2_TLBIASIDE1OS_MASK GENMASK(20, 20)
#define SIOCGIFENCAP 0x8925
#define PF_SMC AF_SMC
#define PMSIRR_EL1_RND_WIDTH 1
#define __local_lock_irq(lock) do { local_irq_disable(); local_lock_acquire(this_cpu_ptr(lock)); } while (0)
#define KERNEL_HWCAP_AFP __khwcap2_feature(AFP)
#define for_each_node(node) for_each_node_state(node, N_POSSIBLE)
#define __this_cpu_sub(pcp,val) __this_cpu_add(pcp, -(typeof(pcp))(val))
#define ETH_RESET_SHARED_SHIFT 16
#define pte_alloc_kernel(pmd,address) ((unlikely(pmd_none(*(pmd))) && __pte_alloc_kernel(pmd))? NULL: pte_offset_kernel(pmd, address))
#define MDIO_PMA_CTRL2_BASET1 0x003D
#define TCR2_EL2_POE_SHIFT 3
#define ID_DFR0_EL1_PerfMon_MASK GENMASK(27, 24)
#define __O_TMPFILE 020000000
#define NODES_WIDTH NODES_SHIFT
#define ID_AA64DFR0_EL1_HPMN0_SHIFT 60
#define lockdep_set_class_and_subclass(lock,key,sub) lockdep_init_map_type(&(lock)->dep_map, #key, key, sub, (lock)->dep_map.wait_type_inner, (lock)->dep_map.wait_type_outer, (lock)->dep_map.lock_type)
#define IOCB_DSYNC (__force int) RWF_DSYNC
#define HCRX_EL2_TMEA GENMASK(19, 19)
#define user_read_access_end user_access_end
#define SYS_MVFR2_EL1_CRn 0
#define ID_ISAR6_EL1_BF16_SIGNED false
#define _LINUX_RCULIST_H 
#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu))
#define ETHTOOL_SRXCLSRLINS 0x00000032
#define HFGITR_EL2_ICIALLUIS GENMASK(0, 0)
#define DACR32_EL2_D5_WIDTH 2
#define IOCB_DIO_CALLER_COMP (1 << 22)
#define __LINUX_NETLINK_H 
#define JOBCTL_TRAPPING (1UL << JOBCTL_TRAPPING_BIT)
#define ID_MMFR1_EL1_BPred_BP_SW_MANGED UL(0b0001)
#define SO_PEEK_OFF 42
#define PAGE_EXECONLY __pgprot(_PAGE_EXECONLY)
#define ATOMIC_NOTIFIER_INIT(name) { .lock = __SPIN_LOCK_UNLOCKED(name.lock), .head = NULL }
#define NT_ARM_TAGGED_ADDR_CTRL 0x409
#define __LINUX_PERCPU_H 
#define raw_cpu_ptr(ptr) ({ __verify_pcpu_ptr(ptr); arch_raw_cpu_ptr(ptr); })
#define __inline__ inline
#define CTR_EL0_DIC GENMASK(29, 29)
#define SMPRIMAP_EL2_P3_SHIFT 12
#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
#define PR_SPEC_FORCE_DISABLE (1UL << 3)
#define ID_AA64MMFR3_EL1_D128_2_NI UL(0b0000)
#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
#define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
#define _LINUX_PERCPU_COUNTER_H 
#define SYS_ID_AA64PFR1_EL1_Op0 3
#define NSEC_PER_MSEC 1000000L
#define SCTLR_EL1_EE_SHIFT 25
#define MNT_USER_SETTABLE_MASK (MNT_NOSUID | MNT_NODEV | MNT_NOEXEC | MNT_NOATIME | MNT_NODIRATIME | MNT_RELATIME | MNT_READONLY | MNT_NOSYMFOLLOW)
#define SCTLR_EL1_LSMAOE_MASK GENMASK(29, 29)
#define TRBSR_EL1_EA GENMASK(18, 18)
#define TRBSR_EL1_EC GENMASK(31, 26)
#define PIRx_ELx_Perm5_SHIFT 20
#define ID_AA64PFR1_EL1_GCS_SIGNED false
#define WNOWAIT 0x01000000
#define ID_ISAR4_EL1_SynchPrim_frac GENMASK(23, 20)
#define ID_ISAR3_EL1_Saturate_SHIFT 0
#define CONFIG_CGROUP_SCHED 1
#define ID_ISAR2_EL1_PSR_AR_IMP UL(0b0001)
#define STACK_TOP STACK_TOP_MAX
#define SCTLR_EL1_E0E_SHIFT 24
#define CTR_EL0_TminLine_MASK GENMASK(37, 32)
#define HCRX_EL2_EnSNERR_SHIFT 18
#define DEFINE_PER_CPU_ALIGNED(type,name) DEFINE_PER_CPU_SECTION(type, name, PER_CPU_ALIGNED_SECTION) ____cacheline_aligned
#define ID_PFR1_EL1_MProgMod GENMASK(11, 8)
#define CCSIDR_EL1_Associativity_MASK GENMASK(12, 3)
#define PMSIDR_EL1_INTERVAL_512 UL(0b0010)
#define CONFIG_AS_IS_GNU 1
#define EM_PARISC 15
#define _LINUX_ARRAY_SIZE_H 
#define ID_AA64MMFR3_EL1_D128_SHIFT 32
#define EM_PPC 20
#define FS_QSTAT_VERSION 1
#define DMA_ATTR_NO_WARN (1UL << 8)
#define CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK 1
#define TRBPTR_EL1_UNKN (UL(0))
#define QIF_SPACE (1 << QIF_SPACE_B)
#define MMF_DUMP_HUGETLB_SHARED 8
#define UMH_NO_WAIT 0x00
#define CONFIG_NET_IP_TUNNEL 1
#define MDSCR_EL1_EnSPM_WIDTH 1
#define ID_DFR0_EL1_TraceFilt_NI UL(0b0000)
#define __NR_clone 220
#define shift_right(x,s) ({ __typeof__(x) __x = (x); __typeof__(s) __s = (s); __x < 0 ? -(-__x >> __s) : __x >> __s; })
#define ___test_and_set_bit arch___test_and_set_bit
#define SCTLR_EL1_SA0 GENMASK(4, 4)
#define _UAPI_LINUX_BYTEORDER_LITTLE_ENDIAN_H 
#define VM_NOHUGEPAGE 0x40000000
#define NR_FIX_BTMAPS (SZ_256K / PAGE_SIZE)
#define HFGITR_EL2_TLBIRVAALE1OS_WIDTH 1
#define key_ref_to_ptr(k) NULL
#define _UAPI_LINUX_RESOURCE_H 
#define ID_ISAR0_EL1_Debug_NI UL(0b0000)
#define TIME_OK 0
#define ETH_MODULE_SFF_8436 0x4
#define ID_AA64DFR0_EL1_TraceFilt_IMP UL(0b0001)
#define ID_MMFR1_EL1_L1HvdSW_INVALIDATE UL(0b0011)
#define HDFGWTR_EL2_MDSCR_EL1 GENMASK(4, 4)
#define SOL_ICMPV6 58
#define COMPAT_PTRACE_SETREGS 13
#define CONFIG_DEBUG_INFO 1
#define __LINUX_SEMAPHORE_H 
#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
#define CONFIG_PCPU_DEV_REFCNT 1
#define KUNIT_EXPECT_GT(test,left,right) KUNIT_EXPECT_GT_MSG(test, left, right, NULL)
#define ID_MMFR4_EL1_SpecSEI_SIGNED false
#define PMBSR_EL1_MSS_WIDTH 16
#define CHECKSUM_UNNECESSARY 1
#define EPROTONOSUPPORT 93
#define ZA_MAGIC 0x54366345
#define raw_try_cmpxchg64_release(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg64_release((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define ID_ISAR4_EL1_SynchPrim_frac_MASK GENMASK(23, 20)
#define request_mem_region_exclusive(start,n,name) __request_region(&iomem_resource, (start), (n), (name), IORESOURCE_EXCLUSIVE)
#define _LINUX_SIGNAL_H 
#define VM_BUG_ON_FOLIO(cond,folio) VM_BUG_ON(cond)
#define __io_wait_event(wq_head,condition) (void)___wait_event(wq_head, condition, TASK_UNINTERRUPTIBLE, 0, 0, io_schedule())
#define SRCU_SIZE_WAIT_CALL 3
#define AT_BASE_PLATFORM 24
#define HFGITR_EL2_TLBIVALE1IS_SHIFT 32
#define prevent_tail_call_optimization() mb()
#define __UAPI_DEF_IPX_INTERFACE_DEFINITION 1
#define SB_I_TS_EXPIRY_WARNED 0x00000400
#define HDFGRTR_EL2_PMCCNTR_EL0_WIDTH 1
#define PACKET_DROP_MEMBERSHIP 2
#define __LINUX_COMPLETION_H 
#define request_muxed_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name), IORESOURCE_MUXED)
#define PR_GET_CHILD_SUBREAPER 37
#define __pcpu_size_call_return2bool(stem,variable,...) ({ bool pscr2_ret__; __verify_pcpu_ptr(&(variable)); switch(sizeof(variable)) { case 1: pscr2_ret__ = stem ##1(variable, __VA_ARGS__); break; case 2: pscr2_ret__ = stem ##2(variable, __VA_ARGS__); break; case 4: pscr2_ret__ = stem ##4(variable, __VA_ARGS__); break; case 8: pscr2_ret__ = stem ##8(variable, __VA_ARGS__); break; default: __bad_size_call_parameter(); break; } pscr2_ret__; })
#define __percpu BTF_TYPE_TAG(percpu)
#define virt_load_acquire(p) __smp_load_acquire(p)
#define REG_HDFGRTR_EL2 S3_4_C3_C1_4
#define ETH_FRAME_LEN 1514
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
#define STT_SECTION 3
#define ID_MMFR2_EL1_HvdTLB_WIDTH 4
#define __NR_readv 65
#define DT_SYMENT 11
#define UDP_V6_FLOW 0x06
#define __UAPI_DEF_SOCKADDR_IN 1
#define COMPAT_HWCAP2_SSBS (1 << 6)
#define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12
#define HFGITR_EL2_DCCIVAC_MASK GENMASK(10, 10)
#define __HAVE_ARCH_COPY_USER_HIGHPAGE 
#define KERNFS_FLAG_MASK ~KERNFS_TYPE_MASK
#define TAINT_FIRMWARE_WORKAROUND 11
#define _LINUX_DELAY_H 
#define compat_user_stack_pointer() current_user_stack_pointer()
#define HDFGRTR_EL2_PMSEVFR_EL1 GENMASK(27, 27)
#define __local_unlock(lock) do { local_lock_release(this_cpu_ptr(lock)); preempt_enable(); } while (0)
#define PR_CAPBSET_DROP 24
#define HCR_TID5 (UL(1) << 58)
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
#define HFGITR_EL2_ERET_WIDTH 1
#define ID_AA64MMFR0_EL1_EXS_NI UL(0b0000)
#define raw_cpu_and_1(pcp,val) raw_cpu_generic_to_op(pcp, val, &=)
#define raw_cpu_and_2(pcp,val) raw_cpu_generic_to_op(pcp, val, &=)
#define raw_cpu_and_4(pcp,val) raw_cpu_generic_to_op(pcp, val, &=)
#define raw_cpu_and_8(pcp,val) raw_cpu_generic_to_op(pcp, val, &=)
#define PSTATE_PAN pstate_field(0, 4)
#define SCTLR_EL1_I_WIDTH 1
#define __GFP_DIRECT_RECLAIM ((__force gfp_t)___GFP_DIRECT_RECLAIM)
#define HCR_FB (UL(1) << 9)
#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
#define find_first_clump8(clump,bits,size) find_next_clump8((clump), (bits), (size), 0)
#define plist_for_each_entry_safe(pos,n,head,m) list_for_each_entry_safe(pos, n, &(head)->node_list, m.node_list)
#define IPV6_FLOWINFO_FLOWLABEL 0x000fffff
#define __LINUX_FDTABLE_H 
#define __phys_addr_symbol(x) __pa_symbol_nodebug(x)
#define PHYS_OFFSET ({ VM_BUG_ON(memstart_addr & 1); memstart_addr; })
#define SOL_VSOCK 287
#define XA_BUG_ON(xa,x) do { } while (0)
#define __aligned_le64 __le64 __attribute__((aligned(8)))
#define SYS_LORID_EL1_Op0 3
#define SYS_LORID_EL1_Op2 7
#define HDFGWTR_EL2_PMSEVFR_EL1_SHIFT 27
#define HDFGRTR_EL2_OSDLR_EL1 GENMASK(11, 11)
#define ID_ISAR6_EL1_FHM_WIDTH 4
#define FS_VERITY_FL 0x00100000
#define SZ_1G 0x40000000
#define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
#define SZ_1K 0x00000400
#define SZ_1M 0x00100000
#define ID_ISAR3_EL1_T32Copy_MASK GENMASK(23, 20)
#define PMBIDR_EL1_F GENMASK(5, 5)
#define SZ_1T _AC(0x10000000000, ULL)
#define __MODULE_INFO(tag,name,info) static const char __UNIQUE_ID(name)[] __used __section(".modinfo") __aligned(1) = __MODULE_INFO_PREFIX __stringify(tag) "=" info
#define PMBIDR_EL1_P GENMASK(4, 4)
#define HCR_NV1 (UL(1) << 43)
#define IPV6_FL_F_REMOTE 8
#define ICH_VMCR_ENG1_SHIFT 1
#define CONFIG_DEFAULT_INIT ""
#define ID_PFR0_EL1_RAS_RAS UL(0b0001)
#define SCHED_FLAG_RECLAIM 0x02
#define ____and(arg1_or_junk,y) __take_second_arg(arg1_or_junk y, 0)
#define ID_AA64ISAR1_EL1_APA_EPAC UL(0b0010)
#define flush_tlb_fix_spurious_fault(vma,address,ptep) do { } while (0)
#define __NR_landlock_add_rule 445
#define PMBIDR_EL1_EA_WIDTH 4
#define ASSERT_EXCLUSIVE_BITS(var,mask) do { kcsan_set_access_mask(mask); __kcsan_check_access(&(var), sizeof(var), KCSAN_ACCESS_ASSERT); kcsan_set_access_mask(0); kcsan_atomic_next(1); } while (0)
#define __ALTERNATIVE_CFG(oldinstr,newinstr,cpucap,cfg_enabled) ".if "__stringify(cfg_enabled)" == 1\n" "661:\n\t" oldinstr "\n" "662:\n" ".pushsection .altinstructions,\"a\"\n" ALTINSTR_ENTRY(cpucap) ".popsection\n" ".subsection 1\n" "663:\n\t" newinstr "\n" "664:\n\t" ".org	. - (664b-663b) + (662b-661b)\n\t" ".org	. - (662b-661b) + (664b-663b)\n\t" ".previous\n" ".endif\n"
#define ID_AA64ISAR1_EL1_GPI GENMASK(31, 28)
#define HFGITR_EL2_DCCSW_SHIFT 5
#define SZ_2G 0x80000000
#define SCTLR_EL1_EnDA_MASK GENMASK(27, 27)
#define SIOCSIFDSTADDR 0x8918
#define ID_MMFR4_EL1_LSM_SHIFT 20
#define ID_ISAR4_EL1_SWP_frac GENMASK(31, 28)
#define SYS_HDFGWTR_EL2_Op0 3
#define SYS_HDFGWTR_EL2_Op1 4
#define SYS_HDFGWTR_EL2_Op2 5
#define IFF_AUTOMEDIA IFF_AUTOMEDIA
#define DACR32_EL2_D9_SHIFT 18
#define HFGITR_EL2_TLBIVAALE1OS_MASK GENMASK(23, 23)
#define ID_ISAR4_EL1_Unpriv_SIGNED_HALFWORD UL(0b0010)
#define SIGRTMIN 32
#define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
#define ID_PFR2_EL1_RAS_frac_RASv1p1 UL(0b0001)
#define TRBLIMITR_EL1_TM_WIDTH 2
#define create_freezable_workqueue(name) alloc_workqueue("%s", __WQ_LEGACY | WQ_FREEZABLE | WQ_UNBOUND | WQ_MEM_RECLAIM, 1, (name))
#define ID_MMFR0_EL1_PMSA_MASK GENMASK(7, 4)
#define _LINUX_CAPABILITY_VERSION_2 0x20071026
#define _LINUX_CAPABILITY_VERSION_3 0x20080522
#define CLOCK_BOOTTIME 7
#define SZ_32 0x00000020
#define BMSR_RFAULT 0x0010
#define ID_AA64MMFR2_EL1_UAO_WIDTH 4
#define IOCB_ALLOC_CACHE (1 << 21)
#define CONFIG_SND_SOC_PCM3168A 1
#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
#define RXH_VLAN (1 << 2)
#define SYS_ID_AA64ISAR1_EL1_Op0 3
#define SYS_ID_AA64ISAR1_EL1_Op1 0
#define SYS_ID_AA64ISAR1_EL1_Op2 1
#define MDIO_AN_10GBT_STAT_LP10G 0x0800
#define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP
#define CONFIG_KALLSYMS_ALL 1
#define PMSCR_EL1_PA_MASK GENMASK(4, 4)
#define SLAB_KMALLOC ((slab_flags_t __force)0x00001000U)
#define NOTIFY_DONE 0x0000
#define __NR_symlinkat 36
#define arch_alloc_nodedata(nid) generic_alloc_nodedata(nid)
#define ASM_BUG() ASM_BUG_FLAGS(0)
#define MCOUNT_ADDR ((unsigned long)_mcount)
#define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
#define SB_LAZYTIME BIT(25)
#define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
#define IPV6_PRIORITY_9 0x0900
#define ID_MMFR0_EL1_TCM_SHIFT 16
#define EM_AARCH64 183
#define __BIT_TYPES_DEFINED__ 
#define SZ_4G _AC(0x100000000, ULL)
#define SZ_4K 0x00001000
#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
#define CONFIG_HAVE_CLK 1
#define HDFGRTR_EL2_TRCSEQSTR_WIDTH 1
#define si_syscall _sifields._sigsys._syscall
#define __NR_sched_get_priority_min 126
#define HDFGRTR_EL2_DBGPRCR_EL1_SHIFT 7
#define NOKPROBE_SYMBOL(fname) 
#define _UAPI_LINUX_PTRACE_H 
#define PAGE_TYPE_OPS(uname,lname,fname) static __always_inline int Page ##uname(const struct page *page) { return PageType(page, PG_ ##lname); } static __always_inline int folio_test_ ##fname(const struct folio *folio){ return folio_test_type(folio, PG_ ##lname); } static __always_inline void __SetPage ##uname(struct page *page) { VM_BUG_ON_PAGE(!PageType(page, 0), page); page->page_type &= ~PG_ ##lname; } static __always_inline void __folio_set_ ##fname(struct folio *folio) { VM_BUG_ON_FOLIO(!folio_test_type(folio, 0), folio); folio->page.page_type &= ~PG_ ##lname; } static __always_inline void __ClearPage ##uname(struct page *page) { VM_BUG_ON_PAGE(!Page ##uname(page), page); page->page_type |= PG_ ##lname; } static __always_inline void __folio_clear_ ##fname(struct folio *folio) { VM_BUG_ON_FOLIO(!folio_test_ ##fname(folio), folio); folio->page.page_type |= PG_ ##lname; }
#define pte_clear_fixmap() clear_fixmap(FIX_PTE)
#define MIDR_REV(m,v,r) MIDR_RANGE(m, v, r, v, r)
#define vma_interval_tree_foreach(vma,root,start,last) for (vma = vma_interval_tree_iter_first(root, start, last); vma; vma = vma_interval_tree_iter_next(vma, start, last))
#define skb_frag_foreach_page(f,f_off,f_len,p,p_off,p_len,copied) for (p = skb_frag_page(f) + ((f_off) >> PAGE_SHIFT), p_off = (f_off) & (PAGE_SIZE - 1), p_len = skb_frag_must_loop(p) ? min_t(u32, f_len, PAGE_SIZE - p_off) : f_len, copied = 0; copied < f_len; copied += p_len, p++, p_off = 0, p_len = min_t(u32, f_len - copied, PAGE_SIZE))
#define __WAITQUEUE_INITIALIZER(name,tsk) { .private = tsk, .func = default_wake_function, .entry = { NULL, NULL } }
#define NLMSG_ALIGN(len) ( ((len)+NLMSG_ALIGNTO-1) & ~(NLMSG_ALIGNTO-1) )
#define arch_xchg_relaxed(...) __xchg_wrapper( , __VA_ARGS__)
#define CPU_BITS_CPU0 { [0] = 1UL }
#define MVFR1_EL1_FPDNaN_WIDTH 4
#define HFGxTR_EL2_nS2POR_EL1 GENMASK(61, 61)
#define __swahw32(x) (__builtin_constant_p((__u32)(x)) ? ___constant_swahw32(x) : __fswahw32(x))
#define is_key_possessed(k) 0
#define HDFGRTR_EL2_TRCVICTLR_WIDTH 1
#define TRBLIMITR_EL1_LIMIT_WIDTH 52
#define _outl _outl
#define IORESOURCE_IO 0x00000100
#define HDFGWTR_EL2_TRBBASER_EL1_WIDTH 1
#define SCTLR_EL1_EnALS GENMASK(56, 56)
#define rb_parent(r) ((struct rb_node *)((r)->__rb_parent_color & ~3))
#define CPACR_EL1_ZEN_EL1EN (BIT(16))
#define PF_APPLETALK AF_APPLETALK
#define ID_MMFR2_EL1_MemBarr_DSB_ONLY UL(0b0001)
#define SIGUSR1 10
#define CNTHCTL_EL1PCTEN (1 << 0)
#define FMODE_NOACCOUNT ((__force fmode_t)0x20000000)
#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
#define arch_set_restart_data(restart) do { } while (0)
#define ID_AA64ISAR2_EL1_PAC_frac_SIGNED false
#define CONFIG_CRYPTO_LIB_SHA1 1
#define SYSCTL_THREE ((void *)&sysctl_vals[3])
#define ID_MMFR0_EL1_InnerShr GENMASK(31, 28)
#define SIGUSR2 12
#define _IOC_READ 2U
#define FSEC_PER_SEC 1000000000000000LL
#define SZ_64 0x00000040
#define MNT_NOEXEC 0x04
#define HWCAP2_SME_I16I32 (1UL << 39)
#define RLIMIT_DATA 2
#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
#define STATX__RESERVED 0x80000000U
#define PMSIDR_EL1_ERND_WIDTH 1
#define IF_PROTO_CISCO 0x2002
#define GFP_ZONEMASK (__GFP_DMA|__GFP_HIGHMEM|__GFP_DMA32|__GFP_MOVABLE)
#define _inb _inb
#define flex_array_size(p,member,count) __builtin_choose_expr(__is_constexpr(count), (count) * sizeof(*(p)->member) + __must_be_array((p)->member), size_mul(count, sizeof(*(p)->member) + __must_be_array((p)->member)))
#define IPV6_PKTINFO 50
#define lockdep_recursing(tsk) ((tsk)->lockdep_recursion)
#define key_revoke(k) do { } while(0)
#define MVFR1_EL1_SIMDFMAC_SHIFT 28
#define MDSCR_EL1_SC2 GENMASK(19, 19)
#define MDIO_DEVAD_NONE (-1)
#define LED_COLOR_ID_GREEN 2
#define raw_try_cmpxchg64_local(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg64_local((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define rb_first_cached(root) (root)->rb_leftmost
#define ID_AA64ISAR0_EL1_SM3_MASK GENMASK(39, 36)
#define PREEMPT_DISABLED (PREEMPT_DISABLE_OFFSET + PREEMPT_ENABLED)
#define ID_AA64ISAR1_EL1_BF16_WIDTH 4
#define __sockaddr_check_size(size) BUILD_BUG_ON(((size) > sizeof(struct __kernel_sockaddr_storage)))
#define PA_HWTYPE_ANY_ID 0xff
#define SG_MITER_FROM_SG (1 << 2)
#define KIMAGE_VADDR (MODULES_END)
#define wait_event_interruptible_timeout(wq_head,condition,timeout) ({ long __ret = timeout; might_sleep(); if (!___wait_cond_timeout(condition)) __ret = __wait_event_interruptible_timeout(wq_head, condition, timeout); __ret; })
#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 90
#define CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE 1
#define rcu_access_pointer(p) __rcu_access_pointer((p), __UNIQUE_ID(rcu), __rcu)
#define TESTPAGEFLAG_FALSE(uname,lname) static inline bool folio_test_ ##lname(const struct folio *folio) { return false; } static inline int Page ##uname(const struct page *page) { return 0; }
#define rcuwait_wait_event(w,condition,state) ___rcuwait_wait_event(w, condition, state, 0, schedule())
#define ID_ISAR1_EL1_Extend_WIDTH 4
#define DQF_INFO_DIRTY (1 << DQF_INFO_DIRTY_B)
#define ID_AA64MMFR3_EL1_SCTLRX GENMASK(7, 4)
#define DCACHE_DONTCACHE 0x00000080
#define EMSGSIZE 90
#define SZ_8G _AC(0x200000000, ULL)
#define SZ_8K 0x00002000
#define BLKROTATIONAL _IO(0x12,126)
#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52
#define RWH_WRITE_LIFE_NONE 1
#define _UAPI_LINUX_TIME_TYPES_H 
#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
#define HDFGWTR_EL2_PMCCFILTR_EL0_MASK GENMASK(14, 14)
#define __ASSERT_EXCLUSIVE_SCOPED(var,type,id) struct kcsan_scoped_access __kcsan_scoped_name(id, _) __kcsan_cleanup_scoped; struct kcsan_scoped_access *__kcsan_scoped_name(id, _dummy_p) __maybe_unused = kcsan_begin_scoped_access( &(var), sizeof(var), KCSAN_ACCESS_SCOPED | (type), &__kcsan_scoped_name(id, _))
#define HFGxTR_EL2_CPACR_EL1_SHIFT 12
#define STATX_ATTR_COMPRESSED 0x00000004
#define time_in_range64(a,b,c) (time_after_eq64(a, b) && time_before_eq64(a, c))
#define PMSCR_EL1_E0SPE GENMASK(0, 0)
#define __NR_timerfd_gettime 87
#define IPV6_DROP_MEMBERSHIP 21
#define CONFIG_NET_VENDOR_SAMSUNG 1
#define ID_AA64PFR1_EL1_NMI_NI UL(0b0000)
#define _LINUX_HIGHMEM_INTERNAL_H 
#define USER_ASID_BIT 48
#define HWCAP2_SME_I16I64 (1 << 24)
#define NETIF_F_FSO __NETIF_F(FSO)
#define __NR_rt_sigqueueinfo 138
#define IPV4_FLOW 0x10
#define CONFIG_IOMMU_DEFAULT_DMA_STRICT 1
#define ID_ISAR0_EL1_Coproc_MASK GENMASK(19, 16)
#define local_inc_not_zero(l) atomic_long_inc_not_zero(&(l)->a)
#define AF_ATMSVC 20
#define __rcu_dereference_check(p,local,c,space) ({ typeof(*p) *local = (typeof(*p) *__force)READ_ONCE(p); RCU_LOCKDEP_WARN(!(c), "suspicious rcu_dereference_check() usage"); rcu_check_sparse(p, space); ((typeof(*p) __force __kernel *)(local)); })
#define _LINUX_TRACE_IRQFLAGS_H 
#define __UINT8_C(c) c
#define ID_ISAR2_EL1_MultU_WIDTH 4
#define local64_add_unless(l,_a,u) local_add_unless((&(l)->a), (_a), (u))
#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
#define ETHTOOL_GRXCSUM 0x00000014
#define _DPRINTK_FLAGS_INCL_TID (1<<4)
#define SCTLR_EL1_TMT GENMASK(51, 51)
#define MOD_MAXERROR ADJ_MAXERROR
#define KUNIT_ASSERT_NOT_ERR_OR_NULL_MSG(test,ptr,fmt,...) KUNIT_PTR_NOT_ERR_OR_NULL_MSG_ASSERTION(test, KUNIT_ASSERTION, ptr, fmt, ##__VA_ARGS__)
#define CONFIG_DEVTMPFS_MOUNT 1
#define ID_AA64PFR0_EL1_FP GENMASK(19, 16)
#define ktime_add_unsafe(lhs,rhs) ((u64) (lhs) + (rhs))
#define SUPPORTED_Asym_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Asym_Pause)
#define AF_PPPOX 24
#define COMPAT_SYSCALL_DEFINEx(x,name,...) __diag_push(); __diag_ignore(GCC, 8, "-Wattribute-alias", "Type aliasing is used to sanitize syscall arguments"); asmlinkage long compat_sys ##name(__MAP(x,__SC_DECL,__VA_ARGS__)) __attribute__((alias(__stringify(__se_compat_sys ##name)))); ALLOW_ERROR_INJECTION(compat_sys ##name, ERRNO); static inline long __do_compat_sys ##name(__MAP(x,__SC_DECL,__VA_ARGS__)); asmlinkage long __se_compat_sys ##name(__MAP(x,__SC_LONG,__VA_ARGS__)); asmlinkage long __se_compat_sys ##name(__MAP(x,__SC_LONG,__VA_ARGS__)) { long ret = __do_compat_sys ##name(__MAP(x,__SC_DELOUSE,__VA_ARGS__)); __MAP(x,__SC_TEST,__VA_ARGS__); return ret; } __diag_pop(); static inline long __do_compat_sys ##name(__MAP(x,__SC_DECL,__VA_ARGS__))
#define CAP_SYS_TTY_CONFIG 26
#define CONFIG_PCI_ECAM 1
#define ID_AA64MMFR2_EL1_LSM_WIDTH 4
#define ID_AA64PFR1_EL1_RNDR_trap_MASK GENMASK(31, 28)
#define PCPU_MIN_ALLOC_SHIFT 2
#define MDIO_PMA_10GBT_SWAPPOL 130
#define LLIST_HEAD(name) struct llist_head name = LLIST_HEAD_INIT(name)
#define ID_PFR1_EL1_Security_NSACR_RFR UL(0b0001)
#define PR_SET_NO_NEW_PRIVS 38
#define FLOW_EXT 0x80000000
#define kunmap_local(__addr) do { BUILD_BUG_ON(__same_type((__addr), struct page *)); __kunmap_local(__addr); } while (0)
#define _LINUX_REFCOUNT_H 
#define mtree_lock(mt) spin_lock((&(mt)->ma_lock))
#define bvec_iter_len(bvec,iter) min_t(unsigned, mp_bvec_iter_len((bvec), (iter)), PAGE_SIZE - bvec_iter_offset((bvec), (iter)))
#define might_resched() do { } while (0)
#define __constant_ntohl(x) ___constant_swab32((__force __be32)(x))
#define THP_FILE_ALLOC ({ BUILD_BUG(); 0; })
#define __constant_ntohs(x) ___constant_swab16((__force __be16)(x))
#define MDIO_AN_T1_CTRL 512
#define FS_DQUOT_VERSION 1
#define ATTR_ATIME (1 << 4)
#define HFGxTR_EL2_nPOR_EL0_WIDTH 1
#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
#define MDIO_MMD_NUM 32
#define HDFGRTR_EL2_nPMSNEVFR_EL1_WIDTH 1
#define cpu_to_le16p __cpu_to_le16p
#define outsl outsl
#define cpu_to_le16s __cpu_to_le16s
#define _LINUX_IOPOLL_H 
#define SO_RCVTIMEO_NEW 66
#define __NR3264_fadvise64 223
#define __NR_clock_nanosleep 115
#define compat_arg_u64_dual(name) u32, name ##_lo, u32, name ##_hi
#define CAP_IPC_OWNER 15
#define ESR_ELx_SME_ISS_SM_DISABLED 2
#define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
#define SCTLR_EL1_EnAS0 GENMASK(55, 55)
#define NET_SKB_PAD max(32, L1_CACHE_BYTES)
#define read_unlock_irq(lock) _raw_read_unlock_irq(lock)
#define EXPANSION_MFAULTS 0x0010
#define HDFGWTR_EL2_PMUSERENR_EL0 GENMASK(57, 57)
#define INIT_MM_CONTEXT(name) .pgd = init_pg_dir,
#define PMSLATFR_EL1_MINLAT_SHIFT 0
#define net_warn_ratelimited(fmt,...) net_ratelimited_function(pr_warn, fmt, ##__VA_ARGS__)
#define PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 2)
#define replace_fops(f,fops) do { struct file *__file = (f); fops_put(__file->f_op); BUG_ON(!(__file->f_op = (fops))); } while(0)
#define SWAPPER_BLOCK_SHIFT PMD_SHIFT
#define SCTLR_EL1_EnASR GENMASK(54, 54)
#define ID_ISAR0_EL1_Coproc_WIDTH 4
#define FITRIM _IOWR('X', 121, struct fstrim_range)
#define CCSIDR_EL1_LineSize_SHIFT 0
#define SCTLR_EL1_TSCXT_WIDTH 1
#define SCTLR_EL1_ATA0 GENMASK(42, 42)
#define SO_MEMINFO 55
#define CONFIG_OF_IRQ 1
#define ETHTOOL_RXNTUPLE_ACTION_DROP (-1)
#define ID_AA64ISAR1_EL1_I8MM_IMP UL(0b0001)
#define compat_ipc_pid_t compat_ipc_pid_t
#define ID_AA64ZFR0_EL1_SHA3_IMP UL(0b0001)
#define HFGITR_EL2_TLBIRVAE1IS_SHIFT 34
#define ID_ISAR6_EL1_BF16_WIDTH 4
#define MDIO_AN_10GBT_STAT_MSFLT 0x8000
#define local_unlock_irqrestore(lock,flags) __local_unlock_irqrestore(lock, flags)
#define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
#define ID_AA64MMFR1_EL1_ECBHB_SHIFT 60
#define GETALL 13
#define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
#define _LINUX_PID_H 
#define __HAVE_ARCH_STRRCHR 
#define MT_FLAGS_LOCK_IRQ 0x100
#define SEQCNT_LATCH_ZERO(seq_name) { .seqcount = SEQCNT_ZERO(seq_name.seqcount), }
#define CONFIG_NET_VENDOR_WIZNET 1
#define OPT_ZONE_DMA32 ZONE_DMA32
#define SCTLR_EL1_TME0_MASK GENMASK(52, 52)
#define CPUCLOCK_PERTHREAD_MASK 4
#define SIGXCPU 24
#define MMF_DUMP_DAX_PRIVATE 9
#define PR_GET_TID_ADDRESS 40
#define ID_DFR0_EL1_MMapDbg_Armv7p1 UL(0b0101)
#define __TASK_TRACED 0x00000008
#define DACR32_EL2_D15_MASK GENMASK(31, 30)
#define RIO_ANY_ID 0xffff
#define HFGITR_EL2_ATS1E0R_SHIFT 14
#define max(x,y) __careful_cmp(max, x, y)
#define SZ_256 0x00000100
#define MODULE_FILE MODULE_INFO(file, KBUILD_MODFILE);
#define COMPAT_PTRACE_SETVFPREGS 28
#define PR_GET_THP_DISABLE 42
#define SCTLR_ELx_A (BIT(1))
#define _LINUX_ERRNAME_H 
#define clear_thread_flag(flag) clear_ti_thread_flag(current_thread_info(), flag)
#define SCTLR_ELx_I (BIT(12))
#define pgd_addr_end(addr,end) ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; (__boundary - 1 < (end) - 1)? __boundary: (end); })
#define __clear_bit(nr,addr) bitop(___clear_bit, nr, addr)
#define SCTLR_ELx_M (BIT(0))
#define MDSCR_EL1_TDCC GENMASK(12, 12)
#define NL_SET_ERR_MSG_ATTR(extack,attr,msg) NL_SET_ERR_MSG_ATTR_POL(extack, attr, NULL, msg)
#define HCRX_EL2_SMPME_MASK GENMASK(5, 5)
#define __LINUX_UIO_H 
#define task_euid(task) (task_cred_xxx((task), euid))
#define PF_IUCV AF_IUCV
#define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
#define CAVIUM_CPU_PART_THUNDERX 0x0A1
#define FAR_EL2_ADDR_WIDTH 64
#define STA_MODE 0x4000
#define SIOCDRARP 0x8960
#define HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT 14
#define __NR_adjtimex 171
#define IPV6_UNICAST_HOPS 16
#define IPV6_FLOWINFO 11
#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
#define __ASM_ATOMIC_LL_SC_H 
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
#define __NR_renameat2 276
#define pud_leaf_size(x) PUD_SIZE
#define HFGITR_EL2_TLBIRVALE1IS_MASK GENMASK(36, 36)
#define VFS_CAP_REVISION_1 0x01000000
#define MAS_OVERFLOW ((struct maple_enode *)33UL)
#define ESTATUS_1000_THALF 0x1000
#define pm_generic_suspend_late NULL
#define MDIO_PCS_SPEED_5G 0x0080
#define MT_NORMAL_TAGGED 1
#define PR_MTE_TCF_ASYNC (1UL << 2)
#define PR_GET_SECCOMP 21
#define __HFGWTR_EL2_MASK GENMASK(49, 0)
#define VFS_CAP_REVISION_2 0x02000000
#define CFI_BRK_IMM_MASK (CFI_BRK_IMM_TARGET | CFI_BRK_IMM_TYPE)
#define __UAPI_DEF_IPV6_MREQ 1
#define CONFIG_ETHTOOL_NETLINK 1
#define VFS_CAP_REVISION_3 0x03000000
#define ID_MMFR4_EL1_UNKN (UL(0))
#define PR_SVE_GET_VL 51
#define __LINUX_RCUTREE_H 
#define ATTR_FILE (1 << 13)
#define ETH_P_LINK_CTL 0x886c
#define PERCPU_DYNAMIC_EARLY_SIZE (20 << PERCPU_DYNAMIC_SIZE_SHIFT)
#define COMPAT_HWCAP_ASIMDFHM (1 << 25)
#define MDIO_MMD_AN 7
#define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd))
#define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
#define ESR_ELx_EC_BTI (0x0D)
#define FAR_EL12_ADDR_SHIFT 0
#define MMF_DISABLE_THP 24
#define __local_inc(l) local_set((l), local_read(l) + 1)
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
#define S_IFLNK 0120000
#define ID_MMFR0_EL1_FCSE_IMP UL(0b0001)
#define SCTLR_EL1_IESB_WIDTH 1
#define ID_AA64PFR1_EL1_MTEX GENMASK(55, 52)
#define ARM64_KVM_PROTECTED_MODE 51
#define HDFGRTR_EL2_nPMSNEVFR_EL1 GENMASK(62, 62)
#define HCRX_EL2_EnALS_SHIFT 1
#define SYSCTL_MAXOLDUID ((void *)&sysctl_vals[10])
#define HFGITR_EL2_TLBIVAALE1_MASK GENMASK(47, 47)
#define JOBCTL_TRAP_STOP (1UL << JOBCTL_TRAP_STOP_BIT)
#define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
#define SCTLR_EL1_TCF0_SYNC UL(0b01)
#define POLLFREE (__force __poll_t)0x4000
#define SIGNAL_CLD_CONTINUED 0x00000020
#define SEGV_ADIDERR 6
#define sve_vq_from_vl(vl) __sve_vq_from_vl(vl)
#define CONFIG_GPIOLIB 1
#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 
#define ARM64_ASM_ARCH "armv8.5-a"
#define XA_MARK_1 ((__force xa_mark_t)1U)
#define ESRMNT 69
#define PHY_PAIR_ALL -1
#define PLIST_NODE_INIT(node,__prio) { .prio = (__prio), .prio_list = LIST_HEAD_INIT((node).prio_list), .node_list = LIST_HEAD_INIT((node).node_list), }
#define CONFIG_SERIAL_CORE_CONSOLE 1
#define HFGITR_EL2_ATS1E1W_WIDTH 1
#define HCRX_EL2_TCR2En_WIDTH 1
#define PMBSR_EL1_DL GENMASK(19, 19)
#define check_sub_overflow(a,b,d) __must_check_overflow(__builtin_sub_overflow(a, b, d))
#define ID_AA64ISAR0_EL1_RDM_WIDTH 4
#define SYS_ID_MMFR0_EL1_CRn 0
#define PAGE_POISON_PATTERN -1l
#define FS_GROUP_QUOTA (1<<2)
#define HDFGRTR_EL2_PMSLATFR_EL1_SHIFT 32
#define ESR_ELx_EC_IABT_LOW (0x20)
#define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
#define pfn_to_nid(pfn) (0)
#define ID_AA64ZFR0_EL1_F64MM_WIDTH 4
#define dev_WARN(dev,format,arg...) WARN(1, "%s %s: " format, dev_driver_string(dev), dev_name(dev), ## arg)
#define SYS_PIR_EL1_Op1 0
#define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
#define __MODULE_INFO_PREFIX KBUILD_MODNAME "."
#define ID_AA64AFR0_EL1_IMPDEF3_MASK GENMASK(15, 12)
#define pcibus_to_node(bus) ((void)(bus), -1)
#define SYS_ID_PFR0_EL1_CRm 1
#define SYS_ID_PFR0_EL1_CRn 0
#define PMBSR_EL1_EA GENMASK(18, 18)
#define PMBSR_EL1_EC GENMASK(31, 26)
#define DMA_ATTR_FORCE_CONTIGUOUS (1UL << 6)
#define pud_offset pud_offset
#define SETALL 17
#define CONFIG_CGROUPS 1
#define ID_DFR0_EL1_MMapDbg_NI UL(0b0000)
#define VM_EXEC 0x00000004
#define ECONNABORTED 103
#define MDIO_PMA_SPEED_2B 0x0002
#define LLIST_HEAD_INIT(name) { NULL }
#define KUNIT_FALSE_MSG_ASSERTION(test,assert_type,condition,fmt,...) KUNIT_UNARY_ASSERTION(test, assert_type, condition, false, fmt, ##__VA_ARGS__)
#define ENOANO 55
#define KERNEL_HWCAP_LRCPC __khwcap_feature(LRCPC)
#define SB_RDONLY BIT(0)
#define MSEC_TO_HZ_DEN 4
#define ID_AA64MMFR3_EL1_SCTLRX_NI UL(0b0000)
#define while_each_pid_task(pid,type,task) if (type == PIDTYPE_PID) break; } } while (0)
#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
#define PM_EVENT_AUTO_SUSPEND (PM_EVENT_AUTO | PM_EVENT_SUSPEND)
#define PMSEVFR_EL1_E GENMASK(63, 0)
#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
#define __NR_recvfrom 207
#define SCTLR_EL1_A_WIDTH 1
#define MVFR2_EL1_FPMisc_WIDTH 4
#define FS_XFLAG_IMMUTABLE 0x00000008
#define CLIDR_EL1_Ctype6_SHIFT 15
#define STATIC_CALL_TRAMP_STR(name) __stringify(STATIC_CALL_TRAMP(name))
#define __NR_dup 23
#define _LINUX_SIPHASH_H 
#define ZA_PT_ZA_OFFSET ((sizeof(struct user_za_header) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
#define ID_AA64ZFR0_EL1_SM4_MASK GENMASK(43, 40)
#define PT_GNU_RELRO (PT_LOOS + 0x474e552)
#define SEM_INFO 19
#define user_write_access_begin user_access_begin
#define ARM_BREAKPOINT_LEN_1 0x1
#define ARM_BREAKPOINT_LEN_2 0x3
#define ARM_BREAKPOINT_LEN_3 0x7
#define ARM_BREAKPOINT_LEN_4 0xf
#define ARM_BREAKPOINT_LEN_5 0x1f
#define ARM_BREAKPOINT_LEN_6 0x3f
#define ARM_BREAKPOINT_LEN_7 0x7f
#define ARM_BREAKPOINT_LEN_8 0xff
#define this_cpu_try_cmpxchg64(pcp,ovalp,nval) __cpu_fallback_try_cmpxchg(pcp, ovalp, nval, this_cpu_cmpxchg64)
#define IS_ENCRYPTED(inode) ((inode)->i_flags & S_ENCRYPTED)
#define CLD_KILLED 2
#define HVC_SET_VECTORS 0
#define ID_AA64MMFR0_EL1_BIGEND_WIDTH 4
#define SMPRIMAP_EL2_P12_SHIFT 48
#define fwnode_has_op(fwnode,op) (!IS_ERR_OR_NULL(fwnode) && (fwnode)->ops && (fwnode)->ops->op)
#define SIOCADDRT 0x890B
#define SCTLR_EL1_RES0 (UL(0) | GENMASK_ULL(59, 58) | GENMASK_ULL(34, 34) | GENMASK_ULL(17, 17))
#define SOCKWQ_ASYNC_WAITDATA 1
#define ID_AFR0_EL1_IMPDEF1_SHIFT 4
#define MVFR0_EL1_FPSqrt_WIDTH 4
#define F_EXLCK 4
#define SYS_ALLINT_CRm 3
#define SYS_ALLINT_CRn 4
#define NODE_MASK_ALL ((nodemask_t) { { [BITS_TO_LONGS(MAX_NUMNODES)-1] = NODE_MASK_LAST_WORD } })
#define __UAPI_DEF_IP_MREQ 1
#define SCTLR_EL1_TWEDEL GENMASK(49, 46)
#define _AC(X,Y) __AC(X,Y)
#define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800
#define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
#define IS_MANDLOCK(inode) __IS_FLG(inode, SB_MANDLOCK)
#define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1)
#define ID_AA64ISAR0_EL1_CRC32_MASK GENMASK(19, 16)
#define min(x,y) __careful_cmp(min, x, y)
#define ID_ISAR3_EL1_SynchPrim_MASK GENMASK(15, 12)
#define ID_AA64ISAR1_EL1_GPI_NI UL(0b0000)
#define SCTLR_EL1_BT0_MASK GENMASK(35, 35)
#define __ASM_GENERIC_SOCKIOS_H 
#define ESR_ELx_EC_VECTOR32 (0x3A)
#define I_DONTCACHE (1 << 16)
#define MDIO_PMA_CTRL2_10GBLR 0x0006
#define IORESOURCE_EXCLUSIVE 0x08000000
#define PIRx_ELx_Perm15_WIDTH 4
#define SYS_ID_AA64DFR1_EL1_Op1 0
#define ID_AA64PFR1_EL1_SME_NI UL(0b0000)
#define HDFGWTR_EL2_TRBSR_EL1_SHIFT 55
#define init_name_hash(salt) (unsigned long)(salt)
#define OSECCR_EL1_EDECCR_MASK GENMASK(31, 0)
#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
#define __initcall_stub(fn,__iid,id) fn
#define __no_sanitize_coverage 
#define __ASM_POINTER_AUTH_H 
#define ID_ISAR2_EL1_MultiAccessInt_RESTARTABLE UL(0b0001)
#define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5)
#define F_OFD_SETLKW 38
#define HWCAP2_SVE_EBF16 (1UL << 33)
#define HCRX_EL2_FnXS GENMASK(3, 3)
#define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias)
#define ID_MMFR4_EL1_CnP_NI UL(0b0000)
#define TCR2_EL2_HAFT GENMASK(11, 11)
#define HCRX_EL2_FGTnXS_SHIFT 4
#define ID_AA64PFR0_EL1_MPAM GENMASK(43, 40)
#define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
#define FILESYSTEM_MAX_STACK_DEPTH 2
#define netif_notice(priv,type,dev,fmt,args...) netif_level(notice, priv, type, dev, fmt, ##args)
#define flowi6_mark __fl_common.flowic_mark
#define this_cpu_try_cmpxchg_1(pcp,ovalp,nval) __cpu_fallback_try_cmpxchg(pcp, ovalp, nval, this_cpu_cmpxchg_1)
#define ID_AA64ISAR0_EL1_CRC32_IMP UL(0b0001)
#define HFGITR_EL2_TLBIVAAE1OS_WIDTH 1
#define this_cpu_try_cmpxchg_4(pcp,ovalp,nval) __cpu_fallback_try_cmpxchg(pcp, ovalp, nval, this_cpu_cmpxchg_4)
#define MPIDR_LEVEL_SHIFT(level) (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
#define CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419 1
#define INVALID_GID KGIDT_INIT(-1)
#define IFF_DEBUG IFF_DEBUG
#define FAR_EL2_ADDR_MASK GENMASK(63, 0)
#define CPACR_EL1_SMEN_EL0EN (BIT(25))
#define HCR_HCD (UL(1) << 29)
#define MDIO_PCS_SPEED_2_5G 0x0040
#define ICH_MISR_EOI (1 << 0)
#define _IOC_SIZEBITS 14
#define I_DIRTY_INODE (I_DIRTY_SYNC | I_DIRTY_DATASYNC)
#define put_cpu_var(var) do { (void)&(var); preempt_enable(); } while (0)
#define MVFR1_EL1_FPDNaN_NI UL(0b0000)
#define UUID_SIZE 16
#define ID_PFR1_EL1_Virtualization_NI UL(0b0000)
#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
#define ID_PFR0_EL1_AMU_SHIFT 20
#define EISCONN 106
#define EM_860 7
#define ID_ISAR3_EL1_SynchPrim_DOUBLE UL(0b0010)
#define TRBMAR_EL1_PAS_ROOT UL(0b10)
#define ID_AA64MMFR3_EL1_D128_2_SIGNED false
#define PMSFCR_EL1_B GENMASK(16, 16)
#define PACKET_OTHERHOST 3
#define VFSGIDT_INIT(val) (vfsgid_t){ __kgid_val(val) }
#define fwnode_call_void_op(fwnode,op,...) do { if (fwnode_has_op(fwnode, op)) (fwnode)->ops->op(fwnode, ## __VA_ARGS__); } while (false)
#define ID_AA64ISAR1_EL1_SB_IMP UL(0b0001)
#define param_check_hexint(name,p) param_check_uint(name, p)
#define IRQF_TRIGGER_PROBE 0x00000010
#define FS_RENAME_DOES_D_MOVE 32768
#define S_DIRSYNC (1 << 6)
#define __NR_recvmmsg 243
#define CONFIG_AS_HAS_LDAPR 1
#define SPINLOCK_MAGIC 0xdead4ead
#define MIDR_RANGE(m,v_min,r_min,v_max,r_max) { .model = m, .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), }
#define smp_mb__after_unlock_lock() do { } while (0)
#define HFGITR_EL2_TLBIVAAE1_SHIFT 45
#define I3C_MATCH_PART 0x4
#define CONFIG_HDMI 1
#define PSR_AA32_C_BIT 0x20000000
#define arch_atomic64_andnot arch_atomic64_andnot
#define EPOLLIN (__force __poll_t)0x00000001
#define ID_ISAR6_EL1_BF16 GENMASK(23, 20)
#define RNDRESEEDCRNG _IO( 'R', 0x07 )
#define ARM64_WORKAROUND_CAVIUM_23154 86
#define ECN(x) { ESR_ELx_EC_ ##x, #x }
#define ID_AA64SMFR0_EL1_I16I32_IMP UL(0b0101)
#define _LINUX_SCHED_MM_H 
#define __ADDRESSABLE(sym) ___ADDRESSABLE(sym, __section(".discard.addressable"))
#define CPUCLOCK_PERTHREAD(clock) (((clock) & (clockid_t) CPUCLOCK_PERTHREAD_MASK) != 0)
#define AT_VECTOR_SIZE_ARCH 2
#define KUNIT_ASSERT_NOT_NULL_MSG(test,ptr,fmt,...) KUNIT_BINARY_PTR_ASSERTION(test, KUNIT_ASSERTION, ptr, !=, NULL, fmt, ##__VA_ARGS__)
#define __be16_to_cpu(x) __swab16((__force __u16)(__be16)(x))
#define PCMCIA_DEV_ID_MATCH_DEVICE_NO 0x0100
#define EUSERS 87
#define SYS_DCZID_EL0_CRm 0
#define MODULE_DEVICE_TABLE(type,name) 
#define __iormb(v) __io_ar(v)
#define __GFP_BITS_MASK ((__force gfp_t)((1 << __GFP_BITS_SHIFT) - 1))
#define SCTLR_EL1_EnDB_MASK GENMASK(13, 13)
#define __test_and_change_bit(nr,addr) bitop(___test_and_change_bit, nr, addr)
#define SIOCGRARP 0x8961
#define ISR_EL1_F_SHIFT 6
#define PR_MCE_KILL_GET 34
#define HFGxTR_EL2_ERRIDR_EL1_SHIFT 40
#define HDFGWTR_EL2_OSLAR_EL1 GENMASK(8, 8)
#define CCW_DEVICE_ID_MATCH_CU_TYPE 0x01
#define MDCR_EL2_HPMD (UL(1) << 17)
#define MDIO_PMA_LASI_TX_PMALFLT 0x0010
#define ID_ISAR5_EL1_CRC32_MASK GENMASK(19, 16)
#define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
#define ETHTOOL_RX_FLOW_SPEC_RING_VF 0x000000FF00000000LL
#define CONFIG_GENERIC_STRNLEN_USER 1
#define MDIO_PMD_RXDET_2 0x0008
#define MDIO_PMD_RXDET_3 0x0010
#define CONFIG_NET_VENDOR_INTEL 1
#define _UAPI_LINUX_SOCKET_H 
#define MVFR2_EL1_FPMisc_FP_MAX_MIN UL(0b0100)
#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ 
#define ADVERTISED_10000baseKX4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKX4_Full)
#define FS_XFLAG_NODUMP 0x00000080
#define __GFP_RECLAIMABLE ((__force gfp_t)___GFP_RECLAIMABLE)
#define HFGITR_EL2_nGCSEPP_WIDTH 1
#define compat_thumb_mode(regs) (0)
#define _UAPI_ASM_GENERIC_INT_LL64_H 
#define ARM64_HAS_DIT 17
#define IS_NOSEC(inode) ((inode)->i_flags & S_NOSEC)
#define LORID_EL1_LR GENMASK(7, 0)
#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5)
#define HDFGWTR_EL2_PMBPTR_EL1 GENMASK(24, 24)
#define SYS_ID_AA64ISAR0_EL1_Op1 0
#define MINORMASK ((1U << MINORBITS) - 1)
#define CONFIG_CPU_LITTLE_ENDIAN 1
#define EX_DATA_REG_ZERO_SHIFT 5
#define ID_MMFR2_EL1_UniTLB_BY_ALL_ASID UL(0b0011)
#define HCRX_EL2_EnSDERR_WIDTH 1
#define MM_CP_PROT_NUMA (1UL << 1)
#define HWCAP2_SVE_B16B16 (1UL << 45)
#define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
#define arch_atomic_fetch_or_release arch_atomic_fetch_or_release
#define arch_rwlock_is_contended(l) queued_rwlock_is_contended(l)
#define set_numa_mem(node) 
#define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
#define NT_S390_TODPREG 0x303
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define CONFIG_ARM64_AS_HAS_MTE 1
#define SYS_ID_AA64AFR1_EL1_Op0 3
#define SYS_ID_AA64AFR1_EL1_Op2 5
#define ITER_DEST 0
#define TRBIDR_EL1_Align_WIDTH 4
#define pmd_user(pmd) pte_user(pmd_pte(pmd))
#define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
#define ptrauth_thread_switch_kernel(tsk) 
#define EPOLLERR (__force __poll_t)0x00000008
#define SCTLR_EL1_CMOW_SHIFT 32
#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
#define SYS_ID_AA64AFR1_EL1_CRm 5
#define ifr_addr ifr_ifru.ifru_addr
#define _linux_POSIX_TIMERS_H 
#define ID_MMFR4_EL1_XNX_IMP UL(0b0001)
#define ID_AA64MMFR0_EL1_FGT_MASK GENMASK(59, 56)
#define NGROUPS_MAX 65536
#define swahw32 __swahw32
#define ARM64_HAS_ADDRESS_AUTH 5
#define raw_safe_halt() arch_safe_halt()
#define AT_PAGESZ 6
#define INR_OPEN_CUR 1024
#define RWLOCK_MAGIC 0xdeaf1eed
#define ID_AA64MMFR3_EL1_D128 GENMASK(35, 32)
#define ID_ISAR3_EL1_T32EE_SHIFT 28
#define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
#define HDFGRTR_EL2_OSECCR_EL1 GENMASK(10, 10)
#define HFGITR_EL2_TLBIRVAAE1IS_SHIFT 35
#define ID_AA64ISAR1_EL1_LS64_LS64 UL(0b0001)
#define HFGxTR_EL2_MPIDR_EL1_MASK GENMASK(26, 26)
#define VL_ARCH_MAX 0x100
#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100
#define ID_ISAR2_EL1_MemHint_PLDW UL(0b0100)
#define DCACHE_CANT_MOUNT 0x00000100
#define ID_AA64ISAR2_EL1_APA3_PAuth2 UL(0b0011)
#define SZ_2 0x00000002
#define SZ_4 0x00000004
#define MAX_CANON 255
#define SZ_8 0x00000008
#define TASK_RTLOCK_WAIT 0x00001000
#define HFGITR_EL2_TLBIVALE1_MASK GENMASK(46, 46)
#define num_online_nodes() num_node_state(N_ONLINE)
#define ID_ISAR4_EL1_Barrier_WIDTH 4
#define REG_SMPRIMAP_EL2 S3_4_C1_C2_5
#define CONFIG_CRC32_SLICEBY8 1
#define SEM_STAT 18
#define HFGITR_EL2_UNKN (UL(0))
#define SCTLR_EL1_EnDB_SHIFT 13
#define work_pending(work) test_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(work))
#define CONFIG_ARCH_INLINE_SPIN_LOCK_BH 1
#define HDFGWTR_EL2_PMCNTEN GENMASK(16, 16)
#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
#define USER_ASID_FLAG (UL(1) << USER_ASID_BIT)
#define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)
#define ID_AA64PFR0_EL1_AdvSIMD GENMASK(23, 20)
#define DN_MULTISHOT 0x80000000
#define SCTLR_ELx_nTLSMD (BIT(28))
#define ARM64_SME2 57
#define WUNTRACED 0x00000002
#define MDIO_AN_T1_ADV_M 515
#define NULL_UUID_LE UUID_LE(0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
#define ID_AA64MMFR0_EL1_TGRAN16_2_IMP UL(0b0010)
#define APM_CPU_VAR_POTENZA 0x00
#define _LINUX_KDEV_T_H 
#define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
#define __GFP_BITS_SHIFT (26 + IS_ENABLED(CONFIG_LOCKDEP))
#define CONFIG_PM_CLK 1
#define CONFIG_OF_EARLY_FLATTREE 1
#define _LINUX_DQBLK_XFS_H 
#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
#define CPTR_EL2_TAM (1 << 30)
#define IPV6_PMTUDISC_WANT 1
#define SUPPORTED_1000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Full)
#define SCTLR_EL1_EE GENMASK(25, 25)
#define _NET_TIMESTAMPING_H 
#define NOMMU_MAP_WRITE VM_MAYWRITE
#define HDFGRTR_EL2_TRBLIMITR_EL1_MASK GENMASK(52, 52)
#define MDIO_EEE_10GKX4 0x0020
#define DL_FLAG_INFERRED BIT(8)
#define EL3HLT 46
#define HFGITR_EL2_TLBIRVAALE1IS_MASK GENMASK(37, 37)
#define __NR_sched_setscheduler 119
#define ID_AA64MMFR1_EL1_HPDS_IMP UL(0b0001)
#define ESR_ELx_EC_WATCHPT_LOW (0x34)
#define SMIDR_EL1_AFFINITY_MASK GENMASK(11, 0)
#define CLONE_NEWUSER 0x10000000
#define LORC_EL1_UNKN (UL(0))
#define ID_AA64PFR0_EL1_AdvSIMD_WIDTH 4
#define sysreg_clear_set_s(sysreg,clear,set) do { u64 __scs_val = read_sysreg_s(sysreg); u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); if (__scs_new != __scs_val) write_sysreg_s(__scs_new, sysreg); } while (0)
#define ID_AA64ISAR1_EL1_API_FPAC UL(0b0100)
#define HFGITR_EL2_TLBIRVALE1_MASK GENMASK(40, 40)
#define CONFIG_GPIOLIB_IRQCHIP 1
#define PARITY_NONE 1
#define PF_VCPU 0x00000001
#define CONFIG_NET_VENDOR_XILINX 1
#define ioremap_prot ioremap_prot
#define CONFIG_STACKTRACE_SUPPORT 1
#define CONFIG_ARCH_WANT_LD_ORPHAN_WARN 1
#define SUPPORTED_40000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseKR4_Full)
#define CALLER_ADDR4 ((unsigned long)ftrace_return_address(4))
#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
#define SG_MITER_TO_SG (1 << 1)
#define ID_AA64AFR0_EL1_IMPDEF4_WIDTH 4
#define __GFP_RETRY_MAYFAIL ((__force gfp_t)___GFP_RETRY_MAYFAIL)
#define CONFIG_NET_VENDOR_AGERE 1
#define PIRx_ELx_Perm8_SHIFT 32
#define __NR_set_mempolicy_home_node 450
#define __SVE_PREG_OFFSET(vq,n) (__SVE_PREGS_OFFSET(vq) + __SVE_PREG_SIZE(vq) * (n))
#define HFGxTR_EL2_ICC_IGRPENn_EL1_MASK GENMASK(39, 39)
#define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
#define REG_TTBR1_EL1 S3_0_C2_C0_1
#define MAS_UNDERFLOW ((struct maple_enode *)65UL)
#define OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var))
#define PMSFCR_EL1_FT_SHIFT 1
#define PMSIRR_EL1_INTERVAL_MASK GENMASK(31, 8)
#define HFGxTR_EL2_AIDR_EL1_SHIFT 2
#define ID_AA64ISAR0_EL1_RES0 (UL(0) | GENMASK_ULL(3, 0))
#define ID_AA64ISAR0_EL1_RES1 (UL(0))
#define KERNEL_HWCAP_FPHP __khwcap_feature(FPHP)
#define SIGNAL_CLD_MASK (SIGNAL_CLD_STOPPED|SIGNAL_CLD_CONTINUED)
#define CONFIG_PROC_FS 1
#define CONFIG_BQL 1
#define __test_and_set_bit(nr,addr) bitop(___test_and_set_bit, nr, addr)
#define ioread32 ioread32
#define MDIO_MMD_TC 6
#define ftrace_ops_set_global_filter(ops) do { } while (0)
#define srcu_cleanup_notifier_head(name) cleanup_srcu_struct(&(name)->srcu);
#define PMSIDR_EL1_LDS_SHIFT 4
#define WORKINGSET_ANON 0
#define ID_ISAR2_EL1_MultU GENMASK(23, 20)
#define EM_OPENRISC 92
#define MDIO_PMA_CTRL2_10GBSR 0x0007
#define SCTLR_EL1_ITFSB_MASK GENMASK(37, 37)
#define ID_AA64PFR1_EL1_BT_MASK GENMASK(3, 0)
#define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
#define _LINUX_ATOMIC_LONG_H 
#define HDFGWTR_EL2_PMSCR_EL1_MASK GENMASK(26, 26)
#define HWCAP_FP (1 << 0)
#define NR_PCP_LISTS (NR_LOWORDER_PCP_LISTS + NR_PCP_THP)
#define VM_BUG_ON_PGFLAGS(cond,page) BUILD_BUG_ON_INVALID(cond)
#define DACR32_EL2_D6_SHIFT 12
#define ID_AA64ISAR1_EL1_I8MM_NI UL(0b0000)
#define ID_AA64ISAR1_EL1_API_EPAC UL(0b0010)
#define EM_BPF 247
#define SVCR_SM GENMASK(0, 0)
#define __ASM_COMPAT_H 
#define TC_AT_INGRESS_MASK (1 << 1)
#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200
#define pud_valid(pud) pte_valid(pud_pte(pud))
#define __NR_sigaltstack 132
#define IS_GETLK(cmd) (IS_GETLK32(cmd) || IS_GETLK64(cmd))
#define SB_DYING BIT(24)
#define WRAP_DIR_ITER(x) static int shared_ ##x(struct file *file , struct dir_context *ctx) { return wrap_directory_iterator(file, ctx, x); }
#define NR_LOWORDER_PCP_LISTS (MIGRATE_PCPTYPES * (PAGE_ALLOC_COSTLY_ORDER + 1))
#define TRBSR_EL1_EC_WIDTH 6
#define ESTRPIPE 86
#define INIT_PSTATE_EL1 (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h)
#define INIT_PSTATE_EL2 (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL2h)
#define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8)
#define SIOCSIFLINK 0x8911
#define ID_PFR0_EL1_RAS_MASK GENMASK(31, 28)
#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
#define __COUNT_ARGS(_0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_n,X...) _n
#define ETH_P_MVRP 0x88F5
#define TCR2_EL1x_DisCH1_MASK GENMASK(15, 15)
#define ID_AA64AFR0_EL1_IMPDEF5_MASK GENMASK(23, 20)
#define __ASM_SPECTRE_H 
#define MODULE_ALIAS_NETPROTO(proto) MODULE_ALIAS("net-pf-" __stringify(proto))
#define ID_MMFR3_EL1_CMemSz_1TB UL(0b0010)
#define CONFIG_SCSI_MOD 1
#define _ASM_GENERIC_ERRNO_H 
#define EAGAIN 11
#define ___GFP_SKIP_ZERO 0
#define SECCOMP_RET_KILL_THREAD 0x00000000U
#define ARM64_WORKAROUND_858921 68
#define PF_RXRPC AF_RXRPC
#define IPC_64 0x0100
#define EM_PERF_DOMAIN_MICROWATTS BIT(0)
#define THP_FILE_FALLBACK ({ BUILD_BUG(); 0; })
#define _KREF_H_ 
#define PIE_RWnX_O 0x6
#define PF_MPLS AF_MPLS
#define __iowmb() __io_bw()
#define TRAMP_SWAPPER_OFFSET (2 * PAGE_SIZE)
#define LIST_HEAD_INIT(name) { &(name), &(name) }
#define ZCR_ELx_RES0 (UL(0) | GENMASK_ULL(63, 9))
#define ZCR_ELx_RES1 (UL(0))
#define SYS_TPIDR_EL1_CRm 0
#define SYS_TPIDR_EL1_CRn 13
#define PAGE_FRAG_CACHE_MAX_SIZE __ALIGN_MASK(32768, ~PAGE_MASK)
#define PMBLIMITR_EL1_PMFZ_SHIFT 5
#define IOCONTEXT_H 
#define local_lock_irqsave(lock,flags) __local_lock_irqsave(lock, flags)
#define __INT16_C(c) c
#define uprobe_get_trap_addr(regs) instruction_pointer(regs)
#define ID_AA64MMFR1_EL1_RES1 (UL(0))
#define ID_AA64ISAR0_EL1_SM4_WIDTH 4
#define KUNIT_EXPECT_PTR_EQ(test,left,right) KUNIT_EXPECT_PTR_EQ_MSG(test, left, right, NULL)
#define ID_AA64MMFR2_EL1_IESB_WIDTH 4
#define vma_alloc_folio(gfp,order,vma,addr,hugepage) folio_alloc(gfp, order)
#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
#define HDFGWTR_EL2_TRBBASER_EL1 GENMASK(50, 50)
#define SOL_AAL 265
#define arch_initcall_sync(fn) __define_initcall(fn, 3s)
#define ARCH_PFN_OFFSET ((unsigned long)PHYS_PFN_OFFSET)
#define _ASM_GENERIC_IRQ_REGS_H 
#define PKT_TYPE_MAX 7
#define CONFIG_DMA_CMA 1
#define CONFIG_HAVE_CONTEXT_TRACKING_USER 1
#define EREMOTEIO 121
#define kcsan_wmb() do { } while (0)
#define ID_AA64ISAR0_EL1_SHA1_WIDTH 4
#define SYS_TTBR0_EL1_CRm 0
#define ID_MMFR4_EL1_CnP GENMASK(15, 12)
#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
#define CONFIG_VT_CONSOLE 1
#define IORESOURCE_IO_SPARSE (1<<2)
#define HCRX_EL2_EnIDCP128_SHIFT 21
#define COMPAT_HWCAP_VFPD32 (1 << 19)
#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
#define MDIO_STAT2_RXFAULT 0x0400
#define TCR2_EL1x_PTTWI_SHIFT 10
#define LED_COLOR_ID_VIOLET 5
#define MVFR2_EL1_FPMisc GENMASK(7, 4)
#define idr_for_each_entry_ul(idr,entry,tmp,id) for (tmp = 0, id = 0; ((entry) = tmp <= id ? idr_get_next_ul(idr, &(id)) : NULL) != NULL; tmp = id, ++id)
#define ID_MMFR3_EL1_BPMaint_BY_VA UL(0b0010)
#define ID_AA64MMFR1_EL1_nTLBPA_SHIFT 48
#define CONFIG_PCI 1
#define BITS_TO_U32(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u32))
#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
#define __NR_io_uring_register 427
#define IRQF_PERCPU 0x00000400
#define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
#define INIT_HLIST_BL_HEAD(ptr) ((ptr)->first = NULL)
#define SYS_PMBIDR_EL1_Op0 3
#define HCRX_EL2_EnALS_MASK GENMASK(1, 1)
#define netif_cond_dbg(priv,type,netdev,cond,level,fmt,args...) do { if (cond) netif_dbg(priv, type, netdev, fmt, ##args); else netif_ ## level(priv, type, netdev, fmt, ##args); } while (0)
#define EL2NSYNC 45
#define ID_AA64PFR0_EL1_MPAM_SIGNED false
#define PMSG_REMOTE_RESUME ((struct pm_message) { .event = PM_EVENT_REMOTE_RESUME, })
#define KUNIT_EXPECT_GT_MSG(test,left,right,fmt,...) KUNIT_BINARY_INT_ASSERTION(test, KUNIT_EXPECTATION, left, >, right, fmt, ##__VA_ARGS__)
#define SCTLR_EL1_LSMAOE_WIDTH 1
#define ZT_SIG_REG_BYTES (ZT_SIG_REG_SIZE / 8)
#define TIF_SYSCALL_TRACE 8
#define _UL(x) (_AC(x, UL))
#define U16_C(x) x ## U
#define CPACR_ELx_SMEN GENMASK(25, 24)
#define PF_ATMPVC AF_ATMPVC
#define SYS_SMIDR_EL1 sys_reg(3, 1, 0, 0, 6)
#define TRBSR_EL1_BSC_SHIFT 0
#define param_check_uint(name,p) __param_check(name, p, unsigned int)
#define ID_MMFR3_EL1_MaintBcst_MASK GENMASK(15, 12)
#define PAGECACHE_TAG_TOWRITE XA_MARK_2
#define builtin_driver(__driver,__register,...) static int __init __driver ##_init(void) { return __register(&(__driver) , ##__VA_ARGS__); } device_initcall(__driver ##_init);
#define HFGITR_EL2_DCCVADP_MASK GENMASK(9, 9)
#define TRBSR_EL1_IRQ_WIDTH 1
#define HFGxTR_EL2_ESR_EL1_SHIFT 16
#define debug_special_state_change(cond) do { } while (0)
#define PMSG_QUIESCE ((struct pm_message){ .event = PM_EVENT_QUIESCE, })
#define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
#define SIGVTALRM 26
#define local_irq_enable() do { trace_hardirqs_on(); raw_local_irq_enable(); } while (0)
#define __ASM_GENERIC_QSPINLOCK_H 
#define rcu_note_voluntary_context_switch(t) do { } while (0)
#define HZ_TO_MSEC_ADJ32 U64_C(0x0)
#define SHIFT_PERCPU_PTR(__p,__offset) RELOC_HIDE((typeof(*(__p)) __kernel __force *)(__p), (__offset))
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
#define pr_devel_once(fmt,...) no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
#define TRBLIMITR_EL1_FM_CBUF UL(0b11)
#define CPACR_ELx_FPEN_MASK GENMASK(21, 20)
#define HDFGRTR_EL2_PMUSERENR_EL0 GENMASK(57, 57)
#define RESOLVE_NO_SYMLINKS 0x04
#define ID_AA64SMFR0_EL1_I16I64_NI UL(0b0000)
#define ERESTART_RESTARTBLOCK 516
#define BIT(nr) (UL(1) << (nr))
#define BLOCKING_INIT_NOTIFIER_HEAD(name) do { init_rwsem(&(name)->rwsem); (name)->head = NULL; } while (0)
#define CCSIDR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define CCSIDR_EL1_RES1 (UL(0))
#define ENOPKG 65
#define NT_ARM_PAC_ENABLED_KEYS 0x40a
#define FS_IOC_GETFLAGS _IOR('f', 1, long)
#define FMODE_DIO_PARALLEL_WRITE ((__force fmode_t)0x1000000)
#define __no_sanitize_undefined __attribute__((__no_sanitize_undefined__))
#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
#define SMPRIMAP_EL2_P8_WIDTH 4
#define TP_STATUS_KERNEL 0
#define cmpxchg_relaxed(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg_relaxed(__ai_ptr, __VA_ARGS__); })
#define safe_halt() do { trace_hardirqs_on(); raw_safe_halt(); } while (0)
#define write_lock_bh(lock) _raw_write_lock_bh(lock)
#define raw_cpu_xchg(pcp,nval) __pcpu_size_call_return2(raw_cpu_xchg_, pcp, nval)
#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
#define swab64p __swab64p
#define swab64s __swab64s
#define FD_CLOEXEC 1
#define rcu_dereference(p) rcu_dereference_check(p, 0)
#define R_AARCH64_MOVW_UABS_G0_NC 264
#define DO_ONCE_SLEEPABLE(func,...) ({ bool ___ret = false; static bool __section(".data.once") ___done = false; static DEFINE_STATIC_KEY_TRUE(___once_key); if (static_branch_unlikely(&___once_key)) { ___ret = __do_once_sleepable_start(&___done); if (unlikely(___ret)) { func(__VA_ARGS__); __do_once_sleepable_done(&___done, &___once_key, THIS_MODULE); } } ___ret; })
#define ETHTOOL_GMODULEINFO 0x00000042
#define HFGxTR_EL2_nPOR_EL0 GENMASK(59, 59)
#define HFGxTR_EL2_nPOR_EL1 GENMASK(60, 60)
#define PMBSR_EL1_RES1 (UL(0))
#define PR_FP_EXC_NONRECOV 1
#define __NR_arch_specific_syscall 244
#define HDFGRTR_EL2_TRCSSCSRn_SHIFT 46
#define roundup(x,y) ( { typeof(y) __y = y; (((x) + (__y - 1)) / __y) * __y; } )
#define this_cpu_and_2(pcp,val) _pcp_protect(__percpu_andnot_case_16, pcp, ~val)
#define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
#define try_cmpxchg128(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); kcsan_mb(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg128(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define FLOW_DISSECTOR_F_STOP_BEFORE_ENCAP BIT(3)
#define CONFIG_CC_IMPLICIT_FALLTHROUGH "-Wimplicit-fallthrough=5"
#define atomic_long_cond_read_acquire atomic64_cond_read_acquire
#define ATTR_ATIME_SET (1 << 7)
#define arch_leave_lazy_mmu_mode() do {} while (0)
#define LEDS_GPIO_DEFSTATE_ON LEDS_DEFSTATE_ON
#define KENTRY(sym) extern typeof(sym) sym; static const unsigned long __kentry_ ##sym __used __attribute__((__section__("___kentry+" #sym))) = (unsigned long)&sym;
#define SI_KERNEL 0x80
#define __INT8_C(c) c
#define ISR_EL1_IS_MASK GENMASK(10, 10)
#define NETLINK_LIST_MEMBERSHIPS 9
#define S16_MIN ((s16)(-S16_MAX - 1))
#define __irq_exit() do { account_hardirq_exit(current); lockdep_hardirq_exit(); preempt_count_sub(HARDIRQ_OFFSET); } while (0)
#define ID_AA64DFR0_EL1_CTX_CMPs_MASK GENMASK(31, 28)
#define SYS_MVFR0_EL1_Op0 3
#define SYS_MVFR0_EL1_Op1 0
#define SYS_MVFR0_EL1_Op2 0
#define __NR_fanotify_mark 263
#define ID_MMFR1_EL1_L1TstCln_MASK GENMASK(27, 24)
#define HDFGWTR_EL2_TRC_WIDTH 1
#define ID_ISAR6_EL1_JSCVT_WIDTH 4
#define U8_MAX ((u8)~0U)
#define OPT_ZONE_HIGHMEM ZONE_NORMAL
#define SYS_RECVMSG 17
#define HFGITR_EL2_ATS1E1RP_MASK GENMASK(16, 16)
#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
#define HFGxTR_EL2_ERXSTATUS_EL1_MASK GENMASK(44, 44)
#define net_notice_ratelimited(fmt,...) net_ratelimited_function(pr_notice, fmt, ##__VA_ARGS__)
#define TRBLIMITR_EL1_XE_WIDTH 1
#define local_lock_init(lock) __local_lock_init(lock)
#define SYS_ID_DFR0_EL1_CRm 1
#define SYS_ID_DFR0_EL1_CRn 0
#define __GFP_NORETRY ((__force gfp_t)___GFP_NORETRY)
#define IS_ENABLED(option) __or(IS_BUILTIN(option), IS_MODULE(option))
#define HCRX_EL2_FnXS_MASK GENMASK(3, 3)
#define _UAPI_LINUX_TYPES_H 
#define SCTLR_EL1_SA GENMASK(3, 3)
#define AF_IPX 4
#define RAW_NOTIFIER_HEAD(name) struct raw_notifier_head name = RAW_NOTIFIER_INIT(name)
#define _PAGE_READONLY_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
#define PT_TRACE_EXIT PT_EVENT_FLAG(PTRACE_EVENT_EXIT)
#define current_fsuid() (current_cred_xxx(fsuid))
#define CLONE_IO 0x80000000
#define JOBCTL_TRACED (1UL << JOBCTL_TRACED_BIT)
#define ID_AA64MMFR0_EL1_SNSMEM_SIGNED false
#define UAPI_SA_FLAGS (SA_NOCLDSTOP | SA_NOCLDWAIT | SA_SIGINFO | SA_ONSTACK | SA_RESTART | SA_NODEFER | SA_RESETHAND | SA_EXPOSE_TAGBITS | __ARCH_UAPI_SA_FLAGS)
#define AF_APPLETALK 5
#define CONFIG_SPARSEMEM_EXTREME 1
#define ID_AA64MMFR3_EL1_ADERR_NI UL(0b0000)
#define MDIO_PMA_CTRL2_10GBER 0x0005
#define KUNIT_EXPECT_EQ_MSG(test,left,right,fmt,...) KUNIT_BINARY_INT_ASSERTION(test, KUNIT_EXPECTATION, left, ==, right, fmt, ##__VA_ARGS__)
#define PMSLATFR_EL1_RES0 (UL(0) | GENMASK_ULL(63, 16))
#define PMSLATFR_EL1_RES1 (UL(0))
#define SMIDR_EL1_SMPS_SHIFT 15
#define NOMMU_MAP_READ VM_MAYREAD
#define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO)
#define SO_ATTACH_FILTER 26
#define ETHTOOL_FLASH_MAX_FILENAME 128
#define test_bit(nr,addr) bitop(_test_bit, nr, addr)
#define FLOW_DISSECTOR_F_PARSE_1ST_FRAG BIT(0)
#define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4
#define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6
#define HFGITR_EL2_DCCISW_SHIFT 6
#define STB_LOCAL 0
#define ID_ISAR6_EL1_SB_NI UL(0b0000)
#define ESR_ELx_AR_SHIFT (14)
#define ID_AA64ISAR1_EL1_DGH_SIGNED false
#define ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 83
#define STATIC_CALL_KEY_PREFIX_LEN (sizeof(STATIC_CALL_KEY_PREFIX_STR) - 1)
#define __wait_event_freezable_exclusive(wq,condition) ___wait_event(wq, condition, (TASK_INTERRUPTIBLE|TASK_FREEZABLE), 1, 0, schedule())
#define TCR2_EL2_PTTWI_MASK GENMASK(10, 10)
#define ID_AA64MMFR3_EL1_D128_2_SHIFT 36
#define SCTLR_EL1_TCF0 GENMASK(39, 38)
#define _LINUX_CAPABILITY_U32S_1 1
#define HWCAP_SB (1 << 29)
#define _LINUX_CAPABILITY_U32S_3 2
#define ENOTUNIQ 76
#define SHT_SYMTAB 2
#define REG_TCR2_EL2 S3_4_C2_C0_3
#define SHRINK_STOP (~0UL)
#define NETLINK_BROADCAST_ERROR 4
#define DRIVER_ATTR_RW(_name) struct driver_attribute driver_attr_ ##_name = __ATTR_RW(_name)
#define __raw_writeq __raw_writeq
#define ARM_KERNEL_STEP_SUSPEND 2
#define MDSCR_EL1_ERR_WIDTH 1
#define MOD_ESTERROR ADJ_ESTERROR
#define PLATFORM_MODULE_PREFIX "platform:"
#define ___is_defined(val) ____is_defined(__ARG_PLACEHOLDER_ ##val)
#define ID_AA64DFR0_EL1_PMUVer GENMASK(11, 8)
#define NT_PPC_DEXCR 0x111
#define try_cmpxchg64_relaxed(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg64_relaxed(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define __WALL 0x40000000
#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
#define MDIO_PMD_STAT2_TXDISAB 0x0100
#define ID_AA64DFR0_EL1_BRPs_SHIFT 12
#define CONFIG_XXHASH 1
#define MMF_DUMP_FILTER_MASK (((1 << MMF_DUMP_FILTER_BITS) - 1) << MMF_DUMP_FILTER_SHIFT)
#define EARLY_ENTRIES(vstart,vend,shift,add) (SPAN_NR_ENTRIES(vstart, vend, shift) + (add))
#define CTR_EL0_L1Ip_VPIPT UL(0b00)
#define ID_AA64ISAR0_EL1_SHA1_SIGNED false
#define ID_ISAR0_EL1_BitCount_IMP UL(0b0001)
#define ID_AA64MMFR0_EL1_TGRAN64_NI UL(0b1111)
#define SOL_ALG 279
#define O_LARGEFILE 0400000
#define CONFIG_RTC_INTF_DEV 1
#define S_IMMUTABLE (1 << 3)
#define __ASM_GENERIC_BARRIER_H 
#define ID_ISAR2_EL1_PSR_AR_NI UL(0b0000)
#define AT_EMPTY_PATH 0x1000
#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
#define __task_cred(task) rcu_dereference((task)->real_cred)
#define mmiowb_set_pending() do { } while (0)
#define ID_ISAR1_EL1_Jazelle_WIDTH 4
#define ID_ISAR6_EL1_SB_WIDTH 4
#define CONFIG_NET_VENDOR_I825XX 1
#define HDFGRTR_EL2_DBGBVRn_EL1_SHIFT 1
#define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9)
#define CONFIG_HAVE_CMPXCHG_DOUBLE 1
#define DIPC 25
#define MDIO_AN_EEE_ADV 60
#define _LINUX_PGTABLE_H 
#define ID_MMFR3_EL1_BPMaint_MASK GENMASK(11, 8)
#define MNT_ATIME_MASK (MNT_NOATIME | MNT_NODIRATIME | MNT_RELATIME )
#define xas_marked(xas,mark) xa_marked((xas)->xa, (mark))
#define lockdep_hrtimer_exit(__expires_hardirq) do { if (!__expires_hardirq) current->irq_config = 0; } while (0)
#define __list_check_rcu(dummy,cond,extra...) ({ check_arg_count_one(extra); })
#define SCTLR_EL1_SA_WIDTH 1
#define HWCAP2_SVEBITPERM (1 << 4)
#define mutex_acquire_nest(l,s,t,n,i) lock_acquire_exclusive(l, s, t, n, i)
#define HDFGWTR_EL2_TRCAUXCTLR_WIDTH 1
#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
#define OSDTRTX_EL1_UNKN (UL(0))
#define skb_shinfo(SKB) ((struct skb_shared_info *)(skb_end_pointer(SKB)))
#define ETH_P_DNA_DL 0x6001
#define ID_AA64MMFR2_EL1_E0PD_NI UL(0b0000)
#define IFF_NOTRAILERS IFF_NOTRAILERS
#define ROOT_TAG_SHIFT (__GFP_BITS_SHIFT)
#define ENCODING_DEFAULT 0
#define __iomem 
#define SCTLR_EL1_MSCEn_WIDTH 1
#define ID_AA64MMFR2_EL1_EVT_TTLBxS UL(0b0010)
#define ID_ISAR0_EL1_Coproc_NI UL(0b0000)
#define NT_S390_HIGH_GPRS 0x300
#define JOBCTL_TRAP_STOP_BIT 19
#define KUNIT_ASSERT_NULL(test,ptr) KUNIT_ASSERT_NULL_MSG(test, ptr, NULL)
#define __NR_rt_tgsigqueueinfo 240
#define CONFIG_DMA_SHARED_BUFFER 1
#define ID_AA64ISAR0_EL1_SHA2_SHA256 UL(0b0001)
#define HCR_TPU (UL(1) << 24)
#define SME_VQ_MAX 16
#define ID_ISAR4_EL1_WithShifts_SHIFT 4
#define ID_AA64ZFR0_EL1_I8MM GENMASK(47, 44)
#define HDFGRTR_EL2_DBGWVRn_EL1_SHIFT 3
#define GFP_TRANSHUGE (GFP_TRANSHUGE_LIGHT | __GFP_DIRECT_RECLAIM)
#define MVFR2_EL1_FPMisc_FP_DIRECTED_ROUNDING UL(0b0010)
#define SECTION_BLOCKFLAGS_BITS ((1UL << (PFN_SECTION_SHIFT - pageblock_order)) * NR_PAGEBLOCK_BITS)
#define ASSERT_EXCLUSIVE_ACCESS_SCOPED(var) __ASSERT_EXCLUSIVE_SCOPED(var, KCSAN_ACCESS_WRITE | KCSAN_ACCESS_ASSERT, __COUNTER__)
#define early_initcall(fn) __define_initcall(fn, early)
#define SIOCGIFNAME 0x8910
#define static_branch_enable_cpuslocked(x) static_key_enable_cpuslocked(&(x)->key)
#define TRBSR_EL1_EC_MASK GENMASK(31, 26)
#define SYS_ID_AFR0_EL1_CRm 1
#define SYS_ID_AFR0_EL1_CRn 0
#define ARM64_WORKAROUND_1463225 70
#define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
#define topology_cluster_id(cpu) (cpu_topology[cpu].cluster_id)
#define ETH_P_AOE 0x88A2
#define HDFGWTR_EL2_PMCNTEN_WIDTH 1
#define ADVERTISE_100BASE4 0x0200
#define DMA_ATTR_NO_KERNEL_MAPPING (1UL << 4)
#define MDIO_AN_T1_LP_L_ACK LPA_LPACK
#define CONFIG_PPS 1
#define __NR_waitid 95
#define MVFR0_EL1_FPSP_NI UL(0b0000)
#define SB_NOSUID BIT(1)
#define __LINUX_CACHE_H 
#define SI_TIMER -2
#define __NR_mq_getsetattr 185
#define ioread64_rep ioread64_rep
#define ID_PFR1_EL1_MProgMod_SIGNED false
#define S_ISCHR(m) (((m) & S_IFMT) == S_IFCHR)
#define DACR32_EL2_D8_MASK GENMASK(17, 16)
#define set_fixmap_offset(idx,phys) __set_fixmap_offset(idx, phys, FIXMAP_PAGE_NORMAL)
#define arch_scale_thermal_pressure topology_get_thermal_pressure
#define SHIFT_USEC 16
#define FLOW_DIS_TUN_OPTS_MAX 255
#define FTR_VISIBLE true
#define ID_PFR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_PFR1_EL1_RES1 (UL(0))
#define BUG() do { __BUG_FLAGS(0); unreachable(); } while (0)
#define ARM64_WORKAROUND_2038923 75
#define PMSFCR_EL1_FL_SHIFT 2
#define TRACE_CONTEXT_BITS 4
#define LED_HW_PLUGGABLE BIT(19)
#define SEND_SIG_NOINFO ((struct kernel_siginfo *) 0)
#define ZAP_FLAG_DROP_MARKER ((__force zap_flags_t) BIT(0))
#define SIOGIFINDEX SIOCGIFINDEX
#define AF_AX25 3
#define O_NOCTTY 00000400
#define HFGITR_EL2_TLBIVALE1OS_MASK GENMASK(22, 22)
#define PR_SPEC_INDIRECT_BRANCH 1
#define IP_USER_FLOW IPV4_USER_FLOW
#define __WARN() __WARN_FLAGS(BUGFLAG_TAINT(TAINT_WARN))
#define MDIO_PCS_CTRL2_10GBW 0x0002
#define TIF_NOTIFY_SIGNAL 6
#define CONFIG_NET_FLOW_LIMIT 1
#define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
#define __this_cpu_or(pcp,val) ({ __this_cpu_preempt_check("or"); raw_cpu_or(pcp, val); })
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define PM_EVENT_PRETHAW PM_EVENT_QUIESCE
#define PR_SCHED_CORE_SCOPE_PROCESS_GROUP 2
#define CONFIG_BLK_PM 1
#define arch_atomic64_add_return_acquire arch_atomic64_add_return_acquire
#define hlist_first_rcu(head) (*((struct hlist_node __rcu **)(&(head)->first)))
#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
#define ID_MMFR4_EL1_SpecSEI_IMP UL(0b0001)
#define PCMCIA_DEV_ID_MATCH_MANF_ID 0x0001
#define ID_AA64SMFR0_EL1_I16I64_MASK GENMASK(55, 52)
#define CAP_NFSD_SET ((kernel_cap_t) { CAP_FS_MASK | BIT_ULL(CAP_SYS_RESOURCE) })
#define __ASM_GENERIC_USER_H 
#define HDFGWTR_EL2_TRCVICTLR_MASK GENMASK(48, 48)
#define high_16_bits(x) (((x) & 0xFFFF0000) >> 16)
#define readl_poll_timeout_atomic(addr,val,cond,delay_us,timeout_us) readx_poll_timeout_atomic(readl, addr, val, cond, delay_us, timeout_us)
#define MSG_SENDPAGE_NOPOLICY 0x10000
#define CONFIG_JBD2 1
#define MDIO_EEE_10GKR 0x0040
#define HFGxTR_EL2_SCTLR_EL1 GENMASK(29, 29)
#define ID_AA64MMFR3_EL1_AIE_SHIFT 24
#define dev_dbg_ratelimited(dev,fmt,...) do { if (0) dev_printk(KERN_DEBUG, dev, dev_fmt(fmt), ##__VA_ARGS__); } while (0)
#define arch_cmpxchg64_acquire arch_cmpxchg_acquire
#define arch_atomic_fetch_add arch_atomic_fetch_add
#define hlist_nulls_for_each_entry_from(tpos,pos,member) for (; (!is_a_nulls(pos)) && ({ tpos = hlist_nulls_entry(pos, typeof(*tpos), member); 1;}); pos = pos->next)
#define SYS_ID_AA64PFR0_EL1_Op0 3
#define SYS_ID_AA64PFR0_EL1_Op1 0
#define SYS_ID_AA64PFR0_EL1_Op2 0
#define SEGV_MTEAERR 8
#define __io_aw(v) 
#define ID_ISAR1_EL1_Interwork GENMASK(27, 24)
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
#define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
#define _LINUX_MODULE_H 
#define hlist_entry_safe(ptr,type,member) ({ typeof(ptr) ____ptr = (ptr); ____ptr ? hlist_entry(____ptr, type, member) : NULL; })
#define ID_ISAR4_EL1_Writeback_MASK GENMASK(11, 8)
#define PMBLIMITR_EL1_E_MASK GENMASK(0, 0)
#define SOL_SOCKET 1
#define TASK_ANY (TASK_STATE_MAX-1)
#define __hash_32 __hash_32_generic
#define mmiowb_spin_lock() do { } while (0)
#define readq_poll_timeout(addr,val,cond,delay_us,timeout_us) readx_poll_timeout(readq, addr, val, cond, delay_us, timeout_us)
#define ATTR_MTIME (1 << 5)
#define ID_AA64MMFR0_EL1_TGRAN64_2_IMP UL(0b0010)
#define PMBSR_EL1_EA_MASK GENMASK(18, 18)
#define NL_SET_ERR_MSG_ATTR_POL_FMT(extack,attr,pol,fmt,args...) do { struct netlink_ext_ack *__extack = (extack); if (!__extack) break; if (snprintf(__extack->_msg_buf, NETLINK_MAX_FMTMSG_LEN, "%s" fmt "%s", "", ##args, "") >= NETLINK_MAX_FMTMSG_LEN) net_warn_ratelimited("%s" fmt "%s", "truncated extack: ", ##args, "\n"); do_trace_netlink_extack(__extack->_msg_buf); __extack->_msg = __extack->_msg_buf; __extack->bad_attr = (attr); __extack->policy = (pol); } while (0)
#define MDIO_PMA_10T1L_CTRL_PMA_RST 0x8000
#define IPC_RMID 0
#define CONFIG_BINFMT_ELF 1
#define __rcu_dereference_raw(p,local) ({ typeof(p) local = READ_ONCE(p); ((typeof(*p) __force __kernel *)(local)); })
#define ID_AA64MMFR3_EL1_S1POE_NI UL(0b0000)
#define INVALID_HWID ULONG_MAX
#define POLL_BUSY_LOOP (__force __poll_t)0x8000
#define HCRX_EL2_PTTWI_MASK GENMASK(16, 16)
#define read_seqcount_retry(s,start) do_read_seqcount_retry(seqprop_const_ptr(s), start)
#define ETHTOOL_GGSO 0x00000023
#define ATTR_KILL_SUID (1 << 11)
#define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
#define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
#define CONFIG_RCU_EXP_CPU_STALL_TIMEOUT 0
#define MDIO_AN_10GBT_CTRL_ADV5G 0x0100
#define ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3 6
#define ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5 7
#define HDFGWTR_EL2_DBGCLAIM_MASK GENMASK(5, 5)
#define QC_INO_SOFT (1<<0)
#define DCACHE_SYMLINK_TYPE 0x00600000
#define __ASM_PGTABLE_HWDEF_H 
#define LORC_EL1_DS GENMASK(9, 2)
#define HWCAP2_FRINT (1 << 8)
#define SCTLR_ELx_EIS (BIT(22))
#define __NR_mount_setattr 442
#define ID_AA64DFR0_EL1_PMSVer_NI UL(0b0000)
#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
#define DQUOT_INIT_ALLOC max(V1_INIT_ALLOC, V2_INIT_ALLOC)
#define CSSELR_EL1_TnD_MASK GENMASK(4, 4)
#define mt_for_each(__tree,__entry,__index,__max) for (__entry = mt_find(__tree, &(__index), __max); __entry; __entry = mt_find_after(__tree, &(__index), __max))
#define SEGV_PKUERR 4
#define PMSIDR_EL1_COUNTSIZE_WIDTH 4
#define ID_AA64MMFR1_EL1_SpecSEI_SIGNED false
#define __DT_BINDINGS_LEDS_H 
#define PMSIDR_EL1_FT_SHIFT 1
#define IORESOURCE_STARTALIGN 0x00080000
#define PR_SET_SECCOMP 22
#define MSGRCV 12
#define PMSCR_EL2_RES0 (UL(0) | GENMASK_ULL(63, 8) | GENMASK_ULL(2, 2))
#define PMSCR_EL2_RES1 (UL(0))
#define LORC_EL1_EN GENMASK(0, 0)
#define HDFGRTR_EL2_TRBPTR_EL1_SHIFT 54
#define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
#define CONFIG_RTC_SYSTOHC 1
#define MVFR1_EL1_SIMDHP_SIMDHP_FLOAT UL(0b0010)
#define for_each_sgtable_dma_sg(sgt,sg,i) for_each_sg((sgt)->sgl, sg, (sgt)->nents, i)
#define SVE_NUM_ZREGS __SVE_NUM_ZREGS
#define skb_checksum_init(skb,proto,compute_pseudo) __skb_checksum_validate(skb, proto, false, false, 0, compute_pseudo)
#define MDIO_AN_T1_LP_M_B10L 0x4000
#define BLKPBSZGET _IO(0x12,123)
#define raw_try_cmpxchg_relaxed(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg_relaxed((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define module_param_hw_array(name,type,hwtype,nump,perm) param_check_ ##type(name, &(name)[0]); static const struct kparam_array __param_arr_ ##name = { .max = ARRAY_SIZE(name), .num = nump, .ops = &param_ops_ ##type, .elemsize = sizeof(name[0]), .elem = name }; __module_param_call(MODULE_PARAM_PREFIX, name, &param_array_ops, .arr = &__param_arr_ ##name, perm, -1, KERNEL_PARAM_FL_HWPARAM | (hwparam_ ##hwtype & 0)); __MODULE_PARM_TYPE(name, "array of " #type)
#define AUTONEG_ENABLE 0x01
#define HID_GROUP_ANY 0x0000
#define PMSCR_EL2_PCT_MASK GENMASK(7, 6)
#define RXH_L4_B_2_3 (1 << 7)
#define seqcount_acquire(l,s,t,i) lock_acquire_exclusive(l, s, t, NULL, i)
#define IS_DAX(inode) ((inode)->i_flags & S_DAX)
#define ZCR_ELx_LEN_SHIFT 0
#define __init_timer(_timer,_fn,_flags) do { static struct lock_class_key __key; init_timer_key((_timer), (_fn), (_flags), #_timer, &__key); } while (0)
#define skb_queue_walk_safe(queue,skb,tmp) for (skb = (queue)->next, tmp = skb->next; skb != (struct sk_buff *)(queue); skb = tmp, tmp = skb->next)
#define __NR_setdomainname 162
#define CONFIG_GENERIC_CPU_AUTOPROBE 1
#define for_each_irq_desc(irq,desc) for (irq = 0, desc = irq_to_desc(irq); irq < nr_irqs; irq++, desc = irq_to_desc(irq)) if (!desc) ; else
#define MDIO_PCS_1000BT1_STAT_FAULT 0x0080
#define ID_AA64MMFR2_EL1_CnP GENMASK(3, 0)
#define PSR_AA32_A_BIT 0x00000100
#define skb_rb_last(root) rb_to_skb(rb_last(root))
#define AF_XDP 44
#define INPUT_DEVICE_ID_REL_MAX 0x0f
#define SO_TXREHASH 74
#define FIOGETOWN 0x8903
#define DACR32_EL2_D13_WIDTH 2
#define HCR_TTLBIS (UL(1) << 54)
#define ELIBMAX 82
#define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
#define MDCR_EL2_TDE (UL(1) << 8)
#define unsafe_copy_from_user(d,s,l,e) unsafe_op_wrap(__copy_from_user(d,s,l),e)
#define MDSCR_EL1_ERR GENMASK(6, 6)
#define cmpxchg64_release(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_release(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg64_release(__ai_ptr, __VA_ARGS__); })
#define LED_FUNCTION_MUTE "mute"
#define PTRACE_O_MASK ( 0x000000ff | PTRACE_O_EXITKILL | PTRACE_O_SUSPEND_SECCOMP)
#define PR_RISCV_V_SET_CONTROL 69
#define _LINUX_KTIME_H 
#define CONFIG_CMA_SIZE_SEL_MBYTES 1
#define MPIDR_HWID_BITMASK UL(0xff00ffffff)
#define __LINUX_DCACHE_H 
#define SMIDR_EL1_IMPLEMENTER_WIDTH 8
#define HFGITR_EL2_ATS1E0W_WIDTH 1
#define BIN_ATTR_ADMIN_RW(_name,_size) struct bin_attribute bin_attr_ ##_name = __BIN_ATTR_ADMIN_RW(_name, _size)
#define ID_ISAR0_EL1_Swap_SIGNED false
#define CTR_EL0_IminLine_MASK GENMASK(3, 0)
#define param_check_bint param_check_int
#define HZ_TO_USEC_DEN 1
#define SOL_PPPOL2TP 273
#define HDFGWTR_EL2_OSDLR_EL1 GENMASK(11, 11)
#define ATTR_CTIME (1 << 6)
#define MMF_HAS_MDWE 28
#define ID_AA64PFR0_EL1_EL0_MASK GENMASK(3, 0)
#define IN6ADDR_LINKLOCAL_ALLNODES_INIT { { { 0xff,2,0,0,0,0,0,0,0,0,0,0,0,0,0,1 } } }
#define __flatten __attribute__((flatten))
#define __ASM_FCNTL_H 
#define VM_WARN(cond,format...) BUILD_BUG_ON_INVALID(cond)
#define ARM64_WORKAROUND_845719 67
#define SMPRIMAP_EL2_P0_WIDTH 4
#define ID_AA64ZFR0_EL1_BitPerm_NI UL(0b0000)
#define NT_PPC_HASHKEYR 0x112
#define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0)
#define HFGITR_EL2_TLBIVMALLE1IS_MASK GENMASK(28, 28)
#define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
#define UEVENT_NUM_ENVP 64
#define PTRACE_GET_SYSCALL_USER_DISPATCH_CONFIG 0x4211
#define PIRx_ELx_Perm2_WIDTH 4
#define static_branch_dec(x) static_key_slow_dec(&(x)->key)
#define CONFIG_NET_VENDOR_AQUANTIA 1
#define SZ_128K 0x00020000
#define __NR_timerfd_create 85
#define I_OVL_INUSE (1 << 14)
#define IS_POSIXACL(inode) 0
#define wait_event_timeout(wq_head,condition,timeout) ({ long __ret = timeout; might_sleep(); if (!___wait_cond_timeout(condition)) __ret = __wait_event_timeout(wq_head, condition, timeout); __ret; })
#define __LINUX_MEMORY_HOTPLUG_H 
#define SB_FORCE BIT(27)
#define ID_ISAR4_EL1_Unpriv_MASK GENMASK(3, 0)
#define ID_AA64PFR0_EL1_GIC_MASK GENMASK(27, 24)
#define ESR_ELx_EC_CP14_64 (0x0C)
#define FS_DQ_BWARNS (1<<9)
#define CALLER_ADDR3 ((unsigned long)ftrace_return_address(3))
#define FIXMAP_PAGE_CLEAR __pgprot(0)
#define ID_AA64PFR0_EL1_SEL2_NI UL(0b0000)
#define __chk_io_ptr(x) (void)0
#define ID_PFR0_EL1_AMU_AMUv1p1 UL(0b0010)
#define SCTLR_EL1_EIS_SHIFT 22
#define DNAME_INLINE_LEN 32
#define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
#define p4d_clear_bad(p4d) do { } while (0)
#define virt_to_page(x) ({ u64 __idx = (__tag_reset((u64)x) - PAGE_OFFSET) / PAGE_SIZE; u64 __addr = VMEMMAP_START + (__idx * sizeof(struct page)); (struct page *)__addr; })
#define flush_pud_tlb_range(vma,addr,end) BUILD_BUG()
#define _LINUX_UNISTD_H_ 
#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
#define PFA_SPREAD_SLAB 2
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
#define __ASM_HARDIRQ_H 
#define ID_AA64ZFR0_EL1_BitPerm_MASK GENMASK(19, 16)
#define ifr_settings ifr_ifru.ifru_settings
#define KUNIT_ASSERT_GE_MSG(test,left,right,fmt,...) KUNIT_BINARY_INT_ASSERTION(test, KUNIT_ASSERTION, left, >=, right, fmt, ##__VA_ARGS__)
#define MMF_VM_MERGE_ANY_MASK (1 << MMF_VM_MERGE_ANY)
#define ICH_LR_EOI (1ULL << 41)
#define SYS_ID_AA64ISAR0_EL1_Op2 0
#define SYS_MVFR2_EL1_CRm 3
#define INIT_WORK_ONSTACK(_work,_func) __INIT_WORK((_work), (_func), 1)
#define REG_ID_AA64ISAR2_EL1 S3_0_C0_C6_2
#define IOPRIO_CLASS_MASK (IOPRIO_NR_CLASSES - 1)
#define SCTLR_EL1_TWEDEn GENMASK(45, 45)
#define ID_AA64MMFR0_EL1_TGRAN16_2_NI UL(0b0001)
#define CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH 1
#define EILSEQ 84
#define _IOC_NONE 0U
#define HDFGWTR_EL2_TRFCR_EL1 GENMASK(49, 49)
#define NETLINK_MAX_FMTMSG_LEN 80
#define MIDR_CPU_VAR_REV(var,rev) (((var) << MIDR_VARIANT_SHIFT) | (rev))
#define ETH_P_PPP_MP 0x0008
#define BREAK_INSTR_SIZE AARCH64_INSN_SIZE
#define ELFDATA2LSB 1
#define RENAME_EXCHANGE (1 << 1)
#define NUM_RCU_LVL_INIT { NUM_RCU_LVL_0, NUM_RCU_LVL_1 }
#define NL_SET_ERR_MSG_ATTR_POL(extack,attr,pol,msg) do { static const char __msg[] = msg; struct netlink_ext_ack *__extack = (extack); do_trace_netlink_extack(__msg); if (__extack) { __extack->_msg = __msg; __extack->bad_attr = (attr); __extack->policy = (pol); } } while (0)
#define rcutree_dying_cpu NULL
#define list_next_or_null_rcu(head,ptr,type,member) ({ struct list_head *__head = (head); struct list_head *__ptr = (ptr); struct list_head *__next = READ_ONCE(__ptr->next); likely(__next != __head) ? list_entry_rcu(__next, type, member) : NULL; })
#define KASAN_VMALLOC_VM_ALLOC ((__force kasan_vmalloc_flags_t)0x02u)
#define MAX_NUM_QUEUE 4096
#define IN6ADDR_ANY_INIT { { { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } } }
#define JOBCTL_STOP_PENDING_BIT 17
#define CNTPOFF_EL2_PhysicalOffset_WIDTH 64
#define ID_AA64ISAR2_EL1_RPRFM_IMP UL(0b0001)
#define MII_EXPANSION 0x06
#define PACKET_MR_ALLMULTI 2
#define USB_DEVICE_ID_MATCH_DEV_HI 0x0008
#define NETIF_F_HW_VLAN_CTAG_RX __NETIF_F(HW_VLAN_CTAG_RX)
#define ID_AA64PFR1_EL1_MPAM_frac_MINOR_0 UL(0b0000)
#define SLUB_RED_ACTIVE 0xcc
#define arch_atomic64_fetch_and_acquire arch_atomic64_fetch_and_acquire
#define LED_FUNCTION_PLAYER1 "player-1"
#define SECCOMP_RET_TRACE 0x7ff00000U
#define ID_ISAR2_EL1_MemHint_NI UL(0b0000)
#define TCR2_EL1x_POE_SHIFT 3
#define RWF_APPEND ((__force __kernel_rwf_t)0x00000010)
#define __ASM_GENERIC_SEMBUF_H 
#define CTR_EL0_L1Ip_WIDTH 2
#define HCRX_EL2_EnSDERR_MASK GENMASK(20, 20)
#define nodes_empty(src) __nodes_empty(&(src), MAX_NUMNODES)
#define SHMSEG SHMMNI
#define get_task_comm(buf,tsk) ({ BUILD_BUG_ON(sizeof(buf) != TASK_COMM_LEN); __get_task_comm(buf, sizeof(buf), tsk); })
#define PM_EVENT_QUIESCE 0x0008
#define I_DIRTY (I_DIRTY_INODE | I_DIRTY_PAGES)
#define __pcpu_size_call(stem,variable,...) do { __verify_pcpu_ptr(&(variable)); switch(sizeof(variable)) { case 1: stem ##1(variable, __VA_ARGS__);break; case 2: stem ##2(variable, __VA_ARGS__);break; case 4: stem ##4(variable, __VA_ARGS__);break; case 8: stem ##8(variable, __VA_ARGS__);break; default: __bad_size_call_parameter();break; } } while (0)
#define ID_AA64ISAR0_EL1_SHA3_SHIFT 32
#define ID_AA64ISAR0_EL1_TS_SHIFT 52
#define ID_ISAR6_EL1_SB_MASK GENMASK(15, 12)
#define ULONG_CMP_GE(a,b) (ULONG_MAX / 2 >= (a) - (b))
#define __private 
#define DO_ONCE(func,...) ({ bool ___ret = false; static bool __section(".data.once") ___done = false; static DEFINE_STATIC_KEY_TRUE(___once_key); if (static_branch_unlikely(&___once_key)) { unsigned long ___flags; ___ret = __do_once_start(&___done, &___flags); if (unlikely(___ret)) { func(__VA_ARGS__); __do_once_done(&___done, &___once_key, &___flags, THIS_MODULE); } } ___ret; })
#define TBSVC_MATCH_PROTOCOL_VERSION 0x0004
#define ID_PFR0_EL1_State2_WIDTH 4
#define ID_MMFR2_EL1_L1HvdBG_SHIFT 4
#define MASTER_SLAVE_CFG_UNKNOWN 1
#define TRBSR_EL1_DAT_SHIFT 23
#define cmpxchg128_relaxed(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg128_relaxed(__ai_ptr, __VA_ARGS__); })
#define ADJ_ESTERROR 0x0008
#define DEFINE_RES_IRQ_NAMED(_irq,_name) DEFINE_RES_NAMED((_irq), 1, (_name), IORESOURCE_IRQ)
#define CONTEXTIDR_ELx_UNKN (UL(0))
#define SLAB_NOLEAKTRACE ((slab_flags_t __force)0x00800000U)
#define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT
#define SO_PEERCRED 17
#define MII_PHYADDR 0x19
#define check_shl_overflow(a,s,d) __must_check_overflow(({ typeof(a) _a = a; typeof(s) _s = s; typeof(d) _d = d; u64 _a_full = _a; unsigned int _to_shift = is_non_negative(_s) && _s < 8 * sizeof(*d) ? _s : 0; *_d = (_a_full << _to_shift); (_to_shift != _s || is_negative(*_d) || is_negative(_a) || (*_d >> _to_shift) != _a); }))
#define __nocfi 
#define ID_DFR0_EL1_CopSDbg_WIDTH 4
#define MEI_CL_VERSION_ANY 0xff
#define FMODE_NEED_UNMOUNT ((__force fmode_t)0x10000000)
#define LRU_GEN_MASK ((BIT(LRU_GEN_WIDTH) - 1) << LRU_GEN_PGOFF)
#define __O_SYNC 04000000
#define SMIDR_EL1_REVISION GENMASK(23, 16)
#define local64_sub(i,l) local_sub((i),(&(l)->a))
#define SVE_PT_SVE_ZREG_OFFSET(vq,n) (SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
#define PTRACE_EVENT_STOP 128
#define COMPAT_USE_64BIT_TIME 0
#define CSSELR_EL1_Level GENMASK(3, 1)
#define current_suid() (current_cred_xxx(suid))
#define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN)
#define MII_BMSR 0x01
#define _ASM_GENERIC_BITOPS_LE_H_ 
#define __INITDATA_OR_MODULE __INITDATA
#define QCOM_CPU_PART_KRYO 0x200
#define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
#define CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC 1
#define MAIR_ATTRIDX(attr,idx) ((attr) << ((idx) * 8))
#define CONFIG_PRINTK_TIME 1
#define plist_last_entry(head,type,member) container_of(plist_last(head), type, member)
#define CONFIG_MAC80211_STA_HASH_MAX_SIZE 0
#define DT_RELACOUNT 0x6ffffff9
#define ID_AA64PFR1_EL1_CSV2_frac_CSV2_1p1 UL(0b0001)
#define ID_AA64PFR1_EL1_CSV2_frac_CSV2_1p2 UL(0b0010)
#define NLM_F_CREATE 0x400
#define _LINUX_MM_TYPES_H 
#define VALID_OPEN_FLAGS (O_RDONLY | O_WRONLY | O_RDWR | O_CREAT | O_EXCL | O_NOCTTY | O_TRUNC | O_APPEND | O_NDELAY | O_NONBLOCK | __O_SYNC | O_DSYNC | FASYNC | O_DIRECT | O_LARGEFILE | O_DIRECTORY | O_NOFOLLOW | O_NOATIME | O_CLOEXEC | O_PATH | __O_TMPFILE)
#define HASH_LEN_DECLARE u32 hash; u32 len
#define BMCR_SPEED10 0x0000
#define PR_MCE_KILL_DEFAULT 2
#define __LINUX_OVERFLOW_H 
#define TRBLIMITR_EL1_nVM_WIDTH 1
#define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
#define __SYSCALL_DEFINEx(x,name,...) asmlinkage long __arm64_sys ##name(const struct pt_regs *regs); ALLOW_ERROR_INJECTION(__arm64_sys ##name, ERRNO); static long __se_sys ##name(__MAP(x,__SC_LONG,__VA_ARGS__)); static inline long __do_sys ##name(__MAP(x,__SC_DECL,__VA_ARGS__)); asmlinkage long __arm64_sys ##name(const struct pt_regs *regs) { return __se_sys ##name(SC_ARM64_REGS_TO_ARGS(x,__VA_ARGS__)); } static long __se_sys ##name(__MAP(x,__SC_LONG,__VA_ARGS__)) { long ret = __do_sys ##name(__MAP(x,__SC_CAST,__VA_ARGS__)); __MAP(x,__SC_TEST,__VA_ARGS__); __PROTECT(x, ret,__MAP(x,__SC_ARGS,__VA_ARGS__)); return ret; } static inline long __do_sys ##name(__MAP(x,__SC_DECL,__VA_ARGS__))
#define __ASM_HWCAP_H 
#define ip_fast_csum ip_fast_csum
#define HUGETLB_FLAG_ENCODE_512MB (29U << HUGETLB_FLAG_ENCODE_SHIFT)
#define nr_cpumask_bits nr_cpu_ids
#define __fid_stringify(dummy,str) #str,
#define PR_CAPBSET_READ 23
#define asm_inline asm __inline
#define ID_AA64PFR1_EL1_SME_IMP UL(0b0001)
#define CAP_FSETID 4
#define MDIO_PCS_1000BT1_CTRL_RESET 0x8000
#define kmalloc_track_caller(size,flags) __kmalloc_node_track_caller(size, flags, NUMA_NO_NODE, _RET_IP_)
#define ID_AA64AFR0_EL1_IMPDEF3_SHIFT 12
#define unsafe_copy_to_user(d,s,l,e) unsafe_op_wrap(__copy_to_user(d,s,l),e)
#define list_for_each_entry_from_reverse(pos,head,member) for (; !list_entry_is_head(pos, head, member); pos = list_prev_entry(pos, member))
#define ID_PFR1_EL1_MProgMod_WIDTH 4
#define ID_DFR0_EL1_MMapTrc_IMP UL(0b0001)
#define BUILD_BUG_ON_MSG(cond,msg) compiletime_assert(!(cond), msg)
#define PMSIDR_EL1_COUNTSIZE_12_BIT_SAT UL(0b0010)
#define WAKE_ARP (1 << 4)
#define INPUT_DEVICE_ID_MATCH_SNDBIT 0x0400
#define FS_DQ_BHARD (1<<3)
#define MDSCR_EL1_MDE_MASK GENMASK(15, 15)
#define wait_var_event_killable(var,condition) ({ int __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_var_event_killable(var, condition); __ret; })
#define SKBTX_ANY_TSTAMP (SKBTX_HW_TSTAMP | SKBTX_HW_TSTAMP_USE_CYCLES | SKBTX_ANY_SW_TSTAMP)
#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52
#define LINK_MAX 127
#define HFGITR_EL2_COSPRCTX_WIDTH 1
#define NSIGTRAP 6
#define SYS_SMCR_EL2_CRm 2
#define SYS_SMCR_EL2_CRn 1
#define FIXMAP_PAGE_IO __pgprot(PROT_DEVICE_nGnRE)
#define ID_ISAR6_EL1_I8MM_SHIFT 24
#define ZT_MAGIC 0x5a544e01
#define EXPORT_SYMBOL_NS(sym,ns) __EXPORT_SYMBOL(sym, "", __stringify(ns))
#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
#define BUFMAX 2048
#define XATTR_SIZE_MAX 65536
#define PMBIDR_EL1_P_WIDTH 1
#define RATELIMIT_STATE_INIT(name,interval_init,burst_init) RATELIMIT_STATE_INIT_FLAGS(name, interval_init, burst_init, 0)
#define ID_AA64PFR1_EL1_THE_IMP UL(0b0001)
#define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT
#define time_after_eq64(a,b) (typecheck(__u64, a) && typecheck(__u64, b) && ((__s64)((a) - (b)) >= 0))
#define wfet(val) asm volatile("msr s0_3_c1_c0_0, %0" : : "r" (val) : "memory")
#define BLKGETSIZE _IO(0x12,96)
#define for_each_zone(zone) for (zone = (first_online_pgdat())->node_zones; zone; zone = next_zone(zone))
#define ID_MMFR2_EL1_L1HvdFG_WIDTH 4
#define CHRDEV_MAJOR_DYN_EXT_END 384
#define _LINUX_VMALLOC_H 
#define ifc_req ifc_ifcu.ifcu_req
#define HDFGRTR_EL2_PMCEIDn_EL0_MASK GENMASK(58, 58)
#define SCTLR_EL1_TCF_SYNC UL(0b01)
#define ID_AA64ISAR1_EL1_DPB_NI UL(0b0000)
#define ___GFP_HIGH 0x20u
#define ULONG_CMP_LT(a,b) (ULONG_MAX / 2 < (a) - (b))
#define irqs_disabled() ({ unsigned long _flags; raw_local_save_flags(_flags); raw_irqs_disabled_flags(_flags); })
#define PTE_AF (_AT(pteval_t, 1) << 10)
#define PMSIDR_EL1_PBT_MASK GENMASK(24, 24)
#define ID_AA64MMFR1_EL1_PAN_IMP UL(0b0001)
#define __ARCH_SI_ATTRIBUTES 
#define AT_VECTOR_SIZE (2*(AT_VECTOR_SIZE_ARCH + AT_VECTOR_SIZE_BASE + 1))
#define __initdata_or_module __initdata
#define SHMDT 22
#define MDIO_PHYXS_LNSTAT 24
#define SCHED_DEADLINE 6
#define MIGRATETYPE_MASK ((1UL << PB_migratetype_bits) - 1)
#define PNP_MAX_DEVICES 8
#define inw_p inw_p
#define ___GFP_NOMEMALLOC 0x80000u
#define __NR_quotactl_fd 443
#define nodes_full(nodemask) __nodes_full(&(nodemask), MAX_NUMNODES)
#define first_memory_node 0
#define CTR_EL0_TminLine_WIDTH 6
#define lock_set_cmp_fn(lock,...) lockdep_set_lock_cmp_fn(&(lock)->dep_map, __VA_ARGS__)
#define ID_AA64PFR1_EL1_RAS_frac_SIGNED false
#define FS_XFLAG_PREALLOC 0x00000002
#define IOPRIO_LEVEL_NR_BITS 3
#define IORESOURCE_DMA_16BIT (2<<0)
#define TAINT_MACHINE_CHECK 4
#define A32_RT_OFFSET 12
#define LED_FUNCTION_HEARTBEAT "heartbeat"
#define MDSCR_EL1_TDA GENMASK(21, 21)
#define POLLREMOVE 0x1000
#define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T
#define IORESOURCE_MEM_EXPANSIONROM (1<<6)
#define ID_AA64MMFR3_EL1_ADERR_MASK GENMASK(59, 56)
#define __GFP_RECLAIM ((__force gfp_t)(___GFP_DIRECT_RECLAIM|___GFP_KSWAPD_RECLAIM))
#define HDFGRTR_EL2_PMUSERENR_EL0_MASK GENMASK(57, 57)
#define ID_ISAR2_EL1_MultS_SHIFT 16
#define HCRX_EL2_MCE2_MASK GENMASK(10, 10)
#define IRQF_NOBALANCING 0x00000800
#define DEFINE_RCU_SYNC(name) struct rcu_sync name = __RCU_SYNC_INITIALIZER(name)
#define ETHTOOL_GEEPROM 0x0000000b
#define ID_ISAR5_EL1_CRC32_SHIFT 16
#define ID_PFR1_EL1_Sec_frac_WALK_DISABLE UL(0b0001)
#define MVFR0_EL1_FPDP GENMASK(11, 8)
#define MII_MMD_CTRL_NOINCR 0x4000
#define CONFIG_ARCH_INLINE_READ_LOCK_BH 1
#define KUNIT_EXPECT_PTR_NE(test,left,right) KUNIT_EXPECT_PTR_NE_MSG(test, left, right, NULL)
#define hlist_for_each_entry_continue(pos,member) for (pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member); pos; pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
#define SCTLR_EL1_TIDCP_SHIFT 63
#define ID_AA64MMFR3_EL1_S2PIE_SHIFT 12
#define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
#define ETH_P_CUST 0x6006
#define __NR_get_mempolicy 236
#define __BF_CHECK_POW2(n) BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0)
#define MDCR_EL2_HLP (UL(1) << 26)
#define DQF_SETINFO_MASK DQF_ROOT_SQUASH
#define HFGxTR_EL2_MAIR_EL1_MASK GENMASK(24, 24)
#define HDFGWTR_EL2_TRCSEQSTR_SHIFT 45
#define __cpu_to_le16(x) ((__force __le16)(__u16)(x))
#define MDIO_PCS_1000BT1_CTRL_LOW_POWER 0x0800
#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
#define SCTLR_EL1_nTLSMD_WIDTH 1
#define MVFR1_EL1_SIMDInt_WIDTH 4
#define SCTLR_EL1_MSCEn GENMASK(33, 33)
#define IORESOURCE_IRQ_SHAREABLE (1<<4)
#define MDIO_PMA_LASI_RXCTRL 0x9000
#define DMA_ATTR_SKIP_CPU_SYNC (1UL << 5)
#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT 6
#define MDSCR_EL1_TFO GENMASK(31, 31)
#define RATELIMIT_STATE_INIT_DISABLED RATELIMIT_STATE_INIT(ratelimit_state, 0, DEFAULT_RATELIMIT_BURST)
#define MODULE_PARAM_PREFIX KBUILD_MODNAME "."
#define EBADE 52
#define EBADF 9
#define ARM64_WORKAROUND_CAVIUM_30115 88
#define HFGxTR_EL2_ERXCTLR_EL1_SHIFT 43
#define cpu_dying_mask ((const struct cpumask *)&__cpu_dying_mask)
#define EBADR 53
#define _LINUX_VMSTAT_H 
#define FMODE_RANDOM ((__force fmode_t)0x1000)
#define ID_MMFR4_EL1_SpecSEI_SHIFT 0
#define SEGV_MTESERR 9
#define HFGxTR_EL2_APIBKey GENMASK(8, 8)
#define FIELD_FIT(_mask,_val) ({ __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_FIT: "); !((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); })
#define SPINLOCK_OWNER_INIT ((void *)-1L)
#define CONFIG_RTC_DRV_PL031 1
#define ID_MMFR2_EL1_L1HvdFG_IMP UL(0b0001)
#define TASK_NORMAL (TASK_INTERRUPTIBLE | TASK_UNINTERRUPTIBLE)
#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
#define LPA_1000FULL 0x0800
#define SO_PEERNAME 28
#define FW_WARN "[Firmware Warn]: "
#define TRBSR_EL1_WRAP_MASK GENMASK(20, 20)
#define _LINUX_HRTIMER_H 
#define pmd_offset_lockless(pudp,pud,address) pmd_offset(&(pud), address)
#define _LINUX_SYNC_CORE_H 
#define NETIF_F_ALL_FOR_ALL (NETIF_F_NOCACHE_COPY | NETIF_F_FSO)
#define ID_AA64ZFR0_EL1_I8MM_SIGNED false
#define _BITUL(x) (_UL(1) << (x))
#define ECANCELED 125
#define cpu_feature(x) KERNEL_HWCAP_ ## x
#define ID_AA64PFR1_EL1_RNDR_trap_WIDTH 4
#define SUPPORTED_1000baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Half)
#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
#define FS_EA_INODE_FL 0x00200000
#define HDFGRTR_EL2_DBGCLAIM GENMASK(5, 5)
#define HDFGWTR_EL2_TRCOSLAR GENMASK(42, 42)
#define MII_BMCR 0x00
#define SIGFPE 8
#define SIOCBONDCHANGEACTIVE 0x8995
#define ID_AA64MMFR2_EL1_TTL_WIDTH 4
#define fops_put(fops) do { if (fops) module_put((fops)->owner); } while(0)
#define ELF_NGREG (sizeof(struct user_pt_regs) / sizeof(elf_greg_t))
#define IPV6_FL_S_USER 3
#define __DEP_MAP_MUTEX_INITIALIZER(lockname) , .dep_map = { .name = #lockname, .wait_type_inner = LD_WAIT_SLEEP, }
#define raw_cpu_cmpxchg_4(pcp,oval,nval) raw_cpu_generic_cmpxchg(pcp, oval, nval)
#define MNT_LOCK_NODEV 0x200000
#define MVFR0_EL1_FPSP_WIDTH 4
#define ID_AA64MMFR3_EL1_SDERR GENMASK(55, 52)
#define __rcu BTF_TYPE_TAG(rcu)
#define HFGxTR_EL2_ERRSELR_EL1_WIDTH 1
#define HPAGE_PUD_SHIFT ({ BUILD_BUG(); 0; })
#define MT_S2_FWB_NORMAL 6
#define PR_SET_MEMORY_MERGE 67
#define CONFIG_CRYPTO_ALGAPI 1
#define IOPRIO_H 
#define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed")
#define ID_AA64ISAR0_EL1_AES_MASK GENMASK(7, 4)
#define _LINUX_FS_TYPES_H 
#define SKB_LINEAR_ASSERT(skb) BUG_ON(skb_is_nonlinear(skb))
#define PCMCIA_DEV_ID_MATCH_CARD_ID 0x0002
#define lockdep_is_held_type(lock,r) lock_is_held_type(&(lock)->dep_map, (r))
#define HFGxTR_EL2_APDAKey GENMASK(4, 4)
#define IORESOURCE_AUTO 0x40000000
#define ID_AA64ZFR0_EL1_F64MM GENMASK(59, 56)
#define RX_CLS_FLOW_WAKE 0xfffffffffffffffeULL
#define NLMSG_DATA(nlh) ((void *)(((char *)nlh) + NLMSG_HDRLEN))
#define CTL1000_ENABLE_MASTER 0x1000
#define ID_MMFR4_EL1_XNX_NI UL(0b0000)
#define __be32_to_cpu(x) __swab32((__force __u32)(__be32)(x))
#define LORID_EL1_LD_SHIFT 16
#define __NR_setxattr 5
#define ARM64_KVM_HVHE 50
#define SYS_PMSLATFR_EL1_CRm 9
#define ID_ISAR5_EL1_UNKN (UL(0))
#define QC_TIMER_MASK (QC_SPC_TIMER | QC_INO_TIMER | QC_RT_SPC_TIMER)
#define xa_lock_bh_nested(xa,subclass) spin_lock_bh_nested(&(xa)->xa_lock, subclass)
#define NSIGEMT 1
#define _LINUX_CONTEXT_TRACKING_STATE_H 
#define _DPRINTK_FLAGS_INCL_LINENO (1<<3)
#define printk_deferred_exit __printk_safe_exit
#define wait_event_freezable_exclusive(wq,condition) ({ int __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_event_freezable_exclusive(wq, condition); __ret; })
#define DT_VERNEEDNUM 0x6fffffff
#define NETLINK_URELEASE 0x0001
#define CONFIG_CPU_RMAP 1
#define __ref __section(".ref.text") noinline
#define PIRx_ELx_Perm14_WIDTH 4
#define CONFIG_OF_ADDRESS 1
#define ID_ISAR5_EL1_SEVL_WIDTH 4
#define __realloc_size(x,...) __alloc_size__(x, ## __VA_ARGS__)
#define __cpu_to_le64(x) ((__force __le64)(__u64)(x))
#define CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 1
#define MDIO_USXGMII_10GHALF 0x0600
#define _LINUX_IRQRETURN_H 
#define SCTLR_ELx_ATA (BIT(43))
#define MAY_APPEND 0x00000008
#define ID_AA64MMFR2_EL1_E0PD GENMASK(63, 60)
#define ID_AA64PFR1_EL1_MTEX_MTE4 UL(0b0001)
#define MDIO_AN_C73_0_S_MASK GENMASK(4, 0)
#define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
#define ID_AFR0_EL1_UNKN (UL(0))
#define init_completion_map(x,m) init_completion(x)
#define __INIT_DELAYED_WORK_ONSTACK(_work,_func,_tflags) do { INIT_WORK_ONSTACK(&(_work)->work, (_func)); __init_timer_on_stack(&(_work)->timer, delayed_work_timer_fn, (_tflags) | TIMER_IRQSAFE); } while (0)
#define ID_PFR1_EL1_GenTimer_IMP UL(0b0001)
#define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55
#define MSG_PEEK 2
#define BUGFLAG_TAINT(taint) ((taint) << 8)
#define HFGxTR_EL2_APDBKey_MASK GENMASK(5, 5)
#define pr_err(fmt,...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
#define ESR_ELx_FSC_SEA_TTW0 (0x14)
#define ESR_ELx_FSC_SEA_TTW1 (0x15)
#define ESR_ELx_FSC_SEA_TTW2 (0x16)
#define ESR_ELx_FSC_SEA_TTW3 (0x17)
#define CONFIG_SND_VERBOSE_PRINTK 1
#define FS_NOTAIL_FL 0x00008000
#define arch_has_hw_pte_young cpu_has_hw_af
#define TIF_SYSCALL_AUDIT 9
#define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
#define fl4_sport uli.ports.sport
#define CONFIG_ZYNQMP_FIRMWARE 1
#define __wait_event_idle_exclusive_timeout(wq_head,condition,timeout) ___wait_event(wq_head, ___wait_cond_timeout(condition), TASK_IDLE, 1, timeout, __ret = schedule_timeout(__ret))
#define __NR_request_key 218
#define static_branch_disable(x) static_key_disable(&(x)->key)
#define _ASM_GENERIC_LOCAL64_H 
#define O_CLOEXEC 02000000
#define CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 1
#define HARDIRQ_MASK (__IRQ_MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT)
#define CONFIG_RD_LZ4 1
#define arch_atomic64_fetch_sub arch_atomic64_fetch_sub
#define ILL_ILLOPC 1
#define SO_TXTIME 61
#define ARCH_TIMER_TYPE_CP15 BIT(0)
#define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
#define MIDR_ARCHITECTURE(midr) (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
#define ILL_ILLOPN 2
#define ID_DFR0_EL1_CopDbg_Armv6 UL(0b0010)
#define ID_DFR0_EL1_CopDbg_Armv7 UL(0b0100)
#define ID_DFR0_EL1_CopDbg_Armv8 UL(0b0110)
#define CONFIG_RD_LZO 1
#define FS_CASEFOLD_FL 0x40000000
#define NET_IP_ALIGN 0
#define radix_tree_for_each_tagged(slot,root,iter,start,tag) for (slot = radix_tree_iter_init(iter, start) ; slot || (slot = radix_tree_next_chunk(root, iter, RADIX_TREE_ITER_TAGGED | tag)) ; slot = radix_tree_next_slot(slot, iter, RADIX_TREE_ITER_TAGGED | tag))
#define KUNIT_EXPECT_MEMEQ(test,left,right,size) KUNIT_EXPECT_MEMEQ_MSG(test, left, right, size, NULL)
#define arch_xchg(...) __xchg_wrapper( _mb, __VA_ARGS__)
#define APR_NAME_SIZE 32
#define ID_AA64PFR0_EL1_EL1_WIDTH 4
#define AF_ISDN 34
#define xas_lock_bh(xas) xa_lock_bh((xas)->xa)
#define NLM_F_APPEND 0x800
#define CAP_LINUX_IMMUTABLE 9
#define ID_AA64DFR0_EL1_PMUVer_IMP_DEF UL(0b1111)
#define __NR_bind 200
#define ID_AA64ISAR2_EL1_CSSC_SIGNED false
#define CONFIG_XZ_DEC_X86 1
#define CONFIG_FS_MBCACHE 1
#define HDFGWTR_EL2_TRBLIMITR_EL1_WIDTH 1
#define LRU_BASE 0
#define SYS_ID_AA64DFR0_EL1_Op0 3
#define SYS_ID_AA64DFR0_EL1_Op1 0
#define SYS_ID_AA64DFR0_EL1_Op2 0
#define SI_FROMUSER(siptr) ((siptr)->si_code <= 0)
#define ID_AA64PFR1_EL1_RNDR_trap GENMASK(31, 28)
#define ICH_VTR_A3V_SHIFT 21
#define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
#define CONFIG_HAVE_GCC_PLUGINS 1
#define xas_for_each(xas,entry,max) for (entry = xas_find(xas, max); entry; entry = xas_next_entry(xas, max))
#define ID_MMFR5_EL1_ETS GENMASK(3, 0)
#define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4))
#define __KERNEL__ 1
#define ID_AA64SMFR0_EL1_F64F64_WIDTH 1
#define KERNEL_HWCAP_SME_I8I32 __khwcap2_feature(SME_I8I32)
#define STT_FUNC 2
#define SYS_ID_AA64ISAR2_EL1_CRn 0
#define ADVERTISE_PAUSE_ASYM 0x0800
#define ID_AA64PFR1_EL1_GCS_WIDTH 4
#define PAGE_READONLY_EXEC __pgprot(_PAGE_READONLY_EXEC)
#define CONFIG_PCI_HOST_GENERIC 1
#define NETIF_F_TSO __NETIF_F(TSO)
#define __ASM_GENERIC_HW_IRQ_H 
#define SIOCSARP 0x8955
#define rcu_replace_pointer(rcu_ptr,ptr,c) ({ typeof(ptr) __tmp = rcu_dereference_protected((rcu_ptr), (c)); rcu_assign_pointer((rcu_ptr), (ptr)); __tmp; })
#define IF_IFACE_SYNC_SERIAL 0x1005
#define PCI_EPF_NAME_SIZE 20
#define CTR_EL0_CWG_MASK GENMASK(27, 24)
#define SYS_ACCEPT 5
#define IORESOURCE_IO_FIXED (1<<1)
#define SYM_FUNC_START_WEAK(name) SYM_START(name, SYM_L_WEAK, SYM_A_ALIGN) bti c ;
#define __local_lock_irqsave(lock,flags) do { local_irq_save(flags); local_lock_acquire(this_cpu_ptr(lock)); } while (0)
#define TRBMAR_EL1_Attr_WIDTH 8
#define ID_AA64MMFR3_EL1_SDERR_SHIFT 52
#define ID_MMFR3_EL1_CohWalk_IMP UL(0b0001)
#define const_test_bit_acquire generic_test_bit_acquire
#define PTE_NG (_AT(pteval_t, 1) << 11)
#define CCSIDR_EL1_Associativity_WIDTH 10
#define CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS 12
#define CONFIG_MMU_GATHER_TABLE_FREE 1
#define ID_AA64ISAR1_EL1_FRINTTS_IMP UL(0b0001)
#define PERCPU_DYNAMIC_RESERVE (28 << PERCPU_DYNAMIC_SIZE_SHIFT)
#define ID_AA64DFR0_EL1_MTPMU_MASK GENMASK(51, 48)
#define ID_AA64MMFR1_EL1_CMOW_IMP UL(0b0001)
#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
#define __NR_shmdt 197
#define __alloc_size(x,...) __alloc_size__(x, ## __VA_ARGS__) __malloc
#define local_sub_return(i,l) atomic_long_sub_return((i), (&(l)->a))
#define CLONE_THREAD 0x00010000
#define current_fsgid() (current_cred_xxx(fsgid))
#define HDFGWTR_EL2_TRCPRGCTLR_MASK GENMASK(44, 44)
#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
#define PR_MCE_KILL_LATE 0
#define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
#define SKB_ALLOC_RX 0x02
#define CPACR_ELx_ZEN_SHIFT 16
#define HFGxTR_EL2_VBAR_EL1 GENMASK(38, 38)
#define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7)
#define FPE_FLTRES 6
#define EINPROGRESS 115
#define CONFIG_RUST 1
#define PT_PHDR 6
#define FAR_EL1_RES0 (UL(0))
#define FAR_EL1_RES1 (UL(0))
#define write_lock_irqsave(lock,flags) do { typecheck(unsigned long, flags); flags = _raw_write_lock_irqsave(lock); } while (0)
#define DEVICE_INT_ATTR(_name,_mode,_var) struct dev_ext_attribute dev_attr_ ##_name = { __ATTR(_name, _mode, device_show_int, device_store_int), &(_var) }
#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
#define DEFINE_PER_CPU_SHARED_ALIGNED(type,name) DEFINE_PER_CPU_SECTION(type, name, PER_CPU_SHARED_ALIGNED_SECTION) ____cacheline_aligned_in_smp
#define ID_AA64MMFR3_EL1_SDERR_DEV_SYNC UL(0b0001)
#define raw_cpu_cmpxchg(pcp,oval,nval) __pcpu_size_call_return2(raw_cpu_cmpxchg_, pcp, oval, nval)
#define EI_OSABI 7
#define __dma_rmb() dmb(oshld)
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 
#define CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE 1
#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
#define PARITY_DEFAULT 0
#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52
#define pm_generic_poweroff NULL
#define __list_check_srcu(cond) ({ })
#define KPROBE_FLAG_OPTIMIZED 4
#define topology_drawer_cpumask(cpu) cpumask_of(cpu)
#define HPAGE_PMD_ORDER (HPAGE_PMD_SHIFT-PAGE_SHIFT)
#define EM_ARCV2 195
#define CONFIG_HAVE_ASM_MODVERSIONS 1
#define PTRACE_SETSIGMASK 0x420b
#define HDFGWTR_EL2_PMEVTYPERn_EL0_MASK GENMASK(13, 13)
#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
#define CLIDR_EL1_Ctype3_WIDTH 3
#define HFGxTR_EL2_TPIDR_EL0_MASK GENMASK(35, 35)
#define ARM64_HAS_ECV 19
#define __rmb() dsb(ld)
#define ID_ISAR2_EL1_PSR_AR_MASK GENMASK(27, 24)
#define __OPTIMIZE__ 1
#define COMPAT_RLIM_INFINITY 0xffffffff
#define BIT_ULL_MASK(nr) (ULL(1) << ((nr) % BITS_PER_LONG_LONG))
#define __ADDR_BND_PKEY_PAD (__alignof__(void *) < sizeof(short) ? sizeof(short) : __alignof__(void *))
#define TTBRx_EL1_BADDR_WIDTH 47
#define __NR_setsid 157
#define ETH_P_AX25 0x0002
#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400
#define ETH_P_EDSA 0xDADA
#define lockdep_on() do { current->lockdep_recursion -= LOCKDEP_OFF; } while (0)
#define OSQ_LOCK_UNLOCKED { ATOMIC_INIT(OSQ_UNLOCKED_VAL) }
#define SEQCOUNT_LOCKNAME_ZERO(seq_name,assoc_lock) { .seqcount = SEQCNT_ZERO(seq_name.seqcount), __SEQ_LOCK(.lock = (assoc_lock)) }
#define SCTLR_EL1_BT1_SHIFT 36
#define __io_br(v) 
#define _LINUX_PRCTL_H 
#define CONFIG_PARTITION_PERCPU 1
#define CAP_SYS_NICE 23
#define ARM64_WORKAROUND_TSB_FLUSH_FAILURE 84
#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
#define TCR2_EL2_AMEC0 GENMASK(12, 12)
#define TCR2_EL2_AMEC1 GENMASK(13, 13)
#define HDFGWTR_EL2_TRCCLAIM_WIDTH 1
#define SPMI_MODULE_PREFIX "spmi:"
#define PTRACE_O_SUSPEND_SECCOMP (1 << 21)
#define __NR_fstatfs __NR3264_fstatfs
#define DEFINE_STATIC_KEY_MAYBE(cfg,name) __PASTE(_DEFINE_STATIC_KEY_, IS_ENABLED(cfg))(name)
#define ptrauth_user_pac_mask() GENMASK_ULL(54, vabits_actual)
#define MVFR0_EL1_SIMDReg_WIDTH 4
#define wait_event_interruptible_exclusive_locked(wq,condition) ((condition) ? 0 : __wait_event_interruptible_locked(wq, condition, 1, do_wait_intr))
#define member_address_is_nonnull(ptr,member) ((uintptr_t)(ptr) + offsetof(typeof(*(ptr)), member) != 0)
#define CPACR_EL1_SMEN_EL1EN (BIT(24))
#define PIE_RWX 0xe
#define NETLINK_NETFILTER 12
#define __hlist_for_each_rcu(pos,head) for (pos = rcu_dereference(hlist_first_rcu(head)); pos; pos = rcu_dereference(hlist_next_rcu(pos)))
#define TAINT_CPU_OUT_OF_SPEC 2
#define CONFIG_MEMBARRIER 1
#define MDSCR_EL1_TTA GENMASK(33, 33)
#define SO_WIFI_STATUS 41
#define hlist_bl_for_each_entry_rcu(tpos,pos,head,member) for (pos = hlist_bl_first_rcu(head); pos && ({ tpos = hlist_bl_entry(pos, typeof(*tpos), member); 1; }); pos = rcu_dereference_raw(pos->next))
#define BMSR_100BASE4 0x8000
#define ptrauth_thread_init_kernel(tsk) 
#define HWCAP_ATOMICS (1 << 8)
#define STATIC_CALL_SITE_FLAGS 3UL
#define LIST_BL_LOCKMASK 1UL
#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
#define STA_NANO 0x2000
#define __wait_event_idle_timeout(wq_head,condition,timeout) ___wait_event(wq_head, ___wait_cond_timeout(condition), TASK_IDLE, 0, timeout, __ret = schedule_timeout(__ret))
#define HFGxTR_EL2_REVIDR_EL1_WIDTH 1
#define debug_normal_state_change(cond) do { } while (0)
#define PACKET_FANOUT_FLAG_UNIQUEID 0x2000
#define SYS_ID_AA64AFR0_EL1_Op0 3
#define FAR_EL1_ADDR_MASK GENMASK(63, 0)
#define SYS_ID_AA64AFR0_EL1_Op2 4
#define xas_unlock(xas) xa_unlock((xas)->xa)
#define LED_FUNCTION_DISK "disk"
#define ID_ISAR4_EL1_PSR_M_IMP UL(0b0001)
#define SMPRIMAP_EL2_P11 GENMASK(47, 44)
#define SMPRIMAP_EL2_P12 GENMASK(51, 48)
#define SMPRIMAP_EL2_P13 GENMASK(55, 52)
#define SMPRIMAP_EL2_P14 GENMASK(59, 56)
#define SMPRIMAP_EL2_P15 GENMASK(63, 60)
#define CLIDR_EL1_ICB_SHIFT 30
#define ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
#define MVFR1_EL1_SIMDSP_SHIFT 16
#define QIF_ITIME (1 << QIF_ITIME_B)
#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
#define HFGITR_EL2_DCCVADP_SHIFT 9
#define smp_mb__after_atomic() do { kcsan_mb(); __smp_mb__after_atomic(); } while (0)
#define lockdep_set_class(lock,key) lockdep_init_map_type(&(lock)->dep_map, #key, key, 0, (lock)->dep_map.wait_type_inner, (lock)->dep_map.wait_type_outer, (lock)->dep_map.lock_type)
#define GMID_EL1_BS_SHIFT 0
#define ARM64_HAS_ECV_CNTPOFF 20
#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 
#define PCI_EPF_MODULE_PREFIX "pci_epf:"
#define PKT_TYPE_OFFSET offsetof(struct sk_buff, __pkt_type_offset)
#define SCTP_V6_FLOW 0x07
#define cap_clear(c) do { (c).val = 0; } while (0)
#define MVFR0_EL1_FPTrap_MASK GENMASK(15, 12)
#define SMCR_ELx_FA64 GENMASK(31, 31)
#define __get_user_error(x,ptr,err) do { __typeof__(*(ptr)) __user *__p = (ptr); might_fault(); if (access_ok(__p, sizeof(*__p))) { __p = uaccess_mask_ptr(__p); __raw_get_user((x), __p, (err)); } else { (x) = (__force __typeof__(x))0; (err) = -EFAULT; } } while (0)
#define FS_NOATIME_FL 0x00000080
#define CTR_EL0_IDC_SHIFT 28
#define SI_FROMKERNEL(siptr) ((siptr)->si_code > 0)
#define llist_for_each_safe(pos,n,node) for ((pos) = (node); (pos) && ((n) = (pos)->next, true); (pos) = (n))
#define SYS_CNTPOFF_EL2_Op0 3
#define SYS_CNTPOFF_EL2_Op1 4
#define SYS_CNTPOFF_EL2_Op2 6
#define CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI 1
#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
#define PREEMPT_DISABLE_OFFSET PREEMPT_OFFSET
#define CONFIG_BPF 1
#define _LINUX_ELF_EM_H 
#define HDFGWTR_EL2_PMSIRR_EL1 GENMASK(31, 31)
#define DECLARE_SOCKADDR(type,dst,src) type dst = ({ __sockaddr_check_size(sizeof(*dst)); (type) src; })
#define ID_ISAR6_EL1_JSCVT_IMP UL(0b0001)
#define set_used_math() set_stopped_child_used_math(current)
#define BMCR_LOOPBACK 0x4000
#define IORESOURCE_DMA_WORD (1<<4)
#define DCACHE_MANAGED_DENTRY (DCACHE_MOUNTED|DCACHE_NEED_AUTOMOUNT|DCACHE_MANAGE_TRANSIT)
#define ETH_MODULE_SFF_8079 0x1
#define __put_kernel_nofault(dst,src,type,err_label) do { __typeof__(dst) __pkn_dst = (dst); __typeof__(src) __pkn_src = (src); int __pkn_err = 0; __mte_enable_tco_async(); __raw_put_mem("str", *((type *)(__pkn_src)), (__force type *)(__pkn_dst), __pkn_err, K); __mte_disable_tco_async(); if (unlikely(__pkn_err)) goto err_label; } while(0)
#define X86_VENDOR_ANY 0xffff
#define cmpxchg128(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_mb(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg128(__ai_ptr, __VA_ARGS__); })
#define IOCB_FLAG_RESFD (1 << 0)
#define _LINUX_CAPABILITY_H 
#define ID_AA64DFR0_EL1_PMSVer_WIDTH 4
#define ADJ_MAXERROR 0x0004
#define nop() asm volatile ("nop")
#define __NR_membarrier 283
#define IOPRIO_HINT_MASK (IOPRIO_NR_HINTS - 1)
#define QC_INO_HARD (1<<1)
#define SECCOMP_RET_TRAP 0x00030000U
#define PSR_BTYPE_SHIFT 10
#define pr_info_ratelimited(fmt,...) printk_ratelimited(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__)
#define CONFIG_ARCH_MMAP_RND_BITS 18
#define CONFIG_CC_HAS_KASAN_SW_TAGS 1
#define HFGxTR_EL2_ICC_IGRPENn_EL1 GENMASK(39, 39)
#define arch_atomic_fetch_andnot_acquire arch_atomic_fetch_andnot_acquire
#define SYS_SECCOMP 1
#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
#define MNT_FORCE 0x00000001
#define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | ESR_ELx_CP15_32_ISS_OP2_MASK | ESR_ELx_CP15_32_ISS_CRN_MASK | ESR_ELx_CP15_32_ISS_CRM_MASK | ESR_ELx_CP15_32_ISS_DIR_MASK)
#define PR_SET_MM_START_STACK 5
#define CONFIG_NET_VENDOR_STMICRO 1
#define SYS_HFGITR_EL2_Op0 3
#define SYS_HFGITR_EL2_Op1 4
#define SYS_HFGITR_EL2_Op2 6
#define MDCR_EL2_HPME (UL(1) << 7)
#define CALLER_ADDR1 ((unsigned long)ftrace_return_address(1))
#define _UAPI_LINUX_CAPABILITY_H 
#define CALLER_ADDR5 ((unsigned long)ftrace_return_address(5))
#define __NR_rt_sigaction 134
#define EALREADY 114
#define KMALLOC_NOT_NORMAL_BITS (__GFP_RECLAIMABLE | (IS_ENABLED(CONFIG_ZONE_DMA) ? __GFP_DMA : 0) | (IS_ENABLED(CONFIG_MEMCG_KMEM) ? __GFP_ACCOUNT : 0))
#define ENOIOCTLCMD 515
#define ID_AA64PFR1_EL1_SSBS_IMP UL(0b0001)
#define VM_PFNMAP 0x00000400
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
#define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
#define SKB_DR_INIT(name,reason) enum skb_drop_reason name = SKB_DROP_REASON_ ##reason
#define JOBCTL_STOP_CONSUME (1UL << JOBCTL_STOP_CONSUME_BIT)
#define ID_ISAR1_EL1_Interwork_BLX UL(0b0010)
#define IPV6_MULTICAST_LOOP 19
#define CONFIG_ARCH_SUPPORTS_CRASH_DUMP 1
#define HFGxTR_EL2_ERXADDR_EL1_SHIFT 49
#define kprobe_busy_begin() do {} while (0)
#define __initdata_or_meminfo __initdata
#define SVE_SIG_FLAG_SM 0x1
#define PHY_SHARED_F_INIT_DONE 0
#define ETHTOOL_SSG 0x00000019
#define CONFIG_APPLE_RTKIT 1
#define pure_initcall(fn) __define_initcall(fn, 0)
#define VFS_CAP_U32_2 2
#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
#define PIRx_ELx_Perm3 GENMASK(15, 12)
#define flowi6_tun_key __fl_common.flowic_tun_key
#define unsafe_save_altstack(uss,sp,label) do { stack_t __user *__uss = uss; struct task_struct *t = current; unsafe_put_user((void __user *)t->sas_ss_sp, &__uss->ss_sp, label); unsafe_put_user(t->sas_ss_flags, &__uss->ss_flags, label); unsafe_put_user(t->sas_ss_size, &__uss->ss_size, label); } while (0);
#define ID_AA64MMFR0_EL1_BIGEND GENMASK(11, 8)
#define ID_AA64PFR0_EL1_CSV2_WIDTH 4
#define lower_32_bits(n) ((u32)((n) & 0xffffffff))
#define ID_ISAR6_EL1_SB_IMP UL(0b0001)
#define MDIO_USXGMII_100 0x0200
#define KUNIT_ASSERT_FALSE_MSG(test,condition,fmt,...) KUNIT_FALSE_MSG_ASSERTION(test, KUNIT_ASSERTION, condition, fmt, ##__VA_ARGS__)
#define __ASM_EXTABLE_RAW(insn,fixup,type,data) ".pushsection	__ex_table, \"a\"\n" ".align		2\n" ".long		((" insn ") - .)\n" ".long		((" fixup ") - .)\n" ".short		(" type ")\n" ".short		(" data ")\n" ".popsection\n"
#define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK
#define ID_AA64PFR0_EL1_RME_SHIFT 52
#define HFGxTR_EL2_APGAKey_WIDTH 1
#define SVE_PT_SVE_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
#define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name))
#define SMIDR_EL1_UNKN (UL(0))
#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
#define CONFIG_EXTRA_FIRMWARE ""
#define ID_AA64SMFR0_EL1_BI32I32_NI UL(0b0)
#define try_cmpxchg_local(ptr,oldp,...) ({ typeof(ptr) __ai_ptr = (ptr); typeof(oldp) __ai_oldp = (oldp); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); instrument_read_write(__ai_oldp, sizeof(*__ai_oldp)); raw_try_cmpxchg_local(__ai_ptr, __ai_oldp, __VA_ARGS__); })
#define _DEFINE_DEV_PM_OPS(name,suspend_fn,resume_fn,runtime_suspend_fn,runtime_resume_fn,idle_fn) const struct dev_pm_ops name = { SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) RUNTIME_PM_OPS(runtime_suspend_fn, runtime_resume_fn, idle_fn) }
#define SCTLR_EL1_SED GENMASK(8, 8)
#define CONFIG_GENERIC_PTDUMP 1
#define VM_WIPEONFORK 0x02000000
#define CONFIG_IO_URING 1
#define ID_AA64SMFR0_EL1_I16I32 GENMASK(47, 44)
#define SMCR_ELx_LEN_SHIFT 0
#define MNT_SYNC_UMOUNT 0x2000000
#define CONFIG_RANDOMIZE_KSTACK_OFFSET 1
#define NR_VM_NUMA_EVENT_ITEMS 0
#define DMA_ATTR_WEAK_ORDERING (1UL << 1)
#define KERNEL_HWCAP_MOPS __khwcap2_feature(MOPS)
#define PIE_R_O 0x1
#define PR_MTE_TCF_SHIFT 1
#define CONFIG_BUG 1
#define __FPE_DECERR 11
#define ARCH_SETUP_ADDITIONAL_PAGES(bprm,ex,interpreter) arch_setup_additional_pages(bprm, interpreter)
#define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
#define ID_AA64SMFR0_EL1_FA64_MASK GENMASK(63, 63)
#define CONFIG_CRYPTO_MANAGER_DISABLE_TESTS 1
#define array_index_mask_nospec array_index_mask_nospec
#define SLAB_MEM_SPREAD ((slab_flags_t __force)0x00100000U)
#define MVFR1_EL1_FPHP_FPHP_CONV UL(0b0010)
#define SVCR_SM_WIDTH 1
#define __this_cpu_generic_read_nopreempt(pcp) ({ typeof(pcp) ___ret; preempt_disable_notrace(); ___ret = READ_ONCE(*raw_cpu_ptr(&(pcp))); preempt_enable_notrace(); ___ret; })
#define __unqual_scalar_typeof(x) typeof( _Generic((x), char: (char)0, __scalar_type_to_expr_cases(char), __scalar_type_to_expr_cases(short), __scalar_type_to_expr_cases(int), __scalar_type_to_expr_cases(long), __scalar_type_to_expr_cases(long long), default: (x)))
#define NETLINK_INET_DIAG NETLINK_SOCK_DIAG
#define ID_AA64MMFR0_EL1_TGRAN4_2 GENMASK(43, 40)
#define AF_TIPC 30
#define devm_add_action_or_reset(dev,action,data) __devm_add_action_or_reset(dev, action, data, #action)
#define SMPRIMAP_EL2_P12_MASK GENMASK(51, 48)
#define topology_core_id(cpu) (cpu_topology[cpu].core_id)
#define ID_MMFR1_EL1_L1UniVA_WIDTH 4
#define PMSFCR_EL1_B_WIDTH 1
#define SOCK_IOC_TYPE 0x89
#define MODULE_FIRMWARE(_firmware) MODULE_INFO(firmware, _firmware)
#define VIRTUAL_BUG_ON(cond) do { } while (0)
#define PACKET_FANOUT_CPU 2
#define __early_set_fixmap __set_fixmap
#define ID_MMFR2_EL1_UniTLB_NI UL(0b0000)
#define MVFR0_EL1_FPTrap GENMASK(15, 12)
#define SZ_1 0x00000001
#define __SVE_PREG_SIZE(vq) ((__u32)(vq) * (__SVE_VQ_BYTES / 8))
#define page_ptdesc(p) (_Generic((p), const struct page *: (const struct ptdesc *)(p), struct page *: (struct ptdesc *)(p)))
#define PTRACE_PEEKSIGINFO 0x4209
#define ID_AA64AFR0_EL1_IMPDEF2_SHIFT 8
#define EM_CRIS 76
#define ID_DFR0_EL1_CopDbg_Debugv8p2 UL(0b1000)
#define ID_DFR0_EL1_CopDbg_Debugv8p4 UL(0b1001)
#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
#define ID_AA64MMFR3_EL1_MEC GENMASK(31, 28)
#define ID_DFR0_EL1_CopDbg_Debugv8p8 UL(0b1010)
#define XA_ERROR(errno) ((struct xa_node *)(((unsigned long)errno << 2) | 2UL))
#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000
#define MDIO_AN_C73_1_40GBASE_KR4 BIT(8)
#define HCR_IMO (UL(1) << 4)
#define FLOW_RSS 0x20000000
#define ID_AA64DFR0_EL1_DebugVer_MASK GENMASK(3, 0)
#define ID_MMFR2_EL1_L1HvdRng_WIDTH 4
#define FS_XFLAG_PROJINHERIT 0x00000200
#define R_AARCH64_ADD_ABS_LO12_NC 277
#define SECCOMP_RET_KILL SECCOMP_RET_KILL_THREAD
#define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
#define do_ftrace_record_recursion(ip,pip) do { } while (0)
#define __pfn_to_phys(pfn) PFN_PHYS(pfn)
#define PR_FP_EXC_PRECISE 3
#define smp_send_reschedule(cpu) ({ trace_ipi_send_cpu(cpu, _RET_IP_, NULL); arch_smp_send_reschedule(cpu); })
#define HFGxTR_EL2_LOREA_EL1 GENMASK(20, 20)
#define REG_ID_AA64ISAR0_EL1 S3_0_C0_C6_0
#define CONFIG_KERNFS 1
#define pci_remap_cfgspace pci_remap_cfgspace
#define HFGITR_EL2_ICIALLUIS_WIDTH 1
#define _LINUX_IRQNR_H 
#define ida_simple_get(ida,start,end,gfp) ida_alloc_range(ida, start, (end) - 1, gfp)
#define KERNEL_HWCAP_SVE2 __khwcap2_feature(SVE2)
#define ID_AA64ISAR2_EL1_WFxT_NI UL(0b0000)
#define CONFIG_NET_VENDOR_ROCKER 1
#define ARCH_HAS_PREFETCH 
#define NODES_PGSHIFT (NODES_PGOFF * (NODES_WIDTH != 0))
#define for_next_zone_zonelist_nodemask(zone,z,highidx,nodemask) for (zone = z->zone; zone; z = next_zones_zonelist(++z, highidx, nodemask), zone = zonelist_zone(z))
#define __always_unused __attribute__((__unused__))
#define _LINUX_ATOMIC_FALLBACK_H 
#define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
#define UMH_WAIT_EXEC 0x01
#define ID_AA64PFR1_EL1_MPAM_frac_SHIFT 16
#define BITS_PER_BYTE 8
#define TRBSR_EL1_EA_SHIFT 18
#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000
#define ID_AA64ISAR1_EL1_LRCPC_NI UL(0b0000)
#define IORESOURCE_BITS 0x000000ff
#define writeb_relaxed writeb_relaxed
#define _UAPI_LINUX_SWAB_H 
#define PSR_AA32_Z_BIT 0x40000000
#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) | ESR_ELx_CP15_32_ISS_DIR_READ)
#define ENODATA 61
#define MNT_NOATIME 0x08
#define HWCAP_USCAT (1 << 25)
#define IPV6_AUTHHDR 10
#define _ASM_GENERIC_BITOPS_FFZ_H_ 
#define __constant_htonl(x) ((__force __be32)___constant_swab32((x)))
#define PTRACE_O_TRACEVFORK (1 << PTRACE_EVENT_VFORK)
#define TRBSR_EL1_MSS GENMASK(15, 0)
#define CNTHCTL_EL1PCEN (1 << 1)
#define fl4_mh_type uli.mht.type
#define HDFGWTR_EL2_TRBPTR_EL1_MASK GENMASK(54, 54)
#define SCTLR_EL1_nAA_SHIFT 6
#define STATX_ATTR_NODUMP 0x00000040
#define MDSCR_EL1_SS_MASK GENMASK(0, 0)
#define ID_AA64MMFR1_EL1_CMOW GENMASK(59, 56)
#define SKB_DATAREF_MASK ((1 << SKB_DATAREF_SHIFT) - 1)
#define ID_AA64ISAR2_EL1_APA3_WIDTH 4
#define BCMA_ANY_REV 0xFF
#define INIT_CPUTIME_ATOMIC (struct task_cputime_atomic) { .utime = ATOMIC64_INIT(0), .stime = ATOMIC64_INIT(0), .sum_exec_runtime = ATOMIC64_INIT(0), }
#define SYS_PMSFCR_EL1_Op0 3
#define ID_AA64SMFR0_EL1_F16F16_NI UL(0b0)
#define ID_AA64DFR0_EL1_BRBE_SIGNED false
#define SYS_PMSFCR_EL1_Op1 0
#define ID_AA64ISAR0_EL1_AES_SHIFT 4
#define raw_cpu_add_1(pcp,val) raw_cpu_generic_to_op(pcp, val, +=)
#define ID_PFR1_EL1_ProgMod_MASK GENMASK(3, 0)
#define raw_cpu_add_4(pcp,val) raw_cpu_generic_to_op(pcp, val, +=)
#define raw_cpu_add_8(pcp,val) raw_cpu_generic_to_op(pcp, val, +=)
#define ID_AA64MMFR3_EL1_MEC_IMP UL(0b0001)
#define PFA_SPEC_SSB_NOEXEC 7
#define ID_ISAR4_EL1_SMC_WIDTH 4
#define EMT_TAGOVF 1
#define SUPPORTED_Backplane __ETHTOOL_LINK_MODE_LEGACY_MASK(Backplane)
#define ID_MMFR1_EL1_BPred_SHIFT 28
#define abs_diff(a,b) ({ typeof(a) __a = (a); typeof(b) __b = (b); (void)(&__a == &__b); __a > __b ? (__a - __b) : (__b - __a); })
#define KERNEL_TIMECONST_H 
#define EPOLL_CLOEXEC O_CLOEXEC
#define ID_AA64PFR1_EL1_BT GENMASK(3, 0)
#define ID_MMFR4_EL1_EVT_WIDTH 4
#define HFGITR_EL2_TLBIVAE1OS_SHIFT 19
#define INIT_IDMAP_DIR_PAGES EARLY_PAGES(KIMAGE_VADDR, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE, 1)
#define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
#define PTRACE_SECCOMP_GET_METADATA 0x420d
#define CONFIG_NET_VENDOR_PENSANDO 1
#define CONFIG_ARCH_ZYNQMP 1
#define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f
#define __ASM_MEMORY_H 
#define delayed_work_pending(w) work_pending(&(w)->work)
#define __tlbi(op,...) __TLBI_N(op, ##__VA_ARGS__, 1, 0)
#define __no_kcsan 
#define arch_flush_lazy_mmu_mode() do {} while (0)
#define mmiowb_spin_unlock() do { } while (0)
#define core_param(name,var,type,perm) param_check_ ##type(name, &(var)); __module_param_call("", name, &param_ops_ ##type, &var, perm, -1, 0)
#define MNT_INTERNAL_FLAGS (MNT_SHARED | MNT_WRITE_HOLD | MNT_INTERNAL | MNT_DOOMED | MNT_SYNC_UMOUNT | MNT_MARKED | MNT_CURSOR)
#define __swait_event_idle(wq,condition) (void)___swait_event(wq, condition, TASK_IDLE, 0, schedule())
#define CONTEXTIDR_ELx_PROCID_MASK GENMASK(31, 0)
#define __swab64(x) (__u64)(__builtin_constant_p(x) ? ___constant_swab64(x) : __fswab64(x))
#define ___EXPORT_SYMBOL(sym,license,ns) .section ".export_symbol","a" ASM_NL __export_symbol_ ##sym: ASM_NL .asciz license ASM_NL .asciz ns ASM_NL __EXPORT_SYMBOL_REF(sym) ASM_NL .previous
#define ID_AA64ZFR0_EL1_I8MM_NI UL(0b0000)
#define ID_ISAR6_EL1_BF16_IMP UL(0b0001)
#define QC_SPC_TIMER (1<<6)
#define SYS_PMSFCR_EL1_CRm 9
#define SYS_PMSFCR_EL1_CRn 9
#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56
#define SCTLR_EL1_TSCXT_MASK GENMASK(20, 20)
#define current_restore_rtlock_saved_state() do { lockdep_assert_irqs_disabled(); raw_spin_lock(&current->pi_lock); debug_rtlock_wait_restore_state(); WRITE_ONCE(current->__state, current->saved_state); current->saved_state = TASK_RUNNING; raw_spin_unlock(&current->pi_lock); } while (0);
#define ID_AA64SMFR0_EL1_F64F64_MASK GENMASK(48, 48)
#define current_user() (current_cred_xxx(user))
#define BVEC_ITER_ALL_INIT (struct bvec_iter) { .bi_sector = 0, .bi_size = UINT_MAX, .bi_idx = 0, .bi_bvec_done = 0, }
#define interval_tree_for_each_span(span,itree,first_index,last_index) for (interval_tree_span_iter_first(span, itree, first_index, last_index); !interval_tree_span_iter_done(span); interval_tree_span_iter_next(span))
#define HFGxTR_EL2_TPIDR_EL0 GENMASK(35, 35)
#define HFGxTR_EL2_TPIDR_EL1 GENMASK(33, 33)
#define HFGITR_EL2_TLBIASIDE1_MASK GENMASK(44, 44)
#define __minmax_array(op,array,len) ({ typeof(&(array)[0]) __array = (array); typeof(len) __len = (len); __unqual_scalar_typeof(__array[0]) __element = __array[--__len]; while (__len--) __element = op(__element, __array[__len]); __element; })
#define __ASM_CMPXCHG_H 
#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
#define HFGITR_EL2_COSPRCTX GENMASK(60, 60)
#define __NR_io_destroy 1
#define HFGITR_EL2_TLBIVAAE1IS_MASK GENMASK(31, 31)
#define PIRx_ELx_Perm5_MASK GENMASK(23, 20)
#define LOCAL_LOCK_DEBUG_INIT(lockname) .dep_map = { .name = #lockname, .wait_type_inner = LD_WAIT_CONFIG, .lock_type = LD_LOCK_PERCPU, }, .owner = NULL,
#define module_name(mod) "kernel"
#define NLM_F_BULK 0x200
#define CONFIG_RANDSTRUCT_NONE 1
#define PSR_AA32_IT_MASK 0x0600fc00
#define __NR_timer_settime 110
#define arch_counter_enforce_ordering(val) do { u64 tmp, _val = (val); asm volatile( "	eor	%0, %1, %1\n" "	add	%0, sp, %0\n" "	ldr	xzr, [%0]" : "=r" (tmp) : "r" (_val)); } while (0)
#define SA_SIGINFO 0x00000004
#define rcu_dereference_sched(p) rcu_dereference_sched_check(p, 0)
#define RCU_DYNTICKS_IDX CONTEXT_MAX
#define S_NOCMTIME (1 << 7)
#define __NR_pread64 67
#define SIGURG 23
#define HDFGWTR_EL2_PMSLATFR_EL1_MASK GENMASK(32, 32)
#define ID_ISAR1_EL1_Interwork_BX UL(0b0001)
#define CONFIG_SPI_MASTER 1
#define IPV6_NEXTHOP 9
#define IFF_DORMANT IFF_DORMANT
#define MDIO_EEE_2_5GT 0x0001
#define STATX_UID 0x00000008U
#define ID_ISAR0_EL1_Swap_IMP UL(0b0001)
#define ARM64_HAS_EVT 22
#define __test_and_clear_bit(nr,addr) bitop(___test_and_clear_bit, nr, addr)
#define DEFAULT_SEEKS 2
#define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
#define MVFR1_EL1_SIMDFMAC_MASK GENMASK(31, 28)
#define CLIDR_EL1_Ctype4_MASK GENMASK(11, 9)
#define CYCLECOUNTER_MASK(bits) (u64)((bits) < 64 ? ((1ULL<<(bits))-1) : -1)
#define ID_MMFR1_EL1_L1Uni_INVALIDATE UL(0b0001)
#define CONFIG_SPI_XILINX 1
#define BMSR_10HALF 0x0800
#define MDSCR_EL1_EHBWE_SHIFT 35
#define LED_FUNCTION_MAIL "mail"
#define DACR32_EL2_D8_WIDTH 2
#define raw_cpu_and(pcp,val) __pcpu_size_call(raw_cpu_and_, pcp, val)
#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
#define skb_walk_frags(skb,iter) for (iter = skb_shinfo(skb)->frag_list; iter; iter = iter->next)
#define ETHTOOL_COALESCE_TX_USECS_LOW BIT(14)
#define CFI_BRK_IMM_TARGET GENMASK(4, 0)
#define HFGxTR_EL2_ERXFR_EL1_MASK GENMASK(42, 42)
#define TASK_PARKED 0x00000040
#define PATH_MAX 4096
#define HCR_TVM (UL(1) << 26)
#define SMPRIMAP_EL2_P6_SHIFT 24
#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
#define _DPRINTK_FLAGS_PRINT (1<<0)
#define SYS_SEND 9
#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | HCR_BSU_IS | HCR_FB | HCR_TACR | HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3)
#define PSR_UAO_BIT 0x00800000
#define esr_sys64_to_sysreg(e) sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> ESR_ELx_SYS64_ISS_OP0_SHIFT), (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> ESR_ELx_SYS64_ISS_OP1_SHIFT), (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> ESR_ELx_SYS64_ISS_CRN_SHIFT), (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT), (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> ESR_ELx_SYS64_ISS_OP2_SHIFT))
#define HFGxTR_EL2_ERXFR_EL1 GENMASK(42, 42)
#define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0)
#define LED_SYSFS_DISABLE BIT(17)
#define cpu_to_node(cpu) ((void)(cpu),0)
#define HDFGRTR_EL2_DBGWCRn_EL1_MASK GENMASK(2, 2)
#define current_sgid() (current_cred_xxx(sgid))
#define HDFGWTR_EL2_PMBLIMITR_EL1_MASK GENMASK(23, 23)
#define ERECALLCONFLICT 530
#define P4D_SHIFT PGDIR_SHIFT
#define READ_ONCE_NOCHECK(x) ({ compiletime_assert(sizeof(x) == sizeof(unsigned long), "Unsupported access size for READ_ONCE_NOCHECK()."); (typeof(x))__read_once_word_nocheck(&(x)); })
#define SO_LINGER 13
#define SOCK_SNDBUF_LOCK 1
#define MA_ERROR(err) ((struct maple_enode *)(((unsigned long)err << 2) | 2UL))
#define _DEVICE_PRINTK_H_ 
#define RCU_CBLIST_NSEGS 4
#define ID_AA64MMFR0_EL1_ECV_SIGNED false
#define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
#define LEDS_TRIG_TYPE_LEVEL 1
#define XA_RETRY_ENTRY xa_mk_internal(256)
#define KUNIT_UNARY_ASSERTION(test,assert_type,condition_,expected_true_,fmt,...) do { if (likely(!!(condition_) == !!expected_true_)) break; _KUNIT_FAILED(test, assert_type, kunit_unary_assert, kunit_unary_assert_format, KUNIT_INIT_ASSERT(.condition = #condition_, .expected_true = expected_true_), fmt, ##__VA_ARGS__); } while (0)
#define __ASM_PROCFNS_H 
#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
#define RUSAGE_BOTH (-2)
#define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
#define arch_write_trylock(l) queued_write_trylock(l)
#define free_highmem_page(page) free_reserved_page(page)
#define MVFR1_EL1_FPFtZ_SIGNED false
#define HFGITR_EL2_nGCSPUSHM_EL1 GENMASK(57, 57)
#define SB_I_UNTRUSTED_MOUNTER 0x00000040
#define DBG_ESR_EVT_BKPT 0x4
#define KASAN_SHADOW_SCALE_SHIFT 
#define ESR_ELx_EC_ERET (0x1a)
#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
#define ID_AA64MMFR2_EL1_FWB_WIDTH 4
#define X86_FEATURE_ANY 0
#define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
#define hex_asc_upper_hi(x) hex_asc_upper[((x) & 0xf0) >> 4]
#define ILL_ILLADR 3
#define HCR_API (UL(1) << 41)
#define FLOWI_FLAG_KNOWN_NH 0x02
#define _LINUX_PERCPU_RWSEM_H 
#define topology_die_cpumask(cpu) cpumask_of(cpu)
#define _LINUX_ERRSEQ_H 
#define SIGQUIT 3
#define SLIMBUS_MODULE_PREFIX "slim:"
#define __WAIT_QUEUE_HEAD_INITIALIZER(name) { .lock = __SPIN_LOCK_UNLOCKED(name.lock), .head = LIST_HEAD_INIT(name.head) }
#define test_and_clear_thread_flag(flag) test_and_clear_ti_thread_flag(current_thread_info(), flag)
#define SCTLR_EL1_ATA_SHIFT 43
#define init_idle_preempt_count(p,cpu) do { task_thread_info(p)->preempt_count = PREEMPT_DISABLED; } while (0)
#define pr_emerg_ratelimited(fmt,...) printk_ratelimited(KERN_EMERG pr_fmt(fmt), ##__VA_ARGS__)
#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x))
#define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
#define mutex_release(l,i) lock_release(l, i)
#define PF_CAIF AF_CAIF
#define CONFIG_SND_PCM_XRUN_DEBUG 1
#define MDIO_PCS_STAT2_RXFLTABLE 0x1000
#define vabits_actual ((u64)VA_BITS)
#define CCSIDR_EL1_NumSets GENMASK(27, 13)
#define dma_rmb() do { kcsan_rmb(); __dma_rmb(); } while (0)
#define SYS_PIR_EL1 sys_reg(3, 0, 10, 2, 3)
#define SYS_PIR_EL2 sys_reg(3, 4, 10, 2, 3)
#define pud_bad(pud) (!pud_table(pud))
#define PACKET_KERNEL 7
#define TIMER_ARRAYSHIFT 22
#define ID_AA64AFR0_EL1_IMPDEF7_MASK GENMASK(31, 28)
#define USEC_TO_HZ_DEN 4000
#define SIG_KTHREAD_KERNEL ((__force __sighandler_t)3)
#define MAS_WR_BUG_ON(__mas,__x) BUG_ON(__x)
#define wait_var_event_timeout(var,condition,timeout) ({ long __ret = timeout; might_sleep(); if (!___wait_cond_timeout(condition)) __ret = __wait_var_event_timeout(var, condition, timeout); __ret; })
#define CONFIG_NET_VENDOR_MICROSOFT 1
#define DMA_ATTR_ALLOC_SINGLE_PAGES (1UL << 7)
#define ID_AA64MMFR2_EL1_RES0 (UL(0) | GENMASK_ULL(47, 44))
#define ID_AA64MMFR2_EL1_RES1 (UL(0))
#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
#define __irq_entry __section(".irqentry.text")
#define REG_OSDTRRX_EL1 S2_0_C0_C0_2
#define arch_set_freq_scale topology_set_freq_scale
#define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
#define PSEC_PER_NSEC 1000L
#define KUNIT_PTR_NOT_ERR_OR_NULL_MSG_ASSERTION(test,assert_type,ptr,fmt,...) do { const typeof(ptr) __ptr = (ptr); if (!IS_ERR_OR_NULL(__ptr)) break; _KUNIT_FAILED(test, assert_type, kunit_ptr_not_err_assert, kunit_ptr_not_err_assert_format, KUNIT_INIT_ASSERT(.text = #ptr, .value = __ptr), fmt, ##__VA_ARGS__); } while (0)
#define CONFIG_ARCH_PROC_KCORE_TEXT 1
#define __pass_object_size(type) 
#define __TLBI_VADDR(addr,asid) ({ unsigned long __ta = (addr) >> 12; __ta &= GENMASK_ULL(43, 0); __ta |= (unsigned long)(asid) << 48; __ta; })
#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
#define list_for_each(pos,head) for (pos = (head)->next; !list_is_head(pos, (head)); pos = pos->next)
#define HCR_APK (UL(1) << 40)
#define CCSIDR2_EL1_UNKN (UL(0))
#define ID_DFR0_EL1_PerfMon_PMUv1 UL(0b0001)
#define ID_DFR0_EL1_PerfMon_PMUv2 UL(0b0010)
#define ID_DFR0_EL1_PerfMon_PMUv3 UL(0b0011)
#define RTSIG_MAX 32
#define PTRACE_SINGLESTEP 9
#define AARCH32_BREAK_THUMB2_HI 0xa000
#define smp_wmb() do { kcsan_wmb(); __smp_wmb(); } while (0)
#define _Q_PENDING_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
#define __MEM_ENCRYPT_H__ 
#define RED_ACTIVE 0xD84156C5635688C0ULL
#define ID_AA64MMFR3_EL1_S1PIE GENMASK(11, 8)
#define ESR_ELx_FnV_SHIFT (10)
#define STATX_CHANGE_COOKIE 0x40000000U
#define IPV6_RECVORIGDSTADDR IPV6_ORIGDSTADDR
#define SIGTTOU 22
#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
#define read_unlock(lock) _raw_read_unlock(lock)
#define DQUOT_DEL_ALLOC max(V1_DEL_ALLOC, V2_DEL_ALLOC)
#define get_current_user() ({ struct user_struct *__u; const struct cred *__cred; __cred = current_cred(); __u = get_uid(__cred->user); __u; })
#define __REFDATA .section ".ref.data", "aw"
#define ID_AA64MMFR3_EL1_ADERR GENMASK(59, 56)
#define for_each_available_cap(cap) for_each_set_bit(cap, system_cpucaps, ARM64_NCAPS)
#define AF_BRIDGE 7
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
#define __LINUX_GFP_H 
#define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
#define HDFGRTR_EL2_OSDLR_EL1_MASK GENMASK(11, 11)
#define F_OWNER_TID 0
#define ARM_CPU_PART_CORTEX_A710 0xD47
#define MDIO_AN_C73_2_5GBASE_KR BIT(1)
#define SYS_ID_ISAR6_EL1_Op0 3
#define SYS_ID_ISAR6_EL1_Op1 0
#define ARM_CPU_PART_CORTEX_A715 0xD4D
#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
#define __WORK_INITIALIZER(n,f) { .data = WORK_DATA_STATIC_INIT(), .entry = { &(n).entry, &(n).entry }, .func = (f), __WORK_INIT_LOCKDEP_MAP(#n, &(n)) }
#define HDFGRTR_EL2_DBGCLAIM_SHIFT 5
#define MDIO_PCS_EEE_WK_ERR 22
#define ID_DFR0_EL1_CopSDbg GENMASK(7, 4)
#define HVC_STUB_HCALL_NR 4
#define FAR_EL12_ADDR GENMASK(63, 0)
#define flowi4_tun_key __fl_common.flowic_tun_key
#define ID_MMFR1_EL1_L1HvdSW_MASK GENMASK(11, 8)
#define ___wait_is_interruptible(state) (!__builtin_constant_p(state) || (state & (TASK_INTERRUPTIBLE | TASK_WAKEKILL)))
#define compat_arg_u64(name) u32 name ##_lo, u32 name ##_hi
#define ID_DFR0_EL1_MMapTrc_WIDTH 4
#define REMAP_FILE_DEDUP (1 << 0)
#define ID_PFR1_EL1_ProgMod_NI UL(0b0000)
#define __NR_fsconfig 431
#define SIOCGIFBRDADDR 0x8919
#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
#define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE)
#define SCTLR_EL1_E0E GENMASK(24, 24)
#define FLOW_CTRL_RX 0x02
#define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
#define pageblock_order MAX_ORDER
#define SPINLOCK_SIZE 64
#define HDFGRTR_EL2_PMCEIDn_EL0 GENMASK(58, 58)
#define SKB_TRUESIZE(X) ((X) + SKB_DATA_ALIGN(sizeof(struct sk_buff)) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
#define MDSCR_EL1_TXfull_MASK GENMASK(29, 29)
#define LED_FUNCTION_BACKLIGHT "backlight"
#define flowi_iif u.__fl_common.flowic_iif
#define SKB_DR_SET(name,reason) (name = SKB_DROP_REASON_ ##reason)
#define __read_seqcount_begin(s) ({ unsigned __seq; while ((__seq = seqprop_sequence(s)) & 1) cpu_relax(); kcsan_atomic_next(KCSAN_SEQLOCK_REGION_MAX); __seq; })
#define HFGITR_EL2_CFPRCTX_MASK GENMASK(48, 48)
#define MVFR0_EL1_FPDivide_SHIFT 16
#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)
#define ID_AA64MMFR2_EL1_CnP_MASK GENMASK(3, 0)
#define DEFINE_WAIT(name) DEFINE_WAIT_FUNC(name, autoremove_wake_function)
#define CONFIG_FW_LOADER 1
#define HFGITR_EL2_DCCVAU_MASK GENMASK(7, 7)
#define SG_DMA_BUS_ADDRESS (1 << 0)
#define CONFIG_VIDEO_CMDLINE 1
#define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
#define _LINUX_COMPAT_H 
#define HFGxTR_EL2_APDAKey_SHIFT 4
#define CONFIG_NET_VENDOR_FUNGIBLE 1
#define CONFIG_GPIO_PL061 1
#define DEFINE_RES_IO(_start,_size) DEFINE_RES_IO_NAMED((_start), (_size), NULL)
#define CONFIG_NET_VENDOR_CISCO 1
#define ID_AA64PFR0_EL1_FP_FP16 UL(0b0001)
#define ID_MMFR0_EL1_AuxReg_WIDTH 4
#define ID_AA64ZFR0_EL1_SVEver_WIDTH 4
#define ARM64_SME 55
#define CONFIG_ILLEGAL_POINTER_VALUE 0xdead000000000000
#define ID_AA64ISAR1_EL1_API_WIDTH 4
#define CONFIG_HZ_250 1
#define _PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
#define pm_generic_poweroff_late NULL
#define SYS_ID_AA64ZFR0_EL1_CRm 4
#define CONFIG_GENERIC_CALIBRATE_DELAY 1
#define CONFIG_NET_VENDOR_WANGXUN 1
#define SYS_HFGWTR_EL2_Op0 3
#define SYS_HFGWTR_EL2_Op1 4
#define SYS_HFGWTR_EL2_Op2 5
#define CCSIDR2_EL1_NumSets_WIDTH 24
#define sigev_notify_thread_id _sigev_un._tid
#define __lockfunc __section(".spinlock.text")
#define ID_PFR2_EL1_CSV3_NI UL(0b0000)
#define DMA_ATTR_WRITE_COMBINE (1UL << 2)
#define alloc_percpu_gfp(type,gfp) (typeof(type) __percpu *)__alloc_percpu_gfp(sizeof(type), __alignof__(type), gfp)
#define HSIPHASH_ALIGNMENT __alignof__(unsigned long)
#define ID_MMFR1_EL1_L1Uni_MASK GENMASK(23, 20)
#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
#define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
#define CAP_IPC_LOCK 14
#define arch_atomic_fetch_andnot_release arch_atomic_fetch_andnot_release
#define IORESOURCE_PREFETCH 0x00002000
#define ioremap_cache ioremap_cache
#define DCACHE_LRU_LIST 0x00080000
#define HFGxTR_EL2_ERXPFGCDN_EL1_WIDTH 1
#define SYS_LORN_EL1_CRm 4
#define SYS_LORN_EL1_CRn 10
#define ID_AA64MMFR0_EL1_TGRAN4_2_NI UL(0b0001)
#define ETH_P_PPP_DISC 0x8863
#define ID_AA64MMFR2_EL1_IDS_WIDTH 4
#define ENOGRACE 531
#define PM_EVENT_INVALID (-1)
#define ID_DFR0_EL1_CopDbg_Armv6p1 UL(0b0011)
#define IPV6_PREFER_SRC_COA 0x0004
#define TAINT_FORCED_RMMOD 3
#define SCTLR_EL1_TME0_SHIFT 52
#define set_stopped_child_used_math(child) do { (child)->flags |= PF_USED_MATH; } while (0)
#define OSDTRTX_EL1_DTRTX_SHIFT 0
#define STATX_SIZE 0x00000200U
#define CONFIG_LOCALVERSION ""
#define wait_event_interruptible_lock_irq_cmd(wq_head,condition,lock,cmd) ({ int __ret = 0; if (!(condition)) __ret = __wait_event_interruptible_lock_irq(wq_head, condition, lock, cmd); __ret; })
#define HFGxTR_EL2_LORN_EL1 GENMASK(22, 22)
#define arch_has_dev_port() (1)
#define SMPRIMAP_EL2_P7_MASK GENMASK(31, 28)
#define SVE_SIG_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
#define MDIO_STAT1_LPOWERABLE 0x0002
#define MAYBE_BUILD_BUG_ON(cond) do { if (__builtin_constant_p((cond))) BUILD_BUG_ON(cond); else BUG_ON(cond); } while (0)
#define ID_AA64MMFR0_EL1_TGRAN4_2_WIDTH 4
#define ID_AA64MMFR3_EL1_S1POE GENMASK(19, 16)
#define ID_AA64ISAR2_EL1_CLRBHB_NI UL(0b0000)
#define PR_RISCV_V_VSTATE_CTRL_ON 2
#define INPUT_DEVICE_ID_LED_MAX 0x0f
#define ARM64_SPECTRE_V3A 59
#define SVCR_ZA_SHIFT 1
#define netif_warn(priv,type,dev,fmt,args...) netif_level(warn, priv, type, dev, fmt, ##args)
#define write_sysreg_s(v,r) do { u64 __val = (u64)(v); u32 __maybe_unused __check_r = (u32)(r); asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); } while (0)
#define IORESOURCE_UNSET 0x20000000
#define DEFINE_DELAYED_CALL(name) struct delayed_call name = {NULL, NULL}
#define CPU_BITS_NONE { [0 ... BITS_TO_LONGS(NR_CPUS)-1] = 0UL }
#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
#define DEFINE_STATIC_KEY_TRUE(name) struct static_key_true name = STATIC_KEY_TRUE_INIT
#define CONFIG_CRYPTO_HASH2 1
#define ID_AA64ISAR1_EL1_SB_MASK GENMASK(39, 36)
#define PMSFCR_EL1_FnE_MASK GENMASK(3, 3)
#define CONFIG_DEFAULT_TCP_CONG "cubic"
#define ENOSR 63
#define EM_IA_64 50
#define S_ISDIR(m) (((m) & S_IFMT) == S_IFDIR)
#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | MIDR_ARCHITECTURE_MASK)
#define CTL1000_AS_MASTER 0x0800
#define preempt_set_need_resched() do { set_preempt_need_resched(); } while (0)
#define HDFGWTR_EL2_TRBLIMITR_EL1 GENMASK(52, 52)
#define ROOT_IS_IDR ((__force gfp_t)4)
#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
#define MVFR1_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define MVFR1_EL1_RES1 (UL(0))
#define LED_FUNCTION_STATUS "status"
#define DECLARE_PER_CPU_READ_MOSTLY(type,name) DECLARE_PER_CPU_SECTION(type, name, "..read_mostly")
#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
#define PCPU_MIN_UNIT_SIZE PFN_ALIGN(32 << 10)
#define NETLINK_SOCK_DIAG 4
#define flowi6_uid __fl_common.flowic_uid
#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
#define CONFIG_RATIONAL 1
#define COMPAT_HWCAP2_PMULL (1 << 1)
#define PR_RISCV_V_VSTATE_CTRL_INHERIT (1 << 4)
#define __local_lock_init(lock) do { static struct lock_class_key __key; debug_check_no_locks_freed((void *)lock, sizeof(*lock)); lockdep_init_map_type(&(lock)->dep_map, #lock, &__key, 0, LD_WAIT_CONFIG, LD_WAIT_INV, LD_LOCK_PERCPU); local_lock_debug_init(lock); } while (0)
#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
#define __pte(x) ((pte_t) { (x) } )
#define is_signed_type(type) (((type)(-1)) < (__force type)1)
#define KERNEL_HWCAP_SME_BI32I32 __khwcap2_feature(SME_BI32I32)
#define __alloc_size__(x,...) __attribute__((__alloc_size__(x, ## __VA_ARGS__)))
#define ID_AA64ISAR0_EL1_AES_WIDTH 4
#define __NR_inotify_init1 26
#define KUNIT_EXPECT_NULL(test,ptr) KUNIT_EXPECT_NULL_MSG(test, ptr, NULL)
#define REG_PIR_EL12 S3_5_C10_C2_3
#define ARM_MAX_BRP 16
#define flowi6_flags __fl_common.flowic_flags
#define ID_ISAR0_EL1_Divide_MASK GENMASK(27, 24)
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
#define arch___clear_bit generic___clear_bit
#define __constant_htons(x) ((__force __be16)___constant_swab16((x)))
#define VTCR_EL2_TG0_64K TCR_TG0_64K
#define SYS_TCR2_EL12_Op0 3
#define SYS_TCR2_EL12_Op1 5
#define SYS_TCR2_EL12_Op2 3
#define KCSAN_ACCESS_WRITE (1 << 0)
#define node_online_map node_states[N_ONLINE]
#define IRQF_EARLY_RESUME 0x00020000
#define NWAYTEST_RESV1 0x00ff
#define ETHTOOL_COALESCE_MAX_FRAMES_LOW_HIGH (ETHTOOL_COALESCE_RX_MAX_FRAMES_LOW | ETHTOOL_COALESCE_TX_MAX_FRAMES_LOW | ETHTOOL_COALESCE_RX_MAX_FRAMES_HIGH | ETHTOOL_COALESCE_TX_MAX_FRAMES_HIGH)
#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | ESR_ELx_SYS64_ISS_DIR_READ)
#define DEFINE_SIMPLE_DEV_PM_OPS(name,suspend_fn,resume_fn) _DEFINE_DEV_PM_OPS(name, suspend_fn, resume_fn, NULL, NULL, NULL)
#define for_each_sgtable_dma_page(sgt,dma_iter,pgoffset) for_each_sg_dma_page((sgt)->sgl, dma_iter, (sgt)->nents, pgoffset)
#define PMBSR_EL1_BUF_BSC_FULL 0x1UL
#define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
#define ICC_NMIAR1_EL1_INTID_WIDTH 24
#define FS_IOC_GETFSLABEL _IOR(0x94, 49, char[FSLABEL_MAX])
#define PR_GET_NO_NEW_PRIVS 39
#define NT_PRXFPREG 0x46e62b7f
#define CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ 1
#define CONFIG_UNINLINE_SPIN_UNLOCK 1
#define NT_S390_VXRS_HIGH 0x30a
#define ID_AA64ISAR1_EL1_UNKN (UL(0))
#define FMODE_CAN_WRITE ((__force fmode_t)0x40000)
#define ID_AA64DFR0_EL1_RES0 (UL(0) | GENMASK_ULL(59, 56) | GENMASK_ULL(27, 24) | GENMASK_ULL(19, 16))
#define ID_AA64DFR0_EL1_RES1 (UL(0))
#define PMBIDR_EL1_ALIGN_MASK GENMASK(3, 0)
#define IPV6_2292PKTOPTIONS 6
#define SCTLR_EL1_EnASR_MASK GENMASK(54, 54)
#define THP_FILE_FALLBACK_CHARGE ({ BUILD_BUG(); 0; })
#define __SVE_PREGS_OFFSET(vq) (__SVE_ZREGS_OFFSET + __SVE_ZREGS_SIZE(vq))
#define SPEED_56000 56000
#define ESR_ELx_EC_DABT_LOW (0x24)
#define slab_prepare_cpu NULL
#define CONFIG_ALLOW_DEV_COREDUMP 1
#define PTE_DBM (_AT(pteval_t, 1) << 51)
#define PAGE_IS_FILE (1 << 2)
#define NT_S390_TIMER 0x301
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define ID_ISAR0_EL1_RES0 (UL(0) | GENMASK_ULL(63, 28))
#define ID_ISAR0_EL1_RES1 (UL(0))
#define FS_INLINE_DATA_FL 0x10000000
#define CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1
#define __tag_shifted(tag) 0UL
#define CLIDR_EL1_LoUIS GENMASK(23, 21)
#define CONFIG_CC_HAS_NO_PROFILE_FN_ATTR 1
#define ID_PFR0_EL1_State3_NI UL(0b0000)
#define ID_AA64MMFR2_EL1_IESB_MASK GENMASK(15, 12)
#define VM_SHADOW_STACK VM_NONE
#define ID_MMFR2_EL1_L1HvdRng GENMASK(11, 8)
#define xchg_release(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_release(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_xchg_release(__ai_ptr, __VA_ARGS__); })
#define CONFIG_NVMEM 1
#define list_first_entry_or_null(ptr,type,member) ({ struct list_head *head__ = (ptr); struct list_head *pos__ = READ_ONCE(head__->next); pos__ != head__ ? list_entry(pos__, type, member) : NULL; })
#define KUNIT_ASSERT_PTR_EQ_MSG(test,left,right,fmt,...) KUNIT_BINARY_PTR_ASSERTION(test, KUNIT_ASSERTION, left, ==, right, fmt, ##__VA_ARGS__)
#define ELF32_GNU_PROPERTY_ALIGN 4
#define ID_DFR1_EL1_MTPMU_IMPDEF UL(0b0000)
#define CONFIG_HAVE_ARCH_JUMP_LABEL 1
#define SYS_GCR_EL1_RRND (BIT(16))
#define __local_unlock_irq(lock) do { local_lock_release(this_cpu_ptr(lock)); local_irq_enable(); } while (0)
#define R_AARCH64_LDST128_ABS_LO12_NC 299
#define LRU_REFS_PGOFF (LRU_GEN_PGOFF - LRU_REFS_WIDTH)
#define cpu_all_mask to_cpumask(cpu_all_bits)
#define S_DT_MASK (S_IFMT >> S_DT_SHIFT)
#define HFGITR_EL2_SVC_EL0_MASK GENMASK(52, 52)
#define CONFIG_ARM_GIC_MAX_NR 1
#define VFSUIDT_INIT(val) (vfsuid_t){ __kuid_val(val) }
#define ETH_MODULE_MAX_I2C_ADDRESS 0x7f
#define ID_AA64SMFR0_EL1_B16F32_MASK GENMASK(34, 34)
#define KERNEL_HWCAP_SVEF64MM __khwcap2_feature(SVEF64MM)
#define ID_MMFR4_EL1_CnP_IMP UL(0b0001)
#define cap_raise(c,flag) ((c).val |= BIT_ULL(flag))
#define raw_local_irq_save(flags) do { typecheck(unsigned long, flags); flags = arch_local_irq_save(); } while (0)
#define SOCK_TYPE_MASK 0xf
#define __careful_clamp(val,lo,hi) ({ __builtin_choose_expr(__is_constexpr((val) - (lo) + (hi)), __clamp(val, lo, hi), __clamp_once(val, lo, hi, __UNIQUE_ID(__val), __UNIQUE_ID(__lo), __UNIQUE_ID(__hi))); })
#define DACR32_EL2_D11_SHIFT 22
#define ARM64_SVE 63
#define FICLONE _IOW(0x94, 9, int)
#define SIOCGIFSLAVE 0x8929
#define SIGTSTP 20
#define SYS_MVFR1_EL1_CRm 3
#define PREEMPT_LOCK_OFFSET PREEMPT_DISABLE_OFFSET
#define set_current_state(state_value) do { debug_normal_state_change((state_value)); smp_store_mb(current->__state, (state_value)); } while (0)
#define siginmask(sig,mask) ((sig) > 0 && (sig) < SIGRTMIN && (rt_sigmask(sig) & (mask)))
#define SSIZE_MAX ((ssize_t)(SIZE_MAX >> 1))
#define PRIO_PGRP 1
#define ID_AA64DFR0_EL1_HPMN0_MASK GENMASK(63, 60)
#define in_hardirq() (hardirq_count())
#define __LINUX_SPINLOCK_TYPES_RAW_H 
#define TIF_SVE 23
#define raw_cpu_generic_read(pcp) ({ *raw_cpu_ptr(&(pcp)); })
#define SEEK_CUR 1
#define SHF_RELA_LIVEPATCH 0x00100000
#define ID_AA64PFR0_EL1_GIC GENMASK(27, 24)
#define HZ_TO_MSEC_NUM 4
#define DACR32_EL2_D0_WIDTH 2
#define key_put(k) do { } while(0)
#define ID_AA64SMFR0_EL1_F32F32_NI UL(0b0)
#define DQF_ROOT_SQUASH (1 << DQF_ROOT_SQUASH_B)
#define __SPIN_LOCK_UNLOCKED(lockname) (spinlock_t) __SPIN_LOCK_INITIALIZER(lockname)
#define Q_XQUOTAOFF XQM_CMD(2)
#define CAP_NET_ADMIN 12
#define static_key_slow_dec_cpuslocked(key) static_key_slow_dec(key)
#define HFGITR_EL2_TLBIRVAALE1_WIDTH 1
#define ID_AA64MMFR1_EL1_nTLBPA_MASK GENMASK(51, 48)
#define IRQF_TIMER (__IRQF_TIMER | IRQF_NO_SUSPEND | IRQF_NO_THREAD)
#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
#define CPACR_ELx_FPEN_SHIFT 20
#define AARCH64_BREAKPOINT_EL0 2
#define AARCH64_BREAKPOINT_EL1 1
#define CONFIG_HAVE_ARM_SMCCC_DISCOVERY 1
#define COMPAT_PTRACE_GET_THREAD_AREA 22
#define LOCK_SH 1
#define ID_ISAR3_EL1_SIMD GENMASK(7, 4)
#define CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 1
#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
#define SO_OOBINLINE 10
#define _ASM_GENERIC_DIV64_H 
#define AT_CLKTCK 17
#define MDIO_AN_T1_LP_H 519
#define TCR_EL2_SH0_MASK TCR_SH0_MASK
#define CHECKSUM_COMPLETE 2
#define ETHTOOL_GSTRINGS 0x0000001b
#define TCR2_EL2_AMEC1_SHIFT 13
#define CPACR_ELx_TTA_WIDTH 1
#define SHM_INFO 14
#define SIGNAL_UNKILLABLE 0x00000040
#define HFGITR_EL2_DCCIVAC GENMASK(10, 10)
#define ID_ISAR3_EL1_TrueNOP_SHIFT 24
#define ID_AA64ISAR0_EL1_SHA1_IMP UL(0b0001)
#define __PAGE_ALIGNED_DATA .section ".data..page_aligned", "aw"
#define sched_annotate_sleep() do { } while (0)
#define num_possible_nodes() num_node_state(N_POSSIBLE)
#define MSG_EOF MSG_FIN
#define BMCR_FULLDPLX 0x0100
#define __lse_ll_sc_body(op,...) ({ alternative_has_cap_likely(ARM64_HAS_LSE_ATOMICS) ? __lse_ ##op(__VA_ARGS__) : __ll_sc_ ##op(__VA_ARGS__); })
#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
#define SCTLR_EL1_EnAS0_SHIFT 55
#define rbtree_postorder_for_each_entry_safe(pos,n,root,field) for (pos = rb_entry_safe(rb_first_postorder(root), typeof(*pos), field); pos && ({ n = rb_entry_safe(rb_next_postorder(&pos->field), typeof(*pos), field); 1; }); pos = n)
#define HPAGE_PMD_NR (1<<HPAGE_PMD_ORDER)
#define NR_IRQS_LEGACY 0
#define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
#define dev_level_ratelimited(dev_level,dev,fmt,...) do { static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); if (__ratelimit(&_rs)) dev_level(dev, fmt, ##__VA_ARGS__); } while (0)
#define PTR_ALIGN_DOWN(p,a) ((typeof(p))ALIGN_DOWN((unsigned long)(p), (a)))
#define ETH_MODULE_SFF_8636 0x3
#define MT_FLAGS_HEIGHT_OFFSET 0x02
#define SYS_ISR_EL1_CRn 12
#define __UAPI_DEF_IPX_ROUTE_DEFINITION 1
#define CTR_EL0_ERG_MASK GENMASK(23, 20)
#define ID_ISAR1_EL1_Endian_SHIFT 0
#define __wait_var_event_killable(var,condition) ___wait_var_event(var, condition, TASK_KILLABLE, 0, 0, schedule())
#define ID_MMFR3_EL1_CMaintVA_WIDTH 4
#define SYS_PIRE0_EL1_Op0 3
#define SYS_PIRE0_EL1_Op1 0
#define ID_AA64MMFR0_EL1_ASIDBITS_8 UL(0b0000)
#define R_AARCH64_MOVW_UABS_G0 263
#define ASSERT_EXCLUSIVE_WRITER_SCOPED(var) __ASSERT_EXCLUSIVE_SCOPED(var, KCSAN_ACCESS_ASSERT, __COUNTER__)
#define SYS_RGSR_EL1_SEED_MASK 0xffffUL
#define MOD_FREQUENCY ADJ_FREQUENCY
#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
#define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED)
#define __GFP_NOWARN ((__force gfp_t)___GFP_NOWARN)
#define FPE_FLTDIV 3
#define ID_AA64MMFR0_EL1_TGRAN16_2_52_BIT UL(0b0011)
#define HFGxTR_EL2_TPIDRRO_EL0 GENMASK(34, 34)
#define MAX_NICE 19
#define ID_AA64ISAR1_EL1_DPB_SHIFT 0
#define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
#define HFGxTR_EL2_DCZID_EL0_SHIFT 15
#define ID_PFR2_EL1_SSBS_WIDTH 4
#define ID_AA64MMFR0_EL1_ECV_MASK GENMASK(63, 60)
#define MAY_EXEC 0x00000001
#define PIRx_ELx_UNKN (UL(0))
#define ID_AA64PFR0_EL1_DIT_SHIFT 48
#define LSM_UNSAFE_PTRACE 2
#define STT_FILE 4
#define __cpu_to_le16s(x) do { (void)(x); } while (0)
#define ID_AA64ISAR2_EL1_APA3_MASK GENMASK(15, 12)
#define SYS_ID_AFR0_EL1_Op1 0
#define declare_get_random_var_wait(name,ret_type) static inline int get_random_ ## name ## _wait(ret_type *out) { int ret = wait_for_random_bytes(); if (unlikely(ret)) return ret; *out = get_random_ ## name(); return 0; }
#define MODULE_AUTHOR(_author) MODULE_INFO(author, _author)
#define LIST_POISON1 ((void *) 0x100 + POISON_POINTER_DELTA)
#define LIST_POISON2 ((void *) 0x122 + POISON_POINTER_DELTA)
#define ID_AA64MMFR0_EL1_SNSMEM_WIDTH 4
#define DACR32_EL2_D1_MASK GENMASK(3, 2)
#define netdev_notice_once(dev,fmt,...) netdev_level_once(KERN_NOTICE, dev, fmt, ##__VA_ARGS__)
#define ELFDATA2MSB 2
#define _LINUX_TIME64_H 
#define create_workqueue(name) alloc_workqueue("%s", __WQ_LEGACY | WQ_MEM_RECLAIM, 1, (name))
#define IPV6_PMTUDISC_OMIT 5
#define ID_MMFR3_EL1_CMemSz GENMASK(27, 24)
#define HFGITR_EL2_ICIVAU GENMASK(2, 2)
#define cmpxchg64(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_mb(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg64(__ai_ptr, __VA_ARGS__); })
#define CONFIG_TICK_CPU_ACCOUNTING 1
#define POLL_ERR 4
#define for_each_lru(lru) for (lru = 0; lru < NR_LRU_LISTS; lru++)
#define NT_S390_TODCMP 0x302
#define ETHER_FLOW 0x12
#define DIV_ROUND_DOWN_ULL(ll,d) ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
#define MSG_FASTOPEN 0x20000000
#define ID_AA64MMFR1_EL1_SpecSEI_NI UL(0b0000)
#define virt_mb() do { kcsan_mb(); __smp_mb(); } while (0)
#define __NR_kcmp 272
#define XA_MARK_LONGS DIV_ROUND_UP(XA_CHUNK_SIZE, BITS_PER_LONG)
#define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte))
#define ID_AA64MMFR3_EL1_ANERR_WIDTH 4
#define __PCPU_ATTRS(sec) __percpu __attribute__((section(PER_CPU_BASE_SECTION sec))) PER_CPU_ATTRIBUTES
#define OSLAR_EL1_OSLK_MASK GENMASK(0, 0)
#define NLMSG_SPACE(len) NLMSG_ALIGN(NLMSG_LENGTH(len))
#define MMF_DUMP_MASK_DEFAULT_ELF (1 << MMF_DUMP_ELF_HEADERS)
#define ID_AA64PFR0_EL1_CSV3_IMP UL(0b0001)
#define NOTIFY_STOP (NOTIFY_OK|NOTIFY_STOP_MASK)
#define HFGITR_EL2_nGCSPUSHM_EL1_MASK GENMASK(57, 57)
#define _PAGE_KERNEL_RO ((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
#define INITIAL_JIFFIES ((unsigned long)(unsigned int) (-300*HZ))
#define HDFGRTR_EL2_PMSEVFR_EL1_SHIFT 27
#define ID_AA64ISAR1_EL1_SPECRES_MASK GENMASK(43, 40)
#define debug_rtlock_wait_restore_state() do { } while (0)
#define QC_WARNS_MASK (QC_SPC_WARNS | QC_INO_WARNS | QC_RT_SPC_WARNS)
#define ID_AA64PFR1_EL1_NMI_IMP UL(0b0001)
#define ID_ISAR2_EL1_MultiAccessInt_WIDTH 4
#define HDFGWTR_EL2_RES0 (UL(0) | GENMASK_ULL(63, 63) | GENMASK_ULL(59, 58) | GENMASK_ULL(51, 51) | GENMASK_ULL(47, 47) | GENMASK_ULL(43, 43) | GENMASK_ULL(40, 38) | GENMASK_ULL(34, 34) | GENMASK_ULL(30, 30) | GENMASK_ULL(22, 22) | GENMASK_ULL(9, 9) | GENMASK_ULL(6, 6))
#define xa_lock_irqsave_nested(xa,flags,subclass) spin_lock_irqsave_nested(&(xa)->xa_lock, flags, subclass)
#define PMSIDR_EL1_INTERVAL_768 UL(0b0011)
#define FTRACE_PLT_IDX 0
#define HFGxTR_EL2_nAMAIR2_EL1_MASK GENMASK(63, 63)
#define SHM_STAT_ANY 15
#define __DEFINE_LOCK_GUARD_0(_name,_lock) static inline class_ ##_name ##_t class_ ##_name ##_constructor(void) { class_ ##_name ##_t _t = { .lock = (void*)1 }, *_T __maybe_unused = &_t; _lock; return _t; }
#define __DEFINE_LOCK_GUARD_1(_name,_type,_lock) static inline class_ ##_name ##_t class_ ##_name ##_constructor(_type *l) { class_ ##_name ##_t _t = { .lock = l }, *_T = &_t; _lock; return _t; }
#define ID_AA64MMFR1_EL1_AFP_NI UL(0b0000)
#define HDFGRTR_EL2_nBRBDATA_SHIFT 61
#define current_cred_xxx(xxx) ({ current_cred()->xxx; })
#define SYS_SCTLR_EL1_CRm 0
#define F_GETPIPE_SZ (F_LINUX_SPECIFIC_BASE + 8)
#define DEFINE_PER_CPU_DECRYPTED(type,name) DEFINE_PER_CPU(type, name)
#define ATTR_MODE (1 << 0)
#define MVFR1_EL1_FPDNaN_MASK GENMASK(7, 4)
#define SCTLR_EL1_DZE_SHIFT 14
#define ID_PFR1_EL1_Sec_frac_MASK GENMASK(23, 20)
#define SMPRIMAP_EL2_P15_SHIFT 60
#define ETH_P_ECONET 0x0018
#define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2)
#define DCACHE_OP_WEAK_REVALIDATE 0x00000800
#define SYSTEM_SLEEP_PM_OPS(suspend_fn,resume_fn) .suspend = pm_sleep_ptr(suspend_fn), .resume = pm_sleep_ptr(resume_fn), .freeze = pm_sleep_ptr(suspend_fn), .thaw = pm_sleep_ptr(resume_fn), .poweroff = pm_sleep_ptr(suspend_fn), .restore = pm_sleep_ptr(resume_fn),
#define pr_notice_once(fmt,...) printk_once(KERN_NOTICE pr_fmt(fmt), ##__VA_ARGS__)
#define GFP_ATOMIC (__GFP_HIGH|__GFP_KSWAPD_RECLAIM)
#define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
#define ID_MMFR3_EL1_CMaintVA_NI UL(0b0000)
#define HFGxTR_EL2_ICC_IGRPENn_EL1_SHIFT 39
#define VM_STACK_EARLY 0
#define SIOCBRDELIF 0x89a3
#define CONFIG_I2C_CHARDEV 1
#define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM
#define __compiletime_assert(condition,msg,prefix,suffix) do { __noreturn extern void prefix ## suffix(void) __compiletime_error(msg); if (!(condition)) prefix ## suffix(); } while (0)
#define FMODE_PATH ((__force fmode_t)0x4000)
#define static_key_enabled(x) ({ if (!__builtin_types_compatible_p(typeof(*x), struct static_key) && !__builtin_types_compatible_p(typeof(*x), struct static_key_true) && !__builtin_types_compatible_p(typeof(*x), struct static_key_false)) ____wrong_branch_error(); static_key_count((struct static_key *)x) > 0; })
#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
#define EM_TILEPRO 188
#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
#define PAGECACHE_TAG_WRITEBACK XA_MARK_1
#define SMPRIMAP_EL2_F9_SHIFT 36
#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
#define ARM64_VTTBR_X(ipa,levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
#define CONFIG_XILINX_DMA 1
#define MSG_SENDPAGE_DECRYPTED 0x100000
#define _LINUX_BITOPS_H 
#define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT)
#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
#define MSGSND 11
#define RLIM_INFINITY (~0UL)
#define NETIF_F_HW_TLS_TX __NETIF_F(HW_TLS_TX)
#define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
#define SOL_MPTCP 284
#define JOBCTL_STOP_SIGMASK 0xffff
#define SCTLR_EL1_EnRCTX_WIDTH 1
#define LED_FUNCTION_CHARGING "charging"
#define set_numa_node(node) 
#define SYS_ICC_NMIAR1_EL1_CRm 9
#define SYS_ICC_NMIAR1_EL1_CRn 12
#define NT_S390_CTRS 0x304
#define KERNEL_HWCAP_SHA1 __khwcap_feature(SHA1)
#define KERNEL_HWCAP_SHA2 __khwcap_feature(SHA2)
#define KERNEL_HWCAP_SHA3 __khwcap_feature(SHA3)
#define VALID_RESOLVE_FLAGS (RESOLVE_NO_XDEV | RESOLVE_NO_MAGICLINKS | RESOLVE_NO_SYMLINKS | RESOLVE_BENEATH | RESOLVE_IN_ROOT | RESOLVE_CACHED)
#define REG_LORN_EL1 S3_0_C10_C4_2
#define ID_AA64MMFR1_EL1_TWED_IMP UL(0b0001)
#define SKB_ALLOC_NAPI 0x04
#define printk_once(fmt,...) DO_ONCE_LITE(printk, fmt, ##__VA_ARGS__)
#define CONFIG_GENERIC_EARLY_IOREMAP 1
#define rcu_dereference_check(p,c) __rcu_dereference_check((p), __UNIQUE_ID(rcu), (c) || rcu_read_lock_held(), __rcu)
#define HDFGWTR_EL2_PMBSR_EL1_WIDTH 1
#define LRU_GEN_WIDTH 0
#define ARM64_CPUCAP_SCOPE_MASK (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_SCOPE_BOOT_CPU)
#define cmpxchg_release(ptr,...) ({ typeof(ptr) __ai_ptr = (ptr); kcsan_release(); instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); raw_cmpxchg_release(__ai_ptr, __VA_ARGS__); })
#define _LINUX_RBTREE_TYPES_H 
#define MDIO_AN_THP_BP2_5GT 0x0008
#define AT_SECURE 23
#define MAX_FDT_SIZE SZ_2M
#define __NR_linkat 37
#define ECHILD 10
#define in_dbg_master() (0)
#define MDIO_MMD_PMAPMD 1
#define SIGNAL_STOP_CONTINUED 0x00000002
#define ID_AA64ISAR1_EL1_APA_WIDTH 4
#define ID_MMFR1_EL1_L1Hvd_SHIFT 16
#define __printk_index_emit(...) do {} while (0)
#define MDIO_PCS_EEE_ABLE2 21
#define __NR_times 153
#define SIG_KERNEL_ONLY_MASK ( rt_sigmask(SIGKILL) | rt_sigmask(SIGSTOP))
#define FS_EOFBLOCKS_FL 0x00400000
#define PAGE_MAPPING_KSM (PAGE_MAPPING_ANON | PAGE_MAPPING_MOVABLE)
#define SOFTIRQ_MASK (__IRQ_MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT)
#define IS_MAX_ORDER_ALIGNED(pfn) IS_ALIGNED(pfn, MAX_ORDER_NR_PAGES)
#define flowi4_flags __fl_common.flowic_flags
#define SCTLR_EL1_SED_MASK GENMASK(8, 8)
#define __overloadable 
#define SB_I_STABLE_WRITES 0x00000008
#define IS_PRIVATE(inode) ((inode)->i_flags & S_PRIVATE)
#define _LINUX_KERNEL_READ_FILE_H 
#define MVFR0_EL1_FPSqrt_IMP UL(0b0001)
#define SHT_REL 9
#define SYS_ID_AA64PFR1_EL1_CRm 4
#define SYS_ID_AA64PFR1_EL1_CRn 0
#define dma_unmap_len_set(PTR,LEN_NAME,VAL) (((PTR)->LEN_NAME) = (VAL))
#define ID_MMFR4_EL1_AC2_IMP UL(0b0001)
#define CONFIG_NET 1
#define HDFGRTR_EL2_TRCCLAIM_MASK GENMASK(36, 36)
#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
#define nodes_addr(src) ((src).bits)
#define HFGxTR_EL2_nPOR_EL0_MASK GENMASK(59, 59)
#define IPV6_PRIORITY_11 0x0b00
#define FIELD_GET(_mask,_reg) ({ __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); })
#define CONFIG_TREE_RCU 1
#define _KUNIT_RESOURCE_H 
#define __this_cpu_xchg(pcp,nval) ({ __this_cpu_preempt_check("xchg"); raw_cpu_xchg(pcp, nval); })
#define CAP_LEASE 28
#define SDF_NEEDS_GROUPS 0x4
#define LORN_EL1_Num_WIDTH 8
#define cpu_to_le32p __cpu_to_le32p
#define cpu_to_le32s __cpu_to_le32s
#define ETHTOOL_RESET 0x00000034
#define PR_SET_MM_MAP 14
#define __assume_aligned(a,...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
#define PMBIDR_EL1_P_MASK GENMASK(4, 4)
#define i_size_ordered_init(inode) do { } while (0)
#define TESTSETFLAG_FALSE(uname,lname) static inline bool folio_test_set_ ##lname(struct folio *folio) { return 0; } static inline int TestSetPage ##uname(struct page *page) { return 0; }
#define list_for_each_entry_srcu(pos,head,member,cond) for (__list_check_srcu(cond), pos = list_entry_rcu((head)->next, typeof(*pos), member); &pos->member != (head); pos = list_entry_rcu(pos->member.next, typeof(*pos), member))
#define __GFP_HARDWALL ((__force gfp_t)___GFP_HARDWALL)
#define TCR2_EL2_PIE_WIDTH 1
#define INIT_RCU_WORK(_work,_func) INIT_WORK(&(_work)->work, (_func))
#define CONFIG_CMA_AREAS 7
#define _pcp_protect_return(op,pcp,args...) ({ typeof(pcp) __retval; preempt_disable_notrace(); __retval = (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args); preempt_enable_notrace(); __retval; })
#define PACKET_STATISTICS 6
#define SA_RESETHAND 0x80000000
#define ISR_EL1_I_SHIFT 7
#define flowi_secid u.__fl_common.flowic_secid
#define HDFGRTR_EL2_TRCCLAIM GENMASK(36, 36)
#define ID_AA64ISAR1_EL1_LS64 GENMASK(63, 60)
#define UIO_FASTIOV 8
#define _LINUX_SYSCTL_H 
#define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
#define __NR_sync 81
#define IOPRIO_NR_HINTS (1 << IOPRIO_HINT_NR_BITS)
#define ID_AA64PFR1_EL1_DF2_WIDTH 4
#define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
#define __phys_to_pte_val(phys) (phys)
#define CONFIG_PCIEASPM 1
#define pr_cont(fmt,...) printk(KERN_CONT fmt, ##__VA_ARGS__)
#define writeq_relaxed writeq_relaxed
#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
#define CONFIG_CC_HAS_SIGN_RETURN_ADDRESS 1
#define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
#define SECCOMP_FILTER_FLAG_TSYNC_ESRCH (1UL << 4)
#define xa_unlock_irq(xa) spin_unlock_irq(&(xa)->xa_lock)
#define PREEMPT_BITS 8
#define SYS_ID_AA64ISAR0_EL1_CRm 6
#define LED_FUNCTION_PANIC "panic"
#define SEMTIMEDOP 4
#define ID_ISAR4_EL1_PSR_M_WIDTH 4
#define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
#define ID_MMFR5_EL1_ETS_NI UL(0b0000)
#define LED_COLOR_ID_AMBER 4
#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
#define MNT_DOOMED 0x1000000
#define MIDR_IMPLEMENTOR(midr) (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
#define REG_SCXTNUM_EL1 S3_0_C13_C0_7
#define __NR_setsockopt 208
#define CONFIG_AS_HAS_SHA3 1
#define __ASM_ATOMIC_H 
#define instrumentation_begin() do { } while(0)
#define arch_spin_trylock(l) queued_spin_trylock(l)
#define unrcu_pointer(p) __unrcu_pointer(p, __UNIQUE_ID(rcu))
#define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0)
#define ID_ISAR5_EL1_VCMA_SIGNED false
#define HDFGRTR_EL2_PMEVCNTRn_EL0_WIDTH 1
#define pr_fmt(fmt) fmt
#define BUGFLAG_DONE (1 << 2)
#define HFGITR_EL2_TLBIRVAALE1IS GENMASK(37, 37)
#define __ALIGN_MASK(x,mask) __ALIGN_KERNEL_MASK((x), (mask))
#define ID_PFR2_EL1_UNKN (UL(0))
#define LOCAL_SPIN_DEP_MAP_INIT(lockname) .dep_map = { .name = #lockname, .wait_type_inner = LD_WAIT_CONFIG, .lock_type = LD_LOCK_PERCPU, }
#define PMSIDR_EL1_INTERVAL_WIDTH 4
#define HFGxTR_EL2_APDAKey_MASK GENMASK(4, 4)
#define KASAN_TAG_PGSHIFT (KASAN_TAG_PGOFF * (KASAN_TAG_WIDTH != 0))
#define PMSIDR_EL1_ARCHINST_WIDTH 1
#define ID_MMFR0_EL1_PMSA GENMASK(7, 4)
#define DQUOT_INIT_REWRITE max(V1_INIT_REWRITE, V2_INIT_REWRITE)
#define FLOW_KEYS_HASH_START_FIELD basic
#define ID_ISAR1_EL1_Endian_MASK GENMASK(3, 0)
#define __NR_get_robust_list 100
#define ID_AA64MMFR3_EL1_SDERR_FEAT_ADERR UL(0b0010)
#define MSG_MORE 0x8000
#define VM_INIT_DEF_MASK VM_NOHUGEPAGE
#define MNT_RELATIME 0x20
#define CONFIG_QUEUED_SPINLOCKS 1
#define IS_BUILTIN(option) __is_defined(option)
#define ID_AA64DFR0_EL1_WRPs_SHIFT 20
#define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT)
#define HDFGRTR_EL2_PMINTEN_SHIFT 17
#define ID_ISAR5_EL1_RDM_MASK GENMASK(27, 24)
#define MDIO_PRTAD_NONE (-1)
#define _LINUX_SCHED_IDLE_H 
#define SYS_LORID_EL1_CRm 4
#define SYS_LORID_EL1_CRn 10
#define CONFIG_WIRELESS 1
#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL }
#define _LINUX_CONST_H 
#define hlist_for_each_entry_rcu_notrace(pos,head,member) for (pos = hlist_entry_safe(rcu_dereference_raw_check(hlist_first_rcu(head)), typeof(*(pos)), member); pos; pos = hlist_entry_safe(rcu_dereference_raw_check(hlist_next_rcu( &(pos)->member)), typeof(*(pos)), member))
#define SUPPORTED_56000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseSR4_Full)
#define EARLY_KASLR (0)
#define MVFR0_EL1_SIMDReg GENMASK(3, 0)
#define SHM_STAT 13
#define LORN_EL1_Num_MASK GENMASK(7, 0)
#define JOBCTL_TRACED_BIT 27
#define MVFR1_EL1_SIMDHP_SIGNED false
#define GIC_PRIO_IRQON 0xe0
#define __same_type(a,b) __builtin_types_compatible_p(typeof(a), typeof(b))
#define NLM_F_MULTI 0x02
#define I2C_MODULE_PREFIX "i2c:"
#define CONFIG_DRM_PANEL 1
#define ID_AA64PFR0_EL1_GIC_NI UL(0b0000)
#define pgd_access_permitted(pgd,write) (pgd_present(pgd) && (!(write) || pgd_write(pgd)))
#define CUT_HERE "------------[ cut here ]------------\n"
#define F_ADD_SEALS (F_LINUX_SPECIFIC_BASE + 9)
#define HFGxTR_EL2_SCXTNUM_EL0_MASK GENMASK(31, 31)
#define PTRACE_SETOPTIONS 0x4200
#define MASTER_SLAVE_CFG_SLAVE_PREFERRED 3
#define HDFGWTR_EL2_OSLAR_EL1_MASK GENMASK(8, 8)
#define param_check_long(name,p) __param_check(name, p, long)
#define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
#define KERNEL_HWCAP_FCMA __khwcap_feature(FCMA)
#define BUGFLAG_NO_CUT_HERE (1 << 3)
#define SECCOMP_IOR(nr,type) _IOR(SECCOMP_IOC_MAGIC, nr, type)
#define FS_XFLAG_REALTIME 0x00000001
#define SYS_HDFGWTR_EL2_CRm 1
#define SYS_HDFGWTR_EL2_CRn 3
#define IS_SYNC(inode) (__IS_FLG(inode, SB_SYNCHRONOUS) || ((inode)->i_flags & S_SYNC))
#define HFGITR_EL2_TLBIVAALE1OS_SHIFT 23
#define PFA_NO_NEW_PRIVS 0
#define for_each_set_bitrange(b,e,addr,size) for ((b) = 0; (b) = find_next_bit((addr), (size), b), (e) = find_next_zero_bit((addr), (size), (b) + 1), (b) < (size); (b) = (e) + 1)
#define FS_QUOTA_PDQ_ENFD (1<<5)
#define INIT_DEFERRABLE_WORK(_work,_func) __INIT_DELAYED_WORK(_work, _func, TIMER_DEFERRABLE)
#define TRBSR_EL1_MSS2_MASK GENMASK(55, 32)
#define STA_PLL 0x0001
#define ADVERTISE_RESV 0x1000
#define ADVERTISE_SGMII 0x0001
#define SMPRIMAP_EL2_UNKN (UL(0))
#define PP_SIGNATURE (0x40 + POISON_POINTER_DELTA)
#define STATX_GID 0x00000010U
#define ALLOC_SPLIT_PTLOCKS (SPINLOCK_SIZE > BITS_PER_LONG/8)
#define NLM_F_DUMP_INTR 0x10
#define ID_PFR0_EL1_State2_CV UL(0b0010)
#define PMBLIMITR_EL1_E_SHIFT 0
#define SCTLR_EL1_I GENMASK(12, 12)
#define ARM64_HAS_VIRT_HOST_EXTN 47
#define SCTLR_EL1_M GENMASK(0, 0)
#define HFGxTR_EL2_nSMPRI_EL1 GENMASK(54, 54)
#define SIG_SPECIFIC_SICODES_MASK ( rt_sigmask(SIGILL) | rt_sigmask(SIGFPE) | rt_sigmask(SIGSEGV) | rt_sigmask(SIGBUS) | rt_sigmask(SIGTRAP) | rt_sigmask(SIGCHLD) | rt_sigmask(SIGPOLL) | rt_sigmask(SIGSYS) | SIGEMT_MASK )
#define INVALID_HWIRQ (~0UL)
#define ARM64_WORKAROUND_843419 66
#define __NR3264_truncate 45
#define IFF_POINTOPOINT IFF_POINTOPOINT
#define PR_GET_UNALIGN 5
#define compat_sp_irq regs[17]
#define DCACHE_DENTRY_CURSOR 0x20000000
#define HARDIRQ_BITS 4
#define ID_AA64MMFR2_EL1_VARange GENMASK(19, 16)
#define HFGxTR_EL2_nAMAIR2_EL1 GENMASK(63, 63)
#define RLIMIT_CPU 0
#define TRBMAR_EL1_SH_INNER_SHAREABLE UL(0b11)
#define SIPHASH_CONST_0 0x736f6d6570736575ULL
#define __ASM_GENERIC_HARDIRQ_H 
#define KTIME_MONOTONIC_RES KTIME_LOW_RES
#define CAP_BLOCK_SUSPEND 36
#define HFGxTR_EL2_ERXMISCn_EL1_MASK GENMASK(45, 45)
#define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020
#define ID_AA64AFR0_EL1_IMPDEF7_WIDTH 4
#define dev_err(dev,fmt,...) dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
#define sys_insn sys_reg
#define _DEVICE_CLASS_H_ 
#define INIT_DELAYED_WORK(_work,_func) __INIT_DELAYED_WORK(_work, _func, 0)
#define VTCR_EL2_LVLS(vtcr) VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
#define HDFGRTR_EL2_OSLSR_EL1_WIDTH 1
#define CONFIG_ARCH_MMAP_RND_BITS_MIN 18
#define MIDR_VARIANT(midr) (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
#define LOCK_STATE_UNKNOWN -1
#define REG_CLIDR_EL1 S3_1_C0_C0_1
#define ID_MMFR4_EL1_CnP_MASK GENMASK(15, 12)
#define ID_AA64MMFR1_EL1_TIDCP1_MASK GENMASK(55, 52)
#define __RCU_SYNC_INITIALIZER(name) { .gp_state = 0, .gp_count = 0, .gp_wait = __WAIT_QUEUE_HEAD_INITIALIZER(name.gp_wait), }
#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
#define ID_AA64ISAR2_EL1_MOPS_SHIFT 16
#define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
#define __GFP_SKIP_KASAN ((__force gfp_t)___GFP_SKIP_KASAN)
#define DT_JMPREL 23
#define NETLINK_SELINUX 7
#define SKB_DATA_ALIGN(X) ALIGN(X, SMP_CACHE_BYTES)
#define MDIO_EEE_1000KX 0x0010
#define NETIF_F_GSO_IPXIP4 __NETIF_F(GSO_IPXIP4)
#define CONFIG_EXT4_FS 1
#define ID_AA64SMFR0_EL1_I8I32_WIDTH 4
#define IPV6_PMTUDISC_DONT 0
#define HFGITR_EL2_TLBIRVAALE1OS GENMASK(27, 27)
#define SYS_SMPRI_EL1 sys_reg(3, 0, 1, 2, 4)
#define ESR_ELx_SYS64_ISS_RT_SHIFT 5
#define SCTLR_EL1_EnDA GENMASK(27, 27)
#define SCTLR_EL1_EnDB GENMASK(13, 13)
#define DCZID_EL0_BS_WIDTH 4
#define NR_KERNFS_LOCK_BITS (2 * (ilog2(NR_CPUS < 32 ? NR_CPUS : 32)))
#define wake_up_interruptible_sync_poll(x,m) __wake_up_sync_key((x), TASK_INTERRUPTIBLE, poll_to_key(m))
#define ZT_SIG_REG_SIZE 512
#define ID_AA64PFR0_EL1_CSV2_CSV2_2 UL(0b0010)
#define ID_AA64PFR0_EL1_CSV2_CSV2_3 UL(0b0011)
#define LINUX_HARDIRQ_H 
#define __EXPORTED_HEADERS__ 
#define LOCK_CONTENDED_RETURN(_lock,try,lock) lock(_lock)
#define ESR_ELx_AET_SHIFT (10)
#define SA_UNSUPPORTED 0x00000400
#define __SRCU_STRUCT_INIT_MODULE(name,usage_name) { __SRCU_STRUCT_INIT_COMMON(name, usage_name) }
#define NETIF_F_TSO_ECN __NETIF_F(TSO_ECN)
#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 94
#define RED_INACTIVE 0x09F911029D74E35BULL
#define CONFIG_MMU_LAZY_TLB_REFCOUNT 1
#define ftrace_set_early_filter(ops,buf,enable) do { } while (0)
#define ID_AA64PFR1_EL1_MPAM_frac_MINOR_1 UL(0b0001)
#define this_cpu_cmpxchg128(pcp,o,n) ({ typedef typeof(pcp) pcp_op_T__; u128 old__, new__, ret__; pcp_op_T__ *ptr__; old__ = o; new__ = n; preempt_disable_notrace(); ptr__ = raw_cpu_ptr(&(pcp)); ret__ = cmpxchg128_local((void *)ptr__, old__, new__); preempt_enable_notrace(); ret__; })
#define CSSELR_EL1_InD_WIDTH 1
#define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
#define HFGxTR_EL2_nMAIR2_EL1_MASK GENMASK(62, 62)
#define MVFR0_EL1_SIMDReg_IMP_16x64 UL(0b0001)
#define DT_SYMBOLIC 16
#define SYSCTL_ONE_HUNDRED ((void *)&sysctl_vals[5])
#define PUD_TABLE_UXN (_AT(pudval_t, 1) << 60)
#define STATX_MTIME 0x00000040U
#define user_read_access_begin user_access_begin
#define sysfs_bin_attr_init(bin_attr) sysfs_attr_init(&(bin_attr)->attr)
#define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 64)
#define MCOUNT_INSN_SIZE AARCH64_INSN_SIZE
#define _UAPI_LINUX_SIGNAL_H 
#define ID_AA64PFR1_EL1_DF2_MASK GENMASK(59, 56)
#define SCTLR_EL1_UMA_SHIFT 9
#define ID_AA64DFR0_EL1_TraceVer_MASK GENMASK(7, 4)
#define KERNEL_HWCAP_FP __khwcap_feature(FP)
#define HFGITR_EL2_ATS1E1R_WIDTH 1
#define CONFIG_WLAN_VENDOR_ZYDAS 1
#define REG_PMSFCR_EL1 S3_0_C9_C9_4
#define PF_X25 AF_X25
#define PR_SVE_VL_LEN_MASK 0xffff
#define CONFIG_ARCH_SUPPORTS_ATOMIC_RMW 1
#define CONFIG_POSIX_TIMERS 1
#define MAXQUOTAS 3
#define CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK 1
#define VM_DONTDUMP 0x04000000
#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
#define PF_MCTP AF_MCTP
#define raw_cpu_dec(pcp) raw_cpu_sub(pcp, 1)
#define noinstr __noinstr_section(".noinstr.text")
#define APPLE_CPU_PART_M2_BLIZZARD 0x032
#define POISON_POINTER_DELTA _AC(CONFIG_ILLEGAL_POINTER_VALUE, UL)
#define __virt_to_phys_nodebug(x) ({ phys_addr_t __x = (phys_addr_t)(__tag_reset(x)); __is_lm_address(__x) ? __lm_to_phys(__x) : __kimg_to_phys(__x); })
#define PACKET_FANOUT_HASH 0
#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001
#define TAINT_FLAGS_MAX ((1UL << TAINT_FLAGS_COUNT) - 1)
#define ID_ISAR0_EL1_Coproc_MRC2 UL(0b0010)
#define CPUCLOCK_PROF 0
#define ARM_CPU_IMP_NVIDIA 0x4E
#define TCR2_EL2_DisCH1_MASK GENMASK(15, 15)
#define TRBSR_EL1_S_MASK GENMASK(17, 17)
#define SO_PASSSEC 34
#define SIOCATMARK 0x8905
#define SYS_ID_MMFR0_EL1_CRm 1
#define __NR_madvise 233
#define ID_AA64PFR1_EL1_MTEX_SIGNED false
#define dbg_late_init() 
#define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5
#define MAY_NOT_BLOCK 0x00000080
#define _LINUX_RV_H 
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
#define PTRACE_O_TRACESYSGOOD 1
#define ID_AA64ISAR1_EL1_DPB GENMASK(3, 0)
#define VFS_CAP_FLAGS_EFFECTIVE 0x000001
#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
#define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
#define EBADHANDLE 521
#define HFGITR_EL2_ICIVAU_SHIFT 2
#define MII_MMD_CTRL_ADDR 0x0000
#define ID_ISAR0_EL1_Swap GENMASK(3, 0)
#define TAINT_DIE 7
#define IF_PROTO_HDLC 0x2000
#define SEMMSL 32000
#define CONFIG_VIDEO_NOMODESET 1
#define SCTLR_ELx_C (BIT(2))
#define _pcp_protect(op,pcp,...) ({ preempt_disable_notrace(); op(raw_cpu_ptr(&(pcp)), __VA_ARGS__); preempt_enable_notrace(); })
#define UMH_WAIT_PROC 0x02
#define PR_SET_MM_END_CODE 2
#define CONFIG_BLK_DEV_INITRD 1
#define __LINUX_SECURITY_H 
#define rcu_dereference_sched_check(p,c) __rcu_dereference_check((p), __UNIQUE_ID(rcu), (c) || rcu_read_lock_sched_held(), __rcu)
#define ID_AA64ZFR0_EL1_SHA3_WIDTH 4
#define SCTLR_EL1_EnIA GENMASK(31, 31)
#define SCTLR_EL1_EnIB GENMASK(30, 30)
#define ID_ISAR1_EL1_IfThen_NI UL(0b0000)
#define PF_BRIDGE AF_BRIDGE
#define __preserve_most 
#define EXIT_DEAD 0x00000010
#define PR_SET_SPECULATION_CTRL 53
#define F_SHLCK 8
#define ioread8_rep ioread8_rep
#define ID_ISAR4_EL1_WithShifts GENMASK(7, 4)
#define rounddown_pow_of_two(n) ( __builtin_constant_p(n) ? ( (1UL << ilog2(n))) : __rounddown_pow_of_two(n) )
#define writesb writesb
#define ID_AA64MMFR1_EL1_ECBHB GENMASK(63, 60)
#define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
#define NL_SET_ERR_ATTR_MISS(extack,nest,type) do { struct netlink_ext_ack *__extack = (extack); if (__extack) { __extack->miss_nest = (nest); __extack->miss_type = (type); } } while (0)
#define CPACR_ELx_ZEN GENMASK(17, 16)
#define HDFGRTR_EL2_PMBLIMITR_EL1_WIDTH 1
#define PF_NOFREEZE 0x00008000
#define wait_event_idle(wq_head,condition) do { might_sleep(); if (!(condition)) ___wait_event(wq_head, condition, TASK_IDLE, 0, 0, schedule()); } while (0)
#define WNOHANG 0x00000001
#define PMSCR_EL2_E0HSPE GENMASK(0, 0)
#define PACKET_TX_HAS_OFF 19
#define HDFGRTR_EL2_PMBPTR_EL1_SHIFT 24
#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
#define for_each_possible_cpu(cpu) for_each_cpu((cpu), cpu_possible_mask)
#define PMSG_AUTO_RESUME ((struct pm_message) { .event = PM_EVENT_AUTO_RESUME, })
#define CONFIG_CMA 1
#define ID_AA64ISAR0_EL1_SHA3_MASK GENMASK(35, 32)
#define PF_IPX AF_IPX
#define LED_COLOR_ID_IR 7
#define PAGES_PER_SUBSECTION (1UL << PFN_SUBSECTION_SHIFT)
#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive
#define LPA_NPAGE 0x8000
#define _DPRINTK_FLAGS_NONE 0
#define R_AARCH64_CONDBR19 280
#define ENOCSI 50
#define ID_AA64PFR0_EL1_FP_NI UL(0b1111)
#define HCRX_EL2_VINMI GENMASK(7, 7)
#define CONFIG_RCU_CPU_STALL_TIMEOUT 21
#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
#define TESTPAGEFLAG(uname,lname,policy) static __always_inline bool folio_test_ ##lname(struct folio *folio) { return test_bit(PG_ ##lname, folio_flags(folio, FOLIO_ ##policy)); } static __always_inline int Page ##uname(struct page *page) { return test_bit(PG_ ##lname, &policy(page, 0)->flags); }
#define LATCH ((CLOCK_TICK_RATE + HZ/2) / HZ)
#define ID_AA64ISAR0_EL1_SM4_NI UL(0b0000)
#define PMBIDR_EL1_F_SHIFT 5
#define _LINUX_MMAP_LOCK_H 
#define HWCAP2_SVEAES (1 << 2)
#define HWCAP2_LRCPC3 (1UL << 46)
#define ID_AA64ISAR0_EL1_SHA2_WIDTH 4
#define PR_FP_MODE_FRE (1 << 1)
#define MDSCR_EL1_TXfull GENMASK(29, 29)
#define ID_AA64MMFR3_EL1_ADERR_FEAT_ADERR_IND UL(0b0011)
#define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE)
#define IPV6_FLOW 0x11
#define _UAPI_LINUX_IOPRIO_H 
#define LOGLEVEL_ERR 3
#define ptdesc_folio(pt) (_Generic((pt), const struct ptdesc *: (const struct folio *)(pt), struct ptdesc *: (struct folio *)(pt)))
#define SO_TIMESTAMPNS_OLD 35
#define F_GETFL 3
#define netif_vdbg(priv,type,dev,format,args...) ({ if (0) netif_printk(priv, type, KERN_DEBUG, dev, format, ##args); 0; })
#define sched_preempt_enable_no_resched() do { barrier(); preempt_count_dec(); } while (0)
#define ID_AA64MMFR2_EL1_CCIDX_MASK GENMASK(23, 20)
#define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3)
#define __NR_open_tree 428
#define HFGxTR_EL2_ERXADDR_EL1_MASK GENMASK(49, 49)
#define list_tail_rcu(head) (*((struct list_head __rcu **)(&(head)->prev)))
#define PMSICR_EL1_RES1 (UL(0))
#define ID_AA64ISAR1_EL1_FRINTTS_SIGNED false
#define TCR2_EL2_AMEC1_MASK GENMASK(13, 13)
#define ID_PFR0_EL1_State0_MASK GENMASK(3, 0)
#define list_for_each_entry_safe_continue(pos,n,head,member) for (pos = list_next_entry(pos, member), n = list_next_entry(pos, member); !list_entry_is_head(pos, head, member); pos = n, n = list_next_entry(n, member))
#define HFGITR_EL2_DCIVAC_WIDTH 1
#define ID_AA64ZFR0_EL1_I8MM_WIDTH 4
#define __pa(x) __virt_to_phys((unsigned long)(x))
#define _LINUX_NET_TIMESTAMPING_H_ 
#define BITS_PER_COMPAT_LONG (8*sizeof(compat_long_t))
#define AT_SYSINFO_EHDR 33
#define PMSCR_EL1_UNKN (UL(0))
#define ARM64_HAS_FGT 23
#define __noscs 
#define __NR_process_vm_writev 271
#define PMSIDR_EL1_INTERVAL_1024 UL(0b0100)
#define CLIDR_EL1_Ctype4_WIDTH 3
#define TPIDR_EL1_ThreadID GENMASK(63, 0)
#define __ASM_PREEMPT_H 
#define HFGxTR_EL2_DCZID_EL0 GENMASK(15, 15)
#define __visible __attribute__((__externally_visible__))
#define SKBTX_ANY_SW_TSTAMP (SKBTX_SW_TSTAMP | SKBTX_SCHED_TSTAMP)
#define HFGxTR_EL2_nGCS_EL1_SHIFT 53
#define ID_AA64ISAR1_EL1_XS_SIGNED false
#define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
#define TICK_USEC ((USEC_PER_SEC + HZ/2) / HZ)
#define IPPROTO_MH 135
#define ptep_clear_young_notify ptep_test_and_clear_young
#define PER_CPU_FIRST_SECTION "..first"
#define DEFINE_FLEX(type,name,member,count) _DEFINE_FLEX(type, name, member, count, = {})
#define xas_unlock_bh(xas) xa_unlock_bh((xas)->xa)
#define HFGxTR_EL2_FAR_EL1_MASK GENMASK(17, 17)
#define __LINUX_NODEMASK_H 
#define ptep_modify_prot_commit ptep_modify_prot_commit
#define __GFP_ZERO ((__force gfp_t)___GFP_ZERO)
#define KERNEL_HWCAP_I8MM __khwcap2_feature(I8MM)
#define ELF_EXEC_PAGESIZE PAGE_SIZE
#define PTRACE_SYSCALL_INFO_SECCOMP 3
#define ID_AA64SMFR0_EL1_FA64_WIDTH 1
#define PFA_SPREAD_PAGE 1
#define _Q_TAIL_IDX_MASK _Q_SET_MASK(TAIL_IDX)
#define ID_AA64PFR1_EL1_GCS_NI UL(0b0000)
#define ID_AA64DFR0_EL1_DoubleLock_SIGNED false
#define MDSCR_EL1_KDE_MASK GENMASK(13, 13)
#define pgprot_nx(prot) __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
#define MDIO_PMA_STAT2_RXFLTABLE 0x1000
#define PMD_TABLE_PXN (_AT(pmdval_t, 1) << 59)
#define ISR_EL1_A_SHIFT 8
#define TRBMAR_EL1_PAS_MASK GENMASK(11, 10)
#define __NR3264_statfs 43
#define KERNEL_HWCAP_RNG __khwcap2_feature(RNG)
#define PR_SVE_VL_INHERIT (1 << 17)
#define RX_CLS_LOC_FIRST 0xfffffffe
#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
#define ID_AA64MMFR0_EL1_TGRAN4_52_BIT UL(0b0001)
#define idr_unlock_irq(idr) xa_unlock_irq(&(idr)->idr_rt)
#define MDIO_PCS_10T1L_CTRL 2278
#define pm_generic_freeze_late NULL
#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
#define _RET_IP_ (unsigned long)__builtin_return_address(0)
#define ID_AA64PFR1_EL1_DF2_SIGNED false
#define ADVERTISED_100baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Half)
#define MSG_WAITALL 0x100
#define DECLARE_WORK(n,f) struct work_struct n = __WORK_INITIALIZER(n, f)
#define CONFIG_FUTEX 1
#define RXH_DISCARD (1 << 31)
#define SIOCBONDENSLAVE 0x8990
#define MDSCR_EL1_TDCC_SHIFT 12
#define SCTLR_EL1_TCF0_MASK GENMASK(39, 38)
#define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
#define PF_MEMALLOC_NOFS 0x00040000
#define CONFIG_HAVE_KCSAN_COMPILER 1
#define ID_AA64MMFR2_EL1_E0PD_SIGNED false
#define SCTLR_EL1_TCF GENMASK(41, 40)
#define CAP_SETFCAP 31
#define NVIDIA_CPU_PART_CARMEL 0x004
#define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
#define SEMMNS (SEMMNI*SEMMSL)
#define SEMMNU SEMMNS
#define smp_mb__after_spinlock() smp_mb()
#define BMSR_ESTATEN 0x0100
#define LINUX_MOD_DEVICETABLE_H 
#define ID_AA64MMFR0_EL1_EXS_SHIFT 44
#define PACKET_FANOUT 18
#define HDFGRTR_EL2_TRCAUXCTLR_MASK GENMASK(35, 35)
#define IFF_PORTSEL IFF_PORTSEL
#define CONFIG_AS_HAS_ARMV8_5 1
#define _LINUX_MAPLE_TREE_H 
#define _ASM_EXTABLE_KACCESS_ERR_ZERO(insn,fixup,err,zero) __DEFINE_ASM_GPR_NUMS __ASM_EXTABLE_RAW(#insn, #fixup, __stringify(EX_TYPE_KACCESS_ERR_ZERO), "(" EX_DATA_REG(ERR, err) " | " EX_DATA_REG(ZERO, zero) ")")
#define p4d_populate_safe(mm,p4d,pud) do { } while (0)
#define HFGxTR_EL2_TTBR1_EL1_MASK GENMASK(37, 37)
#define ID_ISAR2_EL1_Reversal_SHIFT 28
#define TRAP_PERF_FLAG_ASYNC (1u << 0)
#define AARCH64_BREAK_KGDB_DYN_DBG (AARCH64_BREAK_MON | (KGDB_DYN_DBG_BRK_IMM << 5))
#define CTR_EL0_ERG GENMASK(23, 20)
#define TRBTRG_EL1_TRG_MASK GENMASK(31, 0)
#define get_cpu() ({ preempt_disable(); __smp_processor_id(); })
#define ARCH_TIMER_VIRT_ACCESS 1
#define TRBLIMITR_EL1_FM_MASK GENMASK(2, 1)
#define ETH_P_ARP 0x0806
#define ID_ISAR5_EL1_SHA2_WIDTH 4
#define SYSCALL_DISPATCH_FILTER_BLOCK 1
#define ID_AA64MMFR1_EL1_nTLBPA_NI UL(0b0000)
#define PR_SET_MM_ARG_START 8
#define pud_clear_fixmap() 
#define FLOW_KEYS_HASH_OFFSET offsetof(struct flow_keys, FLOW_KEYS_HASH_START_FIELD)
#define SCTLR_EL1_EnASR_SHIFT 54
#define ID_AA64ISAR1_EL1_LS64_SHIFT 60
#define _LINUX_PERCPU_DEFS_H 
#define HFGITR_EL2_TLBIVAAE1IS GENMASK(31, 31)
#define SCTLR_EL1_SA0_MASK GENMASK(4, 4)
#define DACR32_EL2_D12_MASK GENMASK(25, 24)
#define F_GETLK 5
#define ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
#define ID_MMFR5_EL1_ETS_SIGNED false
#define __MEMINITRODATA .section ".meminit.rodata", "a"
#define EISDIR 21
#define FS_QUOTA_PDQ_ACCT (1<<4)
#define PR_GET_DUMPABLE 3
#define HWCAP2_WFXT (1UL << 31)
#define PSR_I_BIT 0x00000080
#define KERNEL_HWCAP_SB __khwcap_feature(SB)
#define CLIDR_EL1_Ctype5_SHIFT 12
#define HDFGWTR_EL2_nBRBCTL_SHIFT 60
#define ID_AA64MMFR3_EL1_S1PIE_NI UL(0b0000)
#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
#define TCR2_EL2_SKL1_MASK GENMASK(9, 8)
#define MVFR1_EL1_SIMDInt_NI UL(0b0000)
#define ID_PFR0_EL1_CSV2_WIDTH 4
#define RESOURCE_SIZE_MAX ((resource_size_t)~0)
#define LED_FUNCTION_RX "rx"
#define SYS_GCR_EL1_EXCL_MASK 0xffffUL
#define ID_PFR1_EL1_Virt_frac_SIGNED false
#define HDFGWTR_EL2_TRBSR_EL1_WIDTH 1
#define NL_SET_BAD_ATTR_POLICY(extack,attr,pol) do { if ((extack)) { (extack)->bad_attr = (attr); (extack)->policy = (pol); } } while (0)
#define arch_atomic_fetch_xor_release arch_atomic_fetch_xor_release
#define PNP_ID_LEN 8
#define LORSA_EL1_SA_SHIFT 16
#define this_cpu_generic_try_cmpxchg(pcp,ovalp,nval) ({ bool __ret; unsigned long __flags; raw_local_irq_save(__flags); __ret = raw_cpu_generic_try_cmpxchg(pcp, ovalp, nval); raw_local_irq_restore(__flags); __ret; })
#define BMCR_SPEED100 0x2000
#define netdev_err_once(dev,fmt,...) netdev_level_once(KERN_ERR, dev, fmt, ##__VA_ARGS__)
#define DEFINE_DROP_REASON(FN,FNe) FN(NOT_SPECIFIED) FN(NO_SOCKET) FN(PKT_TOO_SMALL) FN(TCP_CSUM) FN(SOCKET_FILTER) FN(UDP_CSUM) FN(NETFILTER_DROP) FN(OTHERHOST) FN(IP_CSUM) FN(IP_INHDR) FN(IP_RPFILTER) FN(UNICAST_IN_L2_MULTICAST) FN(XFRM_POLICY) FN(IP_NOPROTO) FN(SOCKET_RCVBUFF) FN(PROTO_MEM) FN(TCP_AUTH_HDR) FN(TCP_MD5NOTFOUND) FN(TCP_MD5UNEXPECTED) FN(TCP_MD5FAILURE) FN(TCP_AONOTFOUND) FN(TCP_AOUNEXPECTED) FN(TCP_AOKEYNOTFOUND) FN(TCP_AOFAILURE) FN(SOCKET_BACKLOG) FN(TCP_FLAGS) FN(TCP_ZEROWINDOW) FN(TCP_OLD_DATA) FN(TCP_OVERWINDOW) FN(TCP_OFOMERGE) FN(TCP_RFC7323_PAWS) FN(TCP_OLD_SEQUENCE) FN(TCP_INVALID_SEQUENCE) FN(TCP_RESET) FN(TCP_INVALID_SYN) FN(TCP_CLOSE) FN(TCP_FASTOPEN) FN(TCP_OLD_ACK) FN(TCP_TOO_OLD_ACK) FN(TCP_ACK_UNSENT_DATA) FN(TCP_OFO_QUEUE_PRUNE) FN(TCP_OFO_DROP) FN(IP_OUTNOROUTES) FN(BPF_CGROUP_EGRESS) FN(IPV6DISABLED) FN(NEIGH_CREATEFAIL) FN(NEIGH_FAILED) FN(NEIGH_QUEUEFULL) FN(NEIGH_DEAD) FN(TC_EGRESS) FN(QDISC_DROP) FN(CPU_BACKLOG) FN(XDP) FN(TC_INGRESS) FN(UNHANDLED_PROTO) FN(SKB_CSUM) FN(SKB_GSO_SEG) FN(SKB_UCOPY_FAULT) FN(DEV_HDR) FN(DEV_READY) FN(FULL_RING) FN(NOMEM) FN(HDR_TRUNC) FN(TAP_FILTER) FN(TAP_TXFILTER) FN(ICMP_CSUM) FN(INVALID_PROTO) FN(IP_INADDRERRORS) FN(IP_INNOROUTES) FN(PKT_TOO_BIG) FN(DUP_FRAG) FN(FRAG_REASM_TIMEOUT) FN(FRAG_TOO_FAR) FN(TCP_MINTTL) FN(IPV6_BAD_EXTHDR) FN(IPV6_NDISC_FRAG) FN(IPV6_NDISC_HOP_LIMIT) FN(IPV6_NDISC_BAD_CODE) FN(IPV6_NDISC_BAD_OPTIONS) FN(IPV6_NDISC_NS_OTHERHOST) FN(QUEUE_PURGE) FN(TC_COOKIE_ERROR) FN(PACKET_SOCK_ERROR) FN(TC_CHAIN_NOTFOUND) FN(TC_RECLASSIFY_LOOP) FNe(MAX)
#define __ASM_PAGE_H 
#define HDFGWTR_EL2_MDSCR_EL1_MASK GENMASK(4, 4)
#define MDIO_USXGMII_EEE 0x0100
#define CONFIG_NET_VENDOR_MARVELL 1
#define llist_for_each_entry(pos,node,member) for ((pos) = llist_entry((node), typeof(*(pos)), member); member_address_is_nonnull(pos, member); (pos) = llist_entry((pos)->member.next, typeof(*(pos)), member))
#define dev_vdbg(dev,fmt,...) ({ if (0) dev_printk(KERN_DEBUG, dev, dev_fmt(fmt), ##__VA_ARGS__); })
#define CONFIG_TRACE_IRQFLAGS 1
#define GUID_INIT(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) ((guid_t) {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, (b) & 0xff, ((b) >> 8) & 0xff, (c) & 0xff, ((c) >> 8) & 0xff, (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
#define SLAB_POISON ((slab_flags_t __force)0x00000800U)
#define SYS_ID_AA64DFR1_EL1_CRm 5
#define INITIAL_CHAIN_KEY -1
#define __SRCU_STRUCT_INIT_COMMON(name,usage_name) .srcu_sup = &usage_name, __SRCU_DEP_MAP_INIT(name)
#define ETHTOOL_SET_DUMP 0x0000003e
#define ID_MMFR2_EL1_HWAccFlg_IMP UL(0b0001)
#define ESR_ELx_FSC_PERM (0x0C)
#define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
#define make_key_ref(k,p) NULL
#define AF_KCM 41
#define EPOLL_CTL_ADD 1
#define nodes_onto(dst,orig,relmap) __nodes_onto(&(dst), &(orig), &(relmap), MAX_NUMNODES)
#define PAGE_POISON 0xaa
#define DEVICE_ATTR_ADMIN_RO(_name) struct device_attribute dev_attr_ ##_name = __ATTR_RO_MODE(_name, 0400)
#define HCRX_EL2_VFNMI_MASK GENMASK(8, 8)
#define list_safe_reset_next(pos,n,member) n = list_next_entry(pos, member)
#define DEVICE_ATTR_ADMIN_RW(_name) struct device_attribute dev_attr_ ##_name = __ATTR_RW_MODE(_name, 0600)
#define MNT_NODEV 0x02
#define raw_local_irq_enable() arch_local_irq_enable()
#define ID_AA64ISAR2_EL1_APA3_FPAC UL(0b0100)
#define CONFIG_IRQ_FORCED_THREADING 1
#define POOL_POISON_ALLOCATED 0xa9
#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
#define param_check_invbool(name,p) __param_check(name, p, bool)
#define LRU_REFS_MASK ((BIT(LRU_REFS_WIDTH) - 1) << LRU_REFS_PGOFF)
#define CONFIG_CONSTRUCTORS 1
#define HFGITR_EL2_TLBIRVAAE1 GENMASK(39, 39)
#define MDIO_PMA_PMD_BT1_CTRL 2100
#define ULONG_MAX (~0UL)
#define flush_workqueue(wq) ({ struct workqueue_struct *_wq = (wq); if ((__builtin_constant_p(_wq == system_wq) && _wq == system_wq) || (__builtin_constant_p(_wq == system_highpri_wq) && _wq == system_highpri_wq) || (__builtin_constant_p(_wq == system_long_wq) && _wq == system_long_wq) || (__builtin_constant_p(_wq == system_unbound_wq) && _wq == system_unbound_wq) || (__builtin_constant_p(_wq == system_freezable_wq) && _wq == system_freezable_wq) || (__builtin_constant_p(_wq == system_power_efficient_wq) && _wq == system_power_efficient_wq) || (__builtin_constant_p(_wq == system_freezable_power_efficient_wq) && _wq == system_freezable_power_efficient_wq)) __warn_flushing_systemwide_wq(); __flush_workqueue(_wq); })
#define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
#define ID_AA64ZFR0_EL1_SVEver GENMASK(3, 0)
#define ID_ISAR6_EL1_BF16_NI UL(0b0000)
#define ID_PFR0_EL1_RAS_SHIFT 28
#define HDFGWTR_EL2_TRBMAR_EL1_MASK GENMASK(53, 53)
#define CONFIG_NET_VENDOR_SYNOPSYS 1
#define COMPAT_SHMLBA (4 * PAGE_SIZE)
#define local_inc_return(l) atomic_long_inc_return(&(l)->a)
#define DL_FLAG_SYNC_STATE_ONLY BIT(7)
#define MDIO_PMA_CTRL2_10GBEW 0x0001
#define _QW_WAITING 0x100
#define CONFIG_CC_HAS_ZERO_CALL_USED_REGS 1
#define kcsan_check_write(ptr,size) kcsan_check_access(ptr, size, KCSAN_ACCESS_WRITE)
#define EM_CSKY 252
#define __NR_umask 166
#define lockdep_assert_none_held_once() lockdep_assert_once(!current->lockdep_depth)
#define SYS_CONTEXTIDR_EL2_Op0 3
#define SYS_CONTEXTIDR_EL2_Op1 4
#define SYS_CONTEXTIDR_EL2_Op2 1
#define CONFIG_BLK_MQ_VIRTIO 1
#define SHT_SHLIB 10
#define CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT 1
#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
#define CTR_EL0_L1Ip_PIPT UL(0b11)
#define ZONEID_PGSHIFT (ZONEID_PGOFF * (ZONEID_SHIFT != 0))
#define __ASM_CPUFEATURE_H 
#define IPV6_FLOWLABEL_MGR 32
#define ID_AA64SMFR0_EL1_F16F32_WIDTH 1
#define __ASM_UACCESS_H 
#define TIF_SYSCALL_EMU 12
#define ETHTOOL_GET_TS_INFO 0x00000041
#define CONFIG_MMU_GATHER_RCU_TABLE_FREE 1
#define ID_ISAR5_EL1_RDM_SHIFT 24
#define FPE_FLTSUB 8
#define HDFGRTR_EL2_TRBTRG_EL1_MASK GENMASK(56, 56)
#define KUNIT_ASSERT_NOT_ERR_OR_NULL(test,ptr) KUNIT_ASSERT_NOT_ERR_OR_NULL_MSG(test, ptr, NULL)
#define AH_ESP_V6_FLOW 0x08
#define CONFIG_STACKDEPOT 1
#define CONFIG_ARCH_HAVE_ELF_PROT 1
#define HFGITR_EL2_TLBIVAAE1OS GENMASK(21, 21)
#define MVFR1_EL1_SIMDFMAC_IMP UL(0b0001)
#define ETHTOOL_F_UNSUPPORTED (1 << ETHTOOL_F_UNSUPPORTED__BIT)
#define no_printk(fmt,...) ({ if (0) printk(fmt, ##__VA_ARGS__); 0; })
#define ID_PFR1_EL1_GIC_SHIFT 28
#define this_cpu_or(pcp,val) __pcpu_size_call(this_cpu_or_, pcp, val)
#define ID_AA64PFR0_EL1_RAS_V1P1 UL(0b0010)
#define ATOMIC64_INIT ATOMIC_INIT
#define REFCOUNT_INIT(n) { .refs = ATOMIC_INIT(n), }
#define ID_AA64PFR0_EL1_EL2_NI UL(0b0000)
#define MDIO_PCS_EEE_ABLE 20
#define pgd_page_vaddr(pgd) ((unsigned long)(p4d_pgtable((p4d_t){ pgd })))
#define ID_MMFR3_EL1_PAN_WIDTH 4
#define NETIF_F_GSO_UDP_TUNNEL __NETIF_F(GSO_UDP_TUNNEL)
#define KASAN_THREAD_SHIFT 0
#define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
#define __HAVE_ARCH_STRLEN 
#define PR_RISCV_V_VSTATE_CTRL_OFF 1
#define MII_PHYSID2 0x03
#define CONFIG_NET_VENDOR_VERTEXCOM 1
#define SMPRIMAP_EL2_P5_MASK GENMASK(23, 20)
#define PT_TRACE_EXEC PT_EVENT_FLAG(PTRACE_EVENT_EXEC)
#define __NR_pwrite64 68
#define _UAPI_LINUX_OPENAT2_H 
#define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
#define rwlock_is_contended(lock) arch_rwlock_is_contended(&(lock)->raw_lock)
#define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
#define COMPAT_HWCAP_FAST_MULT (1 << 4)
#define I_DIRTY_PAGES (1 << 2)
#define smp_acquire__after_ctrl_dep() smp_rmb()
#define _ASM_GENERIC_BITOPS_INSTRUMENTED_LOCK_H 
#define PMSIDR_EL1_COUNTSIZE GENMASK(19, 16)
#define CONFIG_EXCLUSIVE_SYSTEM_RAM 1
#define MDIO_USXGMII_2500HALF 0x0800
#define register_ftrace_function(ops) ({ 0; })
#define DQUOT_NOLIST_DIRTY (1 << (DQUOT_STATE_LAST + 2))
#define CONFIG_OF_OVERLAY 1
#define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x)
#define set_fixmap_offset_nocache(idx,phys) __set_fixmap_offset(idx, phys, FIXMAP_PAGE_NOCACHE)
#define ID_DFR0_EL1_MMapDbg_SHIFT 8
#define _LINUX_KPROBES_H 
#define ID_AA64ISAR2_EL1_BC_IMP UL(0b0001)
#define TAINT_PROPRIETARY_MODULE 0
#define IOPRIO_NORM 4
#define _ASM_GENERIC_FCNTL_H 
#define HFGITR_EL2_TLBIASIDE1IS_WIDTH 1
#define ENCODING_FM_SPACE 4
#define SCTLR_EL1_TME GENMASK(53, 53)
#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008
#define ID_AA64MMFR3_EL1_AIE_MASK GENMASK(27, 24)
#define __HAVE_ARCH_UPDATE_MMU_TLB 
#define this_cpu_inc(pcp) this_cpu_add(pcp, 1)
#define PMSCR_EL1_PA GENMASK(4, 4)
#define LOCAL_DISTANCE 10
#define SHM_EXEC 0100000
#define CLOCK_BOOTTIME_ALARM 9
#define FS_XFLAG_EXTSIZE 0x00000800
#define SHMAT 21
#define __GENMASK(h,l) (((~UL(0)) - (UL(1) << (l)) + 1) & (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
#define ARM64_HW_DBM 49
#define TP_STATUS_VLAN_VALID (1 << 4)
#define HFGITR_EL2_TLBIRVALE1OS_WIDTH 1
#define KASAN_TAG_MASK ((1UL << KASAN_TAG_WIDTH) - 1)
#define __wait_event_freezable_timeout(wq_head,condition,timeout) ___wait_event(wq_head, ___wait_cond_timeout(condition), (TASK_INTERRUPTIBLE|TASK_FREEZABLE), 0, timeout, __ret = schedule_timeout(__ret))
#define csdb() asm volatile("hint #20" : : : "memory")
#define MTE_CTRL_TCF_ASYMM (1UL << 18)
#define SYS_ID_AA64AFR1_EL1_CRn 0
#define TRBMAR_EL1_PAS_SECURE UL(0b00)
#define ID_AA64SMFR0_EL1_B16B16_SHIFT 43
#define IOCB_WRITE (1 << 18)
#define HFGxTR_EL2_LORC_EL1_MASK GENMASK(19, 19)
#define ID_ISAR2_EL1_MultU_UMAAL UL(0b0010)
#define ID_PFR2_EL1_SSBS_SIGNED false
#define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name), 0)
#define __VDSO_TIME_H 
#define HDFGRTR_EL2_PMSELR_EL0_MASK GENMASK(19, 19)
#define ID_MMFR3_EL1_Supersec GENMASK(31, 28)
#define pud_free(mm,x) do { } while (0)
#define check_mul_overflow(a,b,d) __must_check_overflow(__builtin_mul_overflow(a, b, d))
#define time_in_range(a,b,c) (time_after_eq(a,b) && time_before_eq(a,c))
#define DCACHE_FSNOTIFY_PARENT_WATCHED 0x00004000
#define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020
#define CTR_EL0_DIC_SHIFT 29
#define CACHELINE_ASSERT_GROUP_SIZE(TYPE,GROUP,SIZE) BUILD_BUG_ON(offsetof(TYPE, __cacheline_group_end__ ##GROUP) - offsetofend(TYPE, __cacheline_group_begin__ ##GROUP) > SIZE)
#define ID_AA64MMFR3_EL1_SNERR_SHIFT 40
#define MDSCR_EL1_UNKN (UL(0))
#define SWNODE_GRAPH_PORT_NAME_FMT "port@%u"
#define PMBIDR_EL1_EA_SError UL(0b0010)
#define CSSELR_EL1_Level_WIDTH 3
#define HFGITR_EL2_TLBIVALE1 GENMASK(46, 46)
#define ID_ISAR1_EL1_Interwork_MASK GENMASK(27, 24)
#define iowrite64 iowrite64
#define WORK_STRUCT_NO_POOL (WORK_OFFQ_POOL_NONE << WORK_OFFQ_POOL_SHIFT)
#define ESR_ELx_EA_SHIFT (9)
#define HDFGRTR_EL2_TRCPRGCTLR_MASK GENMASK(44, 44)
#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
#define __used __attribute__((__used__))
#define ID_AA64MMFR1_EL1_VMIDBits_16 UL(0b0010)
#define ID_AA64PFR1_EL1_MTE_frac_NI UL(0b1111)
#define __no_sanitize_address __attribute__((__no_sanitize_address__))
#define SO_KEEPALIVE 9
#define __user BTF_TYPE_TAG(user)
#define CONFIG_DEVTMPFS 1
#define BIN_ATTR_ADMIN_RO(_name,_size) struct bin_attribute bin_attr_ ##_name = __BIN_ATTR_ADMIN_RO(_name, _size)
#define HFGxTR_EL2_MIDR_EL1_SHIFT 25
#define PIRx_ELx_Perm15_MASK GENMASK(63, 60)
#define MMF_DUMP_FILTER_DEFAULT ((1 << MMF_DUMP_ANON_PRIVATE) | (1 << MMF_DUMP_ANON_SHARED) | (1 << MMF_DUMP_HUGETLB_PRIVATE) | MMF_DUMP_MASK_DEFAULT_ELF)
#define ESR_ELx_SF_SHIFT (15)
#define VM_DEFER_KMEMLEAK 0
#define ETHTOOL_GWOL 0x00000005
#define ID_AA64MMFR3_EL1_ANERR_SIGNED false
#define __DEFINE_PERCPU_RWSEM(name,is_static) static DEFINE_PER_CPU(unsigned int, __percpu_rwsem_rc_ ##name); is_static struct percpu_rw_semaphore name = { .rss = __RCU_SYNC_INITIALIZER(name.rss), .read_count = &__percpu_rwsem_rc_ ##name, .writer = __RCUWAIT_INITIALIZER(name.writer), .waiters = __WAIT_QUEUE_HEAD_INITIALIZER(name.waiters), .block = ATOMIC_INIT(0), __PERCPU_RWSEM_DEP_MAP_INIT(name) }
#define node_spanned_pages(nid) (NODE_DATA(nid)->node_spanned_pages)
#define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | ESR_ELx_CP15_64_ISS_CRM_MASK | ESR_ELx_CP15_64_ISS_DIR_MASK)
#define __SVE_VQ_MIN 1
#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
#define TCR2_EL1x_AIE_MASK GENMASK(4, 4)
#define arch_cmpxchg(...) __cmpxchg_wrapper( _mb, __VA_ARGS__)
#define HFGxTR_EL2_ERXADDR_EL1 GENMASK(49, 49)
#define KERNEL_HWCAP_SVE __khwcap_feature(SVE)
#define lock_acquire_shared(l,s,t,n,i) lock_acquire(l, s, t, 1, 1, n, i)
#define SOCK_NOSPACE 2
#define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
#define ISR_EL1_F_WIDTH 1
#define PTRACE_EVENTMSG_SYSCALL_ENTRY 1
#define read_seqlock_excl_irqsave(lock,flags) do { flags = __read_seqlock_excl_irqsave(lock); } while (0)
#define ID_AA64DFR0_EL1_HPMN0_WIDTH 4
#define RLIMIT_SIGPENDING 11
#define ETHTOOL_SCOALESCE 0x0000000f
#define PG_mte_tagged 0
#define SYS_MVFR1_EL1_CRn 0
#define small_const_nbits(nbits) (__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG && (nbits) > 0)
#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
#define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
#define DEFAULT_RATELIMIT_BURST 10
#define IORESOURCE_MEM 0x00000200
#define SECCOMP_IOCTL_NOTIF_RECV SECCOMP_IOWR(0, struct seccomp_notif)
#define arch_atomic64_fetch_andnot_release arch_atomic64_fetch_andnot_release
#define NODES_PGOFF (SECTIONS_PGOFF - NODES_WIDTH)
#define IPV4_USER_FLOW 0x0d
#define this_cpu_try_cmpxchg(pcp,ovalp,nval) __pcpu_size_call_return2bool(this_cpu_try_cmpxchg_, pcp, ovalp, nval)
#define SMPRIMAP_EL2_P3_WIDTH 4
#define raw_cpu_read_8(pcp) raw_cpu_generic_read(pcp)
#define REG_ID_DFR0_EL1 S3_0_C0_C1_2
#define ID_AA64ISAR2_EL1_WFxT GENMASK(3, 0)
#define UIO_MAXIOV 1024
#define __NETIF_F_BIT(bit) ((netdev_features_t)1 << (bit))
#define ID_AA64PFR0_EL1_SVE_WIDTH 4
#define SCTLR_EL1_EE_WIDTH 1
#define SCHED_FLAG_UTIL_CLAMP_MAX 0x40
#define PIRx_ELx_Perm5_WIDTH 4
#define SYS_ID_ISAR5_EL1_Op0 3
#define SYS_ID_ISAR5_EL1_Op1 0
#define SYS_ID_ISAR5_EL1_Op2 5
#define ID_ISAR3_EL1_Saturate_WIDTH 4
#define OSDTRRX_EL1_DTRRX_SHIFT 0
#define ETHTOOL_COALESCE_TX_USECS_IRQ BIT(6)
#define FLOW_DIS_MPLS_MAX 7
#define SCTLR_EL1_E0E_WIDTH 1
#define smp_load_acquire(p) __smp_load_acquire(p)
#define HCRX_EL2_EnSNERR_WIDTH 1
#define SO_SELECT_ERR_QUEUE 45
#define irq_count() (preempt_count() & (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_MASK))
#define const_ilog2(n) ( __builtin_constant_p(n) ? ( (n) < 2 ? 0 : (n) & (1ULL << 63) ? 63 : (n) & (1ULL << 62) ? 62 : (n) & (1ULL << 61) ? 61 : (n) & (1ULL << 60) ? 60 : (n) & (1ULL << 59) ? 59 : (n) & (1ULL << 58) ? 58 : (n) & (1ULL << 57) ? 57 : (n) & (1ULL << 56) ? 56 : (n) & (1ULL << 55) ? 55 : (n) & (1ULL << 54) ? 54 : (n) & (1ULL << 53) ? 53 : (n) & (1ULL << 52) ? 52 : (n) & (1ULL << 51) ? 51 : (n) & (1ULL << 50) ? 50 : (n) & (1ULL << 49) ? 49 : (n) & (1ULL << 48) ? 48 : (n) & (1ULL << 47) ? 47 : (n) & (1ULL << 46) ? 46 : (n) & (1ULL << 45) ? 45 : (n) & (1ULL << 44) ? 44 : (n) & (1ULL << 43) ? 43 : (n) & (1ULL << 42) ? 42 : (n) & (1ULL << 41) ? 41 : (n) & (1ULL << 40) ? 40 : (n) & (1ULL << 39) ? 39 : (n) & (1ULL << 38) ? 38 : (n) & (1ULL << 37) ? 37 : (n) & (1ULL << 36) ? 36 : (n) & (1ULL << 35) ? 35 : (n) & (1ULL << 34) ? 34 : (n) & (1ULL << 33) ? 33 : (n) & (1ULL << 32) ? 32 : (n) & (1ULL << 31) ? 31 : (n) & (1ULL << 30) ? 30 : (n) & (1ULL << 29) ? 29 : (n) & (1ULL << 28) ? 28 : (n) & (1ULL << 27) ? 27 : (n) & (1ULL << 26) ? 26 : (n) & (1ULL << 25) ? 25 : (n) & (1ULL << 24) ? 24 : (n) & (1ULL << 23) ? 23 : (n) & (1ULL << 22) ? 22 : (n) & (1ULL << 21) ? 21 : (n) & (1ULL << 20) ? 20 : (n) & (1ULL << 19) ? 19 : (n) & (1ULL << 18) ? 18 : (n) & (1ULL << 17) ? 17 : (n) & (1ULL << 16) ? 16 : (n) & (1ULL << 15) ? 15 : (n) & (1ULL << 14) ? 14 : (n) & (1ULL << 13) ? 13 : (n) & (1ULL << 12) ? 12 : (n) & (1ULL << 11) ? 11 : (n) & (1ULL << 10) ? 10 : (n) & (1ULL << 9) ? 9 : (n) & (1ULL << 8) ? 8 : (n) & (1ULL << 7) ? 7 : (n) & (1ULL << 6) ? 6 : (n) & (1ULL << 5) ? 5 : (n) & (1ULL << 4) ? 4 : (n) & (1ULL << 3) ? 3 : (n) & (1ULL << 2) ? 2 : 1) : -1)
#define FS_IOC32_GETVERSION _IOR('v', 1, int)
#define compat_arg_u64_glue(name) (((u64)name ##_lo & 0xffffffffUL) | ((u64)name ##_hi << 32))
#define ID_AA64MMFR1_EL1_AFP_SHIFT 44
#define HCRX_EL2_MCE2 GENMASK(10, 10)
#define MAXFREQ 500000
#define ID_AA64MMFR3_EL1_D128_WIDTH 4
#define SIOCGIFMAP 0x8970
#define PMSCR_EL1_PCT_WIDTH 2
#define MDIO_AN_C73_1_10GBASE_KX4 BIT(6)
#define CONT_PMDS (1 << (CONT_PMD_SHIFT - PMD_SHIFT))
#define __ASM_SPINLOCK_H 
#define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
#define CONFIG_LOCKDEP_SUPPORT 1
#define ID_AA64ZFR0_EL1_BF16_SHIFT 20
#define SEGCBLIST_KTHREAD_CB BIT(3)
#define ID_AA64ISAR2_EL1_APA3 GENMASK(15, 12)
#define le64_to_cpus __le64_to_cpus
#define ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ BIT(3)
#define NPROTO AF_MAX
#define HFGITR_EL2_TLBIVMALLE1_MASK GENMASK(42, 42)
#define I_DIRTY_TIME (1 << 11)
#define CONFIG_ARCH_HAS_DEBUG_VIRTUAL 1
#define ID_MMFR0_EL1_PMSA_IMPDEF UL(0b0001)
#define CONFIG_LOCK_SPIN_ON_OWNER 1
#define ID_MMFR1_EL1_L1TstCln_INVALIDATE UL(0b0010)
#define nodes_shift_right(dst,src,n) __nodes_shift_right(&(dst), &(src), (n), MAX_NUMNODES)
#define BLKROSET _IO(0x12,93)
#define ID_AA64PFR0_EL1_AMU_NI UL(0b0000)
#define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK)
#define CONFIG_USB_OHCI_LITTLE_ENDIAN 1
#define JOBCTL_TRAP_MASK (JOBCTL_TRAP_STOP | JOBCTL_TRAP_NOTIFY)
#define _SYSCALL_USER_DISPATCH_H 
#define pageblock_align(pfn) ALIGN((pfn), pageblock_nr_pages)
#define LED_COLOR_ID_PINK 12
#define HFGITR_EL2_DCCVAC_MASK GENMASK(54, 54)
#define KERNEL_HWCAP_BTI __khwcap2_feature(BTI)
#define PR_SET_SYSCALL_USER_DISPATCH 59
#define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
#define FLOW_DISSECTOR_F_STOP_AT_ENCAP BIT(2)
#define IPV6_FL_A_RENEW 2
#define PR_MCE_KILL 33
#define __NR_epoll_ctl 21
#define SB_I_NOEXEC 0x00000002
#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
#define CONFIG_BLK_MQ_PCI 1
#define __cpu_to_be16(x) ((__force __be16)__swab16((x)))
#define HUGETLB_FLAG_ENCODE_64KB (16U << HUGETLB_FLAG_ENCODE_SHIFT)
#define __MUTEX_INITIALIZER(lockname) { .owner = ATOMIC_LONG_INIT(0) , .wait_lock = __RAW_SPIN_LOCK_UNLOCKED(lockname.wait_lock) , .wait_list = LIST_HEAD_INIT(lockname.wait_list) __DEBUG_MUTEX_INITIALIZER(lockname) __DEP_MAP_MUTEX_INITIALIZER(lockname) }
#define PR_SET_MM_START_BRK 6
#define CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ 1
#define HWCAP_ASIMDRDM (1 << 12)
#define SVE_SIG_ZREGS_OFFSET (SVE_SIG_REGS_OFFSET + __SVE_ZREGS_OFFSET)
#define HFGITR_EL2_TLBIVALE1IS_WIDTH 1
#define TCR2_EL1x_E0POE_SHIFT 2
#define SI_ASYNCIO -4
#define __NR_getgid 176
#define TRAP_BRKPT 1
#define MAS_NONE ((struct maple_enode *)9UL)
#define CONFIG_NET_VENDOR_QLOGIC 1
#define IDR_FREE 0
#define ID_MMFR1_EL1_L1Hvd_INVALIDATE_ISIDE_ONLY UL(0b0001)
#define module_param(name,type,perm) module_param_named(name, name, type, perm)
#define PSTATE_DIT pstate_field(3, 2)
#define HFGxTR_EL2_nPIRE0_EL1_SHIFT 57
#define PMSEVFR_EL1_UNKN (UL(0))
#define TCR2_EL1x_PIE_MASK GENMASK(1, 1)
#define __ASM_GENERIC_SHMBUF_H 
#define KTIME_SEC_MAX (KTIME_MAX / NSEC_PER_SEC)
#define VM_DATA_FLAGS_NON_EXEC (VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#define CTR_EL0_DminLine_MASK GENMASK(19, 16)
#define HDFGRTR_EL2_PMBSR_EL1_MASK GENMASK(25, 25)
#define siphash_aligned_key_t siphash_key_t __aligned(16)
#define EBADFD 77
#define FS_DQ_BIGTIME (1<<15)
#define ID_AA64ISAR1_EL1_JSCVT_WIDTH 4
#define SWAPPER_PGTABLE_LEVELS (CONFIG_PGTABLE_LEVELS - 1)
#define SCTLR_EL1_ITD_MASK GENMASK(7, 7)
#define CONFIG_PAGE_SIZE_LESS_THAN_256KB 1
#define __io_pbw() __io_bw()
#define TRBMAR_EL1_Attr GENMASK(7, 0)
#define ESR_ELx_FSC (0x3F)
#define _LINUX_STACKDEPOT_H 
#define CONFIG_AIO 1
#define ETH_P_MACSEC 0x88E5
#define ID_AA64MMFR2_EL1_EVT_MASK GENMASK(59, 56)
#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
#define raw_cmpxchg_local arch_cmpxchg_local
#define MDIO_USXGMII_5000HALF 0x0a00
#define SCTLR_ELx_IESB (BIT(21))
#define pmr_sync() do {} while (0)
#define ID_AA64SMFR0_EL1_BI32I32_MASK GENMASK(33, 33)
#define LED_FUNCTION_FAULT "fault"
#define PHY_MAC_INTERRUPT -2
#define SCM_TIMESTAMPING_OPT_STATS 54
#define __kernel_read_file_id(id) id(UNKNOWN, unknown) id(FIRMWARE, firmware) id(MODULE, kernel-module) id(KEXEC_IMAGE, kexec-image) id(KEXEC_INITRAMFS, kexec-initramfs) id(POLICY, security-policy) id(X509_CERTIFICATE, x509-certificate) id(MAX_ID, )
#define __ASM_GENERIC_IO_H 
#define __cpu_to_be32(x) ((__force __be32)__swab32((x)))
#define QUOTA_NL_BSOFTLONGWARN 5
#define ID_ISAR0_EL1_Swap_NI UL(0b0000)
#define ID_PFR0_EL1_State3_IMP UL(0b0001)
#define GFP_NOWAIT (__GFP_KSWAPD_RECLAIM)
#define NLM_F_ACK_TLVS 0x200
#define V2_INIT_ALLOC QTREE_INIT_ALLOC
#define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_FILTER | NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX)
#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
#define CurrentEL_EL2 (2 << 2)
#define SIOCGPGRP 0x8904
#define CONFIG_PTP_1588_CLOCK_KVM 1
#define ID_ISAR6_EL1_JSCVT_SIGNED false
#define ARM64_HAS_NO_HW_PREFETCH 37
#define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
#define SHM_HUGE_1GB HUGETLB_FLAG_ENCODE_1GB
#define CONFIG_SND_DEBUG_VERBOSE 1
#define IOPRIO_HINT_NR_BITS 10
#define ID_AA64PFR0_EL1_ELx_32BIT_64BIT 0x2
#define mp_bvec_iter_bvec(bvec,iter) ((struct bio_vec) { .bv_page = mp_bvec_iter_page((bvec), (iter)), .bv_len = mp_bvec_iter_len((bvec), (iter)), .bv_offset = mp_bvec_iter_offset((bvec), (iter)), })
#define raw_irqs_disabled() (arch_irqs_disabled())
#define TCR_TCMA0 (UL(1) << 57)
#define TCR_TCMA1 (UL(1) << 58)
#define DT_RELAENT 9
#define pgprot_writethrough pgprot_noncached
#define QUOTA_NL_C_MAX (__QUOTA_NL_C_MAX - 1)
#define CONFIG_DEFAULT_HOSTNAME "(none)"
#define MDIO_USXGMII_LINK 0x8000
#define CAP_AUDIT_WRITE 29
#define CONFIG_ETHERNET 1
#define VFS_CAP_REVISION_MASK 0xFF000000
#define SOCK_TXREHASH_DEFAULT 255
#define HFGxTR_EL2_SCXTNUM_EL1_SHIFT 30
#define NSEC_JIFFIE_SC (SEC_JIFFIE_SC + 29)
#define WARN_TAINT(condition,taint,format...) ({ int __ret_warn_on = !!(condition); if (unlikely(__ret_warn_on)) __WARN_printf(taint, format); unlikely(__ret_warn_on); })
#define PACKET_MULTICAST 2
#define ADVERTISED_10baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Half)
#define pgprot_encrypted(prot) (prot)
#define NT_TASKSTRUCT 4
#define CONFIG_DMA_ENGINE 1
#define QUOTA_NL_A_MAX (__QUOTA_NL_A_MAX - 1)
#define S_DT_SHIFT 12
#define HFGITR_EL2_DCCSW_WIDTH 1
#define SOFTIRQ_DISABLE_OFFSET (2 * SOFTIRQ_OFFSET)
#define STATIC_CALL_TRAMP_PREFIX __SCT__
#define COMPAT_HWCAP_VFPv3 (1 << 13)
#define ID_MMFR4_EL1_LSM_WIDTH 4
#define MNT_LOCK_NOEXEC 0x080000
#define HFGITR_EL2_nGCSSTR_EL1_MASK GENMASK(58, 58)
#define TCR2_EL2_E0POE_MASK GENMASK(2, 2)
#define IPV6_TRANSPARENT 75
#define __CMSG_NXTHDR(ctl,len,cmsg) __cmsg_nxthdr((ctl),(len),(cmsg))
#define ID_MMFR3_EL1_CMemSz_64GB UL(0b0001)
#define FS_ALLOW_IDMAP 32
#define PMSCR_EL1_RES1 (UL(0))
#define SYS_TRBMAR_EL1_Op0 3
#define __cpu_to_be64(x) ((__force __be64)__swab64((x)))
#define HPAGE_PMD_SIZE ({ BUILD_BUG(); 0; })
#define MAX_SEC_IN_JIFFIES (SH_DIV((MAX_JIFFY_OFFSET >> SEC_JIFFIE_SC) * TICK_NSEC, NSEC_PER_SEC, 1) - 1)
#define PMSNEVFR_EL1_RES0 (UL(0))
#define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
#define FIOSETOWN 0x8901
#define static_branch_likely(x) likely_notrace(static_key_enabled(&(x)->key))
#define hash_long(val,bits) hash_64(val, bits)
#define PTRACE_SYSCALL 24
#define CONFIG_ZSTD_COMMON 1
#define ID_MMFR0_EL1_AuxReg_ACTLR UL(0b0001)
#define arch_get_mmap_end(addr,len,flags) (((addr) > DEFAULT_MAP_WINDOW) ? TASK_SIZE : DEFAULT_MAP_WINDOW)
#define MASTER_SLAVE_CFG_MASTER_PREFERRED 2
#define SHRT_MIN ((short)(-SHRT_MAX - 1))
#define IORESOURCE_MEM_SHADOWABLE (1<<5)
#define si_perf_data _sifields._sigfault._perf._data
#define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2))
#define TRAP_UNK 5
#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
#define CONFIG_RPS 1
#define ID_MMFR2_EL1_UniTLB_BY_IPA UL(0b0110)
#define SHMGET 23
#define ETH_MAX_MTU 0xFFFFU
#define HDFGRTR_EL2_DBGPRCR_EL1_WIDTH 1
#define OSDTRRX_EL1_UNKN (UL(0))
#define IDR_INIT(name) IDR_INIT_BASE(name, 0)
#define NETIF_F_GSO_GRE __NETIF_F(GSO_GRE)
#define O_TMPFILE (__O_TMPFILE | O_DIRECTORY)
#define AARCH32_BREAK_THUMB2_LO 0xf7f0
#define MDIO_EMULATE_C22 4
#define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
#define for_each_cpu_or(cpu,mask1,mask2) for_each_or_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
#define IORESOURCE_DMA_SPEED_MASK (3<<6)
#define DBG_HOOK_HANDLED 0
#define TP_STATUS_CSUM_VALID (1 << 7)
#define MVFR0_EL1_FPDivide_MASK GENMASK(19, 16)
#define SO_INCOMING_CPU 49
#define TCR2_EL2_SKL0_SHIFT 6
#define MDIO_CTRL1_RESET BMCR_RESET
#define abs(x) __abs_choose_expr(x, long long, __abs_choose_expr(x, long, __abs_choose_expr(x, int, __abs_choose_expr(x, short, __abs_choose_expr(x, char, __builtin_choose_expr( __builtin_types_compatible_p(typeof(x), char), (char)({ signed char __x = (x); __x<0?-__x:__x; }), ((void)0)))))))
#define PAGE_MAPPING_ANON 0x1
#define PF__HOLE__01000000 0x01000000
#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR, _end, EARLY_KASLR))
#define __TLBI_N(op,arg,n,...) __TLBI_ ##n(op, arg)
#define FWNODE_FLAG_VISITED BIT(5)
#define HWCAP_DIT (1 << 24)
#define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0)
#define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
#define list_for_each_entry_continue(pos,head,member) for (pos = list_next_entry(pos, member); !list_entry_is_head(pos, head, member); pos = list_next_entry(pos, member))
#define PHY_SHARED_F_PROBE_DONE 1
#define ID_AA64MMFR1_EL1_SpecSEI GENMASK(27, 24)
#define __getname() kmem_cache_alloc(names_cachep, GFP_KERNEL)
#define ID_MMFR1_EL1_L1HvdSW_SHIFT 8
#define MDIO_AN_C73_1_10GBASE_KR BIT(7)
#define __diag_push() __diag(push)
#define IPACK_ANY_FORMAT 0xff
#define SYS_TFSR_EL1_TF1_SHIFT 1
#define CPU_STUCK_REASON_SHIFT (8)
#define cpu_to_be16p __cpu_to_be16p
#define cpu_to_be16s __cpu_to_be16s
#define SCTLR_EL1_SPINTMASK_MASK GENMASK(62, 62)
#define KTIME_SEC_MIN (KTIME_MIN / NSEC_PER_SEC)
#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
#define HDFGWTR_EL2_nBRBCTL GENMASK(60, 60)
#define VM_MAP 0x00000004
#define ID_ISAR1_EL1_Interwork_NI UL(0b0000)
#define ID_MMFR2_EL1_WFIStall_SHIFT 24
#define MDIO_PCS_SPEED_10P2B 0x0002
#define ESR_ELx_TnD_SHIFT (10)
#define raw_cpu_try_cmpxchg128(pcp,ovalp,nval) raw_cpu_generic_try_cmpxchg(pcp, ovalp, nval)
#define CPTR_EL2_TZ (1 << 8)
#define REG_SMPRI_EL1 S3_0_C1_C2_4
#define CONFIG_WLAN_VENDOR_REALTEK 1
#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
#define __REFCONST .section ".ref.rodata", "a"
#define SVE_PT_SVE_PREGS_OFFSET(vq) (SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
#define type_max(T) ((T)((__type_half_max(T) - 1) + __type_half_max(T)))
#define MDIO_AN_EEE_ADV2 62
#define ID_AA64MMFR0_EL1_BIGEND_NI UL(0b0000)
#define DT_CHR 2
#define SIGSEGV 11
#define DT_PLTRELSZ 2
#define raw_cpu_or_1(pcp,val) raw_cpu_generic_to_op(pcp, val, |=)
#define __local64_inc(l) local64_set((l), local64_read(l) + 1)
#define FS_IOC_FSGETXATTR _IOR('X', 31, struct fsxattr)
#define late_initcall_sync(fn) __define_initcall(fn, 7s)
#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL 0x0040
#define PMSIRR_EL1_RND GENMASK(0, 0)
#define SRCU_SIZE_WAIT_BARRIER 2
#define FS_APPEND_FL 0x00000020
#define cpu_to_le16 __cpu_to_le16
#define HFGxTR_EL2_nPOR_EL1_SHIFT 60
#define PMBLIMITR_EL1_FM_FILL UL(0b00)
#define HWCAP_LRCPC (1 << 15)
#define HCRX_EL2_GCSEn_MASK GENMASK(22, 22)
#define ID_AA64ISAR1_EL1_I8MM_WIDTH 4
#define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
#define QIF_ILIMITS (1 << QIF_ILIMITS_B)
#define ID_MMFR0_EL1_FCSE_MASK GENMASK(27, 24)
#define TCR2_EL2_SKL0 GENMASK(7, 6)
#define HFGxTR_EL2_CPACR_EL1_WIDTH 1
#define ID_AA64AFR0_EL1_IMPDEF0_MASK GENMASK(3, 0)
#define SYS_RGSR_EL1_SEED_SHIFT 8
#define ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
#define write_seqcount_end(s) do { do_write_seqcount_end(seqprop_ptr(s)); if (seqprop_preemptible(s)) preempt_enable(); } while (0)
#define timers_prepare_cpu NULL
#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
#define HCRX_EL2_MSCEn_MASK GENMASK(11, 11)
#define pm_generic_complete NULL
#define wake_up_interruptible_sync(x) __wake_up_sync((x), TASK_INTERRUPTIBLE)
#define MDCR_EL2_HCCD (UL(1) << 23)
#define SIG_DFL ((__force __sighandler_t)0)
#define ID_PFR1_EL1_Virtualization_IMP UL(0b0001)
#define ESR_ELx_SME_ISS_ZT_DISABLED 4
#define hlist_nulls_entry(ptr,type,member) container_of(ptr,type,member)
#define _UAPI_LINUX_FCNTL_H 
#define ETHTOOL_PHYS_ID 0x0000001c
#define __NR_mincore 232
#define SIOCSIFMETRIC 0x891e
#define __NR_gettid 178
#define IORESOURCE_MEM_8AND16BIT (2<<3)
#define ID_ISAR1_EL1_Except_AR_IMP UL(0b0001)
#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
#define QC_RT_SPC_SOFT (1<<4)
#define SECCOMP_IOWR(nr,type) _IOWR(SECCOMP_IOC_MAGIC, nr, type)
#define SYS_ID_AA64MMFR3_EL1_Op0 3
#define QTYPE_MASK_PRJ (1 << PRJQUOTA)
#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | ESR_ELx_SYS64_ISS_OP1_MASK | ESR_ELx_SYS64_ISS_OP2_MASK | ESR_ELx_SYS64_ISS_CRN_MASK | ESR_ELx_SYS64_ISS_CRM_MASK)
#define cpu_to_le32 __cpu_to_le32
#define SYS_ID_AA64MMFR3_EL1_Op1 0
#define ifr_dstaddr ifr_ifru.ifru_dstaddr
#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
#define _LINUX_KSTRTOX_H 
#define FMODE_CAN_ODIRECT ((__force fmode_t)0x400000)
#define PMSG_USER_RESUME ((struct pm_message) { .event = PM_EVENT_USER_RESUME, })
#define PR_GET_MEMORY_MERGE 68
#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
#define HFGxTR_EL2_CCSIDR_EL1_MASK GENMASK(9, 9)
#define compound_head(page) ((typeof(page))_compound_head(page))
#define TAINT_USER 6
#define SYS_SMCR_EL12_Op0 3
#define SYS_SMCR_EL12_Op1 5
#define CONFIG_OF_IOMMU 1
#define SIOCOUTQ TIOCOUTQ
#define ID_AA64PFR1_EL1_MTE_MASK GENMASK(11, 8)
#define dev_info(dev,fmt,...) dev_printk_index_wrap(_dev_info, KERN_INFO, dev, dev_fmt(fmt), ##__VA_ARGS__)
#define sve_cond_update_zcr_vq(val,reg) do { } while (0)
#define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1)
#define raw_try_cmpxchg64_acquire(_ptr,_oldp,_new) ({ typeof(*(_ptr)) *___op = (_oldp), ___o = *___op, ___r; ___r = raw_cmpxchg64_acquire((_ptr), ___o, (_new)); if (unlikely(___r != ___o)) *___op = ___r; likely(___r == ___o); })
#define KUNIT_EXPECT_NOT_ERR_OR_NULL_MSG(test,ptr,fmt,...) KUNIT_PTR_NOT_ERR_OR_NULL_MSG_ASSERTION(test, KUNIT_EXPECTATION, ptr, fmt, ##__VA_ARGS__)
#define PTRACE_MODE_ATTACH 0x02
#define KERNEL_HWCAP_DGH __khwcap2_feature(DGH)
#define ETHTOOL_COALESCE_RX_USECS_HIGH BIT(17)
#define S_NOSEC (1 << 12)
#define EV_NUM 2
#define SVE_PT_SVE_PREGS_SIZE(vq) (SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - SVE_PT_SVE_PREGS_OFFSET(vq))
#define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
#define __ILL_BREAK 10
#define ETIME 62
#define PMSLATFR_EL1_MINLAT_WIDTH 16
#define HFGxTR_EL2_ESR_EL1_WIDTH 1
#define ID_AA64MMFR1_EL1_TIDCP1_NI UL(0b0000)
#define DECLARE_SWAIT_QUEUE_HEAD_ONSTACK(name) struct swait_queue_head name = __SWAIT_QUEUE_HEAD_INIT_ONSTACK(name)
#define HFGITR_EL2_DCZVA_SHIFT 11
#define _test_bit arch_test_bit
#define PR_GET_TSC 25
#define FS_FL_USER_MODIFIABLE 0x000380FF
#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
#define typecheck(type,x) ({ type __dummy; typeof(x) __dummy2; (void)(&__dummy == &__dummy2); 1; })
#define XATTR_NAME_MAX 255
#define CCSIDR_EL1_LineSize_WIDTH 3
#define request_mem_region_muxed(start,n,name) __request_region(&iomem_resource, (start), (n), (name), IORESOURCE_MUXED)
#define KERN_SOH_ASCII '\001'
#define IFF_DYNAMIC IFF_DYNAMIC
#define raw_cpu_sub(pcp,val) raw_cpu_add(pcp, -(val))
#define HFGITR_EL2_TLBIRVAE1IS_WIDTH 1
#define SO_PRIORITY 12
#define __SEMAPHORE_INITIALIZER(name,n) { .lock = __RAW_SPIN_LOCK_UNLOCKED((name).lock), .count = n, .wait_list = LIST_HEAD_INIT((name).wait_list), }
#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
#define ID_AA64MMFR1_EL1_ECBHB_WIDTH 4
#define CTR_EL0_ERG_SHIFT 20
#define read_sysreg(r) ({ u64 __val; asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); __val; })
#define kcsan_mb() do { } while (0)
#define for_each_irq_desc_reverse(irq,desc) for (irq = nr_irqs - 1, desc = irq_to_desc(irq); irq >= 0; irq--, desc = irq_to_desc(irq)) if (!desc) ; else
#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
#define __ASM_INSN_H 
#define cpu_to_le64 __cpu_to_le64
#define phy_module_driver(__phy_drivers,__count) static int __init phy_module_init(void) { return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); } module_init(phy_module_init); static void __exit phy_module_exit(void) { phy_drivers_unregister(__phy_drivers, __count); } module_exit(phy_module_exit)
#define ID_AA64MMFR0_EL1_TGRAN4_2_MASK GENMASK(43, 40)
#define nodes_intersects(src1,src2) __nodes_intersects(&(src1), &(src2), MAX_NUMNODES)
#define KUNIT_ASSERT_STRNEQ(test,left,right) KUNIT_ASSERT_STRNEQ_MSG(test, left, right, NULL)
#define synchronize_rcu_tasks synchronize_rcu
#define ARCH_TIMER_VIRT_EVT_EN (1 << 2)
#define for_each_numa_hop_mask(mask,node) for (unsigned int __hops = 0; mask = (node != NUMA_NO_NODE || __hops) ? sched_numa_hop_mask(node, __hops) : cpu_online_mask, !IS_ERR_OR_NULL(mask); __hops++)
#define TLBI_RANGE_MASK GENMASK_ULL(4, 0)
#define ID_AA64MMFR2_EL1_AT_IMP UL(0b0001)
#define GETPID 11
#define PRIO_MAX 20
#define KERNEL_HWCAP_DIT __khwcap_feature(DIT)
#define SIOCDIFADDR 0x8936
#define ID_ISAR6_EL1_I8MM_WIDTH 4
#define ETHTOOL_COALESCE_MAX_FRAMES (ETHTOOL_COALESCE_RX_MAX_FRAMES | ETHTOOL_COALESCE_TX_MAX_FRAMES)
#define MII_MMD_CTRL_INCR_ON_WT 0xC000
#define HFGITR_EL2_ATS1E0R_WIDTH 1
#define ID_AA64MMFR2_EL1_VARange_MASK GENMASK(19, 16)
#define HFGxTR_EL2_nGCS_EL0_SHIFT 52
#define topology_drawer_id(cpu) ((void)(cpu), -1)
#define ID_MMFR3_EL1_CMaintSW_WIDTH 4
#define PMSCR_EL1_CX GENMASK(3, 3)
#define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
#define DEFINE_WAIT_FUNC(name,function) struct wait_queue_entry name = { .private = current, .func = function, .entry = LIST_HEAD_INIT((name).entry), }
#define ARM64_WORKAROUND_1418040 69
#define HFGxTR_EL2_LORSA_EL1_SHIFT 23
#define ETH_P_ARCNET 0x001A
#define IIF_IGRACE 2
#define ID_AA64ISAR2_EL1_MOPS GENMASK(19, 16)
#define EM_MICROBLAZE 189
#define cond_resched_tasks_rcu_qs() do { rcu_tasks_qs(current, false); cond_resched(); } while (0)
#define OSLSR_EL1_OSLM_NI 0
#define CONFIG_TRACE_IRQFLAGS_NMI 1
#define CAVIUM_CPU_PART_THUNDERX2 0x0AF
#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1)
#define PIPE_BUF 4096
#define idr_for_each_entry(idr,entry,id) for (id = 0; ((entry) = idr_get_next(idr, &(id))) != NULL; id += 1U)
#define __BIN_ATTR_RW(_name,_size) __BIN_ATTR(_name, 0644, _name ##_read, _name ##_write, _size)
#define TIMER_DEFERRABLE 0x00080000
#define type_min(T) ((T)((T)-type_max(T)-(T)1))
#define SIOCGIFMTU 0x8921
#define ADVERTISE_1000XPSE_ASYM 0x0100
#define TCR2_EL2_RES0 (UL(0) | GENMASK_ULL(63, 16))
#define TCR2_EL2_RES1 (UL(0))
#define SVE_PT_SVE_FFR_OFFSET(vq) (SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
#define HDFGRTR_EL2_PMCCFILTR_EL0_WIDTH 1
#define EM_PERF_DOMAIN_ARTIFICIAL BIT(2)
#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
#define _ASM_GENERIC_CACHEFLUSH_H 
#define NOTIFY_OK 0x0001
#define NODE_MASK_NONE ((nodemask_t) { { [0 ... BITS_TO_LONGS(MAX_NUMNODES)-1] = 0UL } })
#define CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST 1
#define S32_MIN ((s32)(-S32_MAX - 1))
#define ID_MMFR1_EL1_L1HvdVA_MASK GENMASK(3, 0)
#define SYS_PMBLIMITR_EL1_Op2 0
#define SMPRIMAP_EL2_P0_MASK GENMASK(3, 0)
#define ID_AA64SMFR0_EL1_FA64_SIGNED false
#define DCACHE_REGULAR_TYPE 0x00400000
#define HFGITR_EL2_COSPRCTX_MASK GENMASK(60, 60)
#define CONFIG_HAVE_CMPXCHG_LOCAL 1
#define IPV6_FREEBIND 78
#define p4d_access_permitted(p4d,write) (p4d_present(p4d) && (!(write) || p4d_write(p4d)))
#define IORESOURCE_BUS 0x00001000
#define ID_AA64ISAR0_EL1_TLB_NI UL(0b0000)
#define ftrace_set_filter_ips(ops,ips,cnt,remove,reset) ({ -ENODEV; })
#define NETIF_F_ONE_FOR_ALL (NETIF_F_GSO_SOFTWARE | NETIF_F_GSO_ROBUST | NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | NETIF_F_VLAN_CHALLENGED)
#define ID_AA64PFR0_EL1_FP_SHIFT 16
#define PT_OPT_FLAG_SHIFT 3
#define ID_AA64MMFR0_EL1_ECV_IMP UL(0b0001)
#define FAR_EL12_ADDR_WIDTH 64
#define pte_ERROR(e) pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
#define ISR_EL1_UNKN (UL(0))
#define _IOC_NRBITS 8
#define S_IFBLK 0060000
#define EBADTYPE 527
#define _LINUX_IOPORT_H 
#define VM_GROWSUP VM_NONE
#define HCRX_EL2_EnALS_WIDTH 1
#define SCTLR_EL1_LSMAOE_SHIFT 29
#define ETHTOOL_COALESCE_PKT_RATE_HIGH BIT(16)
#define lockdep_hardirqs_enabled() (this_cpu_read(hardirqs_enabled))
#define raw_cpu_generic_try_cmpxchg(pcp,ovalp,nval) ({ typeof(pcp) *__p = raw_cpu_ptr(&(pcp)); typeof(pcp) __val = *__p, ___old = *(ovalp); bool __ret; if (__val == ___old) { *__p = nval; __ret = true; } else { *(ovalp) = __val; __ret = false; } __ret; })
#define MVFR0_EL1_FPSP_VFPv3 UL(0b0010)
#define ID_AA64SMFR0_EL1_F32F32 GENMASK(32, 32)
#define CONFIG_BLOCK 1
#define ID_AA64ISAR0_EL1_TLB_OS UL(0b0001)
#define get_cpu_var(var) (*({ preempt_disable(); this_cpu_ptr(&var); }))
#define HAVE_ARCH_BUG 
#define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? cpu_all_mask : cpumask_of_node(pcibus_to_node(bus)))
#define HDFGWTR_EL2_TRCPRGCTLR GENMASK(44, 44)
#define ID_AA64MMFR2_EL1_IDS_0x0 UL(0b0000)
#define ID_ISAR2_EL1_LoadStore_NI UL(0b0000)
#define F_OWNER_PID 1
#define ELF_ST_BIND(x) ((x) >> 4)
#define HDFGWTR_EL2_PMSEVFR_EL1_MASK GENMASK(27, 27)
#define SCTLR_EL1_RES1 (UL(0))
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
#define lockdep_assert_not_held(l) lockdep_assert(lockdep_is_held(l) != LOCK_STATE_HELD)
#define __must_hold(x) 
#define TRBLIMITR_EL1_LIMIT GENMASK(63, 12)
#define wake_up_interruptible_all(x) __wake_up(x, TASK_INTERRUPTIBLE, 0, NULL)
#define ID_AA64MMFR3_EL1_Spec_FPACC_NI UL(0b0000)
#define csum_fold csum_fold
#define HDFGRTR_EL2_PMSLATFR_EL1_WIDTH 1
#define TYPECHECK_H_INCLUDED 
#define xa_limit_31b XA_LIMIT(0, INT_MAX)
#define rb_entry_safe(ptr,type,member) ({ typeof(ptr) ____ptr = (ptr); ____ptr ? rb_entry(____ptr, type, member) : NULL; })
#define SYS_ID_AA64PFR0_EL1_CRm 4
#define JOBCTL_PTRACE_FROZEN_BIT 24
#define ETHTOOL_FEC_LLRS (1 << ETHTOOL_FEC_LLRS_BIT)
#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
#define __section(section) __attribute__((__section__(section)))
#define _LINUX_WORKQUEUE_H 
#define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
#define HDFGWTR_EL2_TRCIMSPECn GENMASK(41, 41)
#define EM_SPU 23
#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
#define ID_AA64PFR0_EL1_AMU GENMASK(47, 44)
#define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
#define SHT_NOTE 7
#define CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT 1
#define __ASM_ALTERNATIVE_MACROS_H 
#define CONFIG_HAVE_ARCH_SECCOMP_FILTER 1
#define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
#define TCR_ORGN0_SHIFT 10
#define ASM_NL ;
#define SRCU_SIZE_BIG 8
#define ID_AA64SMFR0_EL1_F32F32_SIGNED false
#define SCTLR_EL1_UMA_MASK GENMASK(9, 9)
#define _DEFINE_STATIC_KEY_RO_0(name) DEFINE_STATIC_KEY_FALSE_RO(name)
#define _DEFINE_STATIC_KEY_RO_1(name) DEFINE_STATIC_KEY_TRUE_RO(name)
#define ID_AA64MMFR3_EL1_UNKN (UL(0))
#define CLIDR_EL1_Ctype6_WIDTH 3
#define SYS_GETPEERNAME 7
#define SEQCNT_SPINLOCK_ZERO(name,lock) SEQCOUNT_LOCKNAME_ZERO(name, lock)
#define MSG_TRUNC 0x20
#define REG_ID_AFR0_EL1 S3_0_C0_C1_3
#define ID_ISAR1_EL1_Interwork_SHIFT 24
#define HDFGRTR_EL2_OSECCR_EL1_SHIFT 10
#define HCRX_EL2_PTTWI_SHIFT 16
#define IOPRIO_PRIO_LEVEL(ioprio) ((ioprio) & IOPRIO_LEVEL_MASK)
#define EPOLLPRI (__force __poll_t)0x00000002
#define PT_LOAD 1
#define _UAPI_LINUX_ELF_H 
#define SMPRIMAP_EL2_P12_WIDTH 4
#define _LINUX_CACHEFLUSH_H 
#define VM_MAYWRITE 0x00000020
#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
#define __HDLC_IOCTL_H__ 
#define STATIC_CALL_KEY(name) __PASTE(STATIC_CALL_KEY_PREFIX, name)
#define ioremap_uc ioremap_uc
#define CONFIG_DEBUG_MISC 1
#define ID_MMFR2_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_MMFR2_EL1_RES1 (UL(0))
#define __NR_set_mempolicy 237
#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
#define for_each_vma(__vmi,__vma) while (((__vma) = vma_next(&(__vmi))) != NULL)
#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
#define Elf_Ehdr Elf64_Ehdr
#define SOFTIRQ_BITS 8
#define NSIGFPE 15
#define PAGE_FLAGS_PRIVATE (1UL << PG_private | 1UL << PG_private_2)
#define TIF_SINGLESTEP 21
#define HDFGRTR_EL2_PMCEIDn_EL0_SHIFT 58
#define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
#define ID_AA64DFR0_EL1_TraceFilt_MASK GENMASK(43, 40)
#define ATTR_KILL_SGID (1 << 12)
#define PIRx_ELx_Perm0_SHIFT 0
#define HFGxTR_EL2_nPIR_EL1_SHIFT 58
#define __le64_to_cpu(x) ((__force __u64)(__le64)(x))
#define __is_defined(x) ___is_defined(x)
#define __seqprop(s,prop) _Generic(*(s), seqcount_t: __seqprop_ ##prop, __seqprop_case((s), raw_spinlock, prop), __seqprop_case((s), spinlock, prop), __seqprop_case((s), rwlock, prop), __seqprop_case((s), mutex, prop))
#define F_SETLK64 13
#define ID_DFR0_EL1_TraceFilt GENMASK(31, 28)
#define CONFIG_SND_JACK 1
#define LED_FUNCTION_NUMLOCK "numlock"
#define __ASM_GENERIC_QSPINLOCK_TYPES_H 
#define HFGITR_EL2_TLBIRVAALE1OS_SHIFT 27
#define HWCAP2_SME_F64F64 (1 << 25)
#define RB_EMPTY_ROOT(root) (READ_ONCE((root)->rb_node) == NULL)
#define __page_aligned_data __section(".data..page_aligned") __aligned(PAGE_SIZE)
#define __UAPI_DEF_XATTR 1
#define BMSR_ERCAP 0x0001
#define __NR_clock_gettime 113
#define __smp_processor_id(x) raw_smp_processor_id(x)
#define ID_AA64ISAR2_EL1_RPRES_SIGNED false
#define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
#define LED_RETAIN_AT_SHUTDOWN BIT(22)
#define RLIMIT_CORE 4
#define PTE_RDONLY (_AT(pteval_t, 1) << 7)
#define CONFIG_XZ_DEC_POWERPC 1
#define SHT_STRTAB 3
#define STATIC_CALL_KEY_STR(name) __stringify(STATIC_CALL_KEY(name))
#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
#define HFGxTR_EL2_RES0 (UL(0) | GENMASK_ULL(51, 51))
#define HFGxTR_EL2_RES1 (UL(0))
#define HCRX_EL2_FGTnXS_WIDTH 1
#define PAGE_FLAGS_H 
#define MIN_THREADS_LEFT_FOR_ROOT 4
#define CLIDR_EL1_ICB_MASK GENMASK(32, 30)
#define CONFIG_NET_VENDOR_8390 1
#define STACK_MAGIC 0xdeadbeef
#define AF_IEEE802154 36
#define PIDS_PER_CPU_DEFAULT 1024
#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
#define _LINUX_BITFIELD_H 
#define HFGITR_EL2_TLBIVMALLE1OS_SHIFT 18
#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
#define ID_AA64SMFR0_EL1_B16B16_IMP UL(0b1)
#define FOLIO_PF_ANY 0
#define MAX_CPU_FEATURES 128
#define DEFINE_SIMPLE_ATTRIBUTE_XSIGNED(__fops,__get,__set,__fmt,__is_signed) static int __fops ## _open(struct inode *inode, struct file *file) { __simple_attr_check_format(__fmt, 0ull); return simple_attr_open(inode, file, __get, __set, __fmt); } static const struct file_operations __fops = { .owner = THIS_MODULE, .open = __fops ## _open, .release = simple_attr_release, .read = simple_attr_read, .write = (__is_signed) ? simple_attr_write_signed : simple_attr_write, .llseek = generic_file_llseek, }
#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
#define __LINUX_LEDS_H_INCLUDED 
#define TIF_TAGGED_ADDR 26
#define IFF_UP IFF_UP
#define SDIO_ANY_ID (~0)
#define ID_AA64SMFR0_EL1_F16F16_SIGNED false
#define __cpumask_var_read_mostly 
#define pte_pi_index(pte) ( ((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_IDX_3 - 3)) | ((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_IDX_2 - 2)) | ((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_IDX_1 - 1)) | ((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_IDX_0 - 0)))
#define CONFIG_CC_HAS_ASM_GOTO_OUTPUT 1
#define SYS_CNTPOFF_EL2_CRn 14
#define SMPRIMAP_EL2_P6_WIDTH 4
#define SB_NODEV BIT(2)
#define kunit_printk(lvl,test,fmt,...) kunit_log(lvl, test, KUNIT_SUBTEST_INDENT "# %s: " fmt, (test)->name, ##__VA_ARGS__)
#define ID_PFR0_EL1_AMU_WIDTH 4
#define KERNEL_HWCAP_SVEAES __khwcap2_feature(SVEAES)
#define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3)
#define ID_AA64ZFR0_EL1_SHA3_MASK GENMASK(35, 32)
#define phydev_dbg(_phydev,format,args...) dev_dbg(&_phydev->mdio.dev, format, ##args)
#define _LINUX_KCSAN_CHECKS_H 
#define CONFIG_CC_IS_GCC 1
#define or_softirq_pending(x) (__this_cpu_or(local_softirq_pending_ref, (x)))
#define ioport_unmap ioport_unmap
#define HDFGWTR_EL2_TRBTRG_EL1 GENMASK(56, 56)
#define list_prepare_entry(pos,head,member) ((pos) ? : list_entry(head, typeof(*pos), member))
#define HFGxTR_EL2_TPIDR_EL0_SHIFT 35
#define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l))
#define IOPRIO_PRIO_VALUE(prioclass,priolevel) ioprio_value(prioclass, priolevel, IOPRIO_HINT_NONE)
#define EUCLEAN 117
#define TRBTRG_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define TRBTRG_EL1_RES1 (UL(0))
#define PTRACE_MODE_ATTACH_REALCREDS (PTRACE_MODE_ATTACH | PTRACE_MODE_REALCREDS)
#define __free_page(page) __free_pages((page), 0)
#define __device_lock_set_class(dev,name,key) do { struct device *__d2 __maybe_unused = dev; lock_set_class(&__d2->mutex.dep_map, name, key, 0, _THIS_IP_); } while (0)
#define raw_spin_lock_irqsave(lock,flags) do { typecheck(unsigned long, flags); flags = _raw_spin_lock_irqsave(lock); } while (0)
#define HFGITR_EL2_TLBIVAAE1_WIDTH 1
#define raw_spin_lock_nest_lock(lock,nest_lock) do { typecheck(struct lockdep_map *, &(nest_lock)->dep_map); _raw_spin_lock_nest_lock(lock, &(nest_lock)->dep_map); } while (0)
#define writeq writeq
#define __RWSEM_INITIALIZER(name) { __RWSEM_COUNT_INIT(name), .owner = ATOMIC_LONG_INIT(0), __RWSEM_OPT_INIT(name) .wait_lock = __RAW_SPIN_LOCK_UNLOCKED(name.wait_lock), .wait_list = LIST_HEAD_INIT((name).wait_list), __RWSEM_DEBUG_INIT(name) __RWSEM_DEP_MAP_INIT(name) }
#define fs_param_cb(name,ops,arg,perm) __level_param_cb(name, ops, arg, perm, 5)
#define PF_IRDA AF_IRDA
#define ID_ISAR3_EL1_SVC_IMP UL(0b0001)
#define FS_XFLAG_SYNC 0x00000020
#define MMF_OOM_REAP_QUEUED 25
#define IS_DIRSYNC(inode) (__IS_FLG(inode, SB_SYNCHRONOUS|SB_DIRSYNC) || ((inode)->i_flags & (S_SYNC|S_DIRSYNC)))
#define ID_AA64MMFR1_EL1_PAN_SIGNED false
#define CSD_INIT(_func,_info) (struct __call_single_data){ .func = (_func), .info = (_info), }
#define print_dev_t(buffer,dev) sprintf((buffer), "%u:%u\n", MAJOR(dev), MINOR(dev))
#define SMIDR_EL1_IMPLEMENTER_SHIFT 24
#define __GIC_PRIO_IRQOFF_NS 0xa0
#define PHY_F_NO_IRQ 0x80000000
#define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
#define bitmap_to_arr64(buf,bitmap,nbits) bitmap_copy_clear_tail((unsigned long *)(buf), (const unsigned long *)(bitmap), (nbits))
#define REG_TRBLIMITR_EL1 S3_0_C9_C11_0
#define SUPPORTED_56000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseCR4_Full)
#define SCHED_BATCH 3
#define _LINUX_PAGE_REF_H 
#define ICH_LR_ACTIVE_BIT (1ULL << 63)
#define ARCH_TIMER_MEM_PHYS_ACCESS 2
#define AARCH32_BREAK_ARM 0x07f001f0
#define TASK_PFA_TEST(name,func) static inline bool task_ ##func(struct task_struct *p) { return test_bit(PFA_ ##name, &p->atomic_flags); }
#define STA_FLL 0x0008
#define FIBMAP _IO(0x00,1)
#define ID_AA64MMFR2_EL1_LSM_IMP UL(0b0001)
#define PSR_AA32_T_BIT 0x00000020
#define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
#define HWCAP2_MTE3 (1 << 22)
#define _LINUX_PFN_H_ 
#define ID_MMFR1_EL1_L1UniVA_NI UL(0b0000)
#define SYS_ID_AA64ISAR0_EL1_CRn 0
#define CONFIG_NET_VENDOR_MYRI 1
#define TRBLIMITR_EL1_TM_STOP UL(0b00)
#define HFGxTR_EL2_ERRIDR_EL1_WIDTH 1
#define GLOBAL_ROOT_UID KUIDT_INIT(0)
#define RLIMIT_RSS 5
#define __bvec_iter_bvec(bvec,iter) (&(bvec)[(iter).bi_idx])
#define SZ_512 0x00000200
#define MDIO_PMA_PMD_BT1_B1000_ABLE 0x0002
#define HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT 52
#define FAULT_FLAG_TRACE { FAULT_FLAG_WRITE, "WRITE" }, { FAULT_FLAG_MKWRITE, "MKWRITE" }, { FAULT_FLAG_ALLOW_RETRY, "ALLOW_RETRY" }, { FAULT_FLAG_RETRY_NOWAIT, "RETRY_NOWAIT" }, { FAULT_FLAG_KILLABLE, "KILLABLE" }, { FAULT_FLAG_TRIED, "TRIED" }, { FAULT_FLAG_USER, "USER" }, { FAULT_FLAG_REMOTE, "REMOTE" }, { FAULT_FLAG_INSTRUCTION, "INSTRUCTION" }, { FAULT_FLAG_INTERRUPTIBLE, "INTERRUPTIBLE" }, { FAULT_FLAG_VMA_LOCK, "VMA_LOCK" }
#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
#define O_CREAT 00000100
#define MTE_CTRL_TCF_ASYNC (1UL << 17)
#define ID_PFR1_EL1_ProgMod_SIGNED false
#define HFGxTR_EL2_nPIRE0_EL1_MASK GENMASK(57, 57)
#define SA_RESTART 0x10000000
#define __unique_initcall(fn,id,__sec,__iid) ____define_initcall(fn, __initcall_stub(fn, __iid, id), __initcall_name(initcall, __iid, id), __initcall_section(__sec, __iid))
#define ENODEV 19
#define _LINUX_SHRINKER_H 
#define SIOCGIFMEM 0x891f
#define ID_ISAR4_EL1_SMC_NI UL(0b0000)
#define POLL_OUT 2
#define LRU_ACTIVE 1
#define __ASM_PGTABLE_H 
#define CONFIG_ARCH_WANT_DEFAULT_BPF_JIT 1
#define _LINUX_OBJPOOL_H 
#define KERNEL_HWCAP_DCPOP __khwcap_feature(DCPOP)
#define HCR_TLOR (UL(1) << 35)
#define __take_second_arg(__ignored,val,...) val
#define ESR_ELx_EC_BREAKPT_CUR (0x31)
#define MDSCR_EL1_SC2_MASK GENMASK(19, 19)
#define skb_rbtree_walk(skb,root) for (skb = skb_rb_first(root); skb != NULL; skb = skb_rb_next(skb))
#define trace_preempt_on(a0,a1) do { } while (0)
#define idr_unlock(idr) xa_unlock(&(idr)->idr_rt)
#define SVCR_UNKN (UL(0))
#define ID_AA64ISAR1_EL1_FRINTTS_NI UL(0b0000)
#define __deprecated 
#define FAR_EL1_UNKN (UL(0))
#define write_trylock(lock) __cond_lock(lock, _raw_write_trylock(lock))
#define MVFR2_EL1_UNKN (UL(0))
#define CPU_MASK_CPU0 (cpumask_t) { { [0] = 1UL } }
#define ARM64_HAS_DCPOP 16
#define __ARCH_COMPAT_FLOCK64_PACK 
#define SYS_FAR_EL1_CRn 6
#define put_cpu_ptr(var) do { (void)(var); preempt_enable(); } while (0)
#define ID_AA64MMFR1_EL1_PAN_PAN2 UL(0b0010)
#define __ETHTOOL_LINK_MODE_LEGACY_MASK(base_name) (1UL << (ETHTOOL_LINK_MODE_ ## base_name ## _BIT))
#define NMI_OFFSET (1UL << NMI_SHIFT)
#define LOREA_EL1_EA_51_48_MASK GENMASK(51, 48)
#define RWF_SYNC ((__force __kernel_rwf_t)0x00000004)
#define SCTLR_EL1_CMOW_WIDTH 1
#define SCTLR_ELx_LSMAOE (BIT(29))
#define EKEYEXPIRED 127
#define static_key_slow_inc_cpuslocked(key) static_key_slow_inc(key)
#define ETHTOOL_GFLAGS 0x00000025
#define _UAPI_LINUX_IN6_H 
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
#define __cond_lock(x,c) (c)
#define ETH_P_ETHERCAT 0x88A4
#define ESR_ELx_EC_SMC32 (0x13)
#define O_DIRECT 0200000
#define BLKTRACESETUP _IOWR(0x12,115,struct blk_user_trace_setup)
#define SYS_FAR_EL2_Op0 3
#define CCW_DEVICE_ID_MATCH_DEVICE_TYPE 0x04
#define NT_ARM_HW_WATCH 0x403
#define AF_PHONET 35
#define ID_ISAR3_EL1_T32EE_WIDTH 4
#define ID_ISAR6_EL1_SPECRES_SHIFT 16
#define __smp_mb() dmb(ish)
#define EM_DATA_CB(_active_power_cb) { }
#define HFGITR_EL2_TLBIRVAAE1IS_WIDTH 1
#define PG_table 0x00000200
#define SYS_FAR_EL2_Op1 4
#define RADIX_TREE_ENTRY_MASK 3UL
#define LORN_EL1_Num_SHIFT 0
#define HWEIGHT(w) HWEIGHT64((u64)w)
#define KUNIT_EXPECT_PTR_NE_MSG(test,left,right,fmt,...) KUNIT_BINARY_PTR_ASSERTION(test, KUNIT_EXPECTATION, left, !=, right, fmt, ##__VA_ARGS__)
#define MINSIGSTKSZ 5120
#define DEBUG_NET_WARN_ON_ONCE(cond) BUILD_BUG_ON_INVALID(cond)
#define HSIPHASH_CONST_1 0U
#define HSIPHASH_CONST_2 0x6c796765U
#define IOCB_DIRECT (1 << 17)
#define le64_to_cpu __le64_to_cpu
#define DT_REG 8
#define NUMREGBYTES ((_GP_REGS * 8) + (_FP_REGS * 16) + (_EXTRA_REGS * 4))
#define QC_SPACE (1<<12)
#define ETH_P_MAP 0x00F9
#define PMSCR_EL1_TS GENMASK(5, 5)
#define ID_MMFR4_EL1_EVT_MASK GENMASK(31, 28)
#define CONFIG_GENERIC_GETTIMEOFDAY 1
#define SECCOMP_ADDFD_FLAG_SEND (1UL << 1)
#define SCTLR_EL1_EnDB_WIDTH 1
#define ID_AA64PFR1_EL1_SSBS_SHIFT 4
#define CPACR_ELx_TTA_MASK GENMASK(28, 28)
#define ID_AA64AFR0_EL1_IMPDEF5_SHIFT 20
#define xa_lock_bh(xa) spin_lock_bh(&(xa)->xa_lock)
#define ID_AA64DFR1_EL1_UNKN (UL(0))
#define P_PGID 2
#define plist_for_each_continue(pos,head) list_for_each_entry_continue(pos, &(head)->node_list, node_list)
#define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
#define RCU_FANOUT_LEAF 16
#define SYS_PMSIDR_EL1_Op0 3
#define HDFGRTR_EL2_PMEVCNTRn_EL0_MASK GENMASK(12, 12)
#define ETH_P_IPV6 0x86DD
#define ID_PFR2_EL1_RAS_frac_MASK GENMASK(11, 8)
#define MTE_CTRL_TCF_SYNC (1UL << 16)
#define FT_BLKDEV 4
#define DT_BLK 6
#define HDFGWTR_EL2_TRBSR_EL1_MASK GENMASK(55, 55)
#define SCTLR_EL1_SA0_WIDTH 1
#define __PGTBL_PGD_MODIFIED 0
#define PMSIDR_EL1_PBT_SHIFT 24
#define ID_ISAR1_EL1_UNKN (UL(0))
#define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
#define PSR_N_BIT 0x80000000
#define CONFIG_HAVE_ARCH_HUGE_VMALLOC 1
#define __TLBI_VADDR_RANGE(addr,asid,scale,num,ttl) ({ unsigned long __ta = (addr) >> PAGE_SHIFT; __ta &= GENMASK_ULL(36, 0); __ta |= (unsigned long)(ttl) << 37; __ta |= (unsigned long)(num) << 39; __ta |= (unsigned long)(scale) << 44; __ta |= get_trans_granule() << 46; __ta |= (unsigned long)(asid) << 48; __ta; })
#define ELF_ST_TYPE(x) ((x) & 0xf)
#define _AT(T,X) ((T)(X))
#define EHWPOISON 133
#define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK)
#define __GFP_DMA ((__force gfp_t)___GFP_DMA)
#define SO_SNDBUF 7
#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
#define SCHED_FLAG_KEEP_ALL (SCHED_FLAG_KEEP_POLICY | SCHED_FLAG_KEEP_PARAMS)
#define CONFIG_HAVE_ARCH_KASAN_VMALLOC 1
#define HDFGRTR_EL2_TRCSSCSRn GENMASK(46, 46)
#define phys_to_page(phys) (pfn_to_page(__phys_to_pfn(phys)))
#define PMBIDR_EL1_EA GENMASK(11, 8)
#define TRBIDR_EL1_Align GENMASK(3, 0)
#define NSIGCHLD 6
#define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
#define SCTLR_EL1_nTWE GENMASK(18, 18)
#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
#define CONFIG_NET_PTP_CLASSIFY 1
#define _LINUX_UPROBES_H 
#define INPUT_DEVICE_ID_SND_MAX 0x07
#define hlist_pprev_rcu(node) (*((struct hlist_node __rcu **)((node)->pprev)))
#define SIGXFSZ 25
#define MDCR_EL2_TDA (UL(1) << 9)
#define SVCR_ZA_MASK GENMASK(1, 1)
#define ID_AA64PFR0_EL1_MPAM_SHIFT 40
#define PT_INTERP 3
#define PR_SET_KEEPCAPS 8
#define DBG_ESR_EVT(x) (((x) >> 27) & 0x7)
#define SCTLR_EL1_SPINTMASK_SHIFT 62
#define SIGHUP 1
#define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
#define HFGITR_EL2_ATS1E1R_MASK GENMASK(12, 12)
#define TESTCLEARFLAG(uname,lname,policy) static __always_inline bool folio_test_clear_ ##lname(struct folio *folio) { return test_and_clear_bit(PG_ ##lname, folio_flags(folio, FOLIO_ ##policy)); } static __always_inline int TestClearPage ##uname(struct page *page) { return test_and_clear_bit(PG_ ##lname, &policy(page, 1)->flags); }
#define AT_NULL 0
#define GPIO_LED_BLINK 2
#define SKB_DATAREF_SHIFT 16
#define XA_FLAGS_ZERO_BUSY ((__force gfp_t)8U)
#define dev_info_ratelimited(dev,fmt,...) dev_level_ratelimited(dev_info, dev, fmt, ##__VA_ARGS__)
#define ID_DFR1_EL1_MTPMU_NI UL(0b1111)
#define local_set(l,i) atomic_long_set((&(l)->a),(i))
#define PT_LOOS 0x60000000
#define HDFGRTR_EL2_TRCSTATR GENMASK(47, 47)
#define PMSFCR_EL1_FT_WIDTH 1
#define KUNIT_CASE_PARAM(test_name,gen_params) { .run_case = test_name, .name = #test_name, .generate_params = gen_params, .module_name = KBUILD_MODNAME}
#define NUM_RCU_NODES (NUM_RCU_LVL_0 + NUM_RCU_LVL_1)
#define SIGEV_MAX_SIZE 64
#define MDIO_USXGMII_2500 0x0800
#define HFGxTR_EL2_AIDR_EL1_WIDTH 1
#define __LINUX_BOUNDS_H__ 
#define BLKSECTSET _IO(0x12,102)
#define PMSIDR_EL1_LDS_WIDTH 1
#define INPUT_DEVICE_ID_PROP_MAX 0x1f
#define read_task_thread_flags(t) read_ti_thread_flags(task_thread_info(t))
#define ID_AA64SMFR0_EL1_SMEver_SME2 UL(0b0001)
#define TRBLIMITR_EL1_FM_WRAP UL(0b01)
#define CONFIG_SND_SOC_I2C_AND_SPI 1
#define AT_SYMLINK_NOFOLLOW 0x100
#define PR_UNALIGN_SIGBUS 2
#define SVE_SIG_FFR_OFFSET(vq) (SVE_SIG_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
#define CONFIG_ARCH_SUPPORTS_NUMA_BALANCING 1
#define HDFGRTR_EL2_PMSIRR_EL1_SHIFT 31
#define ETHTOOL_COALESCE_TX_MAX_FRAMES_HIGH BIT(20)
#define fs_initcall_sync(fn) __define_initcall(fn, 5s)
#define ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF 32
#define SCTLR_EL1_TWEDEn_WIDTH 1
#define __PGTBL_PUD_MODIFIED 2
#define ICH_VMCR_BPR1_SHIFT 18
#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
#define HWCAP_SM3 (1 << 18)
#define HWCAP_SM4 (1 << 19)
#define wmark_pages(z,i) (z->_watermark[i] + z->watermark_boost)
#define mas_unlock(mas) spin_unlock(&((mas)->tree->ma_lock))
#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
#define ENCODE_PAGE_BITS 3ul
#define KUNIT_EXPECT_STREQ_MSG(test,left,right,fmt,...) KUNIT_BINARY_STR_ASSERTION(test, KUNIT_EXPECTATION, left, ==, right, fmt, ##__VA_ARGS__)
#define Op2_shift 5
#define XATTR_CAPS_SZ_2 (sizeof(__le32)*(1 + 2*VFS_CAP_U32_2))
#define __NR_accept4 242
#define ILL_ILLTRP 4
#define __tsb_csync() asm volatile("hint #18" : : : "memory")
#define TRBIDR_EL1_EA_MASK GENMASK(11, 8)
#define UBSAN_BRK_MASK 0x00ff
#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
#define user_access_end() do { } while (0)
#define __DELAYED_WORK_INITIALIZER(n,f,tflags) { .work = __WORK_INITIALIZER((n).work, (f)), .timer = __TIMER_INITIALIZER(delayed_work_timer_fn, (tflags) | TIMER_IRQSAFE), }
#define KERNEL_HWCAP_SVEF32MM __khwcap2_feature(SVEF32MM)
#define ID_AA64MMFR3_EL1_SDERR_NI UL(0b0000)
#define EXPORT_PER_CPU_SYMBOL_GPL(var) EXPORT_SYMBOL_GPL(var)
#define PTRACE_EVENT_EXEC 4
#define _LINUX_DQBLK_V1_H 
#define MDIO_PMA_SPEED_100 0x0020
#define SWNODE_GRAPH_ENDPOINT_NAME_FMT "endpoint@%u"
#define IPV6_XFRM_POLICY 35
#define phy_read_mmd_poll_timeout(phydev,devaddr,regnum,val,cond,sleep_us,timeout_us,sleep_before_read) ({ int __ret, __val; __ret = read_poll_timeout(__val = phy_read_mmd, val, __val < 0 || (cond), sleep_us, timeout_us, sleep_before_read, phydev, devaddr, regnum); if (__val < 0) __ret = __val; if (__ret) phydev_err(phydev, "%s failed: %d\n", __func__, __ret); __ret; })
#define PF_SIGNALED 0x00000400
#define IRQ_AFFINITY_MAX_SETS 4
#define SIOCGSKNS 0x894C
#define IORESOURCE_MEM_64 0x00100000
#define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K
#define const___clear_bit generic___clear_bit
#define REG_ID_AA64PFR0_EL1 S3_0_C0_C4_0
#define swab64 __swab64
#define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page)))
#define CONFIG_INET_TUNNEL 1
#define MDIO_PMA_SPEED_10P 0x0004
#define MDIO_PMA_10T1L_STAT_FAULT 0x0002
#define ___GFP_WRITE 0x1000u
#define ESR_ELx_EC_HVC64 (0x16)
#define SYSCALL_DEFINE0(sname) SYSCALL_METADATA(_ ##sname, 0); asmlinkage long __arm64_sys_ ##sname(const struct pt_regs *__unused); ALLOW_ERROR_INJECTION(__arm64_sys_ ##sname, ERRNO); asmlinkage long __arm64_sys_ ##sname(const struct pt_regs *__unused)
#define RCU_SEGCBLIST_INITIALIZER(n) { .head = NULL, .tails[RCU_DONE_TAIL] = &n.head, .tails[RCU_WAIT_TAIL] = &n.head, .tails[RCU_NEXT_READY_TAIL] = &n.head, .tails[RCU_NEXT_TAIL] = &n.head, }
#define local_save_flags(flags) raw_local_save_flags(flags)
#define ID_MMFR2_EL1_HWAccFlg_SHIFT 28
#define PF_QIPCRTR AF_QIPCRTR
#define ID_AA64SMFR0_EL1_B16B16 GENMASK(43, 43)
#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK
#define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
#define TCR2_EL2_AIE_SHIFT 4
#define NETIF_F_HW_CSUM __NETIF_F(HW_CSUM)
#define CONFIG_SERIAL_AMBA_PL011 1
#define HFGxTR_EL2_TCR_EL1 GENMASK(32, 32)
#define for_each_set_bit_from(bit,addr,size) for (; (bit) = find_next_bit((addr), (size), (bit)), (bit) < (size); (bit)++)
#define DEFINE_RAW_SPINLOCK(x) raw_spinlock_t x = __RAW_SPIN_LOCK_UNLOCKED(x)
#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
#define PMBLIMITR_EL1_PMFZ_WIDTH 1
#define CONFIG_TIMER_OF 1
#define count_vm_numa_event(x) do {} while (0)
#define ETH_TP_MDI_AUTO 0x03
#define MSG_OOB 1
#define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
#define ID_AA64ISAR1_EL1_BF16_NI UL(0b0000)
#define lockdep_set_subclass(lock,sub) lockdep_init_map_type(&(lock)->dep_map, #lock, (lock)->dep_map.key, sub, (lock)->dep_map.wait_type_inner, (lock)->dep_map.wait_type_outer, (lock)->dep_map.lock_type)
#define MAX_TLBI_RANGE_PAGES __TLBI_RANGE_PAGES(31, 3)
#define ID_MMFR0_EL1_AuxReg GENMASK(23, 20)
#define ESR_ELx_EC_PAC (0x09)
#define ethtool_link_ksettings_zero_link_mode(ptr,name) bitmap_zero((ptr)->link_modes.name, __ETHTOOL_LINK_MODE_MASK_NBITS)
#define ID_AA64SMFR0_EL1_SMEver_SHIFT 56
#define for_each_cmsghdr(cmsg,msg) for (cmsg = CMSG_FIRSTHDR(msg); cmsg; cmsg = CMSG_NXTHDR(msg, cmsg))
#define ktime_sub(lhs,rhs) ((lhs) - (rhs))
#define HWCAP2_SVEF64MM (1 << 11)
#define IPV6_TLV_HAO 201
#define ETHTOOL_SRXFH 0x0000002a
#define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
#define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
#define PACKET_RECV_OUTPUT 3
#define COMPAT_HWCAP_LPAE (1 << 20)
#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
#define __NR_restart_syscall 128
#define FMODE_PREAD ((__force fmode_t)0x8)
#define HCRX_EL2_EnIDCP128_WIDTH 1
#define flowi6_scope __fl_common.flowic_scope
#define __get_kernel_nofault(dst,src,type,err_label) do { __typeof__(dst) __gkn_dst = (dst); __typeof__(src) __gkn_src = (src); int __gkn_err = 0; __mte_enable_tco_async(); __raw_get_mem("ldr", *((type *)(__gkn_dst)), (__force type *)(__gkn_src), __gkn_err, K); __mte_disable_tco_async(); if (unlikely(__gkn_err)) goto err_label; } while (0)
#define CONFIG_INPUT 1
#define SG_END 0x02UL
#define SEEK_HOLE 4
#define TCR2_EL1x_PTTWI_WIDTH 1
#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
#define JOBCTL_TRAP_NOTIFY (1UL << JOBCTL_TRAP_NOTIFY_BIT)
#define GENMASK_INPUT_CHECK(h,l) (BUILD_BUG_ON_ZERO(__builtin_choose_expr( __is_constexpr((l) > (h)), (l) > (h), 0)))
#define NOTIFY_STOP_MASK 0x8000
#define _ASM_GENERIC_BITOPS_FLS64_H_ 
#define SCM_TIMESTAMPING_PKTINFO 58
#define HDFGRTR_EL2_TRCPRGCTLR_SHIFT 44
#define smp_store_release(p,v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
#define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
#define PR_TASK_PERF_EVENTS_ENABLE 32
#define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
#define CONFIG_PREEMPTIRQ_TRACEPOINTS 1
#define HFGITR_EL2_DCCVAC GENMASK(54, 54)
#define KERNEL_HWCAP_PMULL __khwcap_feature(PMULL)
#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
#define HFGITR_EL2_DCCVAP GENMASK(8, 8)
#define HFGITR_EL2_TLBIRVAAE1_SHIFT 39
#define HFGITR_EL2_DCCVAU GENMASK(7, 7)
#define NETIF_F_VLAN_CHALLENGED __NETIF_F(VLAN_CHALLENGED)
#define DT_INIT 12
#define HFGITR_EL2_TLBIRVAE1 GENMASK(38, 38)
#define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
#define assert_raw_spin_locked(x) BUG_ON(!raw_spin_is_locked(x))
#define SLAB_NO_MERGE ((slab_flags_t __force)0x01000000U)
#define __get_mem_asm(load,reg,x,addr,err,type) asm volatile( "1:	" load "	" reg "1, [%2]\n" "2:\n" _ASM_EXTABLE_ ##type ##ACCESS_ERR_ZERO(1b, 2b, %w0, %w1) : "+r" (err), "=r" (x) : "r" (addr))
#define __smp_rmb() dmb(ishld)
#define SYS_LOREA_EL1_Op1 0
#define ETHTOOL_SFEATURES 0x0000003b
#define HFGxTR_EL2_FAR_EL1_SHIFT 17
#define CONFIG_ARCH_INLINE_WRITE_UNLOCK 1
#define ID_MMFR3_EL1_CMemSz_4GB UL(0b0000)
#define NLM_F_NONREC 0x100
#define _LINUX_LIMITS_H 
#define KERNEL_HWCAP_SVEBITPERM __khwcap2_feature(SVEBITPERM)
#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
#define MIN_MEMBLOCK_ADDR 0
#define for_each_set_bit_wrap(bit,addr,size,start) for ((bit) = find_next_bit_wrap((addr), (size), (start)); (bit) < (size); (bit) = __for_each_wrap((addr), (size), (start), (bit) + 1))
#define _ALTERNATIVE_CFG(oldinstr,newinstr,cpucap,cfg,...) __ALTERNATIVE_CFG(oldinstr, newinstr, cpucap, IS_ENABLED(cfg))
#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
#define for_each_online_node(node) for_each_node_state(node, N_ONLINE)
#define __atomic_op_acquire(op,args...) ({ typeof(op ##_relaxed(args)) __ret = op ##_relaxed(args); __atomic_acquire_fence(); __ret; })
#define ID_PFR2_EL1_CSV3_MASK GENMASK(3, 0)
#define ID_AA64ISAR1_EL1_FCMA_SHIFT 16
#define NSEC_PER_SEC 1000000000L
#define CLOCK_MONOTONIC 1
#define SYS_ZCR_EL12_Op0 3
#define SYS_ZCR_EL12_Op1 5
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
#define ID_AA64PFR0_EL1_SEL2_MASK GENMASK(39, 36)
#define CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK 1
#define SVE_PT_REGS_FPSIMD 0
#define __NR_sendmsg 211
#define MIGRATE_MODE_H_INCLUDED 
#define alloc_ordered_workqueue(fmt,flags,args...) alloc_workqueue(fmt, WQ_UNBOUND | __WQ_ORDERED | __WQ_ORDERED_EXPLICIT | (flags), 1, ##args)
#define TCR2_EL1x_PnCH_SHIFT 0
#define CTR_EL0_TminLine GENMASK(37, 32)
#define lockdep_set_class_and_name(lock,key,name) lockdep_init_map_type(&(lock)->dep_map, name, key, 0, (lock)->dep_map.wait_type_inner, (lock)->dep_map.wait_type_outer, (lock)->dep_map.lock_type)
#define TRBBASER_EL1_BASE_MASK GENMASK(63, 12)
#define ID_AA64MMFR3_EL1_TCRX_MASK GENMASK(3, 0)
#define ifr_ifindex ifr_ifru.ifru_ivalue
#define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
#define PR_SCHED_CORE_SCOPE_THREAD_GROUP 1
#define EBADRQC 56
#define BMSR_10FULL 0x1000
#define __ASM_CURRENT_H 
#define __exitdata __section(".exit.data")
#define AT_STATX_FORCE_SYNC 0x2000
#define ETHTOOL_GRXCLSRLCNT 0x0000002e
#define KERNEL_HWCAP_SM3 __khwcap_feature(SM3)
#define KERNEL_HWCAP_SM4 __khwcap_feature(SM4)
#define EX_TYPE_LOAD_UNALIGNED_ZEROPAD 4
#define SHN_LOPROC 0xff00
#define _DEFINE_STATIC_KEY_0(name) DEFINE_STATIC_KEY_FALSE(name)
#define ID_AA64ZFR0_EL1_B16B16 GENMASK(27, 24)
#define jump_label_enabled static_key_enabled
#define DACR32_EL2_D5_MASK GENMASK(11, 10)
#define UTIL_EST_WEIGHT_SHIFT 2
#define KERNEL_HWCAP_SME __khwcap2_feature(SME)
#define PTRACE_PEEKTEXT 1
#define HDFGRTR_EL2_PMCCNTR_EL0_MASK GENMASK(15, 15)
#define SCTLR_EL1_A_MASK GENMASK(1, 1)
#define HDFGWTR_EL2_PMSLATFR_EL1 GENMASK(32, 32)
#define P4D_TABLE_UXN (_AT(p4dval_t, 1) << 60)
#define EL3RST 47
#define SERIO_ANY 0xff
#define lockdep_hrtimer_enter(__hrtimer) ({ bool __expires_hardirq = true; if (!__hrtimer->is_hard) { current->irq_config = 1; __expires_hardirq = false; } __expires_hardirq; })
#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
#define TASK_SIZE_MAX (UL(1) << VA_BITS)
#define PMSLATFR_EL1_MINLAT_MASK GENMASK(15, 0)
#define S_IXUGO (S_IXUSR|S_IXGRP|S_IXOTH)
#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001
#define SYS_ID_AA64DFR1_EL1_Op0 3
#define HFGITR_EL2_nGCSSTR_EL1 GENMASK(58, 58)
#define ID_DFR0_EL1_RES0 (UL(0) | GENMASK_ULL(63, 32))
#define ID_DFR0_EL1_RES1 (UL(0))
#define HWCAP_SVE (1 << 22)
#define __SVE_VQ_MAX 512
#define __NR_fadvise64 __NR3264_fadvise64
#define ID_AA64MMFR1_EL1_CMOW_SIGNED false
#define vma_alloc_zeroed_movable_folio vma_alloc_zeroed_movable_folio
#define HFGITR_EL2_DCISW GENMASK(4, 4)
#define to_mii_bus(d) container_of(d, struct mii_bus, dev)
#define wait_event_killable(wq_head,condition) ({ int __ret = 0; might_sleep(); if (!(condition)) __ret = __wait_event_killable(wq_head, condition); __ret; })
#define KPROBES_BRK_IMM 0x004
#define outsb_p outsb_p
#define DT_PLTGOT 3
#define ID_AA64PFR0_EL1_RES0 (UL(0))
#define ID_AA64PFR0_EL1_RES1 (UL(0))
#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
#define ID_AA64PFR1_EL1_RAS_frac_RASv1p1 UL(0b0001)
#define FS_IOC_GETVERSION _IOR('v', 1, long)
#define CONFIG_DRM 1
#define AT_Op0 1
#define NLM_F_ACK 0x04
#define LMI_ANSI 2
#define SYS_ID_AA64DFR0_EL1_CRm 5
#define SYS_ID_AA64DFR0_EL1_CRn 0
#define SHT_HASH 5
#define SCTLR_EL1_UCI GENMASK(26, 26)
#define ELF_CLASS ELFCLASS64
#define ID_AA64PFR1_EL1_SSBS_SSBS2 UL(0b0010)
#define SCTLR_EL1_UCT GENMASK(15, 15)
#define ID_MMFR2_EL1_UniTLB GENMASK(19, 16)
#define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
#define PTE_PI_IDX_0 6
#define PTE_PI_IDX_1 51
#define PTE_PI_IDX_2 53
#define PTE_PI_IDX_3 54
#define EXPANSION_ENABLENPAGE 0x0004
#define read_poll_timeout(op,val,cond,sleep_us,timeout_us,sleep_before_read,args...) ({ u64 __timeout_us = (timeout_us); unsigned long __sleep_us = (sleep_us); ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); might_sleep_if((__sleep_us) != 0); if (sleep_before_read && __sleep_us) usleep_range((__sleep_us >> 2) + 1, __sleep_us); for (;;) { (val) = op(args); if (cond) break; if (__timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { (val) = op(args); break; } if (__sleep_us) usleep_range((__sleep_us >> 2) + 1, __sleep_us); cpu_relax(); } (cond) ? 0 : -ETIMEDOUT; })
#define MDIO_PMA_CTRL2_10GBLW 0x0002
#define DO_ONCE_LITE(func,...) DO_ONCE_LITE_IF(true, func, ##__VA_ARGS__)
#define S_IFSOCK 0140000
#define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
#define VM_FAULT_ERROR (VM_FAULT_OOM | VM_FAULT_SIGBUS | VM_FAULT_SIGSEGV | VM_FAULT_HWPOISON | VM_FAULT_HWPOISON_LARGE | VM_FAULT_FALLBACK)
#define ID_MMFR1_EL1_L1UniSW_SHIFT 12
#define SIG_KERNEL_IGNORE_MASK ( rt_sigmask(SIGCONT) | rt_sigmask(SIGCHLD) | rt_sigmask(SIGWINCH) | rt_sigmask(SIGURG) )
#define SIOCETHTOOL 0x8946
#define IPC_OWN 00020000
#define dev_err_ratelimited(dev,fmt,...)