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jitdump_7236.txt
BEGIN EXECUTION
"c:\dev\coreclr\bin\tests\Windows_NT.x86.Checked\Tests\Core_Root\corerun.exe" _speed_dbgunsafe-4.exe
****** START compiling TestApp:test_25(int,ref,long,ubyte):long (MethodHash=e5bcc669)
Generating code for Windows x86
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 04 ldarg.2
IL_0003 05 ldarg.3
IL_0004 6e conv.u8
IL_0005 59 sub
IL_0006 d4 conv.ovf.i
IL_0007 16 ldc.i4.0
IL_0008 04 ldarg.2
IL_0009 05 ldarg.3
IL_000a 6e conv.u8
IL_000b 59 sub
IL_000c d4 conv.ovf.i
IL_000d 04 ldarg.2
IL_000e 17 ldc.i4.1
IL_000f 6a conv.i8
IL_0010 59 sub
IL_0011 25 dup
IL_0012 0a stloc.0
IL_0013 28 04 00 00 0a call 0xA000004
IL_0018 06 ldloc.0
IL_0019 fe 1c 04 00 00 02 sizeof 0x2000004
IL_001f 6a conv.i8
IL_0020 5a mul
IL_0021 d3 conv.i
IL_0022 58 add
IL_0023 e0 conv.u
IL_0024 7b 02 00 00 04 ldfld 0x4000002
IL_0029 2a ret
Set preferred register for V00 to [ecx]
Arg #0 passed in register(s) ecx
Set preferred register for V01 to [edx]
Arg #1 passed in register(s) edx
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 ref
; V02 arg2 long
; V03 arg3 ubyte
; V04 loc0 long
*************** In compInitDebuggingInfo() for TestApp:test_25(int,ref,long,ubyte):long
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 5
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 02Ah
1: 01h 01h V01 arg1 000h 02Ah
2: 02h 02h V02 arg2 000h 02Ah
3: 03h 03h V03 arg3 000h 02Ah
4: 04h 04h V04 loc0 000h 02Ah
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for TestApp:test_25(int,ref,long,ubyte):long
Jump targets:
none
New Basic Block BB01 [032A71F8] created.
BB01 [000..02A)
IL Code Size,Instr 42, 29, Basic Block count 1, Local Variable Num,Ref count 5, 9 for method TestApp:test_25(int,ref,long,ubyte):long
OPTIONS: opts.MinOpts() == false
Basic block list for 'TestApp:test_25(int,ref,long,ubyte):long'
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return)
-------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for TestApp:test_25(int,ref,long,ubyte):long
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'TestApp:test_25(int,ref,long,ubyte):long'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
[ 2] 2 (0x002) ldarg.2
[ 3] 3 (0x003) ldarg.3
[ 4] 4 (0x004) conv.u8
[ 4] 5 (0x005) sub
[ 3] 6 (0x006) conv.ovf.i
[ 3] 7 (0x007) ldc.i4.0 0
[ 4] 8 (0x008) ldarg.2
[ 5] 9 (0x009) ldarg.3
[ 6] 10 (0x00a) conv.u8
[ 6] 11 (0x00b) sub
[ 5] 12 (0x00c) conv.ovf.i
[ 5] 13 (0x00d) ldarg.2
[ 6] 14 (0x00e) ldc.i4.1 1
[ 7] 15 (0x00f) conv.i8
[ 7] 16 (0x010) sub
[ 6] 17 (0x011) dup
[ 6] 18 (0x012) stloc.0
[000020] ------------ * stmtExpr void (IL 0x000... ???)
[000016] ------------ | /--* cast long <- int
[000015] ------------ | | \--* const int 1
[000017] ------------ | /--* - long
[000014] ------------ | | \--* lclVar long V02 arg2
[000019] -A---------- \--* = long
[000018] D------N---- \--* lclVar long V04 loc0
[ 6] 19 (0x013) call 0A000004
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
[000025] ------------ * stmtExpr void (IL ???... ???)
[000021] ------------ | /--* lclVar long V04 loc0
[000024] -A-X-------- \--* = long
[000023] ---X---N---- \--* indir long
[000022] ---X-------- \--* arrMD&[,,] byref
[000002] ------------ +--* lclVar ref V01 arg1
[000007] ---X-------- +--* cast_ovfl int <- long
[000005] ---------U-- | | /--* cast long <- ulong <- uint
[000004] ------------ | | | \--* lclVar ubyte V03 arg3
[000006] ------------ | \--* - long
[000003] ------------ | \--* lclVar long V02 arg2
[000008] ------------ +--* const int 0
[000013] ---X-------- \--* cast_ovfl int <- long
[000011] ---------U-- | /--* cast long <- ulong <- uint
[000010] ------------ | | \--* lclVar ubyte V03 arg3
[000012] ------------ \--* - long
[000009] ------------ \--* lclVar long V02 arg2
[ 1] 24 (0x018) ldloc.0
[ 2] 25 (0x019) sizeof 02000004
[ 3] 31 (0x01f) conv.i8
[ 3] 32 (0x020) mul
[ 2] 33 (0x021) conv.i
[ 2] 34 (0x022) add
[ 1] 35 (0x023) conv.u
[ 1] 36 (0x024) ldfld 04000002
[ 1] 41 (0x029) ret
[000035] ------------ * stmtExpr void (IL 0x018... ???)
[000034] ---XG------- \--* return long
[000033] ---XG------- \--* field long m_bval
[000032] ------------ \--* cast int <- uint <- int
[000030] ------------ | /--* cast int <- long
[000028] ------------ | | | /--* cast long <- int
[000027] ------------ | | | | \--* const int 8
[000029] ------------ | | \--* * long
[000026] ------------ | | \--* lclVar long V04 loc0
[000031] ------------ \--* + int
[000001] ------------ \--* lclVar int V00 arg0
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgMorph()
*************** After fgAddInternal()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgInline()
*************** After fgInline()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
[000020] ------------ * stmtExpr void (IL 0x000...0x012)
[000016] ------------ | /--* cast long <- int
[000015] ------------ | | \--* const int 1
[000017] ------------ | /--* - long
[000014] ------------ | | \--* lclVar long V02 arg2
[000019] -A---------- \--* = long
[000018] D------N---- \--* lclVar long V04 loc0
***** BB01, stmt 2
[000025] ------------ * stmtExpr void (IL ???...0x029)
[000021] ------------ | /--* lclVar long V04 loc0
[000024] -A-X-------- \--* = long
[000023] ---X---N---- \--* indir long
[000022] ---X-------- \--* arrMD&[,,] byref
[000002] ------------ +--* lclVar ref V01 arg1
[000007] ---X-------- +--* cast_ovfl int <- long
[000005] ---------U-- | | /--* cast long <- ulong <- uint
[000004] ------------ | | | \--* lclVar ubyte V03 arg3
[000006] ------------ | \--* - long
[000003] ------------ | \--* lclVar long V02 arg2
[000008] ------------ +--* const int 0
[000013] ---X-------- \--* cast_ovfl int <- long
[000011] ---------U-- | /--* cast long <- ulong <- uint
[000010] ------------ | | \--* lclVar ubyte V03 arg3
[000012] ------------ \--* - long
[000009] ------------ \--* lclVar long V02 arg2
***** BB01, stmt 3
[000035] ------------ * stmtExpr void (IL 0x018... ???)
[000034] ---XG------- \--* return long
[000033] ---XG------- \--* field long m_bval
[000032] ------------ \--* cast int <- uint <- int
[000030] ------------ | /--* cast int <- long
[000028] ------------ | | | /--* cast long <- int
[000027] ------------ | | | | \--* const int 8
[000029] ------------ | | \--* * long
[000026] ------------ | | \--* lclVar long V04 loc0
[000031] ------------ \--* + int
[000001] ------------ \--* lclVar int V00 arg0
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 06000004 TestApp:test_25(int,ref,long,ubyte):long
Budget: initialTime=186, finalTime=186, initialBudget=1860, currentBudget=1860
Budget: initialSize=1088, finalSize=1088
*************** In fgDebugCheckBBlist
*************** In fgPromoteStructs()
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'TestApp:test_25(int,ref,long,ubyte):long'
fgMorphTree BB01, stmt 1 (before)
[000016] ------------ /--* cast long <- int
[000015] ------------ | \--* const int 1
[000017] ------------ /--* - long
[000014] ------------ | \--* lclVar long V02 arg2
[000019] -A---------- * = long
[000018] D------N---- \--* lclVar long V04 loc0
Folding long operator with constant nodes into a constant:
[000016] ------------ * cast long <- int
[000015] -----+------ \--* const int 1
Bashed to long constant:
[000016] ------------ * lconst long 0x0000000000000001
*** JitStress: STRESS_FOLD ***
*** JitStress: STRESS_CLONE_EXPR ***
fgMorphTree (stressClone from):
[000016] -----+------ /--* lconst long 0x0000000000000001
[000017] -----+------ /--* - long
[000014] -----+------ | \--* lclVar long V02 arg2
[000019] -A---+------ * = long
[000018] D----+-N---- \--* lclVar long V04 loc0
fgMorphTree (stressClone to):
[000040] ------------ /--* lconst long 0x0000000000000001
[000038] ------------ /--* - long
[000039] ------------ | \--* lclVar long V02 arg2
[000036] -A---------- * = long
[000037] D------N---- \--* lclVar long V04 loc0
fgMorphTree BB01, stmt 1 (after)
[000040] ------------ /--* lconst long 0x0000000000000001
[000038] ------------ /--* - long
[000039] ------------ | \--* lclVar long V02 arg2
[000036] -A---------- * = long
[000037] D------N---- \--* lclVar long V04 loc0
fgMorphTree BB01, stmt 2 (before)
[000021] ------------ /--* lclVar long V04 loc0
[000024] -A-X-------- * = long
[000023] ---X---N---- \--* indir long
[000022] ---X-------- \--* arrMD&[,,] byref
[000002] ------------ +--* lclVar ref V01 arg1
[000007] ---X-------- +--* cast_ovfl int <- long
[000005] ---------U-- | | /--* cast long <- ulong <- uint
[000004] ------------ | | | \--* lclVar ubyte V03 arg3
[000006] ------------ | \--* - long
[000003] ------------ | \--* lclVar long V02 arg2
[000008] ------------ +--* const int 0
[000013] ---X-------- \--* cast_ovfl int <- long
[000011] ---------U-- | /--* cast long <- ulong <- uint
[000010] ------------ | | \--* lclVar ubyte V03 arg3
[000012] ------------ \--* - long
[000009] ------------ \--* lclVar long V02 arg2
fgNewBBinRegion(jumpKind=3, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB01
New Basic Block BB02 [032A9340] created.
fgAddCodeRef - Add BB in non-EH region for OVERFLOW, new block BB02 [032A9340], stkDepth is 0
*** Computing fgRngChkTarget for block BB01 to stkDepth 0
[000025] ------------ * stmtExpr void (IL ???...0x029)
[000021] ------------ | /--* lclVar long V04 loc0
[000024] -A-X-------- \--* = long
[000023] ---X---N---- \--* indir long
[000022] ---X-------- \--* arrMD&[,,] byref
[000002] -----+------ +--* lclVar ref V01 arg1
[000007] ---X-+------ +--* cast_ovfl int <- long
[000005] -----+---U-- | | /--* cast long <- ulong <- uint
[000041] -----+------ | | | \--* cast int <- ubyte <- int
[000004] -----+------ | | | \--* lclVar int V03 arg3
[000006] -----+------ | \--* - long
[000003] -----+------ | \--* lclVar long V02 arg2
[000008] -----+------ +--* const int 0
[000013] ---X-+------ \--* cast_ovfl int <- long
[000011] -----+---U-- | /--* cast long <- ulong <- uint
[000044] -----+------ | | \--* cast int <- ubyte <- int
[000010] -----+------ | | \--* lclVar int V03 arg3
[000012] -----+------ \--* - long
[000009] -----+------ \--* lclVar long V02 arg2
fgNewBBinRegion(jumpKind=3, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB02
New Basic Block BB03 [032A9618] created.
fgAddCodeRef - Add BB in non-EH region for RNGCHK_FAIL, new block BB03 [032A9618], stkDepth is 0
GenTreeNode creates assertion:
[000022] ---X-------- * arrMD&[,,] byref
In BB01 New Local Constant Assertion: V01 != null index=#01, mask=0000000000000001
fgMorphTree (stressClone from):
[000021] -----+------ /--* lclVar long V04 loc0
[000024] -A-X-+------ * = long
[000023] ---X-+-N---- \--* indir long
[000022] ---X-+------ \--* arrMD&[,,] byref
[000002] -----+------ +--* lclVar ref V01 arg1
[000007] ---X-+------ +--* cast_ovfl int <- long
[000005] -----+---U-- | | /--* cast long <- ulong <- uint
[000041] -----+------ | | | \--* cast int <- ubyte <- int
[000004] -----+------ | | | \--* lclVar int V03 arg3
[000006] -----+------ | \--* - long
[000003] -----+------ | \--* lclVar long V02 arg2
[000008] -----+------ +--* const int 0
[000013] ---X-+------ \--* cast_ovfl int <- long
[000011] -----+---U-- | /--* cast long <- ulong <- uint
[000044] -----+------ | | \--* cast int <- ubyte <- int
[000010] -----+------ | | \--* lclVar int V03 arg3
[000012] -----+------ \--* - long
[000009] -----+------ \--* lclVar long V02 arg2
fgMorphTree (stressClone to):
[000064] ------------ /--* lclVar long V04 loc0
[000047] -A-X-------- * = long
[000048] ---X---N---- \--* indir long
[000063] ---X-------- \--* arrMD&[,,] byref
[000062] ------------ +--* lclVar ref V01 arg1
[000049] ---X-------- +--* cast_ovfl int <- long
[000052] ---------U-- | | /--* cast long <- ulong <- uint
[000053] ------------ | | | \--* cast int <- ubyte <- int
[000054] ------------ | | | \--* lclVar int V03 arg3
[000050] ------------ | \--* - long
[000051] ------------ | \--* lclVar long V02 arg2
[000055] ------------ +--* const int 0
[000056] ---X-------- \--* cast_ovfl int <- long
[000059] ---------U-- | /--* cast long <- ulong <- uint
[000060] ------------ | | \--* cast int <- ubyte <- int
[000061] ------------ | | \--* lclVar int V03 arg3
[000057] ------------ \--* - long
[000058] ------------ \--* lclVar long V02 arg2
fgMorphTree BB01, stmt 2 (after)
[000064] ------------ /--* lclVar long V04 loc0
[000047] -A-X-------- * = long
[000048] ---X---N---- \--* indir long
[000063] ---X-------- \--* arrMD&[,,] byref
[000062] ------------ +--* lclVar ref V01 arg1
[000049] ---X-------- +--* cast_ovfl int <- long
[000052] ---------U-- | | /--* cast long <- ulong <- uint
[000053] ------------ | | | \--* cast int <- ubyte <- int
[000054] ------------ | | | \--* lclVar int V03 arg3
[000050] ------------ | \--* - long
[000051] ------------ | \--* lclVar long V02 arg2
[000055] ------------ +--* const int 0
[000056] ---X-------- \--* cast_ovfl int <- long
[000059] ---------U-- | /--* cast long <- ulong <- uint
[000060] ------------ | | \--* cast int <- ubyte <- int
[000061] ------------ | | \--* lclVar int V03 arg3
[000057] ------------ \--* - long
[000058] ------------ \--* lclVar long V02 arg2
fgMorphTree BB01, stmt 3 (before)
[000034] ---XG------- * return long
[000033] ---XG------- \--* field long m_bval
[000032] ------------ \--* cast int <- uint <- int
[000030] ------------ | /--* cast int <- long
[000028] ------------ | | | /--* cast long <- int
[000027] ------------ | | | | \--* const int 8
[000029] ------------ | | \--* * long
[000026] ------------ | | \--* lclVar long V04 loc0
[000031] ------------ \--* + int
[000001] ------------ \--* lclVar int V00 arg0
Folding long operator with constant nodes into a constant:
[000028] ------------ * cast long <- int
[000027] -----+------ \--* const int 8
Bashed to long constant:
[000028] ------------ * lconst long 0x0000000000000008
fgMorphTree (stressClone from):
[000034] ---XG+------ * return long
[000033] ---XG+------ \--* indir long
[000028] -----+------ | /--* const int 3
[000029] -----+------ | /--* << int
[000026] C----+------ | | \--* lclVar int V04 loc0
[000031] -----+------ \--* + int
[000001] -----+------ \--* lclVar int V00 arg0
fgMorphTree (stressClone to):
[000067] ---XG------- * return long
[000068] ---XG------- \--* indir long
[000073] ------------ | /--* const int 3
[000071] ------------ | /--* << int
[000072] C----------- | | \--* lclVar int V04 loc0
[000069] ------------ \--* + int
[000070] ------------ \--* lclVar int V00 arg0
fgMorphTree BB01, stmt 3 (after)
[000067] ---XG------- * return long
[000068] ---XG------- \--* indir long
[000073] ------------ | /--* const int 3
[000071] ------------ | /--* << int
[000072] C----------- | | \--* lclVar int V04 loc0
[000069] ------------ \--* + int
[000070] ------------ \--* lclVar int V00 arg0
Morphing BB02 of 'TestApp:test_25(int,ref,long,ubyte):long'
fgMorphTree BB02, stmt 4 (before)
N001 ( 14, 5) [000042] --CXG------- * call help void HELPER.CORINFO_HELP_OVERFLOW
fgMorphTree (stressClone from):
N001 ( 14, 5) [000042] --CXG+------ * call help void HELPER.CORINFO_HELP_OVERFLOW
fgMorphTree (stressClone to):
( 14, 5) [000074] --CXG------- * call help void HELPER.CORINFO_HELP_OVERFLOW
Morphing BB03 of 'TestApp:test_25(int,ref,long,ubyte):long'
fgMorphTree BB03, stmt 5 (before)
N001 ( 14, 5) [000045] --CXG------- * call help void HELPER.CORINFO_HELP_RNGCHKFAIL
fgMorphTree (stressClone from):
N001 ( 14, 5) [000045] --CXG+------ * call help void HELPER.CORINFO_HELP_RNGCHKFAIL
fgMorphTree (stressClone to):
( 14, 5) [000077] --CXG------- * call help void HELPER.CORINFO_HELP_RNGCHKFAIL
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
New BlockSet epoch 2, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
*************** In fgComputePreds()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() was able to compute exact edge weights for all of the 0 edges, using 1 passes.
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgRelocateEHRegions()
*************** In fgReorderBlocks()
Initial BasicBlocks
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB02
BB03 : BB03
After computing reachability:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01 BB02 BB03
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB03: BB03
BB02: BB02
BB01: BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
*************** In Allocate Objects
Trees before Allocate Objects
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
[000020] ------------ * stmtExpr void (IL 0x000...0x012)
[000040] ------------ | /--* lconst long 0x0000000000000001
[000038] ------------ | /--* - long
[000039] ------------ | | \--* lclVar long V02 arg2
[000036] -A---------- \--* = long
[000037] D------N---- \--* lclVar long V04 loc0
***** BB01, stmt 2
[000025] ------------ * stmtExpr void (IL ???...0x029)
[000064] ------------ | /--* lclVar long V04 loc0
[000047] -A-X-------- \--* = long
[000048] ---X---N---- \--* indir long
[000063] ---X-------- \--* arrMD&[,,] byref
[000062] ------------ +--* lclVar ref V01 arg1
[000049] ---X-------- +--* cast_ovfl int <- long
[000052] ---------U-- | | /--* cast long <- ulong <- uint
[000053] ------------ | | | \--* cast int <- ubyte <- int
[000054] ------------ | | | \--* lclVar int V03 arg3
[000050] ------------ | \--* - long
[000051] ------------ | \--* lclVar long V02 arg2
[000055] ------------ +--* const int 0
[000056] ---X-------- \--* cast_ovfl int <- long
[000059] ---------U-- | /--* cast long <- ulong <- uint
[000060] ------------ | | \--* cast int <- ubyte <- int
[000061] ------------ | | \--* lclVar int V03 arg3
[000057] ------------ \--* - long
[000058] ------------ \--* lclVar long V02 arg2
***** BB01, stmt 3
[000035] ------------ * stmtExpr void (IL 0x018... ???)
[000067] ---XG------- \--* return long
[000068] ---XG------- \--* indir long
[000073] ------------ | /--* const int 3
[000071] ------------ | /--* << int
[000072] C----------- | | \--* lclVar int V04 loc0
[000069] ------------ \--* + int
[000070] ------------ \--* lclVar int V00 arg0
------------ BB02 [???..???) (throw), preds={} succs={}
***** BB02, stmt 4
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
***** BB03, stmt 5
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
[000020] ------------ * stmtExpr void (IL 0x000...0x012)
[000040] ------------ | /--* lconst long 0x0000000000000001
[000038] ------------ | /--* - long
[000039] ------------ | | \--* lclVar long V02 arg2
[000036] -A---------- \--* = long
[000037] D------N---- \--* lclVar long V04 loc0
***** BB01, stmt 2
[000025] ------------ * stmtExpr void (IL ???...0x029)
[000064] ------------ | /--* lclVar long V04 loc0
[000047] -A-X-------- \--* = long
[000048] ---X---N---- \--* indir long
[000063] ---X-------- \--* arrMD&[,,] byref
[000062] ------------ +--* lclVar ref V01 arg1
[000049] ---X-------- +--* cast_ovfl int <- long
[000052] ---------U-- | | /--* cast long <- ulong <- uint
[000053] ------------ | | | \--* cast int <- ubyte <- int
[000054] ------------ | | | \--* lclVar int V03 arg3
[000050] ------------ | \--* - long
[000051] ------------ | \--* lclVar long V02 arg2
[000055] ------------ +--* const int 0
[000056] ---X-------- \--* cast_ovfl int <- long
[000059] ---------U-- | /--* cast long <- ulong <- uint
[000060] ------------ | | \--* cast int <- ubyte <- int
[000061] ------------ | | \--* lclVar int V03 arg3
[000057] ------------ \--* - long
[000058] ------------ \--* lclVar long V02 arg2
***** BB01, stmt 3
[000035] ------------ * stmtExpr void (IL 0x018... ???)
[000067] ---XG------- \--* return long
[000068] ---XG------- \--* indir long
[000073] ------------ | /--* const int 3
[000071] ------------ | /--* << int
[000072] C----------- | | \--* lclVar int V04 loc0
[000069] ------------ \--* + int
[000070] ------------ \--* lclVar int V00 arg0
------------ BB02 [???..???) (throw), preds={} succs={}
***** BB02, stmt 4
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
***** BB03, stmt 5
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optOptimizeLoops()
*************** In fgDebugCheckBBlist
*************** In optCloneLoops()
*************** In lvaMarkLocalVars()
*** marking local variables in block BB01 (weight= 1 )
[000020] ------------ * stmtExpr void (IL 0x000...0x012)
[000040] ------------ | /--* lconst long 0x0000000000000001
[000038] ------------ | /--* - long
[000039] ------------ | | \--* lclVar long V02 arg2
[000036] -A---------- \--* = long
[000037] D------N---- \--* lclVar long V04 loc0
New refCnts for V04: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 1, refCntWtd = 1
[000025] ------------ * stmtExpr void (IL ???...0x029)
[000064] ------------ | /--* lclVar long V04 loc0
[000047] -A-X-------- \--* = long
[000048] ---X---N---- \--* indir long
[000063] ---X-------- \--* arrMD&[,,] byref
[000062] ------------ +--* lclVar ref V01 arg1
[000049] ---X-------- +--* cast_ovfl int <- long
[000052] ---------U-- | | /--* cast long <- ulong <- uint
[000053] ------------ | | | \--* cast int <- ubyte <- int
[000054] ------------ | | | \--* lclVar int V03 arg3
[000050] ------------ | \--* - long
[000051] ------------ | \--* lclVar long V02 arg2
[000055] ------------ +--* const int 0
[000056] ---X-------- \--* cast_ovfl int <- long
[000059] ---------U-- | /--* cast long <- ulong <- uint
[000060] ------------ | | \--* cast int <- ubyte <- int
[000061] ------------ | | \--* lclVar int V03 arg3
[000057] ------------ \--* - long
[000058] ------------ \--* lclVar long V02 arg2
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 3, refCntWtd = 3
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V04: refCnt = 2, refCntWtd = 2
[000035] ------------ * stmtExpr void (IL 0x018... ???)
[000067] ---XG------- \--* return long
[000068] ---XG------- \--* indir long
[000073] ------------ | /--* const int 3
[000071] ------------ | /--* << int
[000072] C----------- | | \--* lclVar int V04 loc0
[000069] ------------ \--* + int
[000070] ------------ \--* lclVar int V00 arg0
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 3, refCntWtd = 3
*** marking local variables in block BB02 (weight= 0 )
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
*** marking local variables in block BB03 (weight= 0 )
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
*************** In optAddCopies()
refCnt table for 'test_25':
V01 arg1 [ ref]: refCnt = 3, refCntWtd = 3 pref [edx]
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3 pref [ecx]
V02 arg2 [ long]: refCnt = 3, refCntWtd = 3
V04 loc0 [ long]: refCnt = 3, refCntWtd = 3
V03 arg3 [ ubyte]: refCnt = 2, refCntWtd = 2
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** In fgFindOperOrder()
*** JitStress: STRESS_REVERSE_FLAG ***
*************** In fgSetBlockOrder()
The biggest BB has 18 tree nodes
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
( 17, 22) [000020] ------------ * stmtExpr void (IL 0x000...0x012)
N002 ( 3, 10) [000040] ------------ | /--* lconst long 0x0000000000000001
N003 ( 10, 16) [000038] ------------ | /--* - long
N001 ( 3, 2) [000039] ------------ | | \--* lclVar long V02 arg2
N005 ( 17, 22) [000036] -A------R--- \--* = long
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0
***** BB01, stmt 2
( 64, 58) [000025] ------------ * stmtExpr void (IL ???...0x029)
N001 ( 3, 2) [000064] ------------ | /--* lclVar long V04 loc0
N018 ( 64, 58) [000047] -A-X----R--- \--* = long
N017 ( 57, 52) [000048] ---X---N---- \--* indir long
N016 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref
N002 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1
N008 ( 19, 20) [000049] ---X-------- +--* cast_ovfl int <- long
N005 ( 5, 6) [000052] ---------U-- | | /--* cast long <- ulong <- uint
N004 ( 4, 4) [000053] ------------ | | | \--* cast int <- ubyte <- int
N003 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3
N007 ( 12, 12) [000050] --------R--- | \--* - long
N006 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2
N009 ( 1, 1) [000055] ------------ +--* const int 0
N015 ( 19, 20) [000056] ---X-------- \--* cast_ovfl int <- long
N012 ( 5, 6) [000059] ---------U-- | /--* cast long <- ulong <- uint
N011 ( 4, 4) [000060] ------------ | | \--* cast int <- ubyte <- int
N010 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3
N014 ( 12, 12) [000057] --------R--- \--* - long
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2
***** BB01, stmt 3
( 6, 5) [000035] ------------ * stmtExpr void (IL 0x018... ???)
N007 ( 6, 5) [000067] ---XG------- \--* return long
N006 ( 5, 4) [000068] ---XG------- \--* indir long
N004 ( 1, 1) [000070] ------------ | /--* lclVar int V00 arg0
N005 ( 3, 3) [000069] -------N---- \--* + int
N002 ( 1, 1) [000073] ------------ | /--* const int 3
N003 ( 2, 2) [000071] -------N---- \--* << int
N001 ( 1, 1) [000072] C----------- \--* lclVar int V04 loc0
------------ BB02 [???..???) (throw), preds={} succs={}
***** BB02, stmt 4
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
***** BB03, stmt 5
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 4.
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...)
*************** In SsaBuilder::InsertPhiFunctions()
*************** In fgLocalVarLiveness()
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(4)={V01 V00 V02 V03} + HEAP
DEF(1)={ V04 } + HEAP
BB02 USE(0)={}
DEF(0)={}
BB03 USE(0)={}
DEF(0)={}
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (4)={V01 V00 V02 V03} + HEAP
OUT(0)={ }
BB02 IN (0)={}
OUT(0)={}
BB03 IN (0)={}
OUT(0)={}
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
( 17, 22) [000020] ------------ * stmtExpr void (IL 0x000...0x012)
N002 ( 3, 10) [000040] ------------ | /--* lconst long 0x0000000000000001
N003 ( 10, 16) [000038] ------------ | /--* - long
N001 ( 3, 2) [000039] ------------ | | \--* lclVar long V02 arg2 u:2
N005 ( 17, 22) [000036] -A------R--- \--* = long
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0 d:3
***** BB01, stmt 2
( 64, 58) [000025] ------------ * stmtExpr void (IL ???...0x029)
N001 ( 3, 2) [000064] ------------ | /--* lclVar long V04 loc0 u:3
N018 ( 64, 58) [000047] -A-X----R--- \--* = long
N017 ( 57, 52) [000048] ---X---N---- \--* indir long
N016 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref
N002 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1 u:2 (last use)
N008 ( 19, 20) [000049] ---X-------- +--* cast_ovfl int <- long
N005 ( 5, 6) [000052] ---------U-- | | /--* cast long <- ulong <- uint
N004 ( 4, 4) [000053] ------------ | | | \--* cast int <- ubyte <- int
N003 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3 u:2
N007 ( 12, 12) [000050] --------R--- | \--* - long
N006 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2 u:2
N009 ( 1, 1) [000055] ------------ +--* const int 0
N015 ( 19, 20) [000056] ---X-------- \--* cast_ovfl int <- long
N012 ( 5, 6) [000059] ---------U-- | /--* cast long <- ulong <- uint
N011 ( 4, 4) [000060] ------------ | | \--* cast int <- ubyte <- int
N010 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use)
N014 ( 12, 12) [000057] --------R--- \--* - long
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use)
***** BB01, stmt 3
( 6, 5) [000035] ------------ * stmtExpr void (IL 0x018... ???)
N007 ( 6, 5) [000067] ---XG------- \--* return long
N006 ( 5, 4) [000068] ---XG------- \--* indir long
N004 ( 1, 1) [000070] ------------ | /--* lclVar int V00 arg0 u:2 (last use)
N005 ( 3, 3) [000069] -------N---- \--* + int
N002 ( 1, 1) [000073] ------------ | /--* const int 3
N003 ( 2, 2) [000071] -------N---- \--* << int
N001 ( 1, 1) [000072] C----------- \--* lclVar int V04 loc0 u:3 (last use)
------------ BB02 [???..???) (throw), preds={} succs={}
***** BB02, stmt 4
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
***** BB03, stmt 5
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In optEarlyProp()
*************** In fgValueNumber()
Heap Initial Value in BB01 is: $c1
The SSA definition for heap (#2) at start of BB01 is $c1 {InitVal($44)}
***** BB01, stmt 1 (before)
N002 ( 3, 10) [000040] ------------ /--* lconst long 0x0000000000000001
N003 ( 10, 16) [000038] ------------ /--* - long
N001 ( 3, 2) [000039] ------------ | \--* lclVar long V02 arg2 u:2
N005 ( 17, 22) [000036] -A------R--- * = long
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0 d:3
N001 [000039] lclVar V02 arg2 u:2 => $100 {InitVal($42)}
N002 [000040] lconst 0x0000000000000001 => $181 {LngCns: 1}
N003 [000038] - => $1c0 {-($100, $181)}
N004 [000037] lclVar V04 loc0 d:3 => $1c0 {-($100, $181)}
N005 [000036] = => $1c0 {-($100, $181)}
***** BB01, stmt 1 (after)
N002 ( 3, 10) [000040] ------------ /--* lconst long 0x0000000000000001 $181
N003 ( 10, 16) [000038] ------------ /--* - long $1c0
N001 ( 3, 2) [000039] ------------ | \--* lclVar long V02 arg2 u:2 $100
N005 ( 17, 22) [000036] -A------R--- * = long $1c0
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0 d:3 $1c0
---------
***** BB01, stmt 2 (before)
N001 ( 3, 2) [000064] ------------ /--* lclVar long V04 loc0 u:3
N018 ( 64, 58) [000047] -A-X----R--- * = long
N017 ( 57, 52) [000048] ---X---N---- \--* indir long
N016 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref
N002 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1 u:2 (last use)
N008 ( 19, 20) [000049] ---X-------- +--* cast_ovfl int <- long
N005 ( 5, 6) [000052] ---------U-- | | /--* cast long <- ulong <- uint
N004 ( 4, 4) [000053] ------------ | | | \--* cast int <- ubyte <- int
N003 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3 u:2
N007 ( 12, 12) [000050] --------R--- | \--* - long
N006 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2 u:2
N009 ( 1, 1) [000055] ------------ +--* const int 0
N015 ( 19, 20) [000056] ---X-------- \--* cast_ovfl int <- long
N012 ( 5, 6) [000059] ---------U-- | /--* cast long <- ulong <- uint
N011 ( 4, 4) [000060] ------------ | | \--* cast int <- ubyte <- int
N010 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use)
N014 ( 12, 12) [000057] --------R--- \--* - long
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use)
N001 [000064] lclVar V04 loc0 u:3 => $1c0 {-($100, $181)}
N002 [000062] lclVar V01 arg1 u:2 (last use) => $c0 {InitVal($41)}
N003 [000054] lclVar V03 arg3 u:2 => $140 {InitVal($43)}
VNForCastOper(ubyte) is $45
N004 [000053] cast => $240 {Cast($140, $45)}
VNForCastOper(ulong, unsignedSrc) is $46
N005 [000052] cast => $1c1 {Cast($240, $46)}
N006 [000051] lclVar V02 arg2 u:2 => $100 {InitVal($42)}
N007 [000050] - => $1c2 {-($100, $1c1)}
VNForCastOper(int) is $47
VNForCastOper(int) is $47
$281 = singleton exc set {ConvOverflowExc($1c2, $47)}
$281 = singleton exc set {ConvOverflowExc($1c2, $47)}
N008 [000049] cast_ovfl => $242 {ValWithExc($241, $281)}
N009 [000055] const 0 => $40 {IntCns 0}
N010 [000061] lclVar V03 arg3 u:2 (last use) => $140 {InitVal($43)}
VNForCastOper(ubyte) is $45
N011 [000060] cast => $240 {Cast($140, $45)}
VNForCastOper(ulong, unsignedSrc) is $46
N012 [000059] cast => $1c1 {Cast($240, $46)}
N013 [000058] lclVar V02 arg2 u:2 (last use) => $100 {InitVal($42)}
N014 [000057] - => $1c2 {-($100, $1c1)}
VNForCastOper(int) is $47
VNForCastOper(int) is $47
$281 = singleton exc set {ConvOverflowExc($1c2, $47)}
$281 = singleton exc set {ConvOverflowExc($1c2, $47)}
N015 [000056] cast_ovfl => $242 {ValWithExc($241, $281)}
N016 [000063] arrMD&[,,] => $2c0 {2c0}
fgCurHeapVN assigned by assign-of-IND at [000047] to new unique VN: $300.
N018 [000047] = => $VN.Void
***** BB01, stmt 2 (after)
N001 ( 3, 2) [000064] ------------ /--* lclVar long V04 loc0 u:3 $1c0
N018 ( 64, 58) [000047] -A-X----R--- * = long $VN.Void
N017 ( 57, 52) [000048] ---X---N---- \--* indir long $1c0
N016 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref $2c0
N002 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1 u:2 (last use) $c0
N008 ( 19, 20) [000049] ---X-------- +--* cast_ovfl int <- long $242
N005 ( 5, 6) [000052] ---------U-- | | /--* cast long <- ulong <- uint $1c1
N004 ( 4, 4) [000053] ------------ | | | \--* cast int <- ubyte <- int $240
N003 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3 u:2 $140
N007 ( 12, 12) [000050] --------R--- | \--* - long $1c2
N006 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2 u:2 $100
N009 ( 1, 1) [000055] ------------ +--* const int 0 $40
N015 ( 19, 20) [000056] ---X-------- \--* cast_ovfl int <- long $242
N012 ( 5, 6) [000059] ---------U-- | /--* cast long <- ulong <- uint $1c1
N011 ( 4, 4) [000060] ------------ | | \--* cast int <- ubyte <- int $240
N010 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use) $140
N014 ( 12, 12) [000057] --------R--- \--* - long $1c2
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use) $100
---------
***** BB01, stmt 3 (before)
N007 ( 6, 5) [000067] ---XG------- * return long
N006 ( 5, 4) [000068] ---XG------- \--* indir long
N004 ( 1, 1) [000070] ------------ | /--* lclVar int V00 arg0 u:2 (last use)
N005 ( 3, 3) [000069] -------N---- \--* + int
N002 ( 1, 1) [000073] ------------ | /--* const int 3
N003 ( 2, 2) [000071] -------N---- \--* << int
N001 ( 1, 1) [000072] C----------- \--* lclVar int V04 loc0 u:3 (last use)
VNForCastOper(int) is $47
N001 [000072] lclVar V04 loc0 u:3 (last use) => $243 {Cast($1c0, $47)}
N002 [000073] const 3 => $43 {IntCns 3}
N003 [000071] << => $244 {<<($243, $43)}
N004 [000070] lclVar V00 arg0 u:2 (last use) => $80 {InitVal($40)}
N005 [000069] + => $245 {+($80, $244)}
N006 [000068] indir => $201 {201}
N007 [000067] return => $202 {202}
***** BB01, stmt 3 (after)
N007 ( 6, 5) [000067] ---XG------- * return long $202
N006 ( 5, 4) [000068] ---XG------- \--* indir long $201
N004 ( 1, 1) [000070] ------------ | /--* lclVar int V00 arg0 u:2 (last use) $80
N005 ( 3, 3) [000069] -------N---- \--* + int $245
N002 ( 1, 1) [000073] ------------ | /--* const int 3 $43
N003 ( 2, 2) [000071] -------N---- \--* << int $244
N001 ( 1, 1) [000072] C----------- \--* lclVar int V04 loc0 u:3 (last use) $243
finish(BB01).
*************** In optVnCopyProp()
*************** In SsaBuilder::ComputeDominators(Compiler*, ...)
Copy Assertion for BB01
Live vars: {V00 V01 V02 V03} => {V00 V01 V02 V03 V04}
Live vars: {V00 V01 V02 V03 V04} => {V00 V02 V03 V04}
Live vars: {V00 V02 V03 V04} => {V00 V02 V04}
Live vars: {V00 V02 V04} => {V00 V04}
Live vars: {V00 V04} => {V00}
Live vars: {V00} => {}
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
( 17, 22) [000020] ------------ * stmtExpr void (IL 0x000...0x012)
N002 ( 3, 10) [000040] ------------ | /--* lconst long 0x0000000000000001 $181
N003 ( 10, 16) [000038] ------------ | /--* - long $1c0
N001 ( 3, 2) [000039] ------------ | | \--* lclVar long V02 arg2 u:2 $100
N005 ( 17, 22) [000036] -A------R--- \--* = long $1c0
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0 d:3 $1c0
***** BB01, stmt 2
( 64, 58) [000025] ------------ * stmtExpr void (IL ???...0x029)
N001 ( 3, 2) [000064] ------------ | /--* lclVar long V04 loc0 u:3 $1c0
N018 ( 64, 58) [000047] -A-X----R--- \--* = long $VN.Void
N017 ( 57, 52) [000048] ---X---N---- \--* indir long $1c0
N016 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref $2c0
N002 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1 u:2 (last use) $c0
N008 ( 19, 20) [000049] ---X-------- +--* cast_ovfl int <- long $242
N005 ( 5, 6) [000052] ---------U-- | | /--* cast long <- ulong <- uint $1c1
N004 ( 4, 4) [000053] ------------ | | | \--* cast int <- ubyte <- int $240
N003 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3 u:2 $140
N007 ( 12, 12) [000050] --------R--- | \--* - long $1c2
N006 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2 u:2 $100
N009 ( 1, 1) [000055] ------------ +--* const int 0 $40
N015 ( 19, 20) [000056] ---X-------- \--* cast_ovfl int <- long $242
N012 ( 5, 6) [000059] ---------U-- | /--* cast long <- ulong <- uint $1c1
N011 ( 4, 4) [000060] ------------ | | \--* cast int <- ubyte <- int $240
N010 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use) $140
N014 ( 12, 12) [000057] --------R--- \--* - long $1c2
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use) $100
***** BB01, stmt 3
( 6, 5) [000035] ------------ * stmtExpr void (IL 0x018... ???)
N007 ( 6, 5) [000067] ---XG------- \--* return long $202
N006 ( 5, 4) [000068] ---XG------- \--* indir long $201
N004 ( 1, 1) [000070] ------------ | /--* lclVar int V00 arg0 u:2 (last use) $80
N005 ( 3, 3) [000069] -------N---- \--* + int $245
N002 ( 1, 1) [000073] ------------ | /--* const int 3 $43
N003 ( 2, 2) [000071] -------N---- \--* << int $244
N001 ( 1, 1) [000072] C----------- \--* lclVar int V04 loc0 u:3 (last use) $243
------------ BB02 [???..???) (throw), preds={} succs={}
***** BB02, stmt 4
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
***** BB03, stmt 5
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
CSE candidate #01, vn=$240 cseMask=0000000000000001 in BB01, [cost= 4, size= 4]:
N011 ( 4, 4) CSE #01 (use)[000060] ------------ * cast int <- ubyte <- int $240
N010 ( 3, 2) [000061] ------------ \--* lclVar int V03 arg3 u:2 (last use) $140
CSE candidate #02, vn=$1c1 cseMask=0000000000000002 in BB01, [cost= 5, size= 6]:
N012 ( 5, 6) CSE #02 (use)[000059] ---------U-- * cast long <- ulong <- uint $1c1
N011 ( 4, 4) CSE #01 (use)[000060] ------------ \--* cast int <- ubyte <- int $240
N010 ( 3, 2) [000061] ------------ \--* lclVar int V03 arg3 u:2 (last use) $140
CSE candidate #03, vn=$1c2 cseMask=0000000000000004 in BB01, [cost=12, size=12]:
N012 ( 5, 6) CSE #02 (use)[000059] ---------U-- /--* cast long <- ulong <- uint $1c1
N011 ( 4, 4) CSE #01 (use)[000060] ------------ | \--* cast int <- ubyte <- int $240
N010 ( 3, 2) [000061] ------------ | \--* lclVar int V03 arg3 u:2 (last use) $140
N014 ( 12, 12) CSE #03 (use)[000057] --------R--- * - long $1c2
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use) $100
CSE candidate #04, vn=$242 cseMask=0000000000000008 in BB01, [cost=19, size=20]:
N015 ( 19, 20) CSE #04 (use)[000056] ---X-------- * cast_ovfl int <- long $242
N012 ( 5, 6) CSE #02 (use)[000059] ---------U-- | /--* cast long <- ulong <- uint $1c1
N011 ( 4, 4) CSE #01 (use)[000060] ------------ | | \--* cast int <- ubyte <- int $240
N010 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use) $140
N014 ( 12, 12) CSE #03 (use)[000057] --------R--- \--* - long $1c2
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use) $100
Blocks that generate CSE def/uses
BB01 cseGen = 000000000000000F
After performing DataFlow for ValnumCSE's
BB01 cseIn = 0000000000000000 cseOut = 000000000000000F
BB02 cseIn = FFFFFFFFFFFFFFFF cseOut = FFFFFFFFFFFFFFFF
BB03 cseIn = FFFFFFFFFFFFFFFF cseOut = FFFFFFFFFFFFFFFF
Labeling the CSEs with Use/Def information
BB01 [000053] Def of CSE #01 [weight= 1 ]
BB01 [000052] Def of CSE #02 [weight= 1 ]
BB01 [000050] Def of CSE #03 [weight= 1 ]
BB01 [000049] Def of CSE #04 [weight= 1 ]
BB01 [000060] Use of CSE #01 [weight= 1 ]
BB01 [000059] Use of CSE #02 [weight= 1 ]
BB01 [000057] Use of CSE #03 [weight= 1 ]
BB01 [000056] Use of CSE #04 [weight= 1 ]
************ Trees at start of optValnumCSE_Heuristic()
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
( 17, 22) [000020] ------------ * stmtExpr void (IL 0x000...0x012)
N002 ( 3, 10) [000040] ------------ | /--* lconst long 0x0000000000000001 $181
N003 ( 10, 16) [000038] ------------ | /--* - long $1c0
N001 ( 3, 2) [000039] ------------ | | \--* lclVar long V02 arg2 u:2 $100
N005 ( 17, 22) [000036] -A------R--- \--* = long $1c0
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0 d:3 $1c0
***** BB01, stmt 2
( 64, 58) [000025] ------------ * stmtExpr void (IL ???...0x029)
N001 ( 3, 2) [000064] ------------ | /--* lclVar long V04 loc0 u:3 $1c0
N018 ( 64, 58) [000047] -A-X----R--- \--* = long $VN.Void
N017 ( 57, 52) [000048] ---X---N---- \--* indir long $1c0
N016 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref $2c0
N002 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1 u:2 (last use) $c0
N008 ( 19, 20) CSE #04 (def)[000049] ---X-------- +--* cast_ovfl int <- long $242
N005 ( 5, 6) CSE #02 (def)[000052] ---------U-- | | /--* cast long <- ulong <- uint $1c1
N004 ( 4, 4) CSE #01 (def)[000053] ------------ | | | \--* cast int <- ubyte <- int $240
N003 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3 u:2 $140
N007 ( 12, 12) CSE #03 (def)[000050] --------R--- | \--* - long $1c2
N006 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2 u:2 $100
N009 ( 1, 1) [000055] ------------ +--* const int 0 $40
N015 ( 19, 20) CSE #04 (use)[000056] ---X-------- \--* cast_ovfl int <- long $242
N012 ( 5, 6) CSE #02 (use)[000059] ---------U-- | /--* cast long <- ulong <- uint $1c1
N011 ( 4, 4) CSE #01 (use)[000060] ------------ | | \--* cast int <- ubyte <- int $240
N010 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use) $140
N014 ( 12, 12) CSE #03 (use)[000057] --------R--- \--* - long $1c2
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use) $100
***** BB01, stmt 3
( 6, 5) [000035] ------------ * stmtExpr void (IL 0x018... ???)
N007 ( 6, 5) [000067] ---XG------- \--* return long $202
N006 ( 5, 4) [000068] ---XG------- \--* indir long $201
N004 ( 1, 1) [000070] ------------ | /--* lclVar int V00 arg0 u:2 (last use) $80
N005 ( 3, 3) [000069] -------N---- \--* + int $245
N002 ( 1, 1) [000073] ------------ | /--* const int 3 $43
N003 ( 2, 2) [000071] -------N---- \--* << int $244
N001 ( 1, 1) [000072] C----------- \--* lclVar int V04 loc0 u:3 (last use) $243
------------ BB02 [???..???) (throw), preds={} succs={}
***** BB02, stmt 4
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
***** BB03, stmt 5
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
Aggressive CSE Promotion cutoff is 400
Moderate CSE Promotion cutoff is 150
Framesize estimate is 0x0010
We have a small frame
Sorted CSE candidates:
CSE #04,cseMask=0000000000000008,useCnt=1: [def=100, use=100] :: N008 ( 19, 20) CSE #04 (def)[000049] ---X-------- * cast_ovfl int <- long $242
CSE #03,cseMask=0000000000000004,useCnt=1: [def=100, use=100] :: N007 ( 12, 12) CSE #03 (def)[000050] --------R--- * - long $1c2
CSE #02,cseMask=0000000000000002,useCnt=1: [def=100, use=100] :: N005 ( 5, 6) CSE #02 (def)[000052] ---------U-- * cast long <- ulong <- uint $1c1
CSE #01,cseMask=0000000000000001,useCnt=1: [def=100, use=100] :: N004 ( 4, 4) CSE #01 (def)[000053] ------------ * cast int <- ubyte <- int $240
Considering CSE #04 [def=100, use=100, cost=19] CSE Expression:
N008 ( 19, 20) CSE #04 (def)[000049] ---X-------- * cast_ovfl int <- long $242
N005 ( 5, 6) CSE #02 (def)[000052] ---------U-- | /--* cast long <- ulong <- uint $1c1
N004 ( 4, 4) CSE #01 (def)[000053] ------------ | | \--* cast int <- ubyte <- int $240
N003 ( 3, 2) [000054] ------------ | | \--* lclVar int V03 arg3 u:2 $140
N007 ( 12, 12) CSE #03 (def)[000050] --------R--- \--* - long $1c2
N006 ( 3, 2) [000051] ------------ \--* lclVar long V02 arg2 u:2 $100
*** JitStress: STRESS_MAKE_CSE ***
JitStressBiasedCSE is OFF, but JitStress is ON: generated bias=26.
No CSE because gen=68 >= bias=26
Did Not promote this CSE
Considering CSE #03 [def=100, use=100, cost=12] CSE Expression:
N005 ( 5, 6) CSE #02 (def)[000052] ---------U-- /--* cast long <- ulong <- uint $1c1
N004 ( 4, 4) CSE #01 (def)[000053] ------------ | \--* cast int <- ubyte <- int $240
N003 ( 3, 2) [000054] ------------ | \--* lclVar int V03 arg3 u:2 $140
N007 ( 12, 12) CSE #03 (def)[000050] --------R--- * - long $1c2
N006 ( 3, 2) [000051] ------------ \--* lclVar long V02 arg2 u:2 $100
JitStressBiasedCSE is OFF, but JitStress is ON: generated bias=26.
No CSE because gen=64 >= bias=26
Did Not promote this CSE
Considering CSE #02 [def=100, use=100, cost= 5] CSE Expression:
N005 ( 5, 6) CSE #02 (def)[000052] ---------U-- * cast long <- ulong <- uint $1c1
N004 ( 4, 4) CSE #01 (def)[000053] ------------ \--* cast int <- ubyte <- int $240
N003 ( 3, 2) [000054] ------------ \--* lclVar int V03 arg3 u:2 $140
JitStressBiasedCSE is OFF, but JitStress is ON: generated bias=26.
No CSE because gen=37 >= bias=26
Did Not promote this CSE
Considering CSE #01 [def=100, use=100, cost= 4] CSE Expression:
N004 ( 4, 4) CSE #01 (def)[000053] ------------ * cast int <- ubyte <- int $240
N003 ( 3, 2) [000054] ------------ \--* lclVar int V03 arg3 u:2 $140
JitStressBiasedCSE is OFF, but JitStress is ON: generated bias=26.
No CSE because gen=81 >= bias=26
Did Not promote this CSE
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
( 17, 22) [000020] ------------ * stmtExpr void (IL 0x000...0x012)
N002 ( 3, 10) [000040] ------------ | /--* lconst long 0x0000000000000001 $181
N003 ( 10, 16) [000038] ------------ | /--* - long $1c0
N001 ( 3, 2) [000039] ------------ | | \--* lclVar long V02 arg2 u:2 $100
N005 ( 17, 22) [000036] -A------R--- \--* = long $1c0
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0 d:3 $1c0
***** BB01, stmt 2
( 64, 58) [000025] ------------ * stmtExpr void (IL ???...0x029)
N001 ( 3, 2) [000064] ------------ | /--* lclVar long V04 loc0 u:3 $1c0
N018 ( 64, 58) [000047] -A-X----R--- \--* = long $VN.Void
N017 ( 57, 52) [000048] ---X---N---- \--* indir long $1c0
N016 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref $2c0
N002 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1 u:2 (last use) $c0
N008 ( 19, 20) [000049] ---X-------- +--* cast_ovfl int <- long $242
N005 ( 5, 6) [000052] ---------U-- | | /--* cast long <- ulong <- uint $1c1
N004 ( 4, 4) [000053] ------------ | | | \--* cast int <- ubyte <- int $240
N003 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3 u:2 $140
N007 ( 12, 12) [000050] --------R--- | \--* - long $1c2
N006 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2 u:2 $100
N009 ( 1, 1) [000055] ------------ +--* const int 0 $40
N015 ( 19, 20) [000056] ---X-------- \--* cast_ovfl int <- long $242
N012 ( 5, 6) [000059] ---------U-- | /--* cast long <- ulong <- uint $1c1
N011 ( 4, 4) [000060] ------------ | | \--* cast int <- ubyte <- int $240
N010 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use) $140
N014 ( 12, 12) [000057] --------R--- \--* - long $1c2
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use) $100
***** BB01, stmt 3
( 6, 5) [000035] ------------ * stmtExpr void (IL 0x018... ???)
N007 ( 6, 5) [000067] ---XG------- \--* return long $202
N006 ( 5, 4) [000068] ---XG------- \--* indir long $201
N004 ( 1, 1) [000070] ------------ | /--* lclVar int V00 arg0 u:2 (last use) $80
N005 ( 3, 3) [000069] -------N---- \--* + int $245
N002 ( 1, 1) [000073] ------------ | /--* const int 3 $43
N003 ( 2, 2) [000071] -------N---- \--* << int $244
N001 ( 1, 1) [000072] C----------- \--* lclVar int V04 loc0 u:3 (last use) $243
------------ BB02 [???..???) (throw), preds={} succs={}
***** BB02, stmt 4
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
***** BB03, stmt 5
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N004 ( 4, 4) [000053] ------------ * cast int <- ubyte <- int $240
In BB01 New Global Subrange Assertion: (320, 0) ($140,$0) V03.02 in [0..255] index=#01, mask=0000000000000001
GenTreeNode creates assertion:
N016 ( 54, 50) [000063] ---X-------- * arrMD&[,,] byref $2c0
In BB01 New Global Constant Assertion: (192, 0) ($c0,$0) V01.02 != null index=#02, mask=0000000000000002
BB01 valueGen = 0000000000000002
BB02 valueGen = 0000000000000000
BB03 valueGen = 0000000000000000AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000
AssertionPropCallback::Changed : BB01 before out -> 0000000000000003; after out -> 0000000000000002;
jumpDest before out -> 0000000000000003; jumpDest after out -> 0000000000000000;
BB01 valueIn = 0000000000000000 valueOut = 0000000000000002
BB02 valueIn = 0000000000000003 valueOut = 0000000000000003
BB03 valueIn = 0000000000000003 valueOut = 0000000000000003
Propagating 0000000000000000 assertions for BB01, stmt [000020], tree [000039], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000020], tree [000040], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000020], tree [000038], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000020], tree [000037], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000020], tree [000036], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000064], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000062], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000054], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000053], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000052], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000051], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000050], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000049], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000055], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000061], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000060], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000059], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000058], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000057], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000056], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000025], tree [000063], tree -> 2
Propagating 0000000000000002 assertions for BB01, stmt [000025], tree [000048], tree -> 0
Propagating 0000000000000002 assertions for BB01, stmt [000025], tree [000047], tree -> 0
Propagating 0000000000000002 assertions for BB01, stmt [000035], tree [000072], tree -> 0
Propagating 0000000000000002 assertions for BB01, stmt [000035], tree [000073], tree -> 0
Propagating 0000000000000002 assertions for BB01, stmt [000035], tree [000071], tree -> 0
Propagating 0000000000000002 assertions for BB01, stmt [000035], tree [000070], tree -> 0
Propagating 0000000000000002 assertions for BB01, stmt [000035], tree [000069], tree -> 0
Propagating 0000000000000002 assertions for BB01, stmt [000035], tree [000068], tree -> 0
Propagating 0000000000000002 assertions for BB01, stmt [000035], tree [000067], tree -> 0
Propagating 0000000000000003 assertions for BB02, stmt [000043], tree [000074], tree -> 0
Propagating 0000000000000003 assertions for BB03, stmt [000046], tree [000077], tree -> 0
*************** In fgDebugCheckBBlist
*************** In OptimizeRangeChecks()
Blocks/trees before phase
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
( 17, 22) [000020] ------------ * stmtExpr void (IL 0x000...0x012)
N002 ( 3, 10) [000040] ------------ | /--* lconst long 0x0000000000000001 $181
N003 ( 10, 16) [000038] ------------ | /--* - long $1c0
N001 ( 3, 2) [000039] ------------ | | \--* lclVar long V02 arg2 u:2 $100
N005 ( 17, 22) [000036] -A------R--- \--* = long $1c0
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0 d:3 $1c0
***** BB01, stmt 2
( 64, 58) [000025] ------------ * stmtExpr void (IL ???...0x029)
N001 ( 3, 2) [000064] ------------ | /--* lclVar long V04 loc0 u:3 $1c0
N018 ( 64, 58) [000047] -A-X----R--- \--* = long $VN.Void
N017 ( 57, 52) [000048] ---X---N---- \--* indir long $1c0
N016 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref $2c0
N002 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1 u:2 (last use) $c0
N008 ( 19, 20) [000049] ---X-------- +--* cast_ovfl int <- long $242
N005 ( 5, 6) [000052] ---------U-- | | /--* cast long <- ulong <- uint $1c1
N004 ( 4, 4) [000053] ------------ | | | \--* cast int <- ubyte <- int $240
N003 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3 u:2 $140
N007 ( 12, 12) [000050] --------R--- | \--* - long $1c2
N006 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2 u:2 $100
N009 ( 1, 1) [000055] ------------ +--* const int 0 $40
N015 ( 19, 20) [000056] ---X-------- \--* cast_ovfl int <- long $242
N012 ( 5, 6) [000059] ---------U-- | /--* cast long <- ulong <- uint $1c1
N011 ( 4, 4) [000060] ------------ | | \--* cast int <- ubyte <- int $240
N010 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use) $140
N014 ( 12, 12) [000057] --------R--- \--* - long $1c2
N013 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use) $100
***** BB01, stmt 3
( 6, 5) [000035] ------------ * stmtExpr void (IL 0x018... ???)
N007 ( 6, 5) [000067] ---XG------- \--* return long $202
N006 ( 5, 4) [000068] ---XG------- \--* indir long $201
N004 ( 1, 1) [000070] ------------ | /--* lclVar int V00 arg0 u:2 (last use) $80
N005 ( 3, 3) [000069] -------N---- \--* + int $245
N002 ( 1, 1) [000073] ------------ | /--* const int 3 $43
N003 ( 2, 2) [000071] -------N---- \--* << int $244
N001 ( 1, 1) [000072] C----------- \--* lclVar int V04 loc0 u:3 (last use) $243
------------ BB02 [???..???) (throw), preds={} succs={}
***** BB02, stmt 4
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
***** BB03, stmt 5
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*** JitStress: STRESS_REMORPH_TREES ***
test morphing morphed tree:
N002 ( 3, 10) [000040] ------------ /--* lconst long 0x0000000000000001 $181
N003 ( 10, 16) [000038] ------------ /--* - long $1c0
N001 ( 3, 2) [000039] ------------ | \--* lclVar long V02 arg2 u:2 $100
N005 ( 17, 22) [000036] -A------R--- * = long $1c0
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0 d:3 $1c0
test morphing morphed tree:
N017 ( 3, 2) [000064] ------------ /--* lclVar long V04 loc0 u:3 $1c0
N018 ( 64, 58) [000047] -A-X-------- * = long $VN.Void
N016 ( 57, 52) [000048] ---X---N---- \--* indir long $1c0
N015 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref $2c0
N001 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1 u:2 (last use) $c0
N007 ( 19, 20) [000049] ---X-------- +--* cast_ovfl int <- long $242
N004 ( 5, 6) [000052] ---------U-- | | /--* cast long <- ulong <- uint $1c1
N003 ( 4, 4) [000053] ------------ | | | \--* cast int <- ubyte <- int $240
N002 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3 u:2 $140
N006 ( 12, 12) [000050] --------R--- | \--* - long $1c2
N005 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2 u:2 $100
N008 ( 1, 1) [000055] ------------ +--* const int 0 $40
N014 ( 19, 20) [000056] ---X-------- \--* cast_ovfl int <- long $242
N011 ( 5, 6) [000059] ---------U-- | /--* cast long <- ulong <- uint $1c1
N010 ( 4, 4) [000060] ------------ | | \--* cast int <- ubyte <- int $240
N009 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use) $140
N013 ( 12, 12) [000057] --------R--- \--* - long $1c2
N012 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use) $100
test morphing morphed tree:
N007 ( 6, 5) [000067] ---XG------- * return long $202
N006 ( 5, 4) [000068] ---XG------- \--* indir long $201
N003 ( 1, 1) [000073] ------------ | /--* const int 3 $43
N004 ( 2, 2) [000071] -------N---- | /--* << int $244
N002 ( 1, 1) [000072] C----------- | | \--* lclVar int V04 loc0 u:3 (last use) $243
N005 ( 3, 3) [000069] -------N---- \--* + int $245
N001 ( 1, 1) [000070] ------------ \--* lclVar int V00 arg0 u:2 (last use) $80
We have a top-level fgIsThrow stmt
Removing the rest of block as unreachable:
test morphing morphed tree:
N001 ( 14, 5) [000074] --CXG------- * call help void HELPER.CORINFO_HELP_OVERFLOW
test morphing Block BB02 becomes a throw block.
We have a top-level fgIsThrow stmt
Removing the rest of block as unreachable:
test morphing morphed tree:
N001 ( 14, 5) [000077] --CXG------- * call help void HELPER.CORINFO_HELP_RNGCHKFAIL
test morphing Block BB03 becomes a throw block.
*************** In IR Rationalize
Trees before IR Rationalize
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
***** BB01, stmt 1
( 17, 22) [000020] ------------ * stmtExpr void (IL 0x000...0x012)
N002 ( 3, 10) [000040] ------------ | /--* lconst long 0x0000000000000001 $181
N003 ( 10, 16) [000038] ------------ | /--* - long $1c0
N001 ( 3, 2) [000039] ------------ | | \--* lclVar long V02 arg2 u:2 $100
N005 ( 17, 22) [000036] -A------R--- \--* = long $1c0
N004 ( 3, 2) [000037] D------N---- \--* lclVar long V04 loc0 d:3 $1c0
***** BB01, stmt 2
( 64, 58) [000025] ------------ * stmtExpr void (IL ???...0x029)
N017 ( 3, 2) [000064] ------------ | /--* lclVar long V04 loc0 u:3 $1c0
N018 ( 64, 58) [000047] -A-X-------- \--* = long $VN.Void
N016 ( 57, 52) [000048] ---X---N---- \--* indir long $1c0
N015 ( 54, 50) [000063] ---X-------- \--* arrMD&[,,] byref $2c0
N001 ( 1, 1) [000062] ------------ +--* lclVar ref V01 arg1 u:2 (last use) $c0
N007 ( 19, 20) [000049] ---X-------- +--* cast_ovfl int <- long $242
N004 ( 5, 6) [000052] ---------U-- | | /--* cast long <- ulong <- uint $1c1
N003 ( 4, 4) [000053] ------------ | | | \--* cast int <- ubyte <- int $240
N002 ( 3, 2) [000054] ------------ | | | \--* lclVar int V03 arg3 u:2 $140
N006 ( 12, 12) [000050] --------R--- | \--* - long $1c2
N005 ( 3, 2) [000051] ------------ | \--* lclVar long V02 arg2 u:2 $100
N008 ( 1, 1) [000055] ------------ +--* const int 0 $40
N014 ( 19, 20) [000056] ---X-------- \--* cast_ovfl int <- long $242
N011 ( 5, 6) [000059] ---------U-- | /--* cast long <- ulong <- uint $1c1
N010 ( 4, 4) [000060] ------------ | | \--* cast int <- ubyte <- int $240
N009 ( 3, 2) [000061] ------------ | | \--* lclVar int V03 arg3 u:2 (last use) $140
N013 ( 12, 12) [000057] --------R--- \--* - long $1c2
N012 ( 3, 2) [000058] ------------ \--* lclVar long V02 arg2 u:2 (last use) $100
***** BB01, stmt 3
( 6, 5) [000035] ------------ * stmtExpr void (IL 0x018... ???)
N007 ( 6, 5) [000067] ---XG------- \--* return long $202
N006 ( 5, 4) [000068] ---XG------- \--* indir long $201
N003 ( 1, 1) [000073] ------------ | /--* const int 3 $43
N004 ( 2, 2) [000071] -------N---- | /--* << int $244
N002 ( 1, 1) [000072] C----------- | | \--* lclVar int V04 loc0 u:3 (last use) $243
N005 ( 3, 3) [000069] -------N---- \--* + int $245
N001 ( 1, 1) [000070] ------------ \--* lclVar int V00 arg0 u:2 (last use) $80
------------ BB02 [???..???) (throw), preds={} succs={}
***** BB02, stmt 4
( 14, 5) [000043] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000074] --CXG------- \--* call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
***** BB03, stmt 5
( 14, 5) [000046] ------------ * stmtExpr void (IL ???... ???)
N001 ( 14, 5) [000077] --CXG------- \--* call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
rewriting asg(lclVar, X) to st.lclVar(X)
N005 ( 17, 22) [000036] DA---------- * st.lclVar long V04 loc0 d:3
*************** Exiting IR Rationalize
Trees after IR Rationalize
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
( 17, 22) [000020] ------------ il_offset void IL offset: 0
N001 ( 3, 2) [000039] ------------ t39 = lclVar long V02 arg2 u:2 $100
N002 ( 3, 10) [000040] ------------ t40 = lconst long 0x0000000000000001 $181
/--* t39 long
+--* t40 long
N003 ( 10, 16) [000038] ------------ t38 = * - long $1c0
/--* t38 long
N005 ( 17, 22) [000036] DA---------- * st.lclVar long V04 loc0 d:3
N001 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 (last use) $c0
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
/--* t53 int
N004 ( 5, 6) [000052] ---------U-- t52 = * cast long <- ulong <- uint $1c1
N005 ( 3, 2) [000051] ------------ t51 = lclVar long V02 arg2 u:2 $100
/--* t52 long
+--* t51 long
N006 ( 12, 12) [000050] --------R--- t50 = * - long $1c2
/--* t50 long
N007 ( 19, 20) [000049] ---X-------- t49 = * cast_ovfl int <- long $242
N008 ( 1, 1) [000055] ------------ t55 = const int 0 $40
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
/--* t60 int
N011 ( 5, 6) [000059] ---------U-- t59 = * cast long <- ulong <- uint $1c1
N012 ( 3, 2) [000058] ------------ t58 = lclVar long V02 arg2 u:2 (last use) $100
/--* t59 long
+--* t58 long
N013 ( 12, 12) [000057] --------R--- t57 = * - long $1c2
/--* t57 long
N014 ( 19, 20) [000056] ---X-------- t56 = * cast_ovfl int <- long $242
/--* t62 ref
+--* t49 int
+--* t55 int
+--* t56 int
N015 ( 54, 50) [000063] ---X-------- t63 = * arrMD&[,,] byref $2c0
N017 ( 3, 2) [000064] ------------ t64 = lclVar long V04 loc0 u:3 $1c0
/--* t63 byref
+--* t64 long
[000080] -A-X-------- * storeIndir long
( 6, 5) [000035] ------------ il_offset void IL offset: 24
N001 ( 1, 1) [000070] ------------ t70 = lclVar int V00 arg0 u:2 (last use) $80
N002 ( 1, 1) [000072] C----------- t72 = lclVar int V04 loc0 u:3 (last use) $243
N003 ( 1, 1) [000073] ------------ t73 = const int 3 $43
/--* t72 int
+--* t73 int
N004 ( 2, 2) [000071] -------N---- t71 = * << int $244
/--* t70 int
+--* t71 int
N005 ( 3, 3) [000069] -------N---- t69 = * + int $245
/--* t69 int
N006 ( 5, 4) [000068] ---XG------- t68 = * indir long $201
/--* t68 long
N007 ( 6, 5) [000067] ---XG------- * return long $202
------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14, 5) [000074] --CXG------- call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
N001 ( 14, 5) [000077] --CXG------- call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
After fgSimpleLowering() added some RngChk throw blocks
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
( 17, 22) [000020] ------------ il_offset void IL offset: 0
N001 ( 3, 2) [000039] ------------ t39 = lclVar long V02 arg2 u:2 $100
N002 ( 3, 10) [000040] ------------ t40 = lconst long 0x0000000000000001 $181
/--* t39 long
+--* t40 long
N003 ( 10, 16) [000038] ------------ t38 = * - long $1c0
/--* t38 long
N005 ( 17, 22) [000036] DA---------- * st.lclVar long V04 loc0 d:3
N001 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 (last use) $c0
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
/--* t53 int
N004 ( 5, 6) [000052] ---------U-- t52 = * cast long <- ulong <- uint $1c1
N005 ( 3, 2) [000051] ------------ t51 = lclVar long V02 arg2 u:2 $100
/--* t52 long
+--* t51 long
N006 ( 12, 12) [000050] --------R--- t50 = * - long $1c2
/--* t50 long
N007 ( 19, 20) [000049] ---X-------- t49 = * cast_ovfl int <- long $242
N008 ( 1, 1) [000055] ------------ t55 = const int 0 $40
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
/--* t60 int
N011 ( 5, 6) [000059] ---------U-- t59 = * cast long <- ulong <- uint $1c1
N012 ( 3, 2) [000058] ------------ t58 = lclVar long V02 arg2 u:2 (last use) $100
/--* t59 long
+--* t58 long
N013 ( 12, 12) [000057] --------R--- t57 = * - long $1c2
/--* t57 long
N014 ( 19, 20) [000056] ---X-------- t56 = * cast_ovfl int <- long $242
/--* t62 ref
+--* t49 int
+--* t55 int
+--* t56 int
N015 ( 54, 50) [000063] ---X-------- t63 = * arrMD&[,,] byref $2c0
N017 ( 3, 2) [000064] ------------ t64 = lclVar long V04 loc0 u:3 $1c0
/--* t63 byref
+--* t64 long
[000080] -A-X-------- * storeIndir long
( 6, 5) [000035] ------------ il_offset void IL offset: 24
N001 ( 1, 1) [000070] ------------ t70 = lclVar int V00 arg0 u:2 (last use) $80
N002 ( 1, 1) [000072] C----------- t72 = lclVar int V04 loc0 u:3 (last use) $243
N003 ( 1, 1) [000073] ------------ t73 = const int 3 $43
/--* t72 int
+--* t73 int
N004 ( 2, 2) [000071] -------N---- t71 = * << int $244
/--* t70 int
+--* t71 int
N005 ( 3, 3) [000069] -------N---- t69 = * + int $245
/--* t69 int
N006 ( 5, 4) [000068] ---XG------- t68 = * indir long $201
/--* t68 long
N007 ( 6, 5) [000067] ---XG------- * return long $202
------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14, 5) [000074] --CXG------- call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
N001 ( 14, 5) [000077] --CXG------- call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
Promoting long local V02:
lvaGrabTemp returning 5 (V05 rat0) (a long lifetime temp) called for field V02.lo (fldOffset=0x0).
lvaGrabTemp returning 6 (V06 rat1) (a long lifetime temp) called for field V02.hi (fldOffset=0x4).
Promoting long local V04:
lvaGrabTemp returning 7 (V07 rat2) (a long lifetime temp) called for field V04.lo (fldOffset=0x0).
lvaGrabTemp returning 8 (V08 rat3) (a long lifetime temp) called for field V04.hi (fldOffset=0x4).
lvaTable after lvaPromoteLongVars
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 ref
; V02 arg2 long
; V03 arg3 ubyte
; V04 loc0 long
; V05 rat0 int V02.lo(offs=0x00)
; V06 rat1 int V02.hi(offs=0x04)
; V07 rat2 int V04.lo(offs=0x00)
; V08 rat3 int V04.hi(offs=0x04)
Decomposing TYP_LONG tree. BEFORE:
N001 ( 3, 2) [000039] ------------ t39 = lclVar long (P) V02 arg2 u:2
* int V02.hi (offs=0x00) -> V05 rat0
* int V02.hi (offs=0x04) -> V06 rat1 $100
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 3, refCntWtd = 2
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 4, refCntWtd = 2
New refCnts for V06: refCnt = 1, refCntWtd = 1
Decomposing TYP_LONG tree. AFTER:
N001 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 $100
[000081] ------------ t81 = lclVar int V06 rat1
/--* t39 int
+--* t81 int
[000082] ------------ t82 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N002 ( 3, 10) [000040] ------------ t40 = lconst long 0x0000000000000001 $181
Decomposing TYP_LONG tree. AFTER:
N002 ( 3, 10) [000040] ------------ t40 = const int 1
[000083] ------------ t83 = const int 0
/--* t40 int
+--* t83 int
[000084] ------------ t84 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N001 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 $100
[000081] ------------ t81 = lclVar int V06 rat1
/--* t39 int
+--* t81 int
[000082] ------------ t82 = * gt_long long
N002 ( 3, 10) [000040] ------------ t40 = const int 1
[000083] ------------ t83 = const int 0
/--* t40 int
+--* t83 int
[000084] ------------ t84 = * gt_long long
/--* t82 long
+--* t84 long
N003 ( 10, 16) [000038] ------------ t38 = * - long $1c0
Decomposing TYP_LONG tree. AFTER:
N001 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 $100
[000081] ------------ t81 = lclVar int V06 rat1
N002 ( 3, 10) [000040] ------------ t40 = const int 1
[000083] ------------ t83 = const int 0
/--* t39 int
+--* t40 int
N003 ( 10, 16) [000038] ------------ t38 = * -Lo int
/--* t81 int
+--* t83 int
[000085] ------------ t85 = * -Hi int
/--* t38 int
+--* t85 int
[000086] ------------ t86 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N001 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 $100
[000081] ------------ t81 = lclVar int V06 rat1
N002 ( 3, 10) [000040] ------------ t40 = const int 1
[000083] ------------ t83 = const int 0
/--* t39 int
+--* t40 int
N003 ( 10, 16) [000038] ------------ t38 = * -Lo int
/--* t81 int
+--* t83 int
[000085] ------------ t85 = * -Hi int
/--* t38 int
+--* t85 int
[000086] ------------ t86 = * gt_long long
/--* t86 long
N005 ( 17, 22) [000036] DA---------- * st.lclVar long (P) V04 loc0 d:3
* int V04.hi (offs=0x00) -> V07 rat2
* int V04.hi (offs=0x04) -> V08 rat3
New refCnts for V04: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V08: refCnt = 1, refCntWtd = 1
Decomposing TYP_LONG tree. AFTER:
N001 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 $100
[000081] ------------ t81 = lclVar int V06 rat1
N002 ( 3, 10) [000040] ------------ t40 = const int 1
[000083] ------------ t83 = const int 0
/--* t39 int
+--* t40 int
N003 ( 10, 16) [000038] ------------ t38 = * -Lo int
/--* t81 int
+--* t83 int
[000085] ------------ t85 = * -Hi int
/--* t38 int
N005 ( 17, 22) [000036] DA---------- * st.lclVar int V07 rat2
Decomposing TYP_LONG tree. BEFORE:
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
/--* t53 int
N004 ( 5, 6) [000052] ---------U-- t52 = * cast long <- ulong <- uint $1c1
Decomposing TYP_LONG tree. AFTER:
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
[000088] ------------ t88 = const int 0
/--* t53 int
+--* t88 int
[000089] ------------ t89 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N005 ( 3, 2) [000051] ------------ t51 = lclVar long (P) V02 arg2 u:2
* int V02.hi (offs=0x00) -> V05 rat0
* int V02.hi (offs=0x04) -> V06 rat1 $100
New refCnts for V02: refCnt = 3, refCntWtd = 1
New refCnts for V02: refCnt = 4, refCntWtd = 1
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 5, refCntWtd = 1
New refCnts for V06: refCnt = 2, refCntWtd = 2
Decomposing TYP_LONG tree. AFTER:
N005 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 $100
[000090] ------------ t90 = lclVar int V06 rat1
/--* t51 int
+--* t90 int
[000091] ------------ t91 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
[000088] ------------ t88 = const int 0
/--* t53 int
+--* t88 int
[000089] ------------ t89 = * gt_long long
N005 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 $100
[000090] ------------ t90 = lclVar int V06 rat1
/--* t51 int
+--* t90 int
[000091] ------------ t91 = * gt_long long
/--* t89 long
+--* t91 long
N006 ( 12, 12) [000050] --------R--- t50 = * - long $1c2
Decomposing TYP_LONG tree. AFTER:
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
[000088] ------------ t88 = const int 0
N005 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 $100
[000090] ------------ t90 = lclVar int V06 rat1
/--* t53 int
+--* t51 int
N006 ( 12, 12) [000050] --------R--- t50 = * -Lo int
/--* t90 int
+--* t88 int
[000092] ------------ t92 = * -Hi int
/--* t50 int
+--* t92 int
[000093] ------------ t93 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
/--* t60 int
N011 ( 5, 6) [000059] ---------U-- t59 = * cast long <- ulong <- uint $1c1
Decomposing TYP_LONG tree. AFTER:
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
[000094] ------------ t94 = const int 0
/--* t60 int
+--* t94 int
[000095] ------------ t95 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N012 ( 3, 2) [000058] ------------ t58 = lclVar long (P) V02 arg2 u:2
* int V02.hi (offs=0x00) -> V05 rat0
* int V02.hi (offs=0x04) -> V06 rat1 $100
New refCnts for V02: refCnt = 4, refCntWtd = 0
New refCnts for V02: refCnt = 5, refCntWtd = 0
New refCnts for V05: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 6, refCntWtd = 0
New refCnts for V06: refCnt = 3, refCntWtd = 3
Decomposing TYP_LONG tree. AFTER:
N012 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 $100
[000096] ------------ t96 = lclVar int V06 rat1
/--* t58 int
+--* t96 int
[000097] ------------ t97 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
[000094] ------------ t94 = const int 0
/--* t60 int
+--* t94 int
[000095] ------------ t95 = * gt_long long
N012 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 $100
[000096] ------------ t96 = lclVar int V06 rat1
/--* t58 int
+--* t96 int
[000097] ------------ t97 = * gt_long long
/--* t95 long
+--* t97 long
N013 ( 12, 12) [000057] --------R--- t57 = * - long $1c2
Decomposing TYP_LONG tree. AFTER:
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
[000094] ------------ t94 = const int 0
N012 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 $100
[000096] ------------ t96 = lclVar int V06 rat1
/--* t60 int
+--* t58 int
N013 ( 12, 12) [000057] --------R--- t57 = * -Lo int
/--* t96 int
+--* t94 int
[000098] ------------ t98 = * -Hi int
/--* t57 int
+--* t98 int
[000099] ------------ t99 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N017 ( 3, 2) [000064] ------------ t64 = lclVar long (P) V04 loc0 u:3
* int V04.hi (offs=0x00) -> V07 rat2
* int V04.hi (offs=0x04) -> V08 rat3 $1c0
New refCnts for V04: refCnt = 1, refCntWtd = 1
New refCnts for V07: refCnt = 2, refCntWtd = 2
New refCnts for V08: refCnt = 2, refCntWtd = 2
Decomposing TYP_LONG tree. AFTER:
N017 ( 3, 2) [000064] ------------ t64 = lclVar int V07 rat2 $1c0
[000100] ------------ t100 = lclVar int V08 rat3
/--* t64 int
+--* t100 int
[000101] ------------ t101 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
N001 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 (last use) $c0
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
[000088] ------------ t88 = const int 0
N005 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 $100
[000090] ------------ t90 = lclVar int V06 rat1
/--* t53 int
+--* t51 int
N006 ( 12, 12) [000050] --------R--- t50 = * -Lo int
/--* t90 int
+--* t88 int
[000092] ------------ t92 = * -Hi int
/--* t50 int
+--* t92 int
[000093] ------------ t93 = * gt_long long
/--* t93 long
N007 ( 19, 20) [000049] ---X-------- t49 = * cast_ovfl int <- long $242
N008 ( 1, 1) [000055] ------------ t55 = const int 0 $40
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
[000094] ------------ t94 = const int 0
N012 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 $100
[000096] ------------ t96 = lclVar int V06 rat1
/--* t60 int
+--* t58 int
N013 ( 12, 12) [000057] --------R--- t57 = * -Lo int
/--* t96 int
+--* t94 int
[000098] ------------ t98 = * -Hi int
/--* t57 int
+--* t98 int
[000099] ------------ t99 = * gt_long long
/--* t99 long
N014 ( 19, 20) [000056] ---X-------- t56 = * cast_ovfl int <- long $242
/--* t62 ref
+--* t49 int
+--* t55 int
+--* t56 int
N015 ( 54, 50) [000063] ---X-------- t63 = * arrMD&[,,] byref $2c0
N017 ( 3, 2) [000064] ------------ t64 = lclVar int V07 rat2 $1c0
[000100] ------------ t100 = lclVar int V08 rat3
/--* t64 int
+--* t100 int
[000101] ------------ t101 = * gt_long long
/--* t63 byref
+--* t101 long
[000080] -A-X-------- * storeIndir long
lvaGrabTemp returning 9 (V09 rat4) called for ReplaceWithLclVar is creating a new local variable.
New refCnts for V09: refCnt = 1, refCntWtd = 2
New refCnts for V09: refCnt = 2, refCntWtd = 4
rewriting asg(lclVar, X) to st.lclVar(X)
[000103] DA-X-------- * st.lclVar byref V09 rat4
ReplaceWithLclVar created store :
[000103] DA-X-------- * st.lclVar byref V09 rat4
[DecomposeStoreInd]: Saving address tree to a temp var:
[000104] ------------ t104 = lclVar byref V09 rat4
New refCnts for V09: refCnt = 3, refCntWtd = 6
Decomposing TYP_LONG tree. AFTER:
[000104] ------------ t104 = lclVar byref V09 rat4
N017 ( 3, 2) [000064] ------------ t64 = lclVar int V07 rat2 $1c0
/--* t104 byref
+--* t64 int
[000080] -A-X-------- * storeIndir int
Changing implicit reference to lo half of long lclVar to an explicit reference of its promoted half:
N002 ( 1, 1) [000072] C----------- t72 = lclVar int (P) V04 loc0 u:3
* int V04.hi (offs=0x00) -> V07 rat2
* int V04.hi (offs=0x04) -> V08 rat3 $243
New refCnts for V04: refCnt = 0, refCntWtd = 0
New refCnts for V07: refCnt = 3, refCntWtd = 3
Decomposing TYP_LONG tree. BEFORE:
N001 ( 1, 1) [000070] ------------ t70 = lclVar int V00 arg0 u:2 (last use) $80
N002 ( 1, 1) [000072] C----------- t72 = lclVar int V07 rat2 $243
N003 ( 1, 1) [000073] ------------ t73 = const int 3 $43
/--* t72 int
+--* t73 int
N004 ( 2, 2) [000071] -------N---- t71 = * << int $244
/--* t70 int
+--* t71 int
N005 ( 3, 3) [000069] -------N---- t69 = * + int $245
/--* t69 int
N006 ( 5, 4) [000068] ---XG------- t68 = * indir long $201
lvaGrabTemp returning 10 (V10 rat5) called for ReplaceWithLclVar is creating a new local variable.
New refCnts for V10: refCnt = 1, refCntWtd = 2
New refCnts for V10: refCnt = 2, refCntWtd = 4
rewriting asg(lclVar, X) to st.lclVar(X)
[000109] DA---------- * st.lclVar int V10 rat5
ReplaceWithLclVar created store :
[000109] DA---------- * st.lclVar int V10 rat5
[DecomposeInd]: Saving addr tree to a temp var:
[000110] ------------ t110 = lclVar int V10 rat5
New refCnts for V10: refCnt = 3, refCntWtd = 6
Decomposing TYP_LONG tree. AFTER:
[000110] ------------ t110 = lclVar int V10 rat5
/--* t110 int
N006 ( 5, 4) [000068] ---XG------- t68 = * indir int $201
[000111] ------------ t111 = lclVar int V10 rat5
/--* t111 int
[000112] ------------ t112 = * lea(b+4) ref
/--* t112 ref
[000113] ---XG------- t113 = * indir int
/--* t68 int
+--* t113 int
[000114] ---XG------- t114 = * gt_long long
Decomposing TYP_LONG tree. BEFORE:
[000110] ------------ t110 = lclVar int V10 rat5
/--* t110 int
N006 ( 5, 4) [000068] ---XG------- t68 = * indir int $201
[000111] ------------ t111 = lclVar int V10 rat5
/--* t111 int
[000112] ------------ t112 = * lea(b+4) ref
/--* t112 ref
[000113] ---XG------- t113 = * indir int
/--* t68 int
+--* t113 int
[000114] ---XG------- t114 = * gt_long long
/--* t114 long
N007 ( 6, 5) [000067] ---XG------- * return long $202
Decomposing TYP_LONG tree. AFTER:
[000110] ------------ t110 = lclVar int V10 rat5
/--* t110 int
N006 ( 5, 4) [000068] ---XG------- t68 = * indir int $201
[000111] ------------ t111 = lclVar int V10 rat5
/--* t111 int
[000112] ------------ t112 = * lea(b+4) ref
/--* t112 ref
[000113] ---XG------- t113 = * indir int
/--* t68 int
+--* t113 int
[000114] ---XG------- t114 = * gt_long long
/--* t114 long
N007 ( 6, 5) [000067] ---XG------- * return long $202
Lowering ArrElem
============
N001 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 (last use) $c0
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
[000088] ------------ t88 = const int 0
N005 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 $100
[000090] ------------ t90 = lclVar int V06 rat1
/--* t53 int
+--* t51 int
N006 ( 12, 12) [000050] --------R--- t50 = * -Lo int
/--* t90 int
+--* t88 int
[000092] ------------ t92 = * -Hi int
/--* t50 int
+--* t92 int
[000093] ------------ t93 = * gt_long long
/--* t93 long
N007 ( 19, 20) [000049] ---X-------- t49 = * cast_ovfl int <- long $242
N008 ( 1, 1) [000055] ------------ t55 = const int 0 $40
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
[000094] ------------ t94 = const int 0
N012 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 $100
[000096] ------------ t96 = lclVar int V06 rat1
/--* t60 int
+--* t58 int
N013 ( 12, 12) [000057] --------R--- t57 = * -Lo int
/--* t96 int
+--* t94 int
[000098] ------------ t98 = * -Hi int
/--* t57 int
+--* t98 int
[000099] ------------ t99 = * gt_long long
/--* t99 long
N014 ( 19, 20) [000056] ---X-------- t56 = * cast_ovfl int <- long $242
/--* t62 ref
+--* t49 int
+--* t55 int
+--* t56 int
N015 ( 54, 50) [000063] ---X-------- t63 = * arrMD&[,,] byref $2c0
Results of lowering ArrElem:
N001 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 (last use) $c0
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
[000088] ------------ t88 = const int 0
N005 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 $100
[000090] ------------ t90 = lclVar int V06 rat1
/--* t53 int
+--* t51 int
N006 ( 12, 12) [000050] --------R--- t50 = * -Lo int
/--* t90 int
+--* t88 int
[000092] ------------ t92 = * -Hi int
/--* t50 int
+--* t92 int
[000093] ------------ t93 = * gt_long long
/--* t93 long
N007 ( 19, 20) [000049] ---X-------- t49 = * cast_ovfl int <- long $242
N008 ( 1, 1) [000055] ------------ t55 = const int 0 $40
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
[000094] ------------ t94 = const int 0
N012 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 $100
[000096] ------------ t96 = lclVar int V06 rat1
/--* t60 int
+--* t58 int
N013 ( 12, 12) [000057] --------R--- t57 = * -Lo int
/--* t96 int
+--* t94 int
[000098] ------------ t98 = * -Hi int
/--* t57 int
+--* t98 int
[000099] ------------ t99 = * gt_long long
/--* t99 long
N014 ( 19, 20) [000056] ---X-------- t56 = * cast_ovfl int <- long $242
[000115] ------------ t115 = const int 0
/--* t62 ref
+--* t49 int
[000116] ---X-------- t116 = * arrMDIdx[i, , ] int
[000117] ------------ t117 = lclVar ref V01 arg1 (last use)
/--* t115 int
+--* t116 int
+--* t117 ref
[000118] ---X-------- t118 = * arrMDOffs[i, , ] int
[000119] ------------ t119 = lclVar ref V01 arg1 (last use)
/--* t119 ref
+--* t55 int
[000120] ---X-------- t120 = * arrMDIdx[*,j, ] int
[000121] ------------ t121 = lclVar ref V01 arg1 (last use)
/--* t118 int
+--* t120 int
+--* t121 ref
[000122] ---X-------- t122 = * arrMDOffs[*,j, ] int
[000123] ------------ t123 = lclVar ref V01 arg1 (last use)
/--* t123 ref
+--* t56 int
[000124] ---X-------- t124 = * arrMDIdx[*,*,k] int
[000125] ------------ t125 = lclVar ref V01 arg1 (last use)
/--* t122 int
+--* t124 int
+--* t125 ref
[000126] ---X-------- t126 = * arrMDOffs[*,*,k] int
[000127] ------------ t127 = lclVar ref V01 arg1 (last use)
/--* t126 int
+--* t127 ref
[000128] ---X----R--- t128 = * lea(b+(i*8)+32) byref
No addressing mode
No addressing mode
Addressing mode:
Base
N001 ( 1, 1) [000070] ------------ * lclVar int V00 arg0 u:2 (last use) $80
+ Index * 8 + 0
N002 ( 1, 1) [000072] C----------- * lclVar int V07 rat2 $243
New addressing mode node:
[000129] ------------ * lea(b+(i*8)+0) int
No addressing mode
No addressing mode
lowering GT_RETURN
N007 ( 6, 5) [000067] ---XG------- * return long $202
============lowering call (before):
N001 ( 14, 5) [000074] --CXG------- call help void HELPER.CORINFO_HELP_OVERFLOW
objp:
======
args:
======
late:
======
lowering call (after):
N001 ( 14, 5) [000074] --CXG------- call help void HELPER.CORINFO_HELP_OVERFLOW
lowering call (before):
N001 ( 14, 5) [000077] --CXG------- call help void HELPER.CORINFO_HELP_RNGCHKFAIL
objp:
======
args:
======
late:
======
lowering call (after):
N001 ( 14, 5) [000077] --CXG------- call help void HELPER.CORINFO_HELP_RNGCHKFAIL
Lower has completed modifying nodes, proceeding to initialize LSRA TreeNodeInfo structs...
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
( 17, 22) [000020] ------------ il_offset void IL offset: 0
N001 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 $100
[000081] ------------ t81 = lclVar int V06 rat1
N002 ( 3, 10) [000040] ------------ t40 = const int 1
[000083] ------------ t83 = const int 0
/--* t39 int
+--* t40 int
N003 ( 10, 16) [000038] ------------ t38 = * -Lo int
/--* t81 int
+--* t83 int
[000085] ------------ t85 = * -Hi int
/--* t38 int
N005 ( 17, 22) [000036] DA---------- * st.lclVar int V07 rat2
/--* t85 int
[000087] D----------- * st.lclVar int V08 rat3
N001 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 (last use) $c0
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
[000088] ------------ t88 = const int 0
N005 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 $100
[000090] ------------ t90 = lclVar int V06 rat1
/--* t53 int
+--* t51 int
N006 ( 12, 12) [000050] --------R--- t50 = * -Lo int
/--* t90 int
+--* t88 int
[000092] ------------ t92 = * -Hi int
/--* t50 int
+--* t92 int
[000093] ------------ t93 = * gt_long long
/--* t93 long
N007 ( 19, 20) [000049] ---X-------- t49 = * cast_ovfl int <- long $242
N008 ( 1, 1) [000055] ------------ t55 = const int 0 $40
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
[000094] ------------ t94 = const int 0
N012 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 $100
[000096] ------------ t96 = lclVar int V06 rat1
/--* t60 int
+--* t58 int
N013 ( 12, 12) [000057] --------R--- t57 = * -Lo int
/--* t96 int
+--* t94 int
[000098] ------------ t98 = * -Hi int
/--* t57 int
+--* t98 int
[000099] ------------ t99 = * gt_long long
/--* t99 long
N014 ( 19, 20) [000056] ---X-------- t56 = * cast_ovfl int <- long $242
[000115] ------------ t115 = const int 0
/--* t62 ref
+--* t49 int
[000116] ---X-------- t116 = * arrMDIdx[i, , ] int
[000117] ------------ t117 = lclVar ref V01 arg1 (last use)
/--* t115 int
+--* t116 int
+--* t117 ref
[000118] ---X-------- t118 = * arrMDOffs[i, , ] int
[000119] ------------ t119 = lclVar ref V01 arg1 (last use)
/--* t119 ref
+--* t55 int
[000120] ---X-------- t120 = * arrMDIdx[*,j, ] int
[000121] ------------ t121 = lclVar ref V01 arg1 (last use)
/--* t118 int
+--* t120 int
+--* t121 ref
[000122] ---X-------- t122 = * arrMDOffs[*,j, ] int
[000123] ------------ t123 = lclVar ref V01 arg1 (last use)
/--* t123 ref
+--* t56 int
[000124] ---X-------- t124 = * arrMDIdx[*,*,k] int
[000125] ------------ t125 = lclVar ref V01 arg1 (last use)
/--* t122 int
+--* t124 int
+--* t125 ref
[000126] ---X-------- t126 = * arrMDOffs[*,*,k] int
[000127] ------------ t127 = lclVar ref V01 arg1 (last use)
/--* t126 int
+--* t127 ref
[000128] ---X----R--- t128 = * lea(b+(i*8)+32) byref
/--* t128 byref
[000103] DA-X-------- * st.lclVar byref V09 rat4
[000104] ------------ t104 = lclVar byref V09 rat4
N017 ( 3, 2) [000064] ------------ t64 = lclVar int V07 rat2 $1c0
/--* t104 byref
+--* t64 int
[000080] -A-X-------- * storeIndir int
[000100] ------------ t100 = lclVar int V08 rat3
[000105] ------------ t105 = lclVar byref V09 rat4
/--* t105 byref
[000106] ------------ t106 = * lea(b+4) ref
/--* t100 int
+--* t106 ref
[000107] -A-X----R--- * storeIndir int
( 6, 5) [000035] ------------ il_offset void IL offset: 24
N001 ( 1, 1) [000070] ------------ t70 = lclVar int V00 arg0 u:2 (last use) $80
N002 ( 1, 1) [000072] C----------- t72 = lclVar int V07 rat2 $243
/--* t70 int
+--* t72 int
[000129] ------------ t129 = * lea(b+(i*8)+0) int
/--* t129 int
[000109] DA---------- * st.lclVar int V10 rat5
[000110] ------------ t110 = lclVar int V10 rat5
/--* t110 int
N006 ( 5, 4) [000068] ---XG------- t68 = * indir int $201
[000111] ------------ t111 = lclVar int V10 rat5
/--* t111 int
[000112] ------------ t112 = * lea(b+4) ref
/--* t112 ref
[000113] ---XG------- t113 = * indir int
/--* t68 int
+--* t113 int
[000114] ---XG------- t114 = * gt_long long
/--* t114 long
N007 ( 6, 5) [000067] ---XG------- * return long $202
------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14, 5) [000074] --CXG------- call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
N001 ( 14, 5) [000077] --CXG------- call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 int
; V01 arg1 ref
; V02 arg2 long
; V03 arg3 ubyte
; V04 loc0 long
; V05 rat0 int V02.lo(offs=0x00)
; V06 rat1 int V02.hi(offs=0x04)
; V07 rat2 int V04.lo(offs=0x00)
; V08 rat3 int V04.hi(offs=0x04)
; V09 rat4 byref
; V10 rat5 int
In fgLocalVarLivenessInit, sorting locals
refCnt table for 'test_25':
V09 rat4 [ byref]: refCnt = 3, refCntWtd = 6
V10 rat5 [ int]: refCnt = 3, refCntWtd = 6
V01 arg1 [ ref]: refCnt = 3, refCntWtd = 3 pref [edx]
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3 pref [ecx]
V07 rat2 [ int]: refCnt = 3, refCntWtd = 3
V03 arg3 [ ubyte]: refCnt = 2, refCntWtd = 2
V08 rat3 [ int]: refCnt = 2, refCntWtd = 2
V05 rat0 [ int]: refCnt = 3, refCntWtd = 3
V06 rat1 [ int]: refCnt = 3, refCntWtd = 3
V02 arg2 [ long]: refCnt = 6, refCntWtd = 0
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(3)={ V01 V00 V03 } + HEAP
DEF(4)={V09 V10 V07 V08}
BB02 USE(0)={}
DEF(0)={}
BB03 USE(0)={}
DEF(0)={}
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (3)={V01 V00 V03} + HEAP
OUT(0)={ }
BB02 IN (0)={}
OUT(0)={}
BB03 IN (0)={}
OUT(0)={}
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Liveness pass finished after lowering, IR:
lvasortagain = 0
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
( 17, 22) [000020] ------------ il_offset void IL offset: 0
N001 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 $100
[000081] ------------ t81 = lclVar int V06 rat1
N002 ( 3, 10) [000040] ------------ t40 = const int 1
[000083] ------------ t83 = const int 0
/--* t39 int
+--* t40 int
N003 ( 10, 16) [000038] ------------ t38 = * -Lo int
/--* t81 int
+--* t83 int
[000085] ------------ t85 = * -Hi int
/--* t38 int
N005 ( 17, 22) [000036] DA---------- * st.lclVar int V07 rat2
/--* t85 int
[000087] D----------- * st.lclVar int V08 rat3
N001 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 $c0
N002 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 $140
/--* t54 int
N003 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int $240
[000088] ------------ t88 = const int 0
N005 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 $100
[000090] ------------ t90 = lclVar int V06 rat1
/--* t53 int
+--* t51 int
N006 ( 12, 12) [000050] --------R--- t50 = * -Lo int
/--* t90 int
+--* t88 int
[000092] ------------ t92 = * -Hi int
/--* t50 int
+--* t92 int
[000093] ------------ t93 = * gt_long long
/--* t93 long
N007 ( 19, 20) [000049] ---X-------- t49 = * cast_ovfl int <- long $242
N008 ( 1, 1) [000055] ------------ t55 = const int 0 $40
N009 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) $140
/--* t61 int
N010 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int $240
[000094] ------------ t94 = const int 0
N012 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 $100
[000096] ------------ t96 = lclVar int V06 rat1
/--* t60 int
+--* t58 int
N013 ( 12, 12) [000057] --------R--- t57 = * -Lo int
/--* t96 int
+--* t94 int
[000098] ------------ t98 = * -Hi int
/--* t57 int
+--* t98 int
[000099] ------------ t99 = * gt_long long
/--* t99 long
N014 ( 19, 20) [000056] ---X-------- t56 = * cast_ovfl int <- long $242
[000115] ------------ t115 = const int 0
/--* t62 ref
+--* t49 int
[000116] ---X-------- t116 = * arrMDIdx[i, , ] int
[000117] ------------ t117 = lclVar ref V01 arg1
/--* t115 int
+--* t116 int
+--* t117 ref
[000118] ---X-------- t118 = * arrMDOffs[i, , ] int
[000119] ------------ t119 = lclVar ref V01 arg1
/--* t119 ref
+--* t55 int
[000120] ---X-------- t120 = * arrMDIdx[*,j, ] int
[000121] ------------ t121 = lclVar ref V01 arg1
/--* t118 int
+--* t120 int
+--* t121 ref
[000122] ---X-------- t122 = * arrMDOffs[*,j, ] int
[000123] ------------ t123 = lclVar ref V01 arg1
/--* t123 ref
+--* t56 int
[000124] ---X-------- t124 = * arrMDIdx[*,*,k] int
[000125] ------------ t125 = lclVar ref V01 arg1
/--* t122 int
+--* t124 int
+--* t125 ref
[000126] ---X-------- t126 = * arrMDOffs[*,*,k] int
[000127] ------------ t127 = lclVar ref V01 arg1 (last use)
/--* t126 int
+--* t127 ref
[000128] ---X----R--- t128 = * lea(b+(i*8)+32) byref
/--* t128 byref
[000103] DA-X-------- * st.lclVar byref V09 rat4
[000104] ------------ t104 = lclVar byref V09 rat4
N017 ( 3, 2) [000064] ------------ t64 = lclVar int V07 rat2 $1c0
/--* t104 byref
+--* t64 int
[000080] -A-X-------- * storeIndir int
[000100] ------------ t100 = lclVar int V08 rat3 (last use)
[000105] ------------ t105 = lclVar byref V09 rat4 (last use)
/--* t105 byref
[000106] ------------ t106 = * lea(b+4) ref
/--* t100 int
+--* t106 ref
[000107] -A-X----R--- * storeIndir int
( 6, 5) [000035] ------------ il_offset void IL offset: 24
N001 ( 1, 1) [000070] ------------ t70 = lclVar int V00 arg0 u:2 (last use) $80
N002 ( 1, 1) [000072] C----------- t72 = lclVar int V07 rat2 (last use) $243
/--* t70 int
+--* t72 int
[000129] ------------ t129 = * lea(b+(i*8)+0) int
/--* t129 int
[000109] DA---------- * st.lclVar int V10 rat5
[000110] ------------ t110 = lclVar int V10 rat5
/--* t110 int
N006 ( 5, 4) [000068] ---XG------- t68 = * indir int $201
[000111] ------------ t111 = lclVar int V10 rat5 (last use)
/--* t111 int
[000112] ------------ t112 = * lea(b+4) ref
/--* t112 ref
[000113] ---XG------- t113 = * indir int
/--* t68 int
+--* t113 int
[000114] ---XG------- t114 = * gt_long long
/--* t114 long
N007 ( 6, 5) [000067] ---XG------- * return long $202
------------ BB02 [???..???) (throw), preds={} succs={}
N001 ( 14, 5) [000074] --CXG------- call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
N001 ( 14, 5) [000077] --CXG------- call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
LSRA Block Sequence: BB01( 1 ) BB02( 0 ) BB03( 0 )
Lower of StoreInd didn't mark the node as self contained for reason: 4
N091 (???,???) [000104] ------------ t104 = lclVar byref V09 rat4 REG NA
N093 ( 3, 2) [000064] ------------ t64 = lclVar int V07 rat2 REG NA $1c0
/--* t104 byref
+--* t64 int
N095 (???,???) [000080] -A-X-------- * storeIndir int REG NA
Lower of StoreInd didn't mark the node as self contained for reason: 4
N097 (???,???) [000100] ------------ t100 = lclVar int V08 rat3 (last use) REG NA
N099 (???,???) [000105] ------------ t105 = lclVar byref V09 rat4 (last use) REG NA
/--* t105 byref
N101 (???,???) [000106] ------------ t106 = * lea(b+4) ref REG NA
/--* t100 int
+--* t106 ref
N103 (???,???) [000107] -A-X----R--- * storeIndir int REG NA
-----------------------------
TREE NODE INFO DUMP
-----------------------------
N003 ( 17, 22) [000020] ------------ * il_offset void IL offset: 0 REG NA
+<TreeNodeInfo @ 3 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N005 ( 3, 2) [000039] ------------ * lclVar int V05 rat0 REG NA $100
+<TreeNodeInfo @ 5 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I P>
N007 (???,???) [000081] ------------ * lclVar int V06 rat1 REG NA
+<TreeNodeInfo @ 7 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I P>
N009 ( 3, 10) [000040] ------------ * const int 1 REG NA
+<TreeNodeInfo @ 9 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>
N011 (???,???) [000083] ------------ * const int 0 REG NA
+<TreeNodeInfo @ 11 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>
N013 ( 10, 16) [000038] ------------ * -Lo int REG NA
+<TreeNodeInfo @ 13 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N015 (???,???) [000085] ------------ * -Hi int REG NA
+<TreeNodeInfo @ 15 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N017 ( 17, 22) [000036] DA---------- * st.lclVar int V07 rat2 REG NA
+<TreeNodeInfo @ 17 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N019 (???,???) [000087] D----------- * st.lclVar int V08 rat3 REG NA
+<TreeNodeInfo @ 19 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N021 ( 1, 1) [000062] ------------ * lclVar ref V01 arg1 u:2 REG NA $c0
+<TreeNodeInfo @ 21 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>
N023 ( 3, 2) [000054] ------------ * lclVar int V03 arg3 u:2 REG NA $140
+<TreeNodeInfo @ 23 1=0 0i 0f src=[eax ecx edx ebx] int=[allInt] dst=[allInt] I>
N025 ( 4, 4) [000053] ------------ * cast int <- ubyte <- int REG NA $240
+<TreeNodeInfo @ 25 1=1 0i 0f src=[allInt] int=[allInt] dst=[eax ecx edx ebx] I D>
N027 (???,???) [000088] ------------ * const int 0 REG NA
+<TreeNodeInfo @ 27 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>
N029 ( 3, 2) [000051] ------------ * lclVar int V05 rat0 REG NA $100
+<TreeNodeInfo @ 29 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I P>
N031 (???,???) [000090] ------------ * lclVar int V06 rat1 REG NA
+<TreeNodeInfo @ 31 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I P>
N033 ( 12, 12) [000050] --------R--- * -Lo int REG NA
+<TreeNodeInfo @ 33 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N035 (???,???) [000092] ------------ * -Hi int REG NA
+<TreeNodeInfo @ 35 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N037 (???,???) [000093] ------------ * gt_long long REG NA
+<TreeNodeInfo @ 37 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N039 ( 19, 20) [000049] ---X-------- * cast_ovfl int <- long REG NA $242
+<TreeNodeInfo @ 39 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N041 ( 1, 1) [000055] ------------ * const int 0 REG NA $40
+<TreeNodeInfo @ 41 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N043 ( 3, 2) [000061] ------------ * lclVar int V03 arg3 u:2 (last use) REG NA $140
+<TreeNodeInfo @ 43 1=0 0i 0f src=[eax ecx edx ebx] int=[allInt] dst=[allInt] I>
N045 ( 4, 4) [000060] ------------ * cast int <- ubyte <- int REG NA $240
+<TreeNodeInfo @ 45 1=1 0i 0f src=[allInt] int=[allInt] dst=[eax ecx edx ebx] I D>
N047 (???,???) [000094] ------------ * const int 0 REG NA
+<TreeNodeInfo @ 47 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>
N049 ( 3, 2) [000058] ------------ * lclVar int V05 rat0 REG NA $100
+<TreeNodeInfo @ 49 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I P>
N051 (???,???) [000096] ------------ * lclVar int V06 rat1 REG NA
+<TreeNodeInfo @ 51 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I P>
N053 ( 12, 12) [000057] --------R--- * -Lo int REG NA
+<TreeNodeInfo @ 53 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N055 (???,???) [000098] ------------ * -Hi int REG NA
+<TreeNodeInfo @ 55 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N057 (???,???) [000099] ------------ * gt_long long REG NA
+<TreeNodeInfo @ 57 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N059 ( 19, 20) [000056] ---X-------- * cast_ovfl int <- long REG NA $242
+<TreeNodeInfo @ 59 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N061 (???,???) [000115] ------------ * const int 0 REG NA
+<TreeNodeInfo @ 61 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N063 (???,???) [000116] ---X-------- * arrMDIdx[i, , ] int REG NA
+<TreeNodeInfo @ 63 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N065 (???,???) [000117] ------------ * lclVar ref V01 arg1 REG NA
+<TreeNodeInfo @ 65 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N067 (???,???) [000118] ---X-------- * arrMDOffs[i, , ] int
+<TreeNodeInfo @ 67 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N069 (???,???) [000119] ------------ * lclVar ref V01 arg1 REG NA
+<TreeNodeInfo @ 69 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>
N071 (???,???) [000120] ---X-------- * arrMDIdx[*,j, ] int REG NA
+<TreeNodeInfo @ 71 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N073 (???,???) [000121] ------------ * lclVar ref V01 arg1 REG NA
+<TreeNodeInfo @ 73 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N075 (???,???) [000122] ---X-------- * arrMDOffs[*,j, ] int
+<TreeNodeInfo @ 75 1=3 1i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N077 (???,???) [000123] ------------ * lclVar ref V01 arg1 REG NA
+<TreeNodeInfo @ 77 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>
N079 (???,???) [000124] ---X-------- * arrMDIdx[*,*,k] int REG NA
+<TreeNodeInfo @ 79 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N081 (???,???) [000125] ------------ * lclVar ref V01 arg1 REG NA
+<TreeNodeInfo @ 81 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N083 (???,???) [000126] ---X-------- * arrMDOffs[*,*,k] int
+<TreeNodeInfo @ 83 1=3 1i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N085 (???,???) [000127] ------------ * lclVar ref V01 arg1 (last use) REG NA
+<TreeNodeInfo @ 85 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N087 (???,???) [000128] ---X----R--- * lea(b+(i*8)+32) byref REG NA
+<TreeNodeInfo @ 87 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N089 (???,???) [000103] DA-X-------- * st.lclVar byref V09 rat4 REG NA
+<TreeNodeInfo @ 89 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N091 (???,???) [000104] ------------ * lclVar byref V09 rat4 REG NA
+<TreeNodeInfo @ 91 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N093 ( 3, 2) [000064] ------------ * lclVar int V07 rat2 REG NA $1c0
+<TreeNodeInfo @ 93 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N095 (???,???) [000080] -A-X-------- * storeIndir int REG NA
+<TreeNodeInfo @ 95 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N097 (???,???) [000100] ------------ * lclVar int V08 rat3 (last use) REG NA
+<TreeNodeInfo @ 97 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N099 (???,???) [000105] ------------ * lclVar byref V09 rat4 (last use) REG NA
+<TreeNodeInfo @ 99 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N101 (???,???) [000106] ------------ * lea(b+4) ref REG NA
+<TreeNodeInfo @ 101 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N103 (???,???) [000107] -A-X----R--- * storeIndir int REG NA
+<TreeNodeInfo @ 103 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N105 ( 6, 5) [000035] ------------ * il_offset void IL offset: 24 REG NA
+<TreeNodeInfo @ 105 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N107 ( 1, 1) [000070] ------------ * lclVar int V00 arg0 u:2 (last use) REG NA $80
+<TreeNodeInfo @ 107 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N109 ( 1, 1) [000072] C----------- * lclVar int V07 rat2 (last use) REG NA $243
+<TreeNodeInfo @ 109 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N111 (???,???) [000129] ------------ * lea(b+(i*8)+0) int REG NA
+<TreeNodeInfo @ 111 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N113 (???,???) [000109] DA---------- * st.lclVar int V10 rat5 REG NA
+<TreeNodeInfo @ 113 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N115 (???,???) [000110] ------------ * lclVar int V10 rat5 REG NA
+<TreeNodeInfo @ 115 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N117 ( 5, 4) [000068] ---XG------- * indir int REG NA $201
+<TreeNodeInfo @ 117 1=1 0i 0f src=[eax] int=[allInt] dst=[allInt] I>
N119 (???,???) [000111] ------------ * lclVar int V10 rat5 (last use) REG NA
+<TreeNodeInfo @ 119 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N121 (???,???) [000112] ------------ * lea(b+4) ref REG NA
+<TreeNodeInfo @ 121 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N123 (???,???) [000113] ---XG------- * indir int REG NA
+<TreeNodeInfo @ 123 1=1 0i 0f src=[edx] int=[allInt] dst=[allInt] I>
N125 (???,???) [000114] ---XG------- * gt_long long REG NA
+<TreeNodeInfo @ 125 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N127 ( 6, 5) [000067] ---XG------- * return long REG NA $202
+<TreeNodeInfo @ 127 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>
N131 ( 14, 5) [000074] --CXG------- * call help void HELPER.CORINFO_HELP_OVERFLOW
+<TreeNodeInfo @ 131 0=0 0i 0f src=[allInt] int=[allInt] dst=[eax] I>
N135 ( 14, 5) [000077] --CXG------- * call help void HELPER.CORINFO_HELP_RNGCHKFAIL
+<TreeNodeInfo @ 135 0=0 0i 0f src=[allInt] int=[allInt] dst=[eax] I>
*************** Exiting Lowering
Trees after Lowering
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
N003 ( 17, 22) [000020] ------------ il_offset void IL offset: 0 REG NA
N005 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 REG NA $100
N007 (???,???) [000081] ------------ t81 = lclVar int V06 rat1 REG NA
N009 ( 3, 10) [000040] ------------ t40 = const int 1 REG NA
N011 (???,???) [000083] ------------ t83 = const int 0 REG NA
/--* t39 int
+--* t40 int
N013 ( 10, 16) [000038] ------------ t38 = * -Lo int REG NA
/--* t81 int
+--* t83 int
N015 (???,???) [000085] ------------ t85 = * -Hi int REG NA
/--* t38 int
N017 ( 17, 22) [000036] DA---------- * st.lclVar int V07 rat2 REG NA
/--* t85 int
N019 (???,???) [000087] D----------- * st.lclVar int V08 rat3 REG NA
N021 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 REG NA $c0
N023 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 REG NA $140
/--* t54 int
N025 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int REG NA $240
N027 (???,???) [000088] ------------ t88 = const int 0 REG NA
N029 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 REG NA $100
N031 (???,???) [000090] ------------ t90 = lclVar int V06 rat1 REG NA
/--* t53 int
+--* t51 int
N033 ( 12, 12) [000050] --------R--- t50 = * -Lo int REG NA
/--* t90 int
+--* t88 int
N035 (???,???) [000092] ------------ t92 = * -Hi int REG NA
/--* t50 int
+--* t92 int
N037 (???,???) [000093] ------------ t93 = * gt_long long REG NA
/--* t93 long
N039 ( 19, 20) [000049] ---X-------- t49 = * cast_ovfl int <- long REG NA $242
N041 ( 1, 1) [000055] ------------ t55 = const int 0 REG NA $40
N043 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) REG NA $140
/--* t61 int
N045 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int REG NA $240
N047 (???,???) [000094] ------------ t94 = const int 0 REG NA
N049 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 REG NA $100
N051 (???,???) [000096] ------------ t96 = lclVar int V06 rat1 REG NA
/--* t60 int
+--* t58 int
N053 ( 12, 12) [000057] --------R--- t57 = * -Lo int REG NA
/--* t96 int
+--* t94 int
N055 (???,???) [000098] ------------ t98 = * -Hi int REG NA
/--* t57 int
+--* t98 int
N057 (???,???) [000099] ------------ t99 = * gt_long long REG NA
/--* t99 long
N059 ( 19, 20) [000056] ---X-------- t56 = * cast_ovfl int <- long REG NA $242
N061 (???,???) [000115] ------------ t115 = const int 0 REG NA
/--* t62 ref
+--* t49 int
N063 (???,???) [000116] ---X-------- t116 = * arrMDIdx[i, , ] int REG NA
N065 (???,???) [000117] ------------ t117 = lclVar ref V01 arg1 REG NA
/--* t115 int
+--* t116 int
+--* t117 ref
N067 (???,???) [000118] ---X-------- t118 = * arrMDOffs[i, , ] int
N069 (???,???) [000119] ------------ t119 = lclVar ref V01 arg1 REG NA
/--* t119 ref
+--* t55 int
N071 (???,???) [000120] ---X-------- t120 = * arrMDIdx[*,j, ] int REG NA
N073 (???,???) [000121] ------------ t121 = lclVar ref V01 arg1 REG NA
/--* t118 int
+--* t120 int
+--* t121 ref
N075 (???,???) [000122] ---X-------- t122 = * arrMDOffs[*,j, ] int
N077 (???,???) [000123] ------------ t123 = lclVar ref V01 arg1 REG NA
/--* t123 ref
+--* t56 int
N079 (???,???) [000124] ---X-------- t124 = * arrMDIdx[*,*,k] int REG NA
N081 (???,???) [000125] ------------ t125 = lclVar ref V01 arg1 REG NA
/--* t122 int
+--* t124 int
+--* t125 ref
N083 (???,???) [000126] ---X-------- t126 = * arrMDOffs[*,*,k] int
N085 (???,???) [000127] ------------ t127 = lclVar ref V01 arg1 (last use) REG NA
/--* t126 int
+--* t127 ref
N087 (???,???) [000128] ---X----R--- t128 = * lea(b+(i*8)+32) byref REG NA
/--* t128 byref
N089 (???,???) [000103] DA-X-------- * st.lclVar byref V09 rat4 REG NA
N091 (???,???) [000104] ------------ t104 = lclVar byref V09 rat4 REG NA
N093 ( 3, 2) [000064] ------------ t64 = lclVar int V07 rat2 REG NA $1c0
/--* t104 byref
+--* t64 int
N095 (???,???) [000080] -A-X-------- * storeIndir int REG NA
N097 (???,???) [000100] ------------ t100 = lclVar int V08 rat3 (last use) REG NA
N099 (???,???) [000105] ------------ t105 = lclVar byref V09 rat4 (last use) REG NA
/--* t105 byref
N101 (???,???) [000106] ------------ t106 = * lea(b+4) ref REG NA
/--* t100 int
+--* t106 ref
N103 (???,???) [000107] -A-X----R--- * storeIndir int REG NA
N105 ( 6, 5) [000035] ------------ il_offset void IL offset: 24 REG NA
N107 ( 1, 1) [000070] ------------ t70 = lclVar int V00 arg0 u:2 (last use) REG NA $80
N109 ( 1, 1) [000072] C----------- t72 = lclVar int V07 rat2 (last use) REG NA $243
/--* t70 int
+--* t72 int
N111 (???,???) [000129] ------------ t129 = * lea(b+(i*8)+0) int REG NA
/--* t129 int
N113 (???,???) [000109] DA---------- * st.lclVar int V10 rat5 REG NA
N115 (???,???) [000110] ------------ t110 = lclVar int V10 rat5 REG NA
/--* t110 int
N117 ( 5, 4) [000068] ---XG------- t68 = * indir int REG NA $201
N119 (???,???) [000111] ------------ t111 = lclVar int V10 rat5 (last use) REG NA
/--* t111 int
N121 (???,???) [000112] ------------ t112 = * lea(b+4) ref REG NA
/--* t112 ref
N123 (???,???) [000113] ---XG------- t113 = * indir int REG NA
/--* t68 int
+--* t113 int
N125 (???,???) [000114] ---XG------- t114 = * gt_long long REG NA
/--* t114 long
N127 ( 6, 5) [000067] ---XG------- * return long REG NA $202
------------ BB02 [???..???) (throw), preds={} succs={}
N131 ( 14, 5) [000074] --CXG------- call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
N135 ( 14, 5) [000077] --CXG------- call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In doLinearScan
Trees before linear scan register allocator (LSRA)
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
N003 ( 17, 22) [000020] ------------ il_offset void IL offset: 0 REG NA
N005 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 REG NA $100
N007 (???,???) [000081] ------------ t81 = lclVar int V06 rat1 REG NA
N009 ( 3, 10) [000040] ------------ t40 = const int 1 REG NA
N011 (???,???) [000083] ------------ t83 = const int 0 REG NA
/--* t39 int
+--* t40 int
N013 ( 10, 16) [000038] ------------ t38 = * -Lo int REG NA
/--* t81 int
+--* t83 int
N015 (???,???) [000085] ------------ t85 = * -Hi int REG NA
/--* t38 int
N017 ( 17, 22) [000036] DA---------- * st.lclVar int V07 rat2 REG NA
/--* t85 int
N019 (???,???) [000087] D----------- * st.lclVar int V08 rat3 REG NA
N021 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 REG NA $c0
N023 ( 3, 2) [000054] ------------ t54 = lclVar int V03 arg3 u:2 REG NA $140
/--* t54 int
N025 ( 4, 4) [000053] ------------ t53 = * cast int <- ubyte <- int REG NA $240
N027 (???,???) [000088] ------------ t88 = const int 0 REG NA
N029 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 REG NA $100
N031 (???,???) [000090] ------------ t90 = lclVar int V06 rat1 REG NA
/--* t53 int
+--* t51 int
N033 ( 12, 12) [000050] --------R--- t50 = * -Lo int REG NA
/--* t90 int
+--* t88 int
N035 (???,???) [000092] ------------ t92 = * -Hi int REG NA
/--* t50 int
+--* t92 int
N037 (???,???) [000093] ------------ t93 = * gt_long long REG NA
/--* t93 long
N039 ( 19, 20) [000049] ---X-------- t49 = * cast_ovfl int <- long REG NA $242
N041 ( 1, 1) [000055] ------------ t55 = const int 0 REG NA $40
N043 ( 3, 2) [000061] ------------ t61 = lclVar int V03 arg3 u:2 (last use) REG NA $140
/--* t61 int
N045 ( 4, 4) [000060] ------------ t60 = * cast int <- ubyte <- int REG NA $240
N047 (???,???) [000094] ------------ t94 = const int 0 REG NA
N049 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 REG NA $100
N051 (???,???) [000096] ------------ t96 = lclVar int V06 rat1 REG NA
/--* t60 int
+--* t58 int
N053 ( 12, 12) [000057] --------R--- t57 = * -Lo int REG NA
/--* t96 int
+--* t94 int
N055 (???,???) [000098] ------------ t98 = * -Hi int REG NA
/--* t57 int
+--* t98 int
N057 (???,???) [000099] ------------ t99 = * gt_long long REG NA
/--* t99 long
N059 ( 19, 20) [000056] ---X-------- t56 = * cast_ovfl int <- long REG NA $242
N061 (???,???) [000115] ------------ t115 = const int 0 REG NA
/--* t62 ref
+--* t49 int
N063 (???,???) [000116] ---X-------- t116 = * arrMDIdx[i, , ] int REG NA
N065 (???,???) [000117] ------------ t117 = lclVar ref V01 arg1 REG NA
/--* t115 int
+--* t116 int
+--* t117 ref
N067 (???,???) [000118] ---X-------- t118 = * arrMDOffs[i, , ] int
N069 (???,???) [000119] ------------ t119 = lclVar ref V01 arg1 REG NA
/--* t119 ref
+--* t55 int
N071 (???,???) [000120] ---X-------- t120 = * arrMDIdx[*,j, ] int REG NA
N073 (???,???) [000121] ------------ t121 = lclVar ref V01 arg1 REG NA
/--* t118 int
+--* t120 int
+--* t121 ref
N075 (???,???) [000122] ---X-------- t122 = * arrMDOffs[*,j, ] int
N077 (???,???) [000123] ------------ t123 = lclVar ref V01 arg1 REG NA
/--* t123 ref
+--* t56 int
N079 (???,???) [000124] ---X-------- t124 = * arrMDIdx[*,*,k] int REG NA
N081 (???,???) [000125] ------------ t125 = lclVar ref V01 arg1 REG NA
/--* t122 int
+--* t124 int
+--* t125 ref
N083 (???,???) [000126] ---X-------- t126 = * arrMDOffs[*,*,k] int
N085 (???,???) [000127] ------------ t127 = lclVar ref V01 arg1 (last use) REG NA
/--* t126 int
+--* t127 ref
N087 (???,???) [000128] ---X----R--- t128 = * lea(b+(i*8)+32) byref REG NA
/--* t128 byref
N089 (???,???) [000103] DA-X-------- * st.lclVar byref V09 rat4 REG NA
N091 (???,???) [000104] ------------ t104 = lclVar byref V09 rat4 REG NA
N093 ( 3, 2) [000064] ------------ t64 = lclVar int V07 rat2 REG NA $1c0
/--* t104 byref
+--* t64 int
N095 (???,???) [000080] -A-X-------- * storeIndir int REG NA
N097 (???,???) [000100] ------------ t100 = lclVar int V08 rat3 (last use) REG NA
N099 (???,???) [000105] ------------ t105 = lclVar byref V09 rat4 (last use) REG NA
/--* t105 byref
N101 (???,???) [000106] ------------ t106 = * lea(b+4) ref REG NA
/--* t100 int
+--* t106 ref
N103 (???,???) [000107] -A-X----R--- * storeIndir int REG NA
N105 ( 6, 5) [000035] ------------ il_offset void IL offset: 24 REG NA
N107 ( 1, 1) [000070] ------------ t70 = lclVar int V00 arg0 u:2 (last use) REG NA $80
N109 ( 1, 1) [000072] C----------- t72 = lclVar int V07 rat2 (last use) REG NA $243
/--* t70 int
+--* t72 int
N111 (???,???) [000129] ------------ t129 = * lea(b+(i*8)+0) int REG NA
/--* t129 int
N113 (???,???) [000109] DA---------- * st.lclVar int V10 rat5 REG NA
N115 (???,???) [000110] ------------ t110 = lclVar int V10 rat5 REG NA
/--* t110 int
N117 ( 5, 4) [000068] ---XG------- t68 = * indir int REG NA $201
N119 (???,???) [000111] ------------ t111 = lclVar int V10 rat5 (last use) REG NA
/--* t111 int
N121 (???,???) [000112] ------------ t112 = * lea(b+4) ref REG NA
/--* t112 ref
N123 (???,???) [000113] ---XG------- t113 = * indir int REG NA
/--* t68 int
+--* t113 int
N125 (???,???) [000114] ---XG------- t114 = * gt_long long REG NA
/--* t114 long
N127 ( 6, 5) [000067] ---XG------- * return long REG NA $202
------------ BB02 [???..???) (throw), preds={} succs={}
N131 ( 14, 5) [000074] --CXG------- call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
N135 ( 14, 5) [000077] --CXG------- call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{V00 V01 V03}
{V07 V08 V09 V10}
{V00 V01 V03}
{}
BB02 use def in out
{}
{}
{}
{}
BB03 use def in out
{}
{}
{}
{}
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
Interval 7: RefPositions {} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {} physReg:NA Preferences=[allInt]
Interval 9: RefPositions {} physReg:NA Preferences=[allInt]
Interval 10: RefPositions {} physReg:NA Preferences=[allInt]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
BB01 [000..02A) (return), preds={} succs={}
=====
N003. il_offset IL offset: 0 REG NA
N005. t5 = V05 MEM
N007. t7 = V06 MEM
N009. const 1 REG NA
N011. const 0 REG NA
N013. t13 = -Lo ; t5
N015. t15 = -Hi ; t7
N017. V07(t17); t13
N019. V08(t19); t15
N021. V01(t21)
N023. V03(t23)
N025. t25 = cast ; t23
N027. const 0 REG NA
N029. t29 = V05 MEM
N031. t31 = V06 MEM
N033. t33 = -Lo (Rev); t25,t29
N035. t35 = -Hi ; t31
N037. gt_long
N039. t39 = cast_ovfl; t33,t35
N041. t41 = const 0 REG NA
N043. V03(t43*)
N045. t45 = cast ; t43*
N047. const 0 REG NA
N049. t49* = V05 MEM
N051. t51 = V06 MEM
N053. t53 = -Lo (Rev); t45,t49*
N055. t55 = -Hi ; t51
N057. gt_long
N059. t59 = cast_ovfl; t53,t55
N061. const 0 REG NA
N063. t63 = arrMDIdx[i, , ]; t21,t39
N065. V01(t65)
N067. t67 = arrMDOffs[i, , ]; t63,t65
N069. V01(t69)
N071. t71 = arrMDIdx[*,j, ]; t69,t41
N073. V01(t73)
N075. t75 = arrMDOffs[*,j, ]; t67,t71,t73
internal (1):
N077. V01(t77)
N079. t79 = arrMDIdx[*,*,k]; t77,t59
N081. V01(t81)
N083. t83 = arrMDOffs[*,*,k]; t75,t79,t81
internal (1):
N085. V01(t85*)
N087. t87 = lea(b+(i*8)+32)(Rev); t83,t85*
N089. V09(t89); t87
N091. V09(t91)
N093. V07(t93)
N095. storeIndir; t91,t93
N097. V08(t97*)
N099. V09(t99*)
N101. lea(b+4)
N103. storeIndir(Rev); t97*,t99*
N105. il_offset IL offset: 24 REG NA
N107. V00(t107*)
N109. V07(t109*)
N111. t111 = lea(b+(i*8)+0); t107*,t109*
N113. V10(t113); t111
N115. V10(t115)
N117. t117 = indir ; t115
N119. V10(t119*)
N121. lea(b+4)
N123. t123 = indir ; t119*
N125. gt_long
N127. return ; t117,t123
BB02 [???..???) (throw), preds={} succs={}
=====
N131. call help
BB03 [???..???) (throw), preds={} succs={}
=====
N135. call help
buildIntervals second part ========
Int arg V01 in reg edx
<RefPosition #0 @0 RefTypeParamDef <Ivl:1 V01> BB03 regmask=[edx] fixed>
Int arg V00 in reg ecx
<RefPosition #1 @0 RefTypeParamDef <Ivl:0 V00> BB03 regmask=[ecx] fixed>
<RefPosition #2 @0 RefTypeParamDef <Ivl:3 V03> BB03 regmask=[ebx esi edi]>
NEW BLOCK BB01
<RefPosition #3 @0 RefTypeBB BB01 regmask=[]>
at start of tree, map contains: { }
N003. il_offset IL offset: 0 REG NA
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { }
N005. t5 = V05 MEM
consume=0 produce=1
t5 = op
Def candidates [allInt], Use candidates [allInt]
Interval 11: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #4 @6 RefTypeDef <Ivl:11> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #4 @6 RefTypeDef <Ivl:11> LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N005. lclVar -> (6.N005) }
N007. t7 = V06 MEM
consume=0 produce=1
t7 = op
Def candidates [allInt], Use candidates [allInt]
Interval 12: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #5 @8 RefTypeDef <Ivl:12> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #5 @8 RefTypeDef <Ivl:12> LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N007. lclVar -> (8.N007); N005. lclVar -> (6.N005) }
N009. const 1 REG NA
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N007. lclVar -> (8.N007); N005. lclVar -> (6.N005) }
N011. const 0 REG NA
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N007. lclVar -> (8.N007); N005. lclVar -> (6.N005) }
N013. t13 = -Lo
consume=1 produce=1
t13 = op
t6 <RefPosition #6 @13 RefTypeUse <Ivl:11> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 13: RefPositions {} physReg:NA Preferences=[allInt]
Assigning related <I11> to <I13>
<RefPosition #7 @14 RefTypeDef <Ivl:13> SUB_LO BB01 regmask=[ebx esi edi]>
<RefPosition #7 @14 RefTypeDef <Ivl:13> SUB_LO BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N007. lclVar -> (8.N007); N013. -Lo -> (14.N013) }
N015. t15 = -Hi
consume=1 produce=1
t15 = op
t8 <RefPosition #8 @15 RefTypeUse <Ivl:12> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 14: RefPositions {} physReg:NA Preferences=[allInt]
Assigning related <I12> to <I14>
<RefPosition #9 @16 RefTypeDef <Ivl:14> SUB_HI BB01 regmask=[ebx esi edi]>
<RefPosition #9 @16 RefTypeDef <Ivl:14> SUB_HI BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N015. -Hi -> (16.N015); N013. -Lo -> (14.N013) }
N017. V07(L7)
consume=1 produce=0
Assigning related <L7> to <I13>
t17 (i:7) = op
t14 <RefPosition #10 @17 RefTypeUse <Ivl:13> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
<RefPosition #11 @18 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #11 @18 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N015. -Hi -> (16.N015) }
N019. V08(L8)
consume=1 produce=0
Assigning related <L8> to <I14>
t19 (i:8) = op
t16 <RefPosition #12 @19 RefTypeUse <Ivl:14> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
<RefPosition #13 @20 RefTypeDef <Ivl:8 V08> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #13 @20 RefTypeDef <Ivl:8 V08> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { }
t21 (i:1)
at start of tree, map contains: { N021. lclVar -> (21.N021) }
t23 (i:3)
at start of tree, map contains: { N023. lclVar -> (23.N023); N021. lclVar -> (21.N021) }
N025. t25 = cast
consume=1 produce=1
t25 = op
t23 <RefPosition #14 @25 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx]>
Def candidates [eax ecx edx ebx], Use candidates [allInt]
Interval 15: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #15 @26 RefTypeDef <Ivl:15> CAST BB01 regmask=[eax ecx edx ebx]>
<RefPosition #15 @26 RefTypeDef <Ivl:15> CAST BB01 regmask=[eax ecx edx ebx]>
at start of tree, map contains: { N025. cast -> (26.N025); N021. lclVar -> (21.N021) }
N027. const 0 REG NA
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N025. cast -> (26.N025); N021. lclVar -> (21.N021) }
N029. t29 = V05 MEM
consume=0 produce=1
t29 = op
Def candidates [allInt], Use candidates [allInt]
Interval 16: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #16 @30 RefTypeDef <Ivl:16> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #16 @30 RefTypeDef <Ivl:16> LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N025. cast -> (26.N025); N029. lclVar -> (30.N029); N021. lclVar -> (21.N021) }
N031. t31 = V06 MEM
consume=0 produce=1
t31 = op
Def candidates [allInt], Use candidates [allInt]
Interval 17: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #17 @32 RefTypeDef <Ivl:17> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #17 @32 RefTypeDef <Ivl:17> LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N025. cast -> (26.N025); N031. lclVar -> (32.N031); N029. lclVar -> (30.N029); N021. lclVar -> (21.N021) }
N033. t33 = -Lo (Rev)
consume=2 produce=1
t33 = op
t26 <RefPosition #18 @33 RefTypeUse <Ivl:15> BB01 regmask=[ebx esi edi]>
t30 <RefPosition #19 @33 RefTypeUse <Ivl:16> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 18: RefPositions {} physReg:NA Preferences=[allInt]
Assigning related <I16> to <I18>
<RefPosition #20 @34 RefTypeDef <Ivl:18> SUB_LO BB01 regmask=[ebx esi edi]>
<RefPosition #20 @34 RefTypeDef <Ivl:18> SUB_LO BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N031. lclVar -> (32.N031); N021. lclVar -> (21.N021); N033. -Lo -> (34.N033) }
N035. t35 = -Hi
consume=1 produce=1
t35 = op
t32 <RefPosition #21 @35 RefTypeUse <Ivl:17> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 19: RefPositions {} physReg:NA Preferences=[allInt]
Assigning related <I17> to <I19>
<RefPosition #22 @36 RefTypeDef <Ivl:19> SUB_HI BB01 regmask=[ebx esi edi]>
<RefPosition #22 @36 RefTypeDef <Ivl:19> SUB_HI BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N035. -Hi -> (36.N035); N021. lclVar -> (21.N021); N033. -Lo -> (34.N033) }
N037. gt_long
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N037. gt_long -> (34.N033, 36.N035); N021. lclVar -> (21.N021) }
N039. t39 = cast_ovfl
consume=2 produce=1
t39 = op
t34 <RefPosition #23 @39 RefTypeUse <Ivl:18> BB01 regmask=[ebx esi edi]>
t36 <RefPosition #24 @39 RefTypeUse <Ivl:19> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 20: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #25 @40 RefTypeDef <Ivl:20> CAST BB01 regmask=[ebx esi edi]>
<RefPosition #25 @40 RefTypeDef <Ivl:20> CAST BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N021. lclVar -> (21.N021); N039. cast -> (40.N039) }
N041. t41 = const 0 REG NA
consume=0 produce=1
t41 = op
Def candidates [allInt], Use candidates [allInt]
Interval 21: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #26 @42 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[ebx esi edi]>
<RefPosition #26 @42 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N041. const -> (42.N041); N021. lclVar -> (21.N021); N039. cast -> (40.N039) }
t43 (i:3)
at start of tree, map contains: { N041. const -> (42.N041); N021. lclVar -> (21.N021); N039. cast -> (40.N039); N043. lclVar -> (43.N043) }
N045. t45 = cast
consume=1 produce=1
t45 = op
t43 <RefPosition #27 @45 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx]>
Def candidates [eax ecx edx ebx], Use candidates [allInt]
Interval 22: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #28 @46 RefTypeDef <Ivl:22> CAST BB01 regmask=[eax ecx edx ebx]>
<RefPosition #28 @46 RefTypeDef <Ivl:22> CAST BB01 regmask=[eax ecx edx ebx]>
at start of tree, map contains: { N041. const -> (42.N041); N021. lclVar -> (21.N021); N045. cast -> (46.N045); N039. cast -> (40.N039) }
N047. const 0 REG NA
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N041. const -> (42.N041); N021. lclVar -> (21.N021); N045. cast -> (46.N045); N039. cast -> (40.N039) }
N049. t49* = V05 MEM
consume=0 produce=1
t49 = op
Def candidates [allInt], Use candidates [allInt]
Interval 23: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #29 @50 RefTypeDef <Ivl:23> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #29 @50 RefTypeDef <Ivl:23> LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N041. const -> (42.N041); N021. lclVar -> (21.N021); N045. cast -> (46.N045); N039. cast -> (40.N039); N049. lclVar -> (50.N049) }
N051. t51 = V06 MEM
consume=0 produce=1
t51 = op
Def candidates [allInt], Use candidates [allInt]
Interval 24: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #30 @52 RefTypeDef <Ivl:24> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #30 @52 RefTypeDef <Ivl:24> LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N041. const -> (42.N041); N051. lclVar -> (52.N051); N021. lclVar -> (21.N021); N045. cast -> (46.N045); N039. cast -> (40.N039); N049. lclVar -> (50.N049) }
N053. t53 = -Lo (Rev)
consume=2 produce=1
t53 = op
t46 <RefPosition #31 @53 RefTypeUse <Ivl:22> BB01 regmask=[ebx esi edi]>
t50 <RefPosition #32 @53 RefTypeUse <Ivl:23> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 25: RefPositions {} physReg:NA Preferences=[allInt]
Assigning related <I23> to <I25>
<RefPosition #33 @54 RefTypeDef <Ivl:25> SUB_LO BB01 regmask=[ebx esi edi]>
<RefPosition #33 @54 RefTypeDef <Ivl:25> SUB_LO BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N053. -Lo -> (54.N053); N041. const -> (42.N041); N051. lclVar -> (52.N051); N021. lclVar -> (21.N021); N039. cast -> (40.N039) }
N055. t55 = -Hi
consume=1 produce=1
t55 = op
t52 <RefPosition #34 @55 RefTypeUse <Ivl:24> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 26: RefPositions {} physReg:NA Preferences=[allInt]
Assigning related <I24> to <I26>
<RefPosition #35 @56 RefTypeDef <Ivl:26> SUB_HI BB01 regmask=[ebx esi edi]>
<RefPosition #35 @56 RefTypeDef <Ivl:26> SUB_HI BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N053. -Lo -> (54.N053); N055. -Hi -> (56.N055); N041. const -> (42.N041); N021. lclVar -> (21.N021); N039. cast -> (40.N039) }
N057. gt_long
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N041. const -> (42.N041); N021. lclVar -> (21.N021); N039. cast -> (40.N039); N057. gt_long -> (54.N053, 56.N055) }
N059. t59 = cast_ovfl
consume=2 produce=1
t59 = op
t54 <RefPosition #36 @59 RefTypeUse <Ivl:25> BB01 regmask=[ebx esi edi]>
t56 <RefPosition #37 @59 RefTypeUse <Ivl:26> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 27: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #38 @60 RefTypeDef <Ivl:27> CAST BB01 regmask=[ebx esi edi]>
<RefPosition #38 @60 RefTypeDef <Ivl:27> CAST BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N059. cast -> (60.N059); N041. const -> (42.N041); N021. lclVar -> (21.N021); N039. cast -> (40.N039) }
N061. const 0 REG NA
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N059. cast -> (60.N059); N041. const -> (42.N041); N021. lclVar -> (21.N021); N039. cast -> (40.N039) }
N063. t63 = arrMDIdx[i, , ]
consume=2 produce=1
t63 = op
t21 <RefPosition #39 @63 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi]>
t40 <RefPosition #40 @63 RefTypeUse <Ivl:20> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 28: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #41 @64 RefTypeDef <Ivl:28> ARR_INDEX BB01 regmask=[ebx esi edi]>
<RefPosition #41 @64 RefTypeDef <Ivl:28> ARR_INDEX BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N059. cast -> (60.N059); N041. const -> (42.N041); N063. arrMDIdx -> (64.N063) }
t65 (i:1)
at start of tree, map contains: { N059. cast -> (60.N059); N065. lclVar -> (65.N065); N041. const -> (42.N041); N063. arrMDIdx -> (64.N063) }
N067. t67 = arrMDOffs[i, , ]
consume=2 produce=1
t67 = op
t64 <RefPosition #42 @67 RefTypeUse <Ivl:28> BB01 regmask=[ebx esi edi]>
t65 <RefPosition #43 @67 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 29: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #44 @68 RefTypeDef <Ivl:29> ARR_OFFSET BB01 regmask=[ebx esi edi]>
<RefPosition #44 @68 RefTypeDef <Ivl:29> ARR_OFFSET BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N059. cast -> (60.N059); N041. const -> (42.N041); N067. arrMDOffs -> (68.N067) }
t69 (i:1)
at start of tree, map contains: { N059. cast -> (60.N059); N041. const -> (42.N041); N067. arrMDOffs -> (68.N067); N069. lclVar -> (69.N069) }
N071. t71 = arrMDIdx[*,j, ]
consume=2 produce=1
t71 = op
t69 <RefPosition #45 @71 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi]>
t42 <RefPosition #46 @71 RefTypeUse <Ivl:21> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 30: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #47 @72 RefTypeDef <Ivl:30> ARR_INDEX BB01 regmask=[ebx esi edi]>
<RefPosition #47 @72 RefTypeDef <Ivl:30> ARR_INDEX BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N059. cast -> (60.N059); N071. arrMDIdx -> (72.N071); N067. arrMDOffs -> (68.N067) }
t73 (i:1)
at start of tree, map contains: { N059. cast -> (60.N059); N071. arrMDIdx -> (72.N071); N073. lclVar -> (73.N073); N067. arrMDOffs -> (68.N067) }
N075. t75 = arrMDOffs[*,j, ]
consume=3 produce=1
t75 = op
Interval 31: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #48 @75 RefTypeDef <Ivl:31 internal> ARR_OFFSET BB01 regmask=[allInt]>
t68 <RefPosition #49 @75 RefTypeUse <Ivl:29> BB01 regmask=[allInt]>
t72 <RefPosition #50 @75 RefTypeUse <Ivl:30> BB01 regmask=[allInt]>
t73 <RefPosition #51 @75 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #52 @75 RefTypeUse <Ivl:31 internal> ARR_OFFSET BB01 regmask=[allInt]>
Def candidates [allInt], Use candidates [allInt]
Interval 32: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #53 @76 RefTypeDef <Ivl:32> ARR_OFFSET BB01 regmask=[allInt]>
<RefPosition #53 @76 RefTypeDef <Ivl:32> ARR_OFFSET BB01 regmask=[allInt]>
at start of tree, map contains: { N059. cast -> (60.N059); N075. arrMDOffs -> (76.N075) }
t77 (i:1)
at start of tree, map contains: { N059. cast -> (60.N059); N075. arrMDOffs -> (76.N075); N077. lclVar -> (77.N077) }
N079. t79 = arrMDIdx[*,*,k]
consume=2 produce=1
t79 = op
t77 <RefPosition #54 @79 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi]>
t60 <RefPosition #55 @79 RefTypeUse <Ivl:27> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 33: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #56 @80 RefTypeDef <Ivl:33> ARR_INDEX BB01 regmask=[ebx esi edi]>
<RefPosition #56 @80 RefTypeDef <Ivl:33> ARR_INDEX BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N079. arrMDIdx -> (80.N079); N075. arrMDOffs -> (76.N075) }
t81 (i:1)
at start of tree, map contains: { N079. arrMDIdx -> (80.N079); N081. lclVar -> (81.N081); N075. arrMDOffs -> (76.N075) }
N083. t83 = arrMDOffs[*,*,k]
consume=3 produce=1
t83 = op
Interval 34: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #57 @83 RefTypeDef <Ivl:34 internal> ARR_OFFSET BB01 regmask=[allInt]>
t76 <RefPosition #58 @83 RefTypeUse <Ivl:32> BB01 regmask=[allInt]>
t80 <RefPosition #59 @83 RefTypeUse <Ivl:33> BB01 regmask=[allInt]>
t81 <RefPosition #60 @83 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #61 @83 RefTypeUse <Ivl:34 internal> ARR_OFFSET BB01 regmask=[allInt]>
Def candidates [allInt], Use candidates [allInt]
Interval 35: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #62 @84 RefTypeDef <Ivl:35> ARR_OFFSET BB01 regmask=[allInt]>
<RefPosition #62 @84 RefTypeDef <Ivl:35> ARR_OFFSET BB01 regmask=[allInt]>
at start of tree, map contains: { N083. arrMDOffs -> (84.N083) }
t85 (i:1)
at start of tree, map contains: { N083. arrMDOffs -> (84.N083); N085. lclVar -> (85.N085) }
N087. t87 = lea(b+(i*8)+32)(Rev)
consume=2 produce=1
t87 = op
t84 <RefPosition #63 @87 RefTypeUse <Ivl:35> BB01 regmask=[ebx esi edi]>
t85 <RefPosition #64 @87 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 36: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #65 @88 RefTypeDef <Ivl:36> LEA BB01 regmask=[ebx esi edi]>
<RefPosition #65 @88 RefTypeDef <Ivl:36> LEA BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N087. lea -> (88.N087) }
N089. V09(L9)
consume=1 produce=0
Assigning related <L9> to <I36>
t89 (i:9) = op
t88 <RefPosition #66 @89 RefTypeUse <Ivl:36> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
<RefPosition #67 @90 RefTypeDef <Ivl:9 V09> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #67 @90 RefTypeDef <Ivl:9 V09> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { }
t91 (i:9)
at start of tree, map contains: { N091. lclVar -> (91.N091) }
t93 (i:7)
at start of tree, map contains: { N091. lclVar -> (91.N091); N093. lclVar -> (93.N093) }
N095. storeIndir
consume=2 produce=0
op
t91 <RefPosition #68 @95 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi]>
t93 <RefPosition #69 @95 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { }
t97 (i:8)
at start of tree, map contains: { N097. lclVar -> (97.N097) }
t99 (i:9)
at start of tree, map contains: { N099. lclVar -> (99.N099); N097. lclVar -> (97.N097) }
N101. lea(b+4)
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N101. lea -> (99.N099); N097. lclVar -> (97.N097) }
N103. storeIndir(Rev)
consume=2 produce=0
op
t97 <RefPosition #70 @103 RefTypeUse <Ivl:8 V08> LCL_VAR BB01 regmask=[ebx esi edi]>
t99 <RefPosition #71 @103 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { }
N105. il_offset IL offset: 24 REG NA
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { }
t107 (i:0)
at start of tree, map contains: { N107. lclVar -> (107.N107) }
t109 (i:7)
at start of tree, map contains: { N107. lclVar -> (107.N107); N109. lclVar -> (109.N109) }
N111. t111 = lea(b+(i*8)+0)
consume=2 produce=1
t111 = op
t107 <RefPosition #72 @111 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ebx esi edi]>
t109 <RefPosition #73 @111 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
Interval 37: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #74 @112 RefTypeDef <Ivl:37> LEA BB01 regmask=[ebx esi edi]>
<RefPosition #74 @112 RefTypeDef <Ivl:37> LEA BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N111. lea -> (112.N111) }
N113. V10(L10)
consume=1 produce=0
Assigning related <L10> to <I37>
t113 (i:10) = op
t112 <RefPosition #75 @113 RefTypeUse <Ivl:37> BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [allInt]
<RefPosition #76 @114 RefTypeDef <Ivl:10 V10> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #76 @114 RefTypeDef <Ivl:10 V10> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { }
t115 (i:10)
at start of tree, map contains: { N115. lclVar -> (115.N115) }
N117. t117 = indir
consume=1 produce=1
t117 = op
t115 <RefPosition #77 @117 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [eax]
Interval 38: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #78 @118 RefTypeDef <Ivl:38> IND BB01 regmask=[ebx esi edi]>
<RefPosition #78 @118 RefTypeDef <Ivl:38> IND BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N117. indir -> (118.N117) }
t119 (i:10)
at start of tree, map contains: { N117. indir -> (118.N117); N119. lclVar -> (119.N119) }
N121. lea(b+4)
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N117. indir -> (118.N117); N121. lea -> (119.N119) }
N123. t123 = indir
consume=1 produce=1
t123 = op
t119 <RefPosition #79 @123 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi]>
Def candidates [allInt], Use candidates [edx]
Interval 39: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #80 @124 RefTypeDef <Ivl:39> IND BB01 regmask=[ebx esi edi]>
<RefPosition #80 @124 RefTypeDef <Ivl:39> IND BB01 regmask=[ebx esi edi]>
at start of tree, map contains: { N117. indir -> (118.N117); N123. indir -> (124.N123) }
N125. gt_long
consume=0 produce=0
op
Def candidates [allInt], Use candidates [allInt]
at start of tree, map contains: { N125. gt_long -> (118.N117, 124.N123) }
N127. return
consume=2 produce=0
op
t118 <RefPosition #81 @127 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax]>
<RefPosition #82 @127 RefTypeUse <Ivl:38> BB01 regmask=[eax] fixed>
t124 <RefPosition #83 @127 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx]>
<RefPosition #84 @127 RefTypeUse <Ivl:39> BB01 regmask=[edx] fixed>
Def candidates [allInt], Use candidates [allInt]
CALCULATING LAST USES for block 1, liveout={}
==============================
last use of V10 @123
last use of V07 @111
last use of V00 @111
last use of V09 @103
last use of V08 @103
last use of V01 @87
last use of V03 @45
use: {V00 V01 V03}
def: {V07 V08 V09 V10}
NEW BLOCK BB02
No allocated predecessor;
Setting incoming variable registers of BB02 to outVarToRegMap of BB01
<RefPosition #85 @129 RefTypeBB BB02 regmask=[]>
at start of tree, map contains: { }
N131. call help
consume=0 produce=0
op
Def candidates [eax], Use candidates [allInt]
<RefPosition #86 @132 RefTypeKill <Reg:eax> BB02 regmask=[eax]>
<RefPosition #87 @132 RefTypeKill <Reg:ecx> BB02 regmask=[ecx]>
<RefPosition #88 @132 RefTypeKill <Reg:edx> BB02 regmask=[edx]>
<RefPosition #89 @132 RefTypeKill <Reg:mm0> BB02 regmask=[mm0]>
<RefPosition #90 @132 RefTypeKill <Reg:mm1> BB02 regmask=[mm1]>
<RefPosition #91 @132 RefTypeKill <Reg:mm2> BB02 regmask=[mm2]>
<RefPosition #92 @132 RefTypeKill <Reg:mm3> BB02 regmask=[mm3]>
<RefPosition #93 @132 RefTypeKill <Reg:mm4> BB02 regmask=[mm4]>
<RefPosition #94 @132 RefTypeKill <Reg:mm5> BB02 regmask=[mm5]>
<RefPosition #95 @132 RefTypeKill <Reg:mm6> BB02 regmask=[mm6]>
<RefPosition #96 @132 RefTypeKill <Reg:mm7> BB02 regmask=[mm7]>
CALCULATING LAST USES for block 2, liveout={}
==============================
use: {}
def: {}
NEW BLOCK BB03
No allocated predecessor;
Setting incoming variable registers of BB03 to outVarToRegMap of BB02
<RefPosition #97 @133 RefTypeBB BB03 regmask=[]>
at start of tree, map contains: { }
N135. call help
consume=0 produce=0
op
Def candidates [eax], Use candidates [allInt]
<RefPosition #98 @136 RefTypeKill <Reg:eax> BB03 regmask=[eax]>
<RefPosition #99 @136 RefTypeKill <Reg:ecx> BB03 regmask=[ecx]>
<RefPosition #100 @136 RefTypeKill <Reg:edx> BB03 regmask=[edx]>
<RefPosition #101 @136 RefTypeKill <Reg:mm0> BB03 regmask=[mm0]>
<RefPosition #102 @136 RefTypeKill <Reg:mm1> BB03 regmask=[mm1]>
<RefPosition #103 @136 RefTypeKill <Reg:mm2> BB03 regmask=[mm2]>
<RefPosition #104 @136 RefTypeKill <Reg:mm3> BB03 regmask=[mm3]>
<RefPosition #105 @136 RefTypeKill <Reg:mm4> BB03 regmask=[mm4]>
<RefPosition #106 @136 RefTypeKill <Reg:mm5> BB03 regmask=[mm5]>
<RefPosition #107 @136 RefTypeKill <Reg:mm6> BB03 regmask=[mm6]>
<RefPosition #108 @136 RefTypeKill <Reg:mm7> BB03 regmask=[mm7]>
CALCULATING LAST USES for block 3, liveout={}
==============================
use: {}
def: {}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) RefPositions {#1@0 #72@111} physReg:ecx Preferences=[ecx]
Interval 1: (V01) RefPositions {#0@0 #39@63 #43@67 #45@71 #51@75 #54@79 #60@83 #64@87} physReg:edx Preferences=[edx]
Interval 2: (V02) RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: (V03) RefPositions {#2@0 #14@25 #27@45} physReg:NA Preferences=[allInt]
Interval 4: (V04) RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: (V05) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: (V06) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 7: (V07) (struct) RefPositions {#11@18 #69@95 #73@111} physReg:NA Preferences=[allInt]
Interval 8: (V08) (struct) RefPositions {#13@20 #70@103} physReg:NA Preferences=[allInt]
Interval 9: (V09) RefPositions {#67@90 #68@95 #71@103} physReg:NA Preferences=[allInt]
Interval 10: (V10) RefPositions {#76@114 #77@117 #79@123} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {#4@6 #6@13} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#5@8 #8@15} physReg:NA Preferences=[allInt]
Interval 13: RefPositions {#7@14 #10@17} physReg:NA Preferences=[allInt] RelatedInterval <L7>[032B20B8]
Interval 14: RefPositions {#9@16 #12@19} physReg:NA Preferences=[allInt] RelatedInterval <L8>[032B20EC]
Interval 15: RefPositions {#15@26 #18@33} physReg:NA Preferences=[eax ecx edx ebx]
Interval 16: RefPositions {#16@30 #19@33} physReg:NA Preferences=[allInt]
Interval 17: RefPositions {#17@32 #21@35} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#20@34 #23@39} physReg:NA Preferences=[allInt] RelatedInterval <I16>[032B266C]
Interval 19: RefPositions {#22@36 #24@39} physReg:NA Preferences=[allInt] RelatedInterval <I17>[032B26D4]
Interval 20: RefPositions {#25@40 #40@63} physReg:NA Preferences=[allInt]
Interval 21: (constant) RefPositions {#26@42 #46@71} physReg:NA Preferences=[allInt]
Interval 22: RefPositions {#28@46 #31@53} physReg:NA Preferences=[eax ecx edx ebx]
Interval 23: RefPositions {#29@50 #32@53} physReg:NA Preferences=[allInt]
Interval 24: RefPositions {#30@52 #34@55} physReg:NA Preferences=[allInt]
Interval 25: RefPositions {#33@54 #36@59} physReg:NA Preferences=[allInt] RelatedInterval <I23>[032B2A7C]
Interval 26: RefPositions {#35@56 #37@59} physReg:NA Preferences=[allInt] RelatedInterval <I24>[032B2AE4]
Interval 27: RefPositions {#38@60 #55@79} physReg:NA Preferences=[allInt]
Interval 28: RefPositions {#41@64 #42@67} physReg:NA Preferences=[allInt]
Interval 29: RefPositions {#44@68 #49@75} physReg:NA Preferences=[allInt]
Interval 30: RefPositions {#47@72 #50@75} physReg:NA Preferences=[allInt]
Interval 31: (INTERNAL) RefPositions {#48@75 #52@75} physReg:NA Preferences=[allInt]
Interval 32: RefPositions {#53@76 #58@83} physReg:NA Preferences=[allInt]
Interval 33: RefPositions {#56@80 #59@83} physReg:NA Preferences=[allInt]
Interval 34: (INTERNAL) RefPositions {#57@83 #61@83} physReg:NA Preferences=[allInt]
Interval 35: RefPositions {#62@84 #63@87} physReg:NA Preferences=[allInt]
Interval 36: RefPositions {#65@88 #66@89} physReg:NA Preferences=[allInt] RelatedInterval <L9>[032B2120]
Interval 37: RefPositions {#74@112 #75@113} physReg:NA Preferences=[allInt] RelatedInterval <L10>[032B2154]
Interval 38: RefPositions {#78@118 #82@127} physReg:NA Preferences=[eax]
Interval 39: RefPositions {#80@124 #84@127} physReg:NA Preferences=[edx]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 ->#39 RefTypeParamDef <Ivl:1 V01> BB03 regmask=[edx] fixed>
<RefPosition #1 @0 ->#72 RefTypeParamDef <Ivl:0 V00> BB03 regmask=[ecx] fixed>
<RefPosition #2 @0 ->#14 RefTypeParamDef <Ivl:3 V03> BB03 regmask=[ebx esi edi]>
<RefPosition #3 @0 RefTypeBB BB01 regmask=[]>
<RefPosition #4 @6 ->#6 RefTypeDef <Ivl:11> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #5 @8 ->#8 RefTypeDef <Ivl:12> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #6 @13 RefTypeUse <Ivl:11> BB01 regmask=[ebx esi edi] last>
<RefPosition #7 @14 ->#10 RefTypeDef <Ivl:13> SUB_LO BB01 regmask=[ebx esi edi]>
<RefPosition #8 @15 RefTypeUse <Ivl:12> BB01 regmask=[ebx esi edi] last>
<RefPosition #9 @16 ->#12 RefTypeDef <Ivl:14> SUB_HI BB01 regmask=[ebx esi edi]>
<RefPosition #10 @17 RefTypeUse <Ivl:13> BB01 regmask=[ebx esi edi] last>
<RefPosition #11 @18 ->#69 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #12 @19 RefTypeUse <Ivl:14> BB01 regmask=[ebx esi edi] last>
<RefPosition #13 @20 ->#70 RefTypeDef <Ivl:8 V08> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #14 @25 ->#27 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx]>
<RefPosition #15 @26 ->#18 RefTypeDef <Ivl:15> CAST BB01 regmask=[ebx]>
<RefPosition #16 @30 ->#19 RefTypeDef <Ivl:16> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #17 @32 ->#21 RefTypeDef <Ivl:17> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #18 @33 RefTypeUse <Ivl:15> BB01 regmask=[ebx esi edi] last delay regOptional>
<RefPosition #19 @33 RefTypeUse <Ivl:16> BB01 regmask=[ebx esi edi] last>
<RefPosition #20 @34 ->#23 RefTypeDef <Ivl:18> SUB_LO BB01 regmask=[ebx esi edi]>
<RefPosition #21 @35 RefTypeUse <Ivl:17> BB01 regmask=[ebx esi edi] last>
<RefPosition #22 @36 ->#24 RefTypeDef <Ivl:19> SUB_HI BB01 regmask=[ebx esi edi]>
<RefPosition #23 @39 RefTypeUse <Ivl:18> BB01 regmask=[ebx esi edi] last>
<RefPosition #24 @39 RefTypeUse <Ivl:19> BB01 regmask=[ebx esi edi] last>
<RefPosition #25 @40 ->#40 RefTypeDef <Ivl:20> CAST BB01 regmask=[ebx esi edi]>
<RefPosition #26 @42 ->#46 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[ebx esi edi]>
<RefPosition #27 @45 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx] last>
<RefPosition #28 @46 ->#31 RefTypeDef <Ivl:22> CAST BB01 regmask=[ebx]>
<RefPosition #29 @50 ->#32 RefTypeDef <Ivl:23> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #30 @52 ->#34 RefTypeDef <Ivl:24> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #31 @53 RefTypeUse <Ivl:22> BB01 regmask=[ebx esi edi] last delay regOptional>
<RefPosition #32 @53 RefTypeUse <Ivl:23> BB01 regmask=[ebx esi edi] last>
<RefPosition #33 @54 ->#36 RefTypeDef <Ivl:25> SUB_LO BB01 regmask=[ebx esi edi]>
<RefPosition #34 @55 RefTypeUse <Ivl:24> BB01 regmask=[ebx esi edi] last>
<RefPosition #35 @56 ->#37 RefTypeDef <Ivl:26> SUB_HI BB01 regmask=[ebx esi edi]>
<RefPosition #36 @59 RefTypeUse <Ivl:25> BB01 regmask=[ebx esi edi] last>
<RefPosition #37 @59 RefTypeUse <Ivl:26> BB01 regmask=[ebx esi edi] last>
<RefPosition #38 @60 ->#55 RefTypeDef <Ivl:27> CAST BB01 regmask=[ebx esi edi]>
<RefPosition #39 @63 ->#43 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #40 @63 RefTypeUse <Ivl:20> BB01 regmask=[ebx esi edi] last>
<RefPosition #41 @64 ->#42 RefTypeDef <Ivl:28> ARR_INDEX BB01 regmask=[ebx esi edi]>
<RefPosition #42 @67 RefTypeUse <Ivl:28> BB01 regmask=[ebx esi edi] last>
<RefPosition #43 @67 ->#45 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #44 @68 ->#49 RefTypeDef <Ivl:29> ARR_OFFSET BB01 regmask=[ebx esi edi]>
<RefPosition #45 @71 ->#51 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #46 @71 RefTypeUse <Ivl:21> BB01 regmask=[ebx esi edi] last>
<RefPosition #47 @72 ->#50 RefTypeDef <Ivl:30> ARR_INDEX BB01 regmask=[ebx esi edi]>
<RefPosition #48 @75 ->#52 RefTypeDef <Ivl:31 internal> ARR_OFFSET BB01 regmask=[allInt]>
<RefPosition #49 @75 RefTypeUse <Ivl:29> BB01 regmask=[allInt] last>
<RefPosition #50 @75 RefTypeUse <Ivl:30> BB01 regmask=[allInt] last>
<RefPosition #51 @75 ->#54 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #52 @75 RefTypeUse <Ivl:31 internal> ARR_OFFSET BB01 regmask=[allInt] last>
<RefPosition #53 @76 ->#58 RefTypeDef <Ivl:32> ARR_OFFSET BB01 regmask=[allInt]>
<RefPosition #54 @79 ->#60 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #55 @79 RefTypeUse <Ivl:27> BB01 regmask=[ebx esi edi] last>
<RefPosition #56 @80 ->#59 RefTypeDef <Ivl:33> ARR_INDEX BB01 regmask=[ebx esi edi]>
<RefPosition #57 @83 ->#61 RefTypeDef <Ivl:34 internal> ARR_OFFSET BB01 regmask=[allInt]>
<RefPosition #58 @83 RefTypeUse <Ivl:32> BB01 regmask=[allInt] last>
<RefPosition #59 @83 RefTypeUse <Ivl:33> BB01 regmask=[allInt] last>
<RefPosition #60 @83 ->#64 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #61 @83 RefTypeUse <Ivl:34 internal> ARR_OFFSET BB01 regmask=[allInt] last>
<RefPosition #62 @84 ->#63 RefTypeDef <Ivl:35> ARR_OFFSET BB01 regmask=[ebx esi edi]>
<RefPosition #63 @87 RefTypeUse <Ivl:35> BB01 regmask=[ebx esi edi] last>
<RefPosition #64 @87 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #65 @88 ->#66 RefTypeDef <Ivl:36> LEA BB01 regmask=[ebx esi edi]>
<RefPosition #66 @89 RefTypeUse <Ivl:36> BB01 regmask=[ebx esi edi] last>
<RefPosition #67 @90 ->#68 RefTypeDef <Ivl:9 V09> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #68 @95 ->#71 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #69 @95 ->#73 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #70 @103 RefTypeUse <Ivl:8 V08> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #71 @103 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #72 @111 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #73 @111 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #74 @112 ->#75 RefTypeDef <Ivl:37> LEA BB01 regmask=[ebx esi edi]>
<RefPosition #75 @113 RefTypeUse <Ivl:37> BB01 regmask=[ebx esi edi] last>
<RefPosition #76 @114 ->#77 RefTypeDef <Ivl:10 V10> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #77 @117 ->#79 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #78 @118 ->#82 RefTypeDef <Ivl:38> IND BB01 regmask=[ebx esi edi]>
<RefPosition #79 @123 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #80 @124 ->#84 RefTypeDef <Ivl:39> IND BB01 regmask=[ebx esi edi]>
<RefPosition #81 @127 ->#86 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax]>
<RefPosition #82 @127 RefTypeUse <Ivl:38> BB01 regmask=[eax] last fixed>
<RefPosition #83 @127 ->#88 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx]>
<RefPosition #84 @127 RefTypeUse <Ivl:39> BB01 regmask=[edx] last fixed>
<RefPosition #85 @129 RefTypeBB BB02 regmask=[]>
<RefPosition #86 @132 ->#98 RefTypeKill <Reg:eax> BB02 regmask=[eax] last>
<RefPosition #87 @132 ->#99 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] last>
<RefPosition #88 @132 ->#100 RefTypeKill <Reg:edx> BB02 regmask=[edx] last>
<RefPosition #89 @132 ->#101 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] last>
<RefPosition #90 @132 ->#102 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] last>
<RefPosition #91 @132 ->#103 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] last>
<RefPosition #92 @132 ->#104 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] last>
<RefPosition #93 @132 ->#105 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] last>
<RefPosition #94 @132 ->#106 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] last>
<RefPosition #95 @132 ->#107 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] last>
<RefPosition #96 @132 ->#108 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] last>
<RefPosition #97 @133 RefTypeBB BB03 regmask=[]>
<RefPosition #98 @136 RefTypeKill <Reg:eax> BB03 regmask=[eax] last>
<RefPosition #99 @136 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] last>
<RefPosition #100 @136 RefTypeKill <Reg:edx> BB03 regmask=[edx] last>
<RefPosition #101 @136 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] last>
<RefPosition #102 @136 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] last>
<RefPosition #103 @136 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] last>
<RefPosition #104 @136 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] last>
<RefPosition #105 @136 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] last>
<RefPosition #106 @136 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] last>
<RefPosition #107 @136 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] last>
<RefPosition #108 @136 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] last>
-----------------
<RefPosition #1 @0 ->#72 RefTypeParamDef <Ivl:0 V00> BB03 regmask=[ecx] fixed>
<RefPosition #72 @111 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ebx esi edi] last>
-----------------
<RefPosition #0 @0 ->#39 RefTypeParamDef <Ivl:1 V01> BB03 regmask=[edx] fixed>
<RefPosition #39 @63 ->#43 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #43 @67 ->#45 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #45 @71 ->#51 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #51 @75 ->#54 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #54 @79 ->#60 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #60 @83 ->#64 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #64 @87 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] last>
-----------------
-----------------
<RefPosition #2 @0 ->#14 RefTypeParamDef <Ivl:3 V03> BB03 regmask=[ebx esi edi]>
<RefPosition #14 @25 ->#27 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx]>
<RefPosition #27 @45 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx] last>
-----------------
-----------------
-----------------
-----------------
<RefPosition #11 @18 ->#69 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #69 @95 ->#73 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #73 @111 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi] last>
-----------------
<RefPosition #13 @20 ->#70 RefTypeDef <Ivl:8 V08> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #70 @103 RefTypeUse <Ivl:8 V08> LCL_VAR BB01 regmask=[ebx esi edi] last>
-----------------
<RefPosition #67 @90 ->#68 RefTypeDef <Ivl:9 V09> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #68 @95 ->#71 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #71 @103 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi] last>
-----------------
<RefPosition #76 @114 ->#77 RefTypeDef <Ivl:10 V10> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #77 @117 ->#79 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #79 @123 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi] last>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V01 V00 V03
BB01 [000..02A) (return), preds={} succs={}
=====
N003. il_offset IL offset: 0 REG NA
N005. V05 MEM
Def:<I11>(#4)
N007. V06 MEM
Def:<I12>(#5)
N009. const 1 REG NA
N011. const 0 REG NA
N013. -Lo
Use:<I11>(#6) *
Def:<I13>(#7) Pref:<L7>
N015. -Hi
Use:<I12>(#8) *
Def:<I14>(#9) Pref:<L8>
N017. V07(L7)
Use:<I13>(#10) *
Def:<L7>(#11)
N019. V08(L8)
Use:<I14>(#12) *
Def:<L8>(#13)
N021. V01(L1)
N023. V03(L3)
N025. cast
Use:<L3>(#14)
Def:<I15>(#15)
N027. const 0 REG NA
N029. V05 MEM
Def:<I16>(#16)
N031. V06 MEM
Def:<I17>(#17)
N033. -Lo (Rev)
Use:<I15>(#18) *
Use:<I16>(#19) *
Def:<I18>(#20) Pref:<I16>
N035. -Hi
Use:<I17>(#21) *
Def:<I19>(#22) Pref:<I17>
N037. gt_long
N039. cast_ovfl
Use:<I18>(#23) *
Use:<I19>(#24) *
Def:<I20>(#25)
N041. const 0 REG NA
Def:<I21>(#26)
N043. V03(L3)
N045. cast
Use:<L3>(#27) *
Def:<I22>(#28)
N047. const 0 REG NA
N049. V05 MEM
Def:<I23>(#29)
N051. V06 MEM
Def:<I24>(#30)
N053. -Lo (Rev)
Use:<I22>(#31) *
Use:<I23>(#32) *
Def:<I25>(#33) Pref:<I23>
N055. -Hi
Use:<I24>(#34) *
Def:<I26>(#35) Pref:<I24>
N057. gt_long
N059. cast_ovfl
Use:<I25>(#36) *
Use:<I26>(#37) *
Def:<I27>(#38)
N061. const 0 REG NA
N063. arrMDIdx[i, , ]
Use:<L1>(#39)
Use:<I20>(#40) *
Def:<I28>(#41)
N065. V01(L1)
N067. arrMDOffs[i, , ]
Use:<I28>(#42) *
Use:<L1>(#43)
Def:<I29>(#44)
N069. V01(L1)
N071. arrMDIdx[*,j, ]
Use:<L1>(#45)
Use:<I21>(#46) *
Def:<I30>(#47)
N073. V01(L1)
N075. arrMDOffs[*,j, ]
Def:<T31>(#48)
Use:<I29>(#49) *
Use:<I30>(#50) *
Use:<L1>(#51)
Use:<T31>(#52) *
Def:<I32>(#53)
N077. V01(L1)
N079. arrMDIdx[*,*,k]
Use:<L1>(#54)
Use:<I27>(#55) *
Def:<I33>(#56)
N081. V01(L1)
N083. arrMDOffs[*,*,k]
Def:<T34>(#57)
Use:<I32>(#58) *
Use:<I33>(#59) *
Use:<L1>(#60)
Use:<T34>(#61) *
Def:<I35>(#62)
N085. V01(L1)
N087. lea(b+(i*8)+32)(Rev)
Use:<I35>(#63) *
Use:<L1>(#64) *
Def:<I36>(#65) Pref:<L9>
N089. V09(L9)
Use:<I36>(#66) *
Def:<L9>(#67)
N091. V09(L9)
N093. V07(L7)
N095. storeIndir
Use:<L9>(#68)
Use:<L7>(#69)
N097. V08(L8)
N099. V09(L9)
N101. lea(b+4)
N103. storeIndir(Rev)
Use:<L8>(#70) *
Use:<L9>(#71) *
N105. il_offset IL offset: 24 REG NA
N107. V00(L0)
N109. V07(L7)
N111. lea(b+(i*8)+0)
Use:<L0>(#72) *
Use:<L7>(#73) *
Def:<I37>(#74) Pref:<L10>
N113. V10(L10)
Use:<I37>(#75) *
Def:<L10>(#76)
N115. V10(L10)
N117. indir
Use:<L10>(#77)
Def:<I38>(#78)
N119. V10(L10)
N121. lea(b+4)
N123. indir
Use:<L10>(#79) *
Def:<I39>(#80)
N125. gt_long
N127. return
Use:<I38>(#82) Fixed:eax(#81) *
Use:<I39>(#84) Fixed:edx(#83) *
BB02 [???..???) (throw), preds={} succs={}
=====
N131. call help
Kill: eax ecx edx mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7
BB03 [???..???) (throw), preds={} succs={}
=====
N135. call help
Kill: eax ecx edx mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7
Linear scan intervals after buildIntervals:
Interval 0: (V00) RefPositions {#1@0 #72@111} physReg:ecx Preferences=[ecx]
Interval 1: (V01) RefPositions {#0@0 #39@63 #43@67 #45@71 #51@75 #54@79 #60@83 #64@87} physReg:edx Preferences=[edx]
Interval 2: (V02) RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: (V03) RefPositions {#2@0 #14@25 #27@45} physReg:NA Preferences=[allInt]
Interval 4: (V04) RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: (V05) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: (V06) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 7: (V07) (struct) RefPositions {#11@18 #69@95 #73@111} physReg:NA Preferences=[allInt]
Interval 8: (V08) (struct) RefPositions {#13@20 #70@103} physReg:NA Preferences=[allInt]
Interval 9: (V09) RefPositions {#67@90 #68@95 #71@103} physReg:NA Preferences=[allInt]
Interval 10: (V10) RefPositions {#76@114 #77@117 #79@123} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {#4@6 #6@13} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#5@8 #8@15} physReg:NA Preferences=[allInt]
Interval 13: RefPositions {#7@14 #10@17} physReg:NA Preferences=[allInt] RelatedInterval <L7>[032B20B8]
Interval 14: RefPositions {#9@16 #12@19} physReg:NA Preferences=[allInt] RelatedInterval <L8>[032B20EC]
Interval 15: RefPositions {#15@26 #18@33} physReg:NA Preferences=[eax ecx edx ebx]
Interval 16: RefPositions {#16@30 #19@33} physReg:NA Preferences=[allInt]
Interval 17: RefPositions {#17@32 #21@35} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#20@34 #23@39} physReg:NA Preferences=[allInt] RelatedInterval <I16>[032B266C]
Interval 19: RefPositions {#22@36 #24@39} physReg:NA Preferences=[allInt] RelatedInterval <I17>[032B26D4]
Interval 20: RefPositions {#25@40 #40@63} physReg:NA Preferences=[allInt]
Interval 21: (constant) RefPositions {#26@42 #46@71} physReg:NA Preferences=[allInt]
Interval 22: RefPositions {#28@46 #31@53} physReg:NA Preferences=[eax ecx edx ebx]
Interval 23: RefPositions {#29@50 #32@53} physReg:NA Preferences=[allInt]
Interval 24: RefPositions {#30@52 #34@55} physReg:NA Preferences=[allInt]
Interval 25: RefPositions {#33@54 #36@59} physReg:NA Preferences=[allInt] RelatedInterval <I23>[032B2A7C]
Interval 26: RefPositions {#35@56 #37@59} physReg:NA Preferences=[allInt] RelatedInterval <I24>[032B2AE4]
Interval 27: RefPositions {#38@60 #55@79} physReg:NA Preferences=[allInt]
Interval 28: RefPositions {#41@64 #42@67} physReg:NA Preferences=[allInt]
Interval 29: RefPositions {#44@68 #49@75} physReg:NA Preferences=[allInt]
Interval 30: RefPositions {#47@72 #50@75} physReg:NA Preferences=[allInt]
Interval 31: (INTERNAL) RefPositions {#48@75 #52@75} physReg:NA Preferences=[allInt]
Interval 32: RefPositions {#53@76 #58@83} physReg:NA Preferences=[allInt]
Interval 33: RefPositions {#56@80 #59@83} physReg:NA Preferences=[allInt]
Interval 34: (INTERNAL) RefPositions {#57@83 #61@83} physReg:NA Preferences=[allInt]
Interval 35: RefPositions {#62@84 #63@87} physReg:NA Preferences=[allInt]
Interval 36: RefPositions {#65@88 #66@89} physReg:NA Preferences=[allInt] RelatedInterval <L9>[032B2120]
Interval 37: RefPositions {#74@112 #75@113} physReg:NA Preferences=[allInt] RelatedInterval <L10>[032B2154]
Interval 38: RefPositions {#78@118 #82@127} physReg:NA Preferences=[eax]
Interval 39: RefPositions {#80@124 #84@127} physReg:NA Preferences=[edx]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) RefPositions {#1@0 #72@111} physReg:ecx Preferences=[ecx]
Interval 1: (V01) RefPositions {#0@0 #39@63 #43@67 #45@71 #51@75 #54@79 #60@83 #64@87} physReg:edx Preferences=[edx]
Interval 2: (V02) RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: (V03) RefPositions {#2@0 #14@25 #27@45} physReg:NA Preferences=[allInt]
Interval 4: (V04) RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: (V05) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: (V06) (struct) RefPositions {} physReg:NA Preferences=[allInt]
Interval 7: (V07) (struct) RefPositions {#11@18 #69@95 #73@111} physReg:NA Preferences=[allInt]
Interval 8: (V08) (struct) RefPositions {#13@20 #70@103} physReg:NA Preferences=[allInt]
Interval 9: (V09) RefPositions {#67@90 #68@95 #71@103} physReg:NA Preferences=[allInt]
Interval 10: (V10) RefPositions {#76@114 #77@117 #79@123} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {#4@6 #6@13} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#5@8 #8@15} physReg:NA Preferences=[allInt]
Interval 13: RefPositions {#7@14 #10@17} physReg:NA Preferences=[allInt] RelatedInterval <L7>[032B20B8]
Interval 14: RefPositions {#9@16 #12@19} physReg:NA Preferences=[allInt] RelatedInterval <L8>[032B20EC]
Interval 15: RefPositions {#15@26 #18@33} physReg:NA Preferences=[eax ecx edx ebx]
Interval 16: RefPositions {#16@30 #19@33} physReg:NA Preferences=[allInt]
Interval 17: RefPositions {#17@32 #21@35} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#20@34 #23@39} physReg:NA Preferences=[allInt] RelatedInterval <I16>[032B266C]
Interval 19: RefPositions {#22@36 #24@39} physReg:NA Preferences=[allInt] RelatedInterval <I17>[032B26D4]
Interval 20: RefPositions {#25@40 #40@63} physReg:NA Preferences=[allInt]
Interval 21: (constant) RefPositions {#26@42 #46@71} physReg:NA Preferences=[allInt]
Interval 22: RefPositions {#28@46 #31@53} physReg:NA Preferences=[eax ecx edx ebx]
Interval 23: RefPositions {#29@50 #32@53} physReg:NA Preferences=[allInt]
Interval 24: RefPositions {#30@52 #34@55} physReg:NA Preferences=[allInt]
Interval 25: RefPositions {#33@54 #36@59} physReg:NA Preferences=[allInt] RelatedInterval <I23>[032B2A7C]
Interval 26: RefPositions {#35@56 #37@59} physReg:NA Preferences=[allInt] RelatedInterval <I24>[032B2AE4]
Interval 27: RefPositions {#38@60 #55@79} physReg:NA Preferences=[allInt]
Interval 28: RefPositions {#41@64 #42@67} physReg:NA Preferences=[allInt]
Interval 29: RefPositions {#44@68 #49@75} physReg:NA Preferences=[allInt]
Interval 30: RefPositions {#47@72 #50@75} physReg:NA Preferences=[allInt]
Interval 31: (INTERNAL) RefPositions {#48@75 #52@75} physReg:NA Preferences=[allInt]
Interval 32: RefPositions {#53@76 #58@83} physReg:NA Preferences=[allInt]
Interval 33: RefPositions {#56@80 #59@83} physReg:NA Preferences=[allInt]
Interval 34: (INTERNAL) RefPositions {#57@83 #61@83} physReg:NA Preferences=[allInt]
Interval 35: RefPositions {#62@84 #63@87} physReg:NA Preferences=[allInt]
Interval 36: RefPositions {#65@88 #66@89} physReg:NA Preferences=[allInt] RelatedInterval <L9>[032B2120]
Interval 37: RefPositions {#74@112 #75@113} physReg:NA Preferences=[allInt] RelatedInterval <L10>[032B2154]
Interval 38: RefPositions {#78@118 #82@127} physReg:NA Preferences=[eax]
Interval 39: RefPositions {#80@124 #84@127} physReg:NA Preferences=[edx]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 ->#39 RefTypeParamDef <Ivl:1 V01> BB03 regmask=[edx] fixed>
<RefPosition #1 @0 ->#72 RefTypeParamDef <Ivl:0 V00> BB03 regmask=[ecx] fixed>
<RefPosition #2 @0 ->#14 RefTypeParamDef <Ivl:3 V03> BB03 regmask=[ebx esi edi]>
<RefPosition #3 @0 RefTypeBB BB01 regmask=[]>
<RefPosition #4 @6 ->#6 RefTypeDef <Ivl:11> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #5 @8 ->#8 RefTypeDef <Ivl:12> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #6 @13 RefTypeUse <Ivl:11> BB01 regmask=[ebx esi edi] last>
<RefPosition #7 @14 ->#10 RefTypeDef <Ivl:13> SUB_LO BB01 regmask=[ebx esi edi]>
<RefPosition #8 @15 RefTypeUse <Ivl:12> BB01 regmask=[ebx esi edi] last>
<RefPosition #9 @16 ->#12 RefTypeDef <Ivl:14> SUB_HI BB01 regmask=[ebx esi edi]>
<RefPosition #10 @17 RefTypeUse <Ivl:13> BB01 regmask=[ebx esi edi] last>
<RefPosition #11 @18 ->#69 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #12 @19 RefTypeUse <Ivl:14> BB01 regmask=[ebx esi edi] last>
<RefPosition #13 @20 ->#70 RefTypeDef <Ivl:8 V08> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #14 @25 ->#27 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx]>
<RefPosition #15 @26 ->#18 RefTypeDef <Ivl:15> CAST BB01 regmask=[ebx]>
<RefPosition #16 @30 ->#19 RefTypeDef <Ivl:16> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #17 @32 ->#21 RefTypeDef <Ivl:17> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #18 @33 RefTypeUse <Ivl:15> BB01 regmask=[ebx esi edi] last delay regOptional>
<RefPosition #19 @33 RefTypeUse <Ivl:16> BB01 regmask=[ebx esi edi] last>
<RefPosition #20 @34 ->#23 RefTypeDef <Ivl:18> SUB_LO BB01 regmask=[ebx esi edi]>
<RefPosition #21 @35 RefTypeUse <Ivl:17> BB01 regmask=[ebx esi edi] last>
<RefPosition #22 @36 ->#24 RefTypeDef <Ivl:19> SUB_HI BB01 regmask=[ebx esi edi]>
<RefPosition #23 @39 RefTypeUse <Ivl:18> BB01 regmask=[ebx esi edi] last>
<RefPosition #24 @39 RefTypeUse <Ivl:19> BB01 regmask=[ebx esi edi] last>
<RefPosition #25 @40 ->#40 RefTypeDef <Ivl:20> CAST BB01 regmask=[ebx esi edi]>
<RefPosition #26 @42 ->#46 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[ebx esi edi]>
<RefPosition #27 @45 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx] last>
<RefPosition #28 @46 ->#31 RefTypeDef <Ivl:22> CAST BB01 regmask=[ebx]>
<RefPosition #29 @50 ->#32 RefTypeDef <Ivl:23> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #30 @52 ->#34 RefTypeDef <Ivl:24> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #31 @53 RefTypeUse <Ivl:22> BB01 regmask=[ebx esi edi] last delay regOptional>
<RefPosition #32 @53 RefTypeUse <Ivl:23> BB01 regmask=[ebx esi edi] last>
<RefPosition #33 @54 ->#36 RefTypeDef <Ivl:25> SUB_LO BB01 regmask=[ebx esi edi]>
<RefPosition #34 @55 RefTypeUse <Ivl:24> BB01 regmask=[ebx esi edi] last>
<RefPosition #35 @56 ->#37 RefTypeDef <Ivl:26> SUB_HI BB01 regmask=[ebx esi edi]>
<RefPosition #36 @59 RefTypeUse <Ivl:25> BB01 regmask=[ebx esi edi] last>
<RefPosition #37 @59 RefTypeUse <Ivl:26> BB01 regmask=[ebx esi edi] last>
<RefPosition #38 @60 ->#55 RefTypeDef <Ivl:27> CAST BB01 regmask=[ebx esi edi]>
<RefPosition #39 @63 ->#43 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #40 @63 RefTypeUse <Ivl:20> BB01 regmask=[ebx esi edi] last>
<RefPosition #41 @64 ->#42 RefTypeDef <Ivl:28> ARR_INDEX BB01 regmask=[ebx esi edi]>
<RefPosition #42 @67 RefTypeUse <Ivl:28> BB01 regmask=[ebx esi edi] last>
<RefPosition #43 @67 ->#45 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #44 @68 ->#49 RefTypeDef <Ivl:29> ARR_OFFSET BB01 regmask=[ebx esi edi]>
<RefPosition #45 @71 ->#51 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #46 @71 RefTypeUse <Ivl:21> BB01 regmask=[ebx esi edi] last>
<RefPosition #47 @72 ->#50 RefTypeDef <Ivl:30> ARR_INDEX BB01 regmask=[ebx esi edi]>
<RefPosition #48 @75 ->#52 RefTypeDef <Ivl:31 internal> ARR_OFFSET BB01 regmask=[allInt]>
<RefPosition #49 @75 RefTypeUse <Ivl:29> BB01 regmask=[allInt] last>
<RefPosition #50 @75 RefTypeUse <Ivl:30> BB01 regmask=[allInt] last>
<RefPosition #51 @75 ->#54 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #52 @75 RefTypeUse <Ivl:31 internal> ARR_OFFSET BB01 regmask=[allInt] last>
<RefPosition #53 @76 ->#58 RefTypeDef <Ivl:32> ARR_OFFSET BB01 regmask=[allInt]>
<RefPosition #54 @79 ->#60 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #55 @79 RefTypeUse <Ivl:27> BB01 regmask=[ebx esi edi] last>
<RefPosition #56 @80 ->#59 RefTypeDef <Ivl:33> ARR_INDEX BB01 regmask=[ebx esi edi]>
<RefPosition #57 @83 ->#61 RefTypeDef <Ivl:34 internal> ARR_OFFSET BB01 regmask=[allInt]>
<RefPosition #58 @83 RefTypeUse <Ivl:32> BB01 regmask=[allInt] last>
<RefPosition #59 @83 RefTypeUse <Ivl:33> BB01 regmask=[allInt] last>
<RefPosition #60 @83 ->#64 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #61 @83 RefTypeUse <Ivl:34 internal> ARR_OFFSET BB01 regmask=[allInt] last>
<RefPosition #62 @84 ->#63 RefTypeDef <Ivl:35> ARR_OFFSET BB01 regmask=[ebx esi edi]>
<RefPosition #63 @87 RefTypeUse <Ivl:35> BB01 regmask=[ebx esi edi] last>
<RefPosition #64 @87 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #65 @88 ->#66 RefTypeDef <Ivl:36> LEA BB01 regmask=[ebx esi edi]>
<RefPosition #66 @89 RefTypeUse <Ivl:36> BB01 regmask=[ebx esi edi] last>
<RefPosition #67 @90 ->#68 RefTypeDef <Ivl:9 V09> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #68 @95 ->#71 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #69 @95 ->#73 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #70 @103 RefTypeUse <Ivl:8 V08> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #71 @103 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #72 @111 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #73 @111 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #74 @112 ->#75 RefTypeDef <Ivl:37> LEA BB01 regmask=[ebx esi edi]>
<RefPosition #75 @113 RefTypeUse <Ivl:37> BB01 regmask=[ebx esi edi] last>
<RefPosition #76 @114 ->#77 RefTypeDef <Ivl:10 V10> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #77 @117 ->#79 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #78 @118 ->#82 RefTypeDef <Ivl:38> IND BB01 regmask=[ebx esi edi]>
<RefPosition #79 @123 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi] last>
<RefPosition #80 @124 ->#84 RefTypeDef <Ivl:39> IND BB01 regmask=[ebx esi edi]>
<RefPosition #81 @127 ->#86 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax]>
<RefPosition #82 @127 RefTypeUse <Ivl:38> BB01 regmask=[eax] last fixed>
<RefPosition #83 @127 ->#88 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx]>
<RefPosition #84 @127 RefTypeUse <Ivl:39> BB01 regmask=[edx] last fixed>
<RefPosition #85 @129 RefTypeBB BB02 regmask=[]>
<RefPosition #86 @132 ->#98 RefTypeKill <Reg:eax> BB02 regmask=[eax] last>
<RefPosition #87 @132 ->#99 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] last>
<RefPosition #88 @132 ->#100 RefTypeKill <Reg:edx> BB02 regmask=[edx] last>
<RefPosition #89 @132 ->#101 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] last>
<RefPosition #90 @132 ->#102 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] last>
<RefPosition #91 @132 ->#103 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] last>
<RefPosition #92 @132 ->#104 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] last>
<RefPosition #93 @132 ->#105 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] last>
<RefPosition #94 @132 ->#106 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] last>
<RefPosition #95 @132 ->#107 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] last>
<RefPosition #96 @132 ->#108 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] last>
<RefPosition #97 @133 RefTypeBB BB03 regmask=[]>
<RefPosition #98 @136 RefTypeKill <Reg:eax> BB03 regmask=[eax] last>
<RefPosition #99 @136 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] last>
<RefPosition #100 @136 RefTypeKill <Reg:edx> BB03 regmask=[edx] last>
<RefPosition #101 @136 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] last>
<RefPosition #102 @136 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] last>
<RefPosition #103 @136 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] last>
<RefPosition #104 @136 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] last>
<RefPosition #105 @136 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] last>
<RefPosition #106 @136 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] last>
<RefPosition #107 @136 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] last>
<RefPosition #108 @136 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] last>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
<RefPosition #1 @0 ->#72 RefTypeParamDef <Ivl:0 V00> BB03 regmask=[ecx] fixed>
<RefPosition #72 @111 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ebx esi edi] last>
--- V01
<RefPosition #0 @0 ->#39 RefTypeParamDef <Ivl:1 V01> BB03 regmask=[edx] fixed>
<RefPosition #39 @63 ->#43 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #43 @67 ->#45 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #45 @71 ->#51 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #51 @75 ->#54 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #54 @79 ->#60 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] delay>
<RefPosition #60 @83 ->#64 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt]>
<RefPosition #64 @87 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx esi edi] last>
--- V02
--- V03
<RefPosition #2 @0 ->#14 RefTypeParamDef <Ivl:3 V03> BB03 regmask=[ebx esi edi]>
<RefPosition #14 @25 ->#27 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx]>
<RefPosition #27 @45 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax ecx edx ebx] last>
--- V04
--- V05
--- V06
--- V07
<RefPosition #11 @18 ->#69 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #69 @95 ->#73 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #73 @111 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[ebx esi edi] last>
--- V08
<RefPosition #13 @20 ->#70 RefTypeDef <Ivl:8 V08> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #70 @103 RefTypeUse <Ivl:8 V08> LCL_VAR BB01 regmask=[ebx esi edi] last>
--- V09
<RefPosition #67 @90 ->#68 RefTypeDef <Ivl:9 V09> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #68 @95 ->#71 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #71 @103 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[ebx esi edi] last>
--- V10
<RefPosition #76 @114 ->#77 RefTypeDef <Ivl:10 V10> STORE_LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #77 @117 ->#79 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi]>
<RefPosition #79 @123 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[ebx esi edi] last>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
--------------------------------+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |
--------------------------------+----+----+----+
| |V0 a|V1 a|
0.#0 V1 Parm Keep edx | |V0 a|V1 a|
0.#1 V0 Parm Keep ecx | |V0 a|V1 a|
0.#2 V3 Parm Alloc esi | |V0 a|V1 a|----|----|----|V3 a|
0.#3 BB1 PredBB0 | |V0 a|V1 a|----|----|----|V3 a|
6.#4 I11 Def Alloc edi | |V0 a|V1 a|----|----|----|V3 a|I11a|
8.#5 I12 Def Alloc ebx | |V0 a|V1 a|I12a|----|----|V3 a|I11a|
13.#6 I11 Use * Keep edi | |V0 a|V1 a|I12a|----|----|V3 a|I11a|
14.#7 I13 Def Alloc edi | |V0 a|V1 a|I12a|----|----|V3 a|I13a|
15.#8 I12 Use * Keep ebx | |V0 a|V1 a|I12a|----|----|V3 a|I13a|
16.#9 I14 Def Alloc ebx | |V0 a|V1 a|I14a|----|----|V3 a|I13a|
17.#10 I13 Use * Keep edi | |V0 a|V1 a|I14a|----|----|V3 a|I13a|
18.#11 V7 Def Alloc edi | |V0 a|V1 a|I14a|----|----|V3 a|V7 a|
19.#12 I14 Use * Keep ebx | |V0 a|V1 a|I14a|----|----|V3 a|V7 a|
20.#13 V8 Def Alloc ebx | |V0 a|V1 a|V8 a|----|----|V3 a|V7 a|
25.#14 V3 Use Copy eax |V3 a|V0 a|V1 a|V8 a|----|----|V3 a|V7 a|
26.#15 I15 Def Spill ebx |V3 a|V0 a|V1 a| |----|----|V3 a|V7 a|
Steal ebx |V3 a|V0 a|V1 a|I15a|----|----|V3 a|V7 a|
30.#16 I16 Def Spill esi |V3 a|V0 a|V1 a|I15a|----|----| |V7 a|
Steal esi |V3 i|V0 a|V1 a|I15a|----|----|I16a|V7 a|
32.#17 I17 Def Spill ebx |V3 i|V0 a|V1 a| |----|----|I16a|V7 a|
Steal ebx |V3 i|V0 a|V1 a|I17a|----|----|I16a|V7 a|
33.#18 I15 Use *D ReLod NA |V3 i|V0 a|V1 a|I17a|----|----|I16a|V7 a|
NoReg |V3 i|V0 a|V1 a|I17a|----|----|I16a|V7 a|
33.#19 I16 Use * Keep esi |V3 i|V0 a|V1 a|I17a|----|----|I16a|V7 a|
34.#20 I18 Def Alloc esi |V3 i|V0 a|V1 a|I17a|----|----|I18a|V7 a|
35.#21 I17 Use * Keep ebx |V3 i|V0 a|V1 a|I17a|----|----|I18a|V7 a|
36.#22 I19 Def Alloc ebx |V3 i|V0 a|V1 a|I19a|----|----|I18a|V7 a|
39.#23 I18 Use * Keep esi |V3 i|V0 a|V1 a|I19a|----|----|I18a|V7 a|
39.#24 I19 Use * Keep ebx |V3 i|V0 a|V1 a|I19a|----|----|I18a|V7 a|
40.#25 I20 Def Alloc esi |V3 i|V0 a|V1 a| |----|----|I20a|V7 a|
42.#26 C21 Def Alloc ebx |V3 i|V0 a|V1 a|C21a|----|----|I20a|V7 a|
45.#27 V3 Use * ReLod NA |V3 i|V0 a|V1 a|C21a|----|----|I20a|V7 a|
Alloc eax |V3 a|V0 a|V1 a|C21a|----|----|I20a|V7 a|
46.#28 I22 Def Spill ebx | |V0 a|V1 a| |----|----|I20a|V7 a|
Steal ebx | |V0 a|V1 a|I22a|----|----|I20a|V7 a|
50.#29 I23 Def Spill esi | |V0 a|V1 a|I22a|----|----| |V7 a|
Steal esi | |V0 a|V1 a|I22a|----|----|I23a|V7 a|
52.#30 I24 Def Spill ebx | |V0 a|V1 a| |----|----|I23a|V7 a|
Steal ebx | |V0 a|V1 a|I24a|----|----|I23a|V7 a|
53.#31 I22 Use *D ReLod NA | |V0 a|V1 a|I24a|----|----|I23a|V7 a|
NoReg | |V0 a|V1 a|I24a|----|----|I23a|V7 a|
53.#32 I23 Use * Keep esi | |V0 a|V1 a|I24a|----|----|I23a|V7 a|
54.#33 I25 Def Alloc esi | |V0 a|V1 a|I24a|----|----|I25a|V7 a|
55.#34 I24 Use * Keep ebx | |V0 a|V1 a|I24a|----|----|I25a|V7 a|
56.#35 I26 Def Alloc ebx | |V0 a|V1 a|I26a|----|----|I25a|V7 a|
59.#36 I25 Use * Keep esi | |V0 a|V1 a|I26a|----|----|I25a|V7 a|
59.#37 I26 Use * Keep ebx | |V0 a|V1 a|I26a|----|----|I25a|V7 a|
60.#38 I27 Def Alloc esi | |V0 a|V1 a| |----|----|I27a|V7 a|
63.#39 V1 Use Copy ebx | |V0 a|V1 a|V1 a|----|----|I27a|V7 a|
63.#40 I20 Use * ReLod NA | |V0 a|V1 a|V1 a|----|----|I27a|V7 a|
Spill esi | |V0 a|V1 a|V1 a|----|----| |V7 a|
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |ebx |esp |ebp |esi |edi |
--------------------------------+----+----+----+----+----+----+----+----+
Steal esi | |V0 a|V1 a|V1 a|----|----|I20a|V7 a|
64.#41 I28 Def Alloc esi | |V0 a|V1 a|V1 a|----|----|I28a|V7 a|
67.#42 I28 Use * Keep esi | |V0 a|V1 a|V1 a|----|----|I28a|V7 a|
67.#43 V1 Use Copy ebx | |V0 a|V1 a|V1 a|----|----|I28a|V7 a|
68.#44 I29 Def Alloc esi | |V0 a|V1 a|V1 a|----|----|I29a|V7 a|
71.#45 V1 Use Copy ebx | |V0 a|V1 a|V1 a|----|----|I29a|V7 a|
71.#46 C21 Use * ReLod NA | |V0 a|V1 a|V1 a|----|----|I29a|V7 a|
Spill esi | |V0 a|V1 a|V1 a|----|----| |V7 a|
Steal esi | |V0 a|V1 a|V1 a|----|----|C21a|V7 a|
72.#47 I30 Def Alloc esi | |V0 a|V1 a|V1 a|----|----|I30a|V7 a|
75.#48 I31 Def Alloc eax |I31a|V0 a|V1 a|V1 a|----|----|I30a|V7 a|
75.#49 I29 Use * ReLod NA |I31a|V0 a|V1 a|V1 a|----|----|I30a|V7 a|
Alloc ebx |I31a|V0 a|V1 a|I29a|----|----|I30a|V7 a|
75.#50 I30 Use * Keep esi |I31a|V0 a|V1 a|I29a|----|----|I30a|V7 a|
75.#51 V1 Use Keep edx |I31a|V0 a|V1 a|I29a|----|----|I30a|V7 a|
75.#52 I31 Use * Keep eax |I31a|V0 a|V1 a|I29a|----|----|I30a|V7 a|
76.#53 I32 Def Alloc eax |I32a|V0 a|V1 a| |----|----| |V7 a|
79.#54 V1 Use Copy ebx |I32a|V0 a|V1 a|V1 a|----|----| |V7 a|
79.#55 I27 Use * ReLod NA |I32a|V0 a|V1 a|V1 a|----|----| |V7 a|
Alloc esi |I32a|V0 a|V1 a|V1 a|----|----|I27a|V7 a|
80.#56 I33 Def Alloc esi |I32a|V0 a|V1 a|V1 a|----|----|I33a|V7 a|
83.#57 I34 Def Alloc ebx |I32a|V0 a|V1 a|I34a|----|----|I33a|V7 a|
83.#58 I32 Use * Keep eax |I32a|V0 a|V1 a|I34a|----|----|I33a|V7 a|
83.#59 I33 Use * Keep esi |I32a|V0 a|V1 a|I34a|----|----|I33a|V7 a|
83.#60 V1 Use Keep edx |I32a|V0 a|V1 a|I34a|----|----|I33a|V7 a|
83.#61 I34 Use * Keep ebx |I32a|V0 a|V1 a|I34a|----|----|I33a|V7 a|
84.#62 I35 Def Alloc esi | |V0 a|V1 a| |----|----|I35a|V7 a|
87.#63 I35 Use * Keep esi | |V0 a|V1 a| |----|----|I35a|V7 a|
87.#64 V1 Use * Copy ebx | |V0 a|V1 a|V1 a|----|----|I35a|V7 a|
88.#65 I36 Def Alloc esi | |V0 a| | |----|----|I36a|V7 a|
89.#66 I36 Use * Keep esi | |V0 a| | |----|----|I36a|V7 a|
90.#67 V9 Def Alloc esi | |V0 a| | |----|----|V9 a|V7 a|
95.#68 V9 Use Keep esi | |V0 a| | |----|----|V9 a|V7 a|
95.#69 V7 Use Keep edi | |V0 a| | |----|----|V9 a|V7 a|
103.#70 V8 Use * ReLod NA | |V0 a| | |----|----|V9 a|V7 a|
Alloc ebx | |V0 a| |V8 a|----|----|V9 a|V7 a|
103.#71 V9 Use * Keep esi | |V0 a| |V8 a|----|----|V9 a|V7 a|
111.#72 V0 Use * Copy esi | |V0 a| | |----|----|V0 a|V7 a|
111.#73 V7 Use * Keep edi | |V0 a| | |----|----|V0 a|V7 a|
112.#74 I37 Def Alloc esi | | | | |----|----|I37a| |
113.#75 I37 Use * Keep esi | | | | |----|----|I37a| |
114.#76 V10 Def Alloc esi | | | | |----|----|V10a| |
117.#77 V10 Use Keep esi | | | | |----|----|V10a| |
118.#78 I38 Def DUconflict | | | | |----|----|V10a| |
case #2 use useRegAssignment | | | | |----|----|V10a| |
Alloc eax |I38a| | | |----|----|V10a| |
123.#79 V10 Use * Keep esi |I38a| | | |----|----|V10a| |
124.#80 I39 Def DUconflict |I38a| | | |----|----| | |
case #2 use useRegAssignment |I38a| | | |----|----| | |
Alloc edx |I38a| |I39a| |----|----| | |
127.#81 eax Fixd Keep eax |I38a| |I39a| |----|----| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |ebx |esp |ebp |esi |edi |
--------------------------------+----+----+----+----+----+----+----+----+
127.#82 I38 Use * Keep eax |I38a| |I39a| |----|----| | |
127.#83 edx Fixd Keep edx |I38a| |I39a| |----|----| | |
127.#84 I39 Use * Keep edx |I38a| |I39a| |----|----| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |ebx |esp |ebp |esi |edi |
--------------------------------+----+----+----+----+----+----+----+----+
129.#85 BB2 PredBB1 | | | | |----|----| | |
132.#86 eax Kill Keep eax | | | | |----|----| | |
132.#87 ecx Kill Keep ecx | | | | |----|----| | |
132.#88 edx Kill Keep edx | | | | |----|----| | |
132.#89 mm0 Kill Keep mm0 | | | | |----|----| | |
132.#90 mm1 Kill Keep mm1 | | | | |----|----| | |
132.#91 mm2 Kill Keep mm2 | | | | |----|----| | |
132.#92 mm3 Kill Keep mm3 | | | | |----|----| | |
132.#93 mm4 Kill Keep mm4 | | | | |----|----| | |
132.#94 mm5 Kill Keep mm5 | | | | |----|----| | |
132.#95 mm6 Kill Keep mm6 | | | | |----|----| | |
132.#96 mm7 Kill Keep mm7 | | | | |----|----| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |ebx |esp |ebp |esi |edi |
--------------------------------+----+----+----+----+----+----+----+----+
133.#97 BB3 PredBB2 | | | | |----|----| | |
136.#98 eax Kill Keep eax | | | | |----|----| | |
136.#99 ecx Kill Keep ecx | | | | |----|----| | |
136.#100 edx Kill Keep edx | | | | |----|----| | |
136.#101 mm0 Kill Keep mm0 | | | | |----|----| | |
136.#102 mm1 Kill Keep mm1 | | | | |----|----| | |
136.#103 mm2 Kill Keep mm2 | | | | |----|----| | |
136.#104 mm3 Kill Keep mm3 | | | | |----|----| | |
136.#105 mm4 Kill Keep mm4 | | | | |----|----| | |
136.#106 mm5 Kill Keep mm5 | | | | |----|----| | |
136.#107 mm6 Kill Keep mm6 | | | | |----|----| | |
136.#108 mm7 Kill Keep mm7 | | | | |----|----| | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 ->#39 RefTypeParamDef <Ivl:1 V01> BB03 regmask=[edx] fixed>
<RefPosition #1 @0 ->#72 RefTypeParamDef <Ivl:0 V00> BB03 regmask=[ecx] fixed>
<RefPosition #2 @0 ->#14 RefTypeParamDef <Ivl:3 V03> BB03 regmask=[esi]>
<RefPosition #3 @0 RefTypeBB BB01 regmask=[]>
<RefPosition #4 @6 ->#6 RefTypeDef <Ivl:11> LCL_VAR BB01 regmask=[edi]>
<RefPosition #5 @8 ->#8 RefTypeDef <Ivl:12> LCL_VAR BB01 regmask=[ebx]>
<RefPosition #6 @13 RefTypeUse <Ivl:11> BB01 regmask=[edi] last>
<RefPosition #7 @14 ->#10 RefTypeDef <Ivl:13> SUB_LO BB01 regmask=[edi]>
<RefPosition #8 @15 RefTypeUse <Ivl:12> BB01 regmask=[ebx] last>
<RefPosition #9 @16 ->#12 RefTypeDef <Ivl:14> SUB_HI BB01 regmask=[ebx]>
<RefPosition #10 @17 RefTypeUse <Ivl:13> BB01 regmask=[edi] last>
<RefPosition #11 @18 ->#69 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[edi]>
<RefPosition #12 @19 RefTypeUse <Ivl:14> BB01 regmask=[ebx] last>
<RefPosition #13 @20 ->#70 RefTypeDef <Ivl:8 V08> STORE_LCL_VAR BB01 regmask=[ebx] spillAfter>
<RefPosition #14 @25 ->#27 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax] spillAfter copy>
<RefPosition #15 @26 ->#18 RefTypeDef <Ivl:15> CAST BB01 regmask=[ebx] spillAfter>
<RefPosition #16 @30 ->#19 RefTypeDef <Ivl:16> LCL_VAR BB01 regmask=[esi]>
<RefPosition #17 @32 ->#21 RefTypeDef <Ivl:17> LCL_VAR BB01 regmask=[ebx]>
<RefPosition #18 @33 RefTypeUse <Ivl:15> BB01 regmask=[] last delay regOptional>
<RefPosition #19 @33 RefTypeUse <Ivl:16> BB01 regmask=[esi] last>
<RefPosition #20 @34 ->#23 RefTypeDef <Ivl:18> SUB_LO BB01 regmask=[esi]>
<RefPosition #21 @35 RefTypeUse <Ivl:17> BB01 regmask=[ebx] last>
<RefPosition #22 @36 ->#24 RefTypeDef <Ivl:19> SUB_HI BB01 regmask=[ebx]>
<RefPosition #23 @39 RefTypeUse <Ivl:18> BB01 regmask=[esi] last>
<RefPosition #24 @39 RefTypeUse <Ivl:19> BB01 regmask=[ebx] last>
<RefPosition #25 @40 ->#40 RefTypeDef <Ivl:20> CAST BB01 regmask=[esi] spillAfter>
<RefPosition #26 @42 ->#46 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[ebx] spillAfter>
<RefPosition #27 @45 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax] last reload>
<RefPosition #28 @46 ->#31 RefTypeDef <Ivl:22> CAST BB01 regmask=[ebx] spillAfter>
<RefPosition #29 @50 ->#32 RefTypeDef <Ivl:23> LCL_VAR BB01 regmask=[esi]>
<RefPosition #30 @52 ->#34 RefTypeDef <Ivl:24> LCL_VAR BB01 regmask=[ebx]>
<RefPosition #31 @53 RefTypeUse <Ivl:22> BB01 regmask=[] last delay regOptional>
<RefPosition #32 @53 RefTypeUse <Ivl:23> BB01 regmask=[esi] last>
<RefPosition #33 @54 ->#36 RefTypeDef <Ivl:25> SUB_LO BB01 regmask=[esi]>
<RefPosition #34 @55 RefTypeUse <Ivl:24> BB01 regmask=[ebx] last>
<RefPosition #35 @56 ->#37 RefTypeDef <Ivl:26> SUB_HI BB01 regmask=[ebx]>
<RefPosition #36 @59 RefTypeUse <Ivl:25> BB01 regmask=[esi] last>
<RefPosition #37 @59 RefTypeUse <Ivl:26> BB01 regmask=[ebx] last>
<RefPosition #38 @60 ->#55 RefTypeDef <Ivl:27> CAST BB01 regmask=[esi] spillAfter>
<RefPosition #39 @63 ->#43 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy delay>
<RefPosition #40 @63 RefTypeUse <Ivl:20> BB01 regmask=[esi] last reload>
<RefPosition #41 @64 ->#42 RefTypeDef <Ivl:28> ARR_INDEX BB01 regmask=[esi]>
<RefPosition #42 @67 RefTypeUse <Ivl:28> BB01 regmask=[esi] last>
<RefPosition #43 @67 ->#45 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy>
<RefPosition #44 @68 ->#49 RefTypeDef <Ivl:29> ARR_OFFSET BB01 regmask=[esi] spillAfter>
<RefPosition #45 @71 ->#51 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy delay>
<RefPosition #46 @71 RefTypeUse <Ivl:21> BB01 regmask=[esi] last reload>
<RefPosition #47 @72 ->#50 RefTypeDef <Ivl:30> ARR_INDEX BB01 regmask=[esi]>
<RefPosition #48 @75 ->#52 RefTypeDef <Ivl:31 internal> ARR_OFFSET BB01 regmask=[eax]>
<RefPosition #49 @75 RefTypeUse <Ivl:29> BB01 regmask=[ebx] last reload>
<RefPosition #50 @75 RefTypeUse <Ivl:30> BB01 regmask=[esi] last>
<RefPosition #51 @75 ->#54 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[edx]>
<RefPosition #52 @75 RefTypeUse <Ivl:31 internal> ARR_OFFSET BB01 regmask=[eax] last>
<RefPosition #53 @76 ->#58 RefTypeDef <Ivl:32> ARR_OFFSET BB01 regmask=[eax]>
<RefPosition #54 @79 ->#60 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy delay>
<RefPosition #55 @79 RefTypeUse <Ivl:27> BB01 regmask=[esi] last reload>
<RefPosition #56 @80 ->#59 RefTypeDef <Ivl:33> ARR_INDEX BB01 regmask=[esi]>
<RefPosition #57 @83 ->#61 RefTypeDef <Ivl:34 internal> ARR_OFFSET BB01 regmask=[ebx]>
<RefPosition #58 @83 RefTypeUse <Ivl:32> BB01 regmask=[eax] last>
<RefPosition #59 @83 RefTypeUse <Ivl:33> BB01 regmask=[esi] last>
<RefPosition #60 @83 ->#64 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[edx]>
<RefPosition #61 @83 RefTypeUse <Ivl:34 internal> ARR_OFFSET BB01 regmask=[ebx] last>
<RefPosition #62 @84 ->#63 RefTypeDef <Ivl:35> ARR_OFFSET BB01 regmask=[esi]>
<RefPosition #63 @87 RefTypeUse <Ivl:35> BB01 regmask=[esi] last>
<RefPosition #64 @87 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] last copy>
<RefPosition #65 @88 ->#66 RefTypeDef <Ivl:36> LEA BB01 regmask=[esi]>
<RefPosition #66 @89 RefTypeUse <Ivl:36> BB01 regmask=[esi] last>
<RefPosition #67 @90 ->#68 RefTypeDef <Ivl:9 V09> STORE_LCL_VAR BB01 regmask=[esi]>
<RefPosition #68 @95 ->#71 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[esi]>
<RefPosition #69 @95 ->#73 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[edi]>
<RefPosition #70 @103 RefTypeUse <Ivl:8 V08> LCL_VAR BB01 regmask=[ebx] last reload>
<RefPosition #71 @103 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[esi] last>
<RefPosition #72 @111 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[esi] last copy>
<RefPosition #73 @111 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[edi] last>
<RefPosition #74 @112 ->#75 RefTypeDef <Ivl:37> LEA BB01 regmask=[esi]>
<RefPosition #75 @113 RefTypeUse <Ivl:37> BB01 regmask=[esi] last>
<RefPosition #76 @114 ->#77 RefTypeDef <Ivl:10 V10> STORE_LCL_VAR BB01 regmask=[esi]>
<RefPosition #77 @117 ->#79 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[esi]>
<RefPosition #78 @118 ->#82 RefTypeDef <Ivl:38> IND BB01 regmask=[eax]>
<RefPosition #79 @123 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[esi] last>
<RefPosition #80 @124 ->#84 RefTypeDef <Ivl:39> IND BB01 regmask=[edx]>
<RefPosition #81 @127 ->#86 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax]>
<RefPosition #82 @127 RefTypeUse <Ivl:38> BB01 regmask=[eax] last fixed>
<RefPosition #83 @127 ->#88 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx]>
<RefPosition #84 @127 RefTypeUse <Ivl:39> BB01 regmask=[edx] last fixed>
<RefPosition #85 @129 RefTypeBB BB02 regmask=[]>
<RefPosition #86 @132 ->#98 RefTypeKill <Reg:eax> BB02 regmask=[eax] last>
<RefPosition #87 @132 ->#99 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] last>
<RefPosition #88 @132 ->#100 RefTypeKill <Reg:edx> BB02 regmask=[edx] last>
<RefPosition #89 @132 ->#101 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] last>
<RefPosition #90 @132 ->#102 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] last>
<RefPosition #91 @132 ->#103 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] last>
<RefPosition #92 @132 ->#104 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] last>
<RefPosition #93 @132 ->#105 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] last>
<RefPosition #94 @132 ->#106 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] last>
<RefPosition #95 @132 ->#107 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] last>
<RefPosition #96 @132 ->#108 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] last>
<RefPosition #97 @133 RefTypeBB BB03 regmask=[]>
<RefPosition #98 @136 RefTypeKill <Reg:eax> BB03 regmask=[eax] last>
<RefPosition #99 @136 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] last>
<RefPosition #100 @136 RefTypeKill <Reg:edx> BB03 regmask=[edx] last>
<RefPosition #101 @136 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] last>
<RefPosition #102 @136 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] last>
<RefPosition #103 @136 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] last>
<RefPosition #104 @136 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] last>
<RefPosition #105 @136 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] last>
<RefPosition #106 @136 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] last>
<RefPosition #107 @136 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] last>
<RefPosition #108 @136 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] last>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00
<RefPosition #1 @0 ->#72 RefTypeParamDef <Ivl:0 V00> BB03 regmask=[ecx] fixed>
<RefPosition #72 @111 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[esi] last copy>
--- V01
<RefPosition #0 @0 ->#39 RefTypeParamDef <Ivl:1 V01> BB03 regmask=[edx] fixed>
<RefPosition #39 @63 ->#43 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy delay>
<RefPosition #43 @67 ->#45 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy>
<RefPosition #45 @71 ->#51 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy delay>
<RefPosition #51 @75 ->#54 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[edx]>
<RefPosition #54 @79 ->#60 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy delay>
<RefPosition #60 @83 ->#64 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[edx]>
<RefPosition #64 @87 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] last copy>
--- V02
--- V03
<RefPosition #2 @0 ->#14 RefTypeParamDef <Ivl:3 V03> BB03 regmask=[esi]>
<RefPosition #14 @25 ->#27 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax] spillAfter copy>
<RefPosition #27 @45 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax] last reload>
--- V04
--- V05
--- V06
--- V07
<RefPosition #11 @18 ->#69 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[edi]>
<RefPosition #69 @95 ->#73 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[edi]>
<RefPosition #73 @111 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[edi] last>
--- V08
<RefPosition #13 @20 ->#70 RefTypeDef <Ivl:8 V08> STORE_LCL_VAR BB01 regmask=[ebx] spillAfter>
<RefPosition #70 @103 RefTypeUse <Ivl:8 V08> LCL_VAR BB01 regmask=[ebx] last reload>
--- V09
<RefPosition #67 @90 ->#68 RefTypeDef <Ivl:9 V09> STORE_LCL_VAR BB01 regmask=[esi]>
<RefPosition #68 @95 ->#71 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[esi]>
<RefPosition #71 @103 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[esi] last>
--- V10
<RefPosition #76 @114 ->#77 RefTypeDef <Ivl:10 V10> STORE_LCL_VAR BB01 regmask=[esi]>
<RefPosition #77 @117 ->#79 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[esi]>
<RefPosition #79 @123 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[esi] last>
Active intervals at end of allocation:
------------------------
WRITING BACK ASSIGNMENTS
------------------------
BB01 [000..02A) (return), preds={} succs={}
<RefPosition #3 @0 RefTypeBB BB01 regmask=[]>
current : <RefPosition #4 @6 ->#6 RefTypeDef <Ivl:11> LCL_VAR BB01 regmask=[edi]>
N005. t5 = V05 MEM
curr = 6 mapped = 5
current : <RefPosition #5 @8 ->#8 RefTypeDef <Ivl:12> LCL_VAR BB01 regmask=[ebx]>
N007. t7 = V06 MEM
curr = 8 mapped = 7
current : <RefPosition #6 @13 RefTypeUse <Ivl:11> BB01 regmask=[edi] last>
No tree node to write back to
current : <RefPosition #7 @14 ->#10 RefTypeDef <Ivl:13> SUB_LO BB01 regmask=[edi]>
N013. t13 = -Lo
curr = 14 mapped = 13
current : <RefPosition #8 @15 RefTypeUse <Ivl:12> BB01 regmask=[ebx] last>
No tree node to write back to
current : <RefPosition #9 @16 ->#12 RefTypeDef <Ivl:14> SUB_HI BB01 regmask=[ebx]>
N015. t15 = -Hi
curr = 16 mapped = 15
current : <RefPosition #10 @17 RefTypeUse <Ivl:13> BB01 regmask=[edi] last>
No tree node to write back to
current : <RefPosition #11 @18 ->#69 RefTypeDef <Ivl:7 V07> STORE_LCL_VAR BB01 regmask=[edi]>
N017. V07(L7)
curr = 18 mapped = 17
current : <RefPosition #12 @19 RefTypeUse <Ivl:14> BB01 regmask=[ebx] last>
No tree node to write back to
current : <RefPosition #13 @20 ->#70 RefTypeDef <Ivl:8 V08> STORE_LCL_VAR BB01 regmask=[ebx] spillAfter>
N019. V08(L8)
curr = 20 mapped = 19
current : <RefPosition #14 @25 ->#27 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax] spillAfter copy>
N023. V03(L3)
curr = 25 mapped = 23
current : <RefPosition #15 @26 ->#18 RefTypeDef <Ivl:15> CAST BB01 regmask=[ebx] spillAfter>
Max spill for int is 1
N025. t25 = cast
curr = 26 mapped = 25
current : <RefPosition #16 @30 ->#19 RefTypeDef <Ivl:16> LCL_VAR BB01 regmask=[esi]>
N029. t29 = V05 MEM
curr = 30 mapped = 29
current : <RefPosition #17 @32 ->#21 RefTypeDef <Ivl:17> LCL_VAR BB01 regmask=[ebx]>
N031. t31 = V06 MEM
curr = 32 mapped = 31
current : <RefPosition #18 @33 RefTypeUse <Ivl:15> BB01 regmask=[] last delay regOptional>
Max spill for int is 1
No tree node to write back to
current : <RefPosition #19 @33 RefTypeUse <Ivl:16> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #20 @34 ->#23 RefTypeDef <Ivl:18> SUB_LO BB01 regmask=[esi]>
N033. t33 = -Lo (Rev)
curr = 34 mapped = 33
current : <RefPosition #21 @35 RefTypeUse <Ivl:17> BB01 regmask=[ebx] last>
No tree node to write back to
current : <RefPosition #22 @36 ->#24 RefTypeDef <Ivl:19> SUB_HI BB01 regmask=[ebx]>
N035. t35 = -Hi
curr = 36 mapped = 35
current : <RefPosition #23 @39 RefTypeUse <Ivl:18> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #24 @39 RefTypeUse <Ivl:19> BB01 regmask=[ebx] last>
No tree node to write back to
current : <RefPosition #25 @40 ->#40 RefTypeDef <Ivl:20> CAST BB01 regmask=[esi] spillAfter>
Max spill for int is 1
N039. t39 = cast_ovfl
curr = 40 mapped = 39
current : <RefPosition #26 @42 ->#46 RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[ebx] spillAfter>
Max spill for int is 2
N041. t41 = const 0 REG NA
curr = 42 mapped = 41
current : <RefPosition #27 @45 RefTypeUse <Ivl:3 V03> LCL_VAR BB01 regmask=[eax] last reload>
N043. V03(L3)
curr = 45 mapped = 43
current : <RefPosition #28 @46 ->#31 RefTypeDef <Ivl:22> CAST BB01 regmask=[ebx] spillAfter>
Max spill for int is 3
N045. t45 = cast
curr = 46 mapped = 45
current : <RefPosition #29 @50 ->#32 RefTypeDef <Ivl:23> LCL_VAR BB01 regmask=[esi]>
N049. t49* = V05 MEM
curr = 50 mapped = 49
current : <RefPosition #30 @52 ->#34 RefTypeDef <Ivl:24> LCL_VAR BB01 regmask=[ebx]>
N051. t51 = V06 MEM
curr = 52 mapped = 51
current : <RefPosition #31 @53 RefTypeUse <Ivl:22> BB01 regmask=[] last delay regOptional>
Max spill for int is 3
No tree node to write back to
current : <RefPosition #32 @53 RefTypeUse <Ivl:23> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #33 @54 ->#36 RefTypeDef <Ivl:25> SUB_LO BB01 regmask=[esi]>
N053. t53 = -Lo (Rev)
curr = 54 mapped = 53
current : <RefPosition #34 @55 RefTypeUse <Ivl:24> BB01 regmask=[ebx] last>
No tree node to write back to
current : <RefPosition #35 @56 ->#37 RefTypeDef <Ivl:26> SUB_HI BB01 regmask=[ebx]>
N055. t55 = -Hi
curr = 56 mapped = 55
current : <RefPosition #36 @59 RefTypeUse <Ivl:25> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #37 @59 RefTypeUse <Ivl:26> BB01 regmask=[ebx] last>
No tree node to write back to
current : <RefPosition #38 @60 ->#55 RefTypeDef <Ivl:27> CAST BB01 regmask=[esi] spillAfter>
Max spill for int is 3
N059. t59 = cast_ovfl
curr = 60 mapped = 59
current : <RefPosition #39 @63 ->#43 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy delay>
N021. V01(L1)
curr = 63 mapped = 21
current : <RefPosition #40 @63 RefTypeUse <Ivl:20> BB01 regmask=[esi] last reload>
Max spill for int is 3
No tree node to write back to
current : <RefPosition #41 @64 ->#42 RefTypeDef <Ivl:28> ARR_INDEX BB01 regmask=[esi]>
N063. t63 = arrMDIdx[i, , ]
curr = 64 mapped = 63
current : <RefPosition #42 @67 RefTypeUse <Ivl:28> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #43 @67 ->#45 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy>
N065. V01(L1)
curr = 67 mapped = 65
current : <RefPosition #44 @68 ->#49 RefTypeDef <Ivl:29> ARR_OFFSET BB01 regmask=[esi] spillAfter>
Max spill for int is 3
N067. t67 = arrMDOffs[i, , ]
curr = 68 mapped = 67
current : <RefPosition #45 @71 ->#51 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy delay>
N069. V01(L1)
curr = 71 mapped = 69
current : <RefPosition #46 @71 RefTypeUse <Ivl:21> BB01 regmask=[esi] last reload>
Max spill for int is 3
No tree node to write back to
current : <RefPosition #47 @72 ->#50 RefTypeDef <Ivl:30> ARR_INDEX BB01 regmask=[esi]>
N071. t71 = arrMDIdx[*,j, ]
curr = 72 mapped = 71
current : <RefPosition #48 @75 ->#52 RefTypeDef <Ivl:31 internal> ARR_OFFSET BB01 regmask=[eax]>
N075. t75 = arrMDOffs[*,j, ]
curr = 75 mapped = 75 internal
current : <RefPosition #49 @75 RefTypeUse <Ivl:29> BB01 regmask=[ebx] last reload>
Max spill for int is 3
No tree node to write back to
current : <RefPosition #50 @75 RefTypeUse <Ivl:30> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #51 @75 ->#54 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[edx]>
N073. V01(L1)
curr = 75 mapped = 73
current : <RefPosition #52 @75 RefTypeUse <Ivl:31 internal> ARR_OFFSET BB01 regmask=[eax] last>
N075. t75 = arrMDOffs[*,j, ]
curr = 75 mapped = 75 internal
current : <RefPosition #53 @76 ->#58 RefTypeDef <Ivl:32> ARR_OFFSET BB01 regmask=[eax]>
N075. t75 = arrMDOffs[*,j, ]
curr = 76 mapped = 75
current : <RefPosition #54 @79 ->#60 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] copy delay>
N077. V01(L1)
curr = 79 mapped = 77
current : <RefPosition #55 @79 RefTypeUse <Ivl:27> BB01 regmask=[esi] last reload>
Max spill for int is 3
No tree node to write back to
current : <RefPosition #56 @80 ->#59 RefTypeDef <Ivl:33> ARR_INDEX BB01 regmask=[esi]>
N079. t79 = arrMDIdx[*,*,k]
curr = 80 mapped = 79
current : <RefPosition #57 @83 ->#61 RefTypeDef <Ivl:34 internal> ARR_OFFSET BB01 regmask=[ebx]>
N083. t83 = arrMDOffs[*,*,k]
curr = 83 mapped = 83 internal
current : <RefPosition #58 @83 RefTypeUse <Ivl:32> BB01 regmask=[eax] last>
No tree node to write back to
current : <RefPosition #59 @83 RefTypeUse <Ivl:33> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #60 @83 ->#64 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[edx]>
N081. V01(L1)
curr = 83 mapped = 81
current : <RefPosition #61 @83 RefTypeUse <Ivl:34 internal> ARR_OFFSET BB01 regmask=[ebx] last>
N083. t83 = arrMDOffs[*,*,k]
curr = 83 mapped = 83 internal
current : <RefPosition #62 @84 ->#63 RefTypeDef <Ivl:35> ARR_OFFSET BB01 regmask=[esi]>
N083. t83 = arrMDOffs[*,*,k]
curr = 84 mapped = 83
current : <RefPosition #63 @87 RefTypeUse <Ivl:35> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #64 @87 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[ebx] last copy>
N085. V01(L1)
curr = 87 mapped = 85
current : <RefPosition #65 @88 ->#66 RefTypeDef <Ivl:36> LEA BB01 regmask=[esi]>
N087. t87 = lea(b+(i*8)+32)(Rev)
curr = 88 mapped = 87
current : <RefPosition #66 @89 RefTypeUse <Ivl:36> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #67 @90 ->#68 RefTypeDef <Ivl:9 V09> STORE_LCL_VAR BB01 regmask=[esi]>
N089. V09(L9)
curr = 90 mapped = 89
current : <RefPosition #68 @95 ->#71 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[esi]>
N091. V09(L9)
curr = 95 mapped = 91
current : <RefPosition #69 @95 ->#73 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[edi]>
N093. V07(L7)
curr = 95 mapped = 93
current : <RefPosition #70 @103 RefTypeUse <Ivl:8 V08> LCL_VAR BB01 regmask=[ebx] last reload>
N097. V08(L8)
curr = 103 mapped = 97
current : <RefPosition #71 @103 RefTypeUse <Ivl:9 V09> LCL_VAR BB01 regmask=[esi] last>
N099. V09(L9)
curr = 103 mapped = 99
current : <RefPosition #72 @111 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[esi] last copy>
N107. V00(L0)
curr = 111 mapped = 107
current : <RefPosition #73 @111 RefTypeUse <Ivl:7 V07> LCL_VAR BB01 regmask=[edi] last>
N109. V07(L7)
curr = 111 mapped = 109
current : <RefPosition #74 @112 ->#75 RefTypeDef <Ivl:37> LEA BB01 regmask=[esi]>
N111. t111 = lea(b+(i*8)+0)
curr = 112 mapped = 111
current : <RefPosition #75 @113 RefTypeUse <Ivl:37> BB01 regmask=[esi] last>
No tree node to write back to
current : <RefPosition #76 @114 ->#77 RefTypeDef <Ivl:10 V10> STORE_LCL_VAR BB01 regmask=[esi]>
N113. V10(L10)
curr = 114 mapped = 113
current : <RefPosition #77 @117 ->#79 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[esi]>
N115. V10(L10)
curr = 117 mapped = 115
current : <RefPosition #78 @118 ->#82 RefTypeDef <Ivl:38> IND BB01 regmask=[eax]>
N117. t117 = indir
curr = 118 mapped = 117
current : <RefPosition #79 @123 RefTypeUse <Ivl:10 V10> LCL_VAR BB01 regmask=[esi] last>
N119. V10(L10)
curr = 123 mapped = 119
current : <RefPosition #80 @124 ->#84 RefTypeDef <Ivl:39> IND BB01 regmask=[edx]>
N123. t123 = indir
curr = 124 mapped = 123
current : <RefPosition #81 @127 ->#86 RefTypeFixedReg <Reg:eax> BB01 regmask=[eax]>
current : <RefPosition #82 @127 RefTypeUse <Ivl:38> BB01 regmask=[eax] last fixed>
No tree node to write back to
current : <RefPosition #83 @127 ->#88 RefTypeFixedReg <Reg:edx> BB01 regmask=[edx]>
current : <RefPosition #84 @127 RefTypeUse <Ivl:39> BB01 regmask=[edx] last fixed>
No tree node to write back to
BB02 [???..???) (throw), preds={} succs={}
<RefPosition #85 @129 RefTypeBB BB02 regmask=[]>
current : <RefPosition #86 @132 ->#98 RefTypeKill <Reg:eax> BB02 regmask=[eax] last>
current : <RefPosition #87 @132 ->#99 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] last>
current : <RefPosition #88 @132 ->#100 RefTypeKill <Reg:edx> BB02 regmask=[edx] last>
current : <RefPosition #89 @132 ->#101 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] last>
current : <RefPosition #90 @132 ->#102 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] last>
current : <RefPosition #91 @132 ->#103 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] last>
current : <RefPosition #92 @132 ->#104 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] last>
current : <RefPosition #93 @132 ->#105 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] last>
current : <RefPosition #94 @132 ->#106 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] last>
current : <RefPosition #95 @132 ->#107 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] last>
current : <RefPosition #96 @132 ->#108 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] last>
BB03 [???..???) (throw), preds={} succs={}
<RefPosition #97 @133 RefTypeBB BB03 regmask=[]>
current : <RefPosition #98 @136 RefTypeKill <Reg:eax> BB03 regmask=[eax] last>
current : <RefPosition #99 @136 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] last>
current : <RefPosition #100 @136 RefTypeKill <Reg:edx> BB03 regmask=[edx] last>
current : <RefPosition #101 @136 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] last>
current : <RefPosition #102 @136 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] last>
current : <RefPosition #103 @136 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] last>
current : <RefPosition #104 @136 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] last>
current : <RefPosition #105 @136 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] last>
current : <RefPosition #106 @136 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] last>
current : <RefPosition #107 @136 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] last>
current : <RefPosition #108 @136 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] last>
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Prior to Resolution
BB01 use def in out
{V00 V01 V03}
{V07 V08 V09 V10}
{V00 V01 V03}
{}
Var=Reg beg of BB01: V01=edx V00=ecx V03=esi
Var=Reg end of BB01: none
BB02 use def in out
{}
{}
{}
{}
Var=Reg beg of BB02: none
Var=Reg end of BB02: none
BB03 use def in out
{}
{}
{}
{}
Var=Reg beg of BB03: none
Var=Reg end of BB03: none
RESOLVING EDGES
Set V00 argument initial register to ecx
Set V01 argument initial register to edx
Set V03 argument initial register to esi
Trees after linear scan register allocator (LSRA)
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..02A) (return), preds={} succs={}
N003 ( 17, 22) [000020] ------------ il_offset void IL offset: 0 REG NA
N005 ( 3, 2) [000039] ------------ t39 = lclVar int V05 rat0 REG edi $100
N007 (???,???) [000081] ------------ t81 = lclVar int V06 rat1 REG ebx
N009 ( 3, 10) [000040] ------------ t40 = const int 1 REG NA
N011 (???,???) [000083] ------------ t83 = const int 0 REG NA
/--* t39 int
+--* t40 int
N013 ( 10, 16) [000038] ------------ t38 = * -Lo int REG edi
/--* t81 int
+--* t83 int
N015 (???,???) [000085] ------------ t85 = * -Hi int REG ebx
/--* t38 int
N017 ( 17, 22) [000036] DA---------- * st.lclVar int V07 rat2 edi REG edi RV
/--* t85 int
N019 (???,???) [000087] D----------- * st.lclVar int V08 rat3 REG NA
N021 ( 1, 1) [000062] ------------ t62 = lclVar ref V01 arg1 u:2 edx REG edx RV $c0
/--* t62 ref
[000132] ------------ t132 = * copy ref REG ebx
N023 ( 3, 2) [000054] -----------Z t54 = lclVar int V03 arg3 u:2 esi REG esi RV $140
/--* t54 int
[000130] ------------ t130 = * copy int REG eax
/--* t130 int
N025 ( 4, 4) [000053] -----------Z t53 = * cast int <- ubyte <- int REG ebx $240
N027 (???,???) [000088] ------------ t88 = const int 0 REG NA
N029 ( 3, 2) [000051] ------------ t51 = lclVar int V05 rat0 REG esi $100
N031 (???,???) [000090] ------------ t90 = lclVar int V06 rat1 REG ebx
/--* t53 int
+--* t51 int
N033 ( 12, 12) [000050] --------R--- t50 = * -Lo int REG esi
/--* t90 int
+--* t88 int
N035 (???,???) [000092] ------------ t92 = * -Hi int REG ebx
/--* t50 int
+--* t92 int
N037 (???,???) [000093] ------------ t93 = * gt_long long REG NA
/--* t93 long
N039 ( 19, 20) [000049] ---X-------Z t49 = * cast_ovfl int <- long REG esi $242
N041 ( 1, 1) [000055] -----------Z t55 = const int 0 REG ebx $40
/--* t55 int
[000131] ------------ t131 = * reload int REG esi
N043 ( 3, 2) [000061] -----------z t61 = lclVar int V03 arg3 u:2 (last use) REG eax $140
/--* t61 int
N045 ( 4, 4) [000060] -----------Z t60 = * cast int <- ubyte <- int REG ebx $240
N047 (???,???) [000094] ------------ t94 = const int 0 REG NA
N049 ( 3, 2) [000058] ------------ t58 = lclVar int V05 rat0 REG esi $100
N051 (???,???) [000096] ------------ t96 = lclVar int V06 rat1 REG ebx
/--* t60 int
+--* t58 int
N053 ( 12, 12) [000057] --------R--- t57 = * -Lo int REG esi
/--* t96 int
+--* t94 int
N055 (???,???) [000098] ------------ t98 = * -Hi int REG ebx
/--* t57 int
+--* t98 int
N057 (???,???) [000099] ------------ t99 = * gt_long long REG NA
/--* t99 long
N059 ( 19, 20) [000056] ---X-------Z t56 = * cast_ovfl int <- long REG esi $242
N061 (???,???) [000115] ------------ t115 = const int 0 REG NA
/--* t132 ref
+--* t49 int
N063 (???,???) [000116] ---X-------- t116 = * arrMDIdx[i, , ] int REG esi
N065 (???,???) [000117] ------------ t117 = lclVar ref V01 arg1 edx REG edx RV
/--* t117 ref
[000133] ------------ t133 = * copy ref REG ebx
/--* t115 int
+--* t116 int
+--* t133 ref
N067 (???,???) [000118] ---X-------Z t118 = * arrMDOffs[i, , ] int
/--* t118 int
[000134] ---X-------- t134 = * reload int REG ebx
N069 (???,???) [000119] ------------ t119 = lclVar ref V01 arg1 edx REG edx RV
/--* t119 ref
[000135] ------------ t135 = * copy ref REG ebx
/--* t135 ref
+--* t131 int
N071 (???,???) [000120] ---X-------- t120 = * arrMDIdx[*,j, ] int REG esi
N073 (???,???) [000121] ------------ t121 = lclVar ref V01 arg1 edx REG edx RV
/--* t134 int
+--* t120 int
+--* t121 ref
N075 (???,???) [000122] ---X-------- t122 = * arrMDOffs[*,j, ] int
N077 (???,???) [000123] ------------ t123 = lclVar ref V01 arg1 edx REG edx RV
/--* t123 ref
[000136] ------------ t136 = * copy ref REG ebx
/--* t136 ref
+--* t56 int
N079 (???,???) [000124] ---X-------- t124 = * arrMDIdx[*,*,k] int REG esi
N081 (???,???) [000125] ------------ t125 = lclVar ref V01 arg1 edx REG edx RV
/--* t122 int
+--* t124 int
+--* t125 ref
N083 (???,???) [000126] ---X-------- t126 = * arrMDOffs[*,*,k] int
N085 (???,???) [000127] ------------ t127 = lclVar ref V01 arg1 edx (last use) REG edx RV
/--* t127 ref
[000137] ------------ t137 = * copy ref REG ebx
/--* t126 int
+--* t137 ref
N087 (???,???) [000128] ---X----R--- t128 = * lea(b+(i*8)+32) byref REG esi
/--* t128 byref
N089 (???,???) [000103] DA-X-------- * st.lclVar byref V09 rat4 esi REG esi RV
N091 (???,???) [000104] ------------ t104 = lclVar byref V09 rat4 esi REG esi RV
N093 ( 3, 2) [000064] ------------ t64 = lclVar int V07 rat2 edi REG edi RV $1c0
/--* t104 byref
+--* t64 int
N095 (???,???) [000080] -A-X-------- * storeIndir int REG NA
N097 (???,???) [000100] -----------z t100 = lclVar int V08 rat3 (last use) REG ebx
N099 (???,???) [000105] ------------ t105 = lclVar byref V09 rat4 esi (last use) REG esi RV
/--* t105 byref
N101 (???,???) [000106] ------------ t106 = * lea(b+4) ref REG NA
/--* t100 int
+--* t106 ref
N103 (???,???) [000107] -A-X----R--- * storeIndir int REG NA
N105 ( 6, 5) [000035] ------------ il_offset void IL offset: 24 REG NA
N107 ( 1, 1) [000070] ------------ t70 = lclVar int V00 arg0 u:2 ecx (last use) REG ecx RV $80
/--* t70 int
[000138] ------------ t138 = * copy int REG esi
N109 ( 1, 1) [000072] C----------- t72 = lclVar int V07 rat2 edi (last use) REG edi RV $243
/--* t138 int
+--* t72 int
N111 (???,???) [000129] ------------ t129 = * lea(b+(i*8)+0) int REG esi
/--* t129 int
N113 (???,???) [000109] DA---------- * st.lclVar int V10 rat5 esi REG esi RV
N115 (???,???) [000110] ------------ t110 = lclVar int V10 rat5 esi REG esi RV
/--* t110 int
N117 ( 5, 4) [000068] ---XG------- t68 = * indir int REG eax $201
N119 (???,???) [000111] ------------ t111 = lclVar int V10 rat5 esi (last use) REG esi RV
/--* t111 int
N121 (???,???) [000112] ------------ t112 = * lea(b+4) ref REG NA
/--* t112 ref
N123 (???,???) [000113] ---XG------- t113 = * indir int REG edx
/--* t68 int
+--* t113 int
N125 (???,???) [000114] ---XG------- t114 = * gt_long long REG NA
/--* t114 long
N127 ( 6, 5) [000067] ---XG------- * return long REG NA $202
------------ BB02 [???..???) (throw), preds={} succs={}
N131 ( 14, 5) [000074] --CXG------- call help void HELPER.CORINFO_HELP_OVERFLOW
------------ BB03 [???..???) (throw), preds={} succs={}
N135 ( 14, 5) [000077] --CXG------- call help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |ebx |esp |ebp |esi |edi |
--------------------------------+----+----+----+----+----+----+----+----+
0.#0 V1 Parm Alloc edx | | |V1 a| |----|----| | |
0.#1 V0 Parm Alloc ecx | |V0 a|V1 a| |----|----| | |
0.#2 V3 Parm Alloc esi | |V0 a|V1 a| |----|----|V3 a| |
0.#3 BB1 PredBB0 | |V0 a|V1 a| |----|----|V3 a| |
6.#4 I11 Def Alloc edi | |V0 a|V1 a| |----|----|V3 a|I11a|
8.#5 I12 Def Alloc ebx | |V0 a|V1 a|I12a|----|----|V3 a|I11a|
13.#6 I11 Use * Keep edi | |V0 a|V1 a|I12a|----|----|V3 a|I11i|
14.#7 I13 Def Alloc edi | |V0 a|V1 a|I12a|----|----|V3 a|I13a|
15.#8 I12 Use * Keep ebx | |V0 a|V1 a|I12i|----|----|V3 a|I13a|
16.#9 I14 Def Alloc ebx | |V0 a|V1 a|I14a|----|----|V3 a|I13a|
17.#10 I13 Use * Keep edi | |V0 a|V1 a|I14a|----|----|V3 a|I13i|
18.#11 V7 Def Alloc edi | |V0 a|V1 a|I14a|----|----|V3 a|V7 a|
19.#12 I14 Use * Keep ebx | |V0 a|V1 a|I14i|----|----|V3 a|V7 a|
20.#13 V8 Def Alloc ebx | |V0 a|V1 a| |----|----|V3 a|V7 a|
Spill ebx | |V0 a|V1 a| |----|----|V3 a|V7 a|
25.#14 V3 Use Copy eax | |V0 a|V1 a| |----|----|V3 i|V7 a|
Spill eax | |V0 a|V1 a| |----|----|V3 i|V7 a|
26.#15 I15 Def Alloc ebx | |V0 a|V1 a| |----|----| |V7 a|
Spill ebx | |V0 a|V1 a| |----|----| |V7 a|
30.#16 I16 Def Alloc esi | |V0 a|V1 a| |----|----|I16a|V7 a|
32.#17 I17 Def Alloc ebx | |V0 a|V1 a|I17a|----|----|I16a|V7 a|
33.#18 I15 Use *D NoReg | |V0 a|V1 a|I17a|----|----|I16a|V7 a|
33.#19 I16 Use * Keep esi | |V0 a|V1 a|I17a|----|----|I16i|V7 a|
34.#20 I18 Def Alloc esi | |V0 a|V1 a|I17a|----|----|I18a|V7 a|
35.#21 I17 Use * Keep ebx | |V0 a|V1 a|I17i|----|----|I18a|V7 a|
36.#22 I19 Def Alloc ebx | |V0 a|V1 a|I19a|----|----|I18a|V7 a|
39.#23 I18 Use * Keep esi | |V0 a|V1 a|I19a|----|----|I18i|V7 a|
39.#24 I19 Use * Keep ebx | |V0 a|V1 a|I19i|----|----| |V7 a|
40.#25 I20 Def Alloc esi | |V0 a|V1 a| |----|----| |V7 a|
Spill esi | |V0 a|V1 a| |----|----| |V7 a|
42.#26 C21 Def Alloc ebx | |V0 a|V1 a| |----|----| |V7 a|
Spill ebx | |V0 a|V1 a| |----|----| |V7 a|
45.#27 V3 Use * ReLod eax |V3 a|V0 a|V1 a| |----|----| |V7 a|
Keep eax |V3 i|V0 a|V1 a| |----|----| |V7 a|
46.#28 I22 Def Alloc ebx | |V0 a|V1 a| |----|----| |V7 a|
Spill ebx | |V0 a|V1 a| |----|----| |V7 a|
50.#29 I23 Def Alloc esi | |V0 a|V1 a| |----|----|I23a|V7 a|
52.#30 I24 Def Alloc ebx | |V0 a|V1 a|I24a|----|----|I23a|V7 a|
53.#31 I22 Use *D NoReg | |V0 a|V1 a|I24a|----|----|I23a|V7 a|
53.#32 I23 Use * Keep esi | |V0 a|V1 a|I24a|----|----|I23i|V7 a|
54.#33 I25 Def Alloc esi | |V0 a|V1 a|I24a|----|----|I25a|V7 a|
55.#34 I24 Use * Keep ebx | |V0 a|V1 a|I24i|----|----|I25a|V7 a|
56.#35 I26 Def Alloc ebx | |V0 a|V1 a|I26a|----|----|I25a|V7 a|
59.#36 I25 Use * Keep esi | |V0 a|V1 a|I26a|----|----|I25i|V7 a|
59.#37 I26 Use * Keep ebx | |V0 a|V1 a|I26i|----|----| |V7 a|
60.#38 I27 Def Alloc esi | |V0 a|V1 a| |----|----| |V7 a|
Spill esi | |V0 a|V1 a| |----|----| |V7 a|
63.#39 V1 Use Copy ebx | |V0 a|V1 a|V1 a|----|----| |V7 a|
63.#40 I20 Use * ReLod esi | |V0 a|V1 a| |----|----|I20a|V7 a|
Keep esi | |V0 a|V1 a| |----|----|I20i|V7 a|
64.#41 I28 Def Alloc esi | |V0 a|V1 a| |----|----|I28a|V7 a|
67.#42 I28 Use * Keep esi | |V0 a|V1 a| |----|----|I28i|V7 a|
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |ebx |esp |ebp |esi |edi |
--------------------------------+----+----+----+----+----+----+----+----+
67.#43 V1 Use Copy ebx | |V0 a|V1 a|V1 a|----|----| |V7 a|
68.#44 I29 Def Alloc esi | |V0 a|V1 a| |----|----| |V7 a|
Spill esi | |V0 a|V1 a| |----|----| |V7 a|
71.#45 V1 Use Copy ebx | |V0 a|V1 a|V1 a|----|----| |V7 a|
71.#46 C21 Use * ReLod esi | |V0 a|V1 a| |----|----|C21a|V7 a|
Keep esi | |V0 a|V1 a| |----|----|C21i|V7 a|
72.#47 I30 Def Alloc esi | |V0 a|V1 a| |----|----|I30a|V7 a|
75.#48 I31 Def Alloc eax |I31a|V0 a|V1 a| |----|----|I30a|V7 a|
75.#49 I29 Use * ReLod ebx |I31a|V0 a|V1 a|I29a|----|----|I30a|V7 a|
Keep ebx |I31a|V0 a|V1 a|I29i|----|----|I30a|V7 a|
75.#50 I30 Use * Keep esi |I31a|V0 a|V1 a| |----|----|I30i|V7 a|
75.#51 V1 Use Keep edx |I31a|V0 a|V1 a| |----|----| |V7 a|
75.#52 I31 Use * Keep eax |I31i|V0 a|V1 a| |----|----| |V7 a|
76.#53 I32 Def Alloc eax |I32a|V0 a|V1 a| |----|----| |V7 a|
79.#54 V1 Use Copy ebx |I32a|V0 a|V1 a|V1 a|----|----| |V7 a|
79.#55 I27 Use * ReLod esi |I32a|V0 a|V1 a| |----|----|I27a|V7 a|
Keep esi |I32a|V0 a|V1 a| |----|----|I27i|V7 a|
80.#56 I33 Def Alloc esi |I32a|V0 a|V1 a| |----|----|I33a|V7 a|
83.#57 I34 Def Alloc ebx |I32a|V0 a|V1 a|I34a|----|----|I33a|V7 a|
83.#58 I32 Use * Keep eax |I32i|V0 a|V1 a|I34a|----|----|I33a|V7 a|
83.#59 I33 Use * Keep esi | |V0 a|V1 a|I34a|----|----|I33i|V7 a|
83.#60 V1 Use Keep edx | |V0 a|V1 a|I34a|----|----| |V7 a|
83.#61 I34 Use * Keep ebx | |V0 a|V1 a|I34i|----|----| |V7 a|
84.#62 I35 Def Alloc esi | |V0 a|V1 a| |----|----|I35a|V7 a|
87.#63 I35 Use * Keep esi | |V0 a|V1 a| |----|----|I35i|V7 a|
87.#64 V1 Use * Copy ebx | |V0 a|V1 i|V1 i|----|----| |V7 a|
88.#65 I36 Def Alloc esi | |V0 a| | |----|----|I36a|V7 a|
89.#66 I36 Use * Keep esi | |V0 a| | |----|----|I36i|V7 a|
90.#67 V9 Def Alloc esi | |V0 a| | |----|----|V9 a|V7 a|
95.#68 V9 Use Keep esi | |V0 a| | |----|----|V9 a|V7 a|
95.#69 V7 Use Keep edi | |V0 a| | |----|----|V9 a|V7 a|
103.#70 V8 Use * ReLod ebx | |V0 a| |V8 a|----|----|V9 a|V7 a|
Keep ebx | |V0 a| |V8 i|----|----|V9 a|V7 a|
103.#71 V9 Use * Keep esi | |V0 a| | |----|----|V9 i|V7 a|
111.#72 V0 Use * Copy esi | |V0 i| | |----|----|V0 i|V7 a|
111.#73 V7 Use * Keep edi | | | | |----|----| |V7 i|
112.#74 I37 Def Alloc esi | | | | |----|----|I37a| |
113.#75 I37 Use * Keep esi | | | | |----|----|I37i| |
114.#76 V10 Def Alloc esi | | | | |----|----|V10a| |
117.#77 V10 Use Keep esi | | | | |----|----|V10a| |
118.#78 I38 Def Alloc eax |I38a| | | |----|----|V10a| |
123.#79 V10 Use * Keep esi |I38a| | | |----|----|V10i| |
124.#80 I39 Def Alloc edx |I38a| |I39a| |----|----| | |
127.#81 eax Fixd Keep eax |I38a| |I39a| |----|----| | |
127.#82 I38 Use * Keep eax |I38i| |I39a| |----|----| | |
127.#83 edx Fixd Keep edx | | |I39a| |----|----| | |
127.#84 I39 Use * Keep edx | | |I39i| |----|----| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |ebx |esp |ebp |esi |edi |
--------------------------------+----+----+----+----+----+----+----+----+
129.#85 BB2 PredBB1 | | | | |----|----| | |
132.#86 eax Kill Keep eax | | | | |----|----| | |
132.#87 ecx Kill Keep ecx | | | | |----|----| | |
132.#88 edx Kill Keep edx | | | | |----|----| | |
132.#89 mm0 Kill Keep mm0 | | | | |----|----| | |
132.#90 mm1 Kill Keep mm1 | | | | |----|----| | |
132.#91 mm2 Kill Keep mm2 | | | | |----|----| | |
132.#92 mm3 Kill Keep mm3 | | | | |----|----| | |
132.#93 mm4 Kill Keep mm4 | | | | |----|----| | |
132.#94 mm5 Kill Keep mm5 | | | | |----|----| | |
132.#95 mm6 Kill Keep mm6 | | | | |----|----| | |
132.#96 mm7 Kill Keep mm7 | | | | |----|----| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |ebx |esp |ebp |esi |edi |
--------------------------------+----+----+----+----+----+----+----+----+
133.#97 BB3 PredBB2 | | | | |----|----| | |
136.#98 eax Kill Keep eax | | | | |----|----| | |
136.#99 ecx Kill Keep ecx | | | | |----|----| | |
136.#100 edx Kill Keep edx | | | | |----|----| | |
136.#101 mm0 Kill Keep mm0 | | | | |----|----| | |
136.#102 mm1 Kill Keep mm1 | | | | |----|----| | |
136.#103 mm2 Kill Keep mm2 | | | | |----|----| | |
136.#104 mm3 Kill Keep mm3 | | | | |----|----| | |
136.#105 mm4 Kill Keep mm4 | | | | |----|----| | |
136.#106 mm5 Kill Keep mm5 | | | | |----|----| | |
136.#107 mm6 Kill Keep mm6 | | | | |----|----| | |
136.#108 mm7 Kill Keep mm7 | | | | |----|----| | |
Recording the maximum number of concurrent spills:
<UNDEF>: 0
void: 0
bool: 0
byte: 0
ubyte: 0
char: 0
short: 0
ushort: 0
int: 3
pre-allocated temp #1, slot 0, size = 4
pre-allocated temp #2, slot 0, size = 4
pre-allocated temp #3, slot 0, size = 4
uint: 0
long: 0
ulong: 0
float: 0
double: 0
ref: 0
byref: 0
array: 0
struct: 0
blk: 0
lclBlk: 0
pointer: 0
function: 0
unknown: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V01(edx) V00(ecx) V03(STK=>esi)
BB01 [000..02A) (return), preds={} succs={}
=====
N003. il_offset IL offset: 0 REG NA
N005. edi = V05 MEM
N007. ebx = V06 MEM
N009. const 1 REG NA
N011. const 0 REG NA
N013. edi = -Lo ; edi
N015. ebx = -Hi ; ebx
* N017. V07(edi); edi
N019. V08(STK); ebx
N021. V01(edx)
N000. ebx* = copy ; edx
S N023. V03(esi)
N000. eax* = copy ; esi
S N025. ebx = cast ; eax*
N027. const 0 REG NA
N029. esi = V05 MEM
N031. ebx = V06 MEM
N033. esi = -Lo (Rev); ebx,esi
N035. ebx = -Hi ; ebx
N037. gt_long
S N039. esi = cast_ovfl; esi,ebx
S N041. ebx = const 0 REG ebx
N000. esi = reload ; ebx
N043. V03(eax*)R
S N045. ebx = cast ; eax*
N047. const 0 REG NA
N049. esi* = V05 MEM
N051. ebx = V06 MEM
N053. esi = -Lo (Rev); ebx,esi*
N055. ebx = -Hi ; ebx
N057. gt_long
S N059. esi = cast_ovfl; esi,ebx
N061. const 0 REG NA
N063. esi = arrMDIdx[i, , ]; ebx*,esi
N065. V01(edx)
N000. ebx* = copy ; edx
S N067. esi = arrMDOffs[i, , ]; esi,ebx*
N000. ebx = reload ; esi
N069. V01(edx)
N000. ebx* = copy ; edx
N071. esi = arrMDIdx[*,j, ]; ebx*,esi
N073. V01(edx)
N075. eax = arrMDOffs[*,j, ]; ebx,esi,edx
internal (1): [eax]
N077. V01(edx)
N000. ebx* = copy ; edx
N079. esi = arrMDIdx[*,*,k]; ebx*,esi
N081. V01(edx)
N083. esi = arrMDOffs[*,*,k]; eax,esi,edx
internal (1): [ebx]
N085. V01(edx*)
N000. ebx* = copy ; edx*
N087. esi = lea(b+(i*8)+32)(Rev); esi,ebx*
* N089. V09(esi); esi
N091. V09(esi)
N093. V07(edi)
N095. storeIndir; esi,edi
N097. V08(ebx*)R
N099. V09(esi*)
N101. lea(b+4)
N103. storeIndir(Rev); ebx*,esi*
N105. il_offset IL offset: 24 REG NA
N107. V00(ecx*)
N000. esi* = copy ; ecx*
N109. V07(edi*)
N111. esi = lea(b+(i*8)+0); esi*,edi*
* N113. V10(esi); esi
N115. V10(esi)
N117. eax = indir ; esi
N119. V10(esi*)
N121. lea(b+4)
N123. edx = indir ; esi*
N125. gt_long
N127. return ; eax,edx
Var=Reg end of BB01: none
BB02 [???..???) (throw), preds={} succs={}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: none
N131. call help
Var=Reg end of BB02: none
BB03 [???..???) (throw), preds={} succs={}
=====
Predecessor for variable locations: BB02
Var=Reg beg of BB03: none
N135. call help
Var=Reg end of BB03: none
*************** In genGenerateCode()
-------------------------------------------------------------------------------------------------------------------------------------
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags]
-------------------------------------------------------------------------------------------------------------------------------------
BB01 [032A71F8] 1 1 [000..02A) (return) i label target LIR
BB02 [032A9340] 0 0 [???..???) (throw ) keep i internal rare label target LIR
BB03 [032A9618] 0 0 [???..???) (throw ) keep i internal rare label target LIR
-------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V01(edx) V00(ecx) V03(esi)
Modified regs: [eax ecx edx ebx esi edi mm0-mm7]
Callee-saved registers pushed: 3 [ebx esi edi]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V08 rat3, size=4, stkOffs=-0x20
; Final local variable assignments
;
; V00 arg0 [V00,T03] ( 3, 3 ) int -> ecx
; V01 arg1 [V01,T02] ( 3, 3 ) ref -> edx
; V02 arg2 [V02 ] ( 6, 0 ) long -> [esp+0x24]
; V03 arg3 [V03,T05] ( 2, 2 ) ubyte -> [esp+0x20]
;* V04 loc0 [V04 ] ( 0, 0 ) long -> zero-ref
; V05 rat0 [V05 ] ( 3, 3 ) int -> [esp+0x24] V02.lo(offs=0x00)
; V06 rat1 [V06 ] ( 3, 3 ) int -> [esp+0x28] V02.hi(offs=0x04)
; V07 rat2 [V07,T04] ( 3, 3 ) int -> edi V04.lo(offs=0x00)
; V08 rat3 [V08,T06] ( 2, 2 ) int -> [esp+0x00] V04.hi(offs=0x04)
; V09 rat4 [V09,T00] ( 3, 6 ) byref -> esi
; V10 rat5 [V10,T01] ( 3, 6 ) int -> esi
; TEMP_03 int -> [esp+0x0C]
; TEMP_02 int -> [esp+0x08]
; TEMP_01 int -> [esp+0x04]
;
; Lcl frame size = 16
The register ecx now holds V00
=============== Generating BB01 [000..02A) (return), preds={} succs={} flags=0x40030020: i label target LIR
BB01 IN (3)={V01 V00 V03} + HEAP
OUT(0)={ }
Recording Var Locations at start of BB01
V01(edx) V00(ecx) V03(esi)
Change life 00000000 {} -> 0000002C {V00 V01 V03}
V01 in reg edx is becoming live [------]
Live regs: 00000000 {} => 00000004 {edx}
V00 in reg ecx is becoming live [------]
Live regs: 00000004 {edx} => 00000006 {ecx edx}
V03 in reg esi is becoming live [------]
Live regs: 00000006 {ecx edx} => 00000046 {ecx edx esi}
Live regs: (unchanged) 00000046 {ecx edx esi}
GC regs: (unchanged) 00000004 {edx}
Byref regs: (unchanged) 00000000 {}
L_M14742_BB01:
Label: IG02, GCvars=00000000 {}, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}
Scope info: begin block BB01, IL range [000..02A)
Scope info: open scopes =
1 (V01 arg1) [000..02A)
0 (V00 arg0) [000..02A)
3 (V03 arg3) [000..02A)
Added IP mapping: 0x0000 STACK_EMPTY (G_M14742_IG02,ins#0,ofs#0) label
Generating: N003 ( 17, 22) [000020] ------------ * il_offset void IL offset: 0 REG NA
Generating: N005 ( 3, 2) [000039] ------------ * lclVar int V05 rat0 REG edi $100
IN0001: mov edi, dword ptr [V05 esp+24H]
Generating: N007 (???,???) [000081] ------------ * lclVar int V06 rat1 REG ebx
G_M14742_IG02: ; offs=000000H, funclet=00
IN0002: mov ebx, dword ptr [V06 esp+28H]
Generating: N009 ( 3, 10) [000040] ------------ * const int 1 REG NA
Generating: N011 (???,???) [000083] ------------ * const int 0 REG NA
Generating: N013 ( 10, 16) [000038] ------------ * -Lo int REG edi
G_M14742_IG03: ; offs=000004H, funclet=00
IN0003: sub edi, 1
Generating: N015 (???,???) [000085] ------------ * -Hi int REG ebx
G_M14742_IG04: ; offs=000008H, funclet=00
IN0004: sbb ebx, 0
Generating: N017 ( 17, 22) [000036] DA---------- * st.lclVar int V07 rat2 edi REG edi RV
V07 in reg edi is becoming live [000036]
Live regs: 00000046 {ecx edx esi} => 000000C6 {ecx edx esi edi}
Live vars: {V00 V01 V03} => {V00 V01 V03 V07}
Generating: N019 (???,???) [000087] D----------- * st.lclVar int V08 rat3 REG NA
G_M14742_IG05: ; offs=00000BH, funclet=00
IN0005: mov dword ptr [V08 esp], ebx
Live vars: {V00 V01 V03 V07} => {V00 V01 V03 V07 V08}
Generating: N021 ( 1, 1) [000062] ------------ * lclVar ref V01 arg1 u:2 edx REG edx RV $c0
Generating: [000132] ------------ * copy ref REG ebx
Generating: N023 ( 3, 2) [000054] -----------Z * lclVar int V03 arg3 u:2 esi REG esi RV $140
Generating: [000130] ------------ * copy int REG eax
Generating: N025 ( 4, 4) [000053] -----------Z * cast int <- ubyte <- int REG ebx $240
G_M14742_IG06: ; offs=00000EH, funclet=00
IN0006: mov byte ptr [V03 esp+20H], sl
V03 in reg esi is becoming dead [000054]
Live regs: 000000C6 {ecx edx esi edi} => 00000086 {ecx edx edi}
G_M14742_IG07: ; offs=000011H, funclet=00
IN0007: mov eax, esi
G_M14742_IG08: ; offs=000015H, funclet=00
IN0008: movzx ebx, al
reused temp #3, slot 0, size = 4
The register ebx spilled with [000053]
G_M14742_IG09: ; offs=000017H, funclet=00
IN0009: mov dword ptr [TEMP_03 esp+0CH], ebx
Generating: N027 (???,???) [000088] ------------ * const int 0 REG NA
Generating: N029 ( 3, 2) [000051] ------------ * lclVar int V05 rat0 REG esi $100
G_M14742_IG10: ; offs=00001AH, funclet=00
IN000a: mov esi, dword ptr [V05 esp+24H]
Generating: N031 (???,???) [000090] ------------ * lclVar int V06 rat1 REG ebx
G_M14742_IG11: ; offs=00001EH, funclet=00
IN000b: mov ebx, dword ptr [V06 esp+28H]
Generating: N033 ( 12, 12) [000050] --------R--- * -Lo int REG esi
G_M14742_IG12: ; offs=000022H, funclet=00
IN000c: sub esi, dword ptr [TEMP_03 esp+0CH]
release temp #3, slot 0, size = 4
Generating: N035 (???,???) [000092] ------------ * -Hi int REG ebx
G_M14742_IG13: ; offs=000026H, funclet=00
IN000d: sbb ebx, 0
Generating: N037 (???,???) [000093] ------------ * gt_long long REG NA
Generating: N039 ( 19, 20) [000049] ---X-------Z * cast_ovfl int <- long REG esi $242
New Basic Block BB04 [032F9320] created.
New Basic Block BB05 [032F93E0] created.
G_M14742_IG14: ; offs=00002AH, funclet=00
IN000e: test esi, esi
G_M14742_IG15: ; offs=00002DH, funclet=00
IN000f: js L_M14742_BB04
G_M14742_IG16: ; offs=00002FH, funclet=00
IN0010: test ebx, ebx
G_M14742_IG17: ; offs=000035H, funclet=00
IN0011: jne L_M14742_BB02
G_M14742_IG18: ; offs=000037H, funclet=00
IN0012: jmp L_M14742_BB05
L_M14742_BB04:
G_M14742_IG19: ; offs=00003DH, funclet=00
Label: IG20, GCvars=00000000 {}, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}
IN0013: cmp ebx, -1
G_M14742_IG20: ; offs=000042H, funclet=00
IN0014: jne L_M14742_BB02
L_M14742_BB05:
G_M14742_IG21: ; offs=000045H, funclet=00
Label: IG22, GCvars=00000000 {}, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}
reused temp #3, slot 0, size = 4
The register esi spilled with [000049]
IN0015: mov dword ptr [TEMP_03 esp+0CH], esi
Generating: N041 ( 1, 1) [000055] -----------Z * const int 0 REG ebx $40
G_M14742_IG22: ; offs=00004BH, funclet=00
IN0016: xor ebx, ebx
reused temp #2, slot 0, size = 4
The register ebx spilled with [000055]
G_M14742_IG23: ; offs=00004FH, funclet=00
IN0017: mov dword ptr [TEMP_02 esp+08H], ebx
Generating: [000131] ------------ * reload int REG esi
Generating: N043 ( 3, 2) [000061] -----------z * lclVar int V03 arg3 u:2 (last use) REG eax $140
Generating: N045 ( 4, 4) [000060] -----------Z * cast int <- ubyte <- int REG ebx $240
G_M14742_IG24: ; offs=000051H, funclet=00
IN0018: mov eax, dword ptr [V03 esp+20H]
V03 in reg eax is becoming live [000061]
Live regs: 00000086 {ecx edx edi} => 00000087 {eax ecx edx edi}
V03 in reg eax is becoming dead [000061]
Live regs: 00000087 {eax ecx edx edi} => 00000086 {ecx edx edi}
Live vars: {V00 V01 V03 V07 V08} => {V00 V01 V07 V08}
G_M14742_IG25: ; offs=000055H, funclet=00
IN0019: movzx ebx, al
reused temp #1, slot 0, size = 4
The register ebx spilled with [000060]
G_M14742_IG26: ; offs=000059H, funclet=00
IN001a: mov dword ptr [TEMP_01 esp+04H], ebx
Generating: N047 (???,???) [000094] ------------ * const int 0 REG NA
Generating: N049 ( 3, 2) [000058] ------------ * lclVar int V05 rat0 REG esi $100
G_M14742_IG27: ; offs=00005CH, funclet=00
IN001b: mov esi, dword ptr [V05 esp+24H]
Generating: N051 (???,???) [000096] ------------ * lclVar int V06 rat1 REG ebx
G_M14742_IG28: ; offs=000060H, funclet=00
IN001c: mov ebx, dword ptr [V06 esp+28H]
Generating: N053 ( 12, 12) [000057] --------R--- * -Lo int REG esi
G_M14742_IG29: ; offs=000064H, funclet=00
IN001d: sub esi, dword ptr [TEMP_01 esp+04H]
release temp #1, slot 0, size = 4
Generating: N055 (???,???) [000098] ------------ * -Hi int REG ebx
G_M14742_IG30: ; offs=000068H, funclet=00
IN001e: sbb ebx, 0
Generating: N057 (???,???) [000099] ------------ * gt_long long REG NA
Generating: N059 ( 19, 20) [000056] ---X-------Z * cast_ovfl int <- long REG esi $242
New Basic Block BB06 [032F9CD8] created.
New Basic Block BB07 [032F9D98] created.
G_M14742_IG31: ; offs=00006CH, funclet=00
IN001f: test esi, esi
G_M14742_IG32: ; offs=00006FH, funclet=00
IN0020: js L_M14742_BB06
G_M14742_IG33: ; offs=000071H, funclet=00
IN0021: test ebx, ebx
G_M14742_IG34: ; offs=000077H, funclet=00
IN0022: jne L_M14742_BB02
G_M14742_IG35: ; offs=000079H, funclet=00
IN0023: jmp L_M14742_BB07
L_M14742_BB06:
G_M14742_IG36: ; offs=00007FH, funclet=00
Label: IG37, GCvars=00000000 {}, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}
IN0024: cmp ebx, -1
G_M14742_IG37: ; offs=000084H, funclet=00
IN0025: jne L_M14742_BB02
L_M14742_BB07:
G_M14742_IG38: ; offs=000087H, funclet=00
Label: IG39, GCvars=00000000 {}, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}
reused temp #1, slot 0, size = 4
The register esi spilled with [000056]
IN0026: mov dword ptr [TEMP_01 esp+04H], esi
Generating: N061 (???,???) [000115] ------------ * const int 0 REG NA
Generating: N063 (???,???) [000116] ---X-------- * arrMDIdx[i, , ] int REG esi
G_M14742_IG39: ; offs=00008DH, funclet=00
IN0027: mov ebx, edx
GC regs: 00000004 {edx} => 0000000C {edx ebx}
GC regs: 0000000C {edx ebx} => 00000004 {edx}
Tree-Node marked unspilled from [000049]
G_M14742_IG40: ; offs=000091H, funclet=00
IN0028: mov esi, dword ptr [TEMP_03 esp+0CH]
release temp #3, slot 0, size = 4
G_M14742_IG41: ; offs=000093H, funclet=00
IN0029: sub esi, dword ptr [ebx+20]
G_M14742_IG42: ; offs=000097H, funclet=00
IN002a: cmp esi, dword ptr [ebx+8]
G_M14742_IG43: ; offs=00009AH, funclet=00
IN002b: jae L_M14742_BB03
Generating: N065 (???,???) [000117] ------------ * lclVar ref V01 arg1 edx REG edx RV
Generating: [000133] ------------ * copy ref REG ebx
Generating: N067 (???,???) [000118] ---X-------Z * arrMDOffs[i, , ] int
G_M14742_IG44: ; offs=00009DH, funclet=00
IN002c: mov ebx, edx
GC regs: 00000004 {edx} => 0000000C {edx ebx}
GC regs: 0000000C {edx ebx} => 00000004 {edx}
reused temp #3, slot 0, size = 4
The register esi spilled with [000118]
G_M14742_IG45: ; offs=0000A3H, funclet=00
IN002d: mov dword ptr [TEMP_03 esp+0CH], esi
Generating: [000134] ---X-------- * reload int REG ebx
Generating: N069 (???,???) [000119] ------------ * lclVar ref V01 arg1 edx REG edx RV
Generating: [000135] ------------ * copy ref REG ebx
Generating: N071 (???,???) [000120] ---X-------- * arrMDIdx[*,j, ] int REG esi
G_M14742_IG46: ; offs=0000A5H, funclet=00
IN002e: mov ebx, edx
GC regs: 00000004 {edx} => 0000000C {edx ebx}
GC regs: 0000000C {edx ebx} => 00000004 {edx}
Tree-Node marked unspilled from [000055]
G_M14742_IG47: ; offs=0000A9H, funclet=00
IN002f: mov esi, dword ptr [TEMP_02 esp+08H]
release temp #2, slot 0, size = 4
G_M14742_IG48: ; offs=0000ABH, funclet=00
IN0030: sub esi, dword ptr [ebx+24]
G_M14742_IG49: ; offs=0000AFH, funclet=00
IN0031: cmp esi, dword ptr [ebx+12]
G_M14742_IG50: ; offs=0000B2H, funclet=00
IN0032: jae L_M14742_BB03
Generating: N073 (???,???) [000121] ------------ * lclVar ref V01 arg1 edx REG edx RV
Generating: N075 (???,???) [000122] ---X-------- * arrMDOffs[*,j, ] int
Tree-Node marked unspilled from [000118]
G_M14742_IG51: ; offs=0000B5H, funclet=00
IN0033: mov ebx, dword ptr [TEMP_03 esp+0CH]
release temp #3, slot 0, size = 4
G_M14742_IG52: ; offs=0000BBH, funclet=00
IN0034: mov eax, dword ptr [edx+12]
G_M14742_IG53: ; offs=0000BFH, funclet=00
IN0035: imul eax, ebx
G_M14742_IG54: ; offs=0000C2H, funclet=00
IN0036: add eax, esi
Generating: N077 (???,???) [000123] ------------ * lclVar ref V01 arg1 edx REG edx RV
Generating: [000136] ------------ * copy ref REG ebx
Generating: N079 (???,???) [000124] ---X-------- * arrMDIdx[*,*,k] int REG esi
G_M14742_IG55: ; offs=0000C5H, funclet=00
IN0037: mov ebx, edx
GC regs: 00000004 {edx} => 0000000C {edx ebx}
GC regs: 0000000C {edx ebx} => 00000004 {edx}
Tree-Node marked unspilled from [000056]
G_M14742_IG56: ; offs=0000C7H, funclet=00
IN0038: mov esi, dword ptr [TEMP_01 esp+04H]
release temp #1, slot 0, size = 4
Nodes were consumed out-of-order:
N077 (???,???) [000123] ------------ * lclVar ref V01 arg1 edx REG edx RV
N059 ( 19, 20) [000056] ---X-------- * cast_ovfl int <- long REG esi RV $242
G_M14742_IG57: ; offs=0000C9H, funclet=00
IN0039: sub esi, dword ptr [ebx+28]
G_M14742_IG58: ; offs=0000CDH, funclet=00
IN003a: cmp esi, dword ptr [ebx+16]
G_M14742_IG59: ; offs=0000D0H, funclet=00
IN003b: jae L_M14742_BB03
Generating: N081 (???,???) [000125] ------------ * lclVar ref V01 arg1 edx REG edx RV
Generating: N083 (???,???) [000126] ---X-------- * arrMDOffs[*,*,k] int
G_M14742_IG60: ; offs=0000D3H, funclet=00
IN003c: mov ebx, dword ptr [edx+16]
G_M14742_IG61: ; offs=0000D9H, funclet=00
IN003d: imul ebx, eax
G_M14742_IG62: ; offs=0000DCH, funclet=00
IN003e: add esi, ebx
Generating: N085 (???,???) [000127] ------------ * lclVar ref V01 arg1 edx (last use) REG edx RV
Generating: [000137] ------------ * copy ref REG ebx
Generating: N087 (???,???) [000128] ---X----R--- * lea(b+(i*8)+32) byref REG esi
V01 in reg edx is becoming dead [000127]
Live regs: 00000086 {ecx edx edi} => 00000082 {ecx edi}
Live vars: {V00 V01 V07 V08} => {V00 V07 V08}
GC regs: 00000004 {edx} => 00000000 {}
G_M14742_IG63: ; offs=0000DFH, funclet=00
IN003f: mov ebx, edx
GC regs: 00000000 {} => 00000008 {ebx}
GC regs: 00000008 {ebx} => 00000000 {}
G_M14742_IG64: ; offs=0000E1H, funclet=00
IN0040: lea esi, bword ptr [ebx+8*esi+32]
Byref regs: 00000000 {} => 00000040 {esi}
Generating: N089 (???,???) [000103] DA-X-------- * st.lclVar byref V09 rat4 esi REG esi RV
Byref regs: 00000040 {esi} => 00000000 {}
V09 in reg esi is becoming live [000103]
Live regs: 00000082 {ecx edi} => 000000C2 {ecx esi edi}
Live vars: {V00 V07 V08} => {V00 V07 V08 V09}
Byref regs: 00000000 {} => 00000040 {esi}
Generating: N091 (???,???) [000104] ------------ * lclVar byref V09 rat4 esi REG esi RV
Generating: N093 ( 3, 2) [000064] ------------ * lclVar int V07 rat2 edi REG edi RV $1c0
Generating: N095 (???,???) [000080] -A-X-------- * storeIndir int REG NA
G_M14742_IG65: ; offs=0000E3H, funclet=00
IN0041: mov dword ptr [esi], edi
Generating: N097 (???,???) [000100] -----------z * lclVar int V08 rat3 (last use) REG ebx
Generating: N099 (???,???) [000105] ------------ * lclVar byref V09 rat4 esi (last use) REG esi RV
Generating: N101 (???,???) [000106] ------------ * lea(b+4) ref REG NA
Generating: N103 (???,???) [000107] -A-X----R--- * storeIndir int REG NA
G_M14742_IG66: ; offs=0000E7H, funclet=00
IN0042: mov ebx, dword ptr [V08 esp]
V08 in reg ebx is becoming live [000100]
Live regs: 000000C2 {ecx esi edi} => 000000CA {ecx ebx esi edi}
V08 in reg ebx is becoming dead [000100]
Live regs: 000000CA {ecx ebx esi edi} => 000000C2 {ecx esi edi}
Live vars: {V00 V07 V08 V09} => {V00 V07 V09}
V09 in reg esi is becoming dead [000105]
Live regs: 000000C2 {ecx esi edi} => 00000082 {ecx edi}
Live vars: {V00 V07 V09} => {V00 V07}
Byref regs: 00000040 {esi} => 00000000 {}
G_M14742_IG67: ; offs=0000E9H, funclet=00
IN0043: mov dword ptr [esi+4], ebx
Added IP mapping: 0x0018 (G_M14742_IG68,ins#1,ofs#3)
Generating: N105 ( 6, 5) [000035] ------------ * il_offset void IL offset: 24 REG NA
Generating: N107 ( 1, 1) [000070] ------------ * lclVar int V00 arg0 u:2 ecx (last use) REG ecx RV $80
Generating: [000138] ------------ * copy int REG esi
Generating: N109 ( 1, 1) [000072] C----------- * lclVar int V07 rat2 edi (last use) REG edi RV $243
Generating: N111 (???,???) [000129] ------------ * lea(b+(i*8)+0) int REG esi
V00 in reg ecx is becoming dead [000070]
Live regs: 00000082 {ecx edi} => 00000080 {edi}
Live vars: {V00 V07} => {V07}
G_M14742_IG68: ; offs=0000ECH, funclet=00
IN0044: mov esi, ecx
V07 in reg edi is becoming dead [000072]
Live regs: 00000080 {edi} => 00000000 {}
Live vars: {V07} => {}
G_M14742_IG69: ; offs=0000EFH, funclet=00
IN0045: lea esi, [esi+8*edi]
Generating: N113 (???,???) [000109] DA---------- * st.lclVar int V10 rat5 esi REG esi RV
V10 in reg esi is becoming live [000109]
Live regs: 00000000 {} => 00000040 {esi}
Live vars: {} => {V10}
Generating: N115 (???,???) [000110] ------------ * lclVar int V10 rat5 esi REG esi RV
Generating: N117 ( 5, 4) [000068] ---XG------- * indir int REG eax $201
G_M14742_IG70: ; offs=0000F1H, funclet=00
IN0046: mov eax, dword ptr [esi]
Generating: N119 (???,???) [000111] ------------ * lclVar int V10 rat5 esi (last use) REG esi RV
Generating: N121 (???,???) [000112] ------------ * lea(b+4) ref REG NA
Generating: N123 (???,???) [000113] ---XG------- * indir int REG edx
V10 in reg esi is becoming dead [000111]
Live regs: 00000040 {esi} => 00000000 {}
Live vars: {V10} => {}
G_M14742_IG71: ; offs=0000F4H, funclet=00
IN0047: mov edx, dword ptr [esi+4]
Generating: N125 (???,???) [000114] ---XG------- * gt_long long REG NA
Generating: N127 ( 6, 5) [000067] ---XG------- * return long REG NA $202
Scope info: end block BB01, IL range [000..02A)
Scope info: ending scope, LVnum=1 [000..02A)
Scope info: ending scope, LVnum=2 [000..02A)
Scope info: ending scope, LVnum=3 [000..02A)
Scope info: ending scope, LVnum=4 [000..02A)
Scope info: ending scope, LVnum=0 [000..02A)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M14742_IG72,ins#1,ofs#3) label
Reserving epilog IG for block BB01
G_M14742_IG72: ; offs=0000F6H, funclet=00
*************** After placeholder IG creation
G_M14742_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M14742_IG02: ; offs=000000H, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG03: ; offs=000004H, size=0004H, emitadd
G_M14742_IG04: ; offs=000008H, size=0003H, emitadd
G_M14742_IG05: ; offs=00000BH, size=0003H, emitadd
G_M14742_IG06: ; offs=00000EH, size=0003H, emitadd
G_M14742_IG07: ; offs=000011H, size=0004H, emitadd
G_M14742_IG08: ; offs=000015H, size=0002H, emitadd
G_M14742_IG09: ; offs=000017H, size=0003H, emitadd
G_M14742_IG10: ; offs=00001AH, size=0004H, emitadd
G_M14742_IG11: ; offs=00001EH, size=0004H, emitadd
G_M14742_IG12: ; offs=000022H, size=0004H, emitadd
G_M14742_IG13: ; offs=000026H, size=0004H, emitadd
G_M14742_IG14: ; offs=00002AH, size=0003H, emitadd
G_M14742_IG15: ; offs=00002DH, size=0002H, emitadd
G_M14742_IG16: ; offs=00002FH, size=0006H, emitadd
G_M14742_IG17: ; offs=000035H, size=0002H, emitadd
G_M14742_IG18: ; offs=000037H, size=0006H, emitadd
G_M14742_IG19: ; offs=00003DH, size=0005H, emitadd
G_M14742_IG20: ; offs=000042H, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG21: ; offs=000045H, size=0006H, emitadd
G_M14742_IG22: ; offs=00004BH, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG23: ; offs=00004FH, size=0002H, emitadd
G_M14742_IG24: ; offs=000051H, size=0004H, emitadd
G_M14742_IG25: ; offs=000055H, size=0004H, emitadd
G_M14742_IG26: ; offs=000059H, size=0003H, emitadd
G_M14742_IG27: ; offs=00005CH, size=0004H, emitadd
G_M14742_IG28: ; offs=000060H, size=0004H, emitadd
G_M14742_IG29: ; offs=000064H, size=0004H, emitadd
G_M14742_IG30: ; offs=000068H, size=0004H, emitadd
G_M14742_IG31: ; offs=00006CH, size=0003H, emitadd
G_M14742_IG32: ; offs=00006FH, size=0002H, emitadd
G_M14742_IG33: ; offs=000071H, size=0006H, emitadd
G_M14742_IG34: ; offs=000077H, size=0002H, emitadd
G_M14742_IG35: ; offs=000079H, size=0006H, emitadd
G_M14742_IG36: ; offs=00007FH, size=0005H, emitadd
G_M14742_IG37: ; offs=000084H, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG38: ; offs=000087H, size=0006H, emitadd
G_M14742_IG39: ; offs=00008DH, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG40: ; offs=000091H, size=0002H, emitadd
G_M14742_IG41: ; offs=000093H, size=0004H, emitadd
G_M14742_IG42: ; offs=000097H, size=0003H, emitadd
G_M14742_IG43: ; offs=00009AH, size=0003H, emitadd
G_M14742_IG44: ; offs=00009DH, size=0006H, emitadd
G_M14742_IG45: ; offs=0000A3H, size=0002H, emitadd
G_M14742_IG46: ; offs=0000A5H, size=0004H, emitadd
G_M14742_IG47: ; offs=0000A9H, size=0002H, emitadd
G_M14742_IG48: ; offs=0000ABH, size=0004H, emitadd
G_M14742_IG49: ; offs=0000AFH, size=0003H, emitadd
G_M14742_IG50: ; offs=0000B2H, size=0003H, emitadd
G_M14742_IG51: ; offs=0000B5H, size=0006H, emitadd
G_M14742_IG52: ; offs=0000BBH, size=0004H, emitadd
G_M14742_IG53: ; offs=0000BFH, size=0003H, emitadd
G_M14742_IG54: ; offs=0000C2H, size=0003H, emitadd
G_M14742_IG55: ; offs=0000C5H, size=0002H, emitadd
G_M14742_IG56: ; offs=0000C7H, size=0002H, emitadd
G_M14742_IG57: ; offs=0000C9H, size=0004H, emitadd
G_M14742_IG58: ; offs=0000CDH, size=0003H, emitadd
G_M14742_IG59: ; offs=0000D0H, size=0003H, emitadd
G_M14742_IG60: ; offs=0000D3H, size=0006H, emitadd
G_M14742_IG61: ; offs=0000D9H, size=0003H, emitadd
G_M14742_IG62: ; offs=0000DCH, size=0003H, emitadd
G_M14742_IG63: ; offs=0000DFH, size=0002H, emitadd
G_M14742_IG64: ; offs=0000E1H, size=0002H, emitadd
G_M14742_IG65: ; offs=0000E3H, size=0004H, emitadd
G_M14742_IG66: ; offs=0000E7H, size=0002H, emitadd
G_M14742_IG67: ; offs=0000E9H, size=0003H, emitadd
G_M14742_IG68: ; offs=0000ECH, size=0003H, emitadd
G_M14742_IG69: ; offs=0000EFH, size=0002H, emitadd
G_M14742_IG70: ; offs=0000F1H, size=0003H, emitadd
G_M14742_IG71: ; offs=0000F4H, size=0002H, emitadd
G_M14742_IG72: ; offs=0000F6H, size=0003H, emitadd
G_M14742_IG73: ; epilog placeholder, next placeholder=<END>, BB=032A71F8H (BB01), epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000004 {edx}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000004 {edx}, InitByrefRegs=00000000 {}
G_M14742_IG74: ; offs=0001F9H, size=0000H, gcrefRegs=00000000 {} <-- Current IG
=============== Generating BB02 [???..???) (throw), preds={} succs={} flags=0x40031070: keep i internal rare label target LIR
BB02 IN (0)={}
OUT(0)={}
Recording Var Locations at start of BB02
<none>
Liveness not changing: 00000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M14742_BB02:
Label: IG74, GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB02, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP STACK_EMPTY (G_M14742_IG74,ins#0,ofs#0) label
Generating: N131 ( 14, 5) [000074] --CXG------- * call help void HELPER.CORINFO_HELP_OVERFLOW
Call: GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0048: call CORINFO_HELP_OVERFLOW
Scope info: end block BB02, IL range [???..???)
Scope info: ignoring block end
G_M14742_IG74: ; offs=0001F9H, funclet=00
IN0049: int3
=============== Generating BB03 [???..???) (throw), preds={} succs={} flags=0x40031070: keep i internal rare label target LIR
BB03 IN (0)={}
OUT(0)={}
Recording Var Locations at start of BB03
<none>
Liveness not changing: 00000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M14742_BB03:
G_M14742_IG75: ; offs=0001FEH, funclet=00
Label: IG76, GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB03, IL range [???..???)
Scope info: ignoring block beginning
genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
Generating: N135 ( 14, 5) [000077] --CXG------- * call help void HELPER.CORINFO_HELP_RNGCHKFAIL
Call: GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN004a: call CORINFO_HELP_RNGCHKFAIL
Scope info: end block BB03, IL range [???..???)
Scope info: ignoring block end
G_M14742_IG76: ; offs=0001FFH, funclet=00
IN004b: int3
Liveness not changing: 00000000 {}
3 tmps used
# compCycleEstimate = 115, compSizeEstimate = 95 TestApp:test_25(int,ref,long,ubyte):long
; Final local variable assignments
;
; V00 arg0 [V00,T03] ( 3, 3 ) int -> ecx
; V01 arg1 [V01,T02] ( 3, 3 ) ref -> edx
; V02 arg2 [V02 ] ( 6, 0 ) long -> [esp+0x24]
; V03 arg3 [V03,T05] ( 2, 2 ) ubyte -> [esp+0x20]
;* V04 loc0 [V04 ] ( 0, 0 ) long -> zero-ref
; V05 rat0 [V05 ] ( 3, 3 ) int -> [esp+0x24] V02.lo(offs=0x00)
; V06 rat1 [V06 ] ( 3, 3 ) int -> [esp+0x28] V02.hi(offs=0x04)
; V07 rat2 [V07,T04] ( 3, 3 ) int -> edi V04.lo(offs=0x00)
; V08 rat3 [V08,T06] ( 2, 2 ) int -> [esp+0x00] V04.hi(offs=0x04)
; V09 rat4 [V09,T00] ( 3, 6 ) byref -> esi
; V10 rat5 [V10,T01] ( 3, 6 ) int -> esi
; TEMP_01 int -> [esp+0x04]
; TEMP_03 int -> [esp+0x0C]
; TEMP_02 int -> [esp+0x08]
;
; Lcl frame size = 16
*************** Before prolog / epilog generation
G_M14742_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M14742_IG02: ; offs=000000H, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG03: ; offs=000004H, size=0004H, emitadd
G_M14742_IG04: ; offs=000008H, size=0003H, emitadd
G_M14742_IG05: ; offs=00000BH, size=0003H, emitadd
G_M14742_IG06: ; offs=00000EH, size=0003H, emitadd
G_M14742_IG07: ; offs=000011H, size=0004H, emitadd
G_M14742_IG08: ; offs=000015H, size=0002H, emitadd
G_M14742_IG09: ; offs=000017H, size=0003H, emitadd
G_M14742_IG10: ; offs=00001AH, size=0004H, emitadd
G_M14742_IG11: ; offs=00001EH, size=0004H, emitadd
G_M14742_IG12: ; offs=000022H, size=0004H, emitadd
G_M14742_IG13: ; offs=000026H, size=0004H, emitadd
G_M14742_IG14: ; offs=00002AH, size=0003H, emitadd
G_M14742_IG15: ; offs=00002DH, size=0002H, emitadd
G_M14742_IG16: ; offs=00002FH, size=0006H, emitadd
G_M14742_IG17: ; offs=000035H, size=0002H, emitadd
G_M14742_IG18: ; offs=000037H, size=0006H, emitadd
G_M14742_IG19: ; offs=00003DH, size=0005H, emitadd
G_M14742_IG20: ; offs=000042H, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG21: ; offs=000045H, size=0006H, emitadd
G_M14742_IG22: ; offs=00004BH, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG23: ; offs=00004FH, size=0002H, emitadd
G_M14742_IG24: ; offs=000051H, size=0004H, emitadd
G_M14742_IG25: ; offs=000055H, size=0004H, emitadd
G_M14742_IG26: ; offs=000059H, size=0003H, emitadd
G_M14742_IG27: ; offs=00005CH, size=0004H, emitadd
G_M14742_IG28: ; offs=000060H, size=0004H, emitadd
G_M14742_IG29: ; offs=000064H, size=0004H, emitadd
G_M14742_IG30: ; offs=000068H, size=0004H, emitadd
G_M14742_IG31: ; offs=00006CH, size=0003H, emitadd
G_M14742_IG32: ; offs=00006FH, size=0002H, emitadd
G_M14742_IG33: ; offs=000071H, size=0006H, emitadd
G_M14742_IG34: ; offs=000077H, size=0002H, emitadd
G_M14742_IG35: ; offs=000079H, size=0006H, emitadd
G_M14742_IG36: ; offs=00007FH, size=0005H, emitadd
G_M14742_IG37: ; offs=000084H, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG38: ; offs=000087H, size=0006H, emitadd
G_M14742_IG39: ; offs=00008DH, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG40: ; offs=000091H, size=0002H, emitadd
G_M14742_IG41: ; offs=000093H, size=0004H, emitadd
G_M14742_IG42: ; offs=000097H, size=0003H, emitadd
G_M14742_IG43: ; offs=00009AH, size=0003H, emitadd
G_M14742_IG44: ; offs=00009DH, size=0006H, emitadd
G_M14742_IG45: ; offs=0000A3H, size=0002H, emitadd
G_M14742_IG46: ; offs=0000A5H, size=0004H, emitadd
G_M14742_IG47: ; offs=0000A9H, size=0002H, emitadd
G_M14742_IG48: ; offs=0000ABH, size=0004H, emitadd
G_M14742_IG49: ; offs=0000AFH, size=0003H, emitadd
G_M14742_IG50: ; offs=0000B2H, size=0003H, emitadd
G_M14742_IG51: ; offs=0000B5H, size=0006H, emitadd
G_M14742_IG52: ; offs=0000BBH, size=0004H, emitadd
G_M14742_IG53: ; offs=0000BFH, size=0003H, emitadd
G_M14742_IG54: ; offs=0000C2H, size=0003H, emitadd
G_M14742_IG55: ; offs=0000C5H, size=0002H, emitadd
G_M14742_IG56: ; offs=0000C7H, size=0002H, emitadd
G_M14742_IG57: ; offs=0000C9H, size=0004H, emitadd
G_M14742_IG58: ; offs=0000CDH, size=0003H, emitadd
G_M14742_IG59: ; offs=0000D0H, size=0003H, emitadd
G_M14742_IG60: ; offs=0000D3H, size=0006H, emitadd
G_M14742_IG61: ; offs=0000D9H, size=0003H, emitadd
G_M14742_IG62: ; offs=0000DCH, size=0003H, emitadd
G_M14742_IG63: ; offs=0000DFH, size=0002H, emitadd
G_M14742_IG64: ; offs=0000E1H, size=0002H, emitadd
G_M14742_IG65: ; offs=0000E3H, size=0004H, emitadd
G_M14742_IG66: ; offs=0000E7H, size=0002H, emitadd
G_M14742_IG67: ; offs=0000E9H, size=0003H, emitadd
G_M14742_IG68: ; offs=0000ECH, size=0003H, emitadd
G_M14742_IG69: ; offs=0000EFH, size=0002H, emitadd
G_M14742_IG70: ; offs=0000F1H, size=0003H, emitadd
G_M14742_IG71: ; offs=0000F4H, size=0002H, emitadd
G_M14742_IG72: ; offs=0000F6H, size=0003H, emitadd
G_M14742_IG73: ; epilog placeholder, next placeholder=<END>, BB=032A71F8H (BB01), epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000004 {edx}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000004 {edx}, InitByrefRegs=00000000 {}
G_M14742_IG74: ; offs=0001F9H, size=0005H, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M14742_IG75: ; offs=0001FEH, size=0001H, emitadd
G_M14742_IG76: ; offs=0001FFH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M14742_IG77: ; offs=000204H, size=0000H, emitadd <-- Current IG
Recording Var Locations at start of BB01
V01(edx) V00(ecx) V03(eax->esi)
G_M14742_IG77: ; offs=000204H, funclet=00
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M14742_IG01,ins#0,ofs#0) label
__prolog:
IN004c: push edi
IN004d: push esi
IN004e: push ebx
IN004f: sub esp, 16
*************** In genFnPrologCalleeRegArgs() for int regs
*************** In genEnregisterIncomingStackArgs()
IN0050: mov esi, dword ptr [V03 esp+20H]
G_M14742_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=00000000 {}, gcRegGCrefSetCur=00000004 {edx}, gcRegByrefSetCur=00000000 {}
IN0051: add esp, 16
IN0052: pop ebx
IN0053: pop esi
IN0054: pop edi
IN0055: ret 12
G_M14742_IG73: ; offs=0000F9H, funclet=00
0 prologs, 1 epilogs
*************** After prolog / epilog generation
G_M14742_IG01: ; func=00, offs=000000H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M14742_IG02: ; offs=00000AH, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG03: ; offs=00000EH, size=0004H, emitadd
G_M14742_IG04: ; offs=000012H, size=0003H, emitadd
G_M14742_IG05: ; offs=000015H, size=0003H, emitadd
G_M14742_IG06: ; offs=000018H, size=0003H, emitadd
G_M14742_IG07: ; offs=00001BH, size=0004H, emitadd
G_M14742_IG08: ; offs=00001FH, size=0002H, emitadd
G_M14742_IG09: ; offs=000021H, size=0003H, emitadd
G_M14742_IG10: ; offs=000024H, size=0004H, emitadd
G_M14742_IG11: ; offs=000028H, size=0004H, emitadd
G_M14742_IG12: ; offs=00002CH, size=0004H, emitadd
G_M14742_IG13: ; offs=000030H, size=0004H, emitadd
G_M14742_IG14: ; offs=000034H, size=0003H, emitadd
G_M14742_IG15: ; offs=000037H, size=0002H, emitadd
G_M14742_IG16: ; offs=000039H, size=0006H, emitadd
G_M14742_IG17: ; offs=00003FH, size=0002H, emitadd
G_M14742_IG18: ; offs=000041H, size=0006H, emitadd
G_M14742_IG19: ; offs=000047H, size=0005H, emitadd
G_M14742_IG20: ; offs=00004CH, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG21: ; offs=00004FH, size=0006H, emitadd
G_M14742_IG22: ; offs=000055H, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG23: ; offs=000059H, size=0002H, emitadd
G_M14742_IG24: ; offs=00005BH, size=0004H, emitadd
G_M14742_IG25: ; offs=00005FH, size=0004H, emitadd
G_M14742_IG26: ; offs=000063H, size=0003H, emitadd
G_M14742_IG27: ; offs=000066H, size=0004H, emitadd
G_M14742_IG28: ; offs=00006AH, size=0004H, emitadd
G_M14742_IG29: ; offs=00006EH, size=0004H, emitadd
G_M14742_IG30: ; offs=000072H, size=0004H, emitadd
G_M14742_IG31: ; offs=000076H, size=0003H, emitadd
G_M14742_IG32: ; offs=000079H, size=0002H, emitadd
G_M14742_IG33: ; offs=00007BH, size=0006H, emitadd
G_M14742_IG34: ; offs=000081H, size=0002H, emitadd
G_M14742_IG35: ; offs=000083H, size=0006H, emitadd
G_M14742_IG36: ; offs=000089H, size=0005H, emitadd
G_M14742_IG37: ; offs=00008EH, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG38: ; offs=000091H, size=0006H, emitadd
G_M14742_IG39: ; offs=000097H, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
G_M14742_IG40: ; offs=00009BH, size=0002H, emitadd
G_M14742_IG41: ; offs=00009DH, size=0004H, emitadd
G_M14742_IG42: ; offs=0000A1H, size=0003H, emitadd
G_M14742_IG43: ; offs=0000A4H, size=0003H, emitadd
G_M14742_IG44: ; offs=0000A7H, size=0006H, emitadd
G_M14742_IG45: ; offs=0000ADH, size=0002H, emitadd
G_M14742_IG46: ; offs=0000AFH, size=0004H, emitadd
G_M14742_IG47: ; offs=0000B3H, size=0002H, emitadd
G_M14742_IG48: ; offs=0000B5H, size=0004H, emitadd
G_M14742_IG49: ; offs=0000B9H, size=0003H, emitadd
G_M14742_IG50: ; offs=0000BCH, size=0003H, emitadd
G_M14742_IG51: ; offs=0000BFH, size=0006H, emitadd
G_M14742_IG52: ; offs=0000C5H, size=0004H, emitadd
G_M14742_IG53: ; offs=0000C9H, size=0003H, emitadd
G_M14742_IG54: ; offs=0000CCH, size=0003H, emitadd
G_M14742_IG55: ; offs=0000CFH, size=0002H, emitadd
G_M14742_IG56: ; offs=0000D1H, size=0002H, emitadd
G_M14742_IG57: ; offs=0000D3H, size=0004H, emitadd
G_M14742_IG58: ; offs=0000D7H, size=0003H, emitadd
G_M14742_IG59: ; offs=0000DAH, size=0003H, emitadd
G_M14742_IG60: ; offs=0000DDH, size=0006H, emitadd
G_M14742_IG61: ; offs=0000E3H, size=0003H, emitadd
G_M14742_IG62: ; offs=0000E6H, size=0003H, emitadd
G_M14742_IG63: ; offs=0000E9H, size=0002H, emitadd
G_M14742_IG64: ; offs=0000EBH, size=0002H, emitadd
G_M14742_IG65: ; offs=0000EDH, size=0004H, emitadd
G_M14742_IG66: ; offs=0000F1H, size=0002H, emitadd
G_M14742_IG67: ; offs=0000F3H, size=0003H, emitadd
G_M14742_IG68: ; offs=0000F6H, size=0003H, emitadd
G_M14742_IG69: ; offs=0000F9H, size=0002H, emitadd
G_M14742_IG70: ; offs=0000FBH, size=0003H, emitadd
G_M14742_IG71: ; offs=0000FEH, size=0002H, emitadd
G_M14742_IG72: ; offs=000100H, size=0003H, emitadd
G_M14742_IG73: ; offs=000103H, size=0009H, epilog, nogc, emitadd
G_M14742_IG74: ; offs=00010CH, size=0005H, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M14742_IG75: ; offs=000111H, size=0001H, emitadd
G_M14742_IG76: ; offs=000112H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M14742_IG77: ; offs=000117H, size=0001H, emitadd
*************** In emitJumpDistBind()
Binding: IN000f: 000000 js L_M14742_BB04
Binding L_M14742_BB04 to G_M14742_IG20
Estimate of fwd jump [032F9540/015]: 0039 -> 004C = 0011
Shrinking jump [032F9540/015]
Binding: IN0011: 000000 jne L_M14742_BB02
Binding L_M14742_BB02 to G_M14742_IG74
Estimate of fwd jump [032F95F4/017]: 003D -> 0108 = 00C9
Binding: IN0012: 000000 jmp L_M14742_BB05
Binding L_M14742_BB05 to G_M14742_IG22
Estimate of fwd jump [032F9658/018]: 0043 -> 0051 = 000C
Shrinking jump [032F9658/018]
Binding: IN0014: 000000 jne L_M14742_BB02
Binding L_M14742_BB02 to G_M14742_IG74
Estimate of fwd jump [032F9724/020]: 0048 -> 0105 = 00BB
Binding: IN0020: 000000 js L_M14742_BB06
Binding L_M14742_BB06 to G_M14742_IG37
Estimate of fwd jump [032F9EF8/032]: 0074 -> 0087 = 0011
Shrinking jump [032F9EF8/032]
Binding: IN0022: 000000 jne L_M14742_BB02
Binding L_M14742_BB02 to G_M14742_IG74
Estimate of fwd jump [032F9FAC/034]: 0078 -> 0101 = 0087
Binding: IN0023: 000000 jmp L_M14742_BB07
Binding L_M14742_BB07 to G_M14742_IG39
Estimate of fwd jump [032FA010/035]: 007E -> 008C = 000C
Shrinking jump [032FA010/035]
Binding: IN0025: 000000 jne L_M14742_BB02
Binding L_M14742_BB02 to G_M14742_IG74
Estimate of fwd jump [032FA0DC/037]: 0083 -> 00FE = 0079
Shrinking jump [032FA0DC/037]
Binding: IN002b: 000000 jae L_M14742_BB03
Binding L_M14742_BB03 to G_M14742_IG76
Estimate of fwd jump [032FA3F4/043]: 0095 -> 0100 = 0069
Shrinking jump [032FA3F4/043]
Binding: IN0032: 000000 jae L_M14742_BB03
Binding L_M14742_BB03 to G_M14742_IG76
Estimate of fwd jump [032FA780/050]: 00A9 -> 00FC = 0051
Shrinking jump [032FA780/050]
Binding: IN003b: 000000 jae L_M14742_BB03
Binding L_M14742_BB03 to G_M14742_IG76
Estimate of fwd jump [032FABE4/059]: 00C3 -> 00F8 = 0033
Shrinking jump [032FABE4/059]
Total shrinkage = 30, min extra jump size = 8
Iterating branch shortening. Iteration = 2
Estimate of fwd jump [032F95F4/017]: 003D -> 00EE = 00AF
Estimate of fwd jump [032F9724/020]: 0048 -> 00EE = 00A4
Estimate of fwd jump [032F9FAC/034]: 0078 -> 00EE = 0074
Shrinking jump [032F9FAC/034]
Total shrinkage = 4, min extra jump size = 37
Hot code size = 0xF6 bytes
Cold code size = 0x0 bytes
*************** In emitEndCodeGen()
***************************************************************************
Instructions as they come out of the scheduler
G_M14742_IG01: ; func=00, offs=000000H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN004c: 000000 57 push edi
IN004d: 000001 56 push esi
IN004e: 000002 53 push ebx
IN004f: 000003 83EC10 sub esp, 16
IN0050: 000006 8B742420 mov esi, dword ptr [esp+20H]
G_M14742_IG02: ; func=00, offs=00000AH, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
New gcrReg live regs=00000004 {edx}
gcrReg +[edx]
IN0001: 00000A 8B7C2424 mov edi, dword ptr [esp+24H]
G_M14742_IG03: ; func=00, offs=00000EH, size=0004H, emitadd
IN0002: 00000E 8B5C2428 mov ebx, dword ptr [esp+28H]
G_M14742_IG04: ; func=00, offs=000012H, size=0003H, emitadd
IN0003: 000012 83EF01 sub edi, 1
G_M14742_IG05: ; func=00, offs=000015H, size=0003H, emitadd
IN0004: 000015 83DB00 sbb ebx, 0
G_M14742_IG06: ; func=00, offs=000018H, size=0003H, emitadd
IN0005: 000018 891C24 mov dword ptr [esp], ebx
G_M14742_IG07: ; func=00, offs=00001BH, size=0004H, emitadd
IN0006: 00001B 88742420 mov byte ptr [esp+20H], sl
G_M14742_IG08: ; func=00, offs=00001FH, size=0002H, emitadd
IN0007: 00001F 8BC6 mov eax, esi
G_M14742_IG09: ; func=00, offs=000021H, size=0003H, emitadd
IN0008: 000021 0FB6D8 movzx ebx, al
G_M14742_IG10: ; func=00, offs=000024H, size=0004H, emitadd
IN0009: 000024 895C240C mov dword ptr [esp+0CH], ebx
G_M14742_IG11: ; func=00, offs=000028H, size=0004H, emitadd
IN000a: 000028 8B742424 mov esi, dword ptr [esp+24H]
G_M14742_IG12: ; func=00, offs=00002CH, size=0004H, emitadd
IN000b: 00002C 8B5C2428 mov ebx, dword ptr [esp+28H]
G_M14742_IG13: ; func=00, offs=000030H, size=0004H, emitadd
IN000c: 000030 2B74240C sub esi, dword ptr [esp+0CH]
G_M14742_IG14: ; func=00, offs=000034H, size=0003H, emitadd
IN000d: 000034 83DB00 sbb ebx, 0
G_M14742_IG15: ; func=00, offs=000037H, size=0002H, emitadd
IN000e: 000037 85F6 test esi, esi
G_M14742_IG16: ; func=00, offs=000039H, size=0002H, isz, emitadd
IN000f: 000039 780A js SHORT G_M14742_IG20
G_M14742_IG17: ; func=00, offs=00003BH, size=0002H, emitadd
IN0010: 00003B 85DB test ebx, ebx
G_M14742_IG18: ; func=00, offs=00003DH, size=0006H, emitadd
IN0011: 00003D 0F85A7000000 jne G_M14742_IG74
G_M14742_IG19: ; func=00, offs=000043H, size=0002H, isz, emitadd
IN0012: 000043 EB09 jmp SHORT G_M14742_IG22
G_M14742_IG20: ; func=00, offs=000045H, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
IN0013: 000045 83FBFF cmp ebx, -1
G_M14742_IG21: ; func=00, offs=000048H, size=0006H, emitadd
IN0014: 000048 0F859C000000 jne G_M14742_IG74
G_M14742_IG22: ; func=00, offs=00004EH, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
IN0015: 00004E 8974240C mov dword ptr [esp+0CH], esi
G_M14742_IG23: ; func=00, offs=000052H, size=0002H, emitadd
IN0016: 000052 33DB xor ebx, ebx
G_M14742_IG24: ; func=00, offs=000054H, size=0004H, emitadd
IN0017: 000054 895C2408 mov dword ptr [esp+08H], ebx
G_M14742_IG25: ; func=00, offs=000058H, size=0004H, emitadd
IN0018: 000058 8B442420 mov eax, dword ptr [esp+20H]
G_M14742_IG26: ; func=00, offs=00005CH, size=0003H, emitadd
IN0019: 00005C 0FB6D8 movzx ebx, al
G_M14742_IG27: ; func=00, offs=00005FH, size=0004H, emitadd
IN001a: 00005F 895C2404 mov dword ptr [esp+04H], ebx
G_M14742_IG28: ; func=00, offs=000063H, size=0004H, emitadd
IN001b: 000063 8B742424 mov esi, dword ptr [esp+24H]
G_M14742_IG29: ; func=00, offs=000067H, size=0004H, emitadd
IN001c: 000067 8B5C2428 mov ebx, dword ptr [esp+28H]
G_M14742_IG30: ; func=00, offs=00006BH, size=0004H, emitadd
IN001d: 00006B 2B742404 sub esi, dword ptr [esp+04H]
G_M14742_IG31: ; func=00, offs=00006FH, size=0003H, emitadd
IN001e: 00006F 83DB00 sbb ebx, 0
G_M14742_IG32: ; func=00, offs=000072H, size=0002H, emitadd
IN001f: 000072 85F6 test esi, esi
G_M14742_IG33: ; func=00, offs=000074H, size=0002H, isz, emitadd
IN0020: 000074 7806 js SHORT G_M14742_IG37
G_M14742_IG34: ; func=00, offs=000076H, size=0002H, emitadd
IN0021: 000076 85DB test ebx, ebx
G_M14742_IG35: ; func=00, offs=000078H, size=0002H, isz, emitadd
IN0022: 000078 7570 jne SHORT G_M14742_IG74
G_M14742_IG36: ; func=00, offs=00007AH, size=0002H, isz, emitadd
IN0023: 00007A EB05 jmp SHORT G_M14742_IG39
G_M14742_IG37: ; func=00, offs=00007CH, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
IN0024: 00007C 83FBFF cmp ebx, -1
G_M14742_IG38: ; func=00, offs=00007FH, size=0002H, isz, emitadd
IN0025: 00007F 7569 jne SHORT G_M14742_IG74
G_M14742_IG39: ; func=00, offs=000081H, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
IN0026: 000081 89742404 mov dword ptr [esp+04H], esi
G_M14742_IG40: ; func=00, offs=000085H, size=0002H, emitadd
gcrReg +[ebx]
IN0027: 000085 8BDA mov ebx, edx
G_M14742_IG41: ; func=00, offs=000087H, size=0004H, emitadd
IN0028: 000087 8B74240C mov esi, dword ptr [esp+0CH]
G_M14742_IG42: ; func=00, offs=00008BH, size=0003H, emitadd
IN0029: 00008B 2B7314 sub esi, dword ptr [ebx+20]
G_M14742_IG43: ; func=00, offs=00008EH, size=0003H, emitadd
IN002a: 00008E 3B7308 cmp esi, dword ptr [ebx+8]
G_M14742_IG44: ; func=00, offs=000091H, size=0002H, isz, emitadd
IN002b: 000091 735D jae SHORT G_M14742_IG76
G_M14742_IG45: ; func=00, offs=000093H, size=0002H, emitadd
IN002c: 000093 8BDA mov ebx, edx
G_M14742_IG46: ; func=00, offs=000095H, size=0004H, emitadd
IN002d: 000095 8974240C mov dword ptr [esp+0CH], esi
G_M14742_IG47: ; func=00, offs=000099H, size=0002H, emitadd
IN002e: 000099 8BDA mov ebx, edx
G_M14742_IG48: ; func=00, offs=00009BH, size=0004H, emitadd
IN002f: 00009B 8B742408 mov esi, dword ptr [esp+08H]
G_M14742_IG49: ; func=00, offs=00009FH, size=0003H, emitadd
IN0030: 00009F 2B7318 sub esi, dword ptr [ebx+24]
G_M14742_IG50: ; func=00, offs=0000A2H, size=0003H, emitadd
IN0031: 0000A2 3B730C cmp esi, dword ptr [ebx+12]
G_M14742_IG51: ; func=00, offs=0000A5H, size=0002H, isz, emitadd
IN0032: 0000A5 7349 jae SHORT G_M14742_IG76
G_M14742_IG52: ; func=00, offs=0000A7H, size=0004H, emitadd
gcrReg -[ebx]
IN0033: 0000A7 8B5C240C mov ebx, dword ptr [esp+0CH]
G_M14742_IG53: ; func=00, offs=0000ABH, size=0003H, emitadd
IN0034: 0000AB 8B420C mov eax, dword ptr [edx+12]
G_M14742_IG54: ; func=00, offs=0000AEH, size=0003H, emitadd
IN0035: 0000AE 0FAFC3 imul eax, ebx
G_M14742_IG55: ; func=00, offs=0000B1H, size=0002H, emitadd
IN0036: 0000B1 03C6 add eax, esi
G_M14742_IG56: ; func=00, offs=0000B3H, size=0002H, emitadd
gcrReg +[ebx]
IN0037: 0000B3 8BDA mov ebx, edx
G_M14742_IG57: ; func=00, offs=0000B5H, size=0004H, emitadd
IN0038: 0000B5 8B742404 mov esi, dword ptr [esp+04H]
G_M14742_IG58: ; func=00, offs=0000B9H, size=0003H, emitadd
IN0039: 0000B9 2B731C sub esi, dword ptr [ebx+28]
G_M14742_IG59: ; func=00, offs=0000BCH, size=0003H, emitadd
IN003a: 0000BC 3B7310 cmp esi, dword ptr [ebx+16]
G_M14742_IG60: ; func=00, offs=0000BFH, size=0002H, isz, emitadd
IN003b: 0000BF 732F jae SHORT G_M14742_IG76
G_M14742_IG61: ; func=00, offs=0000C1H, size=0003H, emitadd
gcrReg -[ebx]
IN003c: 0000C1 8B5A10 mov ebx, dword ptr [edx+16]
G_M14742_IG62: ; func=00, offs=0000C4H, size=0003H, emitadd
IN003d: 0000C4 0FAFD8 imul ebx, eax
G_M14742_IG63: ; func=00, offs=0000C7H, size=0002H, emitadd
IN003e: 0000C7 03F3 add esi, ebx
G_M14742_IG64: ; func=00, offs=0000C9H, size=0002H, emitadd
gcrReg +[ebx]
IN003f: 0000C9 8BDA mov ebx, edx
G_M14742_IG65: ; func=00, offs=0000CBH, size=0004H, emitadd
byrReg +[esi]
IN0040: 0000CB 8D74F320 lea esi, bword ptr [ebx+8*esi+32]
G_M14742_IG66: ; func=00, offs=0000CFH, size=0002H, emitadd
IN0041: 0000CF 893E mov dword ptr [esi], edi
G_M14742_IG67: ; func=00, offs=0000D1H, size=0003H, emitadd
gcrReg -[ebx]
IN0042: 0000D1 8B1C24 mov ebx, dword ptr [esp]
G_M14742_IG68: ; func=00, offs=0000D4H, size=0003H, emitadd
IN0043: 0000D4 895E04 mov dword ptr [esi+4], ebx
G_M14742_IG69: ; func=00, offs=0000D7H, size=0002H, emitadd
byrReg -[esi]
IN0044: 0000D7 8BF1 mov esi, ecx
G_M14742_IG70: ; func=00, offs=0000D9H, size=0003H, emitadd
IN0045: 0000D9 8D34FE lea esi, [esi+8*edi]
G_M14742_IG71: ; func=00, offs=0000DCH, size=0002H, emitadd
IN0046: 0000DC 8B06 mov eax, dword ptr [esi]
G_M14742_IG72: ; func=00, offs=0000DEH, size=0003H, emitadd
gcrReg -[edx]
IN0047: 0000DE 8B5604 mov edx, dword ptr [esi+4]
G_M14742_IG73: ; func=00, offs=0000E1H, size=0009H, epilog, nogc, emitadd
IN0051: 0000E1 83C410 add esp, 16
IN0052: 0000E4 5B pop ebx
IN0053: 0000E5 5E pop esi
IN0054: 0000E6 5F pop edi
IN0055: 0000E7 C20C00 ret 12
G_M14742_IG74: ; func=00, offs=0000EAH, size=0005H, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
IN0048: 0000EA E8A9BE6551 call CORINFO_HELP_OVERFLOW
G_M14742_IG75: ; func=00, offs=0000EFH, size=0001H, emitadd
IN0049: 0000EF CC int3
G_M14742_IG76: ; func=00, offs=0000F0H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN004a: 0000F0 E8A38E6551 call CORINFO_HELP_RNGCHKFAIL
G_M14742_IG77: ; func=00, offs=0000F5H, size=0001H, emitadd
IN004b: 0000F5 CC int3
Allocated method code size = 246 , actual size = 246
*************** After end code gen, before unwindEmit()
G_M14742_IG01: ; func=00, offs=000000H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN004c: 000000 push edi
IN004d: 000001 push esi
IN004e: 000002 push ebx
IN004f: 000003 sub esp, 16
IN0050: 000006 mov esi, dword ptr [V03 esp+20H]
G_M14742_IG02: ; offs=00000AH, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
IN0001: 00000A mov edi, dword ptr [V05 esp+24H]
G_M14742_IG03: ; offs=00000EH, size=0004H, emitadd
IN0002: 00000E mov ebx, dword ptr [V06 esp+28H]
G_M14742_IG04: ; offs=000012H, size=0003H, emitadd
IN0003: 000012 sub edi, 1
G_M14742_IG05: ; offs=000015H, size=0003H, emitadd
IN0004: 000015 sbb ebx, 0
G_M14742_IG06: ; offs=000018H, size=0003H, emitadd
IN0005: 000018 mov dword ptr [V08 esp], ebx
G_M14742_IG07: ; offs=00001BH, size=0004H, emitadd
IN0006: 00001B mov byte ptr [V03 esp+20H], sl
G_M14742_IG08: ; offs=00001FH, size=0002H, emitadd
IN0007: 00001F mov eax, esi
G_M14742_IG09: ; offs=000021H, size=0003H, emitadd
IN0008: 000021 movzx ebx, al
G_M14742_IG10: ; offs=000024H, size=0004H, emitadd
IN0009: 000024 mov dword ptr [TEMP_03 esp+0CH], ebx
G_M14742_IG11: ; offs=000028H, size=0004H, emitadd
IN000a: 000028 mov esi, dword ptr [V05 esp+24H]
G_M14742_IG12: ; offs=00002CH, size=0004H, emitadd
IN000b: 00002C mov ebx, dword ptr [V06 esp+28H]
G_M14742_IG13: ; offs=000030H, size=0004H, emitadd
IN000c: 000030 sub esi, dword ptr [TEMP_03 esp+0CH]
G_M14742_IG14: ; offs=000034H, size=0003H, emitadd
IN000d: 000034 sbb ebx, 0
G_M14742_IG15: ; offs=000037H, size=0002H, emitadd
IN000e: 000037 test esi, esi
G_M14742_IG16: ; offs=000039H, size=0002H, isz, emitadd
IN000f: 000039 js SHORT G_M14742_IG20
G_M14742_IG17: ; offs=00003BH, size=0002H, emitadd
IN0010: 00003B test ebx, ebx
G_M14742_IG18: ; offs=00003DH, size=0006H, emitadd
IN0011: 00003D jne G_M14742_IG74
G_M14742_IG19: ; offs=000043H, size=0002H, isz, emitadd
IN0012: 000043 jmp SHORT G_M14742_IG22
G_M14742_IG20: ; offs=000045H, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
IN0013: 000045 cmp ebx, -1
G_M14742_IG21: ; offs=000048H, size=0006H, emitadd
IN0014: 000048 jne G_M14742_IG74
G_M14742_IG22: ; offs=00004EH, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
IN0015: 00004E mov dword ptr [TEMP_03 esp+0CH], esi
G_M14742_IG23: ; offs=000052H, size=0002H, emitadd
IN0016: 000052 xor ebx, ebx
G_M14742_IG24: ; offs=000054H, size=0004H, emitadd
IN0017: 000054 mov dword ptr [TEMP_02 esp+08H], ebx
G_M14742_IG25: ; offs=000058H, size=0004H, emitadd
IN0018: 000058 mov eax, dword ptr [V03 esp+20H]
G_M14742_IG26: ; offs=00005CH, size=0003H, emitadd
IN0019: 00005C movzx ebx, al
G_M14742_IG27: ; offs=00005FH, size=0004H, emitadd
IN001a: 00005F mov dword ptr [TEMP_01 esp+04H], ebx
G_M14742_IG28: ; offs=000063H, size=0004H, emitadd
IN001b: 000063 mov esi, dword ptr [V05 esp+24H]
G_M14742_IG29: ; offs=000067H, size=0004H, emitadd
IN001c: 000067 mov ebx, dword ptr [V06 esp+28H]
G_M14742_IG30: ; offs=00006BH, size=0004H, emitadd
IN001d: 00006B sub esi, dword ptr [TEMP_01 esp+04H]
G_M14742_IG31: ; offs=00006FH, size=0003H, emitadd
IN001e: 00006F sbb ebx, 0
G_M14742_IG32: ; offs=000072H, size=0002H, emitadd
IN001f: 000072 test esi, esi
G_M14742_IG33: ; offs=000074H, size=0002H, isz, emitadd
IN0020: 000074 js SHORT G_M14742_IG37
G_M14742_IG34: ; offs=000076H, size=0002H, emitadd
IN0021: 000076 test ebx, ebx
G_M14742_IG35: ; offs=000078H, size=0002H, isz, emitadd
IN0022: 000078 jne SHORT G_M14742_IG74
G_M14742_IG36: ; offs=00007AH, size=0002H, isz, emitadd
IN0023: 00007A jmp SHORT G_M14742_IG39
G_M14742_IG37: ; offs=00007CH, size=0003H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
IN0024: 00007C cmp ebx, -1
G_M14742_IG38: ; offs=00007FH, size=0002H, isz, emitadd
IN0025: 00007F jne SHORT G_M14742_IG74
G_M14742_IG39: ; offs=000081H, size=0004H, gcrefRegs=00000004 {edx}, byrefRegs=00000000 {}, byref
IN0026: 000081 mov dword ptr [TEMP_01 esp+04H], esi
G_M14742_IG40: ; offs=000085H, size=0002H, emitadd
IN0027: 000085 mov ebx, edx
G_M14742_IG41: ; offs=000087H, size=0004H, emitadd
IN0028: 000087 mov esi, dword ptr [TEMP_03 esp+0CH]
G_M14742_IG42: ; offs=00008BH, size=0003H, emitadd
IN0029: 00008B sub esi, dword ptr [ebx+20]
G_M14742_IG43: ; offs=00008EH, size=0003H, emitadd
IN002a: 00008E cmp esi, dword ptr [ebx+8]
G_M14742_IG44: ; offs=000091H, size=0002H, isz, emitadd
IN002b: 000091 jae SHORT G_M14742_IG76
G_M14742_IG45: ; offs=000093H, size=0002H, emitadd
IN002c: 000093 mov ebx, edx
G_M14742_IG46: ; offs=000095H, size=0004H, emitadd
IN002d: 000095 mov dword ptr [TEMP_03 esp+0CH], esi
G_M14742_IG47: ; offs=000099H, size=0002H, emitadd
IN002e: 000099 mov ebx, edx
G_M14742_IG48: ; offs=00009BH, size=0004H, emitadd
IN002f: 00009B mov esi, dword ptr [TEMP_02 esp+08H]
G_M14742_IG49: ; offs=00009FH, size=0003H, emitadd
IN0030: 00009F sub esi, dword ptr [ebx+24]
G_M14742_IG50: ; offs=0000A2H, size=0003H, emitadd
IN0031: 0000A2 cmp esi, dword ptr [ebx+12]
G_M14742_IG51: ; offs=0000A5H, size=0002H, isz, emitadd
IN0032: 0000A5 jae SHORT G_M14742_IG76
G_M14742_IG52: ; offs=0000A7H, size=0004H, emitadd
IN0033: 0000A7 mov ebx, dword ptr [TEMP_03 esp+0CH]
G_M14742_IG53: ; offs=0000ABH, size=0003H, emitadd
IN0034: 0000AB mov eax, dword ptr [edx+12]
G_M14742_IG54: ; offs=0000AEH, size=0003H, emitadd
IN0035: 0000AE imul eax, ebx
G_M14742_IG55: ; offs=0000B1H, size=0002H, emitadd
IN0036: 0000B1 add eax, esi
G_M14742_IG56: ; offs=0000B3H, size=0002H, emitadd
IN0037: 0000B3 mov ebx, edx
G_M14742_IG57: ; offs=0000B5H, size=0004H, emitadd
IN0038: 0000B5 mov esi, dword ptr [TEMP_01 esp+04H]
G_M14742_IG58: ; offs=0000B9H, size=0003H, emitadd
IN0039: 0000B9 sub esi, dword ptr [ebx+28]
G_M14742_IG59: ; offs=0000BCH, size=0003H, emitadd
IN003a: 0000BC cmp esi, dword ptr [ebx+16]
G_M14742_IG60: ; offs=0000BFH, size=0002H, isz, emitadd
IN003b: 0000BF jae SHORT G_M14742_IG76
G_M14742_IG61: ; offs=0000C1H, size=0003H, emitadd
IN003c: 0000C1 mov ebx, dword ptr [edx+16]
G_M14742_IG62: ; offs=0000C4H, size=0003H, emitadd
IN003d: 0000C4 imul ebx, eax
G_M14742_IG63: ; offs=0000C7H, size=0002H, emitadd
IN003e: 0000C7 add esi, ebx
G_M14742_IG64: ; offs=0000C9H, size=0002H, emitadd
IN003f: 0000C9 mov ebx, edx
G_M14742_IG65: ; offs=0000CBH, size=0004H, emitadd
IN0040: 0000CB lea esi, bword ptr [ebx+8*esi+32]
G_M14742_IG66: ; offs=0000CFH, size=0002H, emitadd
IN0041: 0000CF mov dword ptr [esi], edi
G_M14742_IG67: ; offs=0000D1H, size=0003H, emitadd
IN0042: 0000D1 mov ebx, dword ptr [V08 esp]
G_M14742_IG68: ; offs=0000D4H, size=0003H, emitadd
IN0043: 0000D4 mov dword ptr [esi+4], ebx
G_M14742_IG69: ; offs=0000D7H, size=0002H, emitadd
IN0044: 0000D7 mov esi, ecx
G_M14742_IG70: ; offs=0000D9H, size=0003H, emitadd
IN0045: 0000D9 lea esi, [esi+8*edi]
G_M14742_IG71: ; offs=0000DCH, size=0002H, emitadd
IN0046: 0000DC mov eax, dword ptr [esi]
G_M14742_IG72: ; offs=0000DEH, size=0003H, emitadd
IN0047: 0000DE mov edx, dword ptr [esi+4]
G_M14742_IG73: ; offs=0000E1H, size=0009H, epilog, nogc, emitadd
IN0051: 0000E1 add esp, 16
IN0052: 0000E4 pop ebx
IN0053: 0000E5 pop esi
IN0054: 0000E6 pop edi
IN0055: 0000E7 ret 12
G_M14742_IG74: ; offs=0000EAH, size=0005H, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
IN0048: 0000EA call CORINFO_HELP_OVERFLOW
G_M14742_IG75: ; offs=0000EFH, size=0001H, emitadd
IN0049: 0000EF int3
G_M14742_IG76: ; offs=0000F0H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN004a: 0000F0 call CORINFO_HELP_RNGCHKFAIL
G_M14742_IG77: ; offs=0000F5H, size=0001H, emitadd
IN004b: 0000F5 int3
*************** In genIPmappingGen()
IP mapping count : 5
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000000A ( STACK_EMPTY )
IL offs 0x0018 : 0x000000D7
IL offs EPILOG : 0x000000E1 ( STACK_EMPTY )
IL offs NO_MAP : 0x000000EA ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 7
*************** Variable debug info
7 vars
1( UNKNOWN) : From 00000000h to 0000000Ah, in edx
2( UNKNOWN) : From 00000000h to 0000000Ah, in esp[8] (1 slot)
3( UNKNOWN) : From 00000000h to 0000000Ah, in esp[4] (1 slot)
0( UNKNOWN) : From 00000000h to 0000000Ah, in ecx
3( UNKNOWN) : From 0000000Ah to 0000005Ch, in esi
1( UNKNOWN) : From 0000000Ah to 000000C9h, in edx
0( UNKNOWN) : From 0000000Ah to 000000D7h, in ecx
*************** In gcInfoBlockHdrSave()
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
*************** In gcInfoBlockHdrSave()
GCINFO: methodSize = 00F6
GCINFO: prologSize = 0006
GCINFO: epilogSize = 0009
GC Info for method TestApp:test_25(int,ref,long,ubyte):long
GC info size = 10
Method info block:
method size = 00F6
prolog size = 6
epilog size = 9
epilog count = 1
epilog end = no
callee-saved regs = EDI ESI EBX
ebp frame = no
fully interruptible= no
double align = no
arguments size = 3 DWORDs
stack frame size = 4 DWORDs
untracked count = 0
var ptr tab count = 0
epilog # 0 at 00E1
81 76 D5 8B 84 |
AF 2B 81 61 |
Pointer table:
FF |
Allocations for TestApp:test_25(int,ref,long,ubyte):long (MethodHash=e5bcc669)
count: 1183, size: 68960, max = 2560
allocateMemory: 131072, nraUsed: 80112
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 0 | 0.00%
ASTNode | 14812 | 21.48%
InstDesc | 7920 | 11.48%
ImpStack | 0 | 0.00%
BasicBlock | 1348 | 1.95%
fgArgInfo | 0 | 0.00%
fgArgInfoPtrArr | 0 | 0.00%
FlowList | 0 | 0.00%
TreeStatementList | 128 | 0.19%
SiScope | 296 | 0.43%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 64 | 0.09%
LSRA | 1748 | 2.53%
LSRA_Interval | 2080 | 3.02%
LSRA_RefPosition | 5668 | 8.22%
Reachability | 8 | 0.01%
SSA | 460 | 0.67%
ValueNumber | 8784 | 12.74%
LvaTable | 1408 | 2.04%
UnwindInfo | 0 | 0.00%
hashBv | 60 | 0.09%
bitset | 560 | 0.81%
FixedBitVect | 0 | 0.00%
AsIAllocator | 6404 | 9.29%
IndirAssignMap | 40 | 0.06%
FieldSeqStore | 108 | 0.16%
ZeroOffsetFieldMap | 88 | 0.13%
ArrayInfoMap | 40 | 0.06%
HeapPhiArg | 0 | 0.00%
CSE | 880 | 1.28%
GC | 208 | 0.30%
CorSig | 0 | 0.00%
Inlining | 56 | 0.08%
ArrayStack | 64 | 0.09%
DebugInfo | 240 | 0.35%
DebugOnly | 14972 | 21.71%
Codegen | 0 | 0.00%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 516 | 0.75%
****** DONE compiling TestApp:test_25(int,ref,long,ubyte):long
Expected: 100
Actual: 255
END EXECUTION - FAILED
FAILED
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