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phire/1_test.asm

Created March 21, 2021 03:52
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1_test.asm
%ifdef CONFIG
{
"Match": "All",
"RegData": {
"MM7": ["0xfb53d1c000000000", "0x4002"]
}
}
%endif
inner:
; calcuate pi + pi + pi + pi + pi
fld dword [rel pi]
fld dword [rel pi]
fld dword [rel pi]
fld dword [rel pi]
fld dword [rel pi]
faddp
faddp
faddp
faddp
hlt
align 8
pi: dd 0x40490fdb ; 3.14...
one: dd 0x3f800000 ; 1.0
ptone: dd 0x3dcccccd ; 0.1
Raw
2_Before.ir
(%ssa0) IRHeader #0x10000, %ssa2, #0
(%ssa2) CodeBlock %ssa3, %ssa130
(%ssa3 i0) BeginBlock %ssa2
%ssa4 i64 = EntrypointOffset #0x28
%ssa5 i32 = LoadMemTSO %ssa4 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa6 i128 = F80CVTTo %ssa5 i32, #0x4
%ssa7 i8 = LoadContext #0x1d3, GPR
(%ssa8 i0) InlineConstant #0x7
(%ssa9 i0) InlineConstant #0x7
(%ssa10 i0) InlineConstant #0x7
(%ssa11 i0) InlineConstant #0x7
(%ssa12 i0) InlineConstant #0x7
(%ssa13 i0) InlineConstant #0x7
(%ssa14 i0) InlineConstant #0x7
(%ssa15 i0) InlineConstant #0x7
(%ssa16 i0) InlineConstant #0x7
(%ssa17 i0) InlineConstant #0x7
(%ssa18 i0) InlineConstant #0x7
(%ssa19 i0) InlineConstant #0x7
(%ssa20 i0) InlineConstant #0x7
(%ssa21 i0) InlineConstant #0x1
(%ssa22 i0) InlineConstant #0x1
(%ssa23 i0) InlineConstant #0x1
(%ssa24 i0) InlineConstant #0x1
(%ssa25 i0) InlineConstant #0x1
(%ssa26 i0) InlineConstant #0x1
(%ssa27 i0) InlineConstant #0x1
(%ssa28 i0) InlineConstant #0x1
(%ssa29 i0) InlineConstant #0x1
(%ssa30 i0) InlineConstant #0x1
(%ssa31 i0) InlineConstant #0x1
(%ssa32 i0) InlineConstant #0x1
(%ssa33 i0) InlineConstant #0x1
%ssa34 i64 = Sub %ssa7 i8, %ssa33
%ssa35 i64 = And %ssa34 i64, %ssa20
(%ssa36 i8) StoreContext %ssa35 i64, #0x1d3, GPR
%ssa37 i8 = Bfe %ssa35 i64, #0x8, #0x0
(%ssa38 i0) StoreContextIndexed %ssa6 i128, %ssa37 i8, #0x10, #0x1e0, #0x10, FPR
%ssa39 i64 = EntrypointOffset #0x28
%ssa40 i32 = LoadMemTSO %ssa39 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa41 i128 = F80CVTTo %ssa40 i32, #0x4
%ssa42 i8 = LoadContext #0x1d3, GPR
%ssa43 i64 = Sub %ssa42 i8, %ssa32
%ssa44 i64 = And %ssa43 i64, %ssa19
(%ssa45 i8) StoreContext %ssa44 i64, #0x1d3, GPR
%ssa46 i8 = Bfe %ssa44 i64, #0x8, #0x0
(%ssa47 i0) StoreContextIndexed %ssa41 i128, %ssa46 i8, #0x10, #0x1e0, #0x10, FPR
%ssa48 i64 = EntrypointOffset #0x28
%ssa49 i32 = LoadMemTSO %ssa48 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa50 i128 = F80CVTTo %ssa49 i32, #0x4
%ssa51 i8 = LoadContext #0x1d3, GPR
%ssa52 i64 = Sub %ssa51 i8, %ssa31
%ssa53 i64 = And %ssa52 i64, %ssa18
(%ssa54 i8) StoreContext %ssa53 i64, #0x1d3, GPR
%ssa55 i8 = Bfe %ssa53 i64, #0x8, #0x0
(%ssa56 i0) StoreContextIndexed %ssa50 i128, %ssa55 i8, #0x10, #0x1e0, #0x10, FPR
%ssa57 i64 = EntrypointOffset #0x28
%ssa58 i32 = LoadMemTSO %ssa57 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa59 i128 = F80CVTTo %ssa58 i32, #0x4
%ssa60 i8 = LoadContext #0x1d3, GPR
%ssa61 i64 = Sub %ssa60 i8, %ssa30
%ssa62 i64 = And %ssa61 i64, %ssa17
(%ssa63 i8) StoreContext %ssa62 i64, #0x1d3, GPR
%ssa64 i8 = Bfe %ssa62 i64, #0x8, #0x0
(%ssa65 i0) StoreContextIndexed %ssa59 i128, %ssa64 i8, #0x10, #0x1e0, #0x10, FPR
%ssa66 i64 = EntrypointOffset #0x28
%ssa67 i32 = LoadMemTSO %ssa66 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa68 i128 = F80CVTTo %ssa67 i32, #0x4
%ssa69 i8 = LoadContext #0x1d3, GPR
%ssa70 i64 = Sub %ssa69 i8, %ssa29
%ssa71 i64 = And %ssa70 i64, %ssa16
(%ssa72 i8) StoreContext %ssa71 i64, #0x1d3, GPR
%ssa73 i8 = Bfe %ssa71 i64, #0x8, #0x0
(%ssa74 i0) StoreContextIndexed %ssa68 i128, %ssa73 i8, #0x10, #0x1e0, #0x10, FPR
%ssa75 i8 = LoadContext #0x1d3, GPR
%ssa76 i64 = Add %ssa75 i8, %ssa28
%ssa77 i64 = And %ssa76 i64, %ssa15
%ssa78 i128 = LoadContextIndexed %ssa77 i64, #0x10, #0x1e0, #0x10, FPR
%ssa79 i8 = LoadContext #0x1d3, GPR
%ssa80 i128 = LoadContextIndexed %ssa79 i8, #0x10, #0x1e0, #0x10, FPR
%ssa81 i128 = F80Add %ssa80 i128, %ssa78 i128
%ssa82 i8 = LoadContext #0x1d3, GPR
%ssa83 i64 = Add %ssa82 i8, %ssa27
%ssa84 i64 = And %ssa83 i64, %ssa14
(%ssa85 i8) StoreContext %ssa84 i64, #0x1d3, GPR
%ssa86 i8 = Bfe %ssa84 i64, #0x8, #0x0
(%ssa87 i0) StoreContextIndexed %ssa81 i128, %ssa86 i8, #0x10, #0x1e0, #0x10, FPR
%ssa88 i8 = LoadContext #0x1d3, GPR
%ssa89 i64 = Add %ssa88 i8, %ssa26
%ssa90 i64 = And %ssa89 i64, %ssa13
%ssa91 i128 = LoadContextIndexed %ssa90 i64, #0x10, #0x1e0, #0x10, FPR
%ssa92 i8 = LoadContext #0x1d3, GPR
%ssa93 i128 = LoadContextIndexed %ssa92 i8, #0x10, #0x1e0, #0x10, FPR
%ssa94 i128 = F80Add %ssa93 i128, %ssa91 i128
%ssa95 i8 = LoadContext #0x1d3, GPR
%ssa96 i64 = Add %ssa95 i8, %ssa25
%ssa97 i64 = And %ssa96 i64, %ssa12
(%ssa98 i8) StoreContext %ssa97 i64, #0x1d3, GPR
%ssa99 i8 = Bfe %ssa97 i64, #0x8, #0x0
(%ssa100 i0) StoreContextIndexed %ssa94 i128, %ssa99 i8, #0x10, #0x1e0, #0x10, FPR
%ssa101 i8 = LoadContext #0x1d3, GPR
%ssa102 i64 = Add %ssa101 i8, %ssa24
%ssa103 i64 = And %ssa102 i64, %ssa11
%ssa104 i128 = LoadContextIndexed %ssa103 i64, #0x10, #0x1e0, #0x10, FPR
%ssa105 i8 = LoadContext #0x1d3, GPR
%ssa106 i128 = LoadContextIndexed %ssa105 i8, #0x10, #0x1e0, #0x10, FPR
%ssa107 i128 = F80Add %ssa106 i128, %ssa104 i128
%ssa108 i8 = LoadContext #0x1d3, GPR
%ssa109 i64 = Add %ssa108 i8, %ssa23
%ssa110 i64 = And %ssa109 i64, %ssa10
(%ssa111 i8) StoreContext %ssa110 i64, #0x1d3, GPR
%ssa112 i8 = Bfe %ssa110 i64, #0x8, #0x0
(%ssa113 i0) StoreContextIndexed %ssa107 i128, %ssa112 i8, #0x10, #0x1e0, #0x10, FPR
%ssa114 i8 = LoadContext #0x1d3, GPR
%ssa115 i64 = Add %ssa114 i8, %ssa22
%ssa116 i64 = And %ssa115 i64, %ssa9
%ssa117 i128 = LoadContextIndexed %ssa116 i64, #0x10, #0x1e0, #0x10, FPR
%ssa118 i8 = LoadContext #0x1d3, GPR
%ssa119 i128 = LoadContextIndexed %ssa118 i8, #0x10, #0x1e0, #0x10, FPR
%ssa120 i128 = F80Add %ssa119 i128, %ssa117 i128
%ssa121 i8 = LoadContext #0x1d3, GPR
%ssa122 i64 = Add %ssa121 i8, %ssa21
%ssa123 i64 = And %ssa122 i64, %ssa8
(%ssa124 i8) StoreContext %ssa123 i64, #0x1d3, GPR
%ssa125 i8 = Bfe %ssa123 i64, #0x8, #0x0
(%ssa126 i0) StoreContextIndexed %ssa120 i128, %ssa125 i8, #0x10, #0x1e0, #0x10, FPR
%ssa127 i64 = EntrypointOffset #0x27
(%ssa128 i64) StoreContext %ssa127 i64, #0x0, GPR
(%ssa129 i0) Break #0x4, #0x0
(%ssa130 i0) EndBlock %ssa2
Raw
3_After.ir
(%ssa0) IRHeader #0x10000, %ssa2, #0
(%ssa2) CodeBlock %ssa3, %ssa39
(%ssa3 i0) BeginBlock %ssa2
%ssa4 i64 = EntrypointOffset #0x28
%ssa5 i32 = LoadMemTSO %ssa4 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa6 i64 = EntrypointOffset #0x28
%ssa7 i32 = LoadMemTSO %ssa6 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa8 i64 = EntrypointOffset #0x28
%ssa9 i32 = LoadMemTSO %ssa8 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa10 i64 = EntrypointOffset #0x28
%ssa11 i32 = LoadMemTSO %ssa10 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa12 i64 = EntrypointOffset #0x28
%ssa13 i32 = LoadMemTSO %ssa12 i64, %Invalid, #0x4, #0x4, FPR, SXTX, #0x1
%ssa14 i64 = Float_FToF %ssa13 i32, #0x4
%ssa15 i64 = Float_FToF %ssa11 i32, #0x4
%ssa16 i64 = VFAdd %ssa14 i64, %ssa15 i64
%ssa17 i64 = Float_FToF %ssa9 i32, #0x4
%ssa18 i64 = VFAdd %ssa16 i64, %ssa17 i64
%ssa19 i64 = Float_FToF %ssa7 i32, #0x4
%ssa20 i64 = VFAdd %ssa18 i64, %ssa19 i64
%ssa21 i64 = Float_FToF %ssa5 i32, #0x4
%ssa22 i64 = VFAdd %ssa20 i64, %ssa21 i64
%ssa23 i128 = F80CVTTo %ssa22 i64, #0x8
%ssa24 i8 = LoadContext #0x1d3, GPR
(%ssa25 i0) InlineConstant #0x7
(%ssa26 i0) InlineConstant #0x7
(%ssa27 i0) InlineConstant #0x1
(%ssa28 i0) InlineConstant #0x1
%ssa29 i64 = Sub %ssa24 i8, %ssa28
%ssa30 i64 = And %ssa29 i64, %ssa26
(%ssa31 i0) StoreContextIndexed %ssa23 i128, %ssa30 i64, #0x10, #0x1e0, #0x10, FPR
%ssa32 i64 = EntrypointOffset #0x27
%ssa33 i8 = LoadContext #0x1d3, GPR
%ssa34 i64 = Sub %ssa33 i8, %ssa27
%ssa35 i64 = And %ssa34 i64, %ssa25
(%ssa36 i8) StoreContext %ssa35 i64, #0x1d3, GPR
(%ssa37 i64) StoreContext %ssa32 i64, #0x0, GPR
(%ssa38 i0) Break #0x4, #0x0
(%ssa39 i0) EndBlock %ssa2
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