7seg.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Polprog Computer Heresy Systems
// Engineer: The Man Himself
// 
// Create Date:    17:38:08 02/10/2020 
// Design Name: 
// Module Name:    test 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

// test 7 seg decoder
module test(
    display_out,
	bcd_in,
	dclk
	);
	input [3:0] bcd_in; //BCD input
	input dclk;   //data latch
	output [6:0] display_out; //7 seg outputs
	reg [6:0] display_out;
	wire [3:0] bcd_in;
	wire dclk;
	initial begin
			display_out = 7'b0101010;
	end
	
	always @ (posedge dclk) begin
		case(bcd_in)
		4'b1111: display_out = 7'b1000000; //0
		4'b1110: display_out = 7'b1111001; //1
		4'b1101: display_out = 7'b0100100; //2
		4'b1100: display_out = 7'b0110000; //3
		4'b1011: display_out = 7'b0011001; //4
		4'b1010: display_out = 7'b0010010; //5
		4'b1001: display_out = 7'b0000010; //6
		4'b1000: display_out = 7'b1111000; //7
		4'b0111: display_out = 7'b0000000; //8
		4'b0110: display_out = 7'b0010000; //9

		
		default: display_out = 7'b1010101;
		endcase
	end
endmodule