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posborne/reg.rs

Created June 11, 2015 04:04
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reg.rs
//
// Generated by svdconvert.py from SVD XML description for device:
// - Device Name: MKL25Z4
// - Description: MKL25Z4 Freescale Microcontroller
// - Device Vendor: Freescale Semiconductor, Inc.
// - Device Version: 1.6
//
use volatile_cell::VolatileCell;
use core::ops::Drop;
ioregs!(FTFA_FlashConfig @ 0x400 = { //! Flash configuration field
0x00 => reg8 BACKKEY3 { //! Backdoor Comparison Key 3.
0..7 => KEY ro, //= Backdoor Comparison Key.
},
0x01 => reg8 BACKKEY2 { //! Backdoor Comparison Key 2.
0..7 => KEY ro, //= Backdoor Comparison Key.
},
0x02 => reg8 BACKKEY1 { //! Backdoor Comparison Key 1.
0..7 => KEY ro, //= Backdoor Comparison Key.
},
0x03 => reg8 BACKKEY0 { //! Backdoor Comparison Key 0.
0..7 => KEY ro, //= Backdoor Comparison Key.
},
0x04 => reg8 BACKKEY7 { //! Backdoor Comparison Key 7.
0..7 => KEY ro, //= Backdoor Comparison Key.
},
0x05 => reg8 BACKKEY6 { //! Backdoor Comparison Key 6.
0..7 => KEY ro, //= Backdoor Comparison Key.
},
0x06 => reg8 BACKKEY5 { //! Backdoor Comparison Key 5.
0..7 => KEY ro, //= Backdoor Comparison Key.
},
0x07 => reg8 BACKKEY4 { //! Backdoor Comparison Key 4.
0..7 => KEY ro, //= Backdoor Comparison Key.
},
0x08 => reg8 FPROT3 { //! Non-volatile P-Flash Protection 1 - Low Register
0..7 => PROT ro, //= P-Flash Region Protect
},
0x09 => reg8 FPROT2 { //! Non-volatile P-Flash Protection 1 - High Register
0..7 => PROT ro, //= P-Flash Region Protect
},
0x0A => reg8 FPROT1 { //! Non-volatile P-Flash Protection 0 - Low Register
0..7 => PROT ro, //= P-Flash Region Protect
},
0x0B => reg8 FPROT0 { //! Non-volatile P-Flash Protection 0 - High Register
0..7 => PROT ro, //= P-Flash Region Protect
},
0x0C => reg8 FSEC { //! Non-volatile Flash Security Register
0..1 => SECro { //! Flash Security
2 => MCU_SECURITY_STATUS_IS_UNSECURE, //= MCU security status is unsecure
3 => MCU_SECURITY_STATUS_IS_SECURE, //= MCU security status is secure
}
2..3 => FSLACCro { //! Freescale Failure Analysis Access Code
2 => FREESCALE_FACTORY_ACCESS_DENIED, //= Freescale factory access denied
3 => FREESCALE_FACTORY_ACCESS_GRANTED, //= Freescale factory access granted
}
4..5 => MEENro { //! no description available
2 => MASS_ERASE_IS_DISABLED, //= Mass erase is disabled
3 => MASS_ERASE_IS_ENABLED, //= Mass erase is enabled
}
6..7 => KEYENro { //! Backdoor Key Security Enable
2 => BACKDOOR_KEY_ACCESS_ENABLED, //= Backdoor key access enabled
3 => BACKDOOR_KEY_ACCESS_DISABLED, //= Backdoor key access disabled
}
},
0x0D => reg8 FOPT { //! Non-volatile Flash Option Register
0 => LPBOOT0ro { //! no description available
0 => E_00, //= Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
1 => E_01, //= Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
}
2 => NMI_DISro { //! no description available
0 => NMI_INTERRUPTS_ARE_ALWAYS_BLOCKED, //= NMI interrupts are always blocked
1 => NMI_B_PININTERRUPTS_RESET_DEFAULT_TO_ENABLED, //= NMI_b pin/interrupts reset default to enabled
}
3 => RESET_PIN_CFGro { //! no description available
0 => RESET_PIN_IS_DISABLED_FOLLOWING_A_POR_AND_CANNOT_BE_ENABLED_AS_RESET_FUNCTION, //= RESET pin is disabled following a POR and cannot be enabled as reset function
1 => RESET_B_PIN_IS_DEDICATED, //= RESET_b pin is dedicated
}
4 => LPBOOT1ro { //! no description available
0 => E_00, //= Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
1 => E_01, //= Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
}
5 => FAST_INITro { //! no description available
0 => SLOWER_INITIALIZATION, //= Slower initialization
1 => FAST_INITIALIZATION, //= Fast Initialization
}
},
});
ioregs!(DMA @ 0x40008000 = { //! DMA Controller
0x100 => reg32 SAR0 { //! Source Address Register
0..31 => SAR rw, //= no description available
},
0x104 => reg32 DAR0 { //! Destination Address Register
0..31 => DAR rw, //= no description available
},
0x108 => reg32 DSR_BCR0 { //! DMA Status Register / Byte Count Register
0..23 => BCR rw, //= no description available
24 => DONErw { //! Transactions done
0 => DMA_TRANSFER_IS_NOT_YET_COMPLETE_WRITING_A_0_HAS_NO_EFFECT, //= DMA transfer is not yet complete. Writing a 0 has no effect.
1 => DMA_TRANSFER_COMPLETED_WRITING_A_1_TO_THIS_BIT_CLEARS_ALL_DMA_STATUS_BITS_AND_SHOULD_BE_USED_IN_AN_INTERRUPT_SERVICE_ROUTINE_TO_CLEAR_THE_DMA_INTERRUPT_AND_ERROR_BITS, //= DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
}
25 => BSYro { //! Busy
0 => DMA_CHANNEL_IS_INACTIVE_CLEARED_WHEN_THE_DMA_HAS_FINISHED_THE_LAST_TRANSACTION, //= DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 => BSY_IS_SET_THE_FIRST_TIME_THE_CHANNEL_IS_ENABLED_AFTER_A_TRANSFER_IS_INITIATED, //= BSY is set the first time the channel is enabled after a transfer is initiated.
}
26 => REQro { //! Request
0 => NO_REQUEST_IS_PENDING_OR_THE_CHANNEL_IS_CURRENTLY_ACTIVE_CLEARED_WHEN_THE_CHANNEL_IS_SELECTED, //= No request is pending or the channel is currently active. Cleared when the channel is selected.
1 => THE_DMA_CHANNEL_HAS_A_TRANSFER_REMAINING_AND_THE_CHANNEL_IS_NOT_SELECTED, //= The DMA channel has a transfer remaining and the channel is not selected.
}
28 => BEDro { //! Bus error on destination
0 => NO_BUS_ERROR_OCCURRED, //= No bus error occurred.
1 => THE_DMA_CHANNEL_TERMINATED_WITH_A_BUS_ERROR_DURING_THE_WRITE_PORTION_OF_A_TRANSFER, //= The DMA channel terminated with a bus error during the write portion of a transfer.
}
29 => BESro { //! Bus error on source
0 => NO_BUS_ERROR_OCCURRED, //= No bus error occurred.
1 => THE_DMA_CHANNEL_TERMINATED_WITH_A_BUS_ERROR_DURING_THE_READ_PORTION_OF_A_TRANSFER, //= The DMA channel terminated with a bus error during the read portion of a transfer.
}
30 => CEro { //! Configuration error
0 => NO_CONFIGURATION_ERROR_EXISTS, //= No configuration error exists.
1 => A_CONFIGURATION_ERROR_HAS_OCCURRED, //= A configuration error has occurred.
}
},
0x10B => reg8 DSR0 { //! DMA_DSR0 register.
},
0x10C => reg32 DCR0 { //! DMA Control Register
0..1 => LCH2rw { //! Link channel 2
0 => DMA_CHANNEL_0, //= DMA Channel 0
1 => DMA_CHANNEL_1, //= DMA Channel 1
2 => DMA_CHANNEL_2, //= DMA Channel 2
3 => DMA_CHANNEL_3, //= DMA Channel 3
}
2..3 => LCH1rw { //! Link channel 1
0 => DMA_CHANNEL_0, //= DMA Channel 0
1 => DMA_CHANNEL_1, //= DMA Channel 1
2 => DMA_CHANNEL_2, //= DMA Channel 2
3 => DMA_CHANNEL_3, //= DMA Channel 3
}
4..5 => LINKCCrw { //! Link channel control
0 => NO_CHANNEL_TO_CHANNEL_LINKING, //= No channel-to-channel linking
1 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_EACH_CYCLE_STEAL_TRANSFER_FOLLOWED_BY_A_LINK_TO_LCH2_AFTER_THE_BCR_DECREMENTS_TO_ZERO, //= Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero
2 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_EACH_CYCLE_STEAL_TRANSFER, //= Perform a link to channel LCH1 after each cycle-steal transfer
3 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_THE_BCR_DECREMENTS_TO_ZERO, //= Perform a link to channel LCH1 after the BCR decrements to zero
}
7 => D_REQrw { //! Disable request
0 => ERQ_BIT_IS_NOT_AFFECTED, //= ERQ bit is not affected.
1 => ERQ_BIT_IS_CLEARED_WHEN_THE_BCR_IS_EXHAUSTED, //= ERQ bit is cleared when the BCR is exhausted.
}
8..11 => DMODrw { //! Destination address modulo
0 => BUFFER_DISABLED, //= Buffer disabled
1 => CIRCULAR_BUFFER_SIZE_IS_16_BYTES, //= Circular buffer size is 16 bytes
2 => CIRCULAR_BUFFER_SIZE_IS_32_BYTES, //= Circular buffer size is 32 bytes
3 => CIRCULAR_BUFFER_SIZE_IS_64_BYTES, //= Circular buffer size is 64 bytes
4 => CIRCULAR_BUFFER_SIZE_IS_128_BYTES, //= Circular buffer size is 128 bytes
5 => CIRCULAR_BUFFER_SIZE_IS_256_BYTES, //= Circular buffer size is 256 bytes
6 => CIRCULAR_BUFFER_SIZE_IS_512_BYTES, //= Circular buffer size is 512 bytes
7 => CIRCULAR_BUFFER_SIZE_IS_1_KB, //= Circular buffer size is 1 KB
8 => CIRCULAR_BUFFER_SIZE_IS_2_KB, //= Circular buffer size is 2 KB
9 => CIRCULAR_BUFFER_SIZE_IS_4_KB, //= Circular buffer size is 4 KB
10 => CIRCULAR_BUFFER_SIZE_IS_8_KB, //= Circular buffer size is 8 KB
11 => CIRCULAR_BUFFER_SIZE_IS_16_KB, //= Circular buffer size is 16 KB
12 => CIRCULAR_BUFFER_SIZE_IS_32_KB, //= Circular buffer size is 32 KB
13 => CIRCULAR_BUFFER_SIZE_IS_64_KB, //= Circular buffer size is 64 KB
14 => CIRCULAR_BUFFER_SIZE_IS_128_KB, //= Circular buffer size is 128 KB
15 => CIRCULAR_BUFFER_SIZE_IS_256_KB, //= Circular buffer size is 256 KB
}
12..15 => SMODrw { //! Source address modulo
0 => BUFFER_DISABLED, //= Buffer disabled
1 => CIRCULAR_BUFFER_SIZE_IS_16_BYTES, //= Circular buffer size is 16 bytes
2 => CIRCULAR_BUFFER_SIZE_IS_32_BYTES, //= Circular buffer size is 32 bytes
3 => CIRCULAR_BUFFER_SIZE_IS_64_BYTES, //= Circular buffer size is 64 bytes
4 => CIRCULAR_BUFFER_SIZE_IS_128_BYTES, //= Circular buffer size is 128 bytes
5 => CIRCULAR_BUFFER_SIZE_IS_256_BYTES, //= Circular buffer size is 256 bytes
6 => CIRCULAR_BUFFER_SIZE_IS_512_BYTES, //= Circular buffer size is 512 bytes
7 => CIRCULAR_BUFFER_SIZE_IS_1_KB, //= Circular buffer size is 1 KB
8 => CIRCULAR_BUFFER_SIZE_IS_2_KB, //= Circular buffer size is 2 KB
9 => CIRCULAR_BUFFER_SIZE_IS_4_KB, //= Circular buffer size is 4 KB
10 => CIRCULAR_BUFFER_SIZE_IS_8_KB, //= Circular buffer size is 8 KB
11 => CIRCULAR_BUFFER_SIZE_IS_16_KB, //= Circular buffer size is 16 KB
12 => CIRCULAR_BUFFER_SIZE_IS_32_KB, //= Circular buffer size is 32 KB
13 => CIRCULAR_BUFFER_SIZE_IS_64_KB, //= Circular buffer size is 64 KB
14 => CIRCULAR_BUFFER_SIZE_IS_128_KB, //= Circular buffer size is 128 KB
15 => CIRCULAR_BUFFER_SIZE_IS_256_KB, //= Circular buffer size is 256 KB
}
16 => STARTwo { //! Start transfer
0 => DMA_INACTIVE, //= DMA inactive
1 => THE_DMA_BEGINS_THE_TRANSFER_IN_ACCORDANCE_TO_THE_VALUES_IN_THE_TCDN_START_IS_CLEARED_AUTOMATICALLY_AFTER_ONE_MODULE_CLOCK_AND_ALWAYS_READS_AS_LOGIC_0, //= The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
}
17..18 => DSIZErw { //! Destination size
0 => 32_BIT, //= 32-bit
1 => 8_BIT, //= 8-bit
2 => 16_BIT, //= 16-bit
3 => E_11, //= Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
}
19 => DINCrw { //! Destination increment
0 => NO_CHANGE_TO_THE_DAR_AFTER_A_SUCCESSFUL_TRANSFER, //= No change to the DAR after a successful transfer.
1 => THE_DAR_INCREMENTS_BY_1_2_4_DEPENDING_UPON_THE_SIZE_OF_THE_TRANSFER, //= The DAR increments by 1, 2, 4 depending upon the size of the transfer.
}
20..21 => SSIZErw { //! Source size
0 => 32_BIT, //= 32-bit
1 => 8_BIT, //= 8-bit
2 => 16_BIT, //= 16-bit
3 => E_11, //= Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
}
22 => SINCrw { //! Source increment
0 => NO_CHANGE_TO_SAR_AFTER_A_SUCCESSFUL_TRANSFER, //= No change to SAR after a successful transfer.
1 => THE_SAR_INCREMENTS_BY_1_2_4_AS_DETERMINED_BY_THE_TRANSFER_SIZE, //= The SAR increments by 1, 2, 4 as determined by the transfer size.
}
23 => EADREQrw { //! Enable asynchronous DMA requests
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
28 => AArw { //! Auto-align
0 => AUTO_ALIGN_DISABLED, //= Auto-align disabled
1 => E_1, //= If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
}
29 => CSrw { //! Cycle steal
0 => DMA_CONTINUOUSLY_MAKES_READWRITE_TRANSFERS_UNTIL_THE_BCR_DECREMENTS_TO_0, //= DMA continuously makes read/write transfers until the BCR decrements to 0.
1 => FORCES_A_SINGLE_READWRITE_TRANSFER_PER_REQUEST, //= Forces a single read/write transfer per request.
}
30 => ERQrw { //! Enable peripheral request
0 => PERIPHERAL_REQUEST_IS_IGNORED, //= Peripheral request is ignored.
1 => E_1, //= Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is always enabled.
}
31 => EINTrw { //! Enable interrupt on completion of transfer
0 => NO_INTERRUPT_IS_GENERATED, //= No interrupt is generated.
1 => INTERRUPT_SIGNAL_IS_ENABLED, //= Interrupt signal is enabled.
}
},
0x110 => reg32 SAR1 { //! Source Address Register
0..31 => SAR rw, //= no description available
},
0x114 => reg32 DAR1 { //! Destination Address Register
0..31 => DAR rw, //= no description available
},
0x118 => reg32 DSR_BCR1 { //! DMA Status Register / Byte Count Register
0..23 => BCR rw, //= no description available
24 => DONErw { //! Transactions done
0 => DMA_TRANSFER_IS_NOT_YET_COMPLETE_WRITING_A_0_HAS_NO_EFFECT, //= DMA transfer is not yet complete. Writing a 0 has no effect.
1 => DMA_TRANSFER_COMPLETED_WRITING_A_1_TO_THIS_BIT_CLEARS_ALL_DMA_STATUS_BITS_AND_SHOULD_BE_USED_IN_AN_INTERRUPT_SERVICE_ROUTINE_TO_CLEAR_THE_DMA_INTERRUPT_AND_ERROR_BITS, //= DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
}
25 => BSYro { //! Busy
0 => DMA_CHANNEL_IS_INACTIVE_CLEARED_WHEN_THE_DMA_HAS_FINISHED_THE_LAST_TRANSACTION, //= DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 => BSY_IS_SET_THE_FIRST_TIME_THE_CHANNEL_IS_ENABLED_AFTER_A_TRANSFER_IS_INITIATED, //= BSY is set the first time the channel is enabled after a transfer is initiated.
}
26 => REQro { //! Request
0 => NO_REQUEST_IS_PENDING_OR_THE_CHANNEL_IS_CURRENTLY_ACTIVE_CLEARED_WHEN_THE_CHANNEL_IS_SELECTED, //= No request is pending or the channel is currently active. Cleared when the channel is selected.
1 => THE_DMA_CHANNEL_HAS_A_TRANSFER_REMAINING_AND_THE_CHANNEL_IS_NOT_SELECTED, //= The DMA channel has a transfer remaining and the channel is not selected.
}
28 => BEDro { //! Bus error on destination
0 => NO_BUS_ERROR_OCCURRED, //= No bus error occurred.
1 => THE_DMA_CHANNEL_TERMINATED_WITH_A_BUS_ERROR_DURING_THE_WRITE_PORTION_OF_A_TRANSFER, //= The DMA channel terminated with a bus error during the write portion of a transfer.
}
29 => BESro { //! Bus error on source
0 => NO_BUS_ERROR_OCCURRED, //= No bus error occurred.
1 => THE_DMA_CHANNEL_TERMINATED_WITH_A_BUS_ERROR_DURING_THE_READ_PORTION_OF_A_TRANSFER, //= The DMA channel terminated with a bus error during the read portion of a transfer.
}
30 => CEro { //! Configuration error
0 => NO_CONFIGURATION_ERROR_EXISTS, //= No configuration error exists.
1 => A_CONFIGURATION_ERROR_HAS_OCCURRED, //= A configuration error has occurred.
}
},
0x11B => reg8 DSR1 { //! DMA_DSR1 register.
},
0x11C => reg32 DCR1 { //! DMA Control Register
0..1 => LCH2rw { //! Link channel 2
0 => DMA_CHANNEL_0, //= DMA Channel 0
1 => DMA_CHANNEL_1, //= DMA Channel 1
2 => DMA_CHANNEL_2, //= DMA Channel 2
3 => DMA_CHANNEL_3, //= DMA Channel 3
}
2..3 => LCH1rw { //! Link channel 1
0 => DMA_CHANNEL_0, //= DMA Channel 0
1 => DMA_CHANNEL_1, //= DMA Channel 1
2 => DMA_CHANNEL_2, //= DMA Channel 2
3 => DMA_CHANNEL_3, //= DMA Channel 3
}
4..5 => LINKCCrw { //! Link channel control
0 => NO_CHANNEL_TO_CHANNEL_LINKING, //= No channel-to-channel linking
1 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_EACH_CYCLE_STEAL_TRANSFER_FOLLOWED_BY_A_LINK_TO_LCH2_AFTER_THE_BCR_DECREMENTS_TO_ZERO, //= Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero
2 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_EACH_CYCLE_STEAL_TRANSFER, //= Perform a link to channel LCH1 after each cycle-steal transfer
3 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_THE_BCR_DECREMENTS_TO_ZERO, //= Perform a link to channel LCH1 after the BCR decrements to zero
}
7 => D_REQrw { //! Disable request
0 => ERQ_BIT_IS_NOT_AFFECTED, //= ERQ bit is not affected.
1 => ERQ_BIT_IS_CLEARED_WHEN_THE_BCR_IS_EXHAUSTED, //= ERQ bit is cleared when the BCR is exhausted.
}
8..11 => DMODrw { //! Destination address modulo
0 => BUFFER_DISABLED, //= Buffer disabled
1 => CIRCULAR_BUFFER_SIZE_IS_16_BYTES, //= Circular buffer size is 16 bytes
2 => CIRCULAR_BUFFER_SIZE_IS_32_BYTES, //= Circular buffer size is 32 bytes
3 => CIRCULAR_BUFFER_SIZE_IS_64_BYTES, //= Circular buffer size is 64 bytes
4 => CIRCULAR_BUFFER_SIZE_IS_128_BYTES, //= Circular buffer size is 128 bytes
5 => CIRCULAR_BUFFER_SIZE_IS_256_BYTES, //= Circular buffer size is 256 bytes
6 => CIRCULAR_BUFFER_SIZE_IS_512_BYTES, //= Circular buffer size is 512 bytes
7 => CIRCULAR_BUFFER_SIZE_IS_1_KB, //= Circular buffer size is 1 KB
8 => CIRCULAR_BUFFER_SIZE_IS_2_KB, //= Circular buffer size is 2 KB
9 => CIRCULAR_BUFFER_SIZE_IS_4_KB, //= Circular buffer size is 4 KB
10 => CIRCULAR_BUFFER_SIZE_IS_8_KB, //= Circular buffer size is 8 KB
11 => CIRCULAR_BUFFER_SIZE_IS_16_KB, //= Circular buffer size is 16 KB
12 => CIRCULAR_BUFFER_SIZE_IS_32_KB, //= Circular buffer size is 32 KB
13 => CIRCULAR_BUFFER_SIZE_IS_64_KB, //= Circular buffer size is 64 KB
14 => CIRCULAR_BUFFER_SIZE_IS_128_KB, //= Circular buffer size is 128 KB
15 => CIRCULAR_BUFFER_SIZE_IS_256_KB, //= Circular buffer size is 256 KB
}
12..15 => SMODrw { //! Source address modulo
0 => BUFFER_DISABLED, //= Buffer disabled
1 => CIRCULAR_BUFFER_SIZE_IS_16_BYTES, //= Circular buffer size is 16 bytes
2 => CIRCULAR_BUFFER_SIZE_IS_32_BYTES, //= Circular buffer size is 32 bytes
3 => CIRCULAR_BUFFER_SIZE_IS_64_BYTES, //= Circular buffer size is 64 bytes
4 => CIRCULAR_BUFFER_SIZE_IS_128_BYTES, //= Circular buffer size is 128 bytes
5 => CIRCULAR_BUFFER_SIZE_IS_256_BYTES, //= Circular buffer size is 256 bytes
6 => CIRCULAR_BUFFER_SIZE_IS_512_BYTES, //= Circular buffer size is 512 bytes
7 => CIRCULAR_BUFFER_SIZE_IS_1_KB, //= Circular buffer size is 1 KB
8 => CIRCULAR_BUFFER_SIZE_IS_2_KB, //= Circular buffer size is 2 KB
9 => CIRCULAR_BUFFER_SIZE_IS_4_KB, //= Circular buffer size is 4 KB
10 => CIRCULAR_BUFFER_SIZE_IS_8_KB, //= Circular buffer size is 8 KB
11 => CIRCULAR_BUFFER_SIZE_IS_16_KB, //= Circular buffer size is 16 KB
12 => CIRCULAR_BUFFER_SIZE_IS_32_KB, //= Circular buffer size is 32 KB
13 => CIRCULAR_BUFFER_SIZE_IS_64_KB, //= Circular buffer size is 64 KB
14 => CIRCULAR_BUFFER_SIZE_IS_128_KB, //= Circular buffer size is 128 KB
15 => CIRCULAR_BUFFER_SIZE_IS_256_KB, //= Circular buffer size is 256 KB
}
16 => STARTwo { //! Start transfer
0 => DMA_INACTIVE, //= DMA inactive
1 => THE_DMA_BEGINS_THE_TRANSFER_IN_ACCORDANCE_TO_THE_VALUES_IN_THE_TCDN_START_IS_CLEARED_AUTOMATICALLY_AFTER_ONE_MODULE_CLOCK_AND_ALWAYS_READS_AS_LOGIC_0, //= The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
}
17..18 => DSIZErw { //! Destination size
0 => 32_BIT, //= 32-bit
1 => 8_BIT, //= 8-bit
2 => 16_BIT, //= 16-bit
3 => E_11, //= Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
}
19 => DINCrw { //! Destination increment
0 => NO_CHANGE_TO_THE_DAR_AFTER_A_SUCCESSFUL_TRANSFER, //= No change to the DAR after a successful transfer.
1 => THE_DAR_INCREMENTS_BY_1_2_4_DEPENDING_UPON_THE_SIZE_OF_THE_TRANSFER, //= The DAR increments by 1, 2, 4 depending upon the size of the transfer.
}
20..21 => SSIZErw { //! Source size
0 => 32_BIT, //= 32-bit
1 => 8_BIT, //= 8-bit
2 => 16_BIT, //= 16-bit
3 => E_11, //= Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
}
22 => SINCrw { //! Source increment
0 => NO_CHANGE_TO_SAR_AFTER_A_SUCCESSFUL_TRANSFER, //= No change to SAR after a successful transfer.
1 => THE_SAR_INCREMENTS_BY_1_2_4_AS_DETERMINED_BY_THE_TRANSFER_SIZE, //= The SAR increments by 1, 2, 4 as determined by the transfer size.
}
23 => EADREQrw { //! Enable asynchronous DMA requests
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
28 => AArw { //! Auto-align
0 => AUTO_ALIGN_DISABLED, //= Auto-align disabled
1 => E_1, //= If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
}
29 => CSrw { //! Cycle steal
0 => DMA_CONTINUOUSLY_MAKES_READWRITE_TRANSFERS_UNTIL_THE_BCR_DECREMENTS_TO_0, //= DMA continuously makes read/write transfers until the BCR decrements to 0.
1 => FORCES_A_SINGLE_READWRITE_TRANSFER_PER_REQUEST, //= Forces a single read/write transfer per request.
}
30 => ERQrw { //! Enable peripheral request
0 => PERIPHERAL_REQUEST_IS_IGNORED, //= Peripheral request is ignored.
1 => E_1, //= Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is always enabled.
}
31 => EINTrw { //! Enable interrupt on completion of transfer
0 => NO_INTERRUPT_IS_GENERATED, //= No interrupt is generated.
1 => INTERRUPT_SIGNAL_IS_ENABLED, //= Interrupt signal is enabled.
}
},
0x120 => reg32 SAR2 { //! Source Address Register
0..31 => SAR rw, //= no description available
},
0x124 => reg32 DAR2 { //! Destination Address Register
0..31 => DAR rw, //= no description available
},
0x128 => reg32 DSR_BCR2 { //! DMA Status Register / Byte Count Register
0..23 => BCR rw, //= no description available
24 => DONErw { //! Transactions done
0 => DMA_TRANSFER_IS_NOT_YET_COMPLETE_WRITING_A_0_HAS_NO_EFFECT, //= DMA transfer is not yet complete. Writing a 0 has no effect.
1 => DMA_TRANSFER_COMPLETED_WRITING_A_1_TO_THIS_BIT_CLEARS_ALL_DMA_STATUS_BITS_AND_SHOULD_BE_USED_IN_AN_INTERRUPT_SERVICE_ROUTINE_TO_CLEAR_THE_DMA_INTERRUPT_AND_ERROR_BITS, //= DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
}
25 => BSYro { //! Busy
0 => DMA_CHANNEL_IS_INACTIVE_CLEARED_WHEN_THE_DMA_HAS_FINISHED_THE_LAST_TRANSACTION, //= DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 => BSY_IS_SET_THE_FIRST_TIME_THE_CHANNEL_IS_ENABLED_AFTER_A_TRANSFER_IS_INITIATED, //= BSY is set the first time the channel is enabled after a transfer is initiated.
}
26 => REQro { //! Request
0 => NO_REQUEST_IS_PENDING_OR_THE_CHANNEL_IS_CURRENTLY_ACTIVE_CLEARED_WHEN_THE_CHANNEL_IS_SELECTED, //= No request is pending or the channel is currently active. Cleared when the channel is selected.
1 => THE_DMA_CHANNEL_HAS_A_TRANSFER_REMAINING_AND_THE_CHANNEL_IS_NOT_SELECTED, //= The DMA channel has a transfer remaining and the channel is not selected.
}
28 => BEDro { //! Bus error on destination
0 => NO_BUS_ERROR_OCCURRED, //= No bus error occurred.
1 => THE_DMA_CHANNEL_TERMINATED_WITH_A_BUS_ERROR_DURING_THE_WRITE_PORTION_OF_A_TRANSFER, //= The DMA channel terminated with a bus error during the write portion of a transfer.
}
29 => BESro { //! Bus error on source
0 => NO_BUS_ERROR_OCCURRED, //= No bus error occurred.
1 => THE_DMA_CHANNEL_TERMINATED_WITH_A_BUS_ERROR_DURING_THE_READ_PORTION_OF_A_TRANSFER, //= The DMA channel terminated with a bus error during the read portion of a transfer.
}
30 => CEro { //! Configuration error
0 => NO_CONFIGURATION_ERROR_EXISTS, //= No configuration error exists.
1 => A_CONFIGURATION_ERROR_HAS_OCCURRED, //= A configuration error has occurred.
}
},
0x12B => reg8 DSR2 { //! DMA_DSR2 register.
},
0x12C => reg32 DCR2 { //! DMA Control Register
0..1 => LCH2rw { //! Link channel 2
0 => DMA_CHANNEL_0, //= DMA Channel 0
1 => DMA_CHANNEL_1, //= DMA Channel 1
2 => DMA_CHANNEL_2, //= DMA Channel 2
3 => DMA_CHANNEL_3, //= DMA Channel 3
}
2..3 => LCH1rw { //! Link channel 1
0 => DMA_CHANNEL_0, //= DMA Channel 0
1 => DMA_CHANNEL_1, //= DMA Channel 1
2 => DMA_CHANNEL_2, //= DMA Channel 2
3 => DMA_CHANNEL_3, //= DMA Channel 3
}
4..5 => LINKCCrw { //! Link channel control
0 => NO_CHANNEL_TO_CHANNEL_LINKING, //= No channel-to-channel linking
1 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_EACH_CYCLE_STEAL_TRANSFER_FOLLOWED_BY_A_LINK_TO_LCH2_AFTER_THE_BCR_DECREMENTS_TO_ZERO, //= Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero
2 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_EACH_CYCLE_STEAL_TRANSFER, //= Perform a link to channel LCH1 after each cycle-steal transfer
3 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_THE_BCR_DECREMENTS_TO_ZERO, //= Perform a link to channel LCH1 after the BCR decrements to zero
}
7 => D_REQrw { //! Disable request
0 => ERQ_BIT_IS_NOT_AFFECTED, //= ERQ bit is not affected.
1 => ERQ_BIT_IS_CLEARED_WHEN_THE_BCR_IS_EXHAUSTED, //= ERQ bit is cleared when the BCR is exhausted.
}
8..11 => DMODrw { //! Destination address modulo
0 => BUFFER_DISABLED, //= Buffer disabled
1 => CIRCULAR_BUFFER_SIZE_IS_16_BYTES, //= Circular buffer size is 16 bytes
2 => CIRCULAR_BUFFER_SIZE_IS_32_BYTES, //= Circular buffer size is 32 bytes
3 => CIRCULAR_BUFFER_SIZE_IS_64_BYTES, //= Circular buffer size is 64 bytes
4 => CIRCULAR_BUFFER_SIZE_IS_128_BYTES, //= Circular buffer size is 128 bytes
5 => CIRCULAR_BUFFER_SIZE_IS_256_BYTES, //= Circular buffer size is 256 bytes
6 => CIRCULAR_BUFFER_SIZE_IS_512_BYTES, //= Circular buffer size is 512 bytes
7 => CIRCULAR_BUFFER_SIZE_IS_1_KB, //= Circular buffer size is 1 KB
8 => CIRCULAR_BUFFER_SIZE_IS_2_KB, //= Circular buffer size is 2 KB
9 => CIRCULAR_BUFFER_SIZE_IS_4_KB, //= Circular buffer size is 4 KB
10 => CIRCULAR_BUFFER_SIZE_IS_8_KB, //= Circular buffer size is 8 KB
11 => CIRCULAR_BUFFER_SIZE_IS_16_KB, //= Circular buffer size is 16 KB
12 => CIRCULAR_BUFFER_SIZE_IS_32_KB, //= Circular buffer size is 32 KB
13 => CIRCULAR_BUFFER_SIZE_IS_64_KB, //= Circular buffer size is 64 KB
14 => CIRCULAR_BUFFER_SIZE_IS_128_KB, //= Circular buffer size is 128 KB
15 => CIRCULAR_BUFFER_SIZE_IS_256_KB, //= Circular buffer size is 256 KB
}
12..15 => SMODrw { //! Source address modulo
0 => BUFFER_DISABLED, //= Buffer disabled
1 => CIRCULAR_BUFFER_SIZE_IS_16_BYTES, //= Circular buffer size is 16 bytes
2 => CIRCULAR_BUFFER_SIZE_IS_32_BYTES, //= Circular buffer size is 32 bytes
3 => CIRCULAR_BUFFER_SIZE_IS_64_BYTES, //= Circular buffer size is 64 bytes
4 => CIRCULAR_BUFFER_SIZE_IS_128_BYTES, //= Circular buffer size is 128 bytes
5 => CIRCULAR_BUFFER_SIZE_IS_256_BYTES, //= Circular buffer size is 256 bytes
6 => CIRCULAR_BUFFER_SIZE_IS_512_BYTES, //= Circular buffer size is 512 bytes
7 => CIRCULAR_BUFFER_SIZE_IS_1_KB, //= Circular buffer size is 1 KB
8 => CIRCULAR_BUFFER_SIZE_IS_2_KB, //= Circular buffer size is 2 KB
9 => CIRCULAR_BUFFER_SIZE_IS_4_KB, //= Circular buffer size is 4 KB
10 => CIRCULAR_BUFFER_SIZE_IS_8_KB, //= Circular buffer size is 8 KB
11 => CIRCULAR_BUFFER_SIZE_IS_16_KB, //= Circular buffer size is 16 KB
12 => CIRCULAR_BUFFER_SIZE_IS_32_KB, //= Circular buffer size is 32 KB
13 => CIRCULAR_BUFFER_SIZE_IS_64_KB, //= Circular buffer size is 64 KB
14 => CIRCULAR_BUFFER_SIZE_IS_128_KB, //= Circular buffer size is 128 KB
15 => CIRCULAR_BUFFER_SIZE_IS_256_KB, //= Circular buffer size is 256 KB
}
16 => STARTwo { //! Start transfer
0 => DMA_INACTIVE, //= DMA inactive
1 => THE_DMA_BEGINS_THE_TRANSFER_IN_ACCORDANCE_TO_THE_VALUES_IN_THE_TCDN_START_IS_CLEARED_AUTOMATICALLY_AFTER_ONE_MODULE_CLOCK_AND_ALWAYS_READS_AS_LOGIC_0, //= The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
}
17..18 => DSIZErw { //! Destination size
0 => 32_BIT, //= 32-bit
1 => 8_BIT, //= 8-bit
2 => 16_BIT, //= 16-bit
3 => E_11, //= Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
}
19 => DINCrw { //! Destination increment
0 => NO_CHANGE_TO_THE_DAR_AFTER_A_SUCCESSFUL_TRANSFER, //= No change to the DAR after a successful transfer.
1 => THE_DAR_INCREMENTS_BY_1_2_4_DEPENDING_UPON_THE_SIZE_OF_THE_TRANSFER, //= The DAR increments by 1, 2, 4 depending upon the size of the transfer.
}
20..21 => SSIZErw { //! Source size
0 => 32_BIT, //= 32-bit
1 => 8_BIT, //= 8-bit
2 => 16_BIT, //= 16-bit
3 => E_11, //= Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
}
22 => SINCrw { //! Source increment
0 => NO_CHANGE_TO_SAR_AFTER_A_SUCCESSFUL_TRANSFER, //= No change to SAR after a successful transfer.
1 => THE_SAR_INCREMENTS_BY_1_2_4_AS_DETERMINED_BY_THE_TRANSFER_SIZE, //= The SAR increments by 1, 2, 4 as determined by the transfer size.
}
23 => EADREQrw { //! Enable asynchronous DMA requests
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
28 => AArw { //! Auto-align
0 => AUTO_ALIGN_DISABLED, //= Auto-align disabled
1 => E_1, //= If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
}
29 => CSrw { //! Cycle steal
0 => DMA_CONTINUOUSLY_MAKES_READWRITE_TRANSFERS_UNTIL_THE_BCR_DECREMENTS_TO_0, //= DMA continuously makes read/write transfers until the BCR decrements to 0.
1 => FORCES_A_SINGLE_READWRITE_TRANSFER_PER_REQUEST, //= Forces a single read/write transfer per request.
}
30 => ERQrw { //! Enable peripheral request
0 => PERIPHERAL_REQUEST_IS_IGNORED, //= Peripheral request is ignored.
1 => E_1, //= Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is always enabled.
}
31 => EINTrw { //! Enable interrupt on completion of transfer
0 => NO_INTERRUPT_IS_GENERATED, //= No interrupt is generated.
1 => INTERRUPT_SIGNAL_IS_ENABLED, //= Interrupt signal is enabled.
}
},
0x130 => reg32 SAR3 { //! Source Address Register
0..31 => SAR rw, //= no description available
},
0x134 => reg32 DAR3 { //! Destination Address Register
0..31 => DAR rw, //= no description available
},
0x138 => reg32 DSR_BCR3 { //! DMA Status Register / Byte Count Register
0..23 => BCR rw, //= no description available
24 => DONErw { //! Transactions done
0 => DMA_TRANSFER_IS_NOT_YET_COMPLETE_WRITING_A_0_HAS_NO_EFFECT, //= DMA transfer is not yet complete. Writing a 0 has no effect.
1 => DMA_TRANSFER_COMPLETED_WRITING_A_1_TO_THIS_BIT_CLEARS_ALL_DMA_STATUS_BITS_AND_SHOULD_BE_USED_IN_AN_INTERRUPT_SERVICE_ROUTINE_TO_CLEAR_THE_DMA_INTERRUPT_AND_ERROR_BITS, //= DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
}
25 => BSYro { //! Busy
0 => DMA_CHANNEL_IS_INACTIVE_CLEARED_WHEN_THE_DMA_HAS_FINISHED_THE_LAST_TRANSACTION, //= DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 => BSY_IS_SET_THE_FIRST_TIME_THE_CHANNEL_IS_ENABLED_AFTER_A_TRANSFER_IS_INITIATED, //= BSY is set the first time the channel is enabled after a transfer is initiated.
}
26 => REQro { //! Request
0 => NO_REQUEST_IS_PENDING_OR_THE_CHANNEL_IS_CURRENTLY_ACTIVE_CLEARED_WHEN_THE_CHANNEL_IS_SELECTED, //= No request is pending or the channel is currently active. Cleared when the channel is selected.
1 => THE_DMA_CHANNEL_HAS_A_TRANSFER_REMAINING_AND_THE_CHANNEL_IS_NOT_SELECTED, //= The DMA channel has a transfer remaining and the channel is not selected.
}
28 => BEDro { //! Bus error on destination
0 => NO_BUS_ERROR_OCCURRED, //= No bus error occurred.
1 => THE_DMA_CHANNEL_TERMINATED_WITH_A_BUS_ERROR_DURING_THE_WRITE_PORTION_OF_A_TRANSFER, //= The DMA channel terminated with a bus error during the write portion of a transfer.
}
29 => BESro { //! Bus error on source
0 => NO_BUS_ERROR_OCCURRED, //= No bus error occurred.
1 => THE_DMA_CHANNEL_TERMINATED_WITH_A_BUS_ERROR_DURING_THE_READ_PORTION_OF_A_TRANSFER, //= The DMA channel terminated with a bus error during the read portion of a transfer.
}
30 => CEro { //! Configuration error
0 => NO_CONFIGURATION_ERROR_EXISTS, //= No configuration error exists.
1 => A_CONFIGURATION_ERROR_HAS_OCCURRED, //= A configuration error has occurred.
}
},
0x13B => reg8 DSR3 { //! DMA_DSR3 register.
},
0x13C => reg32 DCR3 { //! DMA Control Register
0..1 => LCH2rw { //! Link channel 2
0 => DMA_CHANNEL_0, //= DMA Channel 0
1 => DMA_CHANNEL_1, //= DMA Channel 1
2 => DMA_CHANNEL_2, //= DMA Channel 2
3 => DMA_CHANNEL_3, //= DMA Channel 3
}
2..3 => LCH1rw { //! Link channel 1
0 => DMA_CHANNEL_0, //= DMA Channel 0
1 => DMA_CHANNEL_1, //= DMA Channel 1
2 => DMA_CHANNEL_2, //= DMA Channel 2
3 => DMA_CHANNEL_3, //= DMA Channel 3
}
4..5 => LINKCCrw { //! Link channel control
0 => NO_CHANNEL_TO_CHANNEL_LINKING, //= No channel-to-channel linking
1 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_EACH_CYCLE_STEAL_TRANSFER_FOLLOWED_BY_A_LINK_TO_LCH2_AFTER_THE_BCR_DECREMENTS_TO_ZERO, //= Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero
2 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_EACH_CYCLE_STEAL_TRANSFER, //= Perform a link to channel LCH1 after each cycle-steal transfer
3 => PERFORM_A_LINK_TO_CHANNEL_LCH1_AFTER_THE_BCR_DECREMENTS_TO_ZERO, //= Perform a link to channel LCH1 after the BCR decrements to zero
}
7 => D_REQrw { //! Disable request
0 => ERQ_BIT_IS_NOT_AFFECTED, //= ERQ bit is not affected.
1 => ERQ_BIT_IS_CLEARED_WHEN_THE_BCR_IS_EXHAUSTED, //= ERQ bit is cleared when the BCR is exhausted.
}
8..11 => DMODrw { //! Destination address modulo
0 => BUFFER_DISABLED, //= Buffer disabled
1 => CIRCULAR_BUFFER_SIZE_IS_16_BYTES, //= Circular buffer size is 16 bytes
2 => CIRCULAR_BUFFER_SIZE_IS_32_BYTES, //= Circular buffer size is 32 bytes
3 => CIRCULAR_BUFFER_SIZE_IS_64_BYTES, //= Circular buffer size is 64 bytes
4 => CIRCULAR_BUFFER_SIZE_IS_128_BYTES, //= Circular buffer size is 128 bytes
5 => CIRCULAR_BUFFER_SIZE_IS_256_BYTES, //= Circular buffer size is 256 bytes
6 => CIRCULAR_BUFFER_SIZE_IS_512_BYTES, //= Circular buffer size is 512 bytes
7 => CIRCULAR_BUFFER_SIZE_IS_1_KB, //= Circular buffer size is 1 KB
8 => CIRCULAR_BUFFER_SIZE_IS_2_KB, //= Circular buffer size is 2 KB
9 => CIRCULAR_BUFFER_SIZE_IS_4_KB, //= Circular buffer size is 4 KB
10 => CIRCULAR_BUFFER_SIZE_IS_8_KB, //= Circular buffer size is 8 KB
11 => CIRCULAR_BUFFER_SIZE_IS_16_KB, //= Circular buffer size is 16 KB
12 => CIRCULAR_BUFFER_SIZE_IS_32_KB, //= Circular buffer size is 32 KB
13 => CIRCULAR_BUFFER_SIZE_IS_64_KB, //= Circular buffer size is 64 KB
14 => CIRCULAR_BUFFER_SIZE_IS_128_KB, //= Circular buffer size is 128 KB
15 => CIRCULAR_BUFFER_SIZE_IS_256_KB, //= Circular buffer size is 256 KB
}
12..15 => SMODrw { //! Source address modulo
0 => BUFFER_DISABLED, //= Buffer disabled
1 => CIRCULAR_BUFFER_SIZE_IS_16_BYTES, //= Circular buffer size is 16 bytes
2 => CIRCULAR_BUFFER_SIZE_IS_32_BYTES, //= Circular buffer size is 32 bytes
3 => CIRCULAR_BUFFER_SIZE_IS_64_BYTES, //= Circular buffer size is 64 bytes
4 => CIRCULAR_BUFFER_SIZE_IS_128_BYTES, //= Circular buffer size is 128 bytes
5 => CIRCULAR_BUFFER_SIZE_IS_256_BYTES, //= Circular buffer size is 256 bytes
6 => CIRCULAR_BUFFER_SIZE_IS_512_BYTES, //= Circular buffer size is 512 bytes
7 => CIRCULAR_BUFFER_SIZE_IS_1_KB, //= Circular buffer size is 1 KB
8 => CIRCULAR_BUFFER_SIZE_IS_2_KB, //= Circular buffer size is 2 KB
9 => CIRCULAR_BUFFER_SIZE_IS_4_KB, //= Circular buffer size is 4 KB
10 => CIRCULAR_BUFFER_SIZE_IS_8_KB, //= Circular buffer size is 8 KB
11 => CIRCULAR_BUFFER_SIZE_IS_16_KB, //= Circular buffer size is 16 KB
12 => CIRCULAR_BUFFER_SIZE_IS_32_KB, //= Circular buffer size is 32 KB
13 => CIRCULAR_BUFFER_SIZE_IS_64_KB, //= Circular buffer size is 64 KB
14 => CIRCULAR_BUFFER_SIZE_IS_128_KB, //= Circular buffer size is 128 KB
15 => CIRCULAR_BUFFER_SIZE_IS_256_KB, //= Circular buffer size is 256 KB
}
16 => STARTwo { //! Start transfer
0 => DMA_INACTIVE, //= DMA inactive
1 => THE_DMA_BEGINS_THE_TRANSFER_IN_ACCORDANCE_TO_THE_VALUES_IN_THE_TCDN_START_IS_CLEARED_AUTOMATICALLY_AFTER_ONE_MODULE_CLOCK_AND_ALWAYS_READS_AS_LOGIC_0, //= The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
}
17..18 => DSIZErw { //! Destination size
0 => 32_BIT, //= 32-bit
1 => 8_BIT, //= 8-bit
2 => 16_BIT, //= 16-bit
3 => E_11, //= Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
}
19 => DINCrw { //! Destination increment
0 => NO_CHANGE_TO_THE_DAR_AFTER_A_SUCCESSFUL_TRANSFER, //= No change to the DAR after a successful transfer.
1 => THE_DAR_INCREMENTS_BY_1_2_4_DEPENDING_UPON_THE_SIZE_OF_THE_TRANSFER, //= The DAR increments by 1, 2, 4 depending upon the size of the transfer.
}
20..21 => SSIZErw { //! Source size
0 => 32_BIT, //= 32-bit
1 => 8_BIT, //= 8-bit
2 => 16_BIT, //= 16-bit
3 => E_11, //= Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
}
22 => SINCrw { //! Source increment
0 => NO_CHANGE_TO_SAR_AFTER_A_SUCCESSFUL_TRANSFER, //= No change to SAR after a successful transfer.
1 => THE_SAR_INCREMENTS_BY_1_2_4_AS_DETERMINED_BY_THE_TRANSFER_SIZE, //= The SAR increments by 1, 2, 4 as determined by the transfer size.
}
23 => EADREQrw { //! Enable asynchronous DMA requests
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
28 => AArw { //! Auto-align
0 => AUTO_ALIGN_DISABLED, //= Auto-align disabled
1 => E_1, //= If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
}
29 => CSrw { //! Cycle steal
0 => DMA_CONTINUOUSLY_MAKES_READWRITE_TRANSFERS_UNTIL_THE_BCR_DECREMENTS_TO_0, //= DMA continuously makes read/write transfers until the BCR decrements to 0.
1 => FORCES_A_SINGLE_READWRITE_TRANSFER_PER_REQUEST, //= Forces a single read/write transfer per request.
}
30 => ERQrw { //! Enable peripheral request
0 => PERIPHERAL_REQUEST_IS_IGNORED, //= Peripheral request is ignored.
1 => E_1, //= Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is always enabled.
}
31 => EINTrw { //! Enable interrupt on completion of transfer
0 => NO_INTERRUPT_IS_GENERATED, //= No interrupt is generated.
1 => INTERRUPT_SIGNAL_IS_ENABLED, //= Interrupt signal is enabled.
}
},
});
ioregs!(FTFA @ 0x40020000 = { //! Flash Memory Interface
0x00 => reg8 FSTAT { //! Flash Status Register
0 => MGSTAT0 ro, //= Memory Controller Command Completion Status Flag
4 => FPVIOLrw { //! Flash Protection Violation Flag
0 => NO_PROTECTION_VIOLATION_DETECTED, //= No protection violation detected
1 => PROTECTION_VIOLATION_DETECTED, //= Protection violation detected
}
5 => ACCERRrw { //! Flash Access Error Flag
0 => NO_ACCESS_ERROR_DETECTED, //= No access error detected
1 => ACCESS_ERROR_DETECTED, //= Access error detected
}
6 => RDCOLERRrw { //! Flash Read Collision Error Flag
0 => NO_COLLISION_ERROR_DETECTED, //= No collision error detected
1 => COLLISION_ERROR_DETECTED, //= Collision error detected
}
7 => CCIFrw { //! Command Complete Interrupt Flag
0 => FLASH_COMMAND_IN_PROGRESS, //= Flash command in progress
1 => FLASH_COMMAND_HAS_COMPLETED, //= Flash command has completed
}
},
0x01 => reg8 FCNFG { //! Flash Configuration Register
4 => ERSSUSPrw { //! Erase Suspend
0 => NO_SUSPEND_REQUESTED, //= No suspend requested
1 => SUSPEND_THE_CURRENT_ERASE_FLASH_SECTOR_COMMAND_EXECUTION, //= Suspend the current Erase Flash Sector command execution.
}
5 => ERSAREQro { //! Erase All Request
0 => NO_REQUEST_OR_REQUEST_COMPLETE, //= No request or request complete
1 => E_1, //= Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
}
6 => RDCOLLIErw { //! Read Collision Error Interrupt Enable
0 => READ_COLLISION_ERROR_INTERRUPT_DISABLED, //= Read collision error interrupt disabled
1 => E_1, //= Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
}
7 => CCIErw { //! Command Complete Interrupt Enable
0 => COMMAND_COMPLETE_INTERRUPT_DISABLED, //= Command complete interrupt disabled
1 => COMMAND_COMPLETE_INTERRUPT_ENABLED_AN_INTERRUPT_REQUEST_IS_GENERATED_WHENEVER_THE_FSTAT[CCIF]_FLAG_IS_SET, //= Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
}
},
0x02 => reg8 FSEC { //! Flash Security Register
0..1 => SECro { //! Flash Security
0 => MCU_SECURITY_STATUS_IS_SECURE, //= MCU security status is secure
1 => MCU_SECURITY_STATUS_IS_SECURE, //= MCU security status is secure
2 => E_10, //= MCU security status is unsecure (The standard shipping condition of the flash memory module is unsecure.)
3 => MCU_SECURITY_STATUS_IS_SECURE, //= MCU security status is secure
}
2..3 => FSLACCro { //! Freescale Failure Analysis Access Code
0 => FREESCALE_FACTORY_ACCESS_GRANTED, //= Freescale factory access granted
1 => FREESCALE_FACTORY_ACCESS_DENIED, //= Freescale factory access denied
2 => FREESCALE_FACTORY_ACCESS_DENIED, //= Freescale factory access denied
3 => FREESCALE_FACTORY_ACCESS_GRANTED, //= Freescale factory access granted
}
4..5 => MEENro { //! Mass Erase Enable Bits
0 => MASS_ERASE_IS_ENABLED, //= Mass erase is enabled
1 => MASS_ERASE_IS_ENABLED, //= Mass erase is enabled
2 => MASS_ERASE_IS_DISABLED, //= Mass erase is disabled
3 => MASS_ERASE_IS_ENABLED, //= Mass erase is enabled
}
6..7 => KEYENro { //! Backdoor Key Security Enable
0 => BACKDOOR_KEY_ACCESS_DISABLED, //= Backdoor key access disabled
1 => E_01, //= Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
2 => BACKDOOR_KEY_ACCESS_ENABLED, //= Backdoor key access enabled
3 => BACKDOOR_KEY_ACCESS_DISABLED, //= Backdoor key access disabled
}
},
0x03 => reg8 FOPT { //! Flash Option Register
0..7 => OPT ro, //= Nonvolatile Option
},
0x04 => reg8 FCCOB%s { //! Flash Common Command Object Registers
0..7 => CCOBn rw, //= no description available
},
0x10 => reg8 FPROT%s { //! Program Flash Protection Registers
0..7 => PROTrw { //! Program Flash Region Protect
0 => PROGRAM_FLASH_REGION_IS_PROTECTED, //= Program flash region is protected.
1 => PROGRAM_FLASH_REGION_IS_NOT_PROTECTED, //= Program flash region is not protected
}
},
});
ioregs!(DMAMUX0 @ 0x40021000 = { //! DMA channel multiplexor
0x00 => reg8 CHCFG%s { //! Channel Configuration register
0..5 => SOURCE rw, //= DMA Channel Source (Slot)
6 => TRIGrw { //! DMA Channel Trigger Enable
0 => E_0, //= Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
1 => TRIGGERING_IS_ENABLED_IF_TRIGGERING_IS_ENABLED_AND_THE_ENBL_BIT_IS_SET_THE_DMAMUX_IS_IN_PERIODIC_TRIGGER_MODE, //= Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode.
}
7 => ENBLrw { //! DMA Channel Enable
0 => DMA_CHANNEL_IS_DISABLED_THIS_MODE_IS_PRIMARILY_USED_DURING_CONFIGURATION_OF_THE_DMA_MUX_THE_DMA_HAS_SEPARATE_CHANNEL_ENABLESDISABLES_WHICH_SHOULD_BE_USED_TO_DISABLE_OR_RE_CONFIGURE_A_DMA_CHANNEL, //= DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
1 => DMA_CHANNEL_IS_ENABLED, //= DMA channel is enabled
}
},
});
ioregs!(PIT @ 0x40037000 = { //! Periodic Interrupt Timer
0x00 => reg32 MCR { //! PIT Module Control Register
0 => FRZrw { //! Freeze
0 => TIMERS_CONTINUE_TO_RUN_IN_DEBUG_MODE, //= Timers continue to run in Debug mode.
1 => TIMERS_ARE_STOPPED_IN_DEBUG_MODE, //= Timers are stopped in Debug mode.
}
1 => MDISrw { //! Module Disable - (PIT section)
0 => CLOCK_FOR_STANDARD_PIT_TIMERS_IS_ENABLED, //= Clock for standard PIT timers is enabled.
1 => CLOCK_FOR_STANDARD_PIT_TIMERS_IS_DISABLED, //= Clock for standard PIT timers is disabled.
}
},
0xE0 => reg32 LTMR64H { //! PIT Upper Lifetime Timer Register
0..31 => LTH ro, //= Life Timer value
},
0xE4 => reg32 LTMR64L { //! PIT Lower Lifetime Timer Register
0..31 => LTL ro, //= Life Timer value
},
0x100 => reg32 LDVAL%s { //! Timer Load Value Register
0..31 => TSV rw, //= Timer Start Value
},
0x104 => reg32 CVAL%s { //! Current Timer Value Register
0..31 => TVL ro, //= Current Timer Value
},
0x108 => reg32 TCTRL%s { //! Timer Control Register
0 => TENrw { //! Timer Enable
0 => TIMER_N_IS_DISABLED, //= Timer n is disabled.
1 => TIMER_N_IS_ENABLED, //= Timer n is enabled.
}
1 => TIErw { //! Timer Interrupt Enable
0 => INTERRUPT_REQUESTS_FROM_TIMER_N_ARE_DISABLED, //= Interrupt requests from Timer n are disabled.
1 => INTERRUPT_WILL_BE_REQUESTED_WHENEVER_TIF_IS_SET, //= Interrupt will be requested whenever TIF is set.
}
2 => CHNrw { //! Chain Mode
0 => TIMER_IS_NOT_CHAINED, //= Timer is not chained.
1 => TIMER_IS_CHAINED_TO_PREVIOUS_TIMER_FOR_EXAMPLE_FOR_CHANNEL_2_IF_THIS_FIELD_IS_SET_TIMER_2_IS_CHAINED_TO_TIMER_1, //= Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
}
},
0x10C => reg32 TFLG%s { //! Timer Flag Register
0 => TIFrw { //! Timer Interrupt Flag
0 => TIMEOUT_HAS_NOT_YET_OCCURRED, //= Timeout has not yet occurred.
1 => TIMEOUT_HAS_OCCURRED, //= Timeout has occurred.
}
},
});
ioregs!(TPM0 @ 0x40038000 = { //! Timer/PWM Module
0x00 => reg32 SC { //! Status and Control
0..2 => PSrw { //! Prescale Factor Selection
0 => DIVIDE_BY_1, //= Divide by 1
1 => DIVIDE_BY_2, //= Divide by 2
2 => DIVIDE_BY_4, //= Divide by 4
3 => DIVIDE_BY_8, //= Divide by 8
4 => DIVIDE_BY_16, //= Divide by 16
5 => DIVIDE_BY_32, //= Divide by 32
6 => DIVIDE_BY_64, //= Divide by 64
7 => DIVIDE_BY_128, //= Divide by 128
}
3..4 => CMODrw { //! Clock Mode Selection
0 => LPTPM_COUNTER_IS_DISABLED, //= LPTPM counter is disabled
1 => LPTPM_COUNTER_INCREMENTS_ON_EVERY_LPTPM_COUNTER_CLOCK, //= LPTPM counter increments on every LPTPM counter clock
2 => LPTPM_COUNTER_INCREMENTS_ON_RISING_EDGE_OF_LPTPM_EXTCLK_SYNCHRONIZED_TO_THE_LPTPM_COUNTER_CLOCK, //= LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock
}
5 => CPWMSrw { //! Center-aligned PWM Select
0 => LPTPM_COUNTER_OPERATES_IN_UP_COUNTING_MODE, //= LPTPM counter operates in up counting mode.
1 => LPTPM_COUNTER_OPERATES_IN_UP_DOWN_COUNTING_MODE, //= LPTPM counter operates in up-down counting mode.
}
6 => TOIErw { //! Timer Overflow Interrupt Enable
0 => DISABLE_TOF_INTERRUPTS_USE_SOFTWARE_POLLING_OR_DMA_REQUEST, //= Disable TOF interrupts. Use software polling or DMA request.
1 => ENABLE_TOF_INTERRUPTS_AN_INTERRUPT_IS_GENERATED_WHEN_TOF_EQUALS_ONE, //= Enable TOF interrupts. An interrupt is generated when TOF equals one.
}
7 => TOFrw { //! Timer Overflow Flag
0 => LPTPM_COUNTER_HAS_NOT_OVERFLOWED, //= LPTPM counter has not overflowed.
1 => LPTPM_COUNTER_HAS_OVERFLOWED, //= LPTPM counter has overflowed.
}
8 => DMArw { //! DMA Enable
0 => DISABLES_DMA_TRANSFERS, //= Disables DMA transfers.
1 => ENABLES_DMA_TRANSFERS, //= Enables DMA transfers.
}
},
0x04 => reg32 CNT { //! Counter
0..15 => COUNT rw, //= Counter value
},
0x08 => reg32 MOD { //! Modulo
0..15 => MOD rw, //= Modulo value
},
0x0C => reg32 C%sSC { //! Channel (n) Status and Control
0 => DMArw { //! DMA Enable
0 => DISABLE_DMA_TRANSFERS, //= Disable DMA transfers.
1 => ENABLE_DMA_TRANSFERS, //= Enable DMA transfers.
}
2 => ELSA rw, //= Edge or Level Select
3 => ELSB rw, //= Edge or Level Select
4 => MSA rw, //= Channel Mode Select
5 => MSB rw, //= Channel Mode Select
6 => CHIErw { //! Channel Interrupt Enable
0 => DISABLE_CHANNEL_INTERRUPTS, //= Disable channel interrupts.
1 => ENABLE_CHANNEL_INTERRUPTS, //= Enable channel interrupts.
}
7 => CHFrw { //! Channel Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
},
0x10 => reg32 C%sV { //! Channel (n) Value
0..15 => VAL rw, //= Channel Value
},
0x50 => reg32 STATUS { //! Capture and Compare Status
0 => CH0Frw { //! Channel 0 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
1 => CH1Frw { //! Channel 1 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
2 => CH2Frw { //! Channel 2 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
3 => CH3Frw { //! Channel 3 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
4 => CH4Frw { //! Channel 4 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
5 => CH5Frw { //! Channel 5 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
8 => TOFrw { //! Timer Overflow Flag
0 => LPTPM_COUNTER_HAS_NOT_OVERFLOWED, //= LPTPM counter has not overflowed.
1 => LPTPM_COUNTER_HAS_OVERFLOWED, //= LPTPM counter has overflowed.
}
},
0x84 => reg32 CONF { //! Configuration
5 => DOZEENrw { //! Doze Enable
0 => INTERNAL_LPTPM_COUNTER_CONTINUES_IN_DOZE_MODE, //= Internal LPTPM counter continues in Doze mode.
1 => INTERNAL_LPTPM_COUNTER_IS_PAUSED_AND_DOES_NOT_INCREMENT_DURING_DOZE_MODE_TRIGGER_INPUTS_AND_INPUT_CAPTURE_EVENTS_ARE_ALSO_IGNORED, //= Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
}
6..7 => DBGMODErw { //! Debug Mode
0 => LPTPM_COUNTER_IS_PAUSED_AND_DOES_NOT_INCREMENT_DURING_DEBUG_MODE_TRIGGER_INPUTS_AND_INPUT_CAPTURE_EVENTS_ARE_ALSO_IGNORED, //= LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
3 => LPTPM_COUNTER_CONTINUES_IN_DEBUG_MODE, //= LPTPM counter continues in debug mode.
}
9 => GTBEENrw { //! Global time base enable
0 => ALL_CHANNELS_USE_THE_INTERNALLY_GENERATED_LPTPM_COUNTER_AS_THEIR_TIMEBASE, //= All channels use the internally generated LPTPM counter as their timebase
1 => ALL_CHANNELS_USE_AN_EXTERNALLY_GENERATED_GLOBAL_TIMEBASE_AS_THEIR_TIMEBASE, //= All channels use an externally generated global timebase as their timebase
}
16 => CSOTrw { //! Counter Start on Trigger
0 => LPTPM_COUNTER_STARTS_TO_INCREMENT_IMMEDIATELY_ONCE_IT_IS_ENABLED, //= LPTPM counter starts to increment immediately, once it is enabled.
1 => LPTPM_COUNTER_ONLY_STARTS_TO_INCREMENT_WHEN_IT_A_RISING_EDGE_ON_THE_SELECTED_INPUT_TRIGGER_IS_DETECTED_AFTER_IT_HAS_BEEN_ENABLED_OR_AFTER_IT_HAS_STOPPED_DUE_TO_OVERFLOW, //= LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
}
17 => CSOOrw { //! Counter Stop On Overflow
0 => LPTPM_COUNTER_CONTINUES_INCREMENTING_OR_DECREMENTING_AFTER_OVERFLOW, //= LPTPM counter continues incrementing or decrementing after overflow
1 => LPTPM_COUNTER_STOPS_INCREMENTING_OR_DECREMENTING_AFTER_OVERFLOW, //= LPTPM counter stops incrementing or decrementing after overflow.
}
18 => CROTrw { //! Counter Reload On Trigger
0 => COUNTER_IS_NOT_RELOADED_DUE_TO_A_RISING_EDGE_ON_THE_SELECTED_INPUT_TRIGGER, //= Counter is not reloaded due to a rising edge on the selected input trigger
1 => COUNTER_IS_RELOADED_WHEN_A_RISING_EDGE_IS_DETECTED_ON_THE_SELECTED_INPUT_TRIGGER, //= Counter is reloaded when a rising edge is detected on the selected input trigger
}
24..27 => TRGSEL rw, //= Trigger Select
},
});
ioregs!(TPM1 @ 0x40039000 = { //! Timer/PWM Module
0x00 => reg32 SC { //! Status and Control
0..2 => PSrw { //! Prescale Factor Selection
0 => DIVIDE_BY_1, //= Divide by 1
1 => DIVIDE_BY_2, //= Divide by 2
2 => DIVIDE_BY_4, //= Divide by 4
3 => DIVIDE_BY_8, //= Divide by 8
4 => DIVIDE_BY_16, //= Divide by 16
5 => DIVIDE_BY_32, //= Divide by 32
6 => DIVIDE_BY_64, //= Divide by 64
7 => DIVIDE_BY_128, //= Divide by 128
}
3..4 => CMODrw { //! Clock Mode Selection
0 => LPTPM_COUNTER_IS_DISABLED, //= LPTPM counter is disabled
1 => LPTPM_COUNTER_INCREMENTS_ON_EVERY_LPTPM_COUNTER_CLOCK, //= LPTPM counter increments on every LPTPM counter clock
2 => LPTPM_COUNTER_INCREMENTS_ON_RISING_EDGE_OF_LPTPM_EXTCLK_SYNCHRONIZED_TO_THE_LPTPM_COUNTER_CLOCK, //= LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock
}
5 => CPWMSrw { //! Center-aligned PWM Select
0 => LPTPM_COUNTER_OPERATES_IN_UP_COUNTING_MODE, //= LPTPM counter operates in up counting mode.
1 => LPTPM_COUNTER_OPERATES_IN_UP_DOWN_COUNTING_MODE, //= LPTPM counter operates in up-down counting mode.
}
6 => TOIErw { //! Timer Overflow Interrupt Enable
0 => DISABLE_TOF_INTERRUPTS_USE_SOFTWARE_POLLING_OR_DMA_REQUEST, //= Disable TOF interrupts. Use software polling or DMA request.
1 => ENABLE_TOF_INTERRUPTS_AN_INTERRUPT_IS_GENERATED_WHEN_TOF_EQUALS_ONE, //= Enable TOF interrupts. An interrupt is generated when TOF equals one.
}
7 => TOFrw { //! Timer Overflow Flag
0 => LPTPM_COUNTER_HAS_NOT_OVERFLOWED, //= LPTPM counter has not overflowed.
1 => LPTPM_COUNTER_HAS_OVERFLOWED, //= LPTPM counter has overflowed.
}
8 => DMArw { //! DMA Enable
0 => DISABLES_DMA_TRANSFERS, //= Disables DMA transfers.
1 => ENABLES_DMA_TRANSFERS, //= Enables DMA transfers.
}
},
0x04 => reg32 CNT { //! Counter
0..15 => COUNT rw, //= Counter value
},
0x08 => reg32 MOD { //! Modulo
0..15 => MOD rw, //= Modulo value
},
0x0C => reg32 C%sSC { //! Channel (n) Status and Control
0 => DMArw { //! DMA Enable
0 => DISABLE_DMA_TRANSFERS, //= Disable DMA transfers.
1 => ENABLE_DMA_TRANSFERS, //= Enable DMA transfers.
}
2 => ELSA rw, //= Edge or Level Select
3 => ELSB rw, //= Edge or Level Select
4 => MSA rw, //= Channel Mode Select
5 => MSB rw, //= Channel Mode Select
6 => CHIErw { //! Channel Interrupt Enable
0 => DISABLE_CHANNEL_INTERRUPTS, //= Disable channel interrupts.
1 => ENABLE_CHANNEL_INTERRUPTS, //= Enable channel interrupts.
}
7 => CHFrw { //! Channel Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
},
0x10 => reg32 C%sV { //! Channel (n) Value
0..15 => VAL rw, //= Channel Value
},
0x50 => reg32 STATUS { //! Capture and Compare Status
0 => CH0Frw { //! Channel 0 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
1 => CH1Frw { //! Channel 1 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
2 => CH2Frw { //! Channel 2 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
3 => CH3Frw { //! Channel 3 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
4 => CH4Frw { //! Channel 4 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
5 => CH5Frw { //! Channel 5 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
8 => TOFrw { //! Timer Overflow Flag
0 => LPTPM_COUNTER_HAS_NOT_OVERFLOWED, //= LPTPM counter has not overflowed.
1 => LPTPM_COUNTER_HAS_OVERFLOWED, //= LPTPM counter has overflowed.
}
},
0x84 => reg32 CONF { //! Configuration
5 => DOZEENrw { //! Doze Enable
0 => INTERNAL_LPTPM_COUNTER_CONTINUES_IN_DOZE_MODE, //= Internal LPTPM counter continues in Doze mode.
1 => INTERNAL_LPTPM_COUNTER_IS_PAUSED_AND_DOES_NOT_INCREMENT_DURING_DOZE_MODE_TRIGGER_INPUTS_AND_INPUT_CAPTURE_EVENTS_ARE_ALSO_IGNORED, //= Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
}
6..7 => DBGMODErw { //! Debug Mode
0 => LPTPM_COUNTER_IS_PAUSED_AND_DOES_NOT_INCREMENT_DURING_DEBUG_MODE_TRIGGER_INPUTS_AND_INPUT_CAPTURE_EVENTS_ARE_ALSO_IGNORED, //= LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
3 => LPTPM_COUNTER_CONTINUES_IN_DEBUG_MODE, //= LPTPM counter continues in debug mode.
}
9 => GTBEENrw { //! Global time base enable
0 => ALL_CHANNELS_USE_THE_INTERNALLY_GENERATED_LPTPM_COUNTER_AS_THEIR_TIMEBASE, //= All channels use the internally generated LPTPM counter as their timebase
1 => ALL_CHANNELS_USE_AN_EXTERNALLY_GENERATED_GLOBAL_TIMEBASE_AS_THEIR_TIMEBASE, //= All channels use an externally generated global timebase as their timebase
}
16 => CSOTrw { //! Counter Start on Trigger
0 => LPTPM_COUNTER_STARTS_TO_INCREMENT_IMMEDIATELY_ONCE_IT_IS_ENABLED, //= LPTPM counter starts to increment immediately, once it is enabled.
1 => LPTPM_COUNTER_ONLY_STARTS_TO_INCREMENT_WHEN_IT_A_RISING_EDGE_ON_THE_SELECTED_INPUT_TRIGGER_IS_DETECTED_AFTER_IT_HAS_BEEN_ENABLED_OR_AFTER_IT_HAS_STOPPED_DUE_TO_OVERFLOW, //= LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
}
17 => CSOOrw { //! Counter Stop On Overflow
0 => LPTPM_COUNTER_CONTINUES_INCREMENTING_OR_DECREMENTING_AFTER_OVERFLOW, //= LPTPM counter continues incrementing or decrementing after overflow
1 => LPTPM_COUNTER_STOPS_INCREMENTING_OR_DECREMENTING_AFTER_OVERFLOW, //= LPTPM counter stops incrementing or decrementing after overflow.
}
18 => CROTrw { //! Counter Reload On Trigger
0 => COUNTER_IS_NOT_RELOADED_DUE_TO_A_RISING_EDGE_ON_THE_SELECTED_INPUT_TRIGGER, //= Counter is not reloaded due to a rising edge on the selected input trigger
1 => COUNTER_IS_RELOADED_WHEN_A_RISING_EDGE_IS_DETECTED_ON_THE_SELECTED_INPUT_TRIGGER, //= Counter is reloaded when a rising edge is detected on the selected input trigger
}
24..27 => TRGSEL rw, //= Trigger Select
},
});
ioregs!(TPM2 @ 0x4003A000 = { //! Timer/PWM Module
0x00 => reg32 SC { //! Status and Control
0..2 => PSrw { //! Prescale Factor Selection
0 => DIVIDE_BY_1, //= Divide by 1
1 => DIVIDE_BY_2, //= Divide by 2
2 => DIVIDE_BY_4, //= Divide by 4
3 => DIVIDE_BY_8, //= Divide by 8
4 => DIVIDE_BY_16, //= Divide by 16
5 => DIVIDE_BY_32, //= Divide by 32
6 => DIVIDE_BY_64, //= Divide by 64
7 => DIVIDE_BY_128, //= Divide by 128
}
3..4 => CMODrw { //! Clock Mode Selection
0 => LPTPM_COUNTER_IS_DISABLED, //= LPTPM counter is disabled
1 => LPTPM_COUNTER_INCREMENTS_ON_EVERY_LPTPM_COUNTER_CLOCK, //= LPTPM counter increments on every LPTPM counter clock
2 => LPTPM_COUNTER_INCREMENTS_ON_RISING_EDGE_OF_LPTPM_EXTCLK_SYNCHRONIZED_TO_THE_LPTPM_COUNTER_CLOCK, //= LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock
}
5 => CPWMSrw { //! Center-aligned PWM Select
0 => LPTPM_COUNTER_OPERATES_IN_UP_COUNTING_MODE, //= LPTPM counter operates in up counting mode.
1 => LPTPM_COUNTER_OPERATES_IN_UP_DOWN_COUNTING_MODE, //= LPTPM counter operates in up-down counting mode.
}
6 => TOIErw { //! Timer Overflow Interrupt Enable
0 => DISABLE_TOF_INTERRUPTS_USE_SOFTWARE_POLLING_OR_DMA_REQUEST, //= Disable TOF interrupts. Use software polling or DMA request.
1 => ENABLE_TOF_INTERRUPTS_AN_INTERRUPT_IS_GENERATED_WHEN_TOF_EQUALS_ONE, //= Enable TOF interrupts. An interrupt is generated when TOF equals one.
}
7 => TOFrw { //! Timer Overflow Flag
0 => LPTPM_COUNTER_HAS_NOT_OVERFLOWED, //= LPTPM counter has not overflowed.
1 => LPTPM_COUNTER_HAS_OVERFLOWED, //= LPTPM counter has overflowed.
}
8 => DMArw { //! DMA Enable
0 => DISABLES_DMA_TRANSFERS, //= Disables DMA transfers.
1 => ENABLES_DMA_TRANSFERS, //= Enables DMA transfers.
}
},
0x04 => reg32 CNT { //! Counter
0..15 => COUNT rw, //= Counter value
},
0x08 => reg32 MOD { //! Modulo
0..15 => MOD rw, //= Modulo value
},
0x0C => reg32 C%sSC { //! Channel (n) Status and Control
0 => DMArw { //! DMA Enable
0 => DISABLE_DMA_TRANSFERS, //= Disable DMA transfers.
1 => ENABLE_DMA_TRANSFERS, //= Enable DMA transfers.
}
2 => ELSA rw, //= Edge or Level Select
3 => ELSB rw, //= Edge or Level Select
4 => MSA rw, //= Channel Mode Select
5 => MSB rw, //= Channel Mode Select
6 => CHIErw { //! Channel Interrupt Enable
0 => DISABLE_CHANNEL_INTERRUPTS, //= Disable channel interrupts.
1 => ENABLE_CHANNEL_INTERRUPTS, //= Enable channel interrupts.
}
7 => CHFrw { //! Channel Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
},
0x10 => reg32 C%sV { //! Channel (n) Value
0..15 => VAL rw, //= Channel Value
},
0x50 => reg32 STATUS { //! Capture and Compare Status
0 => CH0Frw { //! Channel 0 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
1 => CH1Frw { //! Channel 1 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
2 => CH2Frw { //! Channel 2 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
3 => CH3Frw { //! Channel 3 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
4 => CH4Frw { //! Channel 4 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
5 => CH5Frw { //! Channel 5 Flag
0 => NO_CHANNEL_EVENT_HAS_OCCURRED, //= No channel event has occurred.
1 => A_CHANNEL_EVENT_HAS_OCCURRED, //= A channel event has occurred.
}
8 => TOFrw { //! Timer Overflow Flag
0 => LPTPM_COUNTER_HAS_NOT_OVERFLOWED, //= LPTPM counter has not overflowed.
1 => LPTPM_COUNTER_HAS_OVERFLOWED, //= LPTPM counter has overflowed.
}
},
0x84 => reg32 CONF { //! Configuration
5 => DOZEENrw { //! Doze Enable
0 => INTERNAL_LPTPM_COUNTER_CONTINUES_IN_DOZE_MODE, //= Internal LPTPM counter continues in Doze mode.
1 => INTERNAL_LPTPM_COUNTER_IS_PAUSED_AND_DOES_NOT_INCREMENT_DURING_DOZE_MODE_TRIGGER_INPUTS_AND_INPUT_CAPTURE_EVENTS_ARE_ALSO_IGNORED, //= Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
}
6..7 => DBGMODErw { //! Debug Mode
0 => LPTPM_COUNTER_IS_PAUSED_AND_DOES_NOT_INCREMENT_DURING_DEBUG_MODE_TRIGGER_INPUTS_AND_INPUT_CAPTURE_EVENTS_ARE_ALSO_IGNORED, //= LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
3 => LPTPM_COUNTER_CONTINUES_IN_DEBUG_MODE, //= LPTPM counter continues in debug mode.
}
9 => GTBEENrw { //! Global time base enable
0 => ALL_CHANNELS_USE_THE_INTERNALLY_GENERATED_LPTPM_COUNTER_AS_THEIR_TIMEBASE, //= All channels use the internally generated LPTPM counter as their timebase
1 => ALL_CHANNELS_USE_AN_EXTERNALLY_GENERATED_GLOBAL_TIMEBASE_AS_THEIR_TIMEBASE, //= All channels use an externally generated global timebase as their timebase
}
16 => CSOTrw { //! Counter Start on Trigger
0 => LPTPM_COUNTER_STARTS_TO_INCREMENT_IMMEDIATELY_ONCE_IT_IS_ENABLED, //= LPTPM counter starts to increment immediately, once it is enabled.
1 => LPTPM_COUNTER_ONLY_STARTS_TO_INCREMENT_WHEN_IT_A_RISING_EDGE_ON_THE_SELECTED_INPUT_TRIGGER_IS_DETECTED_AFTER_IT_HAS_BEEN_ENABLED_OR_AFTER_IT_HAS_STOPPED_DUE_TO_OVERFLOW, //= LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
}
17 => CSOOrw { //! Counter Stop On Overflow
0 => LPTPM_COUNTER_CONTINUES_INCREMENTING_OR_DECREMENTING_AFTER_OVERFLOW, //= LPTPM counter continues incrementing or decrementing after overflow
1 => LPTPM_COUNTER_STOPS_INCREMENTING_OR_DECREMENTING_AFTER_OVERFLOW, //= LPTPM counter stops incrementing or decrementing after overflow.
}
18 => CROTrw { //! Counter Reload On Trigger
0 => COUNTER_IS_NOT_RELOADED_DUE_TO_A_RISING_EDGE_ON_THE_SELECTED_INPUT_TRIGGER, //= Counter is not reloaded due to a rising edge on the selected input trigger
1 => COUNTER_IS_RELOADED_WHEN_A_RISING_EDGE_IS_DETECTED_ON_THE_SELECTED_INPUT_TRIGGER, //= Counter is reloaded when a rising edge is detected on the selected input trigger
}
24..27 => TRGSEL rw, //= Trigger Select
},
});
ioregs!(ADC0 @ 0x4003B000 = { //! Analog-to-Digital Converter
0x00 => reg32 SC1%s { //! ADC Status and Control Registers 1
0..4 => ADCHrw { //! Input channel select
0 => E_00000, //= When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
1 => E_00001, //= When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
2 => E_00010, //= When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
3 => E_00011, //= When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
4 => E_00100, //= When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
5 => E_00101, //= When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
6 => E_00110, //= When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
7 => E_00111, //= When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
8 => E_01000, //= When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
9 => E_01001, //= When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
10 => E_01010, //= When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
11 => E_01011, //= When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
12 => E_01100, //= When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
13 => E_01101, //= When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
14 => E_01110, //= When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
15 => E_01111, //= When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
16 => E_10000, //= When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
17 => E_10001, //= When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
18 => E_10010, //= When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
19 => E_10011, //= When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
20 => E_10100, //= When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
21 => E_10101, //= When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
22 => E_10110, //= When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
23 => E_10111, //= When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
26 => E_11010, //= When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
27 => E_11011, //= When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
29 => E_11101, //= When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
30 => E_11110, //= When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
31 => MODULE_IS_DISABLED, //= Module is disabled.
}
5 => DIFFrw { //! Differential Mode Enable
0 => SINGLE_ENDED_CONVERSIONS_AND_INPUT_CHANNELS_ARE_SELECTED, //= Single-ended conversions and input channels are selected.
1 => DIFFERENTIAL_CONVERSIONS_AND_INPUT_CHANNELS_ARE_SELECTED, //= Differential conversions and input channels are selected.
}
6 => AIENrw { //! Interrupt Enable
0 => CONVERSION_COMPLETE_INTERRUPT_IS_DISABLED, //= Conversion complete interrupt is disabled.
1 => CONVERSION_COMPLETE_INTERRUPT_IS_ENABLED, //= Conversion complete interrupt is enabled.
}
7 => COCOro { //! Conversion Complete Flag
0 => CONVERSION_IS_NOT_COMPLETED, //= Conversion is not completed.
1 => CONVERSION_IS_COMPLETED, //= Conversion is completed.
}
},
0x08 => reg32 CFG1 { //! ADC Configuration Register 1
0..1 => ADICLKrw { //! Input Clock Select
0 => BUS_CLOCK, //= Bus clock
1 => E_01, //= (Bus clock)/2
2 => E_10, //= Alternate clock (ALTCLK)
3 => E_11, //= Asynchronous clock (ADACK)
}
2..3 => MODErw { //! Conversion mode selection
0 => E_00, //= When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
1 => E_01, //= When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
2 => E_10, //= When DIFF=0:It is single-ended 10-bit conversion ; when DIFF=1, it is differential 11-bit conversion with 2's complement output.
3 => E_11, //= When DIFF=0:It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output.
}
4 => ADLSMPrw { //! Sample time configuration
0 => SHORT_SAMPLE_TIME, //= Short sample time.
1 => LONG_SAMPLE_TIME, //= Long sample time.
}
5..6 => ADIVrw { //! Clock Divide Select
0 => THE_DIVIDE_RATIO_IS_1_AND_THE_CLOCK_RATE_IS_INPUT_CLOCK, //= The divide ratio is 1 and the clock rate is input clock.
1 => E_01, //= The divide ratio is 2 and the clock rate is (input clock)/2.
2 => E_10, //= The divide ratio is 4 and the clock rate is (input clock)/4.
3 => E_11, //= The divide ratio is 8 and the clock rate is (input clock)/8.
}
7 => ADLPCrw { //! Low-Power Configuration
0 => NORMAL_POWER_CONFIGURATION, //= Normal power configuration.
1 => LOW_POWER_CONFIGURATION_THE_POWER_IS_REDUCED_AT_THE_EXPENSE_OF_MAXIMUM_CLOCK_SPEED, //= Low-power configuration. The power is reduced at the expense of maximum clock speed.
}
},
0x0C => reg32 CFG2 { //! ADC Configuration Register 2
0..1 => ADLSTSrw { //! Long Sample Time Select
0 => E_00, //= Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
1 => E_01, //= 12 extra ADCK cycles; 16 ADCK cycles total sample time.
2 => E_10, //= 6 extra ADCK cycles; 10 ADCK cycles total sample time.
3 => E_11, //= 2 extra ADCK cycles; 6 ADCK cycles total sample time.
}
2 => ADHSCrw { //! High-Speed Configuration
0 => NORMAL_CONVERSION_SEQUENCE_SELECTED, //= Normal conversion sequence selected.
1 => HIGH_SPEED_CONVERSION_SEQUENCE_SELECTED_WITH_2_ADDITIONAL_ADCK_CYCLES_TO_TOTAL_CONVERSION_TIME, //= High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
}
3 => ADACKENrw { //! Asynchronous Clock Output Enable
0 => E_0, //= Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
1 => ASYNCHRONOUS_CLOCK_AND_CLOCK_OUTPUT_IS_ENABLED_REGARDLESS_OF_THE_STATE_OF_THE_ADC, //= Asynchronous clock and clock output is enabled regardless of the state of the ADC.
}
4 => MUXSELrw { //! ADC Mux Select
0 => ADXXA_CHANNELS_ARE_SELECTED, //= ADxxa channels are selected.
1 => ADXXB_CHANNELS_ARE_SELECTED, //= ADxxb channels are selected.
}
},
0x10 => reg32 R%s { //! ADC Data Result Register
0..15 => D ro, //= Data result
},
0x18 => reg32 CV%s { //! Compare Value Registers
0..15 => CV rw, //= Compare Value.
},
0x20 => reg32 SC2 { //! Status and Control Register 2
0..1 => REFSELrw { //! Voltage Reference Selection
0 => DEFAULT_VOLTAGE_REFERENCE_PIN_PAIR_THAT_IS_EXTERNAL_PINS_VREFH_AND_VREFL, //= Default voltage reference pin pair, that is, external pins VREFH and VREFL
1 => ALTERNATE_REFERENCE_PAIR_THAT_IS_VALTH_AND_VALTL__THIS_PAIR_MAY_BE_ADDITIONAL_EXTERNAL_PINS_OR_INTERNAL_SOURCES_DEPENDING_ON_THE_MCU_CONFIGURATION_SEE_THE_CHIP_CONFIGURATION_INFORMATION_FOR_DETAILS_SPECIFIC_TO_THIS_MCU, //= Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
}
2 => DMAENrw { //! DMA Enable
0 => DMA_IS_DISABLED, //= DMA is disabled.
1 => DMA_IS_ENABLED_AND_WILL_ASSERT_THE_ADC_DMA_REQUEST_DURING_AN_ADC_CONVERSION_COMPLETE_EVENT_NOTED_WHEN_ANY_OF_THE_SC1N[COCO]_FLAGS_IS_ASSERTED, //= DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
}
3 => ACRENrw { //! Compare Function Range Enable
0 => RANGE_FUNCTION_DISABLED_ONLY_CV1_IS_COMPARED, //= Range function disabled. Only CV1 is compared.
1 => RANGE_FUNCTION_ENABLED_BOTH_CV1_AND_CV2_ARE_COMPARED, //= Range function enabled. Both CV1 and CV2 are compared.
}
4 => ACFGTrw { //! Compare Function Greater Than Enable
0 => E_0, //= Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
1 => E_1, //= Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
}
5 => ACFErw { //! Compare Function Enable
0 => COMPARE_FUNCTION_DISABLED, //= Compare function disabled.
1 => COMPARE_FUNCTION_ENABLED, //= Compare function enabled.
}
6 => ADTRGrw { //! Conversion Trigger Select
0 => SOFTWARE_TRIGGER_SELECTED, //= Software trigger selected.
1 => HARDWARE_TRIGGER_SELECTED, //= Hardware trigger selected.
}
7 => ADACTro { //! Conversion Active
0 => CONVERSION_NOT_IN_PROGRESS, //= Conversion not in progress.
1 => CONVERSION_IN_PROGRESS, //= Conversion in progress.
}
},
0x24 => reg32 SC3 { //! Status and Control Register 3
0..1 => AVGSrw { //! Hardware Average Select
0 => 4_SAMPLES_AVERAGED, //= 4 samples averaged.
1 => 8_SAMPLES_AVERAGED, //= 8 samples averaged.
2 => 16_SAMPLES_AVERAGED, //= 16 samples averaged.
3 => 32_SAMPLES_AVERAGED, //= 32 samples averaged.
}
2 => AVGErw { //! Hardware Average Enable
0 => HARDWARE_AVERAGE_FUNCTION_DISABLED, //= Hardware average function disabled.
1 => HARDWARE_AVERAGE_FUNCTION_ENABLED, //= Hardware average function enabled.
}
3 => ADCOrw { //! Continuous Conversion Enable
0 => E_0, //= One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
1 => E_1, //= Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
}
6 => CALFrw { //! Calibration Failed Flag
0 => CALIBRATION_COMPLETED_NORMALLY, //= Calibration completed normally.
1 => CALIBRATION_FAILED_ADC_ACCURACY_SPECIFICATIONS_ARE_NOT_GUARANTEED, //= Calibration failed. ADC accuracy specifications are not guaranteed.
}
7 => CAL rw, //= Calibration
},
0x28 => reg32 OFS { //! ADC Offset Correction Register
0..15 => OFS rw, //= Offset Error Correction Value
},
0x2C => reg32 PG { //! ADC Plus-Side Gain Register
0..15 => PG rw, //= Plus-Side Gain
},
0x30 => reg32 MG { //! ADC Minus-Side Gain Register
0..15 => MG rw, //= Minus-Side Gain
},
0x34 => reg32 CLPD { //! ADC Plus-Side General Calibration Value Register
0..5 => CLPD rw, //= no description available
},
0x38 => reg32 CLPS { //! ADC Plus-Side General Calibration Value Register
0..5 => CLPS rw, //= no description available
},
0x3C => reg32 CLP4 { //! ADC Plus-Side General Calibration Value Register
0..9 => CLP4 rw, //= no description available
},
0x40 => reg32 CLP3 { //! ADC Plus-Side General Calibration Value Register
0..8 => CLP3 rw, //= no description available
},
0x44 => reg32 CLP2 { //! ADC Plus-Side General Calibration Value Register
0..7 => CLP2 rw, //= no description available
},
0x48 => reg32 CLP1 { //! ADC Plus-Side General Calibration Value Register
0..6 => CLP1 rw, //= no description available
},
0x4C => reg32 CLP0 { //! ADC Plus-Side General Calibration Value Register
0..5 => CLP0 rw, //= no description available
},
0x54 => reg32 CLMD { //! ADC Minus-Side General Calibration Value Register
0..5 => CLMD rw, //= no description available
},
0x58 => reg32 CLMS { //! ADC Minus-Side General Calibration Value Register
0..5 => CLMS rw, //= no description available
},
0x5C => reg32 CLM4 { //! ADC Minus-Side General Calibration Value Register
0..9 => CLM4 rw, //= no description available
},
0x60 => reg32 CLM3 { //! ADC Minus-Side General Calibration Value Register
0..8 => CLM3 rw, //= no description available
},
0x64 => reg32 CLM2 { //! ADC Minus-Side General Calibration Value Register
0..7 => CLM2 rw, //= no description available
},
0x68 => reg32 CLM1 { //! ADC Minus-Side General Calibration Value Register
0..6 => CLM1 rw, //= no description available
},
0x6C => reg32 CLM0 { //! ADC Minus-Side General Calibration Value Register
0..5 => CLM0 rw, //= no description available
},
});
ioregs!(RTC @ 0x4003D000 = { //! Secure Real Time Clock
0x00 => reg32 TSR { //! RTC Time Seconds Register
0..31 => TSR rw, //= Time Seconds Register
},
0x04 => reg32 TPR { //! RTC Time Prescaler Register
0..15 => TPR rw, //= Time Prescaler Register
},
0x08 => reg32 TAR { //! RTC Time Alarm Register
0..31 => TAR rw, //= Time Alarm Register
},
0x0C => reg32 TCR { //! RTC Time Compensation Register
0..7 => TCRrw { //! Time Compensation Register
128 => TIME_PRESCALER_REGISTER_OVERFLOWS_EVERY_32896_CLOCK_CYCLES, //= Time Prescaler Register overflows every 32896 clock cycles.
255 => TIME_PRESCALER_REGISTER_OVERFLOWS_EVERY_32769_CLOCK_CYCLES, //= Time Prescaler Register overflows every 32769 clock cycles.
0 => TIME_PRESCALER_REGISTER_OVERFLOWS_EVERY_32768_CLOCK_CYCLES, //= Time Prescaler Register overflows every 32768 clock cycles.
1 => TIME_PRESCALER_REGISTER_OVERFLOWS_EVERY_32767_CLOCK_CYCLES, //= Time Prescaler Register overflows every 32767 clock cycles.
127 => TIME_PRESCALER_REGISTER_OVERFLOWS_EVERY_32641_CLOCK_CYCLES, //= Time Prescaler Register overflows every 32641 clock cycles.
}
8..15 => CIR rw, //= Compensation Interval Register
16..23 => TCV ro, //= Time Compensation Value
24..31 => CIC ro, //= Compensation Interval Counter
},
0x10 => reg32 CR { //! RTC Control Register
0 => SWRrw { //! Software Reset
0 => NO_EFFECT, //= No effect.
1 => RESETS_ALL_RTC_REGISTERS_EXCEPT_FOR_THE_SWR_BIT__THE_SWR_BIT_IS_CLEARED_BY_POR_AND_BY_SOFTWARE_EXPLICITLY_CLEARING_IT, //= Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it.
}
1 => WPErw { //! Wakeup Pin Enable
0 => WAKEUP_PIN_IS_DISABLED, //= Wakeup pin is disabled.
1 => WAKEUP_PIN_IS_ENABLED_AND_WAKEUP_PIN_ASSERTS_IF_THE_RTC_INTERRUPT_ASSERTS_OR_THE_WAKEUP_PIN_IS_TURNED_ON, //= Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
}
2 => SUPrw { //! Supervisor Access
0 => NON_SUPERVISOR_MODE_WRITE_ACCESSES_ARE_NOT_SUPPORTED_AND_GENERATE_A_BUS_ERROR, //= Non-supervisor mode write accesses are not supported and generate a bus error.
1 => NON_SUPERVISOR_MODE_WRITE_ACCESSES_ARE_SUPPORTED, //= Non-supervisor mode write accesses are supported.
}
3 => UMrw { //! Update Mode
0 => REGISTERS_CANNOT_BE_WRITTEN_WHEN_LOCKED, //= Registers cannot be written when locked.
1 => REGISTERS_CAN_BE_WRITTEN_WHEN_LOCKED_UNDER_LIMITED_CONDITIONS, //= Registers can be written when locked under limited conditions.
}
8 => OSCErw { //! Oscillator Enable
0 => 32768_KHZ_OSCILLATOR_IS_DISABLED, //= 32.768 kHz oscillator is disabled.
1 => 32768_KHZ_OSCILLATOR_IS_ENABLED_AFTER_SETTING_THIS_BIT_WAIT_THE_OSCILLATOR_STARTUP_TIME_BEFORE_ENABLING_THE_TIME_COUNTER_TO_ALLOW_THE_32768_KHZ_CLOCK_TIME_TO_STABILIZE, //= 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
}
9 => CLKOrw { //! Clock Output
0 => THE_32_KHZ_CLOCK_IS_OUTPUT_TO_OTHER_PERIPHERALS, //= The 32 kHz clock is output to other peripherals.
1 => THE_32_KHZ_CLOCK_IS_NOT_OUTPUT_TO_OTHER_PERIPHERALS, //= The 32 kHz clock is not output to other peripherals.
}
10 => SC16Prw { //! Oscillator 16pF Load Configure
0 => DISABLE_THE_LOAD, //= Disable the load.
1 => ENABLE_THE_ADDITIONAL_LOAD, //= Enable the additional load.
}
11 => SC8Prw { //! Oscillator 8pF Load Configure
0 => DISABLE_THE_LOAD, //= Disable the load.
1 => ENABLE_THE_ADDITIONAL_LOAD, //= Enable the additional load.
}
12 => SC4Prw { //! Oscillator 4pF Load Configure
0 => DISABLE_THE_LOAD, //= Disable the load.
1 => ENABLE_THE_ADDITIONAL_LOAD, //= Enable the additional load.
}
13 => SC2Prw { //! Oscillator 2pF Load Configure
0 => DISABLE_THE_LOAD, //= Disable the load.
1 => ENABLE_THE_ADDITIONAL_LOAD, //= Enable the additional load.
}
},
0x14 => reg32 SR { //! RTC Status Register
0 => TIFro { //! Time Invalid Flag
0 => TIME_IS_VALID, //= Time is valid.
1 => TIME_IS_INVALID_AND_TIME_COUNTER_IS_READ_AS_ZERO, //= Time is invalid and time counter is read as zero.
}
1 => TOFro { //! Time Overflow Flag
0 => TIME_OVERFLOW_HAS_NOT_OCCURRED, //= Time overflow has not occurred.
1 => TIME_OVERFLOW_HAS_OCCURRED_AND_TIME_COUNTER_IS_READ_AS_ZERO, //= Time overflow has occurred and time counter is read as zero.
}
2 => TAFro { //! Time Alarm Flag
0 => TIME_ALARM_HAS_NOT_OCCURRED, //= Time alarm has not occurred.
1 => TIME_ALARM_HAS_OCCURRED, //= Time alarm has occurred.
}
4 => TCErw { //! Time Counter Enable
0 => TIME_COUNTER_IS_DISABLED, //= Time counter is disabled.
1 => TIME_COUNTER_IS_ENABLED, //= Time counter is enabled.
}
},
0x18 => reg32 LR { //! RTC Lock Register
3 => TCLrw { //! Time Compensation Lock
0 => TIME_COMPENSATION_REGISTER_IS_LOCKED_AND_WRITES_ARE_IGNORED, //= Time Compensation Register is locked and writes are ignored.
1 => TIME_COMPENSATION_REGISTER_IS_NOT_LOCKED_AND_WRITES_COMPLETE_AS_NORMAL, //= Time Compensation Register is not locked and writes complete as normal.
}
4 => CRLrw { //! Control Register Lock
0 => CONTROL_REGISTER_IS_LOCKED_AND_WRITES_ARE_IGNORED, //= Control Register is locked and writes are ignored.
1 => CONTROL_REGISTER_IS_NOT_LOCKED_AND_WRITES_COMPLETE_AS_NORMAL, //= Control Register is not locked and writes complete as normal.
}
5 => SRLrw { //! Status Register Lock
0 => STATUS_REGISTER_IS_LOCKED_AND_WRITES_ARE_IGNORED, //= Status Register is locked and writes are ignored.
1 => STATUS_REGISTER_IS_NOT_LOCKED_AND_WRITES_COMPLETE_AS_NORMAL, //= Status Register is not locked and writes complete as normal.
}
6 => LRLrw { //! Lock Register Lock
0 => LOCK_REGISTER_IS_LOCKED_AND_WRITES_ARE_IGNORED, //= Lock Register is locked and writes are ignored.
1 => LOCK_REGISTER_IS_NOT_LOCKED_AND_WRITES_COMPLETE_AS_NORMAL, //= Lock Register is not locked and writes complete as normal.
}
},
0x1C => reg32 IER { //! RTC Interrupt Enable Register
0 => TIIErw { //! Time Invalid Interrupt Enable
0 => TIME_INVALID_FLAG_DOES_NOT_GENERATE_AN_INTERRUPT, //= Time invalid flag does not generate an interrupt.
1 => TIME_INVALID_FLAG_DOES_GENERATE_AN_INTERRUPT, //= Time invalid flag does generate an interrupt.
}
1 => TOIErw { //! Time Overflow Interrupt Enable
0 => TIME_OVERFLOW_FLAG_DOES_NOT_GENERATE_AN_INTERRUPT, //= Time overflow flag does not generate an interrupt.
1 => TIME_OVERFLOW_FLAG_DOES_GENERATE_AN_INTERRUPT, //= Time overflow flag does generate an interrupt.
}
2 => TAIErw { //! Time Alarm Interrupt Enable
0 => TIME_ALARM_FLAG_DOES_NOT_GENERATE_AN_INTERRUPT, //= Time alarm flag does not generate an interrupt.
1 => TIME_ALARM_FLAG_DOES_GENERATE_AN_INTERRUPT, //= Time alarm flag does generate an interrupt.
}
4 => TSIErw { //! Time Seconds Interrupt Enable
0 => SECONDS_INTERRUPT_IS_DISABLED, //= Seconds interrupt is disabled.
1 => SECONDS_INTERRUPT_IS_ENABLED, //= Seconds interrupt is enabled.
}
7 => WPONrw { //! Wakeup Pin On
0 => NO_EFFECT, //= No effect.
1 => IF_THE_WAKEUP_PIN_IS_ENABLED_THEN_THE_WAKEUP_PIN_WILL_ASSERT, //= If the wakeup pin is enabled, then the wakeup pin will assert.
}
},
});
ioregs!(DAC0 @ 0x4003F000 = { //! 12-Bit Digital-to-Analog Converter
0x00 => reg8 DAT%sL { //! DAC Data Low Register
0..7 => DATA0 rw, //= no description available
},
0x01 => reg8 DAT%sH { //! DAC Data High Register
0..3 => DATA1 rw, //= no description available
},
0x20 => reg8 SR { //! DAC Status Register
0 => DACBFRPBFrw { //! DAC Buffer Read Pointer Bottom Position Flag
0 => THE_DAC_BUFFER_READ_POINTER_IS_NOT_EQUAL_TO_C2[DACBFUP], //= The DAC buffer read pointer is not equal to C2[DACBFUP].
1 => THE_DAC_BUFFER_READ_POINTER_IS_EQUAL_TO_C2[DACBFUP], //= The DAC buffer read pointer is equal to C2[DACBFUP].
}
1 => DACBFRPTFrw { //! DAC Buffer Read Pointer Top Position Flag
0 => THE_DAC_BUFFER_READ_POINTER_IS_NOT_ZERO, //= The DAC buffer read pointer is not zero.
1 => THE_DAC_BUFFER_READ_POINTER_IS_ZERO, //= The DAC buffer read pointer is zero.
}
},
0x21 => reg8 C0 { //! DAC Control Register
0 => DACBBIENrw { //! DAC Buffer Read Pointer Bottom Flag Interrupt Enable
0 => THE_DAC_BUFFER_READ_POINTER_BOTTOM_FLAG_INTERRUPT_IS_DISABLED, //= The DAC buffer read pointer bottom flag interrupt is disabled.
1 => THE_DAC_BUFFER_READ_POINTER_BOTTOM_FLAG_INTERRUPT_IS_ENABLED, //= The DAC buffer read pointer bottom flag interrupt is enabled.
}
1 => DACBTIENrw { //! DAC Buffer Read Pointer Top Flag Interrupt Enable
0 => THE_DAC_BUFFER_READ_POINTER_TOP_FLAG_INTERRUPT_IS_DISABLED, //= The DAC buffer read pointer top flag interrupt is disabled.
1 => THE_DAC_BUFFER_READ_POINTER_TOP_FLAG_INTERRUPT_IS_ENABLED, //= The DAC buffer read pointer top flag interrupt is enabled.
}
3 => LPENrw { //! DAC Low Power Control
0 => HIGH_POWER_MODE, //= High-Power mode
1 => LOW_POWER_MODE, //= Low-Power mode
}
4 => DACSWTRGwo { //! DAC Software Trigger
0 => THE_DAC_SOFT_TRIGGER_IS_NOT_VALID, //= The DAC soft trigger is not valid.
1 => THE_DAC_SOFT_TRIGGER_IS_VALID, //= The DAC soft trigger is valid.
}
5 => DACTRGSELrw { //! DAC Trigger Select
0 => THE_DAC_HARDWARE_TRIGGER_IS_SELECTED, //= The DAC hardware trigger is selected.
1 => THE_DAC_SOFTWARE_TRIGGER_IS_SELECTED, //= The DAC software trigger is selected.
}
6 => DACRFSrw { //! DAC Reference Select
0 => THE_DAC_SELECTS_DACREF_1_AS_THE_REFERENCE_VOLTAGE, //= The DAC selects DACREF_1 as the reference voltage.
1 => THE_DAC_SELECTS_DACREF_2_AS_THE_REFERENCE_VOLTAGE, //= The DAC selects DACREF_2 as the reference voltage.
}
7 => DACENrw { //! DAC Enable
0 => THE_DAC_SYSTEM_IS_DISABLED, //= The DAC system is disabled.
1 => THE_DAC_SYSTEM_IS_ENABLED, //= The DAC system is enabled.
}
},
0x22 => reg8 C1 { //! DAC Control Register 1
0 => DACBFENrw { //! DAC Buffer Enable
0 => BUFFER_READ_POINTER_IS_DISABLED_THE_CONVERTED_DATA_IS_ALWAYS_THE_FIRST_WORD_OF_THE_BUFFER, //= Buffer read pointer is disabled. The converted data is always the first word of the buffer.
1 => BUFFER_READ_POINTER_IS_ENABLED_THE_CONVERTED_DATA_IS_THE_WORD_THAT_THE_READ_POINTER_POINTS_TO_IT_MEANS_CONVERTED_DATA_CAN_BE_FROM_ANY_WORD_OF_THE_BUFFER, //= Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
}
2 => DACBFMDrw { //! DAC Buffer Work Mode Select
0 => NORMAL_MODE, //= Normal mode
1 => ONE_TIME_SCAN_MODE, //= One-Time Scan mode
}
7 => DMAENrw { //! DMA Enable Select
0 => DMA_IS_DISABLED, //= DMA is disabled.
1 => DMA_IS_ENABLED_WHEN_DMA_IS_ENABLED_THE_DMA_REQUEST_WILL_BE_GENERATED_BY_ORIGINAL_INTERRUPTS_THE_INTERRUPTS_WILL_NOT_BE_PRESENTED_ON_THIS_MODULE_AT_THE_SAME_TIME, //= DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
}
},
0x23 => reg8 C2 { //! DAC Control Register 2
0 => DACBFUP rw, //= DAC Buffer Upper Limit
4 => DACBFRP rw, //= DAC Buffer Read Pointer
},
});
ioregs!(LPTMR0 @ 0x40040000 = { //! Low Power Timer
0x00 => reg32 CSR { //! Low Power Timer Control Status Register
0 => TENrw { //! Timer Enable
0 => LPTMR_IS_DISABLED_AND_INTERNAL_LOGIC_IS_RESET, //= LPTMR is disabled and internal logic is reset.
1 => LPTMR_IS_ENABLED, //= LPTMR is enabled.
}
1 => TMSrw { //! Timer Mode Select
0 => TIME_COUNTER_MODE, //= Time Counter mode.
1 => PULSE_COUNTER_MODE, //= Pulse Counter mode.
}
2 => TFCrw { //! Timer Free-Running Counter
0 => CNR_IS_RESET_WHENEVER_TCF_IS_SET, //= CNR is reset whenever TCF is set.
1 => CNR_IS_RESET_ON_OVERFLOW, //= CNR is reset on overflow.
}
3 => TPPrw { //! Timer Pin Polarity
0 => PULSE_COUNTER_INPUT_SOURCE_IS_ACTIVE_HIGH_AND_THE_CNR_WILL_INCREMENT_ON_THE_RISING_EDGE, //= Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
1 => PULSE_COUNTER_INPUT_SOURCE_IS_ACTIVE_LOW_AND_THE_CNR_WILL_INCREMENT_ON_THE_FALLING_EDGE, //= Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
}
4..5 => TPSrw { //! Timer Pin Select
0 => PULSE_COUNTER_INPUT_0_IS_SELECTED, //= Pulse counter input 0 is selected.
1 => PULSE_COUNTER_INPUT_1_IS_SELECTED, //= Pulse counter input 1 is selected.
2 => PULSE_COUNTER_INPUT_2_IS_SELECTED, //= Pulse counter input 2 is selected.
3 => PULSE_COUNTER_INPUT_3_IS_SELECTED, //= Pulse counter input 3 is selected.
}
6 => TIErw { //! Timer Interrupt Enable
0 => TIMER_INTERRUPT_DISABLED, //= Timer interrupt disabled.
1 => TIMER_INTERRUPT_ENABLED, //= Timer interrupt enabled.
}
7 => TCFrw { //! Timer Compare Flag
0 => THE_VALUE_OF_CNR_IS_NOT_EQUAL_TO_CMR_AND_INCREMENTS, //= The value of CNR is not equal to CMR and increments.
1 => THE_VALUE_OF_CNR_IS_EQUAL_TO_CMR_AND_INCREMENTS, //= The value of CNR is equal to CMR and increments.
}
},
0x04 => reg32 PSR { //! Low Power Timer Prescale Register
0..1 => PCSrw { //! Prescaler Clock Select
0 => PRESCALERGLITCH_FILTER_CLOCK_0_SELECTED, //= Prescaler/glitch filter clock 0 selected.
1 => PRESCALERGLITCH_FILTER_CLOCK_1_SELECTED, //= Prescaler/glitch filter clock 1 selected.
2 => PRESCALERGLITCH_FILTER_CLOCK_2_SELECTED, //= Prescaler/glitch filter clock 2 selected.
3 => PRESCALERGLITCH_FILTER_CLOCK_3_SELECTED, //= Prescaler/glitch filter clock 3 selected.
}
2 => PBYPrw { //! Prescaler Bypass
0 => PRESCALERGLITCH_FILTER_IS_ENABLED, //= Prescaler/glitch filter is enabled.
1 => PRESCALERGLITCH_FILTER_IS_BYPASSED, //= Prescaler/glitch filter is bypassed.
}
3..6 => PRESCALErw { //! Prescale Value
0 => E_0000, //= Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
1 => E_0001, //= Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
2 => E_0010, //= Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
3 => E_0011, //= Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
4 => E_0100, //= Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
5 => E_0101, //= Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
6 => E_0110, //= Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
7 => E_0111, //= Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
8 => E_1000, //= Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
9 => E_1001, //= Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
10 => E_1010, //= Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
11 => E_1011, //= Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
12 => E_1100, //= Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
13 => E_1101, //= Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
14 => E_1110, //= Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
15 => E_1111, //= Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
}
},
0x08 => reg32 CMR { //! Low Power Timer Compare Register
0..15 => COMPARE rw, //= Compare Value
},
0x0C => reg32 CNR { //! Low Power Timer Counter Register
0..15 => COUNTER rw, //= Counter Value
},
});
ioregs!(TSI0 @ 0x40045000 = { //! Touch sense input
0x00 => reg32 GENCS { //! TSI General Control and Status Register
1 => CURSWrw { //! CURSW
0 => THE_CURRENT_SOURCE_PAIR_ARE_NOT_SWAPPED, //= The current source pair are not swapped.
1 => THE_CURRENT_SOURCE_PAIR_ARE_SWAPPED, //= The current source pair are swapped.
}
2 => EOSFrw { //! End of Scan Flag
0 => SCAN_NOT_COMPLETE, //= Scan not complete.
1 => SCAN_COMPLETE, //= Scan complete.
}
3 => SCNIPro { //! Scan In Progress Status
0 => NO_SCAN_IN_PROGRESS, //= No scan in progress.
1 => SCAN_IN_PROGRESS, //= Scan in progress.
}
4 => STMrw { //! Scan Trigger Mode
0 => SOFTWARE_TRIGGER_SCAN, //= Software trigger scan.
1 => HARDWARE_TRIGGER_SCAN, //= Hardware trigger scan.
}
5 => STPErw { //! TSI STOP Enable
0 => TSI_IS_DISABLED_WHEN_MCU_GOES_INTO_LOW_POWER_MODE, //= TSI is disabled when MCU goes into low power mode.
1 => ALLOWS_TSI_TO_CONTINUE_RUNNING_IN_ALL_LOW_POWER_MODES, //= Allows TSI to continue running in all low power modes.
}
6 => TSIIENrw { //! Touch Sensing Input Interrupt Enable
0 => TSI_INTERRUPT_IS_DISABLED, //= TSI interrupt is disabled.
1 => TSI_INTERRUPT_IS_ENABLED, //= TSI interrupt is enabled.
}
7 => TSIENrw { //! Touch Sensing Input Module Enable
0 => TSI_MODULE_DISABLED, //= TSI module disabled.
1 => TSI_MODULE_ENABLED, //= TSI module enabled.
}
8..12 => NSCNrw { //! NSCN
0 => ONCE_PER_ELECTRODE, //= Once per electrode
1 => TWICE_PER_ELECTRODE, //= Twice per electrode
2 => 3_TIMES_PER_ELECTRODE, //= 3 times per electrode
3 => 4_TIMES_PER_ELECTRODE, //= 4 times per electrode
4 => 5_TIMES_PER_ELECTRODE, //= 5 times per electrode
5 => 6_TIMES_PER_ELECTRODE, //= 6 times per electrode
6 => 7_TIMES_PER_ELECTRODE, //= 7 times per electrode
7 => 8_TIMES_PER_ELECTRODE, //= 8 times per electrode
8 => 9_TIMES_PER_ELECTRODE, //= 9 times per electrode
9 => 10_TIMES_PER_ELECTRODE, //= 10 times per electrode
10 => 11_TIMES_PER_ELECTRODE, //= 11 times per electrode
11 => 12_TIMES_PER_ELECTRODE, //= 12 times per electrode
12 => 13_TIMES_PER_ELECTRODE, //= 13 times per electrode
13 => 14_TIMES_PER_ELECTRODE, //= 14 times per electrode
14 => 15_TIMES_PER_ELECTRODE, //= 15 times per electrode
15 => 16_TIMES_PER_ELECTRODE, //= 16 times per electrode
16 => 17_TIMES_PER_ELECTRODE, //= 17 times per electrode
17 => 18_TIMES_PER_ELECTRODE, //= 18 times per electrode
18 => 19_TIMES_PER_ELECTRODE, //= 19 times per electrode
19 => 20_TIMES_PER_ELECTRODE, //= 20 times per electrode
20 => 21_TIMES_PER_ELECTRODE, //= 21 times per electrode
21 => 22_TIMES_PER_ELECTRODE, //= 22 times per electrode
22 => 23_TIMES_PER_ELECTRODE, //= 23 times per electrode
23 => 24_TIMES_PER_ELECTRODE, //= 24 times per electrode
24 => 25_TIMES_PER_ELECTRODE, //= 25 times per electrode
25 => 26_TIMES_PER_ELECTRODE, //= 26 times per electrode
26 => 27_TIMES_PER_ELECTRODE, //= 27 times per electrode
27 => 28_TIMES_PER_ELECTRODE, //= 28 times per electrode
28 => 29_TIMES_PER_ELECTRODE, //= 29 times per electrode
29 => 30_TIMES_PER_ELECTRODE, //= 30 times per electrode
30 => 31_TIMES_PER_ELECTRODE, //= 31 times per electrode
31 => 32_TIMES_PER_ELECTRODE, //= 32 times per electrode
}
13..15 => PSrw { //! PS
0 => ELECTRODE_OSCILLATOR_FREQUENCY_DIVIDED_BY_1, //= Electrode Oscillator Frequency divided by 1
1 => ELECTRODE_OSCILLATOR_FREQUENCY_DIVIDED_BY_2, //= Electrode Oscillator Frequency divided by 2
2 => ELECTRODE_OSCILLATOR_FREQUENCY_DIVIDED_BY_4, //= Electrode Oscillator Frequency divided by 4
3 => ELECTRODE_OSCILLATOR_FREQUENCY_DIVIDED_BY_8, //= Electrode Oscillator Frequency divided by 8
4 => ELECTRODE_OSCILLATOR_FREQUENCY_DIVIDED_BY_16, //= Electrode Oscillator Frequency divided by 16
5 => ELECTRODE_OSCILLATOR_FREQUENCY_DIVIDED_BY_32, //= Electrode Oscillator Frequency divided by 32
6 => ELECTRODE_OSCILLATOR_FREQUENCY_DIVIDED_BY_64, //= Electrode Oscillator Frequency divided by 64
7 => ELECTRODE_OSCILLATOR_FREQUENCY_DIVIDED_BY_128, //= Electrode Oscillator Frequency divided by 128
}
16..18 => EXTCHRGrw { //! EXTCHRG
0 => 500_NA, //= 500 nA.
1 => 1_UA, //= 1 uA.
2 => 2_UA, //= 2 uA.
3 => 4_UA, //= 4 uA.
4 => 8_UA, //= 8 uA.
5 => 16_UA, //= 16 uA.
6 => 32_UA, //= 32 uA.
7 => 64_UA, //= 64 uA.
}
19..20 => DVOLTrw { //! DVOLT
0 => E_00, //= DV = 1.03 V; VP = 1.33 V; Vm = 0.30 V.
1 => E_01, //= DV = 0.73 V; VP = 1.18 V; Vm = 0.45 V.
2 => E_10, //= DV = 0.43 V; VP = 1.03 V; Vm = 0.60 V.
3 => E_11, //= DV = 0.29 V; VP = 0.95 V; Vm = 0.67 V.
}
21..23 => REFCHRGrw { //! REFCHRG
0 => 500_NA, //= 500 nA.
1 => 1_UA, //= 1 uA.
2 => 2_UA, //= 2 uA.
3 => 4_UA, //= 4 uA.
4 => 8_UA, //= 8 uA.
5 => 16_UA, //= 16 uA.
6 => 32_UA, //= 32 uA.
7 => 64_UA, //= 64 uA.
}
24..27 => MODErw { //! TSI analog modes setup and status bits.
0 => E_0000, //= Set TSI in capacitive sensing(non-noise detection) mode.
4 => SET_TSI_ANALOG_TO_WORK_IN_SINGLE_THRESHOLD_NOISE_DETECTION_MODE_AND_THE_FREQUENCY_LIMITATION_CIRCUIT_IS_DISABLED, //= Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled.
8 => SET_TSI_ANALOG_TO_WORK_IN_SINGLE_THRESHOLD_NOISE_DETECTION_MODE_AND_THE_FREQUENCY_LIMITATION_CIRCUIT_IS_ENABLED_TO_WORK_IN_HIGHER_FREQUENCIES_OPERATIONS, //= Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations.
12 => SET_TSI_ANALOG_TO_WORK_IN_AUTOMATIC_NOISE_DETECTION_MODE, //= Set TSI analog to work in automatic noise detection mode.
}
28 => ESORrw { //! End-of-scan or Out-of-Range Interrupt Selection
0 => OUT_OF_RANGE_INTERRUPT_IS_ALLOWED, //= Out-of-range interrupt is allowed.
1 => END_OF_SCAN_INTERRUPT_IS_ALLOWED, //= End-of-scan interrupt is allowed.
}
31 => OUTRGF rw, //= Out of Range Flag.
},
0x04 => reg32 DATA { //! TSI DATA Register
0..15 => TSICNT ro, //= TSI Conversion Counter Value
22 => SWTSwo { //! Software Trigger Start
0 => NO_EFFECT, //= No effect.
1 => START_A_SCAN_TO_DETERMINE_WHICH_CHANNEL_IS_SPECIFIED_BY_TSI_DATA[TSICH], //= Start a scan to determine which channel is specified by TSI_DATA[TSICH].
}
23 => DMAENrw { //! DMA Transfer Enabled
0 => INTERRUPT_IS_SELECTED_WHEN_THE_INTERRUPT_ENABLE_BIT_IS_SET_AND_THE_CORRESPONDING_TSI_EVENTS_ASSERT, //= Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.
1 => DMA_TRANSFER_REQUEST_IS_SELECTED_WHEN_THE_INTERRUPT_ENABLE_BIT_IS_SET_AND_THE_CORRESPONDING_TSI_EVENTS_ASSERT, //= DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.
}
28..31 => TSICHrw { //! TSICH
0 => CHANNEL_0, //= Channel 0.
1 => CHANNEL_1, //= Channel 1.
2 => CHANNEL_2, //= Channel 2.
3 => CHANNEL_3, //= Channel 3.
4 => CHANNEL_4, //= Channel 4.
5 => CHANNEL_5, //= Channel 5.
6 => CHANNEL_6, //= Channel 6.
7 => CHANNEL_7, //= Channel 7.
8 => CHANNEL_8, //= Channel 8.
9 => CHANNEL_9, //= Channel 9.
10 => CHANNEL_10, //= Channel 10.
11 => CHANNEL_11, //= Channel 11.
12 => CHANNEL_12, //= Channel 12.
13 => CHANNEL_13, //= Channel 13.
14 => CHANNEL_14, //= Channel 14.
15 => CHANNEL_15, //= Channel 15.
}
},
0x08 => reg32 TSHD { //! TSI Threshold Register
0..15 => THRESL rw, //= TSI Wakeup Channel Low-threshold
16..31 => THRESH rw, //= TSI Wakeup Channel High-threshold
},
});
ioregs!(SIM @ 0x40047000 = { //! System Integration Module
0x00 => reg32 SOPT1 { //! System Options Register 1
18..19 => OSC32KSELrw { //! 32K oscillator clock select
0 => E_00, //= System oscillator (OSC32KCLK)
2 => RTC_CLKIN, //= RTC_CLKIN
3 => LPO_1KHZ, //= LPO 1kHz
}
29 => USBVSTBYrw { //! USB voltage regulator in standby mode during VLPR and VLPW modes
0 => USB_VOLTAGE_REGULATOR_NOT_IN_STANDBY_DURING_VLPR_AND_VLPW_MODES, //= USB voltage regulator not in standby during VLPR and VLPW modes.
1 => USB_VOLTAGE_REGULATOR_IN_STANDBY_DURING_VLPR_AND_VLPW_MODES, //= USB voltage regulator in standby during VLPR and VLPW modes.
}
30 => USBSSTBYrw { //! USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
0 => USB_VOLTAGE_REGULATOR_NOT_IN_STANDBY_DURING_STOP_VLPS_LLS_AND_VLLS_MODES, //= USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
1 => USB_VOLTAGE_REGULATOR_IN_STANDBY_DURING_STOP_VLPS_LLS_AND_VLLS_MODES, //= USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
}
31 => USBREGENrw { //! USB voltage regulator enable
0 => USB_VOLTAGE_REGULATOR_IS_DISABLED, //= USB voltage regulator is disabled.
1 => USB_VOLTAGE_REGULATOR_IS_ENABLED, //= USB voltage regulator is enabled.
}
},
0x04 => reg32 SOPT1CFG { //! SOPT1 Configuration Register
24 => URWErw { //! USB voltage regulator enable write enable
0 => SOPT1_USBREGEN_CANNOT_BE_WRITTEN, //= SOPT1 USBREGEN cannot be written.
1 => SOPT1_USBREGEN_CAN_BE_WRITTEN, //= SOPT1 USBREGEN can be written.
}
25 => UVSWErw { //! USB voltage regulator VLP standby write enable
0 => SOPT1_USBVSTB_CANNOT_BE_WRITTEN, //= SOPT1 USBVSTB cannot be written.
1 => SOPT1_USBVSTB_CAN_BE_WRITTEN, //= SOPT1 USBVSTB can be written.
}
26 => USSWErw { //! USB voltage regulator stop standby write enable
0 => SOPT1_USBSSTB_CANNOT_BE_WRITTEN, //= SOPT1 USBSSTB cannot be written.
1 => SOPT1_USBSSTB_CAN_BE_WRITTEN, //= SOPT1 USBSSTB can be written.
}
},
0x1004 => reg32 SOPT2 { //! System Options Register 2
4 => RTCCLKOUTSELrw { //! RTC clock out select
0 => RTC_1_HZ_CLOCK_IS_OUTPUT_ON_THE_RTC_CLKOUT_PIN, //= RTC 1 Hz clock is output on the RTC_CLKOUT pin.
1 => OSCERCLK_CLOCK_IS_OUTPUT_ON_THE_RTC_CLKOUT_PIN, //= OSCERCLK clock is output on the RTC_CLKOUT pin.
}
5..7 => CLKOUTSELrw { //! CLKOUT select
2 => BUS_CLOCK, //= Bus clock
3 => E_011, //= LPO clock (1 kHz)
4 => MCGIRCLK, //= MCGIRCLK
6 => OSCERCLK, //= OSCERCLK
}
16 => PLLFLLSELrw { //! PLL/FLL clock select
0 => MCGFLLCLK_CLOCK, //= MCGFLLCLK clock
1 => MCGPLLCLK_CLOCK_WITH_FIXED_DIVIDE_BY_TWO, //= MCGPLLCLK clock with fixed divide by two
}
18 => USBSRCrw { //! USB clock source select
0 => E_0, //= External bypass clock (USB_CLKIN).
1 => MCGPLLCLK2_OR_MCGFLLCLK_CLOCK, //= MCGPLLCLK/2 or MCGFLLCLK clock
}
24..25 => TPMSRCrw { //! TPM clock source select
0 => CLOCK_DISABLED, //= Clock disabled
1 => MCGFLLCLK_CLOCK_OR_MCGPLLCLK2, //= MCGFLLCLK clock or MCGPLLCLK/2
2 => OSCERCLK_CLOCK, //= OSCERCLK clock
3 => MCGIRCLK_CLOCK, //= MCGIRCLK clock
}
26..27 => UART0SRCrw { //! UART0 clock source select
0 => CLOCK_DISABLED, //= Clock disabled
1 => MCGFLLCLK_CLOCK_OR_MCGPLLCLK2_CLOCK, //= MCGFLLCLK clock or MCGPLLCLK/2 clock
2 => OSCERCLK_CLOCK, //= OSCERCLK clock
3 => MCGIRCLK_CLOCK, //= MCGIRCLK clock
}
},
0x100C => reg32 SOPT4 { //! System Options Register 4
18 => TPM1CH0SRCrw { //! TPM1 channel 0 input capture source select
0 => TPM1_CH0_SIGNAL, //= TPM1_CH0 signal
1 => CMP0_OUTPUT, //= CMP0 output
}
20 => TPM2CH0SRCrw { //! TPM2 channel 0 input capture source select
0 => TPM2_CH0_SIGNAL, //= TPM2_CH0 signal
1 => CMP0_OUTPUT, //= CMP0 output
}
24 => TPM0CLKSELrw { //! TPM0 External Clock Pin Select
0 => TPM0_EXTERNAL_CLOCK_DRIVEN_BY_TPM_CLKIN0_PIN, //= TPM0 external clock driven by TPM_CLKIN0 pin.
1 => TPM0_EXTERNAL_CLOCK_DRIVEN_BY_TPM_CLKIN1_PIN, //= TPM0 external clock driven by TPM_CLKIN1 pin.
}
25 => TPM1CLKSELrw { //! TPM1 External Clock Pin Select
0 => TPM1_EXTERNAL_CLOCK_DRIVEN_BY_TPM_CLKIN0_PIN, //= TPM1 external clock driven by TPM_CLKIN0 pin.
1 => TPM1_EXTERNAL_CLOCK_DRIVEN_BY_TPM_CLKIN1_PIN, //= TPM1 external clock driven by TPM_CLKIN1 pin.
}
26 => TPM2CLKSELrw { //! TPM2 External Clock Pin Select
0 => TPM2_EXTERNAL_CLOCK_DRIVEN_BY_TPM_CLKIN0_PIN, //= TPM2 external clock driven by TPM_CLKIN0 pin.
1 => TPM2_EXTERNAL_CLOCK_DRIVEN_BY_TPM_CLKIN1_PIN, //= TPM2 external clock driven by TPM_CLKIN1 pin.
}
},
0x1010 => reg32 SOPT5 { //! System Options Register 5
0..1 => UART0TXSRCrw { //! UART0 transmit data source select
0 => UART0_TX_PIN, //= UART0_TX pin
1 => UART0_TX_PIN_MODULATED_WITH_TPM1_CHANNEL_0_OUTPUT, //= UART0_TX pin modulated with TPM1 channel 0 output
2 => UART0_TX_PIN_MODULATED_WITH_TPM2_CHANNEL_0_OUTPUT, //= UART0_TX pin modulated with TPM2 channel 0 output
}
2 => UART0RXSRCrw { //! UART0 receive data source select
0 => UART0_RX_PIN, //= UART0_RX pin
1 => CMP0_OUTPUT, //= CMP0 output
}
4..5 => UART1TXSRCrw { //! UART1 transmit data source select
0 => UART1_TX_PIN, //= UART1_TX pin
1 => UART1_TX_PIN_MODULATED_WITH_TPM1_CHANNEL_0_OUTPUT, //= UART1_TX pin modulated with TPM1 channel 0 output
2 => UART1_TX_PIN_MODULATED_WITH_TPM2_CHANNEL_0_OUTPUT, //= UART1_TX pin modulated with TPM2 channel 0 output
}
6 => UART1RXSRCrw { //! UART1 receive data source select
0 => UART1_RX_PIN, //= UART1_RX pin
1 => CMP0_OUTPUT, //= CMP0 output
}
16 => UART0ODErw { //! UART0 Open Drain Enable
0 => OPEN_DRAIN_IS_DISABLED_ON_UART0, //= Open drain is disabled on UART0
1 => OPEN_DRAIN_IS_ENABLED_ON_UART0, //= Open drain is enabled on UART0
}
17 => UART1ODErw { //! UART1 Open Drain Enable
0 => OPEN_DRAIN_IS_DISABLED_ON_UART1, //= Open drain is disabled on UART1
1 => OPEN_DRAIN_IS_ENABLED_ON_UART1, //= Open drain is enabled on UART1
}
18 => UART2ODErw { //! UART2 Open Drain Enable
0 => OPEN_DRAIN_IS_DISABLED_ON_UART2, //= Open drain is disabled on UART2
1 => OPEN_DRAIN_IS_ENABLED_ON_UART2, //= Open drain is enabled on UART2
}
},
0x1018 => reg32 SOPT7 { //! System Options Register 7
0..3 => ADC0TRGSELrw { //! ADC0 trigger select
0 => E_0000, //= External trigger pin input (EXTRG_IN)
1 => CMP0_OUTPUT, //= CMP0 output
4 => PIT_TRIGGER_0, //= PIT trigger 0
5 => PIT_TRIGGER_1, //= PIT trigger 1
8 => TPM0_OVERFLOW, //= TPM0 overflow
9 => TPM1_OVERFLOW, //= TPM1 overflow
10 => TPM2_OVERFLOW, //= TPM2 overflow
12 => RTC_ALARM, //= RTC alarm
13 => RTC_SECONDS, //= RTC seconds
14 => LPTMR0_TRIGGER, //= LPTMR0 trigger
}
4 => ADC0PRETRGSELrw { //! ADC0 pretrigger select
0 => PRE_TRIGGER_A, //= Pre-trigger A
1 => PRE_TRIGGER_B, //= Pre-trigger B
}
7 => ADC0ALTTRGENrw { //! ADC0 alternate trigger enable
0 => E_0, //= TPM1 channel 0 (A) and channel 1 (B) triggers selected for ADC0.
1 => ALTERNATE_TRIGGER_SELECTED_FOR_ADC0, //= Alternate trigger selected for ADC0.
}
},
0x1024 => reg32 SDID { //! System Device Identification Register
0..3 => PINIDro { //! Pincount identification
0 => 16_PIN, //= 16-pin
1 => 24_PIN, //= 24-pin
2 => 32_PIN, //= 32-pin
4 => 48_PIN, //= 48-pin
5 => 64_PIN, //= 64-pin
6 => 80_PIN, //= 80-pin
8 => 100_PIN, //= 100-pin
}
7..11 => DIEID ro, //= Device die number
12..15 => REVID ro, //= Device revision number
16..19 => SRAMSIZEro { //! System SRAM Size
0 => 05_KB, //= 0.5 KB
1 => 1_KB, //= 1 KB
2 => 2_KB, //= 2 KB
3 => 4_KB, //= 4 KB
4 => 8_KB, //= 8 KB
5 => 16_KB, //= 16 KB
6 => 32_KB, //= 32 KB
7 => 64_KB, //= 64 KB
}
20..23 => SERIESIDro { //! Kinetis Series ID
1 => KL_FAMILY, //= KL family
}
24..27 => SUBFAMIDro { //! Kinetis Sub-Family ID
2 => E_0010, //= KLx2 Subfamily (low end)
4 => E_0100, //= KLx4 Subfamily (basic analog)
5 => E_0101, //= KLx5 Subfamily (advanced analog)
6 => E_0110, //= KLx6 Subfamily (advanced analog with I2S)
}
28..31 => FAMIDro { //! Kinetis family ID
0 => E_0000, //= KL0x Family (low end)
1 => E_0001, //= KL1x Family (basic)
2 => E_0010, //= KL2x Family (USB)
3 => E_0011, //= KL3x Family (Segment LCD)
4 => E_0100, //= KL4x Family (USB and Segment LCD)
}
},
0x1034 => reg32 SCGC4 { //! System Clock Gating Control Register 4
6 => I2C0rw { //! I2C0 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
7 => I2C1rw { //! I2C1 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
10 => UART0rw { //! UART0 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
11 => UART1rw { //! UART1 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
12 => UART2rw { //! UART2 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
18 => USBOTGrw { //! USB Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
19 => CMPrw { //! Comparator Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
22 => SPI0rw { //! SPI0 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
23 => SPI1rw { //! SPI1 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
},
0x1038 => reg32 SCGC5 { //! System Clock Gating Control Register 5
0 => LPTMRrw { //! Low Power Timer Access Control
0 => ACCESS_DISABLED, //= Access disabled
1 => ACCESS_ENABLED, //= Access enabled
}
5 => TSIrw { //! TSI Access Control
0 => ACCESS_DISABLED, //= Access disabled
1 => ACCESS_ENABLED, //= Access enabled
}
9 => PORTArw { //! Port A Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
10 => PORTBrw { //! Port B Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
11 => PORTCrw { //! Port C Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
12 => PORTDrw { //! Port D Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
13 => PORTErw { //! Port E Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
},
0x103C => reg32 SCGC6 { //! System Clock Gating Control Register 6
0 => FTFrw { //! Flash Memory Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
1 => DMAMUXrw { //! DMA Mux Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
23 => PITrw { //! PIT Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
24 => TPM0rw { //! TPM0 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
25 => TPM1rw { //! TPM1 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
26 => TPM2rw { //! TPM2 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
27 => ADC0rw { //! ADC0 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
29 => RTCrw { //! RTC Access Control
0 => ACCESS_AND_INTERRUPTS_DISABLED, //= Access and interrupts disabled
1 => ACCESS_AND_INTERRUPTS_ENABLED, //= Access and interrupts enabled
}
31 => DAC0rw { //! DAC0 Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
},
0x1040 => reg32 SCGC7 { //! System Clock Gating Control Register 7
8 => DMArw { //! DMA Clock Gate Control
0 => CLOCK_DISABLED, //= Clock disabled
1 => CLOCK_ENABLED, //= Clock enabled
}
},
0x1044 => reg32 CLKDIV1 { //! System Clock Divider Register 1
16..18 => OUTDIV4rw { //! Clock 4 output divider value
0 => DIVIDE_BY_1, //= Divide-by-1.
1 => DIVIDE_BY_2, //= Divide-by-2.
2 => DIVIDE_BY_3, //= Divide-by-3.
3 => DIVIDE_BY_4, //= Divide-by-4.
4 => DIVIDE_BY_5, //= Divide-by-5.
5 => DIVIDE_BY_6, //= Divide-by-6.
6 => DIVIDE_BY_7, //= Divide-by-7.
7 => DIVIDE_BY_8, //= Divide-by-8.
}
28..31 => OUTDIV1rw { //! Clock 1 output divider value
0 => DIVIDE_BY_1, //= Divide-by-1.
1 => DIVIDE_BY_2, //= Divide-by-2.
2 => DIVIDE_BY_3, //= Divide-by-3.
3 => DIVIDE_BY_4, //= Divide-by-4.
4 => DIVIDE_BY_5, //= Divide-by-5.
5 => DIVIDE_BY_6, //= Divide-by-6.
6 => DIVIDE_BY_7, //= Divide-by-7.
7 => DIVIDE_BY_8, //= Divide-by-8.
8 => DIVIDE_BY_9, //= Divide-by-9.
9 => DIVIDE_BY_10, //= Divide-by-10.
10 => DIVIDE_BY_11, //= Divide-by-11.
11 => DIVIDE_BY_12, //= Divide-by-12.
12 => DIVIDE_BY_13, //= Divide-by-13.
13 => DIVIDE_BY_14, //= Divide-by-14.
14 => DIVIDE_BY_15, //= Divide-by-15.
15 => DIVIDE_BY_16, //= Divide-by-16.
}
},
0x104C => reg32 FCFG1 { //! Flash Configuration Register 1
0 => FLASHDISrw { //! Flash Disable
0 => FLASH_IS_ENABLED, //= Flash is enabled
1 => FLASH_IS_DISABLED, //= Flash is disabled
}
1 => FLASHDOZErw { //! Flash Doze
0 => FLASH_REMAINS_ENABLED_DURING_DOZE_MODE, //= Flash remains enabled during Doze mode
1 => FLASH_IS_DISABLED_FOR_THE_DURATION_OF_DOZE_MODE, //= Flash is disabled for the duration of Doze mode
}
24..27 => PFSIZEro { //! Program flash size
0 => 8_KB_OF_PROGRAM_FLASH_MEMORY_025_KB_PROTECTION_REGION, //= 8 KB of program flash memory, 0.25 KB protection region
1 => 16_KB_OF_PROGRAM_FLASH_MEMORY_05_KB_PROTECTION_REGION, //= 16 KB of program flash memory, 0.5 KB protection region
3 => 32_KB_OF_PROGRAM_FLASH_MEMORY_1_KB_PROTECTION_REGION, //= 32 KB of program flash memory, 1 KB protection region
5 => 64_KB_OF_PROGRAM_FLASH_MEMORY_2_KB_PROTECTION_REGION, //= 64 KB of program flash memory, 2 KB protection region
7 => 128_KB_OF_PROGRAM_FLASH_MEMORY_4_KB_PROTECTION_REGION, //= 128 KB of program flash memory, 4 KB protection region
9 => 256_KB_OF_PROGRAM_FLASH_MEMORY_8_KB_PROTECTION_REGION, //= 256 KB of program flash memory, 8 KB protection region
15 => 128_KB_OF_PROGRAM_FLASH_MEMORY_4_KB_PROTECTION_REGION, //= 128 KB of program flash memory, 4 KB protection region
}
},
0x1050 => reg32 FCFG2 { //! Flash Configuration Register 2
24..30 => MAXADDR0 ro, //= Max address block
},
0x1058 => reg32 UIDMH { //! Unique Identification Register Mid-High
0..15 => UID ro, //= Unique Identification
},
0x105C => reg32 UIDML { //! Unique Identification Register Mid Low
0..31 => UID ro, //= Unique Identification
},
0x1060 => reg32 UIDL { //! Unique Identification Register Low
0..31 => UID ro, //= Unique Identification
},
0x1100 => reg32 COPC { //! COP Control Register
0 => COPWrw { //! COP windowed mode
0 => NORMAL_MODE, //= Normal mode
1 => WINDOWED_MODE, //= Windowed mode
}
1 => COPCLKSrw { //! COP Clock Select
0 => INTERNAL_1_KHZ_CLOCK_IS_SOURCE_TO_COP, //= Internal 1 kHz clock is source to COP
1 => BUS_CLOCK_IS_SOURCE_TO_COP, //= Bus clock is source to COP
}
2..3 => COPTrw { //! COP Watchdog Timeout
0 => COP_DISABLED, //= COP disabled
1 => COP_TIMEOUT_AFTER_25_LPO_CYCLES_OR_213_BUS_CLOCK_CYCLES, //= COP timeout after 2^5 LPO cycles or 213 bus clock cycles
2 => COP_TIMEOUT_AFTER_28_LPO_CYCLES_OR_216_BUS_CLOCK_CYCLES, //= COP timeout after 2^8 LPO cycles or 216 bus clock cycles
3 => COP_TIMEOUT_AFTER_210_LPO_CYCLES_OR_218_BUS_CLOCK_CYCLES, //= COP timeout after 2^10 LPO cycles or 218 bus clock cycles
}
},
0x1104 => reg32 SRVCOP { //! Service COP Register
0..7 => SRVCOP wo, //= Sevice COP Register
},
});
ioregs!(PORTA @ 0x40049000 = { //! Pin Control and Interrupts
0x00 => reg32 PCR%s { //! Pin Control Register n
0 => PSrw { //! Pull Select
0 => INTERNAL_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
1 => INTERNAL_PULLUP_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
}
1 => PErw { //! Pull Enable
0 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_NOT_ENABLED_ON_THE_CORRESPONDING_PIN, //= Internal pullup or pulldown resistor is not enabled on the corresponding pin.
1 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT, //= Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
}
2 => SRErw { //! Slew Rate Enable
0 => FAST_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
1 => SLOW_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
}
4 => PFErw { //! Passive Filter Enable
0 => PASSIVE_INPUT_FILTER_IS_DISABLED_ON_THE_CORRESPONDING_PIN, //= Passive input filter is disabled on the corresponding pin.
1 => PASSIVE_INPUT_FILTER_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT_REFER_TO_THE_DEVICE_DATA_SHEET_FOR_FILTER_CHARACTERISTICS, //= Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
}
6 => DSErw { //! Drive Strength Enable
0 => LOW_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 => HIGH_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
}
8..10 => MUXrw { //! Pin Mux Control
0 => E_000, //= Pin disabled (analog).
1 => E_001, //= Alternative 1 (GPIO).
2 => E_010, //= Alternative 2 (chip-specific).
3 => E_011, //= Alternative 3 (chip-specific).
4 => E_100, //= Alternative 4 (chip-specific).
5 => E_101, //= Alternative 5 (chip-specific).
6 => E_110, //= Alternative 6 (chip-specific).
7 => E_111, //= Alternative 7 (chip-specific).
}
16..19 => IRQCrw { //! Interrupt Configuration
0 => INTERRUPTDMA_REQUEST_DISABLED, //= Interrupt/DMA request disabled.
1 => DMA_REQUEST_ON_RISING_EDGE, //= DMA request on rising edge.
2 => DMA_REQUEST_ON_FALLING_EDGE, //= DMA request on falling edge.
3 => DMA_REQUEST_ON_EITHER_EDGE, //= DMA request on either edge.
8 => INTERRUPT_WHEN_LOGIC_ZERO, //= Interrupt when logic zero.
9 => INTERRUPT_ON_RISING_EDGE, //= Interrupt on rising edge.
10 => INTERRUPT_ON_FALLING_EDGE, //= Interrupt on falling edge.
11 => INTERRUPT_ON_EITHER_EDGE, //= Interrupt on either edge.
12 => INTERRUPT_WHEN_LOGIC_ONE, //= Interrupt when logic one.
}
24 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
0x80 => reg32 GPCLR { //! Global Pin Control Low Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0x84 => reg32 GPCHR { //! Global Pin Control High Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0xA0 => reg32 ISFR { //! Interrupt Status Flag Register
0..31 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
});
ioregs!(PORTB @ 0x4004A000 = { //! Pin Control and Interrupts
0x00 => reg32 PCR%s { //! Pin Control Register n
0 => PSrw { //! Pull Select
0 => INTERNAL_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
1 => INTERNAL_PULLUP_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
}
1 => PErw { //! Pull Enable
0 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_NOT_ENABLED_ON_THE_CORRESPONDING_PIN, //= Internal pullup or pulldown resistor is not enabled on the corresponding pin.
1 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT, //= Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
}
2 => SRErw { //! Slew Rate Enable
0 => FAST_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
1 => SLOW_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
}
4 => PFErw { //! Passive Filter Enable
0 => PASSIVE_INPUT_FILTER_IS_DISABLED_ON_THE_CORRESPONDING_PIN, //= Passive input filter is disabled on the corresponding pin.
1 => PASSIVE_INPUT_FILTER_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT_REFER_TO_THE_DEVICE_DATA_SHEET_FOR_FILTER_CHARACTERISTICS, //= Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
}
6 => DSErw { //! Drive Strength Enable
0 => LOW_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 => HIGH_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
}
8..10 => MUXrw { //! Pin Mux Control
0 => E_000, //= Pin disabled (analog).
1 => E_001, //= Alternative 1 (GPIO).
2 => E_010, //= Alternative 2 (chip-specific).
3 => E_011, //= Alternative 3 (chip-specific).
4 => E_100, //= Alternative 4 (chip-specific).
5 => E_101, //= Alternative 5 (chip-specific).
6 => E_110, //= Alternative 6 (chip-specific).
7 => E_111, //= Alternative 7 (chip-specific).
}
16..19 => IRQCrw { //! Interrupt Configuration
0 => INTERRUPTDMA_REQUEST_DISABLED, //= Interrupt/DMA request disabled.
1 => DMA_REQUEST_ON_RISING_EDGE, //= DMA request on rising edge.
2 => DMA_REQUEST_ON_FALLING_EDGE, //= DMA request on falling edge.
3 => DMA_REQUEST_ON_EITHER_EDGE, //= DMA request on either edge.
8 => INTERRUPT_WHEN_LOGIC_ZERO, //= Interrupt when logic zero.
9 => INTERRUPT_ON_RISING_EDGE, //= Interrupt on rising edge.
10 => INTERRUPT_ON_FALLING_EDGE, //= Interrupt on falling edge.
11 => INTERRUPT_ON_EITHER_EDGE, //= Interrupt on either edge.
12 => INTERRUPT_WHEN_LOGIC_ONE, //= Interrupt when logic one.
}
24 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
0x80 => reg32 GPCLR { //! Global Pin Control Low Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0x84 => reg32 GPCHR { //! Global Pin Control High Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0xA0 => reg32 ISFR { //! Interrupt Status Flag Register
0..31 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
});
ioregs!(PORTC @ 0x4004B000 = { //! Pin Control and Interrupts
0x00 => reg32 PCR%s { //! Pin Control Register n
0 => PSrw { //! Pull Select
0 => INTERNAL_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
1 => INTERNAL_PULLUP_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
}
1 => PErw { //! Pull Enable
0 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_NOT_ENABLED_ON_THE_CORRESPONDING_PIN, //= Internal pullup or pulldown resistor is not enabled on the corresponding pin.
1 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT, //= Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
}
2 => SRErw { //! Slew Rate Enable
0 => FAST_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
1 => SLOW_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
}
4 => PFErw { //! Passive Filter Enable
0 => PASSIVE_INPUT_FILTER_IS_DISABLED_ON_THE_CORRESPONDING_PIN, //= Passive input filter is disabled on the corresponding pin.
1 => PASSIVE_INPUT_FILTER_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT_REFER_TO_THE_DEVICE_DATA_SHEET_FOR_FILTER_CHARACTERISTICS, //= Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
}
6 => DSErw { //! Drive Strength Enable
0 => LOW_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 => HIGH_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
}
8..10 => MUXrw { //! Pin Mux Control
0 => E_000, //= Pin disabled (analog).
1 => E_001, //= Alternative 1 (GPIO).
2 => E_010, //= Alternative 2 (chip-specific).
3 => E_011, //= Alternative 3 (chip-specific).
4 => E_100, //= Alternative 4 (chip-specific).
5 => E_101, //= Alternative 5 (chip-specific).
6 => E_110, //= Alternative 6 (chip-specific).
7 => E_111, //= Alternative 7 (chip-specific).
}
16..19 => IRQCrw { //! Interrupt Configuration
0 => INTERRUPTDMA_REQUEST_DISABLED, //= Interrupt/DMA request disabled.
1 => DMA_REQUEST_ON_RISING_EDGE, //= DMA request on rising edge.
2 => DMA_REQUEST_ON_FALLING_EDGE, //= DMA request on falling edge.
3 => DMA_REQUEST_ON_EITHER_EDGE, //= DMA request on either edge.
8 => INTERRUPT_WHEN_LOGIC_ZERO, //= Interrupt when logic zero.
9 => INTERRUPT_ON_RISING_EDGE, //= Interrupt on rising edge.
10 => INTERRUPT_ON_FALLING_EDGE, //= Interrupt on falling edge.
11 => INTERRUPT_ON_EITHER_EDGE, //= Interrupt on either edge.
12 => INTERRUPT_WHEN_LOGIC_ONE, //= Interrupt when logic one.
}
24 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
0x80 => reg32 GPCLR { //! Global Pin Control Low Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0x84 => reg32 GPCHR { //! Global Pin Control High Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0xA0 => reg32 ISFR { //! Interrupt Status Flag Register
0..31 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
});
ioregs!(PORTD @ 0x4004C000 = { //! Pin Control and Interrupts
0x00 => reg32 PCR%s { //! Pin Control Register n
0 => PSrw { //! Pull Select
0 => INTERNAL_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
1 => INTERNAL_PULLUP_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
}
1 => PErw { //! Pull Enable
0 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_NOT_ENABLED_ON_THE_CORRESPONDING_PIN, //= Internal pullup or pulldown resistor is not enabled on the corresponding pin.
1 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT, //= Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
}
2 => SRErw { //! Slew Rate Enable
0 => FAST_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
1 => SLOW_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
}
4 => PFErw { //! Passive Filter Enable
0 => PASSIVE_INPUT_FILTER_IS_DISABLED_ON_THE_CORRESPONDING_PIN, //= Passive input filter is disabled on the corresponding pin.
1 => PASSIVE_INPUT_FILTER_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT_REFER_TO_THE_DEVICE_DATA_SHEET_FOR_FILTER_CHARACTERISTICS, //= Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
}
6 => DSErw { //! Drive Strength Enable
0 => LOW_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 => HIGH_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
}
8..10 => MUXrw { //! Pin Mux Control
0 => E_000, //= Pin disabled (analog).
1 => E_001, //= Alternative 1 (GPIO).
2 => E_010, //= Alternative 2 (chip-specific).
3 => E_011, //= Alternative 3 (chip-specific).
4 => E_100, //= Alternative 4 (chip-specific).
5 => E_101, //= Alternative 5 (chip-specific).
6 => E_110, //= Alternative 6 (chip-specific).
7 => E_111, //= Alternative 7 (chip-specific).
}
16..19 => IRQCrw { //! Interrupt Configuration
0 => INTERRUPTDMA_REQUEST_DISABLED, //= Interrupt/DMA request disabled.
1 => DMA_REQUEST_ON_RISING_EDGE, //= DMA request on rising edge.
2 => DMA_REQUEST_ON_FALLING_EDGE, //= DMA request on falling edge.
3 => DMA_REQUEST_ON_EITHER_EDGE, //= DMA request on either edge.
8 => INTERRUPT_WHEN_LOGIC_ZERO, //= Interrupt when logic zero.
9 => INTERRUPT_ON_RISING_EDGE, //= Interrupt on rising edge.
10 => INTERRUPT_ON_FALLING_EDGE, //= Interrupt on falling edge.
11 => INTERRUPT_ON_EITHER_EDGE, //= Interrupt on either edge.
12 => INTERRUPT_WHEN_LOGIC_ONE, //= Interrupt when logic one.
}
24 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
0x80 => reg32 GPCLR { //! Global Pin Control Low Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0x84 => reg32 GPCHR { //! Global Pin Control High Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0xA0 => reg32 ISFR { //! Interrupt Status Flag Register
0..31 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
});
ioregs!(PORTE @ 0x4004D000 = { //! Pin Control and Interrupts
0x00 => reg32 PCR%s { //! Pin Control Register n
0 => PSrw { //! Pull Select
0 => INTERNAL_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
1 => INTERNAL_PULLUP_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_CORRESPONDING_PORT_PULL_ENABLE_FIELD_IS_SET, //= Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
}
1 => PErw { //! Pull Enable
0 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_NOT_ENABLED_ON_THE_CORRESPONDING_PIN, //= Internal pullup or pulldown resistor is not enabled on the corresponding pin.
1 => INTERNAL_PULLUP_OR_PULLDOWN_RESISTOR_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT, //= Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
}
2 => SRErw { //! Slew Rate Enable
0 => FAST_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
1 => SLOW_SLEW_RATE_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
}
4 => PFErw { //! Passive Filter Enable
0 => PASSIVE_INPUT_FILTER_IS_DISABLED_ON_THE_CORRESPONDING_PIN, //= Passive input filter is disabled on the corresponding pin.
1 => PASSIVE_INPUT_FILTER_IS_ENABLED_ON_THE_CORRESPONDING_PIN_IF_THE_PIN_IS_CONFIGURED_AS_A_DIGITAL_INPUT_REFER_TO_THE_DEVICE_DATA_SHEET_FOR_FILTER_CHARACTERISTICS, //= Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
}
6 => DSErw { //! Drive Strength Enable
0 => LOW_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 => HIGH_DRIVE_STRENGTH_IS_CONFIGURED_ON_THE_CORRESPONDING_PIN_IF_PIN_IS_CONFIGURED_AS_A_DIGITAL_OUTPUT, //= High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
}
8..10 => MUXrw { //! Pin Mux Control
0 => E_000, //= Pin disabled (analog).
1 => E_001, //= Alternative 1 (GPIO).
2 => E_010, //= Alternative 2 (chip-specific).
3 => E_011, //= Alternative 3 (chip-specific).
4 => E_100, //= Alternative 4 (chip-specific).
5 => E_101, //= Alternative 5 (chip-specific).
6 => E_110, //= Alternative 6 (chip-specific).
7 => E_111, //= Alternative 7 (chip-specific).
}
16..19 => IRQCrw { //! Interrupt Configuration
0 => INTERRUPTDMA_REQUEST_DISABLED, //= Interrupt/DMA request disabled.
1 => DMA_REQUEST_ON_RISING_EDGE, //= DMA request on rising edge.
2 => DMA_REQUEST_ON_FALLING_EDGE, //= DMA request on falling edge.
3 => DMA_REQUEST_ON_EITHER_EDGE, //= DMA request on either edge.
8 => INTERRUPT_WHEN_LOGIC_ZERO, //= Interrupt when logic zero.
9 => INTERRUPT_ON_RISING_EDGE, //= Interrupt on rising edge.
10 => INTERRUPT_ON_FALLING_EDGE, //= Interrupt on falling edge.
11 => INTERRUPT_ON_EITHER_EDGE, //= Interrupt on either edge.
12 => INTERRUPT_WHEN_LOGIC_ONE, //= Interrupt when logic one.
}
24 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
0x80 => reg32 GPCLR { //! Global Pin Control Low Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0x84 => reg32 GPCHR { //! Global Pin Control High Register
0..15 => GPWD wo, //= Global Pin Write Data
16..31 => GPWEwo { //! Global Pin Write Enable
0 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_NOT_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is not updated with the value in GPWD.
1 => CORRESPONDING_PIN_CONTROL_REGISTER_IS_UPDATED_WITH_THE_VALUE_IN_GPWD, //= Corresponding Pin Control Register is updated with the value in GPWD.
}
},
0xA0 => reg32 ISFR { //! Interrupt Status Flag Register
0..31 => ISFrw { //! Interrupt Status Flag
0 => CONFIGURED_INTERRUPT_IS_NOT_DETECTED, //= Configured interrupt is not detected.
1 => CONFIGURED_INTERRUPT_IS_DETECTED_IF_THE_PIN_IS_CONFIGURED_TO_GENERATE_A_DMA_REQUEST_THEN_THE_CORRESPONDING_FLAG_WILL_BE_CLEARED_AUTOMATICALLY_AT_THE_COMPLETION_OF_THE_REQUESTED_DMA_TRANSFER_OTHERWISE_THE_FLAG_REMAINS_SET_UNTIL_A_LOGIC_ONE_IS_WRITTEN_TO_THE_FLAG_IF_THE_PIN_IS_CONFIGURED_FOR_A_LEVEL_SENSITIVE_INTERRUPT_AND_THE_PIN_REMAINS_ASSERTED_THEN_THE_FLAG_IS_SET_AGAIN_IMMEDIATELY_AFTER_IT_IS_CLEARED, //= Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
}
},
});
ioregs!(MCG @ 0x40064000 = { //! Multipurpose Clock Generator module
0x00 => reg8 C1 { //! MCG Control 1 Register
0 => IREFSTENrw { //! Internal Reference Stop Enable
0 => INTERNAL_REFERENCE_CLOCK_IS_DISABLED_IN_STOP_MODE, //= Internal reference clock is disabled in Stop mode.
1 => INTERNAL_REFERENCE_CLOCK_IS_ENABLED_IN_STOP_MODE_IF_IRCLKEN_IS_SET_OR_IF_MCG_IS_IN_FEI_FBI_OR_BLPI_MODES_BEFORE_ENTERING_STOP_MODE, //= Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
}
1 => IRCLKENrw { //! Internal Reference Clock Enable
0 => MCGIRCLK_INACTIVE, //= MCGIRCLK inactive.
1 => MCGIRCLK_ACTIVE, //= MCGIRCLK active.
}
2 => IREFSrw { //! Internal Reference Select
0 => EXTERNAL_REFERENCE_CLOCK_IS_SELECTED, //= External reference clock is selected.
1 => THE_SLOW_INTERNAL_REFERENCE_CLOCK_IS_SELECTED, //= The slow internal reference clock is selected.
}
3..5 => FRDIVrw { //! FLL External Reference Divider
0 => E_000, //= If RANGE 0 = 0 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is 32.
1 => E_001, //= If RANGE 0 = 0 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is 64.
2 => E_010, //= If RANGE 0 = 0 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is 128.
3 => E_011, //= If RANGE 0 = 0 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is 256.
4 => E_100, //= If RANGE 0 = 0 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is 512.
5 => E_101, //= If RANGE 0 = 0 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is 1024.
6 => E_110, //= If RANGE 0 = 0 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is 1280 .
7 => E_111, //= If RANGE 0 = 0 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is 1536 .
}
6..7 => CLKSrw { //! Clock Source Select
0 => E_00, //= Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).
1 => ENCODING_1___INTERNAL_REFERENCE_CLOCK_IS_SELECTED, //= Encoding 1 - Internal reference clock is selected.
2 => ENCODING_2___EXTERNAL_REFERENCE_CLOCK_IS_SELECTED, //= Encoding 2 - External reference clock is selected.
3 => ENCODING_3___RESERVED, //= Encoding 3 - Reserved.
}
},
0x01 => reg8 C2 { //! MCG Control 2 Register
0 => IRCSrw { //! Internal Reference Clock Select
0 => SLOW_INTERNAL_REFERENCE_CLOCK_SELECTED, //= Slow internal reference clock selected.
1 => FAST_INTERNAL_REFERENCE_CLOCK_SELECTED, //= Fast internal reference clock selected.
}
1 => LPrw { //! Low Power Select
0 => FLL_OR_PLL_IS_NOT_DISABLED_IN_BYPASS_MODES, //= FLL or PLL is not disabled in bypass modes.
1 => E_1, //= FLL or PLL is disabled in bypass modes (lower power)
}
2 => EREFS0rw { //! External Reference Select
0 => EXTERNAL_REFERENCE_CLOCK_REQUESTED, //= External reference clock requested.
1 => OSCILLATOR_REQUESTED, //= Oscillator requested.
}
3 => HGO0rw { //! High Gain Oscillator Select
0 => CONFIGURE_CRYSTAL_OSCILLATOR_FOR_LOW_POWER_OPERATION, //= Configure crystal oscillator for low-power operation.
1 => CONFIGURE_CRYSTAL_OSCILLATOR_FOR_HIGH_GAIN_OPERATION, //= Configure crystal oscillator for high-gain operation.
}
4..5 => RANGE0rw { //! Frequency Range Select
0 => ENCODING_0___LOW_FREQUENCY_RANGE_SELECTED_FOR_THE_CRYSTAL_OSCILLATOR_, //= Encoding 0 - Low frequency range selected for the crystal oscillator .
1 => ENCODING_1___HIGH_FREQUENCY_RANGE_SELECTED_FOR_THE_CRYSTAL_OSCILLATOR_, //= Encoding 1 - High frequency range selected for the crystal oscillator .
}
7 => LOCRE0rw { //! Loss of Clock Reset Enable
0 => INTERRUPT_REQUEST_IS_GENERATED_ON_A_LOSS_OF_OSC0_EXTERNAL_REFERENCE_CLOCK, //= Interrupt request is generated on a loss of OSC0 external reference clock.
1 => GENERATE_A_RESET_REQUEST_ON_A_LOSS_OF_OSC0_EXTERNAL_REFERENCE_CLOCK, //= Generate a reset request on a loss of OSC0 external reference clock.
}
},
0x02 => reg8 C3 { //! MCG Control 3 Register
0..7 => SCTRIM rw, //= Slow Internal Reference Clock Trim Setting
},
0x03 => reg8 C4 { //! MCG Control 4 Register
0 => SCFTRIM rw, //= Slow Internal Reference Clock Fine Trim
1..4 => FCTRIM rw, //= Fast Internal Reference Clock Trim Setting
5..6 => DRST_DRSrw { //! DCO Range Select
0 => E_00, //= Encoding 0 - Low range (reset default).
1 => ENCODING_1___MID_RANGE, //= Encoding 1 - Mid range.
2 => ENCODING_2___MID_HIGH_RANGE, //= Encoding 2 - Mid-high range.
3 => ENCODING_3___HIGH_RANGE, //= Encoding 3 - High range.
}
7 => DMX32rw { //! DCO Maximum Frequency with 32.768 kHz Reference
0 => DCO_HAS_A_DEFAULT_RANGE_OF_25, //= DCO has a default range of 25%.
1 => DCO_IS_FINE_TUNED_FOR_MAXIMUM_FREQUENCY_WITH_32768_KHZ_REFERENCE, //= DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
}
},
0x04 => reg8 C5 { //! MCG Control 5 Register
0..4 => PRDIV0 rw, //= PLL External Reference Divider
5 => PLLSTEN0rw { //! PLL Stop Enable
0 => MCGPLLCLK_IS_DISABLED_IN_ANY_OF_THE_STOP_MODES, //= MCGPLLCLK is disabled in any of the Stop modes.
1 => MCGPLLCLK_IS_ENABLED_IF_SYSTEM_IS_IN_NORMAL_STOP_MODE, //= MCGPLLCLK is enabled if system is in Normal Stop mode.
}
6 => PLLCLKEN0rw { //! PLL Clock Enable
0 => MCGPLLCLK_IS_INACTIVE, //= MCGPLLCLK is inactive.
1 => MCGPLLCLK_IS_ACTIVE, //= MCGPLLCLK is active.
}
},
0x05 => reg8 C6 { //! MCG Control 6 Register
0..4 => VDIV0 rw, //= VCO 0 Divider
5 => CME0rw { //! Clock Monitor Enable
0 => EXTERNAL_CLOCK_MONITOR_IS_DISABLED_FOR_OSC0, //= External clock monitor is disabled for OSC0.
1 => EXTERNAL_CLOCK_MONITOR_IS_ENABLED_FOR_OSC0, //= External clock monitor is enabled for OSC0.
}
6 => PLLSrw { //! PLL Select
0 => FLL_IS_SELECTED, //= FLL is selected.
1 => E_1, //= PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit).
}
7 => LOLIE0rw { //! Loss of Lock Interrrupt Enable
0 => NO_INTERRUPT_REQUEST_IS_GENERATED_ON_LOSS_OF_LOCK, //= No interrupt request is generated on loss of lock.
1 => GENERATE_AN_INTERRUPT_REQUEST_ON_LOSS_OF_LOCK, //= Generate an interrupt request on loss of lock.
}
},
0x06 => reg8 S { //! MCG Status Register
0 => IRCSTro { //! Internal Reference Clock Status
0 => E_0, //= Source of internal reference clock is the slow clock (32 kHz IRC).
1 => E_1, //= Source of internal reference clock is the fast clock (4 MHz IRC).
}
1 => OSCINIT0 ro, //= OSC Initialization
2..3 => CLKSTro { //! Clock Mode Status
0 => E_00, //= Encoding 0 - Output of the FLL is selected (reset default).
1 => ENCODING_1___INTERNAL_REFERENCE_CLOCK_IS_SELECTED, //= Encoding 1 - Internal reference clock is selected.
2 => ENCODING_2___EXTERNAL_REFERENCE_CLOCK_IS_SELECTED, //= Encoding 2 - External reference clock is selected.
3 => ENCODING_3___OUTPUT_OF_THE_PLL_IS_SELECTED, //= Encoding 3 - Output of the PLL is selected.
}
4 => IREFSTro { //! Internal Reference Status
0 => SOURCE_OF_FLL_REFERENCE_CLOCK_IS_THE_EXTERNAL_REFERENCE_CLOCK, //= Source of FLL reference clock is the external reference clock.
1 => SOURCE_OF_FLL_REFERENCE_CLOCK_IS_THE_INTERNAL_REFERENCE_CLOCK, //= Source of FLL reference clock is the internal reference clock.
}
5 => PLLSTro { //! PLL Select Status
0 => SOURCE_OF_PLLS_CLOCK_IS_FLL_CLOCK, //= Source of PLLS clock is FLL clock.
1 => SOURCE_OF_PLLS_CLOCK_IS_PLL_OUTPUT_CLOCK, //= Source of PLLS clock is PLL output clock.
}
6 => LOCK0ro { //! Lock Status
0 => PLL_IS_CURRENTLY_UNLOCKED, //= PLL is currently unlocked.
1 => PLL_IS_CURRENTLY_LOCKED, //= PLL is currently locked.
}
7 => LOLS0rw { //! Loss of Lock Status
0 => PLL_HAS_NOT_LOST_LOCK_SINCE_LOLS_0_WAS_LAST_CLEARED, //= PLL has not lost lock since LOLS 0 was last cleared.
1 => PLL_HAS_LOST_LOCK_SINCE_LOLS_0_WAS_LAST_CLEARED, //= PLL has lost lock since LOLS 0 was last cleared.
}
},
0x08 => reg8 SC { //! MCG Status and Control Register
0 => LOCS0rw { //! OSC0 Loss of Clock Status
0 => LOSS_OF_OSC0_HAS_NOT_OCCURRED, //= Loss of OSC0 has not occurred.
1 => LOSS_OF_OSC0_HAS_OCCURRED, //= Loss of OSC0 has occurred.
}
1..3 => FCRDIVrw { //! Fast Clock Internal Reference Divider
0 => DIVIDE_FACTOR_IS_1, //= Divide Factor is 1
1 => DIVIDE_FACTOR_IS_2, //= Divide Factor is 2.
2 => DIVIDE_FACTOR_IS_4, //= Divide Factor is 4.
3 => DIVIDE_FACTOR_IS_8, //= Divide Factor is 8.
4 => DIVIDE_FACTOR_IS_16, //= Divide Factor is 16
5 => DIVIDE_FACTOR_IS_32, //= Divide Factor is 32
6 => DIVIDE_FACTOR_IS_64, //= Divide Factor is 64
7 => DIVIDE_FACTOR_IS_128, //= Divide Factor is 128.
}
4 => FLTPRSRVrw { //! FLL Filter Preserve Enable
0 => FLL_FILTER_AND_FLL_FREQUENCY_WILL_RESET_ON_CHANGES_TO_CURRECT_CLOCK_MODE, //= FLL filter and FLL frequency will reset on changes to currect clock mode.
1 => FLL_FILTER_AND_FLL_FREQUENCY_RETAIN_THEIR_PREVIOUS_VALUES_DURING_NEW_CLOCK_MODE_CHANGE, //= Fll filter and FLL frequency retain their previous values during new clock mode change.
}
5 => ATMFrw { //! Automatic Trim Machine Fail Flag
0 => AUTOMATIC_TRIM_MACHINE_COMPLETED_NORMALLY, //= Automatic Trim Machine completed normally.
1 => AUTOMATIC_TRIM_MACHINE_FAILED, //= Automatic Trim Machine failed.
}
6 => ATMSrw { //! Automatic Trim Machine Select
0 => 32_KHZ_INTERNAL_REFERENCE_CLOCK_SELECTED, //= 32 kHz Internal Reference Clock selected.
1 => 4_MHZ_INTERNAL_REFERENCE_CLOCK_SELECTED, //= 4 MHz Internal Reference Clock selected.
}
7 => ATMErw { //! Automatic Trim Machine Enable
0 => AUTO_TRIM_MACHINE_DISABLED, //= Auto Trim Machine disabled.
1 => AUTO_TRIM_MACHINE_ENABLED, //= Auto Trim Machine enabled.
}
},
0x0A => reg8 ATCVH { //! MCG Auto Trim Compare Value High Register
0..7 => ATCVH rw, //= ATM Compare Value High
},
0x0B => reg8 ATCVL { //! MCG Auto Trim Compare Value Low Register
0..7 => ATCVL rw, //= ATM Compare Value Low
},
0x0C => reg8 C7 { //! MCG Control 7 Register
},
0x0D => reg8 C8 { //! MCG Control 8 Register
6 => LOLRErw { //! PLL Loss of Lock Reset Enable
0 => INTERRUPT_REQUEST_IS_GENERATED_ON_A_PLL_LOSS_OF_LOCK_INDICATION_THE_PLL_LOSS_OF_LOCK_INTERRUPT_ENABLE_BIT_MUST_ALSO_BE_SET_TO_GENERATE_THE_INTERRUPT_REQUEST, //= Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.
1 => GENERATE_A_RESET_REQUEST_ON_A_PLL_LOSS_OF_LOCK_INDICATION, //= Generate a reset request on a PLL loss of lock indication.
}
},
0x0E => reg8 C9 { //! MCG Control 9 Register
},
0x0F => reg8 C10 { //! MCG Control 10 Register
},
});
ioregs!(OSC0 @ 0x40065000 = { //! Oscillator
0x00 => reg8 CR { //! OSC Control Register
0 => SC16Prw { //! Oscillator 16 pF Capacitor Load Configure
0 => DISABLE_THE_SELECTION, //= Disable the selection.
1 => ADD_16_PF_CAPACITOR_TO_THE_OSCILLATOR_LOAD, //= Add 16 pF capacitor to the oscillator load.
}
1 => SC8Prw { //! Oscillator 8 pF Capacitor Load Configure
0 => DISABLE_THE_SELECTION, //= Disable the selection.
1 => ADD_8_PF_CAPACITOR_TO_THE_OSCILLATOR_LOAD, //= Add 8 pF capacitor to the oscillator load.
}
2 => SC4Prw { //! Oscillator 4 pF Capacitor Load Configure
0 => DISABLE_THE_SELECTION, //= Disable the selection.
1 => ADD_4_PF_CAPACITOR_TO_THE_OSCILLATOR_LOAD, //= Add 4 pF capacitor to the oscillator load.
}
3 => SC2Prw { //! Oscillator 2 pF Capacitor Load Configure
0 => DISABLE_THE_SELECTION, //= Disable the selection.
1 => ADD_2_PF_CAPACITOR_TO_THE_OSCILLATOR_LOAD, //= Add 2 pF capacitor to the oscillator load.
}
5 => EREFSTENrw { //! External Reference Stop Enable
0 => EXTERNAL_REFERENCE_CLOCK_IS_DISABLED_IN_STOP_MODE, //= External reference clock is disabled in Stop mode.
1 => EXTERNAL_REFERENCE_CLOCK_STAYS_ENABLED_IN_STOP_MODE_IF_ERCLKEN_IS_SET_BEFORE_ENTERING_STOP_MODE, //= External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
}
7 => ERCLKENrw { //! External Reference Enable
0 => EXTERNAL_REFERENCE_CLOCK_IS_INACTIVE, //= External reference clock is inactive.
1 => EXTERNAL_REFERENCE_CLOCK_IS_ENABLED, //= External reference clock is enabled.
}
},
});
ioregs!(I2C0 @ 0x40066000 = { //! Inter-Integrated Circuit
0x00 => reg8 A1 { //! I2C Address Register 1
1..7 => AD rw, //= Address
},
0x01 => reg8 F { //! I2C Frequency Divider register
0..5 => ICR rw, //= ClockRate
6..7 => MULTrw { //! no description available
0 => E_00, //= mul = 1
1 => E_01, //= mul = 2
2 => E_10, //= mul = 4
}
},
0x02 => reg8 C1 { //! I2C Control Register 1
0 => DMAENrw { //! DMA Enable
0 => ALL_DMA_SIGNALLING_DISABLED, //= All DMA signalling disabled.
1 => E_1, //= DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
}
1 => WUENrw { //! Wakeup Enable
0 => NORMAL_OPERATION_NO_INTERRUPT_GENERATED_WHEN_ADDRESS_MATCHING_IN_LOW_POWER_MODE, //= Normal operation. No interrupt generated when address matching in low power mode.
1 => ENABLES_THE_WAKEUP_FUNCTION_IN_LOW_POWER_MODE, //= Enables the wakeup function in low power mode.
}
2 => RSTA wo, //= Repeat START
3 => TXAKrw { //! Transmit Acknowledge Enable
0 => E_0, //= An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
1 => E_1, //= No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
}
4 => TXrw { //! Transmit Mode Select
0 => RECEIVE, //= Receive
1 => TRANSMIT, //= Transmit
}
5 => MSTrw { //! Master Mode Select
0 => SLAVE_MODE, //= Slave mode
1 => MASTER_MODE, //= Master mode
}
6 => IICIErw { //! I2C Interrupt Enable
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
7 => IICENrw { //! I2C Enable
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
},
0x03 => reg8 S { //! I2C Status register
0 => RXAKro { //! Receive Acknowledge
0 => ACKNOWLEDGE_SIGNAL_WAS_RECEIVED_AFTER_THE_COMPLETION_OF_ONE_BYTE_OF_DATA_TRANSMISSION_ON_THE_BUS, //= Acknowledge signal was received after the completion of one byte of data transmission on the bus
1 => NO_ACKNOWLEDGE_SIGNAL_DETECTED, //= No acknowledge signal detected
}
1 => IICIFrw { //! Interrupt Flag
0 => NO_INTERRUPT_PENDING, //= No interrupt pending
1 => INTERRUPT_PENDING, //= Interrupt pending
}
2 => SRWro { //! Slave Read/Write
0 => SLAVE_RECEIVE_MASTER_WRITING_TO_SLAVE, //= Slave receive, master writing to slave
1 => SLAVE_TRANSMIT_MASTER_READING_FROM_SLAVE, //= Slave transmit, master reading from slave
}
3 => RAMrw { //! Range Address Match
0 => NOT_ADDRESSED, //= Not addressed
1 => ADDRESSED_AS_A_SLAVE, //= Addressed as a slave
}
4 => ARBLrw { //! Arbitration Lost
0 => STANDARD_BUS_OPERATION, //= Standard bus operation.
1 => LOSS_OF_ARBITRATION, //= Loss of arbitration.
}
5 => BUSYro { //! Bus Busy
0 => BUS_IS_IDLE, //= Bus is idle
1 => BUS_IS_BUSY, //= Bus is busy
}
6 => IAASrw { //! Addressed As A Slave
0 => NOT_ADDRESSED, //= Not addressed
1 => ADDRESSED_AS_A_SLAVE, //= Addressed as a slave
}
7 => TCFro { //! Transfer Complete Flag
0 => TRANSFER_IN_PROGRESS, //= Transfer in progress
1 => TRANSFER_COMPLETE, //= Transfer complete
}
},
0x04 => reg8 D { //! I2C Data I/O register
0..7 => DATA rw, //= Data
},
0x05 => reg8 C2 { //! I2C Control Register 2
0..2 => AD rw, //= Slave Address
3 => RMENrw { //! Range Address Matching Enable
0 => RANGE_MODE_DISABLED_NO_ADDRESS_MATCH_OCCURS_FOR_AN_ADDRESS_WITHIN_THE_RANGE_OF_VALUES_OF_THE_A1_AND_RA_REGISTERS, //= Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.
1 => RANGE_MODE_ENABLED_ADDRESS_MATCHING_OCCURS_WHEN_A_SLAVE_RECEIVES_AN_ADDRESS_WITHIN_THE_RANGE_OF_VALUES_OF_THE_A1_AND_RA_REGISTERS, //= Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
}
4 => SBRCrw { //! Slave Baud Rate Control
0 => THE_SLAVE_BAUD_RATE_FOLLOWS_THE_MASTER_BAUD_RATE_AND_CLOCK_STRETCHING_MAY_OCCUR, //= The slave baud rate follows the master baud rate and clock stretching may occur
1 => SLAVE_BAUD_RATE_IS_INDEPENDENT_OF_THE_MASTER_BAUD_RATE, //= Slave baud rate is independent of the master baud rate
}
5 => HDRSrw { //! High Drive Select
0 => NORMAL_DRIVE_MODE, //= Normal drive mode
1 => HIGH_DRIVE_MODE, //= High drive mode
}
6 => ADEXTrw { //! Address Extension
0 => 7_BIT_ADDRESS_SCHEME, //= 7-bit address scheme
1 => 10_BIT_ADDRESS_SCHEME, //= 10-bit address scheme
}
7 => GCAENrw { //! General Call Address Enable
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
},
0x06 => reg8 FLT { //! I2C Programmable Input Glitch Filter register
0..4 => FLTrw { //! I2C Programmable Filter Factor
0 => NO_FILTERBYPASS, //= No filter/bypass
}
5 => STOPIErw { //! I2C Bus Stop Interrupt Enable
0 => STOP_DETECTION_INTERRUPT_IS_DISABLED, //= Stop detection interrupt is disabled
1 => STOP_DETECTION_INTERRUPT_IS_ENABLED, //= Stop detection interrupt is enabled
}
6 => STOPFrw { //! I2C Bus Stop Detect Flag
0 => NO_STOP_HAPPENS_ON_I2C_BUS, //= No stop happens on I2C bus
1 => STOP_DETECTED_ON_I2C_BUS, //= Stop detected on I2C bus
}
7 => SHENrw { //! Stop Hold Enable
0 => STOP_HOLDOFF_IS_DISABLED_THE_MCU'S_ENTRY_TO_STOP_MODE_IS_NOT_GATED, //= Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
1 => STOP_HOLDOFF_IS_ENABLED, //= Stop holdoff is enabled.
}
},
0x07 => reg8 RA { //! I2C Range Address register
1..7 => RAD rw, //= Range Slave Address
},
0x08 => reg8 SMB { //! I2C SMBus Control and Status register
0 => SHTF2IErw { //! SHTF2 Interrupt Enable
0 => SHTF2_INTERRUPT_IS_DISABLED, //= SHTF2 interrupt is disabled
1 => SHTF2_INTERRUPT_IS_ENABLED, //= SHTF2 interrupt is enabled
}
1 => SHTF2rw { //! SCL High Timeout Flag 2
0 => NO_SCL_HIGH_AND_SDA_LOW_TIMEOUT_OCCURS, //= No SCL high and SDA low timeout occurs
1 => SCL_HIGH_AND_SDA_LOW_TIMEOUT_OCCURS, //= SCL high and SDA low timeout occurs
}
2 => SHTF1ro { //! SCL High Timeout Flag 1
0 => NO_SCL_HIGH_AND_SDA_HIGH_TIMEOUT_OCCURS, //= No SCL high and SDA high timeout occurs
1 => SCL_HIGH_AND_SDA_HIGH_TIMEOUT_OCCURS, //= SCL high and SDA high timeout occurs
}
3 => SLTFrw { //! SCL Low Timeout Flag
0 => NO_LOW_TIMEOUT_OCCURS, //= No low timeout occurs
1 => LOW_TIMEOUT_OCCURS, //= Low timeout occurs
}
4 => TCKSELrw { //! Timeout Counter Clock Select
0 => TIMEOUT_COUNTER_COUNTS_AT_THE_FREQUENCY_OF_THE_BUS_CLOCK__64, //= Timeout counter counts at the frequency of the bus clock / 64
1 => TIMEOUT_COUNTER_COUNTS_AT_THE_FREQUENCY_OF_THE_BUS_CLOCK, //= Timeout counter counts at the frequency of the bus clock
}
5 => SIICAENrw { //! Second I2C Address Enable
0 => I2C_ADDRESS_REGISTER_2_MATCHING_IS_DISABLED, //= I2C address register 2 matching is disabled
1 => I2C_ADDRESS_REGISTER_2_MATCHING_IS_ENABLED, //= I2C address register 2 matching is enabled
}
6 => ALERTENrw { //! SMBus Alert Response Address Enable
0 => SMBUS_ALERT_RESPONSE_ADDRESS_MATCHING_IS_DISABLED, //= SMBus alert response address matching is disabled
1 => SMBUS_ALERT_RESPONSE_ADDRESS_MATCHING_IS_ENABLED, //= SMBus alert response address matching is enabled
}
7 => FACKrw { //! Fast NACK/ACK Enable
0 => AN_ACK_OR_NACK_IS_SENT_ON_THE_FOLLOWING_RECEIVING_DATA_BYTE, //= An ACK or NACK is sent on the following receiving data byte
1 => WRITING_0_TO_TXAK_AFTER_RECEIVING_A_DATA_BYTE_GENERATES_AN_ACK_WRITING_1_TO_TXAK_AFTER_RECEIVING_A_DATA_BYTE_GENERATES_A_NACK, //= Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
}
},
0x09 => reg8 A2 { //! I2C Address Register 2
1..7 => SAD rw, //= SMBus Address
},
0x0A => reg8 SLTH { //! I2C SCL Low Timeout Register High
0..7 => SSLT rw, //= no description available
},
0x0B => reg8 SLTL { //! I2C SCL Low Timeout Register Low
0..7 => SSLT rw, //= no description available
},
});
ioregs!(I2C1 @ 0x40067000 = { //! Inter-Integrated Circuit
0x00 => reg8 A1 { //! I2C Address Register 1
1..7 => AD rw, //= Address
},
0x01 => reg8 F { //! I2C Frequency Divider register
0..5 => ICR rw, //= ClockRate
6..7 => MULTrw { //! no description available
0 => E_00, //= mul = 1
1 => E_01, //= mul = 2
2 => E_10, //= mul = 4
}
},
0x02 => reg8 C1 { //! I2C Control Register 1
0 => DMAENrw { //! DMA Enable
0 => ALL_DMA_SIGNALLING_DISABLED, //= All DMA signalling disabled.
1 => E_1, //= DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
}
1 => WUENrw { //! Wakeup Enable
0 => NORMAL_OPERATION_NO_INTERRUPT_GENERATED_WHEN_ADDRESS_MATCHING_IN_LOW_POWER_MODE, //= Normal operation. No interrupt generated when address matching in low power mode.
1 => ENABLES_THE_WAKEUP_FUNCTION_IN_LOW_POWER_MODE, //= Enables the wakeup function in low power mode.
}
2 => RSTA wo, //= Repeat START
3 => TXAKrw { //! Transmit Acknowledge Enable
0 => E_0, //= An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
1 => E_1, //= No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
}
4 => TXrw { //! Transmit Mode Select
0 => RECEIVE, //= Receive
1 => TRANSMIT, //= Transmit
}
5 => MSTrw { //! Master Mode Select
0 => SLAVE_MODE, //= Slave mode
1 => MASTER_MODE, //= Master mode
}
6 => IICIErw { //! I2C Interrupt Enable
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
7 => IICENrw { //! I2C Enable
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
},
0x03 => reg8 S { //! I2C Status register
0 => RXAKro { //! Receive Acknowledge
0 => ACKNOWLEDGE_SIGNAL_WAS_RECEIVED_AFTER_THE_COMPLETION_OF_ONE_BYTE_OF_DATA_TRANSMISSION_ON_THE_BUS, //= Acknowledge signal was received after the completion of one byte of data transmission on the bus
1 => NO_ACKNOWLEDGE_SIGNAL_DETECTED, //= No acknowledge signal detected
}
1 => IICIFrw { //! Interrupt Flag
0 => NO_INTERRUPT_PENDING, //= No interrupt pending
1 => INTERRUPT_PENDING, //= Interrupt pending
}
2 => SRWro { //! Slave Read/Write
0 => SLAVE_RECEIVE_MASTER_WRITING_TO_SLAVE, //= Slave receive, master writing to slave
1 => SLAVE_TRANSMIT_MASTER_READING_FROM_SLAVE, //= Slave transmit, master reading from slave
}
3 => RAMrw { //! Range Address Match
0 => NOT_ADDRESSED, //= Not addressed
1 => ADDRESSED_AS_A_SLAVE, //= Addressed as a slave
}
4 => ARBLrw { //! Arbitration Lost
0 => STANDARD_BUS_OPERATION, //= Standard bus operation.
1 => LOSS_OF_ARBITRATION, //= Loss of arbitration.
}
5 => BUSYro { //! Bus Busy
0 => BUS_IS_IDLE, //= Bus is idle
1 => BUS_IS_BUSY, //= Bus is busy
}
6 => IAASrw { //! Addressed As A Slave
0 => NOT_ADDRESSED, //= Not addressed
1 => ADDRESSED_AS_A_SLAVE, //= Addressed as a slave
}
7 => TCFro { //! Transfer Complete Flag
0 => TRANSFER_IN_PROGRESS, //= Transfer in progress
1 => TRANSFER_COMPLETE, //= Transfer complete
}
},
0x04 => reg8 D { //! I2C Data I/O register
0..7 => DATA rw, //= Data
},
0x05 => reg8 C2 { //! I2C Control Register 2
0..2 => AD rw, //= Slave Address
3 => RMENrw { //! Range Address Matching Enable
0 => RANGE_MODE_DISABLED_NO_ADDRESS_MATCH_OCCURS_FOR_AN_ADDRESS_WITHIN_THE_RANGE_OF_VALUES_OF_THE_A1_AND_RA_REGISTERS, //= Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.
1 => RANGE_MODE_ENABLED_ADDRESS_MATCHING_OCCURS_WHEN_A_SLAVE_RECEIVES_AN_ADDRESS_WITHIN_THE_RANGE_OF_VALUES_OF_THE_A1_AND_RA_REGISTERS, //= Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
}
4 => SBRCrw { //! Slave Baud Rate Control
0 => THE_SLAVE_BAUD_RATE_FOLLOWS_THE_MASTER_BAUD_RATE_AND_CLOCK_STRETCHING_MAY_OCCUR, //= The slave baud rate follows the master baud rate and clock stretching may occur
1 => SLAVE_BAUD_RATE_IS_INDEPENDENT_OF_THE_MASTER_BAUD_RATE, //= Slave baud rate is independent of the master baud rate
}
5 => HDRSrw { //! High Drive Select
0 => NORMAL_DRIVE_MODE, //= Normal drive mode
1 => HIGH_DRIVE_MODE, //= High drive mode
}
6 => ADEXTrw { //! Address Extension
0 => 7_BIT_ADDRESS_SCHEME, //= 7-bit address scheme
1 => 10_BIT_ADDRESS_SCHEME, //= 10-bit address scheme
}
7 => GCAENrw { //! General Call Address Enable
0 => DISABLED, //= Disabled
1 => ENABLED, //= Enabled
}
},
0x06 => reg8 FLT { //! I2C Programmable Input Glitch Filter register
0..4 => FLTrw { //! I2C Programmable Filter Factor
0 => NO_FILTERBYPASS, //= No filter/bypass
}
5 => STOPIErw { //! I2C Bus Stop Interrupt Enable
0 => STOP_DETECTION_INTERRUPT_IS_DISABLED, //= Stop detection interrupt is disabled
1 => STOP_DETECTION_INTERRUPT_IS_ENABLED, //= Stop detection interrupt is enabled
}
6 => STOPFrw { //! I2C Bus Stop Detect Flag
0 => NO_STOP_HAPPENS_ON_I2C_BUS, //= No stop happens on I2C bus
1 => STOP_DETECTED_ON_I2C_BUS, //= Stop detected on I2C bus
}
7 => SHENrw { //! Stop Hold Enable
0 => STOP_HOLDOFF_IS_DISABLED_THE_MCU'S_ENTRY_TO_STOP_MODE_IS_NOT_GATED, //= Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
1 => STOP_HOLDOFF_IS_ENABLED, //= Stop holdoff is enabled.
}
},
0x07 => reg8 RA { //! I2C Range Address register
1..7 => RAD rw, //= Range Slave Address
},
0x08 => reg8 SMB { //! I2C SMBus Control and Status register
0 => SHTF2IErw { //! SHTF2 Interrupt Enable
0 => SHTF2_INTERRUPT_IS_DISABLED, //= SHTF2 interrupt is disabled
1 => SHTF2_INTERRUPT_IS_ENABLED, //= SHTF2 interrupt is enabled
}
1 => SHTF2rw { //! SCL High Timeout Flag 2
0 => NO_SCL_HIGH_AND_SDA_LOW_TIMEOUT_OCCURS, //= No SCL high and SDA low timeout occurs
1 => SCL_HIGH_AND_SDA_LOW_TIMEOUT_OCCURS, //= SCL high and SDA low timeout occurs
}
2 => SHTF1ro { //! SCL High Timeout Flag 1
0 => NO_SCL_HIGH_AND_SDA_HIGH_TIMEOUT_OCCURS, //= No SCL high and SDA high timeout occurs
1 => SCL_HIGH_AND_SDA_HIGH_TIMEOUT_OCCURS, //= SCL high and SDA high timeout occurs
}
3 => SLTFrw { //! SCL Low Timeout Flag
0 => NO_LOW_TIMEOUT_OCCURS, //= No low timeout occurs
1 => LOW_TIMEOUT_OCCURS, //= Low timeout occurs
}
4 => TCKSELrw { //! Timeout Counter Clock Select
0 => TIMEOUT_COUNTER_COUNTS_AT_THE_FREQUENCY_OF_THE_BUS_CLOCK__64, //= Timeout counter counts at the frequency of the bus clock / 64
1 => TIMEOUT_COUNTER_COUNTS_AT_THE_FREQUENCY_OF_THE_BUS_CLOCK, //= Timeout counter counts at the frequency of the bus clock
}
5 => SIICAENrw { //! Second I2C Address Enable
0 => I2C_ADDRESS_REGISTER_2_MATCHING_IS_DISABLED, //= I2C address register 2 matching is disabled
1 => I2C_ADDRESS_REGISTER_2_MATCHING_IS_ENABLED, //= I2C address register 2 matching is enabled
}
6 => ALERTENrw { //! SMBus Alert Response Address Enable
0 => SMBUS_ALERT_RESPONSE_ADDRESS_MATCHING_IS_DISABLED, //= SMBus alert response address matching is disabled
1 => SMBUS_ALERT_RESPONSE_ADDRESS_MATCHING_IS_ENABLED, //= SMBus alert response address matching is enabled
}
7 => FACKrw { //! Fast NACK/ACK Enable
0 => AN_ACK_OR_NACK_IS_SENT_ON_THE_FOLLOWING_RECEIVING_DATA_BYTE, //= An ACK or NACK is sent on the following receiving data byte
1 => WRITING_0_TO_TXAK_AFTER_RECEIVING_A_DATA_BYTE_GENERATES_AN_ACK_WRITING_1_TO_TXAK_AFTER_RECEIVING_A_DATA_BYTE_GENERATES_A_NACK, //= Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
}
},
0x09 => reg8 A2 { //! I2C Address Register 2
1..7 => SAD rw, //= SMBus Address
},
0x0A => reg8 SLTH { //! I2C SCL Low Timeout Register High
0..7 => SSLT rw, //= no description available
},
0x0B => reg8 SLTL { //! I2C SCL Low Timeout Register Low
0..7 => SSLT rw, //= no description available
},
});
ioregs!(UART0 @ 0x4006A000 = { //! Universal Asynchronous Receiver/Transmitter
0x00 => reg8 BDH { //! UART Baud Rate Register High
0..4 => SBR rw, //= Baud Rate Modulo Divisor.
5 => SBNSrw { //! Stop Bit Number Select
0 => ONE_STOP_BIT, //= One stop bit.
1 => TWO_STOP_BIT, //= Two stop bit.
}
6 => RXEDGIErw { //! RX Input Active Edge Interrupt Enable (for RXEDGIF)
0 => E_0, //= Hardware interrupts from UART _S2[RXEDGIF] disabled (use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_UART__S2[RXEDGIF]_FLAG_IS_1, //= Hardware interrupt requested when UART _S2[RXEDGIF] flag is 1.
}
7 => LBKDIErw { //! LIN Break Detect Interrupt Enable (for LBKDIF)
0 => E_0, //= Hardware interrupts from UART _S2[LBKDIF] disabled (use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_UART__S2[LBKDIF]_FLAG_IS_1, //= Hardware interrupt requested when UART _S2[LBKDIF] flag is 1.
}
},
0x01 => reg8 BDL { //! UART Baud Rate Register Low
0..7 => SBR rw, //= Baud Rate Modulo Divisor
},
0x02 => reg8 C1 { //! UART Control Register 1
0 => PTrw { //! Parity Type
0 => EVEN_PARITY, //= Even parity.
1 => ODD_PARITY, //= Odd parity.
}
1 => PErw { //! Parity Enable
0 => NO_HARDWARE_PARITY_GENERATION_OR_CHECKING, //= No hardware parity generation or checking.
1 => PARITY_ENABLED, //= Parity enabled.
}
2 => ILTrw { //! Idle Line Type Select
0 => IDLE_CHARACTER_BIT_COUNT_STARTS_AFTER_START_BIT, //= Idle character bit count starts after start bit.
1 => IDLE_CHARACTER_BIT_COUNT_STARTS_AFTER_STOP_BIT, //= Idle character bit count starts after stop bit.
}
3 => WAKErw { //! Receiver Wakeup Method Select
0 => IDLE_LINE_WAKEUP, //= Idle-line wakeup.
1 => ADDRESS_MARK_WAKEUP, //= Address-mark wakeup.
}
4 => Mrw { //! 9-Bit or 8-Bit Mode Select
0 => RECEIVER_AND_TRANSMITTER_USE_8_BIT_DATA_CHARACTERS, //= Receiver and transmitter use 8-bit data characters.
1 => RECEIVER_AND_TRANSMITTER_USE_9_BIT_DATA_CHARACTERS, //= Receiver and transmitter use 9-bit data characters.
}
5 => RSRCrw { //! Receiver Source Select
0 => PROVIDED_LOOPS_IS_SET_RSRC_IS_CLEARED_SELECTS_INTERNAL_LOOP_BACK_MODE_AND_THE_UART_DOES_NOT_USE_THE_UART__RX_PINS, //= Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the UART _RX pins.
1 => SINGLE_WIRE_UART_MODE_WHERE_THE_UART__TX_PIN_IS_CONNECTED_TO_THE_TRANSMITTER_OUTPUT_AND_RECEIVER_INPUT, //= Single-wire UART mode where the UART _TX pin is connected to the transmitter output and receiver input.
}
6 => DOZEENrw { //! Doze Enable
0 => UART_IS_ENABLED_IN_WAIT_MODE, //= UART is enabled in Wait mode.
1 => UART_IS_DISABLED_IN_WAIT_MODE, //= UART is disabled in Wait mode.
}
7 => LOOPSrw { //! Loop Mode Select
0 => NORMAL_OPERATION___UART__RX_AND_UART__TX_USE_SEPARATE_PINS, //= Normal operation - UART _RX and UART _TX use separate pins.
1 => E_1, //= Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) UART _RX pin is not used by UART .
}
},
0x03 => reg8 C2 { //! UART Control Register 2
0 => SBKrw { //! Send Break
0 => NORMAL_TRANSMITTER_OPERATION, //= Normal transmitter operation.
1 => E_1, //= Queue break character(s) to be sent.
}
1 => RWUrw { //! Receiver Wakeup Control
0 => NORMAL_UART_RECEIVER_OPERATION, //= Normal UART receiver operation.
1 => UART_RECEIVER_IN_STANDBY_WAITING_FOR_WAKEUP_CONDITION, //= UART receiver in standby waiting for wakeup condition.
}
2 => RErw { //! Receiver Enable
0 => RECEIVER_DISABLED, //= Receiver disabled.
1 => RECEIVER_ENABLED, //= Receiver enabled.
}
3 => TErw { //! Transmitter Enable
0 => TRANSMITTER_DISABLED, //= Transmitter disabled.
1 => TRANSMITTER_ENABLED, //= Transmitter enabled.
}
4 => ILIErw { //! Idle Line Interrupt Enable for IDLE
0 => E_0, //= Hardware interrupts from IDLE disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_IDLE_FLAG_IS_1, //= Hardware interrupt requested when IDLE flag is 1.
}
5 => RIErw { //! Receiver Interrupt Enable for RDRF
0 => E_0, //= Hardware interrupts from RDRF disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_RDRF_FLAG_IS_1, //= Hardware interrupt requested when RDRF flag is 1.
}
6 => TCIErw { //! Transmission Complete Interrupt Enable for TC
0 => E_0, //= Hardware interrupts from TC disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_TC_FLAG_IS_1, //= Hardware interrupt requested when TC flag is 1.
}
7 => TIErw { //! Transmit Interrupt Enable for TDRE
0 => E_0, //= Hardware interrupts from TDRE disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_TDRE_FLAG_IS_1, //= Hardware interrupt requested when TDRE flag is 1.
}
},
0x04 => reg8 S1 { //! UART Status Register 1
0 => PFrw { //! Parity Error Flag
0 => NO_PARITY_ERROR, //= No parity error.
1 => PARITY_ERROR, //= Parity error.
}
1 => FErw { //! Framing Error Flag
0 => NO_FRAMING_ERROR_DETECTED_THIS_DOES_NOT_GUARANTEE_THE_FRAMING_IS_CORRECT, //= No framing error detected. This does not guarantee the framing is correct.
1 => FRAMING_ERROR, //= Framing error.
}
2 => NFrw { //! Noise Flag
0 => NO_NOISE_DETECTED, //= No noise detected.
1 => NOISE_DETECTED_IN_THE_RECEIVED_CHARACTER_IN_UART__D, //= Noise detected in the received character in UART _D.
}
3 => ORrw { //! Receiver Overrun Flag
0 => NO_OVERRUN, //= No overrun.
1 => E_1, //= Receive overrun (new UART data lost).
}
4 => IDLErw { //! Idle Line Flag
0 => NO_IDLE_LINE_DETECTED, //= No idle line detected.
1 => IDLE_LINE_WAS_DETECTED, //= Idle line was detected.
}
5 => RDRFro { //! Receive Data Register Full Flag
0 => RECEIVE_DATA_BUFFER_EMPTY, //= Receive data buffer empty.
1 => RECEIVE_DATA_BUFFER_FULL, //= Receive data buffer full.
}
6 => TCro { //! Transmission Complete Flag
0 => E_0, //= Transmitter active (sending data, a preamble, or a break).
1 => E_1, //= Transmitter idle (transmission activity complete).
}
7 => TDREro { //! Transmit Data Register Empty Flag
0 => TRANSMIT_DATA_BUFFER_FULL, //= Transmit data buffer full.
1 => TRANSMIT_DATA_BUFFER_EMPTY, //= Transmit data buffer empty.
}
},
0x05 => reg8 S2 { //! UART Status Register 2
0 => RAFro { //! Receiver Active Flag
0 => UART_RECEIVER_IDLE_WAITING_FOR_A_START_BIT, //= UART receiver idle waiting for a start bit.
1 => E_1, //= UART receiver active ( UART _RXD input not idle).
}
1 => LBKDErw { //! LIN Break Detection Enable
0 => E_0, //= Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
1 => E_1, //= Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
}
2 => BRK13rw { //! Break Character Generation Length
0 => E_0, //= Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
1 => E_1, //= Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
}
3 => RWUIDrw { //! Receive Wake Up Idle Detect
0 => E_0, //= During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
1 => E_1, //= During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
}
4 => RXINVrw { //! Receive Data Inversion
0 => RECEIVE_DATA_NOT_INVERTED, //= Receive data not inverted.
1 => RECEIVE_DATA_INVERTED, //= Receive data inverted.
}
5 => MSBFrw { //! MSB First
0 => E_0, //= LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
1 => E_1, //= MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].
}
6 => RXEDGIFrw { //! UART _RX Pin Active Edge Interrupt Flag
0 => NO_ACTIVE_EDGE_ON_THE_RECEIVE_PIN_HAS_OCCURRED, //= No active edge on the receive pin has occurred.
1 => AN_ACTIVE_EDGE_ON_THE_RECEIVE_PIN_HAS_OCCURRED, //= An active edge on the receive pin has occurred.
}
7 => LBKDIFrw { //! LIN Break Detect Interrupt Flag
0 => NO_LIN_BREAK_CHARACTER_HAS_BEEN_DETECTED, //= No LIN break character has been detected.
1 => LIN_BREAK_CHARACTER_HAS_BEEN_DETECTED, //= LIN break character has been detected.
}
},
0x06 => reg8 C3 { //! UART Control Register 3
0 => PEIErw { //! Parity Error Interrupt Enable
0 => E_0, //= PF interrupts disabled; use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_PF_IS_SET, //= Hardware interrupt requested when PF is set.
}
1 => FEIErw { //! Framing Error Interrupt Enable
0 => E_0, //= FE interrupts disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_FE_IS_SET, //= Hardware interrupt requested when FE is set.
}
2 => NEIErw { //! Noise Error Interrupt Enable
0 => E_0, //= NF interrupts disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_NF_IS_SET, //= Hardware interrupt requested when NF is set.
}
3 => ORIErw { //! Overrun Interrupt Enable
0 => E_0, //= OR interrupts disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_OR_IS_SET, //= Hardware interrupt requested when OR is set.
}
4 => TXINVrw { //! Transmit Data Inversion
0 => TRANSMIT_DATA_NOT_INVERTED, //= Transmit data not inverted.
1 => TRANSMIT_DATA_INVERTED, //= Transmit data inverted.
}
5 => TXDIRrw { //! UART _TX Pin Direction in Single-Wire Mode
0 => UART__TXD_PIN_IS_AN_INPUT_IN_SINGLE_WIRE_MODE, //= UART _TXD pin is an input in single-wire mode.
1 => UART__TXD_PIN_IS_AN_OUTPUT_IN_SINGLE_WIRE_MODE, //= UART _TXD pin is an output in single-wire mode.
}
6 => R9T8 rw, //= Receive Bit 9 / Transmit Bit 8
7 => R8T9 rw, //= Receive Bit 8 / Transmit Bit 9
},
0x07 => reg8 D { //! UART Data Register
0 => R0T0 rw, //= no description available
1 => R1T1 rw, //= no description available
2 => R2T2 rw, //= no description available
3 => R3T3 rw, //= no description available
4 => R4T4 rw, //= no description available
5 => R5T5 rw, //= no description available
6 => R6T6 rw, //= no description available
7 => R7T7 rw, //= no description available
},
0x08 => reg8 MA1 { //! UART Match Address Registers 1
0..7 => MA rw, //= Match Address
},
0x09 => reg8 MA2 { //! UART Match Address Registers 2
0..7 => MA rw, //= Match Address
},
0x0A => reg8 C4 { //! UART Control Register 4
0..4 => OSR rw, //= Over Sampling Ratio
5 => M10rw { //! 10-bit Mode select
0 => RECEIVER_AND_TRANSMITTER_USE_8_BIT_OR_9_BIT_DATA_CHARACTERS, //= Receiver and transmitter use 8-bit or 9-bit data characters.
1 => RECEIVER_AND_TRANSMITTER_USE_10_BIT_DATA_CHARACTERS, //= Receiver and transmitter use 10-bit data characters.
}
6 => MAEN2rw { //! Match Address Mode Enable 2
0 => ALL_DATA_RECEIVED_IS_TRANSFERRED_TO_THE_DATA_BUFFER_IF_MAEN1_IS_CLEARED, //= All data received is transferred to the data buffer if MAEN1 is cleared.
1 => ALL_DATA_RECEIVED_WITH_THE_MOST_SIGNIFICANT_BIT_CLEARED_IS_DISCARDED_ALL_DATA_RECEIVED_WITH_THE_MOST_SIGNIFICANT_BIT_SET_IS_COMPARED_WITH_CONTENTS_OF_MA2_REGISTER_IF_NO_MATCH_OCCURS_THE_DATA_IS_DISCARDED_IF_MATCH_OCCURS_DATA_IS_TRANSFERRED_TO_THE_DATA_BUFFER, //= All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.
}
7 => MAEN1rw { //! Match Address Mode Enable 1
0 => ALL_DATA_RECEIVED_IS_TRANSFERRED_TO_THE_DATA_BUFFER_IF_MAEN2_IS_CLEARED, //= All data received is transferred to the data buffer if MAEN2 is cleared.
1 => ALL_DATA_RECEIVED_WITH_THE_MOST_SIGNIFICANT_BIT_CLEARED_IS_DISCARDED_ALL_DATA_RECEIVED_WITH_THE_MOST_SIGNIFICANT_BIT_SET_IS_COMPARED_WITH_CONTENTS_OF_MA1_REGISTER_IF_NO_MATCH_OCCURS_THE_DATA_IS_DISCARDED_IF_MATCH_OCCURS_DATA_IS_TRANSFERRED_TO_THE_DATA_BUFFER, //= All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.
}
},
0x0B => reg8 C5 { //! UART Control Register 5
0 => RESYNCDISrw { //! Resynchronization Disable
0 => RESYNCHRONIZATION_DURING_RECEIVED_DATA_WORD_IS_SUPPORTED, //= Resynchronization during received data word is supported
1 => RESYNCHRONIZATION_DURING_RECEIVED_DATA_WORD_IS_DISABLED, //= Resynchronization during received data word is disabled
}
1 => BOTHEDGErw { //! Both Edge Sampling
0 => RECEIVER_SAMPLES_INPUT_DATA_USING_THE_RISING_EDGE_OF_THE_BAUD_RATE_CLOCK, //= Receiver samples input data using the rising edge of the baud rate clock.
1 => RECEIVER_SAMPLES_INPUT_DATA_USING_THE_RISING_AND_FALLING_EDGE_OF_THE_BAUD_RATE_CLOCK, //= Receiver samples input data using the rising and falling edge of the baud rate clock.
}
5 => RDMAErw { //! Receiver Full DMA Enable
0 => DMA_REQUEST_DISABLED, //= DMA request disabled.
1 => DMA_REQUEST_ENABLED, //= DMA request enabled.
}
7 => TDMAErw { //! Transmitter DMA Enable
0 => DMA_REQUEST_DISABLED, //= DMA request disabled.
1 => DMA_REQUEST_ENABLED, //= DMA request enabled.
}
},
});
ioregs!(UART1 @ 0x4006B000 = { //! Universal Asynchronous Receiver/Transmitter (UART)
0x00 => reg8 BDH { //! UART Baud Rate Register: High
0..4 => SBR rw, //= Baud Rate Modulo Divisor.
5 => SBNSrw { //! Stop Bit Number Select
0 => ONE_STOP_BIT, //= One stop bit.
1 => TWO_STOP_BIT, //= Two stop bit.
}
6 => RXEDGIErw { //! RxD Input Active Edge Interrupt Enable (for RXEDGIF)
0 => E_0, //= Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_UART_S2[RXEDGIF]_FLAG_IS_1, //= Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
}
7 => LBKDIErw { //! LIN Break Detect Interrupt Enable (for LBKDIF)
0 => E_0, //= Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_UART_S2[LBKDIF]_FLAG_IS_1, //= Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
}
},
0x01 => reg8 BDL { //! UART Baud Rate Register: Low
0..7 => SBR rw, //= Baud Rate Modulo Divisor
},
0x02 => reg8 C1 { //! UART Control Register 1
0 => PTrw { //! Parity Type
0 => EVEN_PARITY, //= Even parity.
1 => ODD_PARITY, //= Odd parity.
}
1 => PErw { //! Parity Enable
0 => NO_HARDWARE_PARITY_GENERATION_OR_CHECKING, //= No hardware parity generation or checking.
1 => PARITY_ENABLED, //= Parity enabled.
}
2 => ILTrw { //! Idle Line Type Select
0 => IDLE_CHARACTER_BIT_COUNT_STARTS_AFTER_START_BIT, //= Idle character bit count starts after start bit.
1 => IDLE_CHARACTER_BIT_COUNT_STARTS_AFTER_STOP_BIT, //= Idle character bit count starts after stop bit.
}
3 => WAKErw { //! Receiver Wakeup Method Select
0 => IDLE_LINE_WAKEUP, //= Idle-line wakeup.
1 => ADDRESS_MARK_WAKEUP, //= Address-mark wakeup.
}
4 => Mrw { //! 9-Bit or 8-Bit Mode Select
0 => E_0, //= Normal - start + 8 data bits (lsb first) + stop.
1 => E_1, //= Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
}
5 => RSRCrw { //! Receiver Source Select
0 => PROVIDED_LOOPS_IS_SET_RSRC_IS_CLEARED_SELECTS_INTERNAL_LOOP_BACK_MODE_AND_THE_UART_DOES_NOT_USE_THE_RXD_PINS, //= Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.
1 => SINGLE_WIRE_UART_MODE_WHERE_THE_TXD_PIN_IS_CONNECTED_TO_THE_TRANSMITTER_OUTPUT_AND_RECEIVER_INPUT, //= Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.
}
6 => UARTSWAIrw { //! UART Stops in Wait Mode
0 => UART_CLOCKS_CONTINUE_TO_RUN_IN_WAIT_MODE_SO_THE_UART_CAN_BE_THE_SOURCE_OF_AN_INTERRUPT_THAT_WAKES_UP_THE_CPU, //= UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU.
1 => UART_CLOCKS_FREEZE_WHILE_CPU_IS_IN_WAIT_MODE, //= UART clocks freeze while CPU is in wait mode.
}
7 => LOOPSrw { //! Loop Mode Select
0 => NORMAL_OPERATION___RXD_AND_TXD_USE_SEPARATE_PINS, //= Normal operation - RxD and TxD use separate pins.
1 => E_1, //= Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.
}
},
0x03 => reg8 C2 { //! UART Control Register 2
0 => SBKrw { //! Send Break
0 => NORMAL_TRANSMITTER_OPERATION, //= Normal transmitter operation.
1 => E_1, //= Queue break character(s) to be sent.
}
1 => RWUrw { //! Receiver Wakeup Control
0 => NORMAL_UART_RECEIVER_OPERATION, //= Normal UART receiver operation.
1 => UART_RECEIVER_IN_STANDBY_WAITING_FOR_WAKEUP_CONDITION, //= UART receiver in standby waiting for wakeup condition.
}
2 => RErw { //! Receiver Enable
0 => RECEIVER_OFF, //= Receiver off.
1 => RECEIVER_ON, //= Receiver on.
}
3 => TErw { //! Transmitter Enable
0 => TRANSMITTER_OFF, //= Transmitter off.
1 => TRANSMITTER_ON, //= Transmitter on.
}
4 => ILIErw { //! Idle Line Interrupt Enable for IDLE
0 => E_0, //= Hardware interrupts from IDLE disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_IDLE_FLAG_IS_1, //= Hardware interrupt requested when IDLE flag is 1.
}
5 => RIErw { //! Receiver Interrupt Enable for RDRF
0 => E_0, //= Hardware interrupts from RDRF disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_RDRF_FLAG_IS_1, //= Hardware interrupt requested when RDRF flag is 1.
}
6 => TCIErw { //! Transmission Complete Interrupt Enable for TC
0 => E_0, //= Hardware interrupts from TC disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_TC_FLAG_IS_1, //= Hardware interrupt requested when TC flag is 1.
}
7 => TIErw { //! Transmit Interrupt Enable for TDRE
0 => E_0, //= Hardware interrupts from TDRE disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_TDRE_FLAG_IS_1, //= Hardware interrupt requested when TDRE flag is 1.
}
},
0x04 => reg8 S1 { //! UART Status Register 1
0 => PFro { //! Parity Error Flag
0 => NO_PARITY_ERROR, //= No parity error.
1 => PARITY_ERROR, //= Parity error.
}
1 => FEro { //! Framing Error Flag
0 => NO_FRAMING_ERROR_DETECTED_THIS_DOES_NOT_GUARANTEE_THE_FRAMING_IS_CORRECT, //= No framing error detected. This does not guarantee the framing is correct.
1 => FRAMING_ERROR, //= Framing error.
}
2 => NFro { //! Noise Flag
0 => NO_NOISE_DETECTED, //= No noise detected.
1 => NOISE_DETECTED_IN_THE_RECEIVED_CHARACTER_IN_UART_D, //= Noise detected in the received character in UART_D.
}
3 => ORro { //! Receiver Overrun Flag
0 => NO_OVERRUN, //= No overrun.
1 => E_1, //= Receive overrun (new UART data lost).
}
4 => IDLEro { //! Idle Line Flag
0 => NO_IDLE_LINE_DETECTED, //= No idle line detected.
1 => IDLE_LINE_WAS_DETECTED, //= Idle line was detected.
}
5 => RDRFro { //! Receive Data Register Full Flag
0 => RECEIVE_DATA_REGISTER_EMPTY, //= Receive data register empty.
1 => RECEIVE_DATA_REGISTER_FULL, //= Receive data register full.
}
6 => TCro { //! Transmission Complete Flag
0 => E_0, //= Transmitter active (sending data, a preamble, or a break).
1 => E_1, //= Transmitter idle (transmission activity complete).
}
7 => TDREro { //! Transmit Data Register Empty Flag
0 => E_0, //= Transmit data register (buffer) full.
1 => E_1, //= Transmit data register (buffer) empty.
}
},
0x05 => reg8 S2 { //! UART Status Register 2
0 => RAFro { //! Receiver Active Flag
0 => UART_RECEIVER_IDLE_WAITING_FOR_A_START_BIT, //= UART receiver idle waiting for a start bit.
1 => E_1, //= UART receiver active (RxD input not idle).
}
1 => LBKDErw { //! LIN Break Detection Enable
0 => E_0, //= Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
1 => E_1, //= Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1).
}
2 => BRK13rw { //! Break Character Generation Length
0 => E_0, //= Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
1 => E_1, //= Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).
}
3 => RWUIDrw { //! Receive Wake Up Idle Detect
0 => E_0, //= During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
1 => E_1, //= During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
}
4 => RXINVrw { //! Receive Data Inversion
0 => RECEIVE_DATA_NOT_INVERTED, //= Receive data not inverted.
1 => RECEIVE_DATA_INVERTED, //= Receive data inverted.
}
6 => RXEDGIFrw { //! RxD Pin Active Edge Interrupt Flag
0 => NO_ACTIVE_EDGE_ON_THE_RECEIVE_PIN_HAS_OCCURRED, //= No active edge on the receive pin has occurred.
1 => AN_ACTIVE_EDGE_ON_THE_RECEIVE_PIN_HAS_OCCURRED, //= An active edge on the receive pin has occurred.
}
7 => LBKDIFrw { //! LIN Break Detect Interrupt Flag
0 => NO_LIN_BREAK_CHARACTER_HAS_BEEN_DETECTED, //= No LIN break character has been detected.
1 => LIN_BREAK_CHARACTER_HAS_BEEN_DETECTED, //= LIN break character has been detected.
}
},
0x06 => reg8 C3 { //! UART Control Register 3
0 => PEIErw { //! Parity Error Interrupt Enable
0 => E_0, //= PF interrupts disabled; use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_PF_IS_SET, //= Hardware interrupt requested when PF is set.
}
1 => FEIErw { //! Framing Error Interrupt Enable
0 => E_0, //= FE interrupts disabled; use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_FE_IS_SET, //= Hardware interrupt requested when FE is set.
}
2 => NEIErw { //! Noise Error Interrupt Enable
0 => E_0, //= NF interrupts disabled; use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_NF_IS_SET, //= Hardware interrupt requested when NF is set.
}
3 => ORIErw { //! Overrun Interrupt Enable
0 => E_0, //= OR interrupts disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_OR_IS_SET, //= Hardware interrupt requested when OR is set.
}
4 => TXINVrw { //! Transmit Data Inversion
0 => TRANSMIT_DATA_NOT_INVERTED, //= Transmit data not inverted.
1 => TRANSMIT_DATA_INVERTED, //= Transmit data inverted.
}
5 => TXDIRrw { //! TxD Pin Direction in Single-Wire Mode
0 => TXD_PIN_IS_AN_INPUT_IN_SINGLE_WIRE_MODE, //= TxD pin is an input in single-wire mode.
1 => TXD_PIN_IS_AN_OUTPUT_IN_SINGLE_WIRE_MODE, //= TxD pin is an output in single-wire mode.
}
6 => T8 rw, //= Ninth Data Bit for Transmitter
7 => R8 ro, //= Ninth Data Bit for Receiver
},
0x07 => reg8 D { //! UART Data Register
0 => R0T0 rw, //= no description available
1 => R1T1 rw, //= no description available
2 => R2T2 rw, //= no description available
3 => R3T3 rw, //= no description available
4 => R4T4 rw, //= no description available
5 => R5T5 rw, //= no description available
6 => R6T6 rw, //= no description available
7 => R7T7 rw, //= no description available
},
0x08 => reg8 C4 { //! UART Control Register 4
5 => RDMASrw { //! Receiver Full DMA Select
0 => IF_RIE_IS_SET_AND_THE_RDRF_FLAG_IS_SET_THE_RDRF_INTERRUPT_REQUEST_SIGNAL_IS_ASSERTED_TO_REQUEST_INTERRUPT_SERVICE, //= If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted to request interrupt service.
1 => IF_RIE_IS_SET_AND_THE_RDRF_FLAG_IS_SET_THE_RDRF_DMA_REQUEST_SIGNAL_IS_ASSERTED_TO_REQUEST_A_DMA_TRANSFER, //= If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.
}
7 => TDMASrw { //! Transmitter DMA Select
0 => IF_TIE_IS_SET_AND_THE_TDRE_FLAG_IS_SET_THE_TDRE_INTERRUPT_REQUEST_SIGNAL_IS_ASSERTED_TO_REQUEST_INTERRUPT_SERVICE, //= If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
1 => IF_TIE_IS_SET_AND_THE_TDRE_FLAG_IS_SET_THE_TDRE_DMA_REQUEST_SIGNAL_IS_ASSERTED_TO_REQUEST_A_DMA_TRANSFER, //= If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
}
},
});
ioregs!(UART2 @ 0x4006C000 = { //! Universal Asynchronous Receiver/Transmitter (UART)
0x00 => reg8 BDH { //! UART Baud Rate Register: High
0..4 => SBR rw, //= Baud Rate Modulo Divisor.
5 => SBNSrw { //! Stop Bit Number Select
0 => ONE_STOP_BIT, //= One stop bit.
1 => TWO_STOP_BIT, //= Two stop bit.
}
6 => RXEDGIErw { //! RxD Input Active Edge Interrupt Enable (for RXEDGIF)
0 => E_0, //= Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_UART_S2[RXEDGIF]_FLAG_IS_1, //= Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
}
7 => LBKDIErw { //! LIN Break Detect Interrupt Enable (for LBKDIF)
0 => E_0, //= Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_UART_S2[LBKDIF]_FLAG_IS_1, //= Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
}
},
0x01 => reg8 BDL { //! UART Baud Rate Register: Low
0..7 => SBR rw, //= Baud Rate Modulo Divisor
},
0x02 => reg8 C1 { //! UART Control Register 1
0 => PTrw { //! Parity Type
0 => EVEN_PARITY, //= Even parity.
1 => ODD_PARITY, //= Odd parity.
}
1 => PErw { //! Parity Enable
0 => NO_HARDWARE_PARITY_GENERATION_OR_CHECKING, //= No hardware parity generation or checking.
1 => PARITY_ENABLED, //= Parity enabled.
}
2 => ILTrw { //! Idle Line Type Select
0 => IDLE_CHARACTER_BIT_COUNT_STARTS_AFTER_START_BIT, //= Idle character bit count starts after start bit.
1 => IDLE_CHARACTER_BIT_COUNT_STARTS_AFTER_STOP_BIT, //= Idle character bit count starts after stop bit.
}
3 => WAKErw { //! Receiver Wakeup Method Select
0 => IDLE_LINE_WAKEUP, //= Idle-line wakeup.
1 => ADDRESS_MARK_WAKEUP, //= Address-mark wakeup.
}
4 => Mrw { //! 9-Bit or 8-Bit Mode Select
0 => E_0, //= Normal - start + 8 data bits (lsb first) + stop.
1 => E_1, //= Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
}
5 => RSRCrw { //! Receiver Source Select
0 => PROVIDED_LOOPS_IS_SET_RSRC_IS_CLEARED_SELECTS_INTERNAL_LOOP_BACK_MODE_AND_THE_UART_DOES_NOT_USE_THE_RXD_PINS, //= Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.
1 => SINGLE_WIRE_UART_MODE_WHERE_THE_TXD_PIN_IS_CONNECTED_TO_THE_TRANSMITTER_OUTPUT_AND_RECEIVER_INPUT, //= Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.
}
6 => UARTSWAIrw { //! UART Stops in Wait Mode
0 => UART_CLOCKS_CONTINUE_TO_RUN_IN_WAIT_MODE_SO_THE_UART_CAN_BE_THE_SOURCE_OF_AN_INTERRUPT_THAT_WAKES_UP_THE_CPU, //= UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU.
1 => UART_CLOCKS_FREEZE_WHILE_CPU_IS_IN_WAIT_MODE, //= UART clocks freeze while CPU is in wait mode.
}
7 => LOOPSrw { //! Loop Mode Select
0 => NORMAL_OPERATION___RXD_AND_TXD_USE_SEPARATE_PINS, //= Normal operation - RxD and TxD use separate pins.
1 => E_1, //= Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.
}
},
0x03 => reg8 C2 { //! UART Control Register 2
0 => SBKrw { //! Send Break
0 => NORMAL_TRANSMITTER_OPERATION, //= Normal transmitter operation.
1 => E_1, //= Queue break character(s) to be sent.
}
1 => RWUrw { //! Receiver Wakeup Control
0 => NORMAL_UART_RECEIVER_OPERATION, //= Normal UART receiver operation.
1 => UART_RECEIVER_IN_STANDBY_WAITING_FOR_WAKEUP_CONDITION, //= UART receiver in standby waiting for wakeup condition.
}
2 => RErw { //! Receiver Enable
0 => RECEIVER_OFF, //= Receiver off.
1 => RECEIVER_ON, //= Receiver on.
}
3 => TErw { //! Transmitter Enable
0 => TRANSMITTER_OFF, //= Transmitter off.
1 => TRANSMITTER_ON, //= Transmitter on.
}
4 => ILIErw { //! Idle Line Interrupt Enable for IDLE
0 => E_0, //= Hardware interrupts from IDLE disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_IDLE_FLAG_IS_1, //= Hardware interrupt requested when IDLE flag is 1.
}
5 => RIErw { //! Receiver Interrupt Enable for RDRF
0 => E_0, //= Hardware interrupts from RDRF disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_RDRF_FLAG_IS_1, //= Hardware interrupt requested when RDRF flag is 1.
}
6 => TCIErw { //! Transmission Complete Interrupt Enable for TC
0 => E_0, //= Hardware interrupts from TC disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_TC_FLAG_IS_1, //= Hardware interrupt requested when TC flag is 1.
}
7 => TIErw { //! Transmit Interrupt Enable for TDRE
0 => E_0, //= Hardware interrupts from TDRE disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_TDRE_FLAG_IS_1, //= Hardware interrupt requested when TDRE flag is 1.
}
},
0x04 => reg8 S1 { //! UART Status Register 1
0 => PFro { //! Parity Error Flag
0 => NO_PARITY_ERROR, //= No parity error.
1 => PARITY_ERROR, //= Parity error.
}
1 => FEro { //! Framing Error Flag
0 => NO_FRAMING_ERROR_DETECTED_THIS_DOES_NOT_GUARANTEE_THE_FRAMING_IS_CORRECT, //= No framing error detected. This does not guarantee the framing is correct.
1 => FRAMING_ERROR, //= Framing error.
}
2 => NFro { //! Noise Flag
0 => NO_NOISE_DETECTED, //= No noise detected.
1 => NOISE_DETECTED_IN_THE_RECEIVED_CHARACTER_IN_UART_D, //= Noise detected in the received character in UART_D.
}
3 => ORro { //! Receiver Overrun Flag
0 => NO_OVERRUN, //= No overrun.
1 => E_1, //= Receive overrun (new UART data lost).
}
4 => IDLEro { //! Idle Line Flag
0 => NO_IDLE_LINE_DETECTED, //= No idle line detected.
1 => IDLE_LINE_WAS_DETECTED, //= Idle line was detected.
}
5 => RDRFro { //! Receive Data Register Full Flag
0 => RECEIVE_DATA_REGISTER_EMPTY, //= Receive data register empty.
1 => RECEIVE_DATA_REGISTER_FULL, //= Receive data register full.
}
6 => TCro { //! Transmission Complete Flag
0 => E_0, //= Transmitter active (sending data, a preamble, or a break).
1 => E_1, //= Transmitter idle (transmission activity complete).
}
7 => TDREro { //! Transmit Data Register Empty Flag
0 => E_0, //= Transmit data register (buffer) full.
1 => E_1, //= Transmit data register (buffer) empty.
}
},
0x05 => reg8 S2 { //! UART Status Register 2
0 => RAFro { //! Receiver Active Flag
0 => UART_RECEIVER_IDLE_WAITING_FOR_A_START_BIT, //= UART receiver idle waiting for a start bit.
1 => E_1, //= UART receiver active (RxD input not idle).
}
1 => LBKDErw { //! LIN Break Detection Enable
0 => E_0, //= Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
1 => E_1, //= Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1).
}
2 => BRK13rw { //! Break Character Generation Length
0 => E_0, //= Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
1 => E_1, //= Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).
}
3 => RWUIDrw { //! Receive Wake Up Idle Detect
0 => E_0, //= During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
1 => E_1, //= During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
}
4 => RXINVrw { //! Receive Data Inversion
0 => RECEIVE_DATA_NOT_INVERTED, //= Receive data not inverted.
1 => RECEIVE_DATA_INVERTED, //= Receive data inverted.
}
6 => RXEDGIFrw { //! RxD Pin Active Edge Interrupt Flag
0 => NO_ACTIVE_EDGE_ON_THE_RECEIVE_PIN_HAS_OCCURRED, //= No active edge on the receive pin has occurred.
1 => AN_ACTIVE_EDGE_ON_THE_RECEIVE_PIN_HAS_OCCURRED, //= An active edge on the receive pin has occurred.
}
7 => LBKDIFrw { //! LIN Break Detect Interrupt Flag
0 => NO_LIN_BREAK_CHARACTER_HAS_BEEN_DETECTED, //= No LIN break character has been detected.
1 => LIN_BREAK_CHARACTER_HAS_BEEN_DETECTED, //= LIN break character has been detected.
}
},
0x06 => reg8 C3 { //! UART Control Register 3
0 => PEIErw { //! Parity Error Interrupt Enable
0 => E_0, //= PF interrupts disabled; use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_PF_IS_SET, //= Hardware interrupt requested when PF is set.
}
1 => FEIErw { //! Framing Error Interrupt Enable
0 => E_0, //= FE interrupts disabled; use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_FE_IS_SET, //= Hardware interrupt requested when FE is set.
}
2 => NEIErw { //! Noise Error Interrupt Enable
0 => E_0, //= NF interrupts disabled; use polling).
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_NF_IS_SET, //= Hardware interrupt requested when NF is set.
}
3 => ORIErw { //! Overrun Interrupt Enable
0 => E_0, //= OR interrupts disabled; use polling.
1 => HARDWARE_INTERRUPT_REQUESTED_WHEN_OR_IS_SET, //= Hardware interrupt requested when OR is set.
}
4 => TXINVrw { //! Transmit Data Inversion
0 => TRANSMIT_DATA_NOT_INVERTED, //= Transmit data not inverted.
1 => TRANSMIT_DATA_INVERTED, //= Transmit data inverted.
}
5 => TXDIRrw { //! TxD Pin Direction in Single-Wire Mode
0 => TXD_PIN_IS_AN_INPUT_IN_SINGLE_WIRE_MODE, //= TxD pin is an input in single-wire mode.
1 => TXD_PIN_IS_AN_OUTPUT_IN_SINGLE_WIRE_MODE, //= TxD pin is an output in single-wire mode.
}
6 => T8 rw, //= Ninth Data Bit for Transmitter
7 => R8 ro, //= Ninth Data Bit for Receiver
},
0x07 => reg8 D { //! UART Data Register
0 => R0T0 rw, //= no description available
1 => R1T1 rw, //= no description available
2 => R2T2 rw, //= no description available
3 => R3T3 rw, //= no description available
4 => R4T4 rw, //= no description available
5 => R5T5 rw, //= no description available
6 => R6T6 rw, //= no description available
7 => R7T7 rw, //= no description available
},
0x08 => reg8 C4 { //! UART Control Register 4
5 => RDMASrw { //! Receiver Full DMA Select
0 => IF_RIE_IS_SET_AND_THE_RDRF_FLAG_IS_SET_THE_RDRF_INTERRUPT_REQUEST_SIGNAL_IS_ASSERTED_TO_REQUEST_INTERRUPT_SERVICE, //= If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted to request interrupt service.
1 => IF_RIE_IS_SET_AND_THE_RDRF_FLAG_IS_SET_THE_RDRF_DMA_REQUEST_SIGNAL_IS_ASSERTED_TO_REQUEST_A_DMA_TRANSFER, //= If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.
}
7 => TDMASrw { //! Transmitter DMA Select
0 => IF_TIE_IS_SET_AND_THE_TDRE_FLAG_IS_SET_THE_TDRE_INTERRUPT_REQUEST_SIGNAL_IS_ASSERTED_TO_REQUEST_INTERRUPT_SERVICE, //= If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
1 => IF_TIE_IS_SET_AND_THE_TDRE_FLAG_IS_SET_THE_TDRE_DMA_REQUEST_SIGNAL_IS_ASSERTED_TO_REQUEST_A_DMA_TRANSFER, //= If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
}
},
});
ioregs!(USB0 @ 0x40072000 = { //! Universal Serial Bus, OTG Capable Controller
0x00 => reg8 PERID { //! Peripheral ID register
0..5 => ID ro, //= Peripheral Identification
},
0x04 => reg8 IDCOMP { //! Peripheral ID Complement register
0..5 => NID ro, //= no description available
},
0x08 => reg8 REV { //! Peripheral Revision register
0..7 => REV ro, //= Revision
},
0x0C => reg8 ADDINFO { //! Peripheral Additional Info register
0 => IEHOST ro, //= no description available
3..7 => IRQNUM ro, //= Assigned Interrupt Request Number
},
0x10 => reg8 OTGISTAT { //! OTG Interrupt Status register
0 => AVBUSCHG rw, //= no description available
2 => B_SESS_CHG rw, //= no description available
3 => SESSVLDCHG rw, //= no description available
5 => LINE_STATE_CHG rw, //= no description available
6 => ONEMSEC rw, //= no description available
7 => IDCHG rw, //= no description available
},
0x14 => reg8 OTGICR { //! OTG Interrupt Control Register
0 => AVBUSENrw { //! A VBUS Valid Interrupt Enable
0 => DISABLES_THE_AVBUSCHG_INTERRUPT, //= Disables the AVBUSCHG interrupt.
1 => ENABLES_THE_AVBUSCHG_INTERRUPT, //= Enables the AVBUSCHG interrupt.
}
2 => BSESSENrw { //! B Session END Interrupt Enable
0 => DISABLES_THE_B_SESS_CHG_INTERRUPT, //= Disables the B_SESS_CHG interrupt.
1 => ENABLES_THE_B_SESS_CHG_INTERRUPT, //= Enables the B_SESS_CHG interrupt.
}
3 => SESSVLDENrw { //! Session Valid Interrupt Enable
0 => DISABLES_THE_SESSVLDCHG_INTERRUPT, //= Disables the SESSVLDCHG interrupt.
1 => ENABLES_THE_SESSVLDCHG_INTERRUPT, //= Enables the SESSVLDCHG interrupt.
}
5 => LINESTATEENrw { //! Line State Change Interrupt Enable
0 => DISABLES_THE_LINE_STAT_CHG_INTERRUPT, //= Disables the LINE_STAT_CHG interrupt.
1 => ENABLES_THE_LINE_STAT_CHG_INTERRUPT, //= Enables the LINE_STAT_CHG interrupt.
}
6 => ONEMSECENrw { //! One Millisecond Interrupt Enable
0 => DIABLES_THE_1MS_TIMER_INTERRUPT, //= Diables the 1ms timer interrupt.
1 => ENABLES_THE_1MS_TIMER_INTERRUPT, //= Enables the 1ms timer interrupt.
}
7 => IDENrw { //! ID Interrupt Enable
0 => THE_ID_INTERRUPT_IS_DISABLED, //= The ID interrupt is disabled
1 => THE_ID_INTERRUPT_IS_ENABLED, //= The ID interrupt is enabled
}
},
0x18 => reg8 OTGSTAT { //! OTG Status register
0 => AVBUSVLDrw { //! A VBUS Valid
0 => THE_VBUS_VOLTAGE_IS_BELOW_THE_A_VBUS_VALID_THRESHOLD, //= The VBUS voltage is below the A VBUS Valid threshold.
1 => THE_VBUS_VOLTAGE_IS_ABOVE_THE_A_VBUS_VALID_THRESHOLD, //= The VBUS voltage is above the A VBUS Valid threshold.
}
2 => BSESSENDrw { //! B Session End
0 => THE_VBUS_VOLTAGE_IS_ABOVE_THE_B_SESSION_END_THRESHOLD, //= The VBUS voltage is above the B session end threshold.
1 => THE_VBUS_VOLTAGE_IS_BELOW_THE_B_SESSION_END_THRESHOLD, //= The VBUS voltage is below the B session end threshold.
}
3 => SESS_VLDrw { //! Session Valid
0 => THE_VBUS_VOLTAGE_IS_BELOW_THE_B_SESSION_VALID_THRESHOLD, //= The VBUS voltage is below the B session valid threshold
1 => THE_VBUS_VOLTAGE_IS_ABOVE_THE_B_SESSION_VALID_THRESHOLD, //= The VBUS voltage is above the B session valid threshold.
}
5 => LINESTATESTABLErw { //! no description available
0 => THE_LINE_STAT_CHG_BIT_IS_NOT_YET_STABLE, //= The LINE_STAT_CHG bit is not yet stable.
1 => THE_LINE_STAT_CHG_BIT_HAS_BEEN_DEBOUNCED_AND_IS_STABLE, //= The LINE_STAT_CHG bit has been debounced and is stable.
}
6 => ONEMSECEN rw, //= no description available
7 => IDrw { //! no description available
0 => INDICATES_A_TYPE_A_CABLE_IS_PLUGGED_INTO_THE_USB_CONNECTOR, //= Indicates a Type A cable is plugged into the USB connector.
1 => INDICATES_NO_CABLE_IS_ATTACHED_OR_A_TYPE_B_CABLE_IS_PLUGGED_INTO_THE_USB_CONNECTOR, //= Indicates no cable is attached or a Type B cable is plugged into the USB connector.
}
},
0x1C => reg8 OTGCTL { //! OTG Control register
2 => OTGENrw { //! On-The-Go pullup/pulldown resistor enable
0 => E_0, //= If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged.
1 => THE_PULL_UP_AND_PULL_DOWN_CONTROLS_IN_THIS_REGISTER_ARE_USED, //= The pull-up and pull-down controls in this register are used.
}
4 => DMLOWrw { //! D- Data Line pull-down resistor enable
0 => D__PULLDOWN_RESISTOR_IS_NOT_ENABLED, //= D- pulldown resistor is not enabled.
1 => D__PULLDOWN_RESISTOR_IS_ENABLED, //= D- pulldown resistor is enabled.
}
5 => DPLOWrw { //! D+ Data Line pull-down resistor enable
0 => D+_PULLDOWN_RESISTOR_IS_NOT_ENABLED, //= D+ pulldown resistor is not enabled.
1 => D+_PULLDOWN_RESISTOR_IS_ENABLED, //= D+ pulldown resistor is enabled.
}
7 => DPHIGHrw { //! D+ Data Line pullup resistor enable
0 => D+_PULLUP_RESISTOR_IS_NOT_ENABLED, //= D+ pullup resistor is not enabled
1 => D+_PULLUP_RESISTOR_IS_ENABLED, //= D+ pullup resistor is enabled
}
},
0x80 => reg8 ISTAT { //! Interrupt Status register
0 => USBRST rw, //= no description available
1 => ERROR rw, //= no description available
2 => SOFTOK rw, //= no description available
3 => TOKDNE rw, //= no description available
4 => SLEEP rw, //= no description available
5 => RESUME rw, //= no description available
6 => ATTACH rw, //= Attach Interrupt
7 => STALL rw, //= Stall Interrupt
},
0x84 => reg8 INTEN { //! Interrupt Enable register
0 => USBRSTENrw { //! USBRST Interrupt Enable
0 => DISABLES_THE_USBRST_INTERRUPT, //= Disables the USBRST interrupt.
1 => ENABLES_THE_USBRST_INTERRUPT, //= Enables the USBRST interrupt.
}
1 => ERRORENrw { //! ERROR Interrupt Enable
0 => DISABLES_THE_ERROR_INTERRUPT, //= Disables the ERROR interrupt.
1 => ENABLES_THE_ERROR_INTERRUPT, //= Enables the ERROR interrupt.
}
2 => SOFTOKENrw { //! SOFTOK Interrupt Enable
0 => DISBLES_THE_SOFTOK_INTERRUPT, //= Disbles the SOFTOK interrupt.
1 => ENABLES_THE_SOFTOK_INTERRUPT, //= Enables the SOFTOK interrupt.
}
3 => TOKDNEENrw { //! TOKDNE Interrupt Enable
0 => DISABLES_THE_TOKDNE_INTERRUPT, //= Disables the TOKDNE interrupt.
1 => ENABLES_THE_TOKDNE_INTERRUPT, //= Enables the TOKDNE interrupt.
}
4 => SLEEPENrw { //! SLEEP Interrupt Enable
0 => DISABLES_THE_SLEEP_INTERRUPT, //= Disables the SLEEP interrupt.
1 => ENABLES_THE_SLEEP_INTERRUPT, //= Enables the SLEEP interrupt.
}
5 => RESUMEENrw { //! RESUME Interrupt Enable
0 => DISABLES_THE_RESUME_INTERRUPT, //= Disables the RESUME interrupt.
1 => ENABLES_THE_RESUME_INTERRUPT, //= Enables the RESUME interrupt.
}
6 => ATTACHENrw { //! ATTACH Interrupt Enable
0 => DISABLES_THE_ATTACH_INTERRUPT, //= Disables the ATTACH interrupt.
1 => ENABLES_THE_ATTACH_INTERRUPT, //= Enables the ATTACH interrupt.
}
7 => STALLENrw { //! STALL Interrupt Enable
0 => DIASBLES_THE_STALL_INTERRUPT, //= Diasbles the STALL interrupt.
1 => ENABLES_THE_STALL_INTERRUPT, //= Enables the STALL interrupt.
}
},
0x88 => reg8 ERRSTAT { //! Error Interrupt Status register
0 => PIDERR rw, //= no description available
1 => CRC5EOF rw, //= no description available
2 => CRC16 rw, //= no description available
3 => DFN8 rw, //= no description available
4 => BTOERR rw, //= no description available
5 => DMAERR rw, //= no description available
7 => BTSERR rw, //= no description available
},
0x8C => reg8 ERREN { //! Error Interrupt Enable register
0 => PIDERRENrw { //! PIDERR Interrupt Enable
0 => DISABLES_THE_PIDERR_INTERRUPT, //= Disables the PIDERR interrupt.
1 => ENTERS_THE_PIDERR_INTERRUPT, //= Enters the PIDERR interrupt.
}
1 => CRC5EOFENrw { //! CRC5/EOF Interrupt Enable
0 => DISABLES_THE_CRC5EOF_INTERRUPT, //= Disables the CRC5/EOF interrupt.
1 => ENABLES_THE_CRC5EOF_INTERRUPT, //= Enables the CRC5/EOF interrupt.
}
2 => CRC16ENrw { //! CRC16 Interrupt Enable
0 => DISABLES_THE_CRC16_INTERRUPT, //= Disables the CRC16 interrupt.
1 => ENABLES_THE_CRC16_INTERRUPT, //= Enables the CRC16 interrupt.
}
3 => DFN8ENrw { //! DFN8 Interrupt Enable
0 => DISABLES_THE_DFN8_INTERRUPT, //= Disables the DFN8 interrupt.
1 => ENABLES_THE_DFN8_INTERRUPT, //= Enables the DFN8 interrupt.
}
4 => BTOERRENrw { //! BTOERR Interrupt Enable
0 => DISABLES_THE_BTOERR_INTERRUPT, //= Disables the BTOERR interrupt.
1 => ENABLES_THE_BTOERR_INTERRUPT, //= Enables the BTOERR interrupt.
}
5 => DMAERRENrw { //! DMAERR Interrupt Enable
0 => DISABLES_THE_DMAERR_INTERRUPT, //= Disables the DMAERR interrupt.
1 => ENABLES_THE_DMAERR_INTERRUPT, //= Enables the DMAERR interrupt.
}
7 => BTSERRENrw { //! BTSERR Interrupt Enable
0 => DISABLES_THE_BTSERR_INTERRUPT, //= Disables the BTSERR interrupt.
1 => ENABLES_THE_BTSERR_INTERRUPT, //= Enables the BTSERR interrupt.
}
},
0x90 => reg8 STAT { //! Status register
2 => ODD ro, //= no description available
3 => TXro { //! Transmit Indicator
0 => THE_MOST_RECENT_TRANSACTION_WAS_A_RECEIVE_OPERATION, //= The most recent transaction was a receive operation.
1 => THE_MOST_RECENT_TRANSACTION_WAS_A_TRANSMIT_OPERATION, //= The most recent transaction was a transmit operation.
}
4..7 => ENDP ro, //= no description available
},
0x94 => reg8 CTL { //! Control register
0 => USBENSOFENrw { //! USB Enable
0 => DISABLES_THE_USB_MODULE, //= Disables the USB Module.
1 => ENABLES_THE_USB_MODULE, //= Enables the USB Module.
}
1 => ODDRST rw, //= no description available
2 => RESUME rw, //= no description available
3 => HOSTMODEEN rw, //= no description available
4 => RESET rw, //= no description available
5 => TXSUSPENDTOKENBUSY rw, //= no description available
6 => SE0 rw, //= Live USB Single Ended Zero signal
7 => JSTATE rw, //= Live USB differential receiver JSTATE signal
},
0x98 => reg8 ADDR { //! Address register
0..6 => ADDR rw, //= USB Address
7 => LSEN rw, //= Low Speed Enable bit
},
0x9C => reg8 BDTPAGE1 { //! BDT Page Register 1
1..7 => BDTBA rw, //= no description available
},
0xA0 => reg8 FRMNUML { //! Frame Number Register Low
0..7 => FRM rw, //= no description available
},
0xA4 => reg8 FRMNUMH { //! Frame Number Register High
0..2 => FRM rw, //= no description available
},
0xA8 => reg8 TOKEN { //! Token register
0..3 => TOKENENDPT rw, //= no description available
4..7 => TOKENPIDrw { //! no description available
1 => E_0001, //= OUT Token. USB Module performs an OUT (TX) transaction.
9 => E_1001, //= IN Token. USB Module performs an In (RX) transaction.
13 => E_1101, //= SETUP Token. USB Module performs a SETUP (TX) transaction
}
},
0xAC => reg8 SOFTHLD { //! SOF Threshold Register
0..7 => CNT rw, //= no description available
},
0xB0 => reg8 BDTPAGE2 { //! BDT Page Register 2
0..7 => BDTBA rw, //= no description available
},
0xB4 => reg8 BDTPAGE3 { //! BDT Page Register 3
0..7 => BDTBA rw, //= no description available
},
0xC0 => reg8 ENDPT%s { //! Endpoint Control register
0 => EPHSHK rw, //= no description available
1 => EPSTALL rw, //= no description available
2 => EPTXEN rw, //= no description available
3 => EPRXEN rw, //= no description available
4 => EPCTLDIS rw, //= no description available
6 => RETRYDIS rw, //= no description available
7 => HOSTWOHUB rw, //= no description available
},
0x100 => reg8 USBCTRL { //! USB Control register
6 => PDErw { //! no description available
0 => WEAK_PULLDOWNS_ARE_DISABLED_ON_D+_AND_D_, //= Weak pulldowns are disabled on D+ and D-.
1 => WEAK_PULLDOWNS_ARE_ENABLED_ON_D+_AND_D_, //= Weak pulldowns are enabled on D+ and D-.
}
7 => SUSPrw { //! no description available
0 => USB_TRANSCEIVER_IS_NOT_IN_SUSPEND_STATE, //= USB transceiver is not in suspend state.
1 => USB_TRANSCEIVER_IS_IN_SUSPEND_STATE, //= USB transceiver is in suspend state.
}
},
0x104 => reg8 OBSERVE { //! USB OTG Observe register
4 => DMPDro { //! no description available
0 => D__PULLDOWN_DISABLED, //= D- pulldown disabled.
1 => D__PULLDOWN_ENABLED, //= D- pulldown enabled.
}
6 => DPPDro { //! no description available
0 => D+_PULLDOWN_DISABLED, //= D+ pulldown disabled.
1 => D+_PULLDOWN_ENABLED, //= D+ pulldown enabled.
}
7 => DPPUro { //! no description available
0 => D+_PULLUP_DISABLED, //= D+ pullup disabled.
1 => D+_PULLUP_ENABLED, //= D+ pullup enabled.
}
},
0x108 => reg8 CONTROL { //! USB OTG Control register
4 => DPPULLUPNONOTGrw { //! no description available
0 => DP_PULLUP_IN_NON_OTG_DEVICE_MODE_IS_NOT_ENABLED, //= DP Pullup in non-OTG device mode is not enabled.
1 => DP_PULLUP_IN_NON_OTG_DEVICE_MODE_IS_ENABLED, //= DP Pullup in non-OTG device mode is enabled.
}
},
0x10C => reg8 USBTRC0 { //! USB Transceiver Control Register 0
0 => USB_RESUME_INTro { //! USB Asynchronous Interrupt
0 => NO_INTERRUPT_WAS_GENERATED, //= No interrupt was generated.
1 => INTERRUPT_WAS_GENERATED_BECAUSE_OF_THE_USB_ASYNCHRONOUS_INTERRUPT, //= Interrupt was generated because of the USB asynchronous interrupt.
}
1 => SYNC_DETro { //! Synchronous USB Interrupt Detect
0 => SYNCHRONOUS_INTERRUPT_HAS_NOT_BEEN_DETECTED, //= Synchronous interrupt has not been detected.
1 => SYNCHRONOUS_INTERRUPT_HAS_BEEN_DETECTED, //= Synchronous interrupt has been detected.
}
5 => USBRESMENrw { //! Asynchronous Resume Interrupt Enable
0 => USB_ASYNCHRONOUS_WAKEUP_FROM_SUSPEND_MODE_DISABLED, //= USB asynchronous wakeup from suspend mode disabled.
1 => USB_ASYNCHRONOUS_WAKEUP_FROM_SUSPEND_MODE_ENABLED_THE_ASYNCHRONOUS_RESUME_INTERRUPT_DIFFERS_FROM_THE_SYNCHRONOUS_RESUME_INTERRUPT_IN_THAT_IT_ASYNCHRONOUSLY_DETECTS_K_STATE_USING_THE_UNFILTERED_STATE_OF_THE_D+_AND_D__PINS_THIS_INTERUPT_SHOULD_ONLY_BE_ENABLED_WHEN_THE_TRANSCEIVER_IS_SUSPENDED, //= USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interupt should only be enabled when the Transceiver is suspended.
}
7 => USBRESETwo { //! USB Reset
0 => NORMAL_USB_MODULE_OPERATION, //= Normal USB module operation.
1 => RETURNS_THE_USB_MODULE_TO_ITS_RESET_STATE, //= Returns the USB module to its reset state.
}
},
0x114 => reg8 USBFRMADJUST { //! Frame Adjust Register
0..7 => ADJ rw, //= Frame Adjustment
},
});
ioregs!(CMP0 @ 0x40073000 = { //! High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
0x00 => reg8 CR0 { //! CMP Control Register 0
0..1 => HYSTCTRrw { //! Comparator hard block hysteresis control
0 => LEVEL_0, //= Level 0
1 => LEVEL_1, //= Level 1
2 => LEVEL_2, //= Level 2
3 => LEVEL_3, //= Level 3
}
4..6 => FILTER_CNTrw { //! Filter Sample Count
0 => E_000, //= Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
1 => ONE_SAMPLE_MUST_AGREE_THE_COMPARATOR_OUTPUT_IS_SIMPLY_SAMPLED, //= One sample must agree. The comparator output is simply sampled.
2 => 2_CONSECUTIVE_SAMPLES_MUST_AGREE, //= 2 consecutive samples must agree.
3 => 3_CONSECUTIVE_SAMPLES_MUST_AGREE, //= 3 consecutive samples must agree.
4 => 4_CONSECUTIVE_SAMPLES_MUST_AGREE, //= 4 consecutive samples must agree.
5 => 5_CONSECUTIVE_SAMPLES_MUST_AGREE, //= 5 consecutive samples must agree.
6 => 6_CONSECUTIVE_SAMPLES_MUST_AGREE, //= 6 consecutive samples must agree.
7 => 7_CONSECUTIVE_SAMPLES_MUST_AGREE, //= 7 consecutive samples must agree.
}
},
0x01 => reg8 CR1 { //! CMP Control Register 1
0 => ENrw { //! Comparator Module Enable
0 => ANALOG_COMPARATOR_IS_DISABLED, //= Analog Comparator is disabled.
1 => ANALOG_COMPARATOR_IS_ENABLED, //= Analog Comparator is enabled.
}
1 => OPErw { //! Comparator Output Pin Enable
0 => CMPO_IS_NOT_AVAILABLE_ON_THE_ASSOCIATED_CMPO_OUTPUT_PIN_IF_THE_COMPARATOR_DOES_NOT_OWN_THE_PIN_THIS_FIELD_HAS_NO_EFFECT, //= CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
1 => E_1, //= CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
}
2 => COSrw { //! Comparator Output Select
0 => E_0, //= Set the filtered comparator output (CMPO) to equal COUT.
1 => E_1, //= Set the unfiltered comparator output (CMPO) to equal COUTA.
}
3 => INVrw { //! Comparator INVERT
0 => DOES_NOT_INVERT_THE_COMPARATOR_OUTPUT, //= Does not invert the comparator output.
1 => INVERTS_THE_COMPARATOR_OUTPUT, //= Inverts the comparator output.
}
4 => PMODErw { //! Power Mode Select
0 => E_0, //= Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
1 => E_1, //= High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
}
5 => TRIGMrw { //! Trigger Mode Enable
0 => TRIGGER_MODE_IS_DISABLED, //= Trigger mode is disabled.
1 => TRIGGER_MODE_IS_ENABLED, //= Trigger mode is enabled.
}
6 => WErw { //! Windowing Enable
0 => WINDOWING_MODE_IS_NOT_SELECTED, //= Windowing mode is not selected.
1 => WINDOWING_MODE_IS_SELECTED, //= Windowing mode is selected.
}
7 => SErw { //! Sample Enable
0 => SAMPLING_MODE_IS_NOT_SELECTED, //= Sampling mode is not selected.
1 => SAMPLING_MODE_IS_SELECTED, //= Sampling mode is selected.
}
},
0x02 => reg8 FPR { //! CMP Filter Period Register
0..7 => FILT_PER rw, //= Filter Sample Period
},
0x03 => reg8 SCR { //! CMP Status and Control Register
0 => COUT ro, //= Analog Comparator Output
1 => CFFrw { //! Analog Comparator Flag Falling
0 => FALLING_EDGE_ON_COUT_HAS_NOT_BEEN_DETECTED, //= Falling-edge on COUT has not been detected.
1 => FALLING_EDGE_ON_COUT_HAS_OCCURRED, //= Falling-edge on COUT has occurred.
}
2 => CFRrw { //! Analog Comparator Flag Rising
0 => RISING_EDGE_ON_COUT_HAS_NOT_BEEN_DETECTED, //= Rising-edge on COUT has not been detected.
1 => RISING_EDGE_ON_COUT_HAS_OCCURRED, //= Rising-edge on COUT has occurred.
}
3 => IEFrw { //! Comparator Interrupt Enable Falling
0 => INTERRUPT_IS_DISABLED, //= Interrupt is disabled.
1 => INTERRUPT_IS_ENABLED, //= Interrupt is enabled.
}
4 => IERrw { //! Comparator Interrupt Enable Rising
0 => INTERRUPT_IS_DISABLED, //= Interrupt is disabled.
1 => INTERRUPT_IS_ENABLED, //= Interrupt is enabled.
}
6 => DMAENrw { //! DMA Enable Control
0 => DMA_IS_DISABLED, //= DMA is disabled.
1 => DMA_IS_ENABLED, //= DMA is enabled.
}
},
0x04 => reg8 DACCR { //! DAC Control Register
0..5 => VOSEL rw, //= DAC Output Voltage Select
6 => VRSELrw { //! Supply Voltage Reference Source Select
0 => V_IS_SELECTED_AS_RESISTOR_LADDER_NETWORK_SUPPLY_REFERENCE_V_IN1_IN, //= V is selected as resistor ladder network supply reference V. in1 in
1 => V_IS_SELECTED_AS_RESISTOR_LADDER_NETWORK_SUPPLY_REFERENCE_V_IN2_IN, //= V is selected as resistor ladder network supply reference V. in2 in
}
7 => DACENrw { //! DAC Enable
0 => DAC_IS_DISABLED, //= DAC is disabled.
1 => DAC_IS_ENABLED, //= DAC is enabled.
}
},
0x05 => reg8 MUXCR { //! MUX Control Register
0..2 => MSELrw { //! Minus Input Mux Control
0 => IN0, //= IN0
1 => IN1, //= IN1
2 => IN2, //= IN2
3 => IN3, //= IN3
4 => IN4, //= IN4
5 => IN5, //= IN5
6 => IN6, //= IN6
7 => IN7, //= IN7
}
3..5 => PSELrw { //! Plus Input Mux Control
0 => IN0, //= IN0
1 => IN1, //= IN1
2 => IN2, //= IN2
3 => IN3, //= IN3
4 => IN4, //= IN4
5 => IN5, //= IN5
6 => IN6, //= IN6
7 => IN7, //= IN7
}
7 => PSTMrw { //! Pass Through Mode Enable
0 => PASS_THROUGH_MODE_IS_DISABLED, //= Pass Through Mode is disabled.
1 => PASS_THROUGH_MODE_IS_ENABLED, //= Pass Through Mode is enabled.
}
},
});
ioregs!(SPI0 @ 0x40076000 = { //! Serial Peripheral Interface
0x00 => reg8 C1 { //! SPI control register 1
0 => LSBFErw { //! LSB first (shifter direction)
0 => SPI_SERIAL_DATA_TRANSFERS_START_WITH_MOST_SIGNIFICANT_BIT, //= SPI serial data transfers start with most significant bit
1 => SPI_SERIAL_DATA_TRANSFERS_START_WITH_LEAST_SIGNIFICANT_BIT, //= SPI serial data transfers start with least significant bit
}
1 => SSOErw { //! Slave select output enable
0 => E_0, //= When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
1 => E_1, //= When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
}
2 => CPHArw { //! Clock phase
0 => FIRST_EDGE_ON_SPSCK_OCCURS_AT_THE_MIDDLE_OF_THE_FIRST_CYCLE_OF_A_DATA_TRANSFER, //= First edge on SPSCK occurs at the middle of the first cycle of a data transfer
1 => FIRST_EDGE_ON_SPSCK_OCCURS_AT_THE_START_OF_THE_FIRST_CYCLE_OF_A_DATA_TRANSFER, //= First edge on SPSCK occurs at the start of the first cycle of a data transfer
}
3 => CPOLrw { //! Clock polarity
0 => E_0, //= Active-high SPI clock (idles low)
1 => E_1, //= Active-low SPI clock (idles high)
}
4 => MSTRrw { //! Master/slave mode select
0 => SPI_MODULE_CONFIGURED_AS_A_SLAVE_SPI_DEVICE, //= SPI module configured as a slave SPI device
1 => SPI_MODULE_CONFIGURED_AS_A_MASTER_SPI_DEVICE, //= SPI module configured as a master SPI device
}
5 => SPTIErw { //! SPI transmit interrupt enable
0 => E_0, //= Interrupts from SPTEF inhibited (use polling)
1 => WHEN_SPTEF_IS_1_HARDWARE_INTERRUPT_REQUESTED, //= When SPTEF is 1, hardware interrupt requested
}
6 => SPErw { //! SPI system enable
0 => SPI_SYSTEM_INACTIVE, //= SPI system inactive
1 => SPI_SYSTEM_ENABLED, //= SPI system enabled
}
7 => SPIErw { //! SPI interrupt enable: for SPRF and MODF
0 => INTERRUPTS_FROM_SPRF_AND_MODF_ARE_INHIBITED_USE_POLLING, //= Interrupts from SPRF and MODF are inhibited-use polling
1 => REQUEST_A_HARDWARE_INTERRUPT_WHEN_SPRF_OR_MODF_IS_1, //= Request a hardware interrupt when SPRF or MODF is 1
}
},
0x01 => reg8 C2 { //! SPI control register 2
0 => SPC0rw { //! SPI pin control 0
0 => E_0, //= SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
1 => E_1, //= SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
}
1 => SPISWAIrw { //! SPI stop in wait mode
0 => SPI_CLOCKS_CONTINUE_TO_OPERATE_IN_WAIT_MODE, //= SPI clocks continue to operate in wait mode
1 => SPI_CLOCKS_STOP_WHEN_THE_MCU_ENTERS_WAIT_MODE, //= SPI clocks stop when the MCU enters wait mode
}
2 => RXDMAErw { //! Receive DMA enable
0 => DMA_REQUEST_FOR_RECEIVE_IS_DISABLED_AND_INTERRUPT_FROM_SPRF_IS_ALLOWED, //= DMA request for receive is disabled and interrupt from SPRF is allowed
1 => DMA_REQUEST_FOR_RECEIVE_IS_ENABLED_AND_INTERRUPT_FROM_SPRF_IS_DISABLED, //= DMA request for receive is enabled and interrupt from SPRF is disabled
}
3 => BIDIROErw { //! Bidirectional mode output enable
0 => OUTPUT_DRIVER_DISABLED_SO_SPI_DATA_IO_PIN_ACTS_AS_AN_INPUT, //= Output driver disabled so SPI data I/O pin acts as an input
1 => SPI_IO_PIN_ENABLED_AS_AN_OUTPUT, //= SPI I/O pin enabled as an output
}
4 => MODFENrw { //! Master mode-fault function enable
0 => MODE_FAULT_FUNCTION_DISABLED_MASTER_SS_PIN_REVERTS_TO_GENERAL_PURPOSE_IO_NOT_CONTROLLED_BY_SPI, //= Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 => MODE_FAULT_FUNCTION_ENABLED_MASTER_SS_PIN_ACTS_AS_THE_MODE_FAULT_INPUT_OR_THE_SLAVE_SELECT_OUTPUT, //= Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
}
5 => TXDMAErw { //! Transmit DMA enable
0 => DMA_REQUEST_FOR_TRANSMIT_IS_DISABLED_AND_INTERRUPT_FROM_SPTEF_IS_ALLOWED, //= DMA request for transmit is disabled and interrupt from SPTEF is allowed
1 => DMA_REQUEST_FOR_TRANSMIT_IS_ENABLED_AND_INTERRUPT_FROM_SPTEF_IS_DISABLED, //= DMA request for transmit is enabled and interrupt from SPTEF is disabled
}
7 => SPMIErw { //! SPI match interrupt enable
0 => E_0, //= Interrupts from SPMF inhibited (use polling)
1 => WHEN_SPMF_IS_1_REQUESTS_A_HARDWARE_INTERRUPT, //= When SPMF is 1, requests a hardware interrupt
}
},
0x02 => reg8 BR { //! SPI baud rate register
0..3 => SPRrw { //! SPI baud rate divisor
0 => BAUD_RATE_DIVISOR_IS_2, //= Baud rate divisor is 2
1 => BAUD_RATE_DIVISOR_IS_4, //= Baud rate divisor is 4
2 => BAUD_RATE_DIVISOR_IS_8, //= Baud rate divisor is 8
3 => BAUD_RATE_DIVISOR_IS_16, //= Baud rate divisor is 16
4 => BAUD_RATE_DIVISOR_IS_32, //= Baud rate divisor is 32
5 => BAUD_RATE_DIVISOR_IS_64, //= Baud rate divisor is 64
6 => BAUD_RATE_DIVISOR_IS_128, //= Baud rate divisor is 128
7 => BAUD_RATE_DIVISOR_IS_256, //= Baud rate divisor is 256
8 => BAUD_RATE_DIVISOR_IS_512, //= Baud rate divisor is 512
}
4..6 => SPPRrw { //! SPI baud rate prescale divisor
0 => BAUD_RATE_PRESCALER_DIVISOR_IS_1, //= Baud rate prescaler divisor is 1
1 => BAUD_RATE_PRESCALER_DIVISOR_IS_2, //= Baud rate prescaler divisor is 2
2 => BAUD_RATE_PRESCALER_DIVISOR_IS_3, //= Baud rate prescaler divisor is 3
3 => BAUD_RATE_PRESCALER_DIVISOR_IS_4, //= Baud rate prescaler divisor is 4
4 => BAUD_RATE_PRESCALER_DIVISOR_IS_5, //= Baud rate prescaler divisor is 5
5 => BAUD_RATE_PRESCALER_DIVISOR_IS_6, //= Baud rate prescaler divisor is 6
6 => BAUD_RATE_PRESCALER_DIVISOR_IS_7, //= Baud rate prescaler divisor is 7
7 => BAUD_RATE_PRESCALER_DIVISOR_IS_8, //= Baud rate prescaler divisor is 8
}
},
0x03 => reg8 S { //! SPI status register
4 => MODFro { //! Master mode fault flag
0 => NO_MODE_FAULT_ERROR, //= No mode fault error
1 => MODE_FAULT_ERROR_DETECTED, //= Mode fault error detected
}
5 => SPTEFro { //! SPI transmit buffer empty flag
0 => SPI_TRANSMIT_BUFFER_NOT_EMPTY, //= SPI transmit buffer not empty
1 => SPI_TRANSMIT_BUFFER_EMPTY, //= SPI transmit buffer empty
}
6 => SPMFrw { //! SPI match flag
0 => VALUE_IN_THE_RECEIVE_DATA_BUFFER_DOES_NOT_MATCH_THE_VALUE_IN_THE_M_REGISTER, //= Value in the receive data buffer does not match the value in the M register
1 => VALUE_IN_THE_RECEIVE_DATA_BUFFER_MATCHES_THE_VALUE_IN_THE_M_REGISTER, //= Value in the receive data buffer matches the value in the M register
}
7 => SPRFro { //! SPI read buffer full flag
0 => NO_DATA_AVAILABLE_IN_THE_RECEIVE_DATA_BUFFER, //= No data available in the receive data buffer
1 => DATA_AVAILABLE_IN_THE_RECEIVE_DATA_BUFFER, //= Data available in the receive data buffer
}
},
0x05 => reg8 D { //! SPI data register
0..7 => Bits rw, //= Data (low byte)
},
0x07 => reg8 M { //! SPI match register
0..7 => Bits rw, //= Hardware compare value (low byte)
},
});
ioregs!(SPI1 @ 0x40077000 = { //! Serial Peripheral Interface
0x00 => reg8 C1 { //! SPI control register 1
0 => LSBFErw { //! LSB first (shifter direction)
0 => SPI_SERIAL_DATA_TRANSFERS_START_WITH_MOST_SIGNIFICANT_BIT, //= SPI serial data transfers start with most significant bit
1 => SPI_SERIAL_DATA_TRANSFERS_START_WITH_LEAST_SIGNIFICANT_BIT, //= SPI serial data transfers start with least significant bit
}
1 => SSOErw { //! Slave select output enable
0 => E_0, //= When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
1 => E_1, //= When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
}
2 => CPHArw { //! Clock phase
0 => FIRST_EDGE_ON_SPSCK_OCCURS_AT_THE_MIDDLE_OF_THE_FIRST_CYCLE_OF_A_DATA_TRANSFER, //= First edge on SPSCK occurs at the middle of the first cycle of a data transfer
1 => FIRST_EDGE_ON_SPSCK_OCCURS_AT_THE_START_OF_THE_FIRST_CYCLE_OF_A_DATA_TRANSFER, //= First edge on SPSCK occurs at the start of the first cycle of a data transfer
}
3 => CPOLrw { //! Clock polarity
0 => E_0, //= Active-high SPI clock (idles low)
1 => E_1, //= Active-low SPI clock (idles high)
}
4 => MSTRrw { //! Master/slave mode select
0 => SPI_MODULE_CONFIGURED_AS_A_SLAVE_SPI_DEVICE, //= SPI module configured as a slave SPI device
1 => SPI_MODULE_CONFIGURED_AS_A_MASTER_SPI_DEVICE, //= SPI module configured as a master SPI device
}
5 => SPTIErw { //! SPI transmit interrupt enable
0 => E_0, //= Interrupts from SPTEF inhibited (use polling)
1 => WHEN_SPTEF_IS_1_HARDWARE_INTERRUPT_REQUESTED, //= When SPTEF is 1, hardware interrupt requested
}
6 => SPErw { //! SPI system enable
0 => SPI_SYSTEM_INACTIVE, //= SPI system inactive
1 => SPI_SYSTEM_ENABLED, //= SPI system enabled
}
7 => SPIErw { //! SPI interrupt enable: for SPRF and MODF
0 => INTERRUPTS_FROM_SPRF_AND_MODF_ARE_INHIBITED_USE_POLLING, //= Interrupts from SPRF and MODF are inhibited-use polling
1 => REQUEST_A_HARDWARE_INTERRUPT_WHEN_SPRF_OR_MODF_IS_1, //= Request a hardware interrupt when SPRF or MODF is 1
}
},
0x01 => reg8 C2 { //! SPI control register 2
0 => SPC0rw { //! SPI pin control 0
0 => E_0, //= SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
1 => E_1, //= SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
}
1 => SPISWAIrw { //! SPI stop in wait mode
0 => SPI_CLOCKS_CONTINUE_TO_OPERATE_IN_WAIT_MODE, //= SPI clocks continue to operate in wait mode
1 => SPI_CLOCKS_STOP_WHEN_THE_MCU_ENTERS_WAIT_MODE, //= SPI clocks stop when the MCU enters wait mode
}
2 => RXDMAErw { //! Receive DMA enable
0 => DMA_REQUEST_FOR_RECEIVE_IS_DISABLED_AND_INTERRUPT_FROM_SPRF_IS_ALLOWED, //= DMA request for receive is disabled and interrupt from SPRF is allowed
1 => DMA_REQUEST_FOR_RECEIVE_IS_ENABLED_AND_INTERRUPT_FROM_SPRF_IS_DISABLED, //= DMA request for receive is enabled and interrupt from SPRF is disabled
}
3 => BIDIROErw { //! Bidirectional mode output enable
0 => OUTPUT_DRIVER_DISABLED_SO_SPI_DATA_IO_PIN_ACTS_AS_AN_INPUT, //= Output driver disabled so SPI data I/O pin acts as an input
1 => SPI_IO_PIN_ENABLED_AS_AN_OUTPUT, //= SPI I/O pin enabled as an output
}
4 => MODFENrw { //! Master mode-fault function enable
0 => MODE_FAULT_FUNCTION_DISABLED_MASTER_SS_PIN_REVERTS_TO_GENERAL_PURPOSE_IO_NOT_CONTROLLED_BY_SPI, //= Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 => MODE_FAULT_FUNCTION_ENABLED_MASTER_SS_PIN_ACTS_AS_THE_MODE_FAULT_INPUT_OR_THE_SLAVE_SELECT_OUTPUT, //= Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
}
5 => TXDMAErw { //! Transmit DMA enable
0 => DMA_REQUEST_FOR_TRANSMIT_IS_DISABLED_AND_INTERRUPT_FROM_SPTEF_IS_ALLOWED, //= DMA request for transmit is disabled and interrupt from SPTEF is allowed
1 => DMA_REQUEST_FOR_TRANSMIT_IS_ENABLED_AND_INTERRUPT_FROM_SPTEF_IS_DISABLED, //= DMA request for transmit is enabled and interrupt from SPTEF is disabled
}
7 => SPMIErw { //! SPI match interrupt enable
0 => E_0, //= Interrupts from SPMF inhibited (use polling)
1 => WHEN_SPMF_IS_1_REQUESTS_A_HARDWARE_INTERRUPT, //= When SPMF is 1, requests a hardware interrupt
}
},
0x02 => reg8 BR { //! SPI baud rate register
0..3 => SPRrw { //! SPI baud rate divisor
0 => BAUD_RATE_DIVISOR_IS_2, //= Baud rate divisor is 2
1 => BAUD_RATE_DIVISOR_IS_4, //= Baud rate divisor is 4
2 => BAUD_RATE_DIVISOR_IS_8, //= Baud rate divisor is 8
3 => BAUD_RATE_DIVISOR_IS_16, //= Baud rate divisor is 16
4 => BAUD_RATE_DIVISOR_IS_32, //= Baud rate divisor is 32
5 => BAUD_RATE_DIVISOR_IS_64, //= Baud rate divisor is 64
6 => BAUD_RATE_DIVISOR_IS_128, //= Baud rate divisor is 128
7 => BAUD_RATE_DIVISOR_IS_256, //= Baud rate divisor is 256
8 => BAUD_RATE_DIVISOR_IS_512, //= Baud rate divisor is 512
}
4..6 => SPPRrw { //! SPI baud rate prescale divisor
0 => BAUD_RATE_PRESCALER_DIVISOR_IS_1, //= Baud rate prescaler divisor is 1
1 => BAUD_RATE_PRESCALER_DIVISOR_IS_2, //= Baud rate prescaler divisor is 2
2 => BAUD_RATE_PRESCALER_DIVISOR_IS_3, //= Baud rate prescaler divisor is 3
3 => BAUD_RATE_PRESCALER_DIVISOR_IS_4, //= Baud rate prescaler divisor is 4
4 => BAUD_RATE_PRESCALER_DIVISOR_IS_5, //= Baud rate prescaler divisor is 5
5 => BAUD_RATE_PRESCALER_DIVISOR_IS_6, //= Baud rate prescaler divisor is 6
6 => BAUD_RATE_PRESCALER_DIVISOR_IS_7, //= Baud rate prescaler divisor is 7
7 => BAUD_RATE_PRESCALER_DIVISOR_IS_8, //= Baud rate prescaler divisor is 8
}
},
0x03 => reg8 S { //! SPI status register
4 => MODFro { //! Master mode fault flag
0 => NO_MODE_FAULT_ERROR, //= No mode fault error
1 => MODE_FAULT_ERROR_DETECTED, //= Mode fault error detected
}
5 => SPTEFro { //! SPI transmit buffer empty flag
0 => SPI_TRANSMIT_BUFFER_NOT_EMPTY, //= SPI transmit buffer not empty
1 => SPI_TRANSMIT_BUFFER_EMPTY, //= SPI transmit buffer empty
}
6 => SPMFrw { //! SPI match flag
0 => VALUE_IN_THE_RECEIVE_DATA_BUFFER_DOES_NOT_MATCH_THE_VALUE_IN_THE_M_REGISTER, //= Value in the receive data buffer does not match the value in the M register
1 => VALUE_IN_THE_RECEIVE_DATA_BUFFER_MATCHES_THE_VALUE_IN_THE_M_REGISTER, //= Value in the receive data buffer matches the value in the M register
}
7 => SPRFro { //! SPI read buffer full flag
0 => NO_DATA_AVAILABLE_IN_THE_RECEIVE_DATA_BUFFER, //= No data available in the receive data buffer
1 => DATA_AVAILABLE_IN_THE_RECEIVE_DATA_BUFFER, //= Data available in the receive data buffer
}
},
0x05 => reg8 D { //! SPI data register
0..7 => Bits rw, //= Data (low byte)
},
0x07 => reg8 M { //! SPI match register
0..7 => Bits rw, //= Hardware compare value (low byte)
},
});
ioregs!(LLWU @ 0x4007C000 = { //! Low leakage wakeup unit
0x00 => reg8 PE1 { //! LLWU Pin Enable 1 register
0..1 => WUPE0rw { //! Wakeup Pin Enable For LLWU_P0
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
2..3 => WUPE1rw { //! Wakeup Pin Enable For LLWU_P1
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
4..5 => WUPE2rw { //! Wakeup Pin Enable For LLWU_P2
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
6..7 => WUPE3rw { //! Wakeup Pin Enable For LLWU_P3
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
},
0x01 => reg8 PE2 { //! LLWU Pin Enable 2 register
0..1 => WUPE4rw { //! Wakeup Pin Enable For LLWU_P4
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
2..3 => WUPE5rw { //! Wakeup Pin Enable For LLWU_P5
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
4..5 => WUPE6rw { //! Wakeup Pin Enable For LLWU_P6
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
6..7 => WUPE7rw { //! Wakeup Pin Enable For LLWU_P7
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
},
0x02 => reg8 PE3 { //! LLWU Pin Enable 3 register
0..1 => WUPE8rw { //! Wakeup Pin Enable For LLWU_P8
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
2..3 => WUPE9rw { //! Wakeup Pin Enable For LLWU_P9
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
4..5 => WUPE10rw { //! Wakeup Pin Enable For LLWU_P10
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
6..7 => WUPE11rw { //! Wakeup Pin Enable For LLWU_P11
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
},
0x03 => reg8 PE4 { //! LLWU Pin Enable 4 register
0..1 => WUPE12rw { //! Wakeup Pin Enable For LLWU_P12
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
2..3 => WUPE13rw { //! Wakeup Pin Enable For LLWU_P13
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
4..5 => WUPE14rw { //! Wakeup Pin Enable For LLWU_P14
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
6..7 => WUPE15rw { //! Wakeup Pin Enable For LLWU_P15
0 => EXTERNAL_INPUT_PIN_DISABLED_AS_WAKEUP_INPUT, //= External input pin disabled as wakeup input
1 => EXTERNAL_INPUT_PIN_ENABLED_WITH_RISING_EDGE_DETECTION, //= External input pin enabled with rising edge detection
2 => EXTERNAL_INPUT_PIN_ENABLED_WITH_FALLING_EDGE_DETECTION, //= External input pin enabled with falling edge detection
3 => EXTERNAL_INPUT_PIN_ENABLED_WITH_ANY_CHANGE_DETECTION, //= External input pin enabled with any change detection
}
},
0x04 => reg8 ME { //! LLWU Module Enable register
0 => WUME0rw { //! Wakeup Module Enable For Module 0
0 => INTERNAL_MODULE_FLAG_NOT_USED_AS_WAKEUP_SOURCE, //= Internal module flag not used as wakeup source
1 => INTERNAL_MODULE_FLAG_USED_AS_WAKEUP_SOURCE, //= Internal module flag used as wakeup source
}
1 => WUME1rw { //! Wakeup Module Enable for Module 1
0 => INTERNAL_MODULE_FLAG_NOT_USED_AS_WAKEUP_SOURCE, //= Internal module flag not used as wakeup source
1 => INTERNAL_MODULE_FLAG_USED_AS_WAKEUP_SOURCE, //= Internal module flag used as wakeup source
}
2 => WUME2rw { //! Wakeup Module Enable For Module 2
0 => INTERNAL_MODULE_FLAG_NOT_USED_AS_WAKEUP_SOURCE, //= Internal module flag not used as wakeup source
1 => INTERNAL_MODULE_FLAG_USED_AS_WAKEUP_SOURCE, //= Internal module flag used as wakeup source
}
3 => WUME3rw { //! Wakeup Module Enable For Module 3
0 => INTERNAL_MODULE_FLAG_NOT_USED_AS_WAKEUP_SOURCE, //= Internal module flag not used as wakeup source
1 => INTERNAL_MODULE_FLAG_USED_AS_WAKEUP_SOURCE, //= Internal module flag used as wakeup source
}
4 => WUME4rw { //! Wakeup Module Enable For Module 4
0 => INTERNAL_MODULE_FLAG_NOT_USED_AS_WAKEUP_SOURCE, //= Internal module flag not used as wakeup source
1 => INTERNAL_MODULE_FLAG_USED_AS_WAKEUP_SOURCE, //= Internal module flag used as wakeup source
}
5 => WUME5rw { //! Wakeup Module Enable For Module 5
0 => INTERNAL_MODULE_FLAG_NOT_USED_AS_WAKEUP_SOURCE, //= Internal module flag not used as wakeup source
1 => INTERNAL_MODULE_FLAG_USED_AS_WAKEUP_SOURCE, //= Internal module flag used as wakeup source
}
6 => WUME6rw { //! Wakeup Module Enable For Module 6
0 => INTERNAL_MODULE_FLAG_NOT_USED_AS_WAKEUP_SOURCE, //= Internal module flag not used as wakeup source
1 => INTERNAL_MODULE_FLAG_USED_AS_WAKEUP_SOURCE, //= Internal module flag used as wakeup source
}
7 => WUME7rw { //! Wakeup Module Enable For Module 7
0 => INTERNAL_MODULE_FLAG_NOT_USED_AS_WAKEUP_SOURCE, //= Internal module flag not used as wakeup source
1 => INTERNAL_MODULE_FLAG_USED_AS_WAKEUP_SOURCE, //= Internal module flag used as wakeup source
}
},
0x05 => reg8 F1 { //! LLWU Flag 1 register
0 => WUF0rw { //! Wakeup Flag For LLWU_P0
0 => LLWU_P0_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P0 input was not a wakeup source
1 => LLWU_P0_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P0 input was a wakeup source
}
1 => WUF1rw { //! Wakeup Flag For LLWU_P1
0 => LLWU_P1_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P1 input was not a wakeup source
1 => LLWU_P1_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P1 input was a wakeup source
}
2 => WUF2rw { //! Wakeup Flag For LLWU_P2
0 => LLWU_P2_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P2 input was not a wakeup source
1 => LLWU_P2_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P2 input was a wakeup source
}
3 => WUF3rw { //! Wakeup Flag For LLWU_P3
0 => LLWU_P3_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P3 input was not a wakeup source
1 => LLWU_P3_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P3 input was a wakeup source
}
4 => WUF4rw { //! Wakeup Flag For LLWU_P4
0 => LLWU_P4_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P4 input was not a wakeup source
1 => LLWU_P4_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P4 input was a wakeup source
}
5 => WUF5rw { //! Wakeup Flag For LLWU_P5
0 => LLWU_P5_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P5 input was not a wakeup source
1 => LLWU_P5_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P5 input was a wakeup source
}
6 => WUF6rw { //! Wakeup Flag For LLWU_P6
0 => LLWU_P6_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P6 input was not a wakeup source
1 => LLWU_P6_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P6 input was a wakeup source
}
7 => WUF7rw { //! Wakeup Flag For LLWU_P7
0 => LLWU_P7_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P7 input was not a wakeup source
1 => LLWU_P7_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P7 input was a wakeup source
}
},
0x06 => reg8 F2 { //! LLWU Flag 2 register
0 => WUF8rw { //! Wakeup Flag For LLWU_P8
0 => LLWU_P8_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P8 input was not a wakeup source
1 => LLWU_P8_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P8 input was a wakeup source
}
1 => WUF9rw { //! Wakeup Flag For LLWU_P9
0 => LLWU_P9_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P9 input was not a wakeup source
1 => LLWU_P9_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P9 input was a wakeup source
}
2 => WUF10rw { //! Wakeup Flag For LLWU_P10
0 => LLWU_P10_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P10 input was not a wakeup source
1 => LLWU_P10_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P10 input was a wakeup source
}
3 => WUF11rw { //! Wakeup Flag For LLWU_P11
0 => LLWU_P11_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P11 input was not a wakeup source
1 => LLWU_P11_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P11 input was a wakeup source
}
4 => WUF12rw { //! Wakeup Flag For LLWU_P12
0 => LLWU_P12_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P12 input was not a wakeup source
1 => LLWU_P12_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P12 input was a wakeup source
}
5 => WUF13rw { //! Wakeup Flag For LLWU_P13
0 => LLWU_P13_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P13 input was not a wakeup source
1 => LLWU_P13_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P13 input was a wakeup source
}
6 => WUF14rw { //! Wakeup Flag For LLWU_P14
0 => LLWU_P14_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P14 input was not a wakeup source
1 => LLWU_P14_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P14 input was a wakeup source
}
7 => WUF15rw { //! Wakeup Flag For LLWU_P15
0 => LLWU_P15_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= LLWU_P15 input was not a wakeup source
1 => LLWU_P15_INPUT_WAS_A_WAKEUP_SOURCE, //= LLWU_P15 input was a wakeup source
}
},
0x07 => reg8 F3 { //! LLWU Flag 3 register
0 => MWUF0ro { //! Wakeup flag For module 0
0 => MODULE_0_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= Module 0 input was not a wakeup source
1 => MODULE_0_INPUT_WAS_A_WAKEUP_SOURCE, //= Module 0 input was a wakeup source
}
1 => MWUF1ro { //! Wakeup flag For module 1
0 => MODULE_1_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= Module 1 input was not a wakeup source
1 => MODULE_1_INPUT_WAS_A_WAKEUP_SOURCE, //= Module 1 input was a wakeup source
}
2 => MWUF2ro { //! Wakeup flag For module 2
0 => MODULE_2_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= Module 2 input was not a wakeup source
1 => MODULE_2_INPUT_WAS_A_WAKEUP_SOURCE, //= Module 2 input was a wakeup source
}
3 => MWUF3ro { //! Wakeup flag For module 3
0 => MODULE_3_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= Module 3 input was not a wakeup source
1 => MODULE_3_INPUT_WAS_A_WAKEUP_SOURCE, //= Module 3 input was a wakeup source
}
4 => MWUF4ro { //! Wakeup flag For module 4
0 => MODULE_4_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= Module 4 input was not a wakeup source
1 => MODULE_4_INPUT_WAS_A_WAKEUP_SOURCE, //= Module 4 input was a wakeup source
}
5 => MWUF5ro { //! Wakeup flag For module 5
0 => MODULE_5_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= Module 5 input was not a wakeup source
1 => MODULE_5_INPUT_WAS_A_WAKEUP_SOURCE, //= Module 5 input was a wakeup source
}
6 => MWUF6ro { //! Wakeup flag For module 6
0 => MODULE_6_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= Module 6 input was not a wakeup source
1 => MODULE_6_INPUT_WAS_A_WAKEUP_SOURCE, //= Module 6 input was a wakeup source
}
7 => MWUF7ro { //! Wakeup flag For module 7
0 => MODULE_7_INPUT_WAS_NOT_A_WAKEUP_SOURCE, //= Module 7 input was not a wakeup source
1 => MODULE_7_INPUT_WAS_A_WAKEUP_SOURCE, //= Module 7 input was a wakeup source
}
},
0x08 => reg8 FILT1 { //! LLWU Pin Filter 1 register
0..3 => FILTSELrw { //! Filter Pin Select
0 => SELECT_LLWU_P0_FOR_FILTER, //= Select LLWU_P0 for filter
15 => SELECT_LLWU_P15_FOR_FILTER, //= Select LLWU_P15 for filter
}
5..6 => FILTErw { //! Digital Filter On External Pin
0 => FILTER_DISABLED, //= Filter disabled
1 => FILTER_POSEDGE_DETECT_ENABLED, //= Filter posedge detect enabled
2 => FILTER_NEGEDGE_DETECT_ENABLED, //= Filter negedge detect enabled
3 => FILTER_ANY_EDGE_DETECT_ENABLED, //= Filter any edge detect enabled
}
7 => FILTFrw { //! Filter Detect Flag
0 => PIN_FILTER_1_WAS_NOT_A_WAKEUP_SOURCE, //= Pin Filter 1 was not a wakeup source
1 => PIN_FILTER_1_WAS_A_WAKEUP_SOURCE, //= Pin Filter 1 was a wakeup source
}
},
0x09 => reg8 FILT2 { //! LLWU Pin Filter 2 register
0..3 => FILTSELrw { //! Filter Pin Select
0 => SELECT_LLWU_P0_FOR_FILTER, //= Select LLWU_P0 for filter
15 => SELECT_LLWU_P15_FOR_FILTER, //= Select LLWU_P15 for filter
}
5..6 => FILTErw { //! Digital Filter On External Pin
0 => FILTER_DISABLED, //= Filter disabled
1 => FILTER_POSEDGE_DETECT_ENABLED, //= Filter posedge detect enabled
2 => FILTER_NEGEDGE_DETECT_ENABLED, //= Filter negedge detect enabled
3 => FILTER_ANY_EDGE_DETECT_ENABLED, //= Filter any edge detect enabled
}
7 => FILTFrw { //! Filter Detect Flag
0 => PIN_FILTER_2_WAS_NOT_A_WAKEUP_SOURCE, //= Pin Filter 2 was not a wakeup source
1 => PIN_FILTER_2_WAS_A_WAKEUP_SOURCE, //= Pin Filter 2 was a wakeup source
}
},
});
ioregs!(PMC @ 0x4007D000 = { //! Power Management Controller
0x00 => reg8 LVDSC1 { //! Low Voltage Detect Status And Control 1 register
0..1 => LVDVrw { //! Low-Voltage Detect Voltage Select
0 => E_00, //= Low trip point selected (V LVD = V LVDL )
1 => E_01, //= High trip point selected (V LVD = V LVDH )
}
4 => LVDRErw { //! Low-Voltage Detect Reset Enable
0 => LVDF_DOES_NOT_GENERATE_HARDWARE_RESETS, //= LVDF does not generate hardware resets
1 => E_1, //= Force an MCU reset when LVDF = 1
}
5 => LVDIErw { //! Low-Voltage Detect Interrupt Enable
0 => E_0, //= Hardware interrupt disabled (use polling)
1 => E_1, //= Request a hardware interrupt when LVDF = 1
}
6 => LVDACK wo, //= Low-Voltage Detect Acknowledge
7 => LVDFro { //! Low-Voltage Detect Flag
0 => LOW_VOLTAGE_EVENT_NOT_DETECTED, //= Low-voltage event not detected
1 => LOW_VOLTAGE_EVENT_DETECTED, //= Low-voltage event detected
}
},
0x01 => reg8 LVDSC2 { //! Low Voltage Detect Status And Control 2 register
0..1 => LVWVrw { //! Low-Voltage Warning Voltage Select
0 => E_00, //= Low trip point selected (VLVW = VLVW1)
1 => E_01, //= Mid 1 trip point selected (VLVW = VLVW2)
2 => E_10, //= Mid 2 trip point selected (VLVW = VLVW3)
3 => E_11, //= High trip point selected (VLVW = VLVW4)
}
5 => LVWIErw { //! Low-Voltage Warning Interrupt Enable
0 => E_0, //= Hardware interrupt disabled (use polling)
1 => E_1, //= Request a hardware interrupt when LVWF = 1
}
6 => LVWACK wo, //= Low-Voltage Warning Acknowledge
7 => LVWFro { //! Low-Voltage Warning Flag
0 => LOW_VOLTAGE_WARNING_EVENT_NOT_DETECTED, //= Low-voltage warning event not detected
1 => LOW_VOLTAGE_WARNING_EVENT_DETECTED, //= Low-voltage warning event detected
}
},
0x02 => reg8 REGSC { //! Regulator Status And Control register
0 => BGBErw { //! Bandgap Buffer Enable
0 => BANDGAP_BUFFER_NOT_ENABLED, //= Bandgap buffer not enabled
1 => BANDGAP_BUFFER_ENABLED, //= Bandgap buffer enabled
}
2 => REGONSro { //! Regulator In Run Regulation Status
0 => REGULATOR_IS_IN_STOP_REGULATION_OR_IN_TRANSITION_TOFROM_IT, //= Regulator is in stop regulation or in transition to/from it
1 => REGULATOR_IS_IN_RUN_REGULATION, //= Regulator is in run regulation
}
3 => ACKISOrw { //! Acknowledge Isolation
0 => PERIPHERALS_AND_IO_PADS_ARE_IN_NORMAL_RUN_STATE, //= Peripherals and I/O pads are in normal run state
1 => CERTAIN_PERIPHERALS_AND_IO_PADS_ARE_IN_AN_ISOLATED_AND_LATCHED_STATE, //= Certain peripherals and I/O pads are in an isolated and latched state
}
4 => BGENrw { //! Bandgap Enable In VLPx Operation
0 => BANDGAP_VOLTAGE_REFERENCE_IS_DISABLED_IN_VLPX__LLS__AND_VLLSX_MODES, //= Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes
1 => BANDGAP_VOLTAGE_REFERENCE_IS_ENABLED_IN_VLPX__LLS__AND_VLLSX_MODES, //= Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes
}
},
});
ioregs!(SMC @ 0x4007E000 = { //! System Mode Controller
0x00 => reg8 PMPROT { //! Power Mode Protection register
1 => AVLLSrw { //! Allow Very-Low-Leakage Stop Mode
0 => ANY_VLLSX_MODE_IS_NOT_ALLOWED, //= Any VLLSx mode is not allowed
1 => ANY_VLLSX_MODE_IS_ALLOWED, //= Any VLLSx mode is allowed
}
3 => ALLSrw { //! Allow Low-Leakage Stop Mode
0 => LLS_IS_NOT_ALLOWED, //= LLS is not allowed
1 => LLS_IS_ALLOWED, //= LLS is allowed
}
5 => AVLPrw { //! Allow Very-Low-Power Modes
0 => VLPR_VLPW_AND_VLPS_ARE_NOT_ALLOWED, //= VLPR, VLPW and VLPS are not allowed
1 => VLPR_VLPW_AND_VLPS_ARE_ALLOWED, //= VLPR, VLPW and VLPS are allowed
}
},
0x01 => reg8 PMCTRL { //! Power Mode Control register
0..2 => STOPMrw { //! Stop Mode Control
0 => E_000, //= Normal Stop (STOP)
2 => E_010, //= Very-Low-Power Stop (VLPS)
3 => E_011, //= Low-Leakage Stop (LLS)
4 => E_100, //= Very-Low-Leakage Stop (VLLSx)
6 => RESEVED, //= Reseved
}
3 => STOPAro { //! Stop Aborted
0 => THE_PREVIOUS_STOP_MODE_ENTRY_WAS_SUCCESSSFUL, //= The previous stop mode entry was successsful.
1 => THE_PREVIOUS_STOP_MODE_ENTRY_WAS_ABORTED, //= The previous stop mode entry was aborted.
}
5..6 => RUNMrw { //! Run Mode Control
0 => E_00, //= Normal Run mode (RUN)
2 => E_10, //= Very-Low-Power Run mode (VLPR)
}
},
0x02 => reg8 STOPCTRL { //! Stop Control Register
0..2 => VLLSMrw { //! VLLS Mode Control.
0 => VLLS0, //= VLLS0
1 => VLLS1, //= VLLS1
3 => VLLS3, //= VLLS3
}
5 => PORPOrw { //! POR Power Option
0 => POR_DETECT_CIRCUIT_IS_ENABLED_IN_VLLS0, //= POR detect circuit is enabled in VLLS0
1 => POR_DETECT_CIRCUIT_IS_DISABLED_IN_VLLS0, //= POR detect circuit is disabled in VLLS0
}
6..7 => PSTOPOrw { //! Partial Stop Option
0 => STOP___NORMAL_STOP_MODE, //= STOP - Normal Stop mode
1 => PSTOP1___PARTIAL_STOP_WITH_BOTH_SYSTEM_AND_BUS_CLOCKS_DISABLED, //= PSTOP1 - Partial Stop with both system and bus clocks disabled
2 => PSTOP2___PARTIAL_STOP_WITH_SYSTEM_CLOCK_DISABLED_AND_BUS_CLOCK_ENABLED, //= PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
}
},
0x03 => reg8 PMSTAT { //! Power Mode Status register
0..6 => PMSTAT ro, //= no description available
},
});
ioregs!(RCM @ 0x4007F000 = { //! Reset Control Module
0x00 => reg8 SRS0 { //! System Reset Status Register 0
0 => WAKEUPro { //! Low Leakage Wakeup Reset
0 => RESET_NOT_CAUSED_BY_LLWU_MODULE_WAKEUP_SOURCE, //= Reset not caused by LLWU module wakeup source
1 => RESET_CAUSED_BY_LLWU_MODULE_WAKEUP_SOURCE, //= Reset caused by LLWU module wakeup source
}
1 => LVDro { //! Low-Voltage Detect Reset
0 => RESET_NOT_CAUSED_BY_LVD_TRIP_OR_POR, //= Reset not caused by LVD trip or POR
1 => RESET_CAUSED_BY_LVD_TRIP_OR_POR, //= Reset caused by LVD trip or POR
}
2 => LOCro { //! Loss-of-Clock Reset
0 => RESET_NOT_CAUSED_BY_A_LOSS_OF_EXTERNAL_CLOCK, //= Reset not caused by a loss of external clock.
1 => RESET_CAUSED_BY_A_LOSS_OF_EXTERNAL_CLOCK, //= Reset caused by a loss of external clock.
}
3 => LOLro { //! Loss-of-Lock Reset
0 => RESET_NOT_CAUSED_BY_A_LOSS_OF_LOCK_IN_THE_PLL, //= Reset not caused by a loss of lock in the PLL
1 => RESET_CAUSED_BY_A_LOSS_OF_LOCK_IN_THE_PLL, //= Reset caused by a loss of lock in the PLL
}
5 => WDOGro { //! Watchdog
0 => RESET_NOT_CAUSED_BY_WATCHDOG_TIMEOUT, //= Reset not caused by watchdog timeout
1 => RESET_CAUSED_BY_WATCHDOG_TIMEOUT, //= Reset caused by watchdog timeout
}
6 => PINro { //! External Reset Pin
0 => RESET_NOT_CAUSED_BY_EXTERNAL_RESET_PIN, //= Reset not caused by external reset pin
1 => RESET_CAUSED_BY_EXTERNAL_RESET_PIN, //= Reset caused by external reset pin
}
7 => PORro { //! Power-On Reset
0 => RESET_NOT_CAUSED_BY_POR, //= Reset not caused by POR
1 => RESET_CAUSED_BY_POR, //= Reset caused by POR
}
},
0x01 => reg8 SRS1 { //! System Reset Status Register 1
1 => LOCKUPro { //! Core Lockup
0 => RESET_NOT_CAUSED_BY_CORE_LOCKUP_EVENT, //= Reset not caused by core LOCKUP event
1 => RESET_CAUSED_BY_CORE_LOCKUP_EVENT, //= Reset caused by core LOCKUP event
}
2 => SWro { //! Software
0 => RESET_NOT_CAUSED_BY_SOFTWARE_SETTING_OF_SYSRESETREQ_BIT, //= Reset not caused by software setting of SYSRESETREQ bit
1 => RESET_CAUSED_BY_SOFTWARE_SETTING_OF_SYSRESETREQ_BIT, //= Reset caused by software setting of SYSRESETREQ bit
}
3 => MDM_APro { //! MDM-AP System Reset Request
0 => RESET_NOT_CAUSED_BY_HOST_DEBUGGER_SYSTEM_SETTING_OF_THE_SYSTEM_RESET_REQUEST_BIT, //= Reset not caused by host debugger system setting of the System Reset Request bit
1 => RESET_CAUSED_BY_HOST_DEBUGGER_SYSTEM_SETTING_OF_THE_SYSTEM_RESET_REQUEST_BIT, //= Reset caused by host debugger system setting of the System Reset Request bit
}
5 => SACKERRro { //! Stop Mode Acknowledge Error Reset
0 => RESET_NOT_CAUSED_BY_PERIPHERAL_FAILURE_TO_ACKNOWLEDGE_ATTEMPT_TO_ENTER_STOP_MODE, //= Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
1 => RESET_CAUSED_BY_PERIPHERAL_FAILURE_TO_ACKNOWLEDGE_ATTEMPT_TO_ENTER_STOP_MODE, //= Reset caused by peripheral failure to acknowledge attempt to enter stop mode
}
},
0x04 => reg8 RPFC { //! Reset Pin Filter Control register
0..1 => RSTFLTSRWrw { //! Reset Pin Filter Select in Run and Wait Modes
0 => ALL_FILTERING_DISABLED, //= All filtering disabled
1 => BUS_CLOCK_FILTER_ENABLED_FOR_NORMAL_OPERATION, //= Bus clock filter enabled for normal operation
2 => LPO_CLOCK_FILTER_ENABLED_FOR_NORMAL_OPERATION, //= LPO clock filter enabled for normal operation
}
2 => RSTFLTSSrw { //! Reset Pin Filter Select in Stop Mode
0 => ALL_FILTERING_DISABLED, //= All filtering disabled
1 => LPO_CLOCK_FILTER_ENABLED, //= LPO clock filter enabled
}
},
0x05 => reg8 RPFW { //! Reset Pin Filter Width register
0..4 => RSTFLTSELrw { //! Reset Pin Filter Bus Clock Select
0 => BUS_CLOCK_FILTER_COUNT_IS_1, //= Bus clock filter count is 1
1 => BUS_CLOCK_FILTER_COUNT_IS_2, //= Bus clock filter count is 2
2 => BUS_CLOCK_FILTER_COUNT_IS_3, //= Bus clock filter count is 3
3 => BUS_CLOCK_FILTER_COUNT_IS_4, //= Bus clock filter count is 4
4 => BUS_CLOCK_FILTER_COUNT_IS_5, //= Bus clock filter count is 5
5 => BUS_CLOCK_FILTER_COUNT_IS_6, //= Bus clock filter count is 6
6 => BUS_CLOCK_FILTER_COUNT_IS_7, //= Bus clock filter count is 7
7 => BUS_CLOCK_FILTER_COUNT_IS_8, //= Bus clock filter count is 8
8 => BUS_CLOCK_FILTER_COUNT_IS_9, //= Bus clock filter count is 9
9 => BUS_CLOCK_FILTER_COUNT_IS_10, //= Bus clock filter count is 10
10 => BUS_CLOCK_FILTER_COUNT_IS_11, //= Bus clock filter count is 11
11 => BUS_CLOCK_FILTER_COUNT_IS_12, //= Bus clock filter count is 12
12 => BUS_CLOCK_FILTER_COUNT_IS_13, //= Bus clock filter count is 13
13 => BUS_CLOCK_FILTER_COUNT_IS_14, //= Bus clock filter count is 14
14 => BUS_CLOCK_FILTER_COUNT_IS_15, //= Bus clock filter count is 15
15 => BUS_CLOCK_FILTER_COUNT_IS_16, //= Bus clock filter count is 16
16 => BUS_CLOCK_FILTER_COUNT_IS_17, //= Bus clock filter count is 17
17 => BUS_CLOCK_FILTER_COUNT_IS_18, //= Bus clock filter count is 18
18 => BUS_CLOCK_FILTER_COUNT_IS_19, //= Bus clock filter count is 19
19 => BUS_CLOCK_FILTER_COUNT_IS_20, //= Bus clock filter count is 20
20 => BUS_CLOCK_FILTER_COUNT_IS_21, //= Bus clock filter count is 21
21 => BUS_CLOCK_FILTER_COUNT_IS_22, //= Bus clock filter count is 22
22 => BUS_CLOCK_FILTER_COUNT_IS_23, //= Bus clock filter count is 23
23 => BUS_CLOCK_FILTER_COUNT_IS_24, //= Bus clock filter count is 24
24 => BUS_CLOCK_FILTER_COUNT_IS_25, //= Bus clock filter count is 25
25 => BUS_CLOCK_FILTER_COUNT_IS_26, //= Bus clock filter count is 26
26 => BUS_CLOCK_FILTER_COUNT_IS_27, //= Bus clock filter count is 27
27 => BUS_CLOCK_FILTER_COUNT_IS_28, //= Bus clock filter count is 28
28 => BUS_CLOCK_FILTER_COUNT_IS_29, //= Bus clock filter count is 29
29 => BUS_CLOCK_FILTER_COUNT_IS_30, //= Bus clock filter count is 30
30 => BUS_CLOCK_FILTER_COUNT_IS_31, //= Bus clock filter count is 31
31 => BUS_CLOCK_FILTER_COUNT_IS_32, //= Bus clock filter count is 32
}
},
});
ioregs!(GPIOA @ 0x400FF000 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
ioregs!(GPIOB @ 0x400FF040 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
ioregs!(GPIOC @ 0x400FF080 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
ioregs!(GPIOD @ 0x400FF0C0 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
ioregs!(GPIOE @ 0x400FF100 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
ioregs!(SystemControl @ 0xE000E000 = { //! System Control Registers
0x08 => reg32 ACTLR { //! Auxiliary Control Register,
},
0xD00 => reg32 CPUID { //! CPUID Base Register
0..3 => REVISION ro, //= Indicates patch release: 0x0 = Patch 0
4..15 => PARTNO ro, //= Indicates part number
20..23 => VARIANT ro, //= Indicates processor revision: 0x2 = Revision 2
24..31 => IMPLEMENTER ro, //= Implementer code
},
0xD04 => reg32 ICSR { //! Interrupt Control and State Register
12..17 => VECTPENDING ro, //= Exception number of the highest priority pending enabled exception
25 => PENDSTCLRwo { //! no description available
0 => NO_EFFECT, //= no effect
1 => REMOVES_THE_PENDING_STATE_FROM_THE_SYSTICK_EXCEPTION, //= removes the pending state from the SysTick exception
}
26 => PENDSTSETrw { //! no description available
0 => E_0, //= write: no effect; read: SysTick exception is not pending
1 => E_1, //= write: changes SysTick exception state to pending; read: SysTick exception is pending
}
27 => PENDSVCLRwo { //! no description available
0 => NO_EFFECT, //= no effect
1 => REMOVES_THE_PENDING_STATE_FROM_THE_PENDSV_EXCEPTION, //= removes the pending state from the PendSV exception
}
28 => PENDSVSETrw { //! no description available
0 => E_0, //= write: no effect; read: PendSV exception is not pending
1 => E_1, //= write: changes PendSV exception state to pending; read: PendSV exception is pending
}
31 => NMIPENDSETrw { //! no description available
0 => E_0, //= write: no effect; read: NMI exception is not pending
1 => E_1, //= write: changes NMI exception state to pending; read: NMI exception is pending
}
},
0xD08 => reg32 VTOR { //! Vector Table Offset Register
7..31 => TBLOFF rw, //= Vector table base offset
},
0xD0C => reg32 AIRCR { //! Application Interrupt and Reset Control Register
1 => VECTCLRACTIVE wo, //= no description available
2 => SYSRESETREQwo { //! no description available
0 => NO_SYSTEM_RESET_REQUEST, //= no system reset request
1 => ASSERTS_A_SIGNAL_TO_THE_OUTER_SYSTEM_THAT_REQUESTS_A_RESET, //= asserts a signal to the outer system that requests a reset
}
15 => ENDIANNESSro { //! no description available
0 => LITTLE_ENDIAN, //= Little-endian
1 => BIG_ENDIAN, //= Big-endian
}
16..31 => VECTKEY rw, //= Register key
},
0xD10 => reg32 SCR { //! System Control Register
1 => SLEEPONEXITrw { //! no description available
0 => DO_NOT_SLEEP_WHEN_RETURNING_TO_THREAD_MODE, //= do not sleep when returning to Thread mode
1 => ENTER_SLEEP_OR_DEEP_SLEEP_ON_RETURN_FROM_AN_ISR, //= enter sleep, or deep sleep, on return from an ISR
}
2 => SLEEPDEEPrw { //! no description available
0 => SLEEP, //= sleep
1 => DEEP_SLEEP, //= deep sleep
}
4 => SEVONPENDrw { //! no description available
0 => ONLY_ENABLED_INTERRUPTS_OR_EVENTS_CAN_WAKEUP_THE_PROCESSOR_DISABLED_INTERRUPTS_ARE_EXCLUDED, //= only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1 => ENABLED_EVENTS_AND_ALL_INTERRUPTS_INCLUDING_DISABLED_INTERRUPTS_CAN_WAKEUP_THE_PROCESSOR, //= enabled events and all interrupts, including disabled interrupts, can wakeup the processor
}
},
0xD14 => reg32 CCR { //! Configuration and Control Register
3 => UNALIGN_TRP ro, //= Always reads as one, indicates that all unaligned accesses generate a HardFault
9 => STKALIGN ro, //= Indicates stack alignment on exception entry
},
0xD1C => reg32 SHPR2 { //! System Handler Priority Register 2
30..31 => PRI_11 rw, //= Priority of system handler 11, SVCall
},
0xD20 => reg32 SHPR3 { //! System Handler Priority Register 3
22..23 => PRI_14 rw, //= Priority of system handler 14, PendSV
30..31 => PRI_15 rw, //= Priority of system handler 15, SysTick exception
},
0xD24 => reg32 SHCSR { //! System Handler Control and State Register
15 => SVCALLPENDEDrw { //! no description available
0 => EXCEPTION_IS_NOT_PENDING, //= exception is not pending
1 => EXCEPTION_IS_PENDING, //= exception is pending
}
},
0xD30 => reg32 DFSR { //! Debug Fault Status Register
0 => HALTEDrw { //! no description available
0 => NO_ACTIVE_HALT_REQUEST_DEBUG_EVENT, //= No active halt request debug event
1 => HALT_REQUEST_DEBUG_EVENT_ACTIVE, //= Halt request debug event active
}
1 => BKPTrw { //! no description available
0 => NO_CURRENT_BREAKPOINT_DEBUG_EVENT, //= No current breakpoint debug event
1 => AT_LEAST_ONE_CURRENT_BREAKPOINT_DEBUG_EVENT, //= At least one current breakpoint debug event
}
2 => DWTTRAPrw { //! no description available
0 => NO_CURRENT_DEBUG_EVENTS_GENERATED_BY_THE_DWT, //= No current debug events generated by the DWT
1 => AT_LEAST_ONE_CURRENT_DEBUG_EVENT_GENERATED_BY_THE_DWT, //= At least one current debug event generated by the DWT
}
3 => VCATCHrw { //! no description available
0 => NO_VECTOR_CATCH_TRIGGERED, //= No Vector catch triggered
1 => VECTOR_CATCH_TRIGGERED, //= Vector catch triggered
}
4 => EXTERNALrw { //! no description available
0 => NO_EDBGRQ_DEBUG_EVENT, //= No EDBGRQ debug event
1 => EDBGRQ_DEBUG_EVENT, //= EDBGRQ debug event
}
},
});
ioregs!(SysTick @ 0xE000E010 = { //! System timer
0x00 => reg32 CSR { //! SysTick Control and Status Register
0 => ENABLErw { //! no description available
0 => COUNTER_DISABLED, //= counter disabled
1 => COUNTER_ENABLED, //= counter enabled
}
1 => TICKINTrw { //! no description available
0 => COUNTING_DOWN_TO_0_DOES_NOT_ASSERT_THE_SYSTICK_EXCEPTION_REQUEST, //= counting down to 0 does not assert the SysTick exception request
1 => COUNTING_DOWN_TO_0_ASSERTS_THE_SYSTICK_EXCEPTION_REQUEST, //= counting down to 0 asserts the SysTick exception request
}
2 => CLKSOURCErw { //! no description available
0 => EXTERNAL_CLOCK, //= external clock
1 => PROCESSOR_CLOCK, //= processor clock
}
16 => COUNTFLAG rw, //= no description available
},
0x04 => reg32 RVR { //! SysTick Reload Value Register
0..23 => RELOAD rw, //= Value to load into the SysTick Current Value Register when the counter reaches 0
},
0x08 => reg32 CVR { //! SysTick Current Value Register
0..23 => CURRENT rw, //= Current value at the time the register is accessed
},
0x0C => reg32 CALIB { //! SysTick Calibration Value Register
0..23 => TENMS ro, //= Reload value to use for 10ms timing
30 => SKEWro { //! no description available
0 => 10MS_CALIBRATION_VALUE_IS_EXACT, //= 10ms calibration value is exact
1 => 10MS_CALIBRATION_VALUE_IS_INEXACT_BECAUSE_OF_THE_CLOCK_FREQUENCY, //= 10ms calibration value is inexact, because of the clock frequency
}
31 => NOREFro { //! no description available
0 => THE_REFERENCE_CLOCK_IS_PROVIDED, //= The reference clock is provided
1 => THE_REFERENCE_CLOCK_IS_NOT_PROVIDED, //= The reference clock is not provided
}
},
});
ioregs!(NVIC @ 0xE000E100 = { //! Nested Vectored Interrupt Controller
0x00 => reg32 NVIC_ISER { //! Interrupt Set Enable Register
0 => SETENA0rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 0 transfer complete interrupt disabled
1 => E_1, //= write: enable DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt enabled
}
1 => SETENA1rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 1 transfer complete interrupt disabled
1 => E_1, //= write: enable DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt enabled
}
2 => SETENA2rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 2 transfer complete interrupt disabled
1 => E_1, //= write: enable DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt enabled
}
3 => SETENA3rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 3 transfer complete interrupt disabled
1 => E_1, //= write: enable DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt enabled
}
4 => SETENA4rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 20 interrupt disabled
1 => E_1, //= write: enable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
}
5 => SETENA5rw { //! no description available
0 => E_0, //= write: no effect; read: Command complete and read collision interrupt disabled
1 => E_1, //= write: enable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled
}
6 => SETENA6rw { //! no description available
0 => E_0, //= write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled
1 => E_1, //= write: enable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled
}
7 => SETENA7rw { //! no description available
0 => E_0, //= write: no effect; read: Low Leakage Wakeup interrupt disabled
1 => E_1, //= write: enable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
}
8 => SETENA8rw { //! no description available
0 => E_0, //= write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled
1 => E_1, //= write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
}
9 => SETENA9rw { //! no description available
0 => E_0, //= write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled
1 => E_1, //= write: enable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled
}
10 => SETENA10rw { //! no description available
0 => E_0, //= write: no effect; read: Serial Peripheral Interface 0 interrupt disabled
1 => E_1, //= write: enable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
}
11 => SETENA11rw { //! no description available
0 => E_0, //= write: no effect; read: Serial Peripheral Interface 1 interrupt disabled
1 => E_1, //= write: enable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled
}
12 => SETENA12rw { //! no description available
0 => E_0, //= write: no effect; read: UART0 status and error interrupt disabled
1 => E_1, //= write: enable UART0 status and error interrupt; read: UART0 status and error interrupt enabled
}
13 => SETENA13rw { //! no description available
0 => E_0, //= write: no effect; read: UART1 status and error interrupt disabled
1 => E_1, //= write: enable UART1 status and error interrupt; read: UART1 status and error interrupt enabled
}
14 => SETENA14rw { //! no description available
0 => E_0, //= write: no effect; read: UART2 status and error interrupt disabled
1 => E_1, //= write: enable UART2 status and error interrupt; read: UART2 status and error interrupt enabled
}
15 => SETENA15rw { //! no description available
0 => E_0, //= write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled
1 => E_1, //= write: enable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
}
16 => SETENA16rw { //! no description available
0 => E_0, //= write: no effect; read: Comparator 0 interrupt disabled
1 => E_1, //= write: enable Comparator 0 interrupt; read: Comparator 0 interrupt enabled
}
17 => SETENA17rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 0 interrupt disabled
1 => E_1, //= write: enable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
}
18 => SETENA18rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 1 interrupt disabled
1 => E_1, //= write: enable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
}
19 => SETENA19rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 2 interrupt disabled
1 => E_1, //= write: enable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled
}
20 => SETENA20rw { //! no description available
0 => E_0, //= write: no effect; read: Real-time counter interrupt disabled
1 => E_1, //= write: enable Real-time counter interrupt; read: Real-time counter interrupt enabled
}
21 => SETENA21rw { //! no description available
0 => E_0, //= write: no effect; read: RTC seconds interrupt disabled
1 => E_1, //= write: enable RTC seconds interrupt; read: RTC seconds interrupt enabled
}
22 => SETENA22rw { //! no description available
0 => E_0, //= write: no effect; read: Periodic Interrupt Timer interrupt disabled
1 => E_1, //= write: enable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled
}
23 => SETENA23rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 39 interrupt disabled
1 => E_1, //= write: enable Reserved iv 39 interrupt; read: Reserved iv 39 interrupt enabled
}
24 => SETENA24rw { //! no description available
0 => E_0, //= write: no effect; read: Universal Serial Bus interrupt disabled
1 => E_1, //= write: enable Universal Serial Bus interrupt; read: Universal Serial Bus interrupt enabled
}
25 => SETENA25rw { //! no description available
0 => E_0, //= write: no effect; read: Digital to Analog Converter interrupt disabled
1 => E_1, //= write: enable Digital to Analog Converter interrupt; read: Digital to Analog Converter interrupt enabled
}
26 => SETENA26rw { //! no description available
0 => E_0, //= write: no effect; read: Touch Sensing Input interrupt disabled
1 => E_1, //= write: enable Touch Sensing Input interrupt; read: Touch Sensing Input interrupt enabled
}
27 => SETENA27rw { //! no description available
0 => E_0, //= write: no effect; read: Multipurpose Clock Generator interrupt disabled
1 => E_1, //= write: enable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled
}
28 => SETENA28rw { //! no description available
0 => E_0, //= write: no effect; read: Low-Power Timer interrupt disabled
1 => E_1, //= write: enable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
}
29 => SETENA29rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 45 interrupt disabled
1 => E_1, //= write: enable Reserved iv 45 interrupt; read: Reserved iv 45 interrupt enabled
}
30 => SETENA30rw { //! no description available
0 => E_0, //= write: no effect; read: PORTA Pin detect interrupt disabled
1 => E_1, //= write: enable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled
}
31 => SETENA31rw { //! no description available
0 => E_0, //= write: no effect; read: PORTD Pin detect interrupt disabled
1 => E_1, //= write: enable PORTD Pin detect interrupt; read: PORTD Pin detect interrupt enabled
}
},
0x80 => reg32 NVIC_ICER { //! Interrupt Clear Enable Register
0 => CLRENA0rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 0 transfer complete interrupt disabled
1 => E_1, //= write: disable DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt enabled
}
1 => CLRENA1rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 1 transfer complete interrupt disabled
1 => E_1, //= write: disable DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt enabled
}
2 => CLRENA2rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 2 transfer complete interrupt disabled
1 => E_1, //= write: disable DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt enabled
}
3 => CLRENA3rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 3 transfer complete interrupt disabled
1 => E_1, //= write: disable DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt enabled
}
4 => CLRENA4rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 20 interrupt disabled
1 => E_1, //= write: disable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
}
5 => CLRENA5rw { //! no description available
0 => E_0, //= write: no effect; read: Command complete and read collision interrupt disabled
1 => E_1, //= write: disable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled
}
6 => CLRENA6rw { //! no description available
0 => E_0, //= write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled
1 => E_1, //= write: disable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled
}
7 => CLRENA7rw { //! no description available
0 => E_0, //= write: no effect; read: Low Leakage Wakeup interrupt disabled
1 => E_1, //= write: disable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
}
8 => CLRENA8rw { //! no description available
0 => E_0, //= write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled
1 => E_1, //= write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
}
9 => CLRENA9rw { //! no description available
0 => E_0, //= write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled
1 => E_1, //= write: disable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled
}
10 => CLRENA10rw { //! no description available
0 => E_0, //= write: no effect; read: Serial Peripheral Interface 0 interrupt disabled
1 => E_1, //= write: disable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
}
11 => CLRENA11rw { //! no description available
0 => E_0, //= write: no effect; read: Serial Peripheral Interface 1 interrupt disabled
1 => E_1, //= write: disable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled
}
12 => CLRENA12rw { //! no description available
0 => E_0, //= write: no effect; read: UART0 status and error interrupt disabled
1 => E_1, //= write: disable UART0 status and error interrupt; read: UART0 status and error interrupt enabled
}
13 => CLRENA13rw { //! no description available
0 => E_0, //= write: no effect; read: UART1 status and error interrupt disabled
1 => E_1, //= write: disable UART1 status and error interrupt; read: UART1 status and error interrupt enabled
}
14 => CLRENA14rw { //! no description available
0 => E_0, //= write: no effect; read: UART2 status and error interrupt disabled
1 => E_1, //= write: disable UART2 status and error interrupt; read: UART2 status and error interrupt enabled
}
15 => CLRENA15rw { //! no description available
0 => E_0, //= write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled
1 => E_1, //= write: disable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
}
16 => CLRENA16rw { //! no description available
0 => E_0, //= write: no effect; read: Comparator 0 interrupt disabled
1 => E_1, //= write: disable Comparator 0 interrupt; read: Comparator 0 interrupt enabled
}
17 => CLRENA17rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 0 interrupt disabled
1 => E_1, //= write: disable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
}
18 => CLRENA18rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 1 interrupt disabled
1 => E_1, //= write: disable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
}
19 => CLRENA19rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 2 interrupt disabled
1 => E_1, //= write: disable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled
}
20 => CLRENA20rw { //! no description available
0 => E_0, //= write: no effect; read: Real-time counter interrupt disabled
1 => E_1, //= write: disable Real-time counter interrupt; read: Real-time counter interrupt enabled
}
21 => CLRENA21rw { //! no description available
0 => E_0, //= write: no effect; read: RTC seconds interrupt disabled
1 => E_1, //= write: disable RTC seconds interrupt; read: RTC seconds interrupt enabled
}
22 => CLRENA22rw { //! no description available
0 => E_0, //= write: no effect; read: Periodic Interrupt Timer interrupt disabled
1 => E_1, //= write: disable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled
}
23 => CLRENA23rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 39 interrupt disabled
1 => E_1, //= write: disable Reserved iv 39 interrupt; read: Reserved iv 39 interrupt enabled
}
24 => CLRENA24rw { //! no description available
0 => E_0, //= write: no effect; read: Universal Serial Bus interrupt disabled
1 => E_1, //= write: disable Universal Serial Bus interrupt; read: Universal Serial Bus interrupt enabled
}
25 => CLRENA25rw { //! no description available
0 => E_0, //= write: no effect; read: Digital to Analog Converter interrupt disabled
1 => E_1, //= write: disable Digital to Analog Converter interrupt; read: Digital to Analog Converter interrupt enabled
}
26 => CLRENA26rw { //! no description available
0 => E_0, //= write: no effect; read: Touch Sensing Input interrupt disabled
1 => E_1, //= write: disable Touch Sensing Input interrupt; read: Touch Sensing Input interrupt enabled
}
27 => CLRENA27rw { //! no description available
0 => E_0, //= write: no effect; read: Multipurpose Clock Generator interrupt disabled
1 => E_1, //= write: disable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled
}
28 => CLRENA28rw { //! no description available
0 => E_0, //= write: no effect; read: Low-Power Timer interrupt disabled
1 => E_1, //= write: disable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
}
29 => CLRENA29rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 45 interrupt disabled
1 => E_1, //= write: disable Reserved iv 45 interrupt; read: Reserved iv 45 interrupt enabled
}
30 => CLRENA30rw { //! no description available
0 => E_0, //= write: no effect; read: PORTA Pin detect interrupt disabled
1 => E_1, //= write: disable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled
}
31 => CLRENA31rw { //! no description available
0 => E_0, //= write: no effect; read: PORTD Pin detect interrupt disabled
1 => E_1, //= write: disable PORTD Pin detect interrupt; read: PORTD Pin detect interrupt enabled
}
},
0x100 => reg32 NVIC_ISPR { //! Interrupt Set Pending Register
0 => SETPEND0rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 0 transfer complete interrupt is not pending
1 => E_1, //= write: changes the DMA channel 0 transfer complete interrupt state to pending; read: DMA channel 0 transfer complete interrupt is pending
}
1 => SETPEND1rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 1 transfer complete interrupt is not pending
1 => E_1, //= write: changes the DMA channel 1 transfer complete interrupt state to pending; read: DMA channel 1 transfer complete interrupt is pending
}
2 => SETPEND2rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 2 transfer complete interrupt is not pending
1 => E_1, //= write: changes the DMA channel 2 transfer complete interrupt state to pending; read: DMA channel 2 transfer complete interrupt is pending
}
3 => SETPEND3rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 3 transfer complete interrupt is not pending
1 => E_1, //= write: changes the DMA channel 3 transfer complete interrupt state to pending; read: DMA channel 3 transfer complete interrupt is pending
}
4 => SETPEND4rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 20 interrupt is not pending
1 => E_1, //= write: changes the Reserved iv 20 interrupt state to pending; read: Reserved iv 20 interrupt is pending
}
5 => SETPEND5rw { //! no description available
0 => E_0, //= write: no effect; read: Command complete and read collision interrupt is not pending
1 => E_1, //= write: changes the Command complete and read collision interrupt state to pending; read: Command complete and read collision interrupt is pending
}
6 => SETPEND6rw { //! no description available
0 => E_0, //= write: no effect; read: Low-voltage detect, low-voltage warning interrupt is not pending
1 => E_1, //= write: changes the Low-voltage detect, low-voltage warning interrupt state to pending; read: Low-voltage detect, low-voltage warning interrupt is pending
}
7 => SETPEND7rw { //! no description available
0 => E_0, //= write: no effect; read: Low Leakage Wakeup interrupt is not pending
1 => E_1, //= write: changes the Low Leakage Wakeup interrupt state to pending; read: Low Leakage Wakeup interrupt is pending
}
8 => SETPEND8rw { //! no description available
0 => E_0, //= write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending
1 => E_1, //= write: changes the Inter-Integrated Circuit 0 interrupt state to pending; read: Inter-Integrated Circuit 0 interrupt is pending
}
9 => SETPEND9rw { //! no description available
0 => E_0, //= write: no effect; read: Inter-Integrated Circuit 1 interrupt is not pending
1 => E_1, //= write: changes the Inter-Integrated Circuit 1 interrupt state to pending; read: Inter-Integrated Circuit 1 interrupt is pending
}
10 => SETPEND10rw { //! no description available
0 => E_0, //= write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending
1 => E_1, //= write: changes the Serial Peripheral Interface 0 interrupt state to pending; read: Serial Peripheral Interface 0 interrupt is pending
}
11 => SETPEND11rw { //! no description available
0 => E_0, //= write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending
1 => E_1, //= write: changes the Serial Peripheral Interface 1 interrupt state to pending; read: Serial Peripheral Interface 1 interrupt is pending
}
12 => SETPEND12rw { //! no description available
0 => E_0, //= write: no effect; read: UART0 status and error interrupt is not pending
1 => E_1, //= write: changes the UART0 status and error interrupt state to pending; read: UART0 status and error interrupt is pending
}
13 => SETPEND13rw { //! no description available
0 => E_0, //= write: no effect; read: UART1 status and error interrupt is not pending
1 => E_1, //= write: changes the UART1 status and error interrupt state to pending; read: UART1 status and error interrupt is pending
}
14 => SETPEND14rw { //! no description available
0 => E_0, //= write: no effect; read: UART2 status and error interrupt is not pending
1 => E_1, //= write: changes the UART2 status and error interrupt state to pending; read: UART2 status and error interrupt is pending
}
15 => SETPEND15rw { //! no description available
0 => E_0, //= write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending
1 => E_1, //= write: changes the Analog-to-Digital Converter 0 interrupt state to pending; read: Analog-to-Digital Converter 0 interrupt is pending
}
16 => SETPEND16rw { //! no description available
0 => E_0, //= write: no effect; read: Comparator 0 interrupt is not pending
1 => E_1, //= write: changes the Comparator 0 interrupt state to pending; read: Comparator 0 interrupt is pending
}
17 => SETPEND17rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 0 interrupt is not pending
1 => E_1, //= write: changes the Timer/PWM module 0 interrupt state to pending; read: Timer/PWM module 0 interrupt is pending
}
18 => SETPEND18rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 1 interrupt is not pending
1 => E_1, //= write: changes the Timer/PWM module 1 interrupt state to pending; read: Timer/PWM module 1 interrupt is pending
}
19 => SETPEND19rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 2 interrupt is not pending
1 => E_1, //= write: changes the Timer/PWM module 2 interrupt state to pending; read: Timer/PWM module 2 interrupt is pending
}
20 => SETPEND20rw { //! no description available
0 => E_0, //= write: no effect; read: Real-time counter interrupt is not pending
1 => E_1, //= write: changes the Real-time counter interrupt state to pending; read: Real-time counter interrupt is pending
}
21 => SETPEND21rw { //! no description available
0 => E_0, //= write: no effect; read: RTC seconds interrupt is not pending
1 => E_1, //= write: changes the RTC seconds interrupt state to pending; read: RTC seconds interrupt is pending
}
22 => SETPEND22rw { //! no description available
0 => E_0, //= write: no effect; read: Periodic Interrupt Timer interrupt is not pending
1 => E_1, //= write: changes the Periodic Interrupt Timer interrupt state to pending; read: Periodic Interrupt Timer interrupt is pending
}
23 => SETPEND23rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 39 interrupt is not pending
1 => E_1, //= write: changes the Reserved iv 39 interrupt state to pending; read: Reserved iv 39 interrupt is pending
}
24 => SETPEND24rw { //! no description available
0 => E_0, //= write: no effect; read: Universal Serial Bus interrupt is not pending
1 => E_1, //= write: changes the Universal Serial Bus interrupt state to pending; read: Universal Serial Bus interrupt is pending
}
25 => SETPEND25rw { //! no description available
0 => E_0, //= write: no effect; read: Digital to Analog Converter interrupt is not pending
1 => E_1, //= write: changes the Digital to Analog Converter interrupt state to pending; read: Digital to Analog Converter interrupt is pending
}
26 => SETPEND26rw { //! no description available
0 => E_0, //= write: no effect; read: Touch Sensing Input interrupt is not pending
1 => E_1, //= write: changes the Touch Sensing Input interrupt state to pending; read: Touch Sensing Input interrupt is pending
}
27 => SETPEND27rw { //! no description available
0 => E_0, //= write: no effect; read: Multipurpose Clock Generator interrupt is not pending
1 => E_1, //= write: changes the Multipurpose Clock Generator interrupt state to pending; read: Multipurpose Clock Generator interrupt is pending
}
28 => SETPEND28rw { //! no description available
0 => E_0, //= write: no effect; read: Low-Power Timer interrupt is not pending
1 => E_1, //= write: changes the Low-Power Timer interrupt state to pending; read: Low-Power Timer interrupt is pending
}
29 => SETPEND29rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 45 interrupt is not pending
1 => E_1, //= write: changes the Reserved iv 45 interrupt state to pending; read: Reserved iv 45 interrupt is pending
}
30 => SETPEND30rw { //! no description available
0 => E_0, //= write: no effect; read: PORTA Pin detect interrupt is not pending
1 => E_1, //= write: changes the PORTA Pin detect interrupt state to pending; read: PORTA Pin detect interrupt is pending
}
31 => SETPEND31rw { //! no description available
0 => E_0, //= write: no effect; read: PORTD Pin detect interrupt is not pending
1 => E_1, //= write: changes the PORTD Pin detect interrupt state to pending; read: PORTD Pin detect interrupt is pending
}
},
0x180 => reg32 NVIC_ICPR { //! Interrupt Clear Pending Register
0 => CLRPEND0rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 0 transfer complete interrupt is not pending
1 => E_1, //= write: removes pending state from the DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt is pending
}
1 => CLRPEND1rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 1 transfer complete interrupt is not pending
1 => E_1, //= write: removes pending state from the DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt is pending
}
2 => CLRPEND2rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 2 transfer complete interrupt is not pending
1 => E_1, //= write: removes pending state from the DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt is pending
}
3 => CLRPEND3rw { //! no description available
0 => E_0, //= write: no effect; read: DMA channel 3 transfer complete interrupt is not pending
1 => E_1, //= write: removes pending state from the DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt is pending
}
4 => CLRPEND4rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 20 interrupt is not pending
1 => E_1, //= write: removes pending state from the Reserved iv 20 interrupt; read: Reserved iv 20 interrupt is pending
}
5 => CLRPEND5rw { //! no description available
0 => E_0, //= write: no effect; read: Command complete and read collision interrupt is not pending
1 => E_1, //= write: removes pending state from the Command complete and read collision interrupt; read: Command complete and read collision interrupt is pending
}
6 => CLRPEND6rw { //! no description available
0 => E_0, //= write: no effect; read: Low-voltage detect, low-voltage warning interrupt is not pending
1 => E_1, //= write: removes pending state from the Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt is pending
}
7 => CLRPEND7rw { //! no description available
0 => E_0, //= write: no effect; read: Low Leakage Wakeup interrupt is not pending
1 => E_1, //= write: removes pending state from the Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt is pending
}
8 => CLRPEND8rw { //! no description available
0 => E_0, //= write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending
1 => E_1, //= write: removes pending state from the Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt is pending
}
9 => CLRPEND9rw { //! no description available
0 => E_0, //= write: no effect; read: Inter-Integrated Circuit 1 interrupt is not pending
1 => E_1, //= write: removes pending state from the Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt is pending
}
10 => CLRPEND10rw { //! no description available
0 => E_0, //= write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending
1 => E_1, //= write: removes pending state from the Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt is pending
}
11 => CLRPEND11rw { //! no description available
0 => E_0, //= write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending
1 => E_1, //= write: removes pending state from the Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt is pending
}
12 => CLRPEND12rw { //! no description available
0 => E_0, //= write: no effect; read: UART0 status and error interrupt is not pending
1 => E_1, //= write: removes pending state from the UART0 status and error interrupt; read: UART0 status and error interrupt is pending
}
13 => CLRPEND13rw { //! no description available
0 => E_0, //= write: no effect; read: UART1 status and error interrupt is not pending
1 => E_1, //= write: removes pending state from the UART1 status and error interrupt; read: UART1 status and error interrupt is pending
}
14 => CLRPEND14rw { //! no description available
0 => E_0, //= write: no effect; read: UART2 status and error interrupt is not pending
1 => E_1, //= write: removes pending state from the UART2 status and error interrupt; read: UART2 status and error interrupt is pending
}
15 => CLRPEND15rw { //! no description available
0 => E_0, //= write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending
1 => E_1, //= write: removes pending state from the Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt is pending
}
16 => CLRPEND16rw { //! no description available
0 => E_0, //= write: no effect; read: Comparator 0 interrupt is not pending
1 => E_1, //= write: removes pending state from the Comparator 0 interrupt; read: Comparator 0 interrupt is pending
}
17 => CLRPEND17rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 0 interrupt is not pending
1 => E_1, //= write: removes pending state from the Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt is pending
}
18 => CLRPEND18rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 1 interrupt is not pending
1 => E_1, //= write: removes pending state from the Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt is pending
}
19 => CLRPEND19rw { //! no description available
0 => E_0, //= write: no effect; read: Timer/PWM module 2 interrupt is not pending
1 => E_1, //= write: removes pending state from the Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt is pending
}
20 => CLRPEND20rw { //! no description available
0 => E_0, //= write: no effect; read: Real-time counter interrupt is not pending
1 => E_1, //= write: removes pending state from the Real-time counter interrupt; read: Real-time counter interrupt is pending
}
21 => CLRPEND21rw { //! no description available
0 => E_0, //= write: no effect; read: RTC seconds interrupt is not pending
1 => E_1, //= write: removes pending state from the RTC seconds interrupt; read: RTC seconds interrupt is pending
}
22 => CLRPEND22rw { //! no description available
0 => E_0, //= write: no effect; read: Periodic Interrupt Timer interrupt is not pending
1 => E_1, //= write: removes pending state from the Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt is pending
}
23 => CLRPEND23rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 39 interrupt is not pending
1 => E_1, //= write: removes pending state from the Reserved iv 39 interrupt; read: Reserved iv 39 interrupt is pending
}
24 => CLRPEND24rw { //! no description available
0 => E_0, //= write: no effect; read: Universal Serial Bus interrupt is not pending
1 => E_1, //= write: removes pending state from the Universal Serial Bus interrupt; read: Universal Serial Bus interrupt is pending
}
25 => CLRPEND25rw { //! no description available
0 => E_0, //= write: no effect; read: Digital to Analog Converter interrupt is not pending
1 => E_1, //= write: removes pending state from the Digital to Analog Converter interrupt; read: Digital to Analog Converter interrupt is pending
}
26 => CLRPEND26rw { //! no description available
0 => E_0, //= write: no effect; read: Touch Sensing Input interrupt is not pending
1 => E_1, //= write: removes pending state from the Touch Sensing Input interrupt; read: Touch Sensing Input interrupt is pending
}
27 => CLRPEND27rw { //! no description available
0 => E_0, //= write: no effect; read: Multipurpose Clock Generator interrupt is not pending
1 => E_1, //= write: removes pending state from the Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt is pending
}
28 => CLRPEND28rw { //! no description available
0 => E_0, //= write: no effect; read: Low-Power Timer interrupt is not pending
1 => E_1, //= write: removes pending state from the Low-Power Timer interrupt; read: Low-Power Timer interrupt is pending
}
29 => CLRPEND29rw { //! no description available
0 => E_0, //= write: no effect; read: Reserved iv 45 interrupt is not pending
1 => E_1, //= write: removes pending state from the Reserved iv 45 interrupt; read: Reserved iv 45 interrupt is pending
}
30 => CLRPEND30rw { //! no description available
0 => E_0, //= write: no effect; read: PORTA Pin detect interrupt is not pending
1 => E_1, //= write: removes pending state from the PORTA Pin detect interrupt; read: PORTA Pin detect interrupt is pending
}
31 => CLRPEND31rw { //! no description available
0 => E_0, //= write: no effect; read: PORTD Pin detect interrupt is not pending
1 => E_1, //= write: removes pending state from the PORTD Pin detect interrupt; read: PORTD Pin detect interrupt is pending
}
},
0x300 => reg32 NVIC_IPR0 { //! Interrupt Priority Register 0
6..7 => PRI_0 rw, //= Priority of the DMA channel 0 transfer complete interrupt
14..15 => PRI_1 rw, //= Priority of the DMA channel 1 transfer complete interrupt
22..23 => PRI_2 rw, //= Priority of the DMA channel 2 transfer complete interrupt
30..31 => PRI_3 rw, //= Priority of the DMA channel 3 transfer complete interrupt
},
0x304 => reg32 NVIC_IPR1 { //! Interrupt Priority Register 1
6..7 => PRI_4 rw, //= Priority of the Reserved iv 20 interrupt
14..15 => PRI_5 rw, //= Priority of the Command complete and read collision interrupt
22..23 => PRI_6 rw, //= Priority of the Low-voltage detect, low-voltage warning interrupt
30..31 => PRI_7 rw, //= Priority of the Low Leakage Wakeup interrupt
},
0x308 => reg32 NVIC_IPR2 { //! Interrupt Priority Register 2
6..7 => PRI_8 rw, //= Priority of the Inter-Integrated Circuit 0 interrupt
14..15 => PRI_9 rw, //= Priority of the Inter-Integrated Circuit 1 interrupt
22..23 => PRI_10 rw, //= Priority of the Serial Peripheral Interface 0 interrupt
30..31 => PRI_11 rw, //= Priority of the Serial Peripheral Interface 1 interrupt
},
0x30C => reg32 NVIC_IPR3 { //! Interrupt Priority Register 3
6..7 => PRI_12 rw, //= Priority of the UART0 status and error interrupt
14..15 => PRI_13 rw, //= Priority of the UART1 status and error interrupt
22..23 => PRI_14 rw, //= Priority of the UART2 status and error interrupt
30..31 => PRI_15 rw, //= Priority of the Analog-to-Digital Converter 0 interrupt
},
0x310 => reg32 NVIC_IPR4 { //! Interrupt Priority Register 4
6..7 => PRI_16 rw, //= Priority of the Comparator 0 interrupt
14..15 => PRI_17 rw, //= Priority of the Timer/PWM module 0 interrupt
22..23 => PRI_18 rw, //= Priority of the Timer/PWM module 1 interrupt
30..31 => PRI_19 rw, //= Priority of the Timer/PWM module 2 interrupt
},
0x314 => reg32 NVIC_IPR5 { //! Interrupt Priority Register 5
6..7 => PRI_20 rw, //= Priority of the Real-time counter interrupt
14..15 => PRI_21 rw, //= Priority of the RTC seconds interrupt
22..23 => PRI_22 rw, //= Priority of the Periodic Interrupt Timer interrupt
30..31 => PRI_23 rw, //= Priority of the Reserved iv 39 interrupt
},
0x318 => reg32 NVIC_IPR6 { //! Interrupt Priority Register 6
6..7 => PRI_24 rw, //= Priority of the Universal Serial Bus interrupt
14..15 => PRI_25 rw, //= Priority of the Digital to Analog Converter interrupt
22..23 => PRI_26 rw, //= Priority of the Touch Sensing Input interrupt
30..31 => PRI_27 rw, //= Priority of the Multipurpose Clock Generator interrupt
},
0x31C => reg32 NVIC_IPR7 { //! Interrupt Priority Register 7
6..7 => PRI_28 rw, //= Priority of the Low-Power Timer interrupt
14..15 => PRI_29 rw, //= Priority of the Reserved iv 45 interrupt
22..23 => PRI_30 rw, //= Priority of the PORTA Pin detect interrupt
30..31 => PRI_31 rw, //= Priority of the PORTD Pin detect interrupt
},
});
ioregs!(MTB @ 0xF0000000 = { //! Micro Trace Buffer
0x00 => reg32 POSITION { //! MTB Position Register
2 => WRAP rw, //= no description available
3..31 => POINTER rw, //= Trace Packet Address Pointer
},
0x04 => reg32 MASTER { //! MTB Master Register
0..4 => MASK rw, //= Mask
5 => TSTARTEN rw, //= Trace start input enable
6 => TSTOPEN rw, //= Trace stop input enable
7 => SFRWPRIV rw, //= Special Function Register Write Privilege bit
8 => RAMPRIV rw, //= RAM privilege bit
9 => HALTREQ rw, //= Halt request bit
31 => EN rw, //= Main trace enable bit
},
0x08 => reg32 FLOW { //! MTB Flow Register
0 => AUTOSTOP rw, //= no description available
1 => AUTOHALT rw, //= no description available
3..31 => WATERMARK rw, //= WATERMARK value
},
0x0C => reg32 BASE { //! MTB Base Register
0..31 => BASEADDR ro, //= no description available
},
0xF00 => reg32 MODECTRL { //! Integration Mode Control Register
0..31 => MODECTRL ro, //= no description available
},
0xFA0 => reg32 TAGSET { //! Claim TAG Set Register
0..31 => TAGSET ro, //= no description available
},
0xFA4 => reg32 TAGCLEAR { //! Claim TAG Clear Register
0..31 => TAGCLEAR ro, //= no description available
},
0xFB0 => reg32 LOCKACCESS { //! Lock Access Register
0..31 => LOCKACCESS ro, //= no description available
},
0xFB4 => reg32 LOCKSTAT { //! Lock Status Register
0..31 => LOCKSTAT ro, //= no description available
},
0xFB8 => reg32 AUTHSTAT { //! Authentication Status Register
0 => BIT0 ro, //= no description available
1 => BIT1 ro, //= no description available
2 => BIT2 ro, //= no description available
3 => BIT3 ro, //= no description available
},
0xFBC => reg32 DEVICEARCH { //! Device Architecture Register
0..31 => DEVICEARCH ro, //= no description available
},
0xFC8 => reg32 DEVICECFG { //! Device Configuration Register
0..31 => DEVICECFG ro, //= no description available
},
0xFCC => reg32 DEVICETYPID { //! Device Type Identifier Register
0..31 => DEVICETYPID ro, //= no description available
},
0xFD0 => reg32 PERIPHID%s { //! Peripheral ID Register
0..31 => PERIPHID ro, //= no description available
},
0xFF0 => reg32 COMPID%s { //! Component ID Register
0..31 => COMPID ro, //= Component ID
},
});
ioregs!(MTBDWT @ 0xF0001000 = { //! MTB data watchpoint and trace
0x00 => reg32 CTRL { //! MTB DWT Control Register
0..27 => DWTCFGCTRL ro, //= DWT configuration controls
28..31 => NUMCMP ro, //= Number of comparators
},
0x20 => reg32 COMP%s { //! MTB_DWT Comparator Register
0..31 => COMP rw, //= Reference value for comparison
},
0x24 => reg32 MASK%s { //! MTB_DWT Comparator Mask Register
0..4 => MASK rw, //= MASK
},
0x28 => reg32 FCT0 { //! MTB_DWT Comparator Function Register 0
0..3 => FUNCTIONrw { //! Function
0 => DISABLED, //= Disabled.
4 => INSTRUCTION_FETCH, //= Instruction fetch.
5 => DATA_OPERAND_READ, //= Data operand read.
6 => DATA_OPERAND_WRITE, //= Data operand write.
7 => E_0111, //= Data operand (read + write).
}
8 => DATAVMATCHrw { //! Data Value Match
0 => PERFORM_ADDRESS_COMPARISON, //= Perform address comparison.
1 => PERFORM_DATA_VALUE_COMPARISON, //= Perform data value comparison.
}
10..11 => DATAVSIZErw { //! Data Value Size
0 => BYTE, //= Byte.
1 => HALFWORD, //= Halfword.
2 => WORD, //= Word.
3 => RESERVED_ANY_ATTEMPTS_TO_USE_THIS_VALUE_RESULTS_IN_UNPREDICTABLE_BEHAVIOR, //= Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
}
12..15 => DATAVADDR0 rw, //= Data Value Address 0
24 => MATCHEDro { //! Comparator match
0 => NO_MATCH, //= No match.
1 => MATCH_OCCURRED, //= Match occurred.
}
},
0x38 => reg32 FCT1 { //! MTB_DWT Comparator Function Register 1
0..3 => FUNCTIONrw { //! Function
0 => DISABLED, //= Disabled.
4 => INSTRUCTION_FETCH, //= Instruction fetch.
5 => DATA_OPERAND_READ, //= Data operand read.
6 => DATA_OPERAND_WRITE, //= Data operand write.
7 => E_0111, //= Data operand (read + write).
}
24 => MATCHEDro { //! Comparator match
0 => NO_MATCH, //= No match.
1 => MATCH_OCCURRED, //= Match occurred.
}
},
0x200 => reg32 TBCTRL { //! MTB_DWT Trace Buffer Control Register
0 => ACOMP0rw { //! Action based on Comparator 0 match
0 => TRIGGER_TSTOP_BASED_ON_THE_ASSERTION_OF_MTBDWT_FCT0[MATCHED], //= Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
1 => TRIGGER_TSTART_BASED_ON_THE_ASSERTION_OF_MTBDWT_FCT0[MATCHED], //= Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
}
1 => ACOMP1rw { //! Action based on Comparator 1 match
0 => TRIGGER_TSTOP_BASED_ON_THE_ASSERTION_OF_MTBDWT_FCT1[MATCHED], //= Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
1 => TRIGGER_TSTART_BASED_ON_THE_ASSERTION_OF_MTBDWT_FCT1[MATCHED], //= Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
}
28..31 => NUMCOMP ro, //= Number of Comparators
},
0xFC8 => reg32 DEVICECFG { //! Device Configuration Register
0..31 => DEVICECFG ro, //= no description available
},
0xFCC => reg32 DEVICETYPID { //! Device Type Identifier Register
0..31 => DEVICETYPID ro, //= no description available
},
0xFD0 => reg32 PERIPHID%s { //! Peripheral ID Register
0..31 => PERIPHID ro, //= no description available
},
0xFF0 => reg32 COMPID%s { //! Component ID Register
0..31 => COMPID ro, //= Component ID
},
});
ioregs!(ROM @ 0xF0002000 = { //! System ROM
0x00 => reg32 ENTRY%s { //! Entry
0..31 => ENTRY ro, //= ENTRY
},
0x0C => reg32 TABLEMARK { //! End of Table Marker Register
0..31 => MARK ro, //= no description available
},
0xFCC => reg32 SYSACCESS { //! System Access Register
0..31 => SYSACCESS ro, //= no description available
},
0xFD0 => reg32 PERIPHID%s { //! Peripheral ID Register
0..31 => PERIPHID ro, //= no description available
},
0xFF0 => reg32 COMPID%s { //! Component ID Register
0..31 => COMPID ro, //= Component ID
},
});
ioregs!(MCM @ 0xF0003000 = { //! Core Platform Miscellaneous Control Module
0x08 => reg16 PLASC { //! Crossbar Switch (AXBS) Slave Configuration
0..7 => ASCro { //! Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
0 => A_BUS_SLAVE_CONNECTION_TO_AXBS_INPUT_PORT_N_IS_ABSENT, //= A bus slave connection to AXBS input port n is absent
1 => A_BUS_SLAVE_CONNECTION_TO_AXBS_INPUT_PORT_N_IS_PRESENT, //= A bus slave connection to AXBS input port n is present
}
},
0x0A => reg16 PLAMC { //! Crossbar Switch (AXBS) Master Configuration
0..7 => AMCro { //! Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
0 => A_BUS_MASTER_CONNECTION_TO_AXBS_INPUT_PORT_N_IS_ABSENT, //= A bus master connection to AXBS input port n is absent
1 => A_BUS_MASTER_CONNECTION_TO_AXBS_INPUT_PORT_N_IS_PRESENT, //= A bus master connection to AXBS input port n is present
}
},
0x0C => reg32 PLACR { //! Platform Control Register
9 => ARBrw { //! Arbitration select
0 => FIXED_PRIORITY_ARBITRATION_FOR_THE_CROSSBAR_MASTERS, //= Fixed-priority arbitration for the crossbar masters
1 => ROUND_ROBIN_ARBITRATION_FOR_THE_CROSSBAR_MASTERS, //= Round-robin arbitration for the crossbar masters
}
10 => CFCC wo, //= Clear Flash Controller Cache
11 => DFCDArw { //! Disable Flash Controller Data Caching
0 => ENABLE_FLASH_CONTROLLER_DATA_CACHING, //= Enable flash controller data caching
1 => DISABLE_FLASH_CONTROLLER_DATA_CACHING, //= Disable flash controller data caching.
}
12 => DFCICrw { //! Disable Flash Controller Instruction Caching
0 => ENABLE_FLASH_CONTROLLER_INSTRUCTION_CACHING, //= Enable flash controller instruction caching.
1 => DISABLE_FLASH_CONTROLLER_INSTRUCTION_CACHING, //= Disable flash controller instruction caching.
}
13 => DFCCrw { //! Disable Flash Controller Cache
0 => ENABLE_FLASH_CONTROLLER_CACHE, //= Enable flash controller cache.
1 => DISABLE_FLASH_CONTROLLER_CACHE, //= Disable flash controller cache.
}
14 => EFDSrw { //! Enable Flash Data Speculation
0 => DISABLE_FLASH_DATA_SPECULATION, //= Disable flash data speculation.
1 => ENABLE_FLASH_DATA_SPECULATION, //= Enable flash data speculation.
}
15 => DFCSrw { //! Disable Flash Controller Speculation
0 => ENABLE_FLASH_CONTROLLER_SPECULATION, //= Enable flash controller speculation.
1 => DISABLE_FLASH_CONTROLLER_SPECULATION, //= Disable flash controller speculation.
}
16 => ESFCrw { //! Enable Stalling Flash Controller
0 => DISABLE_STALLING_FLASH_CONTROLLER_WHEN_FLASH_IS_BUSY, //= Disable stalling flash controller when flash is busy.
1 => ENABLE_STALLING_FLASH_CONTROLLER_WHEN_FLASH_IS_BUSY, //= Enable stalling flash controller when flash is busy.
}
},
0x40 => reg32 CPO { //! Compute Operation Control Register
0 => CPOREQrw { //! Compute Operation request
0 => REQUEST_IS_CLEARED, //= Request is cleared.
1 => REQUEST_COMPUTE_OPERATION, //= Request Compute Operation.
}
1 => CPOACKro { //! Compute Operation acknowledge
0 => COMPUTE_OPERATION_ENTRY_HAS_NOT_COMPLETED_OR_COMPUTE_OPERATION_EXIT_HAS_COMPLETED, //= Compute operation entry has not completed or compute operation exit has completed.
1 => COMPUTE_OPERATION_ENTRY_HAS_COMPLETED_OR_COMPUTE_OPERATION_EXIT_HAS_NOT_COMPLETED, //= Compute operation entry has completed or compute operation exit has not completed.
}
2 => CPOWOIrw { //! Compute Operation wakeup on interrupt
0 => NO_EFFECT, //= No effect.
1 => WHEN_SET_THE_CPOREQ_IS_CLEARED_ON_ANY_INTERRUPT_OR_EXCEPTION_VECTOR_FETCH, //= When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
}
},
});
ioregs!(FGPIOA @ 0xF80FF000 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
ioregs!(FGPIOB @ 0xF80FF040 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
ioregs!(FGPIOC @ 0xF80FF080 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
ioregs!(FGPIOD @ 0xF80FF0C0 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
ioregs!(FGPIOE @ 0xF80FF100 = { //! General Purpose Input/Output
0x00 => reg32 PDOR { //! Port Data Output Register
0..31 => PDOrw { //! Port Data Output
0 => LOGIC_LEVEL_0_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 => LOGIC_LEVEL_1_IS_DRIVEN_ON_PIN_PROVIDED_PIN_IS_CONFIGURED_FOR_GENERAL_PURPOSE_OUTPUT, //= Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
}
},
0x04 => reg32 PSOR { //! Port Set Output Register
0..31 => PTSOwo { //! Port Set Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_LOGIC_1, //= Corresponding bit in PDORn is set to logic 1.
}
},
0x08 => reg32 PCOR { //! Port Clear Output Register
0..31 => PTCOwo { //! Port Clear Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_CLEARED_TO_LOGIC_0, //= Corresponding bit in PDORn is cleared to logic 0.
}
},
0x0C => reg32 PTOR { //! Port Toggle Output Register
0..31 => PTTOwo { //! Port Toggle Output
0 => CORRESPONDING_BIT_IN_PDORN_DOES_NOT_CHANGE, //= Corresponding bit in PDORn does not change.
1 => CORRESPONDING_BIT_IN_PDORN_IS_SET_TO_THE_INVERSE_OF_ITS_EXISTING_LOGIC_STATE, //= Corresponding bit in PDORn is set to the inverse of its existing logic state.
}
},
0x10 => reg32 PDIR { //! Port Data Input Register
0..31 => PDIro { //! Port Data Input
0 => PIN_LOGIC_LEVEL_IS_LOGIC_0_OR_IS_NOT_CONFIGURED_FOR_USE_BY_DIGITAL_FUNCTION, //= Pin logic level is logic 0, or is not configured for use by digital function.
1 => PIN_LOGIC_LEVEL_IS_LOGIC_1, //= Pin logic level is logic 1.
}
},
0x14 => reg32 PDDR { //! Port Data Direction Register
0..31 => PDDrw { //! Port Data Direction
0 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_INPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose input, for the GPIO function.
1 => PIN_IS_CONFIGURED_AS_GENERAL_PURPOSE_OUTPUT_FOR_THE_GPIO_FUNCTION, //= Pin is configured as general-purpose output, for the GPIO function.
}
},
});
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