blink-rainbow.diff

diff --git a/hdl/verilog/blink/blink.v b/hdl/verilog/blink/blink.v
index 1e09f5b..c2875df 100644
--- a/hdl/verilog/blink/blink.v
+++ b/hdl/verilog/blink/blink.v
@@ -1,83 +1,150 @@
 // Simple tri-colour LED blink example.
 
 // Correctly map pins for the iCE40UP5K SB_RGBA_DRV hard macro.
-// The variables EVT, PVT and HACKER are set from the Makefile.
-`ifdef EVT
-`define BLUEPWM  RGB0PWM
-`define REDPWM   RGB1PWM
-`define GREENPWM RGB2PWM
-`elsif HACKER
-`define BLUEPWM  RGB0PWM
-`define GREENPWM RGB1PWM
-`define REDPWM   RGB2PWM
-`elsif PVT
-`define GREENPWM RGB0PWM
-`define REDPWM   RGB1PWM
-`define BLUEPWM  RGB2PWM
-`else
-`error_board_not_supported
-`endif
+// The variables EVT, PVT and HACKER are set from the Makefilen.
+
+`include "hsv2rgb.v"
+
+module counter1536 (
+                  input wire         clk,
+                  output wire [0:15] v);
+   reg [31:0]                        counter = 0;
+   always @(posedge clk) begin
+      if (v < 1535)
+        counter <= counter + 1;
+      else
+        counter <= 0;
+   end
+   assign v = {5'b0, counter[26:16]};
+endmodule
+
+module rainbow (
+                input wire        clk,
+                output wire [0:7] r,
+                output wire [0:7] g,
+                output wire [0:7] b);
+
+   wire [15:0]                    n;
+   counter1536 counter_1(clk, n);
+
+   wire [15:0]                    h = n;
+   wire [7:0]                     s = 255;
+   wire [7:0]                     v = 255;
 
+   wire [23:0]                    rgb;
+   __hsv2rgb__hsv2rgb hsv2rgb_1(h, s, v, rgb);
+   assign r = rgb[23:16];
+   assign g = rgb[15:8];
+   assign b = rgb[7:0];
+endmodule // rainbow
+
+module clockdiv(
+                input wire      clki,
+                input wire [7:0] d,
+                output reg clko);
+   reg [31:0]               counter = 0;
+   wire [7:0] v = counter[15:8];
+   always @(posedge clki) begin
+      counter <= counter + 1;
+      if ((255 - v) <= d) clko <= 1;
+      else clko <= 0;
+   end
+endmodule
+
+`ifndef DEBUG
 module top (
-    // 48MHz Clock input
-    // --------
-    input clki,
-    // LED outputs
-    // --------
-    output rgb0,
-    output rgb1,
-    output rgb2,
-    // USB Pins (which should be statically driven if not being used).
-    // --------
-    output usb_dp,
-    output usb_dn,
-    output usb_dp_pu
-);
+            // 48MHz Clock input
+            // --------
+            input  clki,
+            // LED outputs
+            // --------
+            output rgb0,
+            output rgb1,
+            output rgb2,
+            // USB Pins (which should be statically driven if not being used).
+            // --------
+            output usb_dp,
+            output usb_dn,
+            output usb_dp_pu
+            );
 
-    // Assign USB pins to "0" so as to disconnect Fomu from
-    // the host system.  Otherwise it would try to talk to
-    // us over USB, which wouldn't work since we have no stack.
-    assign usb_dp = 1'b0;
-    assign usb_dn = 1'b0;
-    assign usb_dp_pu = 1'b0;
+   // Assign USB pins to "0" so as to disconnect Fomu from
+   // the host system.  Otherwise it would try to talk to
+   // us over USB, which wouldn't work since we have no stack.
+   assign usb_dp = 1'b0;
+   assign usb_dn = 1'b0;
+   assign usb_dp_pu = 1'b0;
 
-    // Connect to system clock (with buffering)
-    wire clk;
-    SB_GB clk_gb (
-        .USER_SIGNAL_TO_GLOBAL_BUFFER(clki),
-        .GLOBAL_BUFFER_OUTPUT(clk)
-    );
+   // Connect to system clock (with buffering)
+   wire            clk;
+   SB_GB clk_gb (
+                 .USER_SIGNAL_TO_GLOBAL_BUFFER(clki),
+                 .GLOBAL_BUFFER_OUTPUT(clk)
+                 );
 
-    // Use counter logic to divide system clock.  The clock is 48 MHz,
-    // so we divide it down by 2^28.
-    reg [28:0] counter = 0;
-    always @(posedge clk) begin
-        counter <= counter + 1;
-    end
+   wire [0:7]      r;
+   wire [0:7]      g;
+   wire [0:7]      b;
+   rainbow rainbow_1(clki, r, g, b);
+   wire            clkr;
+   wire            clkg;
+   wire            clkb;
+   clockdiv clockdiv_r(clki, r, clkr);
+   clockdiv clockdiv_g(clki, g, clkg);
+   clockdiv clockdiv_b(clki, b, clkb);   
 
-    // Instantiate iCE40 LED driver hard logic, connecting up
-    // counter state and LEDs.
-    //
-    // Note that it's possible to drive the LEDs directly,
-    // however that is not current-limited and results in
-    // overvolting the red LED.
-    //
-    // See also:
-    // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/IK/ICE40LEDDriverUsageGuide.ashx?document_id=50668
-    SB_RGBA_DRV #(
-        .CURRENT_MODE("0b1"),       // half current
-        .RGB0_CURRENT("0b000011"),  // 4 mA
-        .RGB1_CURRENT("0b000011"),  // 4 mA
-        .RGB2_CURRENT("0b000011")   // 4 mA
-    ) RGBA_DRIVER (
-        .CURREN(1'b1),
-        .RGBLEDEN(1'b1),
-        .`BLUEPWM(counter[25]),     // Blue
-        .`REDPWM(counter[24]),      // Red
-        .`GREENPWM(counter[23]),    // Green
-        .RGB0(rgb0),
-        .RGB1(rgb1),
-        .RGB2(rgb2)
-    );
+   // Instantiate iCE40 LED driver hard logic, connecting up
+   // counter state and LEDs.
+   //
+   // Note that it's possible to drive the LEDs directly,
+   // however that is not current-limited and results in
+   // overvolting the red LED.
+   //
+   // See also:
+   // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/IK/ICE40LEDDriverUsageGuide.ashx?document_id=50668
+   SB_RGBA_DRV #(
+                 .CURRENT_MODE("0b1"),       // half current
+                 .RGB0_CURRENT("0b000011"),  // 4 mA
+                 .RGB1_CURRENT("0b000011"),  // 4 mA
+                 .RGB2_CURRENT("0b000011")   // 4 mA
+                 ) RGBA_DRIVER (
+                                .CURREN(1'b1),
+                                .RGBLEDEN(1'b1),
+                                .RGB2PWM(clkb),   // Blue
+                                .RGB1PWM(clkr),   // Red
+                                .RGB0PWM(clkg),   // Green
+                                .RGB0(rgb0),
+                                .RGB1(rgb1),
+                                .RGB2(rgb2)
+                                );
 
 endmodule
+`endif
+
+`ifdef DEBUG
+module testbench;
+   reg clk;
+   always #5 clk = ~clk;
+   wire [7:0] r;
+   wire [7:0] g;
+   wire [7:0] b;
+   //wire [15:0] n;
+   //counter1536 counter_1(clk, n);
+   //rainbow rainbow_1(clk, r, g, b);
+   wire       clkd;
+   wire [7:0] div = 127;
+   clockdiv clockdiv_1(clk, div, clkd);
+   reg [7:0]                        counter = 0;
+   always @(posedge clk) begin
+      counter <= counter + 1;
+   end
+   initial begin
+      //$dumpfile("blink.vcd");
+      //$dumpvars(0, testbench);
+      #5 clk = 0;
+      //$monitor("counter %d %b", n, n);
+      //$monitor("rainbow %d %d %d", r, g, b);
+      $monitor("clockdiv %d %d %d", counter, clk, clkd);
+   end
+endmodule // testbench
+`endif