Skip to content

Instantly share code, notes, and snippets.

@pvieito
Created May 28, 2016 14:16
  • Star 2 You must be signed in to star a gist
  • Fork 1 You must be signed in to fork a gist
Star You must be signed in to star a gist
Save pvieito/b0796265c93c8aff3bdfb5a38793e44c to your computer and use it in GitHub Desktop.
Generate sine waves for a VHDL test bench.
#!/usr/bin/env python3
'''VHDLSinGenerator.py - Pedro José Pereira Vieito © 2016
Generate sine waves for a VHDL test bench.
Usage:
VHDLSinGenerator.py <sample_bits> <wave_bits>
Options:
-h, --help show this help
'''
import math
from docopt import docopt
__author__ = "Pedro José Pereira Vieito"
__email__ = "pvieito@gmail.com"
args = docopt(__doc__)
sample_bits = int(args['<sample_bits>'])
wave_bits = int(args['<wave_bits>'])
samples = 2 ** sample_bits
wave_amp = 2 ** (wave_bits - 1)
print('-- Auxiliary signals')
print('signal table_counter : std_logic_vector(' + str(sample_bits - 1) +
' downto 0) := "' + '0' * sample_bits + '";')
print('signal table_value : std_logic_vector(' + str(wave_bits - 1) +
' downto 0) := "' + '0' * wave_bits + '";\n')
print('-- Sine wave table')
print('table_value <= ', end='')
for i in range(samples):
new_sample = int(wave_amp + (wave_amp - 1) *
math.sin(2 * math.pi * i / samples))
print('"' + bin(new_sample)[2:].zfill(wave_bits) +
'" when table_counter =', i, end='')
if i == samples - 1:
print(";")
else:
print(" else")
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment