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rbreslow/cbmem_last_boot.txt Secret

Created January 20, 2023 21:36
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cbmem logs for T440p with CBFS_SIZE set 0xBDEFFF
Raw
cbmem_last_boot.txt
*** Pre-CBMEM romstage console overflowed, log truncated! ***
ting (log level: 7)...
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x40000.
[DEBUG] FMAP: base = 0xff400000 size = 0xc00000 #areas = 4
[DEBUG] FMAP: area COREBOOT found @ 40200 (12320256 bytes)
[INFO ] CBFS: mcache @0xff7c3600 built for 18 files, used 0x3e8 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0xa648 in mcache @0xff7c362c
[INFO ] TCPA: Clearing coreboot TCPA log
[DEBUG] FMAP: area FMAP found @ 40000 (512 bytes)
[DEBUG] TPM: Digest of `FMAP: FMAP` to PCR 2 logged
[INFO ] CBFS: Found 'bootblock' @0xbb9d40 size 0x6080 in mcache @0xff7c39a4
[DEBUG] TPM: Digest of `CBFS: bootblock` to PCR 2 logged
[DEBUG] CRTM initialized.
[DEBUG] TPM: Digest of `CBFS: fallback/romstage` to PCR 2 logged
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 0 ms
[NOTE ] coreboot--TIMELESS--LESSTIME--Heads- Thu Jan 1 00:00:00 UTC 1970 romstage starting (log level: 7)...
[DEBUG] Disabling Watchdog reboot... done.
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done.
[DEBUG] Started PEG11 link training.
[DEBUG] Temporarily hiding PEG11.
[DEBUG] Started PEG10 link training.
[DEBUG] Temporarily hiding PEG10.
[DEBUG] Initializing IGD...
[DEBUG] Back from haswell_early_initialization()
[DEBUG] CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i7-4910MQ CPU @ 2.90GHz
[DEBUG] AES supported, TXT supported, VT supported
[DEBUG] PCH type: QM87, device id: 8c4f, rev id 5
[DEBUG] Starting UEFI PEI System Agent
[DEBUG] FMAP: area RW_MRC_CACHE found @ 30000 (65536 bytes)
[DEBUG] prepare_mrc_cache: at 0xff433ff0, size fd4
[DEBUG] FMAP: area COREBOOT found @ 40200 (12320256 bytes)
[INFO ] CBFS: Found 'mrc.bin' @0xb5fdc0 size 0x2e6e4 in mcache @0xff7c38bc
[DEBUG] TPM: Digest of `CBFS: mrc.bin` to PCR 2 logged
System Agent: Starting up...
System Agent: Initializing PCH
install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845}
install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276}
System Agent: Initializing PCH (SMBUS)
System Agent: Initializing PCH (USB)
System Agent: Initializing PCH (SA Init)
System Agent: Initializing PCH (Me UMA)
System Agent: Initializing Memory
System Agent: Done.
Sanity checking heap.
[DEBUG] MRC Version 1.6.1 Build 2
[DEBUG] memcfg DDR3 clock 1600 MHz
[DEBUG] memcfg channel assignment: A: 0, B 1, C 2
[DEBUG] memcfg channel[0] config (00620020):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode on
[DEBUG] rank interleave on
[DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected
[DEBUG] DIMMB 0 MB width x8 or x32 single rank
[DEBUG] memcfg channel[1] config (00620020):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode on
[DEBUG] rank interleave on
[DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected
[DEBUG] DIMMB 0 MB width x8 or x32 single rank
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : YES
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Initializing
[DEBUG] ME: Current Operation State : Bring up
[DEBUG] ME: Current Operation Mode : Debug
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
[DEBUG] ME: Progress Phase State : 0x4d
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x7f7ff000 254 entries.
[DEBUG] IMD: root @ 0x7f7fec00 62 entries.
[DEBUG] External stage cache:
[DEBUG] IMD: root @ 0x7fbff000 254 entries.
[DEBUG] IMD: root @ 0x7fbfec00 62 entries.
[DEBUG] Unhiding PEG10.
[DEBUG] Unhiding PEG11.
[DEBUG] SMM Memory Map
[DEBUG] SMRAM : 0x7f800000 0x800000
[DEBUG] Subregion 0: 0x7f800000 0x300000
[DEBUG] Subregion 1: 0x7fb00000 0x100000
[DEBUG] Subregion 2: 0x7fc00000 0x400000
[DEBUG] Normal boot
[INFO ] CBFS: Found 'fallback/postcar' @0x37ec0 size 0x6aa8 in mcache @0xff7c384c
[DEBUG] TPM: Digest of `CBFS: fallback/postcar` to PCR 2 logged
[DEBUG] Loading module at 0x7f7cb000 with entry 0x7f7cb031. filesize: 0x6620 memsize: 0xc960
[DEBUG] Processing 274 relocs. Offset value of 0x7d7cb000
[DEBUG] BS: romstage times (exec / console): total (unknown) / 388 ms
[NOTE ] coreboot--TIMELESS--LESSTIME--Heads- Thu Jan 1 00:00:00 UTC 1970 postcar starting (log level: 7)...
[DEBUG] Normal boot
[DEBUG] FMAP: area COREBOOT found @ 40200 (12320256 bytes)
[INFO ] CBFS: Found 'fallback/ramstage' @0x15c40 size 0x1d85e in mcache @0x7f7dd10c
[DEBUG] TPM: Digest of `CBFS: fallback/ramstage` to PCR 2 logged
[DEBUG] Loading module at 0x7f76e000 with entry 0x7f76e000. filesize: 0x3c0c0 memsize: 0x5be70
[DEBUG] Processing 4383 relocs. Offset value of 0x7b76e000
[DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
[NOTE ] coreboot--TIMELESS--LESSTIME--Heads- Thu Jan 1 00:00:00 UTC 1970 ramstage starting (log level: 7)...
[DEBUG] Normal boot
[INFO ] Enumerating buses...
[DEBUG] Root Device scanning...
[DEBUG] CPU_CLUSTER: 0 enabled
[DEBUG] DOMAIN: 0000 enabled
[DEBUG] DOMAIN: 0000 scanning...
[DEBUG] PCI: pci_scan_bus for bus 00
[DEBUG] PCI: 00:00.0 [8086/0c04] enabled
[INFO ] PCI: Static device PCI: 00:01.0 not found, disabling it.
[DEBUG] PCI: 00:01.1 [8086/0c05] disabled
[DEBUG] PCI: 00:02.0 [8086/0416] enabled
[DEBUG] PCI: 00:03.0 [8086/0c0c] enabled
[DEBUG] PCI: 00:04.0 [8086/0c03] enabled
[DEBUG] PCI: 00:14.0 [8086/8c31] enabled
[DEBUG] PCI: 00:16.0 [8086/8c3a] enabled
[DEBUG] PCI: 00:16.1: Disabling device
[DEBUG] PCI: 00:16.2: Disabling device
[DEBUG] PCI: 00:16.3: Disabling device
[DEBUG] PCI: 00:19.0 [8086/153a] enabled
[DEBUG] PCI: 00:1a.0 [8086/8c2d] enabled
[DEBUG] PCI: 00:1b.0 [8086/8c20] enabled
[DEBUG] PCIe Root Port 1 ASPM is disabled
[DEBUG] PCI: 00:1c.0 [8086/8c10] enabled
[DEBUG] PCIe Root Port 2 ASPM is disabled
[DEBUG] PCI: 00:1c.1 [8086/8c12] enabled
[DEBUG] PCI: 00:1c.2 [8086/8c14] disabled
[DEBUG] PCI: 00:1c.3 [8086/8c16] disabled
[DEBUG] Adjusted number of PCIe root ports to 5 as per strpfusecfg2
[DEBUG] PCI: 00:1c.2: Disabling device
[DEBUG] PCI: 00:1c.3: Disabling device
[DEBUG] PCI: 00:1c.4: Disabling device
[DEBUG] PCI: 00:1c.4 [8086/8c18] disabled
[DEBUG] PCI: 00:1d.0 [8086/8c26] enabled
[DEBUG] PCI: 00:1f.0 [8086/8c4f] enabled
[DEBUG] PCI: 00:1f.2 [8086/8c03] enabled
[DEBUG] PCI: 00:1f.3 [8086/8c22] enabled
[DEBUG] PCI: 00:1f.5: Disabling device
[DEBUG] PCI: 00:1f.6: Disabling device
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 00:01.0
[WARN ] PCI: 00:16.1
[WARN ] PCI: 00:16.2
[WARN ] PCI: 00:16.3
[WARN ] PCI: 00:1c.5
[WARN ] PCI: 00:1c.6
[WARN ] PCI: 00:1c.7
[WARN ] PCI: 00:1f.5
[WARN ] PCI: 00:1f.6
[WARN ] PCI: Check your devicetree.cb.
[DEBUG] PCI: 00:1c.0 scanning...
[DEBUG] PCI: pci_scan_bus for bus 01
[DEBUG] PCI: 01:00.0 [10ec/5227] enabled
[INFO ] Enabling Common Clock Configuration
[INFO ] ASPM: Enabled L0s and L1
[INFO ] PCIe: Max_Payload_Size adjusted to 128
[INFO ] PCI: 01:00.0: Enabled LTR
[DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
[DEBUG] PCI: 00:1c.1 scanning...
[DEBUG] PCI: pci_scan_bus for bus 02
[DEBUG] PCI: 02:00.0 [8086/08b2] enabled
[DEBUG] PCI: 02:00.0 scanning...
[DEBUG] scan_bus: bus PCI: 02:00.0 finished in 0 msecs
[INFO ] Enabling Common Clock Configuration
[INFO ] ASPM: Enabled L1
[INFO ] PCIe: Max_Payload_Size adjusted to 128
[INFO ] PCI: 02:00.0: Enabled LTR
[DEBUG] scan_bus: bus PCI: 00:1c.1 finished in 0 msecs
[DEBUG] PCI: 00:1f.0 scanning...
[INFO ] PMH7: ID 05 Revision 12
[DEBUG] PNP: 00ff.1 enabled
[INFO ] H8: EC Firmware ID GLHT30WW-3.23, Version 3.01B
[INFO ] H8: BDC detection not implemented. Assuming BDC installed
[INFO ] H8: WWAN detection not implemented. Assuming WWAN installed
[DEBUG] PNP: 00ff.2 enabled
[DEBUG] PNP: 0c31.0 enabled
[DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 4 msecs
[DEBUG] PCI: 00:1f.3 scanning...
[DEBUG] scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
[DEBUG] scan_bus: bus DOMAIN: 0000 finished in 5 msecs
[DEBUG] scan_bus: bus Root Device finished in 5 msecs
[INFO ] done
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 5 / 0 ms
[DEBUG] FMAP: area RW_MRC_CACHE found @ 30000 (65536 bytes)
[DEBUG] FMAP: area RW_MRC_CACHE found @ 30000 (65536 bytes)
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG] flash size 0x2800000 bytes
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2800000
[ERROR] SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!!
[DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 3 / 0 ms
[DEBUG] found VGA at PCI: 00:02.0
[DEBUG] Setting up VGA for PCI: 00:02.0
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ] Allocating resources...
[INFO ] Reading resources...
[DEBUG] mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff.
[DEBUG] mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff.
[DEBUG] mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff.
[DEBUG] mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff.
[DEBUG] mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff.
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
[DEBUG] MC MAP: TOM: 0x400000000
[DEBUG] MC MAP: TOUUD: 0x47de00000
[DEBUG] MC MAP: MESEG_BASE: 0x7ffff00000
[DEBUG] MC MAP: MESEG_LIMIT: 0xfffff
[DEBUG] MC MAP: REMAP_BASE: 0x400000000
[DEBUG] MC MAP: REMAP_LIMIT: 0x47ddfffff
[DEBUG] MC MAP: TOLUD: 0x82200000
[DEBUG] MC MAP: BGSM: 0x80000000
[DEBUG] MC MAP: BDSM: 0x80200000
[DEBUG] MC MAP: TSEGMB: 0x7f800000
[DEBUG] MC MAP: GGC: 0x209
[DEBUG] MC MAP: DPR: 0x7f800001
[ERROR] PNP: 00ff.1 missing read_resources
[ERROR] PNP: 00ff.2 missing read_resources
[INFO ] Done reading resources.
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
[DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 01:00.0 10 * [0x0 - 0xfff] mem
[DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 02:00.0 10 * [0x0 - 0x1fff] mem
[DEBUG] PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
[DEBUG] update_constraints: PCI: 00:1f.0 84 base 00001600 limit 0000167f io (fixed)
[DEBUG] update_constraints: PCI: 00:1f.0 88 base 000015e0 limit 000015ef io (fixed)
[DEBUG] update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed)
[DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
[INFO ] DOMAIN: 0000: Resource ranges:
[INFO ] * Base: 1000, Size: 5e0, Tag: 100
[INFO ] * Base: 15f0, Size: 10, Tag: 100
[INFO ] * Base: 1680, Size: e980, Tag: 100
[DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
[DEBUG] PCI: 00:19.0 18 * [0x1040 - 0x105f] limit: 105f io
[DEBUG] PCI: 00:1f.2 20 * [0x1060 - 0x107f] limit: 107f io
[DEBUG] PCI: 00:1f.2 10 * [0x1080 - 0x1087] limit: 1087 io
[DEBUG] PCI: 00:1f.2 18 * [0x1088 - 0x108f] limit: 108f io
[DEBUG] PCI: 00:1f.2 14 * [0x1090 - 0x1093] limit: 1093 io
[DEBUG] PCI: 00:1f.2 1c * [0x1094 - 0x1097] limit: 1097 io
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
[DEBUG] update_constraints: PCI: 00:00.0 48 base fed10000 limit fed17fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 68 base fed18000 limit fed18fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 40 base fed19000 limit fed19fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 5420 base fed84000 limit fed84fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 5408 base fed80000 limit fed83fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 00 base fed90000 limit fed90fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 01 base fed91000 limit fed91fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 02 base 00000000 limit 0009ffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 03 base 000c0000 limit 7f7fffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 04 base 7f800000 limit 7fffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 05 base 80000000 limit 821fffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 06 base 100000000 limit 47ddfffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:1f.0 31fe base fec00000 limit ffffffff mem (fixed)
[DEBUG] update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
[INFO ] DOMAIN: 0000: Resource ranges:
[INFO ] * Base: 82200000, Size: 6de00000, Tag: 200
[INFO ] * Base: f4000000, Size: ac00000, Tag: 200
[INFO ] * Base: 47de00000, Size: 7b82200000, Tag: 100200
[DEBUG] PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
[DEBUG] PCI: 00:02.0 10 * [0x82400000 - 0x827fffff] limit: 827fffff mem
[DEBUG] PCI: 00:1c.0 20 * [0x82200000 - 0x822fffff] limit: 822fffff mem
[DEBUG] PCI: 00:1c.1 20 * [0x82300000 - 0x823fffff] limit: 823fffff mem
[DEBUG] PCI: 00:19.0 10 * [0x82800000 - 0x8281ffff] limit: 8281ffff mem
[DEBUG] PCI: 00:14.0 10 * [0x82820000 - 0x8282ffff] limit: 8282ffff mem
[DEBUG] PCI: 00:04.0 10 * [0x82830000 - 0x82837fff] limit: 82837fff mem
[DEBUG] PCI: 00:03.0 10 * [0x82838000 - 0x8283bfff] limit: 8283bfff mem
[DEBUG] PCI: 00:1b.0 10 * [0x8283c000 - 0x8283ffff] limit: 8283ffff mem
[DEBUG] PCI: 00:19.0 14 * [0x82840000 - 0x82840fff] limit: 82840fff mem
[DEBUG] PCI: 00:1f.2 24 * [0x82841000 - 0x828417ff] limit: 828417ff mem
[DEBUG] PCI: 00:1a.0 10 * [0x82842000 - 0x828423ff] limit: 828423ff mem
[DEBUG] PCI: 00:1d.0 10 * [0x82843000 - 0x828433ff] limit: 828433ff mem
[DEBUG] PCI: 00:1f.3 10 * [0x82844000 - 0x828440ff] limit: 828440ff mem
[DEBUG] PCI: 00:16.0 10 * [0x82845000 - 0x8284500f] limit: 8284500f mem
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
[DEBUG] PCI: 00:1c.0 mem: base: 82200000 size: 100000 align: 20 gran: 20 limit: 822fffff
[INFO ] PCI: 00:1c.0: Resource ranges:
[INFO ] * Base: 82200000, Size: 100000, Tag: 200
[DEBUG] PCI: 01:00.0 10 * [0x82200000 - 0x82200fff] limit: 82200fff mem
[DEBUG] PCI: 00:1c.0 mem: base: 82200000 size: 100000 align: 20 gran: 20 limit: 822fffff done
[DEBUG] PCI: 00:1c.1 mem: base: 82300000 size: 100000 align: 20 gran: 20 limit: 823fffff
[INFO ] PCI: 00:1c.1: Resource ranges:
[INFO ] * Base: 82300000, Size: 100000, Tag: 200
[DEBUG] PCI: 02:00.0 10 * [0x82300000 - 0x82301fff] limit: 82301fff mem
[DEBUG] PCI: 00:1c.1 mem: base: 82300000 size: 100000 align: 20 gran: 20 limit: 823fffff done
[INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
[DEBUG] PCI: 00:02.0 10 <- [0x0082400000 - 0x00827fffff] size 0x00400000 gran 0x16 mem64
[DEBUG] PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG] PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
[DEBUG] PCI: 00:03.0 10 <- [0x0082838000 - 0x008283bfff] size 0x00004000 gran 0x0e mem64
[DEBUG] PCI: 00:04.0 10 <- [0x0082830000 - 0x0082837fff] size 0x00008000 gran 0x0f mem64
[DEBUG] PCI: 00:14.0 10 <- [0x0082820000 - 0x008282ffff] size 0x00010000 gran 0x10 mem64
[DEBUG] PCI: 00:16.0 10 <- [0x0082845000 - 0x008284500f] size 0x00000010 gran 0x04 mem64
[DEBUG] PCI: 00:19.0 10 <- [0x0082800000 - 0x008281ffff] size 0x00020000 gran 0x11 mem
[DEBUG] PCI: 00:19.0 14 <- [0x0082840000 - 0x0082840fff] size 0x00001000 gran 0x0c mem
[DEBUG] PCI: 00:19.0 18 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
[DEBUG] PCI: 00:1a.0 10 <- [0x0082842000 - 0x00828423ff] size 0x00000400 gran 0x0a mem
[DEBUG] PCI: 00:1b.0 10 <- [0x008283c000 - 0x008283ffff] size 0x00004000 gran 0x0e mem64
[DEBUG] PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
[DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
[DEBUG] PCI: 00:1c.0 20 <- [0x0082200000 - 0x00822fffff] size 0x00100000 gran 0x14 bus 01 mem
[DEBUG] PCI: 01:00.0 10 <- [0x0082200000 - 0x0082200fff] size 0x00001000 gran 0x0c mem
[DEBUG] PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
[DEBUG] PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
[DEBUG] PCI: 00:1c.1 20 <- [0x0082300000 - 0x00823fffff] size 0x00100000 gran 0x14 bus 02 mem
[DEBUG] PCI: 02:00.0 10 <- [0x0082300000 - 0x0082301fff] size 0x00002000 gran 0x0d mem64
[DEBUG] PCI: 00:1d.0 10 <- [0x0082843000 - 0x00828433ff] size 0x00000400 gran 0x0a mem
[ERROR] PNP: 00ff.1 missing set_resources
[ERROR] PNP: 00ff.2 missing set_resources
[DEBUG] PCI: 00:1f.2 10 <- [0x0000001080 - 0x0000001087] size 0x00000008 gran 0x03 io
[DEBUG] PCI: 00:1f.2 14 <- [0x0000001090 - 0x0000001093] size 0x00000004 gran 0x02 io
[DEBUG] PCI: 00:1f.2 18 <- [0x0000001088 - 0x000000108f] size 0x00000008 gran 0x03 io
[DEBUG] PCI: 00:1f.2 1c <- [0x0000001094 - 0x0000001097] size 0x00000004 gran 0x02 io
[DEBUG] PCI: 00:1f.2 20 <- [0x0000001060 - 0x000000107f] size 0x00000020 gran 0x05 io
[DEBUG] PCI: 00:1f.2 24 <- [0x0082841000 - 0x00828417ff] size 0x00000800 gran 0x0b mem
[DEBUG] PCI: 00:1f.3 10 <- [0x0082844000 - 0x00828440ff] size 0x00000100 gran 0x08 mem64
[INFO ] Done setting resources.
[INFO ] Done allocating resources.
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
[INFO ] Enabling resources...
[DEBUG] PCI: 00:00.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:00.0 cmd <- 06
[DEBUG] PCI: 00:02.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:02.0 cmd <- 03
[DEBUG] PCI: 00:03.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:03.0 cmd <- 02
[DEBUG] PCI: 00:04.0 cmd <- 02
[DEBUG] PCI: 00:14.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:14.0 cmd <- 102
[DEBUG] PCI: 00:16.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:16.0 cmd <- 02
[DEBUG] PCI: 00:19.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:19.0 cmd <- 103
[DEBUG] PCI: 00:1a.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:1a.0 cmd <- 102
[DEBUG] PCI: 00:1b.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:1b.0 cmd <- 102
[DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
[DEBUG] PCI: 00:1c.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:1c.0 cmd <- 06
[DEBUG] PCI: 00:1c.1 bridge ctrl <- 0013
[DEBUG] PCI: 00:1c.1 subsystem <- 17aa/220e
[DEBUG] PCI: 00:1c.1 cmd <- 06
[DEBUG] PCI: 00:1d.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:1d.0 cmd <- 102
[DEBUG] PCI: 00:1f.0 subsystem <- 17aa/220e
[DEBUG] PCI: 00:1f.0 cmd <- 107
[DEBUG] PCI: 00:1f.2 subsystem <- 17aa/220e
[DEBUG] PCI: 00:1f.2 cmd <- 103
[DEBUG] PCI: 00:1f.3 subsystem <- 17aa/220e
[DEBUG] PCI: 00:1f.3 cmd <- 103
[DEBUG] PCI: 01:00.0 cmd <- 02
[DEBUG] PCI: 02:00.0 cmd <- 02
[INFO ] done.
[INFO ] Found TPM ST33ZP24 by ST Microelectronics
[DEBUG] TPM: Startup
[DEBUG] TPM: command 0x99 returned 0x0
[DEBUG] TPM: Asserting physical presence
[DEBUG] TPM: command 0x4000000a returned 0x0
[DEBUG] TPM: command 0x65 returned 0x0
[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
[DEBUG] TPM: Write digests cached in TCPA log to PCR
[DEBUG] TPM: Write digest for FMAP: FMAP into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[DEBUG] TPM: Write digest for CBFS: bootblock into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[DEBUG] TPM: Write digest for CBFS: fallback/romstage into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[DEBUG] TPM: Write digest for CBFS: mrc.bin into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[DEBUG] TPM: Write digest for CBFS: fallback/postcar into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[DEBUG] TPM: Write digest for CBFS: fallback/ramstage into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[INFO ] TPM: setup succeeded
[DEBUG] BS: BS_DEV_INIT entry times (exec / console): 80 / 0 ms
[INFO ] Initializing devices...
[DEBUG] CPU_CLUSTER: 0 init
[DEBUG] MTRR: Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
[DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0
[DEBUG] 0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1
[DEBUG] 0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0
[DEBUG] 0x0000000100000000 - 0x000000047ddfffff size 0x37de00000 type 6
[DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG] CPU physical address size: 39 bits
[DEBUG] MTRR: default type WB/UC MTRR counts: 4/5.
[DEBUG] MTRR: WB selected as default type.
[DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x0000007ff0000000 type 0
[DEBUG] MTRR: 1 base 0x0000000090000000 mask 0x0000007ff0000000 type 1
[DEBUG] MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
[DEBUG] MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
[DEBUG] MTRR check
[DEBUG] Fixed MTRRs : Enabled
[DEBUG] Variable MTRRs: Enabled
[DEBUG] Initializing VR config.
[DEBUG] CPU has 4 cores, 8 threads enabled.
[DEBUG] Setting up SMI for CPU
[INFO ] Will perform SMM setup.
[DEBUG] FMAP: area COREBOOT found @ 40200 (12320256 bytes)
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0xa780 size 0xb400 in mcache @0x7f7dd0ac
[DEBUG] TPM: Extending digest for `CBFS: cpu_microcode_blob.bin` into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[DEBUG] TPM: Digest of `CBFS: cpu_microcode_blob.bin` to PCR 2 measured
[DEBUG] microcode: sig=0x306c3 pf=0x10 revision=0x28
[INFO ] CPU: Intel(R) Core(TM) i7-4910MQ CPU @ 2.90GHz.
[INFO ] LAPIC 0x0 in XAPIC mode.
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG] Processing 18 relocs. Offset value of 0x00030000
[DEBUG] Attempting to start 7 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[DEBUG] Waiting for SIPI to complete...
[INFO ] LAPIC 0x1 in XAPIC mode.
[DEBUG] done.
[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000028
[INFO ] LAPIC 0x2 in XAPIC mode.
[INFO ] LAPIC 0x3 in XAPIC mode.
[INFO ] AP: slot 2 apic_id 2, MCU rev: 0x00000028
[INFO ] AP: slot 3 apic_id 3, MCU rev: 0x00000028
[INFO ] LAPIC 0x4 in XAPIC mode.
[INFO ] LAPIC 0x5 in XAPIC mode.
[INFO ] AP: slot 4 apic_id 4, MCU rev: 0x00000028
[INFO ] AP: slot 5 apic_id 5, MCU rev: 0x00000028
[INFO ] LAPIC 0x7 in XAPIC mode.
[INFO ] LAPIC 0x6 in XAPIC mode.
[INFO ] AP: slot 7 apic_id 7, MCU rev: 0x00000028
[INFO ] AP: slot 6 apic_id 6, MCU rev: 0x00000028
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8
[DEBUG] Processing 11 relocs. Offset value of 0x00038000
[DEBUG] smm_module_setup_stub: stack_top = 0x7f802000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f78d2d5
[DEBUG] Installing permanent SMM handler to 0x7f800000
[DEBUG] fx_save [0x7faff000-0x7fb00000[
[DEBUG] smihandler [0x7fafe000-0x7fafee20[
[DEBUG] -------------NEW CODE SEGMENT --------------
[DEBUG] CPU 0x0
[DEBUG] Stub [0x7faf6000-0x7faf61e8[
[DEBUG] Save state [0x7fafdc00-0x7fafe000[
[DEBUG] CPU 0x1
[DEBUG] Stub [0x7faf5c00-0x7faf5de8[
[DEBUG] Save state [0x7fafd800-0x7fafdc00[
[DEBUG] CPU 0x2
[DEBUG] Stub [0x7faf5800-0x7faf59e8[
[DEBUG] Save state [0x7fafd400-0x7fafd800[
[DEBUG] CPU 0x3
[DEBUG] Stub [0x7faf5400-0x7faf55e8[
[DEBUG] Save state [0x7fafd000-0x7fafd400[
[DEBUG] CPU 0x4
[DEBUG] Stub [0x7faf5000-0x7faf51e8[
[DEBUG] Save state [0x7fafcc00-0x7fafd000[
[DEBUG] CPU 0x5
[DEBUG] Stub [0x7faf4c00-0x7faf4de8[
[DEBUG] Save state [0x7fafc800-0x7fafcc00[
[DEBUG] CPU 0x6
[DEBUG] Stub [0x7faf4800-0x7faf49e8[
[DEBUG] Save state [0x7fafc400-0x7fafc800[
[DEBUG] CPU 0x7
[DEBUG] Stub [0x7faf4400-0x7faf45e8[
[DEBUG] Save state [0x7fafc000-0x7fafc400[
[DEBUG] cpu stacks [0x7f800000-0x7f802000[
[DEBUG] Loading module at 0x7fafe000 with entry 0x7fafe2cc. filesize: 0xe08 memsize: 0xe20
[DEBUG] Processing 56 relocs. Offset value of 0x7fafe000
[DEBUG] Loading module at 0x7faf6000 with entry 0x7faf6000. filesize: 0x1e8 memsize: 0x1e8
[DEBUG] Processing 11 relocs. Offset value of 0x7faf6000
[DEBUG] smm_module_setup_stub: stack_top = 0x7f802000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
[DEBUG] SMM Module: placing smm entry code at 7faf5c00, cpu # 0x1
[DEBUG] smm_place_entry_code: copying from 7faf6000 to 7faf5c00 0x1e8 bytes
[DEBUG] SMM Module: placing smm entry code at 7faf5800, cpu # 0x2
[DEBUG] smm_place_entry_code: copying from 7faf6000 to 7faf5800 0x1e8 bytes
[DEBUG] SMM Module: placing smm entry code at 7faf5400, cpu # 0x3
[DEBUG] smm_place_entry_code: copying from 7faf6000 to 7faf5400 0x1e8 bytes
[DEBUG] SMM Module: placing smm entry code at 7faf5000, cpu # 0x4
[DEBUG] smm_place_entry_code: copying from 7faf6000 to 7faf5000 0x1e8 bytes
[DEBUG] SMM Module: placing smm entry code at 7faf4c00, cpu # 0x5
[DEBUG] smm_place_entry_code: copying from 7faf6000 to 7faf4c00 0x1e8 bytes
[DEBUG] SMM Module: placing smm entry code at 7faf4800, cpu # 0x6
[DEBUG] smm_place_entry_code: copying from 7faf6000 to 7faf4800 0x1e8 bytes
[DEBUG] SMM Module: placing smm entry code at 7faf4400, cpu # 0x7
[DEBUG] smm_place_entry_code: copying from 7faf6000 to 7faf4400 0x1e8 bytes
[DEBUG] SMM Module: stub loaded at 7faf6000. Will call 0x7fafe2cc
[DEBUG] Initializing Southbridge SMI...
[DEBUG] SMI_STS: MCSMI PM1
[DEBUG] WAK PWRBTN TMROF smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faee000, cpu = 0
[DEBUG] In relocation handler: CPU 0
[DEBUG] New SMBASE=0x7faee000 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faedc00, cpu = 1
[DEBUG] In relocation handler: CPU 1
[DEBUG] New SMBASE=0x7faedc00 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faec400, cpu = 7
[DEBUG] In relocation handler: CPU 7
[DEBUG] New SMBASE=0x7faec400 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faec800, cpu = 6
[DEBUG] In relocation handler: CPU 6
[DEBUG] New SMBASE=0x7faec800 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faecc00, cpu = 5
[DEBUG] In relocation handler: CPU 5
[DEBUG] New SMBASE=0x7faecc00 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faed000, cpu = 4
[DEBUG] In relocation handler: CPU 4
[DEBUG] New SMBASE=0x7faed000 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faed800, cpu = 2
[DEBUG] In relocation handler: CPU 2
[DEBUG] New SMBASE=0x7faed800 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faed400, cpu = 3
[DEBUG] In relocation handler: CPU 3
[DEBUG] New SMBASE=0x7faed400 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor Intel device 306c3
[DEBUG] CPU: family 06, model 3c, stepping 03
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] cpu: energy policy set to 6
[INFO ] Turbo is available but hidden
[INFO ] Turbo is available and visible
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #1
[INFO ] Initializing CPU #3
[INFO ] Initializing CPU #2
[INFO ] Initializing CPU #4
[INFO ] Initializing CPU #5
[DEBUG] CPU: vendor Intel device 306c3
[DEBUG] CPU: family 06, model 3c, stepping 03
[DEBUG] CPU: vendor Intel device 306c3
[DEBUG] CPU: family 06, model 3c, stepping 03
[DEBUG] CPU: vendor Intel device 306c3
[DEBUG] CPU: family 06, model 3c, stepping 03
[INFO ] Initializing CPU #7
[INFO ] Initializing CPU #6
[DEBUG] CPU: vendor Intel device 306c3
[DEBUG] CPU: family 06, model 3c, stepping 03
[DEBUG] CPU: vendor Intel device 306c3
[DEBUG] VMX status: enabled
[DEBUG] CPU: family 06, model 3c, stepping 03
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] VMX status: enabled
[DEBUG] CPU: vendor Intel device 306c3
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] CPU: family 06, model 3c, stepping 03
[DEBUG] CPU: vendor Intel device 306c3
[DEBUG] CPU: family 06, model 3c, stepping 03
[DEBUG] VMX status: enabled
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] cpu: energy policy set to 6
[DEBUG] IA32_FEATURE_CONTROL status: locked
[INFO ] CPU #4 initialized
[DEBUG] cpu: energy policy set to 6
[INFO ] CPU #5 initialized
[DEBUG] VMX status: enabled
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] cpu: energy policy set to 6
[INFO ] CPU #1 initialized
[DEBUG] cpu: energy policy set to 6
[INFO ] CPU #7 initialized
[DEBUG] cpu: energy policy set to 6
[INFO ] CPU #6 initialized
[DEBUG] cpu: energy policy set to 6
[INFO ] CPU #2 initialized
[DEBUG] cpu: energy policy set to 6
[INFO ] CPU #3 initialized
[INFO ] bsp_do_flight_plan done after 3 msecs.
[DEBUG] CPU: frequency set to 3900
[DEBUG] Enabling SMIs.
[DEBUG] Locking SMM.
[DEBUG] CPU_CLUSTER: 0 init finished in 57 msecs
[DEBUG] PCI: 00:00.0 init
[DEBUG] Disabling PEG12.
[DEBUG] Disabling PEG11.
[DEBUG] Disabling PEG10.
[DEBUG] Disabling "device 7".
[DEBUG] Set BIOS_RESET_CPL
[DEBUG] CPU TDP: 47 Watts
[DEBUG] PCI: 00:00.0 init finished in 1 msecs
[DEBUG] PCI: 00:02.0 init
[INFO ] CBFS: Found 'vbt.bin' @0x373c0 size 0x582 in mcache @0x7f7dd1f4
[DEBUG] TPM: Extending digest for `CBFS: vbt.bin` into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[DEBUG] TPM: Digest of `CBFS: vbt.bin` to PCR 2 measured
[INFO ] Found a VBT of 4608 bytes after decompression
[INFO ] GMA: Found VBT in CBFS
[INFO ] GMA: Found valid VBT in CBFS
[DEBUG] GT Power Management Init
[INFO ] GMA: Setting backlight PWM frequency to 135MHz / 128 / 4794 = 220Hz
[0.375260] CONFIG =>
[0.375260] (Primary =>
[0.375261] (Port => eDP ,
[0.375261] Framebuffer =>
[0.375261] (Width => 640,
[0.375262] Height => 400,
[0.375262] Start_X => 0,
[0.375263] Start_Y => 0,
[0.375263] Stride => 1,
[0.375264] V_Stride => 1,
[0.375264] Tiling => Linear ,
[0.375265] Rotation => No_Rotation,
[0.375265] Offset => 0xffffffff,
[0.375266] BPC => 8),
[0.375266] Mode =>
[0.375266] (Dotclock => 138700000,
[0.375267] H_Visible => 1920,
[0.375267] H_Sync_Begin => 1968,
[0.375268] H_Sync_End => 2000,
[0.375268] H_Total => 2080,
[0.375269] V_Visible => 1080,
[0.375269] V_Sync_Begin => 1083,
[0.375270] V_Sync_End => 1088,
[0.375270] V_Total => 1111,
[0.375271] H_Sync_Active_High => True,
[0.375271] V_Sync_Active_High => False,
[0.375272] BPC => 6)),
[0.375272] Secondary =>
[0.375273] (Port => Disabled,
[0.375273] Framebuffer =>
[0.375273] (Width => 1,
[0.375274] Height => 1,
[0.375274] Start_X => 0,
[0.375275] Start_Y => 0,
[0.375275] Stride => 1,
[0.375275] V_Stride => 1,
[0.375276] Tiling => Linear ,
[0.375276] Rotation => No_Rotation,
[0.375277] Offset => 0x00000000,
[0.375277] BPC => 8),
[0.375278] Mode =>
[0.375278] (Dotclock => 1000000,
[0.375279] H_Visible => 1,
[0.375279] H_Sync_Begin => 1,
[0.375280] H_Sync_End => 1,
[0.375280] H_Total => 1,
[0.375281] V_Visible => 1,
[0.375281] V_Sync_Begin => 1,
[0.375282] V_Sync_End => 1,
[0.375282] V_Total => 1,
[0.375283] H_Sync_Active_High => False,
[0.375283] V_Sync_Active_High => False,
[0.375284] BPC => 5)),
[0.375284] Tertiary =>
[0.375284] (Port => Disabled,
[0.375285] Framebuffer =>
[0.375285] (Width => 1,
[0.375285] Height => 1,
[0.375286] Start_X => 0,
[0.375286] Start_Y => 0,
[0.375287] Stride => 1,
[0.375287] V_Stride => 1,
[0.375287] Tiling => Linear ,
[0.375288] Rotation => No_Rotation,
[0.375288] Offset => 0x00000000,
[0.375289] BPC => 8),
[0.375289] Mode =>
[0.375289] (Dotclock => 1000000,
[0.375290] H_Visible => 1,
[0.375290] H_Sync_Begin => 1,
[0.375291] H_Sync_End => 1,
[0.375291] H_Total => 1,
[0.375292] V_Visible => 1,
[0.375292] V_Sync_Begin => 1,
[0.375293] V_Sync_End => 1,
[0.375293] V_Total => 1,
[0.375294] H_Sync_Active_High => False,
[0.375294] V_Sync_Active_High => False,
[0.375295] BPC => 5)));
[DEBUG] GT Power Management Init (post VBIOS)
[DEBUG] PCI: 00:02.0 init finished in 229 msecs
[DEBUG] PCI: 00:03.0 init
[DEBUG] Mini-HD: base = 0x82838000
[DEBUG] azalia_audio: Initializing codec #0
[DEBUG] azalia_audio: codec viddid: 80862807
[DEBUG] azalia_audio: verb_size: 16
[DEBUG] azalia_audio: verb loaded.
[DEBUG] PCI: 00:03.0 init finished in 3 msecs
[DEBUG] PCI: 00:04.0 init
[DEBUG] PCI: 00:04.0 init finished in 0 msecs
[DEBUG] PCI: 00:14.0 init
[DEBUG] PCI: 00:14.0 init finished in 0 msecs
[DEBUG] PCI: 00:16.0 init
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : YES
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Initializing
[DEBUG] ME: Current Operation State : Bring up
[DEBUG] ME: Current Operation Mode : Debug
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : BUP Phase
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
[DEBUG] ME: Progress Phase State : 0x4d
[CRIT ] intel_me_path: mbp is not ready!
[NOTE ] ME: BIOS path: Error
[ERROR] ME: MBP not ready
[DEBUG] PCI: 00:16.0 init finished in 0 msecs
[DEBUG] PCI: 00:19.0 init
[DEBUG] PCI: 00:19.0 init finished in 0 msecs
[DEBUG] PCI: 00:1a.0 init
[DEBUG] EHCI: Setting up controller.. done.
[DEBUG] PCI: 00:1a.0 init finished in 0 msecs
[DEBUG] PCI: 00:1b.0 init
[DEBUG] Azalia: base = 0x8283c000
[DEBUG] Azalia: codec_mask = 01
[DEBUG] azalia_audio: Initializing codec #0
[DEBUG] azalia_audio: codec viddid: 10ec0292
[DEBUG] azalia_audio: verb_size: 128
[DEBUG] azalia_audio: verb loaded.
[DEBUG] PCI: 00:1b.0 init finished in 7 msecs
[DEBUG] PCI: 00:1c.0 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:1c.0 init finished in 0 msecs
[DEBUG] PCI: 00:1c.1 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:1c.1 init finished in 0 msecs
[DEBUG] PCI: 00:1d.0 init
[DEBUG] EHCI: Setting up controller.. done.
[DEBUG] PCI: 00:1d.0 init finished in 0 msecs
[DEBUG] PCI: 00:1f.0 init
[DEBUG] pch: lpc_init
[DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000
[DEBUG] IOAPIC: ID = 0x02
[DEBUG] IOAPIC: 24 interrupts
[DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
[INFO ] Set power off after power failure.
[INFO ] NMI sources disabled.
[DEBUG] LynxPoint H PM init
[DEBUG] RTC: failed = 0x0
[DEBUG] RTC Init
[DEBUG] apm_control: Disabling ACPI.
[DEBUG] APMC done.
[DEBUG] PCI: 00:1f.0 init finished in 0 msecs
[DEBUG] PCI: 00:1f.2 init
[DEBUG] SATA: Initializing...
[DEBUG] SATA: Controller in AHCI mode.
[DEBUG] ABAR: 0x82841000
[DEBUG] PCI: 00:1f.2 init finished in 0 msecs
[DEBUG] PCI: 00:1f.3 init
[DEBUG] PCI: 00:1f.3 init finished in 0 msecs
[DEBUG] PCI: 01:00.0 init
[DEBUG] PCI: 01:00.0 init finished in 0 msecs
[DEBUG] PCI: 02:00.0 init
[DEBUG] PCI: 02:00.0 init finished in 0 msecs
[DEBUG] PNP: 00ff.2 init
[DEBUG] PNP: 00ff.2 init finished in 0 msecs
[INFO ] Devices initialized
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 298 / 1 ms
[INFO ] Finalize devices...
[DEBUG] PCI: 00:00.0 final
[DEBUG] PCI: 00:16.0 final
[INFO ] ME: MBP cleared
[DEBUG] PCI: 00:1b.0 final
[DEBUG] PCI: 00:1f.0 final
[DEBUG] apm_control: Finalizing SMM.
[DEBUG] APMC done.
[INFO ] Devices finalized
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x33d40 size 0x3653 in mcache @0x7f7dd1c8
[DEBUG] TPM: Extending digest for `CBFS: fallback/dsdt.aml` into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[DEBUG] TPM: Digest of `CBFS: fallback/dsdt.aml` to PCR 2 measured
[WARN ] CBFS: 'fallback/slic' not found.
[INFO ] ACPI: Writing ACPI tables at 7f72d000.
[DEBUG] ACPI: * FACS
[DEBUG] ACPI: * DSDT
[DEBUG] ACPI: * FADT
[DEBUG] ACPI: added table 1/32, length now 40
[DEBUG] ACPI: * SSDT
[DEBUG] Found 1 CPU(s) with 8 core(s) each.
[DEBUG] PSS: 2901MHz power 47000 control 0x2700 status 0x2700
[DEBUG] PSS: 2900MHz power 47000 control 0x1d00 status 0x1d00
[DEBUG] PSS: 2400MHz power 36653 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 29144 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 22193 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 15839 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10016 control 0x800 status 0x800
[DEBUG] PSS: 2901MHz power 47000 control 0x2700 status 0x2700
[DEBUG] PSS: 2900MHz power 47000 control 0x1d00 status 0x1d00
[DEBUG] PSS: 2400MHz power 36653 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 29144 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 22193 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 15839 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10016 control 0x800 status 0x800
[DEBUG] PSS: 2901MHz power 47000 control 0x2700 status 0x2700
[DEBUG] PSS: 2900MHz power 47000 control 0x1d00 status 0x1d00
[DEBUG] PSS: 2400MHz power 36653 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 29144 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 22193 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 15839 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10016 control 0x800 status 0x800
[DEBUG] PSS: 2901MHz power 47000 control 0x2700 status 0x2700
[DEBUG] PSS: 2900MHz power 47000 control 0x1d00 status 0x1d00
[DEBUG] PSS: 2400MHz power 36653 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 29144 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 22193 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 15839 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10016 control 0x800 status 0x800
[DEBUG] PSS: 2901MHz power 47000 control 0x2700 status 0x2700
[DEBUG] PSS: 2900MHz power 47000 control 0x1d00 status 0x1d00
[DEBUG] PSS: 2400MHz power 36653 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 29144 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 22193 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 15839 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10016 control 0x800 status 0x800
[DEBUG] PSS: 2901MHz power 47000 control 0x2700 status 0x2700
[DEBUG] PSS: 2900MHz power 47000 control 0x1d00 status 0x1d00
[DEBUG] PSS: 2400MHz power 36653 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 29144 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 22193 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 15839 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10016 control 0x800 status 0x800
[DEBUG] PSS: 2901MHz power 47000 control 0x2700 status 0x2700
[DEBUG] PSS: 2900MHz power 47000 control 0x1d00 status 0x1d00
[DEBUG] PSS: 2400MHz power 36653 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 29144 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 22193 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 15839 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10016 control 0x800 status 0x800
[DEBUG] PSS: 2901MHz power 47000 control 0x2700 status 0x2700
[DEBUG] PSS: 2900MHz power 47000 control 0x1d00 status 0x1d00
[DEBUG] PSS: 2400MHz power 36653 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 29144 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 22193 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 15839 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10016 control 0x800 status 0x800
[DEBUG] Generating ACPI PIRQ entries
[INFO ] ACPI: * H8
[INFO ] H8: BDC detection not implemented. Assuming BDC installed
[INFO ] H8: WWAN detection not implemented. Assuming WWAN installed
[INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
[DEBUG] ACPI: added table 2/32, length now 44
[DEBUG] ACPI: * MCFG
[DEBUG] ACPI: added table 3/32, length now 48
[DEBUG] ACPI: * TCPA
[DEBUG] TCPA log created at 0x7f71d000
[DEBUG] ACPI: added table 4/32, length now 52
[DEBUG] ACPI: * MADT
[DEBUG] ACPI: added table 5/32, length now 56
[DEBUG] current = 7f733350
[DEBUG] ACPI: * DMAR
[DEBUG] ACPI: added table 6/32, length now 60
[DEBUG] ACPI: * HPET
[DEBUG] ACPI: added table 7/32, length now 64
[DEBUG] current = 7f733450
[INFO ] ACPI: done.
[DEBUG] ACPI tables: 25680 bytes.
[DEBUG] smbios_write_tables: 7f715000
[DEBUG] BIOS version set to CONFIG_LOCALVERSION: 'Heads-'
[INFO ] Create SMBIOS type 16
[INFO ] Create SMBIOS type 17
[INFO ] Create SMBIOS type 20
[INFO ] PCI: 02:00.0 (unknown)
[DEBUG] SMBIOS tables: 1133 bytes.
[DEBUG] Writing table forward entry at 0x00000500
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 7069
[DEBUG] Writing coreboot table at 0x7f751000
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG] 3. 0000000000100000-000000007f714fff: RAM
[DEBUG] 4. 000000007f715000-000000007f76dfff: CONFIGURATION TABLES
[DEBUG] 5. 000000007f76e000-000000007f7c9fff: RAMSTAGE
[DEBUG] 6. 000000007f7ca000-000000007f7fffff: CONFIGURATION TABLES
[DEBUG] 7. 000000007f800000-00000000821fffff: RESERVED
[DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED
[DEBUG] 9. 00000000fed10000-00000000fed19fff: RESERVED
[DEBUG] 10. 00000000fed40000-00000000fed44fff: RESERVED
[DEBUG] 11. 00000000fed80000-00000000fed84fff: RESERVED
[DEBUG] 12. 00000000fed90000-00000000fed91fff: RESERVED
[DEBUG] 13. 0000000100000000-000000047ddfffff: RAM
[DEBUG] Wrote coreboot table at: 0x7f751000, 0x420 bytes, checksum 4e17
[DEBUG] coreboot table: 1080 bytes.
[DEBUG] IMD ROOT 0. 0x7f7ff000 0x00001000
[DEBUG] IMD SMALL 1. 0x7f7fe000 0x00001000
[DEBUG] CONSOLE 2. 0x7f7de000 0x00020000
[DEBUG] RO MCACHE 3. 0x7f7dd000 0x000003e8
[DEBUG] TIME STAMP 4. 0x7f7dc000 0x00000910
[DEBUG] TCPA LOG 5. 0x7f7da000 0x000019cc
[DEBUG] MRC DATA 6. 0x7f7d9000 0x00000fe4
[DEBUG] MEM INFO 7. 0x7f7d8000 0x00000768
[DEBUG] AFTER CAR 8. 0x7f7ca000 0x0000e000
[DEBUG] RAMSTAGE 9. 0x7f76d000 0x0005d000
[DEBUG] SMM BACKUP 10. 0x7f75d000 0x00010000
[DEBUG] IGD OPREGION11. 0x7f759000 0x00003130
[DEBUG] COREBOOT 12. 0x7f751000 0x00008000
[DEBUG] ACPI 13. 0x7f72d000 0x00024000
[DEBUG] TCPA TCGLOG14. 0x7f71d000 0x00010000
[DEBUG] SMBIOS 15. 0x7f715000 0x00008000
[DEBUG] IMD small region:
[DEBUG] IMD ROOT 0. 0x7f7fec00 0x00000400
[DEBUG] FMAP 1. 0x7f7feb20 0x000000e0
[DEBUG] ROMSTAGE 2. 0x7f7feb00 0x00000004
[DEBUG] ROMSTG STCK 3. 0x7f7fea40 0x000000a8
[DEBUG] ACPI GNVS 4. 0x7f7fe980 0x000000b0
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 23 / 0 ms
[INFO ] CBFS: Found 'fallback/payload' @0x3e9c0 size 0x6dbdec in mcache @0x7f7dd290
[DEBUG] TPM: Extending digest for `CBFS: fallback/payload` into PCR 2
[DEBUG] TPM: command 0x14 returned 0x0
[DEBUG] TPM: Digest of `CBFS: fallback/payload` to PCR 2 measured
[DEBUG] Checking segment from ROM address 0xff47ebec
[DEBUG] Checking segment from ROM address 0xff47ec08
[DEBUG] Checking segment from ROM address 0xff47ec24
[DEBUG] Checking segment from ROM address 0xff47ec40
[DEBUG] Checking segment from ROM address 0xff47ec5c
[DEBUG] Checking segment from ROM address 0xff47ec78
[DEBUG] Loading segment from ROM address 0xff47ebec
[DEBUG] data (compression=0)
[DEBUG] New segment dstaddr 0x00090000 memsize 0x1080 srcaddr 0xff47ec94 filesize 0x1080
[DEBUG] Loading Segment: addr: 0x00090000 memsz: 0x0000000000001080 filesz: 0x0000000000001080
[DEBUG] it's not compressed!
[DEBUG] Loading segment from ROM address 0xff47ec08
[DEBUG] code (compression=0)
[DEBUG] New segment dstaddr 0x01000000 memsize 0x2e97c0 srcaddr 0xff47fd14 filesize 0x2e97c0
[DEBUG] Loading Segment: addr: 0x01000000 memsz: 0x00000000002e97c0 filesz: 0x00000000002e97c0
[DEBUG] it's not compressed!
[DEBUG] Loading segment from ROM address 0xff47ec24
[DEBUG] code (compression=0)
[DEBUG] New segment dstaddr 0x00040000 memsize 0xef srcaddr 0xff7694d4 filesize 0xef
[DEBUG] Loading Segment: addr: 0x00040000 memsz: 0x00000000000000ef filesz: 0x00000000000000ef
[DEBUG] it's not compressed!
[DEBUG] Loading segment from ROM address 0xff47ec40
[DEBUG] data (compression=0)
[DEBUG] New segment dstaddr 0x00091000 memsize 0x15 srcaddr 0xff7695c3 filesize 0x15
[DEBUG] Loading Segment: addr: 0x00091000 memsz: 0x0000000000000015 filesz: 0x0000000000000015
[DEBUG] it's not compressed!
[DEBUG] Loading segment from ROM address 0xff47ec5c
[DEBUG] data (compression=0)
[DEBUG] New segment dstaddr 0x04000000 memsize 0x3f1400 srcaddr 0xff7695d8 filesize 0x3f1400
[DEBUG] Loading Segment: addr: 0x04000000 memsz: 0x00000000003f1400 filesz: 0x00000000003f1400
[DEBUG] it's not compressed!
[DEBUG] Loading segment from ROM address 0xff47ec78
[DEBUG] Entry Point 0x00040000
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 7756 / 0 ms
[INFO ] coreboot TCPA measurements:
[INFO ] PCR-2 b2d72c678ea09ba2f93877bb8ae8d1c4264dd4bb SHA1 [FMAP: FMAP]
[INFO ] PCR-2 822261e3ef5a65f067df9d90eb3d73af10db23c9 SHA1 [CBFS: bootblock]
[INFO ] PCR-2 c2e69eae62fe750b15e7e66552f76431308b0b94 SHA1 [CBFS: fallback/romstage]
[INFO ] PCR-2 d18de1e3d52c0815b82ea406ca07897c56c65696 SHA1 [CBFS: mrc.bin]
[INFO ] PCR-2 0185e308850d08a272b6801c6262103f87d056d2 SHA1 [CBFS: fallback/postcar]
[INFO ] PCR-2 8d3a0b97bca3563a7aa15c3378fe35ef7d2b763b SHA1 [CBFS: fallback/ramstage]
[INFO ] PCR-2 73bf233bbb7df412386a30f1dc652e951d3d1b1c SHA1 [CBFS: cpu_microcode_blob.bin]
[INFO ] PCR-2 281d5cd4a67375632b491a7cf2ca1b2aece96d31 SHA1 [CBFS: vbt.bin]
[INFO ] PCR-2 d13a6f69d308c47a26538280143917ab88cc1630 SHA1 [CBFS: fallback/dsdt.aml]
[INFO ] PCR-2 a84ae3c75a0bed4dca79edd25f72f69d116964cd SHA1 [CBFS: fallback/payload]
[DEBUG] ICH-NM10-PCH: watchdog disabled
[DEBUG] Jumping to boot code at 0x00040000(0x7f751000)
Raw
cbmem_timings.txt
27 entries total:
0:1st timestamp 8,933 (0)
11:start of bootblock 128,412 (119,478)
12:end of bootblock 128,954 (542)
13:starting to load romstage 128,954 (0)
14:finished loading romstage 164,904 (35,949)
1:start of romstage 165,018 (114)
2:before RAM initialization 236,914 (71,896)
3:after RAM initialization 17,162,278 (16,925,364)
4:end of romstage 19,651,350 (2,489,071)
100:start of postcar 19,659,598 (8,248)
101:end of postcar 19,659,599 (0)
8:starting to load ramstage 19,659,601 (1)
15:starting LZMA decompress (ignore for x86) 19,742,306 (82,705)
16:finished LZMA decompress (ignore for x86) 19,808,206 (65,900)
9:finished loading ramstage 19,808,453 (247)
10:start of ramstage 19,808,489 (36)
30:device enumeration 19,808,495 (5)
40:device configuration 19,816,642 (8,146)
50:device enable 19,818,896 (2,254)
60:device initialization 19,929,451 (110,555)
15:starting LZMA decompress (ignore for x86) 19,999,074 (69,622)
16:finished LZMA decompress (ignore for x86) 19,999,499 (425)
70:device setup done 20,239,805 (240,306)
75:cbmem post 20,239,806 (0)
80:write tables 20,239,806 (0)
85:finalize chips 20,264,239 (24,432)
90:starting to load payload 20,264,240 (1)
99:selfboot jump 28,020,889 (7,756,648)
Total Time: 28,011,945
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