Created
November 29, 2021 06:26
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| ❯ make | |
| cd build && symbiflow_synth -t cache_cpu -v ../cache_cpu.v -d zynq7 -p xc7z010clg400-1 -x ../../../rtl/board-specific/squeakyboard/squeakyboard-symbi.xdc | |
| -t | |
| adding top | |
| cache_cpu | |
| -v | |
| ../cache_cpu.v | |
| -d | |
| zynq7 | |
| -p | |
| xc7z010clg400-1 | |
| -x | |
| ../../../rtl/board-specific/squeakyboard/squeakyboard-symbi.xdc | |
| yosys -p tcl /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/scripts/xc7/synth.tcl -l cache_cpu_synth.log ../cache_cpu.v | |
| /----------------------------------------------------------------------------\ | |
| | | | |
| | yosys -- Yosys Open SYnthesis Suite | | |
| | | | |
| | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | | |
| | | | |
| | Permission to use, copy, modify, and/or distribute this software for any | | |
| | purpose with or without fee is hereby granted, provided that the above | | |
| | copyright notice and this permission notice appear in all copies. | | |
| | | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | |
| | | | |
| \----------------------------------------------------------------------------/ | |
| Yosys 0.9+3962 (git sha1 0fb4224e, x86_64-conda_cos6-linux-gnu-gcc 1.23.0.449-a04d0 -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/home/runner/work/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1614595538728/work=/usr/local/src/conda/yosys-0.9_5266_g0fb4224e -fdebug-prefix-map=/home/petergu/.conda/envs/xc7=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants) | |
| -- Parsing `../cache_cpu.v' using frontend `verilog' -- | |
| 1. Executing Verilog-2005 frontend: ../cache_cpu.v | |
| Parsing Verilog input from `../cache_cpu.v' to AST representation. | |
| Generating RTLIL representation for module `\cache_cpu'. | |
| Generating RTLIL representation for module `\cacheway'. | |
| Successfully finished Verilog frontend. | |
| -- Running command `tcl /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/scripts/xc7/synth.tcl' -- | |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. | |
| Loaded SDC plugin | |
| [TCL: yosys -import] Command name collision: found pre-existing command `abc' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `abc9' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `abc9_exe' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `abc9_ops' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `add' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `aigmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `alumacc' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `anlogic_eqn' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `anlogic_fixcarry' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `assertpmux' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `async2sync' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `attrmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `attrmvcp' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `autoname' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `blackbox' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `bugpoint' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `check' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `chformal' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `chparam' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `chtype' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `clean' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `clk2fflogic' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `clkbufmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `connect' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `connect_rpc' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `connwrappers' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `coolrunner2_fixup' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `coolrunner2_sop' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `copy' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `cover' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `cutpoint' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `debug' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `delete' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `deminout' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `design' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `dffinit' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `dfflegalize' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `dfflibmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `dffunmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `dump' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `echo' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `ecp5_gsr' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `edgetypes' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `efinix_fixcarry' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_add' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_induct' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_make' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_mark' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_miter' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_opt' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_purge' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_remove' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_simple' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_status' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `equiv_struct' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `expose' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `extract' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `extract_counter' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `extract_fa' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `extract_reduce' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `extractinv' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `flatten' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `flowmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fmcombine' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fminit' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `freduce' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fsm' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fsm_detect' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fsm_expand' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fsm_export' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fsm_extract' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fsm_info' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fsm_map' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fsm_opt' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `fsm_recode' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `get_bank_tiles' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `get_iobanks' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `getparam' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `greenpak4_dffinv' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `help' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `hierarchy' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `hilomap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `ice40_braminit' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `ice40_dsp' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `ice40_opt' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `ice40_wrapcarry' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `insbuf' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `iopadmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `json' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `log' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `logger' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `ls' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `ltp' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `lut2mux' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `maccmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `memory' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `memory_bram' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `memory_collect' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `memory_dff' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `memory_map' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `memory_memx' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `memory_nordff' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `memory_share' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `memory_unpack' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `miter' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `mutate' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `muxcover' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `muxpack' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `nlutmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `onehot' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_clean' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_demorgan' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_dff' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_expr' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_lut' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_lut_ins' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_mem' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_merge' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_muxtree' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_reduce' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `opt_share' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `paramap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `peepopt' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `plugin' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `pmux2shiftx' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `pmuxtree' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `portlist' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `prep' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `printattrs' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `proc' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `proc_arst' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `proc_clean' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `proc_dff' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `proc_dlatch' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `proc_init' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `proc_mux' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `proc_prune' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `proc_rmdead' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `qbfsat' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `qwp' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read_aiger' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read_blif' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read_ilang' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read_json' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read_liberty' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read_rtlil' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read_verilog' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `rename' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `rmports' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `sat' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `scatter' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `scc' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `scratchpad' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `script' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `select' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `set_property' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `setattr' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `setparam' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `setundef' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `share' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `shell' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `show' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `shregmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `sim' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `simplemap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `splice' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `splitnets' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `stat' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `submod' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `supercover' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_achronix' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_anlogic' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_coolrunner2' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_easic' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_ecp5' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_efinix' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_gowin' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_greenpak4' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_ice40' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_intel' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_intel_alm' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_machxo2' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_nexus' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_sf2' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `synth_xilinx' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `tcl' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `techmap' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `tee' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `test_abcloop' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `test_autotb' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `test_cell' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `test_pmgen' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `torder' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `tribuf' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `uniquify' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `verific' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `verilog_defaults' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `verilog_defines' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `wbflip' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `wreduce' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_aiger' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_blif' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_btor' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_cxxrtl' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_edif' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_file' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_firrtl' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_ilang' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_intersynth' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_json' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_rtlil' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_simplec' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_smt2' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_smv' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_spice' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_table' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_verilog' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `write_xaiger' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `xilinx_dffopt' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `xilinx_dsp' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `xilinx_srl' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `zinit' -> skip. | |
| 2. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v' to AST representation. | |
| Generating RTLIL representation for module `\VCC'. | |
| Generating RTLIL representation for module `\GND'. | |
| Generating RTLIL representation for module `\IBUF'. | |
| Generating RTLIL representation for module `\IBUFG'. | |
| Generating RTLIL representation for module `\OBUF'. | |
| Generating RTLIL representation for module `\IOBUF'. | |
| Generating RTLIL representation for module `\OBUFT'. | |
| Generating RTLIL representation for module `\BUFG'. | |
| Generating RTLIL representation for module `\BUFGCTRL'. | |
| Generating RTLIL representation for module `\BUFHCE'. | |
| Generating RTLIL representation for module `\INV'. | |
| Generating RTLIL representation for module `\LUT1'. | |
| Generating RTLIL representation for module `\LUT2'. | |
| Generating RTLIL representation for module `\LUT3'. | |
| Generating RTLIL representation for module `\LUT4'. | |
| Generating RTLIL representation for module `\LUT5'. | |
| Generating RTLIL representation for module `\LUT6'. | |
| Generating RTLIL representation for module `\LUT6_2'. | |
| Generating RTLIL representation for module `\$__ABC9_LUT7'. | |
| Generating RTLIL representation for module `\$__ABC9_LUT8'. | |
| Generating RTLIL representation for module `\MUXCY'. | |
| Generating RTLIL representation for module `\MUXF5'. | |
| Generating RTLIL representation for module `\MUXF6'. | |
| Generating RTLIL representation for module `\MUXF7'. | |
| Generating RTLIL representation for module `\MUXF8'. | |
| Generating RTLIL representation for module `\MUXF9'. | |
| Generating RTLIL representation for module `\XORCY'. | |
| Generating RTLIL representation for module `\CARRY4'. | |
| Generating RTLIL representation for module `\CARRY8'. | |
| Generating RTLIL representation for module `\ORCY'. | |
| Generating RTLIL representation for module `\MULT_AND'. | |
| Generating RTLIL representation for module `\FDRE'. | |
| Generating RTLIL representation for module `\FDRE_1'. | |
| Generating RTLIL representation for module `\FDSE'. | |
| Generating RTLIL representation for module `\FDSE_1'. | |
| Generating RTLIL representation for module `\FDRSE'. | |
| Generating RTLIL representation for module `\FDRSE_1'. | |
| Generating RTLIL representation for module `\FDCE'. | |
| Generating RTLIL representation for module `\FDCE_1'. | |
| Generating RTLIL representation for module `\FDPE'. | |
| Generating RTLIL representation for module `\FDPE_1'. | |
| Generating RTLIL representation for module `\FDCPE'. | |
| Generating RTLIL representation for module `\FDCPE_1'. | |
| Generating RTLIL representation for module `\LDCE'. | |
| Generating RTLIL representation for module `\LDPE'. | |
| Generating RTLIL representation for module `\LDCPE'. | |
| Generating RTLIL representation for module `\AND2B1L'. | |
| Generating RTLIL representation for module `\OR2L'. | |
| Generating RTLIL representation for module `\RAM16X1S'. | |
| Generating RTLIL representation for module `\RAM16X1S_1'. | |
| Generating RTLIL representation for module `\RAM32X1S'. | |
| Generating RTLIL representation for module `\RAM32X1S_1'. | |
| Generating RTLIL representation for module `\RAM64X1S'. | |
| Generating RTLIL representation for module `\RAM64X1S_1'. | |
| Generating RTLIL representation for module `\RAM128X1S'. | |
| Generating RTLIL representation for module `\RAM128X1S_1'. | |
| Generating RTLIL representation for module `\RAM256X1S'. | |
| Generating RTLIL representation for module `\RAM512X1S'. | |
| Generating RTLIL representation for module `\RAM16X2S'. | |
| Generating RTLIL representation for module `\RAM32X2S'. | |
| Generating RTLIL representation for module `\RAM64X2S'. | |
| Generating RTLIL representation for module `\RAM16X4S'. | |
| Generating RTLIL representation for module `\RAM32X4S'. | |
| Generating RTLIL representation for module `\RAM16X8S'. | |
| Generating RTLIL representation for module `\RAM32X8S'. | |
| Generating RTLIL representation for module `\RAM16X1D'. | |
| Generating RTLIL representation for module `\RAM16X1D_1'. | |
| Generating RTLIL representation for module `\RAM32X1D'. | |
| Generating RTLIL representation for module `\RAM32X1D_1'. | |
| Generating RTLIL representation for module `\RAM64X1D'. | |
| Generating RTLIL representation for module `\RAM64X1D_1'. | |
| Generating RTLIL representation for module `\RAM128X1D'. | |
| Generating RTLIL representation for module `\RAM256X1D'. | |
| Generating RTLIL representation for module `\RAM32M'. | |
| Generating RTLIL representation for module `\RAM32M16'. | |
| Generating RTLIL representation for module `\RAM64M'. | |
| Generating RTLIL representation for module `\RAM64M8'. | |
| Generating RTLIL representation for module `\RAM32X16DR8'. | |
| Generating RTLIL representation for module `\RAM64X8SW'. | |
| Generating RTLIL representation for module `\ROM16X1'. | |
| Generating RTLIL representation for module `\ROM32X1'. | |
| Generating RTLIL representation for module `\ROM64X1'. | |
| Generating RTLIL representation for module `\ROM128X1'. | |
| Generating RTLIL representation for module `\ROM256X1'. | |
| Generating RTLIL representation for module `\SRL16'. | |
| Generating RTLIL representation for module `\SRL16E'. | |
| Generating RTLIL representation for module `\SRLC16'. | |
| Generating RTLIL representation for module `\SRLC16E'. | |
| Generating RTLIL representation for module `\SRLC32E'. | |
| Generating RTLIL representation for module `\CFGLUT5'. | |
| Generating RTLIL representation for module `\MULT18X18'. | |
| Generating RTLIL representation for module `\MULT18X18S'. | |
| Generating RTLIL representation for module `\MULT18X18SIO'. | |
| Generating RTLIL representation for module `\DSP48A'. | |
| Generating RTLIL representation for module `\DSP48A1'. | |
| Generating RTLIL representation for module `\DSP48'. | |
| Generating RTLIL representation for module `\DSP48E1'. | |
| Generating RTLIL representation for module `\RAMB18E1'. | |
| Generating RTLIL representation for module `\RAMB36E1'. | |
| Successfully finished Verilog frontend. | |
| 3. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_xtra.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_xtra.v' to AST representation. | |
| Generating RTLIL representation for module `\RAMB16_S1'. | |
| Generating RTLIL representation for module `\RAMB16_S2'. | |
| Generating RTLIL representation for module `\RAMB16_S4'. | |
| Generating RTLIL representation for module `\RAMB16_S9'. | |
| Generating RTLIL representation for module `\RAMB16_S18'. | |
| Generating RTLIL representation for module `\RAMB16_S36'. | |
| Generating RTLIL representation for module `\RAMB16_S1_S1'. | |
| Generating RTLIL representation for module `\RAMB16_S1_S2'. | |
| Generating RTLIL representation for module `\RAMB16_S1_S4'. | |
| Generating RTLIL representation for module `\RAMB16_S1_S9'. | |
| Generating RTLIL representation for module `\RAMB16_S1_S18'. | |
| Generating RTLIL representation for module `\RAMB16_S1_S36'. | |
| Generating RTLIL representation for module `\RAMB16_S2_S2'. | |
| Generating RTLIL representation for module `\RAMB16_S2_S4'. | |
| Generating RTLIL representation for module `\RAMB16_S2_S9'. | |
| Generating RTLIL representation for module `\RAMB16_S2_S18'. | |
| Generating RTLIL representation for module `\RAMB16_S2_S36'. | |
| Generating RTLIL representation for module `\RAMB16_S4_S4'. | |
| Generating RTLIL representation for module `\RAMB16_S4_S9'. | |
| Generating RTLIL representation for module `\RAMB16_S4_S18'. | |
| Generating RTLIL representation for module `\RAMB16_S4_S36'. | |
| Generating RTLIL representation for module `\RAMB16_S9_S9'. | |
| Generating RTLIL representation for module `\RAMB16_S9_S18'. | |
| Generating RTLIL representation for module `\RAMB16_S9_S36'. | |
| Generating RTLIL representation for module `\RAMB16_S18_S18'. | |
| Generating RTLIL representation for module `\RAMB16_S18_S36'. | |
| Generating RTLIL representation for module `\RAMB16_S36_S36'. | |
| Generating RTLIL representation for module `\RAMB16BWE_S18'. | |
| Generating RTLIL representation for module `\RAMB16BWE_S36'. | |
| Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. | |
| Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. | |
| Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. | |
| Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. | |
| Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. | |
| Generating RTLIL representation for module `\RAMB16BWER'. | |
| Generating RTLIL representation for module `\RAMB8BWER'. | |
| Generating RTLIL representation for module `\FIFO16'. | |
| Generating RTLIL representation for module `\RAMB16'. | |
| Generating RTLIL representation for module `\RAMB32_S64_ECC'. | |
| Generating RTLIL representation for module `\FIFO18'. | |
| Generating RTLIL representation for module `\FIFO18_36'. | |
| Generating RTLIL representation for module `\FIFO36'. | |
| Generating RTLIL representation for module `\FIFO36_72'. | |
| Generating RTLIL representation for module `\RAMB18'. | |
| Generating RTLIL representation for module `\RAMB36'. | |
| Generating RTLIL representation for module `\RAMB18SDP'. | |
| Generating RTLIL representation for module `\RAMB36SDP'. | |
| Generating RTLIL representation for module `\FIFO18E1'. | |
| Generating RTLIL representation for module `\FIFO36E1'. | |
| Generating RTLIL representation for module `\FIFO18E2'. | |
| Generating RTLIL representation for module `\FIFO36E2'. | |
| Generating RTLIL representation for module `\RAMB18E2'. | |
| Generating RTLIL representation for module `\RAMB36E2'. | |
| Generating RTLIL representation for module `\URAM288'. | |
| Generating RTLIL representation for module `\URAM288_BASE'. | |
| Generating RTLIL representation for module `\DSP48E'. | |
| Generating RTLIL representation for module `\DSP48E2'. | |
| Generating RTLIL representation for module `\FDDRCPE'. | |
| Generating RTLIL representation for module `\FDDRRSE'. | |
| Generating RTLIL representation for module `\IFDDRCPE'. | |
| Generating RTLIL representation for module `\IFDDRRSE'. | |
| Generating RTLIL representation for module `\OFDDRCPE'. | |
| Generating RTLIL representation for module `\OFDDRRSE'. | |
| Generating RTLIL representation for module `\OFDDRTCPE'. | |
| Generating RTLIL representation for module `\OFDDRTRSE'. | |
| Generating RTLIL representation for module `\IDDR2'. | |
| Generating RTLIL representation for module `\ODDR2'. | |
| Generating RTLIL representation for module `\IDDR'. | |
| Generating RTLIL representation for module `\IDDR_2CLK'. | |
| Generating RTLIL representation for module `\ODDR'. | |
| Generating RTLIL representation for module `\IDELAYCTRL'. | |
| Generating RTLIL representation for module `\IDELAY'. | |
| Generating RTLIL representation for module `\ISERDES'. | |
| Generating RTLIL representation for module `\OSERDES'. | |
| Generating RTLIL representation for module `\IODELAY'. | |
| Generating RTLIL representation for module `\ISERDES_NODELAY'. | |
| Generating RTLIL representation for module `\IODELAYE1'. | |
| Generating RTLIL representation for module `\ISERDESE1'. | |
| Generating RTLIL representation for module `\OSERDESE1'. | |
| Generating RTLIL representation for module `\IDELAYE2'. | |
| Generating RTLIL representation for module `\ODELAYE2'. | |
| Generating RTLIL representation for module `\ISERDESE2'. | |
| Generating RTLIL representation for module `\OSERDESE2'. | |
| Generating RTLIL representation for module `\PHASER_IN'. | |
| Generating RTLIL representation for module `\PHASER_IN_PHY'. | |
| Generating RTLIL representation for module `\PHASER_OUT'. | |
| Generating RTLIL representation for module `\PHASER_OUT_PHY'. | |
| Generating RTLIL representation for module `\PHASER_REF'. | |
| Generating RTLIL representation for module `\PHY_CONTROL'. | |
| Generating RTLIL representation for module `\IDDRE1'. | |
| Generating RTLIL representation for module `\ODDRE1'. | |
| Generating RTLIL representation for module `\IDELAYE3'. | |
| Generating RTLIL representation for module `\ODELAYE3'. | |
| Generating RTLIL representation for module `\ISERDESE3'. | |
| Generating RTLIL representation for module `\OSERDESE3'. | |
| Generating RTLIL representation for module `\BITSLICE_CONTROL'. | |
| Generating RTLIL representation for module `\RIU_OR'. | |
| Generating RTLIL representation for module `\RX_BITSLICE'. | |
| Generating RTLIL representation for module `\RXTX_BITSLICE'. | |
| Generating RTLIL representation for module `\TX_BITSLICE'. | |
| Generating RTLIL representation for module `\TX_BITSLICE_TRI'. | |
| Generating RTLIL representation for module `\IODELAY2'. | |
| Generating RTLIL representation for module `\IODRP2'. | |
| Generating RTLIL representation for module `\IODRP2_MCB'. | |
| Generating RTLIL representation for module `\ISERDES2'. | |
| Generating RTLIL representation for module `\OSERDES2'. | |
| Generating RTLIL representation for module `\IBUF_DLY_ADJ'. | |
| Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. | |
| Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. | |
| Generating RTLIL representation for module `\IBUF_ANALOG'. | |
| Generating RTLIL representation for module `\IBUFE3'. | |
| Generating RTLIL representation for module `\IBUFDS'. | |
| Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. | |
| Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. | |
| Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. | |
| Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. | |
| Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. | |
| Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. | |
| Generating RTLIL representation for module `\IBUFDSE3'. | |
| Generating RTLIL representation for module `\IBUFDS_DPHY'. | |
| Generating RTLIL representation for module `\IBUFGDS'. | |
| Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. | |
| Generating RTLIL representation for module `\IOBUF_DCIEN'. | |
| Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. | |
| Generating RTLIL representation for module `\IOBUFE3'. | |
| Generating RTLIL representation for module `\IOBUFDS'. | |
| Generating RTLIL representation for module `\IOBUFDS_DCIEN'. | |
| Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. | |
| Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. | |
| Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. | |
| Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. | |
| Generating RTLIL representation for module `\IOBUFDSE3'. | |
| Generating RTLIL representation for module `\OBUFDS'. | |
| Generating RTLIL representation for module `\OBUFDS_DPHY'. | |
| Generating RTLIL representation for module `\OBUFTDS'. | |
| Generating RTLIL representation for module `\KEEPER'. | |
| Generating RTLIL representation for module `\PULLDOWN'. | |
| Generating RTLIL representation for module `\PULLUP'. | |
| Generating RTLIL representation for module `\DCIRESET'. | |
| Generating RTLIL representation for module `\HPIO_VREF'. | |
| Generating RTLIL representation for module `\BUFGCE'. | |
| Generating RTLIL representation for module `\BUFGCE_1'. | |
| Generating RTLIL representation for module `\BUFGMUX'. | |
| Generating RTLIL representation for module `\BUFGMUX_1'. | |
| Generating RTLIL representation for module `\BUFGMUX_CTRL'. | |
| Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. | |
| Generating RTLIL representation for module `\BUFG_GT'. | |
| Generating RTLIL representation for module `\BUFG_GT_SYNC'. | |
| Generating RTLIL representation for module `\BUFG_PS'. | |
| Generating RTLIL representation for module `\BUFGCE_DIV'. | |
| Generating RTLIL representation for module `\BUFH'. | |
| Generating RTLIL representation for module `\BUFIO2'. | |
| Generating RTLIL representation for module `\BUFIO2_2CLK'. | |
| Generating RTLIL representation for module `\BUFIO2FB'. | |
| Generating RTLIL representation for module `\BUFPLL'. | |
| Generating RTLIL representation for module `\BUFPLL_MCB'. | |
| Generating RTLIL representation for module `\BUFIO'. | |
| Generating RTLIL representation for module `\BUFIODQS'. | |
| Generating RTLIL representation for module `\BUFR'. | |
| Generating RTLIL representation for module `\BUFMR'. | |
| Generating RTLIL representation for module `\BUFMRCE'. | |
| Generating RTLIL representation for module `\DCM'. | |
| Generating RTLIL representation for module `\DCM_SP'. | |
| Generating RTLIL representation for module `\DCM_CLKGEN'. | |
| Generating RTLIL representation for module `\DCM_ADV'. | |
| Generating RTLIL representation for module `\DCM_BASE'. | |
| Generating RTLIL representation for module `\DCM_PS'. | |
| Generating RTLIL representation for module `\PMCD'. | |
| Generating RTLIL representation for module `\PLL_ADV'. | |
| Generating RTLIL representation for module `\PLL_BASE'. | |
| Generating RTLIL representation for module `\MMCM_ADV'. | |
| Generating RTLIL representation for module `\MMCM_BASE'. | |
| Generating RTLIL representation for module `\MMCME2_ADV'. | |
| Generating RTLIL representation for module `\MMCME2_BASE'. | |
| Generating RTLIL representation for module `\PLLE2_ADV'. | |
| Generating RTLIL representation for module `\PLLE2_BASE'. | |
| Generating RTLIL representation for module `\MMCME3_ADV'. | |
| Generating RTLIL representation for module `\MMCME3_BASE'. | |
| Generating RTLIL representation for module `\PLLE3_ADV'. | |
| Generating RTLIL representation for module `\PLLE3_BASE'. | |
| Generating RTLIL representation for module `\MMCME4_ADV'. | |
| Generating RTLIL representation for module `\MMCME4_BASE'. | |
| Generating RTLIL representation for module `\PLLE4_ADV'. | |
| Generating RTLIL representation for module `\PLLE4_BASE'. | |
| Generating RTLIL representation for module `\BUFT'. | |
| Generating RTLIL representation for module `\IN_FIFO'. | |
| Generating RTLIL representation for module `\OUT_FIFO'. | |
| Generating RTLIL representation for module `\HARD_SYNC'. | |
| Generating RTLIL representation for module `\STARTUP_SPARTAN3'. | |
| Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. | |
| Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. | |
| Generating RTLIL representation for module `\STARTUP_SPARTAN6'. | |
| Generating RTLIL representation for module `\STARTUP_VIRTEX4'. | |
| Generating RTLIL representation for module `\STARTUP_VIRTEX5'. | |
| Generating RTLIL representation for module `\STARTUP_VIRTEX6'. | |
| Generating RTLIL representation for module `\STARTUPE2'. | |
| Generating RTLIL representation for module `\STARTUPE3'. | |
| Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. | |
| Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. | |
| Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. | |
| Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. | |
| Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. | |
| Generating RTLIL representation for module `\CAPTUREE2'. | |
| Generating RTLIL representation for module `\ICAP_SPARTAN3A'. | |
| Generating RTLIL representation for module `\ICAP_SPARTAN6'. | |
| Generating RTLIL representation for module `\ICAP_VIRTEX4'. | |
| Generating RTLIL representation for module `\ICAP_VIRTEX5'. | |
| Generating RTLIL representation for module `\ICAP_VIRTEX6'. | |
| Generating RTLIL representation for module `\ICAPE2'. | |
| Generating RTLIL representation for module `\ICAPE3'. | |
| Generating RTLIL representation for module `\BSCAN_SPARTAN3'. | |
| Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. | |
| Generating RTLIL representation for module `\BSCAN_SPARTAN6'. | |
| Generating RTLIL representation for module `\BSCAN_VIRTEX4'. | |
| Generating RTLIL representation for module `\BSCAN_VIRTEX5'. | |
| Generating RTLIL representation for module `\BSCAN_VIRTEX6'. | |
| Generating RTLIL representation for module `\BSCANE2'. | |
| Generating RTLIL representation for module `\DNA_PORT'. | |
| Generating RTLIL representation for module `\DNA_PORTE2'. | |
| Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. | |
| Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. | |
| Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. | |
| Generating RTLIL representation for module `\FRAME_ECCE2'. | |
| Generating RTLIL representation for module `\FRAME_ECCE3'. | |
| Generating RTLIL representation for module `\FRAME_ECCE4'. | |
| Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. | |
| Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. | |
| Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. | |
| Generating RTLIL representation for module `\USR_ACCESSE2'. | |
| Generating RTLIL representation for module `\POST_CRC_INTERNAL'. | |
| Generating RTLIL representation for module `\SUSPEND_SYNC'. | |
| Generating RTLIL representation for module `\KEY_CLEAR'. | |
| Generating RTLIL representation for module `\MASTER_JTAG'. | |
| Generating RTLIL representation for module `\SPI_ACCESS'. | |
| Generating RTLIL representation for module `\EFUSE_USR'. | |
| Generating RTLIL representation for module `\SYSMON'. | |
| Generating RTLIL representation for module `\XADC'. | |
| Generating RTLIL representation for module `\SYSMONE1'. | |
| Generating RTLIL representation for module `\SYSMONE4'. | |
| Generating RTLIL representation for module `\GTPA1_DUAL'. | |
| Generating RTLIL representation for module `\GT11_CUSTOM'. | |
| Generating RTLIL representation for module `\GT11_DUAL'. | |
| Generating RTLIL representation for module `\GT11CLK'. | |
| Generating RTLIL representation for module `\GT11CLK_MGT'. | |
| Generating RTLIL representation for module `\GTP_DUAL'. | |
| Generating RTLIL representation for module `\GTX_DUAL'. | |
| Generating RTLIL representation for module `\CRC32'. | |
| Generating RTLIL representation for module `\CRC64'. | |
| Generating RTLIL representation for module `\GTHE1_QUAD'. | |
| Generating RTLIL representation for module `\GTXE1'. | |
| Generating RTLIL representation for module `\IBUFDS_GTXE1'. | |
| Generating RTLIL representation for module `\IBUFDS_GTHE1'. | |
| Generating RTLIL representation for module `\GTHE2_CHANNEL'. | |
| Generating RTLIL representation for module `\GTHE2_COMMON'. | |
| Generating RTLIL representation for module `\GTPE2_CHANNEL'. | |
| Generating RTLIL representation for module `\GTPE2_COMMON'. | |
| Generating RTLIL representation for module `\GTXE2_CHANNEL'. | |
| Generating RTLIL representation for module `\GTXE2_COMMON'. | |
| Generating RTLIL representation for module `\IBUFDS_GTE2'. | |
| Generating RTLIL representation for module `\GTHE3_CHANNEL'. | |
| Generating RTLIL representation for module `\GTHE3_COMMON'. | |
| Generating RTLIL representation for module `\GTYE3_CHANNEL'. | |
| Generating RTLIL representation for module `\GTYE3_COMMON'. | |
| Generating RTLIL representation for module `\IBUFDS_GTE3'. | |
| Generating RTLIL representation for module `\OBUFDS_GTE3'. | |
| Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. | |
| Generating RTLIL representation for module `\GTHE4_CHANNEL'. | |
| Generating RTLIL representation for module `\GTHE4_COMMON'. | |
| Generating RTLIL representation for module `\GTYE4_CHANNEL'. | |
| Generating RTLIL representation for module `\GTYE4_COMMON'. | |
| Generating RTLIL representation for module `\IBUFDS_GTE4'. | |
| Generating RTLIL representation for module `\OBUFDS_GTE4'. | |
| Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. | |
| Generating RTLIL representation for module `\GTM_DUAL'. | |
| Generating RTLIL representation for module `\IBUFDS_GTM'. | |
| Generating RTLIL representation for module `\OBUFDS_GTM'. | |
| Generating RTLIL representation for module `\OBUFDS_GTM_ADV'. | |
| Generating RTLIL representation for module `\HSDAC'. | |
| Generating RTLIL representation for module `\HSADC'. | |
| Generating RTLIL representation for module `\RFDAC'. | |
| Generating RTLIL representation for module `\RFADC'. | |
| Generating RTLIL representation for module `\PCIE_A1'. | |
| Generating RTLIL representation for module `\PCIE_EP'. | |
| Generating RTLIL representation for module `\PCIE_2_0'. | |
| Generating RTLIL representation for module `\PCIE_2_1'. | |
| Generating RTLIL representation for module `\PCIE_3_0'. | |
| Generating RTLIL representation for module `\PCIE_3_1'. | |
| Generating RTLIL representation for module `\PCIE40E4'. | |
| Generating RTLIL representation for module `\PCIE4CE4'. | |
| Generating RTLIL representation for module `\EMAC'. | |
| Generating RTLIL representation for module `\TEMAC'. | |
| Generating RTLIL representation for module `\TEMAC_SINGLE'. | |
| Generating RTLIL representation for module `\CMAC'. | |
| Generating RTLIL representation for module `\CMACE4'. | |
| Generating RTLIL representation for module `\MCB'. | |
| Generating RTLIL representation for module `\HBM_REF_CLK'. | |
| Generating RTLIL representation for module `\HBM_SNGLBLI_INTF_APB'. | |
| Generating RTLIL representation for module `\HBM_SNGLBLI_INTF_AXI'. | |
| Generating RTLIL representation for module `\HBM_ONE_STACK_INTF'. | |
| Generating RTLIL representation for module `\HBM_TWO_STACK_INTF'. | |
| Generating RTLIL representation for module `\PPC405_ADV'. | |
| Generating RTLIL representation for module `\PPC440'. | |
| Generating RTLIL representation for module `\PS7'. | |
| Generating RTLIL representation for module `\PS8'. | |
| Generating RTLIL representation for module `\ILKN'. | |
| Generating RTLIL representation for module `\ILKNE4'. | |
| Generating RTLIL representation for module `\VCU'. | |
| Generating RTLIL representation for module `\FE'. | |
| Successfully finished Verilog frontend. | |
| 4. Executing Verilog-2005 frontend: /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/iobs.v | |
| Parsing Verilog input from `/home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/iobs.v' to AST representation. | |
| Replacing existing blackbox module `\IBUF' at /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/iobs.v:1.1-17.10. | |
| Generating RTLIL representation for module `\IBUF'. | |
| Replacing existing blackbox module `\OBUF' at /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/iobs.v:19.1-35.10. | |
| Generating RTLIL representation for module `\OBUF'. | |
| Generating RTLIL representation for module `\SYN_OBUF'. | |
| Generating RTLIL representation for module `\SYN_IBUF'. | |
| Replacing existing blackbox module `\OBUFDS' at /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/iobs.v:51.1-68.10. | |
| Generating RTLIL representation for module `\OBUFDS'. | |
| Replacing existing blackbox module `\OBUFTDS' at /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/iobs.v:70.1-88.10. | |
| Generating RTLIL representation for module `\OBUFTDS'. | |
| Replacing existing blackbox module `\IOBUF' at /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/iobs.v:90.1-112.10. | |
| Generating RTLIL representation for module `\IOBUF'. | |
| Replacing existing blackbox module `\OBUFT' at /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/iobs.v:114.1-129.10. | |
| Generating RTLIL representation for module `\OBUFT'. | |
| Replacing existing blackbox module `\IOBUFDS' at /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/iobs.v:131.1-145.10. | |
| Generating RTLIL representation for module `\IOBUFDS'. | |
| Successfully finished Verilog frontend. | |
| 5. Executing TECHMAP pass (map to technology primitives). | |
| 5.1. Executing Verilog-2005 frontend: /home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/retarget.v | |
| Parsing Verilog input from `/home/petergu/opt/symbiflow/xc7/install/share/symbiflow/techmaps/xc7_vpr/techmap/retarget.v' to AST representation. | |
| Generating RTLIL representation for module `\FD'. | |
| Successfully finished Verilog frontend. | |
| 5.2. Continuing TECHMAP pass. | |
| No more expansions possible. | |
| 6. Executing HIERARCHY pass (managing design hierarchy). | |
| 6.1. Analyzing design hierarchy.. | |
| Top module: \cache_cpu | |
| Used module: \cacheway | |
| 6.2. Analyzing design hierarchy.. | |
| Top module: \cache_cpu | |
| Used module: \cacheway | |
| Removed 0 unused modules. | |
| 7. Executing SYNTH_XILINX pass. | |
| 7.1. Executing PROC pass (convert processes to netlists). | |
| 7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Cleaned up 0 empty switches. | |
| 7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018 in module RAM64M. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874 in module RAM32M. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$815 in module RAM128X1D. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$775 in module RAM64X1D. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$755 in module RAM32X1D_1. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$723 in module RAM32X1D. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:810$629 in module FDPE_1. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:769$626 in module FDPE. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:731$611 in module FDCE_1. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:690$608 in module FDCE. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:587$593 in module FDSE_1. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:554$589 in module FDSE. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:522$571 in module FDRE_1. | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:489$567 in module FDRE. | |
| Marked 1 switch rules as full_case in process $proc$../cache_cpu.v:72$11 in module cacheway. | |
| Marked 2 switch rules as full_case in process $proc$../cache_cpu.v:21$4 in module cache_cpu. | |
| Removed a total of 0 dead cases. | |
| 7.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). | |
| Removed 0 redundant assignments. | |
| Promoted 80 assignments to connections. | |
| 7.1.4. Executing PROC_INIT pass (extract init attributes). | |
| Found init rule in `\SRLC32E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2400$1175'. | |
| Set init value: \r = 0 | |
| Found init rule in `\SRLC16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2356$1168'. | |
| Set init value: \r = 16'0000000000000000 | |
| Found init rule in `\SRLC16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2324$1161'. | |
| Set init value: \r = 16'0000000000000000 | |
| Found init rule in `\SRL16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2287$1158'. | |
| Set init value: \r = 16'0000000000000000 | |
| Found init rule in `\SRL16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2259$1151'. | |
| Set init value: \r = 16'0000000000000000 | |
| Found init rule in `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1975$1100'. | |
| Set init value: \mem_d = 64'0000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1974$1099'. | |
| Set init value: \mem_c = 64'0000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1973$1098'. | |
| Set init value: \mem_b = 64'0000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1972$1097'. | |
| Set init value: \mem_a = 64'0000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1801$984'. | |
| Set init value: \mem_d = 64'0000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1800$983'. | |
| Set init value: \mem_c = 64'0000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1799$982'. | |
| Set init value: \mem_b = 64'0000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1798$981'. | |
| Set init value: \mem_a = 64'0000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1707$846'. | |
| Set init value: \mem = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1602$806'. | |
| Set init value: \mem = 64'0000000000000000000000000000000000000000000000000000000000000000 | |
| Found init rule in `\RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1556$768'. | |
| Set init value: \mem = 0 | |
| Found init rule in `\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1497$748'. | |
| Set init value: \mem = 0 | |
| Found init rule in `\FDPE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$632'. | |
| Set init value: \Q = 1'1 | |
| Found init rule in `\FDPE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$628'. | |
| Set init value: \Q = 1'1 | |
| Found init rule in `\FDCE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$614'. | |
| Set init value: \Q = 1'0 | |
| Found init rule in `\FDCE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$610'. | |
| Set init value: \Q = 1'0 | |
| Found init rule in `\FDSE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$596'. | |
| Set init value: \Q = 1'1 | |
| Found init rule in `\FDSE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$592'. | |
| Set init value: \Q = 1'1 | |
| Found init rule in `\FDRE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$574'. | |
| Set init value: \Q = 1'0 | |
| Found init rule in `\FDRE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$570'. | |
| Set init value: \Q = 1'0 | |
| Found init rule in `\cacheway.$proc$../cache_cpu.v:71$23'. | |
| Set init value: \count = 10'0000000000 | |
| Found init rule in `\cacheway.$proc$../cache_cpu.v:70$22'. | |
| Set init value: \state = 1'0 | |
| Found init rule in `\cache_cpu.$proc$../cache_cpu.v:15$8'. | |
| Set init value: \state = 4'0001 | |
| 7.1.5. Executing PROC_ARST pass (detect async resets in processes). | |
| Found async reset \PRE in `\FDPE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:810$629'. | |
| Found async reset \PRE in `\FDPE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:769$626'. | |
| Found async reset \CLR in `\FDCE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:731$611'. | |
| Found async reset \CLR in `\FDCE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:690$608'. | |
| 7.1.6. Executing PROC_MUX pass (convert decision trees to multiplexers). | |
| Creating decoders for process `\SRLC32E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2400$1175'. | |
| Creating decoders for process `\SRLC32E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2408$1174'. | |
| 1/1: $0\r[31:0] | |
| Creating decoders for process `\SRLC16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2356$1168'. | |
| Creating decoders for process `\SRLC16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2364$1167'. | |
| 1/1: $0\r[15:0] | |
| Creating decoders for process `\SRLC16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2324$1161'. | |
| Creating decoders for process `\SRLC16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2327$1160'. | |
| Creating decoders for process `\SRL16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2287$1158'. | |
| Creating decoders for process `\SRL16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2294$1157'. | |
| 1/1: $0\r[15:0] | |
| Creating decoders for process `\SRL16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2259$1151'. | |
| Creating decoders for process `\SRL16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2261$1150'. | |
| Creating decoders for process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1975$1100'. | |
| Creating decoders for process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1974$1099'. | |
| Creating decoders for process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1973$1098'. | |
| Creating decoders for process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1972$1097'. | |
| Creating decoders for process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| 1/12: $1$lookahead\mem_d$1017[63:0]$1042 | |
| 2/12: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1986$1008[63:0]$1038 | |
| 3/12: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1986$1007[63:0]$1037 | |
| 4/12: $1$lookahead\mem_c$1016[63:0]$1041 | |
| 5/12: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1985$1006[63:0]$1036 | |
| 6/12: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1985$1005[63:0]$1035 | |
| 7/12: $1$lookahead\mem_b$1015[63:0]$1040 | |
| 8/12: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1984$1004[63:0]$1034 | |
| 9/12: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1984$1003[63:0]$1033 | |
| 10/12: $1$lookahead\mem_a$1014[63:0]$1039 | |
| 11/12: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1983$1002[63:0]$1032 | |
| 12/12: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1983$1001[63:0]$1031 | |
| Creating decoders for process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1801$984'. | |
| Creating decoders for process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1800$983'. | |
| Creating decoders for process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1799$982'. | |
| Creating decoders for process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1798$981'. | |
| Creating decoders for process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| 1/12: $1$lookahead\mem_d$873[63:0]$898 | |
| 2/12: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1812$856[63:0]$894 | |
| 3/12: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1812$855[63:0]$893 | |
| 4/12: $1$lookahead\mem_c$872[63:0]$897 | |
| 5/12: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1811$854[63:0]$892 | |
| 6/12: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1811$853[63:0]$891 | |
| 7/12: $1$lookahead\mem_b$871[63:0]$896 | |
| 8/12: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1810$852[63:0]$890 | |
| 9/12: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1810$851[63:0]$889 | |
| 10/12: $1$lookahead\mem_a$870[63:0]$895 | |
| 11/12: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1809$850[63:0]$888 | |
| 12/12: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1809$849[63:0]$887 | |
| Creating decoders for process `\RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1707$846'. | |
| Creating decoders for process `\RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$815'. | |
| 1/3: $1$lookahead\mem$814[127:0]$821 | |
| 2/3: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$810[127:0]$820 | |
| 3/3: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$809[127:0]$819 | |
| Creating decoders for process `\RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1602$806'. | |
| Creating decoders for process `\RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$775'. | |
| 1/3: $1$lookahead\mem$774[63:0]$781 | |
| 2/3: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$770[63:0]$780 | |
| 3/3: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$769[63:0]$779 | |
| Creating decoders for process `\RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1556$768'. | |
| Creating decoders for process `\RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$755'. | |
| 1/3: $1$lookahead\mem$754[31:0]$761 | |
| 2/3: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$750[31:0]$760 | |
| 3/3: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$749[31:0]$759 | |
| Creating decoders for process `\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1497$748'. | |
| Creating decoders for process `\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$723'. | |
| 1/3: $1$lookahead\mem$722[31:0]$729 | |
| 2/3: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$718[31:0]$728 | |
| 3/3: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$717[31:0]$727 | |
| Creating decoders for process `\FDPE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$632'. | |
| Creating decoders for process `\FDPE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:810$629'. | |
| 1/1: $0\Q[0:0] | |
| Creating decoders for process `\FDPE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$628'. | |
| Creating decoders for process `\FDPE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:769$626'. | |
| 1/1: $0\Q[0:0] | |
| Creating decoders for process `\FDCE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$614'. | |
| Creating decoders for process `\FDCE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:731$611'. | |
| 1/1: $0\Q[0:0] | |
| Creating decoders for process `\FDCE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$610'. | |
| Creating decoders for process `\FDCE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:690$608'. | |
| 1/1: $0\Q[0:0] | |
| Creating decoders for process `\FDSE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$596'. | |
| Creating decoders for process `\FDSE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:587$593'. | |
| 1/1: $0\Q[0:0] | |
| Creating decoders for process `\FDSE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$592'. | |
| Creating decoders for process `\FDSE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:554$589'. | |
| 1/1: $0\Q[0:0] | |
| Creating decoders for process `\FDRE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$574'. | |
| Creating decoders for process `\FDRE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:522$571'. | |
| 1/1: $0\Q[0:0] | |
| Creating decoders for process `\FDRE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$570'. | |
| Creating decoders for process `\FDRE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:489$567'. | |
| 1/1: $0\Q[0:0] | |
| Creating decoders for process `\cacheway.$proc$../cache_cpu.v:71$23'. | |
| Creating decoders for process `\cacheway.$proc$../cache_cpu.v:70$22'. | |
| Creating decoders for process `\cacheway.$proc$../cache_cpu.v:72$11'. | |
| 1/5: $0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 | |
| 2/5: $0$memwr$\tags$../cache_cpu.v:76$9_ADDR[9:0]$12 | |
| 3/5: $0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 | |
| 4/5: $0\count[9:0] | |
| 5/5: $0\state[0:0] | |
| Creating decoders for process `\cache_cpu.$proc$../cache_cpu.v:15$8'. | |
| Creating decoders for process `\cache_cpu.$proc$../cache_cpu.v:37$6'. | |
| 1/1: $0\state[3:0] | |
| Creating decoders for process `\cache_cpu.$proc$../cache_cpu.v:21$4'. | |
| 1/3: $2\way_tag_we[0:0] | |
| 2/3: $1\way_tag_we[0:0] | |
| 3/3: $1\way_en[0:0] | |
| 7.1.7. Executing PROC_DLATCH pass (convert process syncs to latches). | |
| No latch inferred for signal `\cache_cpu.\way_en' from process `\cache_cpu.$proc$../cache_cpu.v:21$4'. | |
| No latch inferred for signal `\cache_cpu.\way_tag_we' from process `\cache_cpu.$proc$../cache_cpu.v:21$4'. | |
| 7.1.8. Executing PROC_DFF pass (convert process syncs to FFs). | |
| Creating register for signal `\SRLC32E.\r' using process `\SRLC32E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2408$1174'. | |
| created $dff cell `$procdff$1408' with positive edge clock. | |
| Creating register for signal `\SRLC16E.\r' using process `\SRLC16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2364$1167'. | |
| created $dff cell `$procdff$1409' with positive edge clock. | |
| Creating register for signal `\SRLC16.\r' using process `\SRLC16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2327$1160'. | |
| created $dff cell `$procdff$1410' with positive edge clock. | |
| Creating register for signal `\SRL16E.\r' using process `\SRL16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2294$1157'. | |
| created $dff cell `$procdff$1411' with positive edge clock. | |
| Creating register for signal `\SRL16.\r' using process `\SRL16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2261$1150'. | |
| created $dff cell `$procdff$1412' with positive edge clock. | |
| Creating register for signal `\RAM64M.\mem_a' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1413' with positive edge clock. | |
| Creating register for signal `\RAM64M.\mem_b' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1414' with positive edge clock. | |
| Creating register for signal `\RAM64M.\mem_c' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1415' with positive edge clock. | |
| Creating register for signal `\RAM64M.\mem_d' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1416' with positive edge clock. | |
| Creating register for signal `\RAM64M.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1983$1001' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1417' with positive edge clock. | |
| Creating register for signal `\RAM64M.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1983$1002' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1418' with positive edge clock. | |
| Creating register for signal `\RAM64M.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1984$1003' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1419' with positive edge clock. | |
| Creating register for signal `\RAM64M.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1984$1004' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1420' with positive edge clock. | |
| Creating register for signal `\RAM64M.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1985$1005' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1421' with positive edge clock. | |
| Creating register for signal `\RAM64M.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1985$1006' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1422' with positive edge clock. | |
| Creating register for signal `\RAM64M.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1986$1007' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1423' with positive edge clock. | |
| Creating register for signal `\RAM64M.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1986$1008' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1424' with positive edge clock. | |
| Creating register for signal `\RAM64M.$lookahead\mem_a$1014' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1425' with positive edge clock. | |
| Creating register for signal `\RAM64M.$lookahead\mem_b$1015' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1426' with positive edge clock. | |
| Creating register for signal `\RAM64M.$lookahead\mem_c$1016' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1427' with positive edge clock. | |
| Creating register for signal `\RAM64M.$lookahead\mem_d$1017' using process `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| created $dff cell `$procdff$1428' with positive edge clock. | |
| Creating register for signal `\RAM32M.\mem_a' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1429' with positive edge clock. | |
| Creating register for signal `\RAM32M.\mem_b' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1430' with positive edge clock. | |
| Creating register for signal `\RAM32M.\mem_c' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1431' with positive edge clock. | |
| Creating register for signal `\RAM32M.\mem_d' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1432' with positive edge clock. | |
| Creating register for signal `\RAM32M.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1809$849' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1433' with positive edge clock. | |
| Creating register for signal `\RAM32M.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1809$850' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1434' with positive edge clock. | |
| Creating register for signal `\RAM32M.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1810$851' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1435' with positive edge clock. | |
| Creating register for signal `\RAM32M.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1810$852' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1436' with positive edge clock. | |
| Creating register for signal `\RAM32M.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1811$853' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1437' with positive edge clock. | |
| Creating register for signal `\RAM32M.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1811$854' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1438' with positive edge clock. | |
| Creating register for signal `\RAM32M.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1812$855' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1439' with positive edge clock. | |
| Creating register for signal `\RAM32M.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1812$856' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1440' with positive edge clock. | |
| Creating register for signal `\RAM32M.$lookahead\mem_a$870' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1441' with positive edge clock. | |
| Creating register for signal `\RAM32M.$lookahead\mem_b$871' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1442' with positive edge clock. | |
| Creating register for signal `\RAM32M.$lookahead\mem_c$872' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1443' with positive edge clock. | |
| Creating register for signal `\RAM32M.$lookahead\mem_d$873' using process `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| created $dff cell `$procdff$1444' with positive edge clock. | |
| Creating register for signal `\RAM128X1D.\mem' using process `\RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$815'. | |
| created $dff cell `$procdff$1445' with positive edge clock. | |
| Creating register for signal `\RAM128X1D.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$809' using process `\RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$815'. | |
| created $dff cell `$procdff$1446' with positive edge clock. | |
| Creating register for signal `\RAM128X1D.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$810' using process `\RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$815'. | |
| created $dff cell `$procdff$1447' with positive edge clock. | |
| Creating register for signal `\RAM128X1D.$lookahead\mem$814' using process `\RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$815'. | |
| created $dff cell `$procdff$1448' with positive edge clock. | |
| Creating register for signal `\RAM64X1D.\mem' using process `\RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$775'. | |
| created $dff cell `$procdff$1449' with positive edge clock. | |
| Creating register for signal `\RAM64X1D.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$769' using process `\RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$775'. | |
| created $dff cell `$procdff$1450' with positive edge clock. | |
| Creating register for signal `\RAM64X1D.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$770' using process `\RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$775'. | |
| created $dff cell `$procdff$1451' with positive edge clock. | |
| Creating register for signal `\RAM64X1D.$lookahead\mem$774' using process `\RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$775'. | |
| created $dff cell `$procdff$1452' with positive edge clock. | |
| Creating register for signal `\RAM32X1D_1.\mem' using process `\RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$755'. | |
| created $dff cell `$procdff$1453' with negative edge clock. | |
| Creating register for signal `\RAM32X1D_1.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$749' using process `\RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$755'. | |
| created $dff cell `$procdff$1454' with negative edge clock. | |
| Creating register for signal `\RAM32X1D_1.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$750' using process `\RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$755'. | |
| created $dff cell `$procdff$1455' with negative edge clock. | |
| Creating register for signal `\RAM32X1D_1.$lookahead\mem$754' using process `\RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$755'. | |
| created $dff cell `$procdff$1456' with negative edge clock. | |
| Creating register for signal `\RAM32X1D.\mem' using process `\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$723'. | |
| created $dff cell `$procdff$1457' with positive edge clock. | |
| Creating register for signal `\RAM32X1D.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$717' using process `\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$723'. | |
| created $dff cell `$procdff$1458' with positive edge clock. | |
| Creating register for signal `\RAM32X1D.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$718' using process `\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$723'. | |
| created $dff cell `$procdff$1459' with positive edge clock. | |
| Creating register for signal `\RAM32X1D.$lookahead\mem$722' using process `\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$723'. | |
| created $dff cell `$procdff$1460' with positive edge clock. | |
| Creating register for signal `\FDPE_1.\Q' using process `\FDPE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:810$629'. | |
| created $adff cell `$procdff$1461' with negative edge clock and positive level reset. | |
| Creating register for signal `\FDPE.\Q' using process `\FDPE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:769$626'. | |
| created $adff cell `$procdff$1462' with positive edge clock and positive level reset. | |
| Creating register for signal `\FDCE_1.\Q' using process `\FDCE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:731$611'. | |
| created $adff cell `$procdff$1463' with negative edge clock and positive level reset. | |
| Creating register for signal `\FDCE.\Q' using process `\FDCE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:690$608'. | |
| created $adff cell `$procdff$1464' with positive edge clock and positive level reset. | |
| Creating register for signal `\FDSE_1.\Q' using process `\FDSE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:587$593'. | |
| created $dff cell `$procdff$1465' with negative edge clock. | |
| Creating register for signal `\FDSE.\Q' using process `\FDSE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:554$589'. | |
| created $dff cell `$procdff$1466' with positive edge clock. | |
| Creating register for signal `\FDRE_1.\Q' using process `\FDRE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:522$571'. | |
| created $dff cell `$procdff$1467' with negative edge clock. | |
| Creating register for signal `\FDRE.\Q' using process `\FDRE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:489$567'. | |
| created $dff cell `$procdff$1468' with positive edge clock. | |
| Creating register for signal `\cacheway.\state' using process `\cacheway.$proc$../cache_cpu.v:72$11'. | |
| created $dff cell `$procdff$1469' with positive edge clock. | |
| Creating register for signal `\cacheway.\count' using process `\cacheway.$proc$../cache_cpu.v:72$11'. | |
| created $dff cell `$procdff$1470' with positive edge clock. | |
| Creating register for signal `\cacheway.$memwr$\tags$../cache_cpu.v:76$9_ADDR' using process `\cacheway.$proc$../cache_cpu.v:72$11'. | |
| created $dff cell `$procdff$1471' with positive edge clock. | |
| Creating register for signal `\cacheway.$memwr$\tags$../cache_cpu.v:76$9_EN' using process `\cacheway.$proc$../cache_cpu.v:72$11'. | |
| created $dff cell `$procdff$1472' with positive edge clock. | |
| Creating register for signal `\cacheway.$memwr$\tags$../cache_cpu.v:78$10_EN' using process `\cacheway.$proc$../cache_cpu.v:72$11'. | |
| created $dff cell `$procdff$1473' with positive edge clock. | |
| Creating register for signal `\cache_cpu.\state' using process `\cache_cpu.$proc$../cache_cpu.v:37$6'. | |
| created $dff cell `$procdff$1474' with positive edge clock. | |
| 7.1.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Removing empty process `SRLC32E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2400$1175'. | |
| Found and cleaned up 1 empty switch in `\SRLC32E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2408$1174'. | |
| Removing empty process `SRLC32E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2408$1174'. | |
| Removing empty process `SRLC16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2356$1168'. | |
| Found and cleaned up 1 empty switch in `\SRLC16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2364$1167'. | |
| Removing empty process `SRLC16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2364$1167'. | |
| Removing empty process `SRLC16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2324$1161'. | |
| Removing empty process `SRLC16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2327$1160'. | |
| Removing empty process `SRL16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2287$1158'. | |
| Found and cleaned up 1 empty switch in `\SRL16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2294$1157'. | |
| Removing empty process `SRL16E.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2294$1157'. | |
| Removing empty process `SRL16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2259$1151'. | |
| Removing empty process `SRL16.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:2261$1150'. | |
| Removing empty process `RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1975$1100'. | |
| Removing empty process `RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1974$1099'. | |
| Removing empty process `RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1973$1098'. | |
| Removing empty process `RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1972$1097'. | |
| Found and cleaned up 1 empty switch in `\RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| Removing empty process `RAM64M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1981$1018'. | |
| Removing empty process `RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1801$984'. | |
| Removing empty process `RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1800$983'. | |
| Removing empty process `RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1799$982'. | |
| Removing empty process `RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1798$981'. | |
| Found and cleaned up 1 empty switch in `\RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| Removing empty process `RAM32M.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1807$874'. | |
| Removing empty process `RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1707$846'. | |
| Found and cleaned up 1 empty switch in `\RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$815'. | |
| Removing empty process `RAM128X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1711$815'. | |
| Removing empty process `RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1602$806'. | |
| Found and cleaned up 1 empty switch in `\RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$775'. | |
| Removing empty process `RAM64X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1606$775'. | |
| Removing empty process `RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1556$768'. | |
| Found and cleaned up 1 empty switch in `\RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$755'. | |
| Removing empty process `RAM32X1D_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1560$755'. | |
| Removing empty process `RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1497$748'. | |
| Found and cleaned up 1 empty switch in `\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$723'. | |
| Removing empty process `RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$723'. | |
| Removing empty process `FDPE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$632'. | |
| Found and cleaned up 1 empty switch in `\FDPE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:810$629'. | |
| Removing empty process `FDPE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:810$629'. | |
| Removing empty process `FDPE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$628'. | |
| Found and cleaned up 1 empty switch in `\FDPE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:769$626'. | |
| Removing empty process `FDPE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:769$626'. | |
| Removing empty process `FDCE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$614'. | |
| Found and cleaned up 1 empty switch in `\FDCE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:731$611'. | |
| Removing empty process `FDCE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:731$611'. | |
| Removing empty process `FDCE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$610'. | |
| Found and cleaned up 1 empty switch in `\FDCE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:690$608'. | |
| Removing empty process `FDCE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:690$608'. | |
| Removing empty process `FDSE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$596'. | |
| Found and cleaned up 2 empty switches in `\FDSE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:587$593'. | |
| Removing empty process `FDSE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:587$593'. | |
| Removing empty process `FDSE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$592'. | |
| Found and cleaned up 2 empty switches in `\FDSE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:554$589'. | |
| Removing empty process `FDSE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:554$589'. | |
| Removing empty process `FDRE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$574'. | |
| Found and cleaned up 2 empty switches in `\FDRE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:522$571'. | |
| Removing empty process `FDRE_1.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:522$571'. | |
| Removing empty process `FDRE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:0$570'. | |
| Found and cleaned up 2 empty switches in `\FDRE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:489$567'. | |
| Removing empty process `FDRE.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:489$567'. | |
| Removing empty process `cacheway.$proc$../cache_cpu.v:71$23'. | |
| Removing empty process `cacheway.$proc$../cache_cpu.v:70$22'. | |
| Found and cleaned up 3 empty switches in `\cacheway.$proc$../cache_cpu.v:72$11'. | |
| Removing empty process `cacheway.$proc$../cache_cpu.v:72$11'. | |
| Removing empty process `cache_cpu.$proc$../cache_cpu.v:15$8'. | |
| Found and cleaned up 2 empty switches in `\cache_cpu.$proc$../cache_cpu.v:37$6'. | |
| Removing empty process `cache_cpu.$proc$../cache_cpu.v:37$6'. | |
| Found and cleaned up 2 empty switches in `\cache_cpu.$proc$../cache_cpu.v:21$4'. | |
| Removing empty process `cache_cpu.$proc$../cache_cpu.v:21$4'. | |
| Cleaned up 28 empty switches. | |
| 7.2. Executing FLATTEN pass (flatten design). | |
| Deleting now unused module cacheway. | |
| 7.3. Executing TRIBUF pass. | |
| 7.4. Executing DEMINOUT pass (demote inout ports to input or output). | |
| 7.5. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.6. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 1 unused cells and 28 unused wires. | |
| 7.7. Executing CHECK pass (checking for obvious problems). | |
| Checking module cache_cpu... | |
| Found and reported 0 problems. | |
| 7.8. Executing OPT pass (performing simple optimizations). | |
| 7.8.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.8.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 6 cells. | |
| 7.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Replacing known input bits on port B of cell $flatten\way_gen.$procmux$1387: \way_gen.state -> 1'1 | |
| Replacing known input bits on port A of cell $flatten\way_gen.$procmux$1385: \way_gen.state -> 1'0 | |
| Analyzing evaluation results. | |
| dead port 2/2 on $mux $procmux$1399. | |
| Removed 1 multiplexer ports. | |
| 7.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Consolidated identical input bits for $mux cell $flatten\way_gen.$procmux$1371: | |
| Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 | |
| New ports: A=1'1, B=1'0, Y=$flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] | |
| New connections: $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [31:1] = { $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_EN[31:0]$13 [0] } | |
| Consolidated identical input bits for $mux cell $flatten\way_gen.$procmux$1376: | |
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\way_gen.$procmux$1376_Y | |
| New ports: A=1'0, B=1'1, Y=$flatten\way_gen.$procmux$1376_Y [0] | |
| New connections: $flatten\way_gen.$procmux$1376_Y [31:1] = { $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] $flatten\way_gen.$procmux$1376_Y [0] } | |
| Optimizing cells in module \cache_cpu. | |
| Consolidated identical input bits for $mux cell $flatten\way_gen.$procmux$1379: | |
| Old ports: A=0, B=$flatten\way_gen.$procmux$1376_Y, Y=$flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 | |
| New ports: A=1'0, B=$flatten\way_gen.$procmux$1376_Y [0], Y=$flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] | |
| New connections: $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [31:1] = { $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] $flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:78$10_EN[31:0]$14 [0] } | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 3 changes. | |
| 7.8.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.8.6. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 0 unused cells and 7 unused wires. | |
| 7.8.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.8.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 7.8.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| 7.8.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.8.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.8.13. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.8.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| 7.8.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.8.16. Finished OPT passes. (There is nothing left to do.) | |
| 7.9. Executing FSM pass (extract and optimize FSM). | |
| 7.9.1. Executing FSM_DETECT pass (finding FSMs in design). | |
| Not marking cache_cpu.$flatten\way_gen.$memwr$\tags$../cache_cpu.v:76$9_EN as FSM state register: | |
| Users of register don't seem to benefit from recoding. | |
| Not marking cache_cpu.$flatten\way_gen.$memwr$\tags$../cache_cpu.v:78$10_EN as FSM state register: | |
| Users of register don't seem to benefit from recoding. | |
| Not marking cache_cpu.state as FSM state register: | |
| Register has an initialization value. | |
| 7.9.2. Executing FSM_EXTRACT pass (extracting FSM from design). | |
| 7.9.3. Executing FSM_OPT pass (simple optimizations of FSMs). | |
| 7.9.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| 7.9.5. Executing FSM_OPT pass (simple optimizations of FSMs). | |
| 7.9.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). | |
| 7.9.7. Executing FSM_INFO pass (dumping all available information on FSM cells). | |
| 7.9.8. Executing FSM_MAP pass (mapping FSMs to basic logic). | |
| 7.10. Executing OPT pass (performing simple optimizations). | |
| 7.10.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.10.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| 7.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.10.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.10.6. Executing OPT_DFF pass (perform DFF optimizations). | |
| Adding EN signal on $procdff$1474 ($dff) from module cache_cpu (D = $0\state[3:0], Q = \state). | |
| Adding EN signal on $flatten\way_gen.$procdff$1470 ($dff) from module cache_cpu (D = $flatten\way_gen.$add$../cache_cpu.v:74$16_Y [9:0], Q = \way_gen.count). | |
| Adding SRST signal on $flatten\way_gen.$procdff$1469 ($dff) from module cache_cpu (D = $flatten\way_gen.$procmux$1385_Y, Q = \way_gen.state, rval = 1'1). | |
| 7.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 2 unused cells and 2 unused wires. | |
| 7.10.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.10.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 7.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| 7.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.10.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.10.13. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| 7.10.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.10.16. Finished OPT passes. (There is nothing left to do.) | |
| 7.11. Executing WREDUCE pass (reducing word size of cells). | |
| Removed top 27 address bits (of 32) from memory read port cache_cpu.$flatten\way_gen.$memrd$\tags$../cache_cpu.v:81$19 (way_gen.tags). | |
| Removed top 5 address bits (of 10) from memory write port cache_cpu.$flatten\way_gen.$memwr$\tags$../cache_cpu.v:0$20 (way_gen.tags). | |
| Removed top 27 address bits (of 32) from memory write port cache_cpu.$flatten\way_gen.$memwr$\tags$../cache_cpu.v:0$21 (way_gen.tags). | |
| Removed top 3 bits (of 4) from port B of cell cache_cpu.$eq$../cache_cpu.v:17$2 ($eq). | |
| Removed top 31 bits (of 32) from FF cell cache_cpu.$flatten\way_gen.$procdff$1473 ($dff). | |
| Removed top 31 bits (of 32) from FF cell cache_cpu.$flatten\way_gen.$procdff$1472 ($dff). | |
| Removed top 5 bits (of 10) from FF cell cache_cpu.$flatten\way_gen.$procdff$1471 ($dff). | |
| Removed top 2 bits (of 4) from port B of cell cache_cpu.$procmux$1390_CMP0 ($eq). | |
| Removed cell cache_cpu.$procmux$1391 ($mux). | |
| Removed top 1 bits (of 2) from port B of cell cache_cpu.$auto$opt_dff.cc:218:make_patterns_logic$1478 ($ne). | |
| Removed cell cache_cpu.$flatten\way_gen.$procmux$1374 ($mux). | |
| Removed top 6 bits (of 10) from port B of cell cache_cpu.$flatten\way_gen.$eq$../cache_cpu.v:75$17 ($eq). | |
| Removed top 31 bits (of 32) from port B of cell cache_cpu.$flatten\way_gen.$add$../cache_cpu.v:74$16 ($add). | |
| Removed top 22 bits (of 32) from port Y of cell cache_cpu.$flatten\way_gen.$add$../cache_cpu.v:74$16 ($add). | |
| Removed top 5 bits (of 10) from wire cache_cpu.$flatten\way_gen.$0$memwr$\tags$../cache_cpu.v:76$9_ADDR[9:0]$12. | |
| Removed top 22 bits (of 32) from wire cache_cpu.$flatten\way_gen.$add$../cache_cpu.v:74$16_Y. | |
| 7.12. Executing PEEPOPT pass (run peephole optimizers). | |
| 7.13. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 0 unused cells and 4 unused wires. | |
| 7.14. Executing TECHMAP pass (map to technology primitives). | |
| 7.14.1. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/cmp2lut.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/cmp2lut.v' to AST representation. | |
| Generating RTLIL representation for module `\_90_lut_cmp_'. | |
| Successfully finished Verilog frontend. | |
| 7.14.2. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/cmp2lcu.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/cmp2lcu.v' to AST representation. | |
| Generating RTLIL representation for module `\_80_lcu_cmp_'. | |
| Generating RTLIL representation for module `\$__CMP2LCU'. | |
| Successfully finished Verilog frontend. | |
| 7.14.3. Continuing TECHMAP pass. | |
| No more expansions possible. | |
| 7.15. Executing ALUMACC pass (create $alu and $macc cells). | |
| Extracting $alu and $macc cells in module cache_cpu: | |
| creating $macc model for $flatten\way_gen.$add$../cache_cpu.v:74$16 ($add). | |
| creating $alu model for $macc $flatten\way_gen.$add$../cache_cpu.v:74$16. | |
| creating $alu cell for $flatten\way_gen.$add$../cache_cpu.v:74$16: $auto$alumacc.cc:485:replace_alu$1488 | |
| created 1 $alu and 0 $macc cells. | |
| 7.16. Executing SHARE pass (SAT-based resource sharing). | |
| 7.17. Executing OPT pass (performing simple optimizations). | |
| 7.17.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.17.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| 7.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.17.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.17.6. Executing OPT_DFF pass (perform DFF optimizations). | |
| Adding SRST signal on $flatten\way_gen.$procdff$1473 ($dff) from module cache_cpu (D = $flatten\way_gen.$procmux$1376_Y [31], Q = $flatten\way_gen.$memwr$\tags$../cache_cpu.v:78$10_EN [31], rval = 1'0). | |
| 7.17.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 1 unused cells and 1 unused wires. | |
| 7.17.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.17.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 7.17.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| 7.17.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.17.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.17.13. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.17.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| 7.17.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.17.16. Finished OPT passes. (There is nothing left to do.) | |
| 7.18. Executing MEMORY pass. | |
| 7.18.1. Executing OPT_MEM pass (optimize memories). | |
| Performed a total of 0 transformations. | |
| 7.18.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). | |
| Checking cell `$flatten\way_gen.$memwr$\tags$../cache_cpu.v:0$20' in module `\cache_cpu': merged $dff to cell. | |
| Checking cell `$flatten\way_gen.$memwr$\tags$../cache_cpu.v:0$21' in module `\cache_cpu': merged $dff to cell. | |
| Checking cell `$flatten\way_gen.$memrd$\tags$../cache_cpu.v:81$19' in module `\cache_cpu': no (compatible) $dff found. | |
| 7.18.3. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 3 unused cells and 3 unused wires. | |
| 7.18.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). | |
| Consolidating write ports of memory cache_cpu.way_gen.tags by address: | |
| New clock domain: posedge \clk | |
| Port 0 ($flatten\way_gen.$memwr$\tags$../cache_cpu.v:0$20) has addr \way_gen.count [4:0]. | |
| Active bits: 11111111111111111111111111111111 | |
| Port 1 ($flatten\way_gen.$memwr$\tags$../cache_cpu.v:0$21) has addr 5'00000. | |
| Active bits: 11111111111111111111111111111111 | |
| Consolidating write ports of memory cache_cpu.way_gen.tags using sat-based resource sharing: | |
| Port 0 ($flatten\way_gen.$memwr$\tags$../cache_cpu.v:0$20) on posedge \clk: considered | |
| Port 1 ($flatten\way_gen.$memwr$\tags$../cache_cpu.v:0$21) on posedge \clk: considered | |
| Common input cone for all EN signals: 10 cells. | |
| Size of unconstrained SAT problem: 107 variables, 220 clauses | |
| Merging port 0 into port 1. | |
| 7.18.5. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| 7.18.6. Executing MEMORY_COLLECT pass (generating $mem cells). | |
| 7.19. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| 7.20. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). | |
| Processing cache_cpu.way_gen.tags: | |
| Properties: ports=2 bits=1024 rports=1 wports=1 dbits=32 abits=5 words=32 | |
| Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1): | |
| Bram geometry: abits=9 dbits=72 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_SDP: awaste=480 dwaste=40 bwaste=35840 waste=35840 efficiency=2 | |
| Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #2 for bram type $__XILINX_RAMB36_SDP (variant 1): | |
| Bram geometry: abits=9 dbits=72 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_SDP: awaste=480 dwaste=40 bwaste=35840 waste=35840 efficiency=2 | |
| Rule for bram type $__XILINX_RAMB36_SDP (variant 1) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #3 for bram type $__XILINX_RAMB18_SDP (variant 1): | |
| Bram geometry: abits=9 dbits=36 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_SDP: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5 | |
| Rule #3 for bram type $__XILINX_RAMB18_SDP (variant 1) accepted. | |
| Mapping to bram type $__XILINX_RAMB18_SDP (variant 1): | |
| Shuffle bit order to accommodate enable buckets of size 9.. | |
| Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -1 -1 -1 -1 | |
| Write port #0 is in clock domain \clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain !~async~. | |
| Bram port A1.1 has incompatible clock type. | |
| Failed to map read port #0. | |
| Mapping to bram type $__XILINX_RAMB18_SDP failed. | |
| Checking rule #4 for bram type $__XILINX_RAMB18_SDP (variant 1): | |
| Bram geometry: abits=9 dbits=36 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Checking rule #5 for bram type $__XILINX_RAMB36_TDP (variant 1): | |
| Bram geometry: abits=10 dbits=36 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=992 dwaste=4 bwaste=35840 waste=35840 efficiency=2 | |
| Rule #5 for bram type $__XILINX_RAMB36_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #5 for bram type $__XILINX_RAMB36_TDP (variant 2): | |
| Bram geometry: abits=11 dbits=18 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=2016 dwaste=4 bwaste=36416 waste=36416 efficiency=1 | |
| Rule #5 for bram type $__XILINX_RAMB36_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #5 for bram type $__XILINX_RAMB36_TDP (variant 3): | |
| Bram geometry: abits=12 dbits=9 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=4064 dwaste=4 bwaste=36704 waste=36704 efficiency=0 | |
| Rule #5 for bram type $__XILINX_RAMB36_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #5 for bram type $__XILINX_RAMB36_TDP (variant 4): | |
| Bram geometry: abits=13 dbits=4 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=8160 dwaste=0 bwaste=32640 waste=32640 efficiency=0 | |
| Rule #5 for bram type $__XILINX_RAMB36_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #5 for bram type $__XILINX_RAMB36_TDP (variant 5): | |
| Bram geometry: abits=14 dbits=2 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=16352 dwaste=0 bwaste=32704 waste=32704 efficiency=0 | |
| Rule #5 for bram type $__XILINX_RAMB36_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #5 for bram type $__XILINX_RAMB36_TDP (variant 6): | |
| Bram geometry: abits=15 dbits=1 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=32736 dwaste=0 bwaste=32736 waste=32736 efficiency=0 | |
| Rule #5 for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #6 for bram type $__XILINX_RAMB36_TDP (variant 1): | |
| Bram geometry: abits=10 dbits=36 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=992 dwaste=4 bwaste=35840 waste=35840 efficiency=2 | |
| Rule for bram type $__XILINX_RAMB36_TDP (variant 1) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #6 for bram type $__XILINX_RAMB36_TDP (variant 2): | |
| Bram geometry: abits=11 dbits=18 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=2016 dwaste=4 bwaste=36416 waste=36416 efficiency=1 | |
| Rule for bram type $__XILINX_RAMB36_TDP (variant 2) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #6 for bram type $__XILINX_RAMB36_TDP (variant 3): | |
| Bram geometry: abits=12 dbits=9 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=4064 dwaste=4 bwaste=36704 waste=36704 efficiency=0 | |
| Rule for bram type $__XILINX_RAMB36_TDP (variant 3) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #6 for bram type $__XILINX_RAMB36_TDP (variant 4): | |
| Bram geometry: abits=13 dbits=4 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=8160 dwaste=0 bwaste=32640 waste=32640 efficiency=0 | |
| Rule for bram type $__XILINX_RAMB36_TDP (variant 4) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #6 for bram type $__XILINX_RAMB36_TDP (variant 5): | |
| Bram geometry: abits=14 dbits=2 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=16352 dwaste=0 bwaste=32704 waste=32704 efficiency=0 | |
| Rule for bram type $__XILINX_RAMB36_TDP (variant 5) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #6 for bram type $__XILINX_RAMB36_TDP (variant 6): | |
| Bram geometry: abits=15 dbits=1 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB36_TDP: awaste=32736 dwaste=0 bwaste=32736 waste=32736 efficiency=0 | |
| Rule for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #7 for bram type $__XILINX_RAMB18_TDP (variant 1): | |
| Bram geometry: abits=10 dbits=18 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2 | |
| Rule #7 for bram type $__XILINX_RAMB18_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #7 for bram type $__XILINX_RAMB18_TDP (variant 2): | |
| Bram geometry: abits=11 dbits=9 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1 | |
| Rule #7 for bram type $__XILINX_RAMB18_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #7 for bram type $__XILINX_RAMB18_TDP (variant 3): | |
| Bram geometry: abits=12 dbits=4 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0 | |
| Rule #7 for bram type $__XILINX_RAMB18_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #7 for bram type $__XILINX_RAMB18_TDP (variant 4): | |
| Bram geometry: abits=13 dbits=2 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0 | |
| Rule #7 for bram type $__XILINX_RAMB18_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #7 for bram type $__XILINX_RAMB18_TDP (variant 5): | |
| Bram geometry: abits=14 dbits=1 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0 | |
| Rule #7 for bram type $__XILINX_RAMB18_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. | |
| Checking rule #8 for bram type $__XILINX_RAMB18_TDP (variant 1): | |
| Bram geometry: abits=10 dbits=18 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2 | |
| Rule for bram type $__XILINX_RAMB18_TDP (variant 1) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #8 for bram type $__XILINX_RAMB18_TDP (variant 2): | |
| Bram geometry: abits=11 dbits=9 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1 | |
| Rule for bram type $__XILINX_RAMB18_TDP (variant 2) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #8 for bram type $__XILINX_RAMB18_TDP (variant 3): | |
| Bram geometry: abits=12 dbits=4 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0 | |
| Rule for bram type $__XILINX_RAMB18_TDP (variant 3) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #8 for bram type $__XILINX_RAMB18_TDP (variant 4): | |
| Bram geometry: abits=13 dbits=2 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0 | |
| Rule for bram type $__XILINX_RAMB18_TDP (variant 4) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| Checking rule #8 for bram type $__XILINX_RAMB18_TDP (variant 5): | |
| Bram geometry: abits=14 dbits=1 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAMB18_TDP: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0 | |
| Rule for bram type $__XILINX_RAMB18_TDP (variant 5) rejected: requirement 'attribute ram_style="block" ...' not met. | |
| No acceptable bram resources found. | |
| 7.21. Executing TECHMAP pass (map to technology primitives). | |
| 7.21.1. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/xc7_brams_map.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/xc7_brams_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$__XILINX_RAMB36_SDP'. | |
| Generating RTLIL representation for module `\$__XILINX_RAMB18_SDP'. | |
| Generating RTLIL representation for module `\$__XILINX_RAMB36_TDP'. | |
| Generating RTLIL representation for module `\$__XILINX_RAMB18_TDP'. | |
| Successfully finished Verilog frontend. | |
| 7.21.2. Continuing TECHMAP pass. | |
| No more expansions possible. | |
| 7.22. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). | |
| Processing cache_cpu.way_gen.tags: | |
| Properties: ports=2 bits=1024 rports=1 wports=1 dbits=32 abits=5 words=32 | |
| Checking rule #1 for bram type $__XILINX_RAM32X1D (variant 1): | |
| Bram geometry: abits=5 dbits=1 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAM32X1D: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 | |
| Rule #1 for bram type $__XILINX_RAM32X1D (variant 1) accepted. | |
| Mapping to bram type $__XILINX_RAM32X1D (variant 1): | |
| Write port #0 is in clock domain \clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain !~async~. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=0 efficiency=100 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__XILINX_RAM64X1D (variant 1): | |
| Bram geometry: abits=6 dbits=1 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAM64X1D: awaste=32 dwaste=0 bwaste=32 waste=32 efficiency=50 | |
| Rule #2 for bram type $__XILINX_RAM64X1D (variant 1) accepted. | |
| Mapping to bram type $__XILINX_RAM64X1D (variant 1): | |
| Write port #0 is in clock domain \clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain !~async~. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=32 efficiency=50 | |
| Storing for later selection. | |
| Checking rule #3 for bram type $__XILINX_RAM128X1D (variant 1): | |
| Bram geometry: abits=7 dbits=1 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAM128X1D: awaste=96 dwaste=0 bwaste=96 waste=96 efficiency=25 | |
| Rule #3 for bram type $__XILINX_RAM128X1D (variant 1) accepted. | |
| Mapping to bram type $__XILINX_RAM128X1D (variant 1): | |
| Write port #0 is in clock domain \clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain !~async~. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=96 efficiency=25 | |
| Storing for later selection. | |
| Checking rule #4 for bram type $__XILINX_RAM32X6SDP (variant 1): | |
| Bram geometry: abits=5 dbits=6 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAM32X6SDP: awaste=0 dwaste=4 bwaste=128 waste=128 efficiency=88 | |
| Rule #4 for bram type $__XILINX_RAM32X6SDP (variant 1) accepted. | |
| Mapping to bram type $__XILINX_RAM32X6SDP (variant 1): | |
| Write port #0 is in clock domain \clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain !~async~. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=128 efficiency=88 | |
| Storing for later selection. | |
| Checking rule #5 for bram type $__XILINX_RAM64X3SDP (variant 1): | |
| Bram geometry: abits=6 dbits=3 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAM64X3SDP: awaste=32 dwaste=1 bwaste=128 waste=128 efficiency=48 | |
| Rule #5 for bram type $__XILINX_RAM64X3SDP (variant 1) accepted. | |
| Mapping to bram type $__XILINX_RAM64X3SDP (variant 1): | |
| Write port #0 is in clock domain \clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain !~async~. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=128 efficiency=48 | |
| Storing for later selection. | |
| Checking rule #6 for bram type $__XILINX_RAM32X2Q (variant 1): | |
| Bram geometry: abits=5 dbits=2 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAM32X2Q: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 | |
| Rule #6 for bram type $__XILINX_RAM32X2Q (variant 1) rejected: requirement 'min rports 2' not met. | |
| Checking rule #7 for bram type $__XILINX_RAM64X1Q (variant 1): | |
| Bram geometry: abits=6 dbits=1 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__XILINX_RAM64X1Q: awaste=32 dwaste=0 bwaste=32 waste=32 efficiency=50 | |
| Rule #7 for bram type $__XILINX_RAM64X1Q (variant 1) rejected: requirement 'min rports 2' not met. | |
| Selecting best of 5 rules: | |
| Efficiency for rule 5.1: efficiency=48, cells=11, acells=1 | |
| Efficiency for rule 4.1: efficiency=88, cells=6, acells=1 | |
| Efficiency for rule 3.1: efficiency=25, cells=32, acells=1 | |
| Efficiency for rule 2.1: efficiency=50, cells=32, acells=1 | |
| Efficiency for rule 1.1: efficiency=100, cells=32, acells=1 | |
| Selected rule 1.1 with efficiency 100. | |
| Mapping to bram type $__XILINX_RAM32X1D (variant 1): | |
| Write port #0 is in clock domain \clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain !~async~. | |
| Mapped to bram port A1.1. | |
| Creating $__XILINX_RAM32X1D cell at grid position <0 0 0>: way_gen.tags.0.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <1 0 0>: way_gen.tags.1.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <2 0 0>: way_gen.tags.2.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <3 0 0>: way_gen.tags.3.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <4 0 0>: way_gen.tags.4.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <5 0 0>: way_gen.tags.5.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <6 0 0>: way_gen.tags.6.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <7 0 0>: way_gen.tags.7.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <8 0 0>: way_gen.tags.8.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <9 0 0>: way_gen.tags.9.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <10 0 0>: way_gen.tags.10.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <11 0 0>: way_gen.tags.11.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <12 0 0>: way_gen.tags.12.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <13 0 0>: way_gen.tags.13.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <14 0 0>: way_gen.tags.14.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <15 0 0>: way_gen.tags.15.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <16 0 0>: way_gen.tags.16.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <17 0 0>: way_gen.tags.17.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <18 0 0>: way_gen.tags.18.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <19 0 0>: way_gen.tags.19.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <20 0 0>: way_gen.tags.20.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <21 0 0>: way_gen.tags.21.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <22 0 0>: way_gen.tags.22.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <23 0 0>: way_gen.tags.23.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <24 0 0>: way_gen.tags.24.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <25 0 0>: way_gen.tags.25.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <26 0 0>: way_gen.tags.26.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <27 0 0>: way_gen.tags.27.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <28 0 0>: way_gen.tags.28.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <29 0 0>: way_gen.tags.29.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <30 0 0>: way_gen.tags.30.0.0 | |
| Creating $__XILINX_RAM32X1D cell at grid position <31 0 0>: way_gen.tags.31.0.0 | |
| 7.23. Executing TECHMAP pass (map to technology primitives). | |
| 7.23.1. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/lutrams_map.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/lutrams_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$__XILINX_RAM16X1D'. | |
| Generating RTLIL representation for module `\$__XILINX_RAM32X1D'. | |
| Generating RTLIL representation for module `\$__XILINX_RAM64X1D'. | |
| Generating RTLIL representation for module `\$__XILINX_RAM128X1D'. | |
| Generating RTLIL representation for module `\$__XILINX_RAM32X6SDP'. | |
| Generating RTLIL representation for module `\$__XILINX_RAM64X3SDP'. | |
| Generating RTLIL representation for module `\$__XILINX_RAM32X2Q'. | |
| Generating RTLIL representation for module `\$__XILINX_RAM64X1Q'. | |
| Successfully finished Verilog frontend. | |
| 7.23.2. Continuing TECHMAP pass. | |
| Using template $paramod\$__XILINX_RAM32X1D\CLKPOL2=1 for cells of type $__XILINX_RAM32X1D. | |
| No more expansions possible. | |
| 7.24. Executing OPT pass (performing simple optimizations). | |
| 7.24.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.24.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.24.3. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 0 unused cells and 229 unused wires. | |
| 7.24.5. Finished fast OPT passes. | |
| 7.25. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). | |
| 7.26. Executing OPT pass (performing simple optimizations). | |
| 7.26.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.26.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Replacing known input bits on port B of cell $auto$memory_share.cc:646:consolidate_wr_using_sat$1501: $auto$rtlil.cc:2125:ReduceOr$1495 -> 1'1 | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| 7.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Consolidated identical input bits for $mux cell $auto$memory_share.cc:629:consolidate_wr_using_sat$1498: | |
| Old ports: A=0, B=23, Y=$auto$rtlil.cc:2218:Mux$1499 | |
| New ports: A=1'0, B=1'1, Y=$auto$rtlil.cc:2218:Mux$1499 [0] | |
| New connections: $auto$rtlil.cc:2218:Mux$1499 [31:1] = { 27'000000000000000000000000000 $auto$rtlil.cc:2218:Mux$1499 [0] 1'0 $auto$rtlil.cc:2218:Mux$1499 [0] $auto$rtlil.cc:2218:Mux$1499 [0] } | |
| Consolidated identical input bits for $mux cell $procmux$1389: | |
| Old ports: A=4'0011, B=4'0001, Y=$0\state[3:0] | |
| New ports: A=1'1, B=1'0, Y=$0\state[3:0] [1] | |
| New connections: { $0\state[3:0] [3:2] $0\state[3:0] [0] } = 3'001 | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 2 changes. | |
| 7.26.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.26.6. Executing OPT_SHARE pass. | |
| 7.26.7. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.26.8. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| 7.26.9. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.26.10. Rerunning OPT passes. (Maybe there is more to do..) | |
| 7.26.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| 7.26.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.26.13. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.26.14. Executing OPT_SHARE pass. | |
| 7.26.15. Executing OPT_DFF pass (perform DFF optimizations). | |
| Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$1481 ($dffe) from module cache_cpu. | |
| Setting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$1481 ($dffe) from module cache_cpu. | |
| Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$1481 ($dffe) from module cache_cpu. | |
| 7.26.16. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 0 unused cells and 1 unused wires. | |
| 7.26.17. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.26.18. Rerunning OPT passes. (Maybe there is more to do..) | |
| 7.26.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| 7.26.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.26.21. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 1 cells. | |
| 7.26.22. Executing OPT_SHARE pass. | |
| 7.26.23. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.26.24. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 0 unused cells and 3 unused wires. | |
| 7.26.25. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.26.26. Rerunning OPT passes. (Maybe there is more to do..) | |
| 7.26.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| 7.26.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.26.29. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.26.30. Executing OPT_SHARE pass. | |
| 7.26.31. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.26.32. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| 7.26.33. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.26.34. Finished OPT passes. (There is nothing left to do.) | |
| 7.27. Executing TECHMAP pass (map to technology primitives). | |
| 7.27.1. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/techmap.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/techmap.v' to AST representation. | |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_various'. | |
| Generating RTLIL representation for module `\_90_simplemap_registers'. | |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. | |
| Generating RTLIL representation for module `\_90_shift_shiftx'. | |
| Generating RTLIL representation for module `\_90_fa'. | |
| Generating RTLIL representation for module `\_90_lcu'. | |
| Generating RTLIL representation for module `\_90_alu'. | |
| Generating RTLIL representation for module `\_90_macc'. | |
| Generating RTLIL representation for module `\_90_alumacc'. | |
| Generating RTLIL representation for module `\$__div_mod_u'. | |
| Generating RTLIL representation for module `\$__div_mod_trunc'. | |
| Generating RTLIL representation for module `\_90_div'. | |
| Generating RTLIL representation for module `\_90_mod'. | |
| Generating RTLIL representation for module `\$__div_mod_floor'. | |
| Generating RTLIL representation for module `\_90_divfloor'. | |
| Generating RTLIL representation for module `\_90_modfloor'. | |
| Generating RTLIL representation for module `\_90_pow'. | |
| Generating RTLIL representation for module `\_90_pmux'. | |
| Generating RTLIL representation for module `\_90_lut'. | |
| Successfully finished Verilog frontend. | |
| 7.27.2. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/arith_map.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/arith_map.v' to AST representation. | |
| Generating RTLIL representation for module `\_80_xilinx_lcu'. | |
| Generating RTLIL representation for module `\_80_xilinx_alu'. | |
| Successfully finished Verilog frontend. | |
| 7.27.3. Continuing TECHMAP pass. | |
| Using extmapper simplemap for cells of type $logic_not. | |
| Using extmapper simplemap for cells of type $not. | |
| Using extmapper simplemap for cells of type $and. | |
| Using extmapper simplemap for cells of type $reduce_bool. | |
| Using extmapper simplemap for cells of type $mux. | |
| Using extmapper simplemap for cells of type $sdff. | |
| Using extmapper simplemap for cells of type $or. | |
| Using template $paramod$11355b9b42c2988c50f848efad9b289fe79bda83\_80_xilinx_alu for cells of type $alu. | |
| Using extmapper simplemap for cells of type $ne. | |
| Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux. | |
| Using extmapper simplemap for cells of type $dffe. | |
| Using extmapper simplemap for cells of type $eq. | |
| Using extmapper simplemap for cells of type $xor. | |
| Using extmapper simplemap for cells of type $pos. | |
| Using extmapper simplemap for cells of type $reduce_or. | |
| No more expansions possible. | |
| 7.28. Executing OPT pass (performing simple optimizations). | |
| 7.28.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.28.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 3 cells. | |
| 7.28.3. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 7 unused cells and 37 unused wires. | |
| 7.28.5. Finished fast OPT passes. | |
| 7.29. Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells). | |
| Mapping port cache_cpu.a using IBUF. | |
| Mapping port cache_cpu.clk using IBUF. | |
| Mapping port cache_cpu.d using IBUF. | |
| Mapping port cache_cpu.ready using OBUF. | |
| Mapping port cache_cpu.we using IBUF. | |
| 7.30. Executing TECHMAP pass (map to technology primitives). | |
| 7.30.1. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/techmap.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/techmap.v' to AST representation. | |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_various'. | |
| Generating RTLIL representation for module `\_90_simplemap_registers'. | |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. | |
| Generating RTLIL representation for module `\_90_shift_shiftx'. | |
| Generating RTLIL representation for module `\_90_fa'. | |
| Generating RTLIL representation for module `\_90_lcu'. | |
| Generating RTLIL representation for module `\_90_alu'. | |
| Generating RTLIL representation for module `\_90_macc'. | |
| Generating RTLIL representation for module `\_90_alumacc'. | |
| Generating RTLIL representation for module `\$__div_mod_u'. | |
| Generating RTLIL representation for module `\$__div_mod_trunc'. | |
| Generating RTLIL representation for module `\_90_div'. | |
| Generating RTLIL representation for module `\_90_mod'. | |
| Generating RTLIL representation for module `\$__div_mod_floor'. | |
| Generating RTLIL representation for module `\_90_divfloor'. | |
| Generating RTLIL representation for module `\_90_modfloor'. | |
| Generating RTLIL representation for module `\_90_pow'. | |
| Generating RTLIL representation for module `\_90_pmux'. | |
| Generating RTLIL representation for module `\_90_lut'. | |
| Successfully finished Verilog frontend. | |
| 7.30.2. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_map.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$__SHREG_'. | |
| Generating RTLIL representation for module `\$__XILINX_SHREG_'. | |
| Generating RTLIL representation for module `\$__XILINX_MUXF78'. | |
| Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. | |
| Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. | |
| Successfully finished Verilog frontend. | |
| 7.30.3. Continuing TECHMAP pass. | |
| No more expansions possible. | |
| Removed 0 unused cells and 1 unused wires. | |
| 7.31. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). | |
| 7.32. Executing TECHMAP pass (map to technology primitives). | |
| 7.32.1. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/ff_map.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/ff_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$_DFFE_NP0P_'. | |
| Generating RTLIL representation for module `\$_DFFE_PP0P_'. | |
| Generating RTLIL representation for module `\$_DFFE_NP1P_'. | |
| Generating RTLIL representation for module `\$_DFFE_PP1P_'. | |
| Generating RTLIL representation for module `\$_DFFSRE_NPPP_'. | |
| Generating RTLIL representation for module `\$_DFFSRE_PPPP_'. | |
| Generating RTLIL representation for module `\$_SDFFE_NP0P_'. | |
| Generating RTLIL representation for module `\$_SDFFE_PP0P_'. | |
| Generating RTLIL representation for module `\$_SDFFE_NP1P_'. | |
| Generating RTLIL representation for module `\$_SDFFE_PP1P_'. | |
| Generating RTLIL representation for module `\$_DLATCH_NP0_'. | |
| Generating RTLIL representation for module `\$_DLATCH_PP0_'. | |
| Generating RTLIL representation for module `\$_DLATCH_NP1_'. | |
| Generating RTLIL representation for module `\$_DLATCH_PP1_'. | |
| Generating RTLIL representation for module `\$_DLATCH_NPP_'. | |
| Generating RTLIL representation for module `\$_DLATCH_PPP_'. | |
| Successfully finished Verilog frontend. | |
| 7.32.2. Continuing TECHMAP pass. | |
| Using template $paramod\$_SDFFE_PP1P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_SDFFE_PP1P_. | |
| Using template $paramod\$_SDFFE_PP0P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_SDFFE_PP0P_. | |
| No more expansions possible. | |
| 7.33. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.34. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/abc9_model.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/abc9_model.v' to AST representation. | |
| Generating RTLIL representation for module `$__XILINX_MUXF78'. | |
| Successfully finished Verilog frontend. | |
| 7.35. Executing ABC9 pass. | |
| 7.35.1. Executing ABC9_OPS pass (helper functions for ABC9). | |
| 7.35.2. Executing ABC9_OPS pass (helper functions for ABC9). | |
| 7.35.3. Executing PROC pass (convert processes to netlists). | |
| 7.35.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Cleaned up 0 empty switches. | |
| 7.35.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). | |
| Marked 1 switch rules as full_case in process $proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1958 in module $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D. | |
| Removed a total of 0 dead cases. | |
| 7.35.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). | |
| Removed 0 redundant assignments. | |
| Promoted 5 assignments to connections. | |
| 7.35.3.4. Executing PROC_INIT pass (extract init attributes). | |
| Found init rule in `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1497$1983'. | |
| Set init value: \mem = 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx | |
| 7.35.3.5. Executing PROC_ARST pass (detect async resets in processes). | |
| 7.35.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). | |
| Creating decoders for process `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1497$1983'. | |
| Creating decoders for process `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1958'. | |
| 1/3: $1$lookahead\mem$1957[31:0]$1964 | |
| 2/3: $1$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1953[31:0]$1963 | |
| 3/3: $1$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1952[31:0]$1962 | |
| 7.35.3.7. Executing PROC_DLATCH pass (convert process syncs to latches). | |
| 7.35.3.8. Executing PROC_DFF pass (convert process syncs to FFs). | |
| Creating register for signal `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$bitselwrite$mask$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1952' using process `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1958'. | |
| created $dff cell `$procdff$1993' with positive edge clock. | |
| Creating register for signal `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.\mem' using process `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1958'. | |
| created $dff cell `$procdff$1994' with positive edge clock. | |
| Creating register for signal `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$bitselwrite$data$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1953' using process `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1958'. | |
| created $dff cell `$procdff$1995' with positive edge clock. | |
| Creating register for signal `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$lookahead\mem$1957' using process `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1958'. | |
| created $dff cell `$procdff$1996' with positive edge clock. | |
| 7.35.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Removing empty process `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1497$1983'. | |
| Found and cleaned up 1 empty switch in `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1958'. | |
| Removing empty process `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.$proc$/home/petergu/.conda/envs/xc7/bin/../share/yosys/xilinx/cells_sim.v:1501$1958'. | |
| Cleaned up 1 empty switch. | |
| 7.35.4. Executing PROC pass (convert processes to netlists). | |
| 7.35.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Cleaned up 0 empty switches. | |
| 7.35.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). | |
| Removed a total of 0 dead cases. | |
| 7.35.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). | |
| Removed 0 redundant assignments. | |
| Promoted 0 assignments to connections. | |
| 7.35.4.4. Executing PROC_INIT pass (extract init attributes). | |
| 7.35.4.5. Executing PROC_ARST pass (detect async resets in processes). | |
| 7.35.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). | |
| 7.35.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). | |
| 7.35.4.8. Executing PROC_DFF pass (convert process syncs to FFs). | |
| 7.35.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Cleaned up 0 empty switches. | |
| 7.35.5. Executing TECHMAP pass (map to technology primitives). | |
| 7.35.5.1. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/techmap.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/techmap.v' to AST representation. | |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_various'. | |
| Generating RTLIL representation for module `\_90_simplemap_registers'. | |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. | |
| Generating RTLIL representation for module `\_90_shift_shiftx'. | |
| Generating RTLIL representation for module `\_90_fa'. | |
| Generating RTLIL representation for module `\_90_lcu'. | |
| Generating RTLIL representation for module `\_90_alu'. | |
| Generating RTLIL representation for module `\_90_macc'. | |
| Generating RTLIL representation for module `\_90_alumacc'. | |
| Generating RTLIL representation for module `\$__div_mod_u'. | |
| Generating RTLIL representation for module `\$__div_mod_trunc'. | |
| Generating RTLIL representation for module `\_90_div'. | |
| Generating RTLIL representation for module `\_90_mod'. | |
| Generating RTLIL representation for module `\$__div_mod_floor'. | |
| Generating RTLIL representation for module `\_90_divfloor'. | |
| Generating RTLIL representation for module `\_90_modfloor'. | |
| Generating RTLIL representation for module `\_90_pow'. | |
| Generating RTLIL representation for module `\_90_pmux'. | |
| Generating RTLIL representation for module `\_90_lut'. | |
| Successfully finished Verilog frontend. | |
| 7.35.5.2. Continuing TECHMAP pass. | |
| No more expansions possible. | |
| 7.35.6. Executing OPT pass (performing simple optimizations). | |
| 7.35.6.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D. | |
| 7.35.6.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D'. | |
| Removed a total of 0 cells. | |
| 7.35.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.. | |
| Creating internal representation of mux trees. | |
| No muxes found in this module. | |
| Removed 0 multiplexer ports. | |
| 7.35.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D. | |
| Performed a total of 0 changes. | |
| 7.35.6.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `$paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D'. | |
| Removed a total of 0 cells. | |
| 7.35.6.6. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.35.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D.. | |
| 7.35.6.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D. | |
| 7.35.6.9. Finished OPT passes. (There is nothing left to do.) | |
| 7.35.7. Executing TECHMAP pass (map to technology primitives). | |
| 7.35.7.1. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/abc9_map.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/abc9_map.v' to AST representation. | |
| Successfully finished Verilog frontend. | |
| 7.35.7.2. Continuing TECHMAP pass. | |
| Using template $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D for cells of type $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D. | |
| No more expansions possible. | |
| 7.35.8. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/abc9_model.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/abc9_model.v' to AST representation. | |
| Generating RTLIL representation for module `$__ABC9_DELAY'. | |
| Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. | |
| Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. | |
| Successfully finished Verilog frontend. | |
| 7.35.9. Executing SCC pass (detecting logic loops). | |
| Found an SCC: $auto$simplemap.cc:277:simplemap_mux$1692 $auto$simplemap.cc:277:simplemap_mux$1690 $auto$simplemap.cc:277:simplemap_mux$1688 $auto$simplemap.cc:277:simplemap_mux$1689 way_gen.tags.11.0.0 $techmap$techmap2104\way_gen.tags.22.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.22.0.0 way_gen.tags.14.0.0 way_gen.tags.17.0.0 $techmap$techmap2109\way_gen.tags.17.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $techmap$techmap2108\way_gen.tags.18.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.18.0.0 way_gen.tags.6.0.0 $techmap$techmap2101\way_gen.tags.6.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.15.0.0 way_gen.tags.0.0.0 $techmap$techmap2087\way_gen.tags.31.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.31.0.0 way_gen.tags.27.0.0 $auto$simplemap.cc:136:simplemap_reduce$1661 $techmap$techmap2107\way_gen.tags.19.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.19.0.0 way_gen.tags.23.0.0 $techmap$techmap2092\way_gen.tags.28.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.28.0.0 $techmap$techmap2083\way_gen.tags.14.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $techmap$techmap2100\way_gen.tags.0.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $techmap$techmap2089\way_gen.tags.11.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $techmap$techmap2111\way_gen.tags.3.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.3.0.0 way_gen.tags.29.0.0 $techmap$techmap2099\way_gen.tags.9.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.9.0.0 way_gen.tags.7.0.0 $auto$simplemap.cc:136:simplemap_reduce$1667 $techmap$techmap2090\way_gen.tags.30.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.30.0.0 $techmap$techmap2105\way_gen.tags.21.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.21.0.0 $techmap$techmap2095\way_gen.tags.25.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.25.0.0 way_gen.tags.16.0.0 $auto$simplemap.cc:136:simplemap_reduce$1662 $techmap$techmap2106\way_gen.tags.20.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.20.0.0 $auto$simplemap.cc:136:simplemap_reduce$1673 $auto$simplemap.cc:136:simplemap_reduce$1660 $techmap$techmap2110\way_gen.tags.16.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $auto$simplemap.cc:136:simplemap_reduce$1664 $techmap$techmap2096\way_gen.tags.24.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.24.0.0 $techmap$techmap2093\way_gen.tags.27.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $auto$simplemap.cc:136:simplemap_reduce$1653 $techmap$techmap2113\way_gen.tags.2.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.2.0.0 $techmap$techmap2086\way_gen.tags.4.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.4.0.0 $auto$simplemap.cc:136:simplemap_reduce$1654 $techmap$techmap2102\way_gen.tags.5.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.5.0.0 $auto$simplemap.cc:136:simplemap_reduce$1680 $auto$simplemap.cc:136:simplemap_reduce$1674 $auto$simplemap.cc:136:simplemap_reduce$1663 $techmap$techmap2097\way_gen.tags.23.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.26.0.0 $auto$simplemap.cc:136:simplemap_reduce$1676 $auto$simplemap.cc:136:simplemap_reduce$1666 $techmap$techmap2091\way_gen.tags.29.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $auto$simplemap.cc:136:simplemap_reduce$1669 $auto$simplemap.cc:136:simplemap_reduce$1652 $techmap$techmap2112\way_gen.tags.1.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.1.0.0 $auto$simplemap.cc:136:simplemap_reduce$1678 $auto$simplemap.cc:136:simplemap_reduce$1670 $auto$simplemap.cc:136:simplemap_reduce$1655 $techmap$techmap2103\way_gen.tags.7.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $auto$simplemap.cc:136:simplemap_reduce$1684 $auto$simplemap.cc:136:simplemap_reduce$1681 $auto$simplemap.cc:136:simplemap_reduce$1675 $auto$simplemap.cc:136:simplemap_reduce$1665 $techmap$techmap2094\way_gen.tags.26.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $auto$simplemap.cc:136:simplemap_reduce$1659 $techmap$techmap2114\way_gen.tags.15.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 $auto$simplemap.cc:136:simplemap_reduce$1657 $techmap$techmap2098\way_gen.tags.10.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.10.0.0 $techmap$techmap2085\way_gen.tags.12.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.12.0.0 $auto$simplemap.cc:136:simplemap_reduce$1671 $auto$simplemap.cc:136:simplemap_reduce$1656 $techmap$techmap2088\way_gen.tags.8.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.8.0.0 $auto$simplemap.cc:277:simplemap_mux$1691 $auto$simplemap.cc:85:simplemap_bitop$1687 $auto$simplemap.cc:85:simplemap_bitop$1722 $auto$simplemap.cc:136:simplemap_reduce$1783 $auto$simplemap.cc:85:simplemap_bitop$1784 $auto$simplemap.cc:136:simplemap_reduce$1686 $auto$simplemap.cc:136:simplemap_reduce$1683 $auto$simplemap.cc:136:simplemap_reduce$1679 $auto$simplemap.cc:136:simplemap_reduce$1672 $auto$simplemap.cc:136:simplemap_reduce$1658 $techmap$techmap2084\way_gen.tags.13.0.0.$auto$abc9_ops.cc:412:prep_bypass$2009 way_gen.tags.13.0.0 | |
| Found 1 SCCs in module cache_cpu. | |
| Found 1 SCCs. | |
| 7.35.10. Executing ABC9_OPS pass (helper functions for ABC9). | |
| 7.35.11. Executing ABC9_OPS pass (helper functions for ABC9). | |
| 7.35.12. Executing ABC9_OPS pass (helper functions for ABC9). | |
| 7.35.13. Executing TECHMAP pass (map to technology primitives). | |
| 7.35.13.1. Executing Verilog-2005 frontend: /home/petergu/.conda/envs/xc7/bin/../share/yosys/techmap.v | |
| Parsing Verilog input from `/home/petergu/.conda/envs/xc7/bin/../share/yosys/techmap.v' to AST representation. | |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_various'. | |
| Generating RTLIL representation for module `\_90_simplemap_registers'. | |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. | |
| Generating RTLIL representation for module `\_90_shift_shiftx'. | |
| Generating RTLIL representation for module `\_90_fa'. | |
| Generating RTLIL representation for module `\_90_lcu'. | |
| Generating RTLIL representation for module `\_90_alu'. | |
| Generating RTLIL representation for module `\_90_macc'. | |
| Generating RTLIL representation for module `\_90_alumacc'. | |
| Generating RTLIL representation for module `\$__div_mod_u'. | |
| Generating RTLIL representation for module `\$__div_mod_trunc'. | |
| Generating RTLIL representation for module `\_90_div'. | |
| Generating RTLIL representation for module `\_90_mod'. | |
| Generating RTLIL representation for module `\$__div_mod_floor'. | |
| Generating RTLIL representation for module `\_90_divfloor'. | |
| Generating RTLIL representation for module `\_90_modfloor'. | |
| Generating RTLIL representation for module `\_90_pow'. | |
| Generating RTLIL representation for module `\_90_pmux'. | |
| Generating RTLIL representation for module `\_90_lut'. | |
| Successfully finished Verilog frontend. | |
| 7.35.13.2. Continuing TECHMAP pass. | |
| Using template CARRY4 for cells of type CARRY4. | |
| Using extmapper simplemap for cells of type $or. | |
| Using extmapper simplemap for cells of type $mux. | |
| Using extmapper simplemap for cells of type $xor. | |
| No more expansions possible. | |
| 7.35.14. Executing OPT pass (performing simple optimizations). | |
| 7.35.14.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.35.14.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 1 cells. | |
| 7.35.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| No muxes found in this module. | |
| Removed 0 multiplexer ports. | |
| 7.35.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.35.14.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.35.14.6. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.35.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| Removed 0 unused cells and 14 unused wires. | |
| 7.35.14.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.35.14.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 7.35.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \cache_cpu.. | |
| Creating internal representation of mux trees. | |
| No muxes found in this module. | |
| Removed 0 multiplexer ports. | |
| 7.35.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \cache_cpu. | |
| Performed a total of 0 changes. | |
| 7.35.14.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\cache_cpu'. | |
| Removed a total of 0 cells. | |
| 7.35.14.13. Executing OPT_DFF pass (perform DFF optimizations). | |
| 7.35.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \cache_cpu.. | |
| 7.35.14.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module cache_cpu. | |
| 7.35.14.16. Finished OPT passes. (There is nothing left to do.) | |
| 7.35.15. Executing AIGMAP pass (map logic to AIG). | |
| Module cache_cpu: replaced 9 cells with 60 new cells, skipped 52 cells. | |
| replaced 3 cell types: | |
| 1 $_OR_ | |
| 4 $_XOR_ | |
| 4 $_MUX_ | |
| not replaced 1 cell types: | |
| 52 $specify2 | |
| 7.35.16. Executing AIGMAP pass (map logic to AIG). | |
| Module cache_cpu: replaced 48 cells with 207 new cells, skipped 167 cells. | |
| replaced 2 cell types: | |
| 43 $_OR_ | |
| 5 $_MUX_ | |
| not replaced 9 cell types: | |
| 17 $_NOT_ | |
| 4 $_AND_ | |
| 32 $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D_$abc9_byp | |
| 66 IBUF | |
| 1 OBUF | |
| 3 CARRY4 | |
| 11 FDRE | |
| 1 FDSE | |
| 32 $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D | |
| 7.35.16.1. Executing ABC9_OPS pass (helper functions for ABC9). | |
| 7.35.16.2. Executing ABC9_OPS pass (helper functions for ABC9). | |
| 7.35.16.3. Executing XAIGER backend. | |
| Extracted 62 AND gates and 406 wires from module `cache_cpu' to a netlist network with 114 inputs and 35 outputs. | |
| 7.35.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). | |
| 7.35.16.5. Executing ABC9. | |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 | |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". | |
| ABC: | |
| ABC: + read_lut <abc-temp-dir>/input.lut | |
| ABC: + read_box <abc-temp-dir>/input.box | |
| ABC: + &read <abc-temp-dir>/input.xaig | |
| ABC: + &ps | |
| ABC: <abc-temp-dir>/input : i/o = 114/ 35 and = 52 lev = 10 (3.74) mem = 0.01 MB box = 35 bb = 32 | |
| ABC: + &scorr | |
| ABC: Warning: The network is combinational. | |
| ABC: + &sweep | |
| ABC: The command has to terminate. Boxes are not in a topological order. | |
| ABC: The following information may help debugging (numbers are 0-based): | |
| ABC: Input 0 of BoxA 3 (1stCI = 138; 1stCO = 30) has TFI with CI 192, | |
| ABC: which corresponds to output 0 of BoxB 30 (1stCI = 192; 1stCO = 354). | |
| ABC: In a correct topological order, BoxB should precede BoxA. | |
| ABC: Error: Abc_FrameUpdateGia(): Tranformation has failed. | |
| ABC: + &dc2 | |
| ABC: Boxes are not in a topological order. Switching to level computation without boxes. | |
| ABC: + &dch -f | |
| ABC: + &ps | |
| ABC: <abc-temp-dir>/input : i/o = 114/ 35 and = 83 lev = 6 (0.77) mem = 0.01 MB ch = 5 box = 35 bb = 32 | |
| ABC: + &if -W 300 -v | |
| ABC: K = 6. Memory (bytes): Truth = 0. Cut = 56. Obj = 136. Set = 600. CutMin = no | |
| ABC: Node = 83. Ch = 5. Total mem = 0.11 MB. Peak cut mem = 0.00 MB. | |
| ABC: P: Del = 2936.00. Ar = 68.0. Edge = 78. Cut = 372. T = 0.00 sec | |
| ABC: P: Del = 2856.00. Ar = 67.0. Edge = 77. Cut = 364. T = 0.00 sec | |
| ABC: P: Del = 2856.00. Ar = 57.0. Edge = 70. Cut = 452. T = 0.00 sec | |
| ABC: F: Del = 2856.00. Ar = 57.0. Edge = 69. Cut = 389. T = 0.00 sec | |
| ABC: A: Del = 2856.00. Ar = 57.0. Edge = 69. Cut = 396. T = 0.00 sec | |
| ABC: A: Del = 2856.00. Ar = 57.0. Edge = 69. Cut = 397. T = 0.00 sec | |
| ABC: Total time = 0.00 sec | |
| ABC: + &write -n <abc-temp-dir>/output.aig | |
| ABC: + &mfs | |
| ABC: The network is not changed by "&mfs". | |
| ABC: + &ps -l | |
| ABC: <abc-temp-dir>/input : i/o = 114/ 35 and = 50 lev = 6 (0.77) mem = 0.01 MB box = 35 bb = 32 | |
| ABC: Mapping (K=6) : lut = 20 edge = 69 lev = 3 (0.75) levB = 4 mem = 0.00 MB | |
| ABC: LUT = 20 : 2=11 55.0 % 3=0 0.0 % 4=2 10.0 % 5=3 15.0 % 6=4 20.0 % Ave = 3.45 | |
| ABC: + &write -n <abc-temp-dir>/output.aig | |
| ABC: + time | |
| ABC: elapse: 0.01 seconds, total: 0.01 seconds | |
| 7.35.16.6. Executing AIGER frontend. | |
| Removed 72 unused cells and 731 unused wires. | |
| 7.35.16.7. Executing ABC9_OPS pass (helper functions for ABC9). | |
| ABC RESULTS: $lut cells: 23 | |
| ABC RESULTS: $paramod$28e244a1308df843a1293a31d7ce146bf1fd525e\RAM32X1D_$abc9_byp cells: 32 | |
| ABC RESULTS: \CARRY4 cells: 3 | |
| /home/petergu/opt/symbiflow/xc7/install/bin/symbiflow_synth: line 109: 16744 Segmentation fault (core dumped) yosys -p "tcl ${SYNTH_TCL_PATH}" -l $LOG ${VERILOG_FILES[*]} | |
| make: *** [Makefile:68: build/cache_cpu.eblif] Error 139 |
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