Skip to content

Instantly share code, notes, and snippets.

@rescurib

rescurib/Fixed_Point_Multiplication.vhd

Created December 2, 2017 03:45
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save rescurib/2159f297bd609970cfd68e68cc9b5860 to your computer and use it in GitHub Desktop.
Save rescurib/2159f297bd609970cfd68e68cc9b5860 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
Fixed_Point_Multiplication.vhd
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\Generador_Coseno_HDL\Fixed_Point_Multiplication.vhd
-- Created: 2017-12-01 00:57:53
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Fixed_Point_Multiplication
-- Source Path: Generador_Coseno_HDL/Fixed-Point Multiplication
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Fixed_Point_Multiplication IS
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- int16
Out1 : OUT std_logic_vector(15 DOWNTO 0) -- int16
);
END Fixed_Point_Multiplication;
ARCHITECTURE rtl OF Fixed_Point_Multiplication IS
-- Constants
CONSTANT C_divbyzero_p : signed(65 DOWNTO 0) := signed'("011111111111111111111111111111111111111111111111111111111111111111"); -- sfix66
CONSTANT C_divbyzero_n : signed(65 DOWNTO 0) := signed'("100000000000000000000000000000000000000000000000000000000000000000"); -- sfix66
-- Signals
SIGNAL In1_signed : signed(15 DOWNTO 0); -- int16
SIGNAL Constant_out1 : signed(15 DOWNTO 0); -- int16
SIGNAL Product1_out1 : signed(31 DOWNTO 0); -- int32
SIGNAL Slope_sfix_16_16_out1 : signed(31 DOWNTO 0); -- int32
SIGNAL Product_out1 : signed(63 DOWNTO 0); -- sfix64
SIGNAL Product_out1_dtc : signed(64 DOWNTO 0); -- sfix65
SIGNAL Constant2_out1 : signed(31 DOWNTO 0); -- int32
SIGNAL Divide_div_temp : signed(65 DOWNTO 0); -- sfix66
SIGNAL Divide_slice_cast : signed(65 DOWNTO 0); -- sfix66
SIGNAL Divide_out1 : signed(15 DOWNTO 0); -- int16
BEGIN
-- cos(\omegaT)
-- [en fixdt(0,10,slope,b)]
--
-- 1/slope
In1_signed <= signed(In1);
Constant_out1 <= to_signed(16#012C#, 16);
Product1_out1 <= In1_signed * Constant_out1;
Slope_sfix_16_16_out1 <= to_signed(211, 32);
Product_out1 <= Product1_out1 * Slope_sfix_16_16_out1;
Product_out1_dtc <= resize(Product_out1, 65);
Constant2_out1 <= to_signed(65536, 32);
Divide_slice_cast <= resize(Product_out1_dtc, 66);
Divide_div_temp <= C_divbyzero_p WHEN (Constant2_out1 = 0) AND (Divide_slice_cast(65) = Constant2_out1(31)) ELSE
C_divbyzero_n WHEN Constant2_out1 = 0 ELSE
resize(Product_out1_dtc, 66) / Constant2_out1;
Divide_out1 <= X"7FFF" WHEN (Divide_div_temp(65) = '0') AND (Divide_div_temp(64 DOWNTO 15) /= "00000000000000000000000000000000000000000000000000") ELSE
X"8000" WHEN (Divide_div_temp(65) = '1') AND (Divide_div_temp(64 DOWNTO 15) /= "11111111111111111111111111111111111111111111111111") ELSE
Divide_div_temp(15 DOWNTO 0);
Out1 <= std_logic_vector(Divide_out1);
END rtl;
Raw
Fixed_Point_Multiplication2.vhd
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\Generador_Coseno_HDL\Fixed_Point_Multiplication1.vhd
-- Created: 2017-12-01 00:57:53
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Fixed_Point_Multiplication1
-- Source Path: Generador_Coseno_HDL/Fixed-Point Multiplication1
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Fixed_Point_Multiplication1 IS
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- int16
Out1 : OUT std_logic_vector(15 DOWNTO 0) -- int16
);
END Fixed_Point_Multiplication1;
ARCHITECTURE rtl OF Fixed_Point_Multiplication1 IS
-- Signals
SIGNAL In1_signed : signed(15 DOWNTO 0); -- int16
SIGNAL Constant_out1 : signed(15 DOWNTO 0); -- int16
SIGNAL Product1_out1 : signed(31 DOWNTO 0); -- int32
SIGNAL Gain_mul_temp : signed(63 DOWNTO 0); -- sfix64_En39
SIGNAL Gain_out1 : signed(15 DOWNTO 0); -- int16
BEGIN
In1_signed <= signed(In1);
Constant_out1 <= to_signed(16#0258#, 16);
Product1_out1 <= In1_signed * Constant_out1;
Gain_mul_temp <= to_signed(1773405851, 32) * Product1_out1;
Gain_out1 <= Gain_mul_temp(54 DOWNTO 39);
Out1 <= std_logic_vector(Gain_out1);
END rtl;
Raw
Generador_Coseno_HDL.vhd
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\Generador_Coseno_HDL\Generador_Coseno_HDL.vhd
-- Created: 2017-12-01 00:57:53
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 1
-- Target subsystem base rate: 1
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 1
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- Out1 ce_out 1
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Generador_Coseno_HDL
-- Source Path: Generador_Coseno_HDL
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.Generador_Coseno_HDL_pkg.ALL;
ENTITY Generador_Coseno_HDL IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
ce_out : OUT std_logic;
Out1 : OUT std_logic_vector(15 DOWNTO 0) -- int16
);
END Generador_Coseno_HDL;
ARCHITECTURE rtl OF Generador_Coseno_HDL IS
-- Component Declarations
COMPONENT Impulse
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
Out1 : OUT std_logic_vector(15 DOWNTO 0) -- int16
);
END COMPONENT;
COMPONENT Fixed_Point_Multiplication
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- int16
Out1 : OUT std_logic_vector(15 DOWNTO 0) -- int16
);
END COMPONENT;
COMPONENT Fixed_Point_Multiplication1
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- int16
Out1 : OUT std_logic_vector(15 DOWNTO 0) -- int16
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Impulse
USE ENTITY work.Impulse(rtl);
FOR ALL : Fixed_Point_Multiplication
USE ENTITY work.Fixed_Point_Multiplication(rtl);
FOR ALL : Fixed_Point_Multiplication1
USE ENTITY work.Fixed_Point_Multiplication1(rtl);
-- Signals
SIGNAL enb : std_logic;
SIGNAL x : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL x_signed : signed(15 DOWNTO 0); -- int16
SIGNAL Delay2_out1 : signed(15 DOWNTO 0); -- int16
SIGNAL Fixed_Point_Multiplication_out1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL Fixed_Point_Multiplication_out1_signed : signed(15 DOWNTO 0); -- int16
SIGNAL Add_op_stage2 : signed(31 DOWNTO 0); -- sfix32
SIGNAL y : signed(15 DOWNTO 0); -- int16
SIGNAL Delay_out1 : signed(15 DOWNTO 0); -- int16
SIGNAL Fixed_Point_Multiplication1_out1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL Fixed_Point_Multiplication1_out1_signed : signed(15 DOWNTO 0); -- int16
SIGNAL Delay1_reg : vector_of_signed16(0 TO 1); -- sfix16 [2]
SIGNAL Delay1_out1 : signed(15 DOWNTO 0); -- int16
SIGNAL Add_op_stage3 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Add_stage4_add_temp : signed(31 DOWNTO 0); -- sfix32
SIGNAL Constant_out1 : signed(15 DOWNTO 0); -- int16
SIGNAL Add1_out1 : signed(15 DOWNTO 0); -- int16
BEGIN
-- \omega = 2\pi/25
-- T = 1s
u_Impulse : Impulse
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
Out1 => x -- int16
);
u_Fixed_Point_Multiplication : Fixed_Point_Multiplication
PORT MAP( In1 => std_logic_vector(Delay2_out1), -- int16
Out1 => Fixed_Point_Multiplication_out1 -- int16
);
u_Fixed_Point_Multiplication1 : Fixed_Point_Multiplication1
PORT MAP( In1 => std_logic_vector(Delay_out1), -- int16
Out1 => Fixed_Point_Multiplication1_out1 -- int16
);
x_signed <= signed(x);
enb <= clk_enable;
Delay2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Delay2_out1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay2_out1 <= x_signed;
END IF;
END IF;
END PROCESS Delay2_process;
Fixed_Point_Multiplication_out1_signed <= signed(Fixed_Point_Multiplication_out1);
Add_op_stage2 <= resize(x_signed, 32) - resize(Fixed_Point_Multiplication_out1_signed, 32);
Delay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Delay_out1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay_out1 <= y;
END IF;
END IF;
END PROCESS Delay_process;
Fixed_Point_Multiplication1_out1_signed <= signed(Fixed_Point_Multiplication1_out1);
Delay1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Delay1_reg <= (OTHERS => to_signed(16#0000#, 16));
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay1_reg(0) <= y;
Delay1_reg(1) <= Delay1_reg(0);
END IF;
END IF;
END PROCESS Delay1_process;
Delay1_out1 <= Delay1_reg(1);
Add_op_stage3 <= Add_op_stage2 - resize(Delay1_out1, 32);
Add_stage4_add_temp <= Add_op_stage3 + resize(Fixed_Point_Multiplication1_out1_signed, 32);
y <= Add_stage4_add_temp(15 DOWNTO 0);
Constant_out1 <= to_signed(16#01FF#, 16);
Add1_out1 <= y + Constant_out1;
Out1 <= std_logic_vector(Add1_out1);
ce_out <= clk_enable;
END rtl;
Raw
Impulse.vhd
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\Generador_Coseno_HDL\Impulse.vhd
-- Created: 2017-12-01 00:57:53
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Impulse
-- Source Path: Generador_Coseno_HDL/Impulse
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Impulse IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
Out1 : OUT std_logic_vector(15 DOWNTO 0) -- int16
);
END Impulse;
ARCHITECTURE rtl OF Impulse IS
-- Signals
SIGNAL Constant_out1 : signed(15 DOWNTO 0); -- int16
SIGNAL Delay3_out1 : signed(15 DOWNTO 0); -- int16
SIGNAL Add1_out1 : signed(15 DOWNTO 0); -- int16
BEGIN
Constant_out1 <= to_signed(16#0000#, 16);
Delay3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Delay3_out1 <= to_signed(16#0136#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay3_out1 <= Constant_out1;
END IF;
END IF;
END PROCESS Delay3_process;
Add1_out1 <= Constant_out1 + Delay3_out1;
Out1 <= std_logic_vector(Add1_out1);
END rtl;
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment