Control.vhd

----------------------------------------------------------------------------------
-- Company: BUAP
-- Engineer: Rodolfo Emilio Escobar Uribe
-- 
-- Create Date:    20:42:27 10/15/2017 
-- Design Name: 
-- Module Name:    Control - Behavioral 
-- Project Name:  Qik 2s12v10 Dual Serial Motor Controller VHDL module
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Control is
    Port ( data_out : out  STD_LOGIC_VECTOR (7 downto 0):="00000000";
	        data_M0  : in   STD_LOGIC_VECTOR (7 downto 0):="00000000";
			  data_M1  : in   STD_LOGIC_VECTOR (7 downto 0):="00000000";
			  EN		  : in STD_LOGIC := '0';
			  RESET	  : in STD_LOGIC := '0';
           clk_control : in  STD_LOGIC; 
           Tx_ini : out  STD_LOGIC := '0';			  
           Tx_fin : in  STD_LOGIC;
           Rx_rd : in  STD_LOGIC;
			  Reset_qik : out STD_LOGIC;
			  ERR   : in STD_LOGIC);
end Control;

architecture Behavioral of Control is
--- ROM (Qik2s12v10 commands)
    type rom_type is array (5 downto 0) of std_logic_vector (7 downto 0);
    constant COMMANDS : rom_type :=(x"88", -- QIK_MOTOR_M0_FORWARD       [5]
				    x"8A", -- QIK_MOTOR_M0_REVERSE       [4]
				    x"8C", -- QIK_MOTOR_M1_FORWARD       [3]
				    x"8E", -- QIK_MOTOR_M1_REVERSE       [2]
				    x"86", -- QIK_2S12V10_MOTOR_M0_BRAKE [1]
				    x"87"  -- QIK_2S12V10_MOTOR_M1_BRAKE [0]
                                   );  
---
--- velocities
    signal velM0 : signed(7 downto 0)   := (others => '0');
	 signal ComM0 : std_logic_vector (7 downto 0);
	 signal velM1 : signed(7 downto 0)   := (others => '0');
	 signal ComM1 : std_logic_vector (7 downto 0);
---	 
--- States
	signal edo : integer range 0 to 8 := 0;
---
--- Flags
   signal flag0: std_logic :='0';
	signal flag1: std_logic :='0'; -- init delay flag
	signal flag2: std_logic :='0'; -- out delay flag 1
	signal flag3: std_logic :='0'; -- out delay flag 2
---
--- Constants
   CONSTANT FIN : INTEGER := 500000;
----
---- Other signals
	SIGNAL i : integer range 0 to FIN:=0;
----	
begin
	-- Command selection
    velM0 <= SIGNED(data_M0);
	 velM1 <= SIGNED(data_M1);
	 
    ComM0 <= COMMANDS(5) when velM0 > 0 else           -- M0 Forward
		       COMMANDS(1) when velM0 = 0 else -- M0 Brake
		       COMMANDS(4);  		       -- M0 Reverse
				 
    ComM1 <= COMMANDS(3) when velM1 > 0 else            -- M1 Forward
		       COMMANDS(0) when velM1 = 0 else  -- M1 Brake			 
		       COMMANDS(2);    		        -- M1 Reverse
   --
   -- Finite State Machine
	PROCESS ( CLK_CONTROL )BEGIN
IF RISING_EDGE(CLK_CONTROL) THEN

	IF  RESET = '1' THEN -- RESET
	     flag0 <= '0';
	     flag1  <= '0';
		  flag2  <= '0';
		  tx_ini <= '0';
		  EDO <= 0;
		  
	ELSIF EDO = 0 THEN -- Init state
	   IF flag1 = '0' THEN
		   RESET_QIK <= '0';
			i<=i+1;       
		   IF i=FIN THEN -- after 10ms delay
			  i <= 0;
			  flag1 <= '1';
			  RESET_QIK <= '1';
			END IF;
			
		ELSIF flag0 = '0' and flag2 = '1' THEN
		   data_out <= x"AA"; -- Auto-baud secuence
			flag0 <= '1';
			Tx_ini <='1';
			
		ELSIF Tx_fin ='1' and flag0 = '1' THEN
			Tx_ini <='0';
                        flag0 <= '0';
			EDO <= 1;
			
		ElSIF flag1 = '1' and flag2 = '0' THEN
			i<=i+1;       
		   IF i=FIN THEN -- after 10ms delay
			  i <= 0;
			  flag2 <= '1';
			END IF;
		
		ELSIF Tx_fin ='0' and flag0 = '1' THEN
			EDO<=0;
		END IF;
		
	ElSIF EDO = 1 THEN -- Write M0 command
		IF Tx_fin ='1' and flag0 = '0' THEN
		   data_out <= ComM0;
			flag0 <= '1';
			Tx_ini <='1';
		ELSIF Tx_fin ='1' and flag0 = '1' THEN
		   EDO <=2;
			flag0 <= '0';
			Tx_ini <='0';
		ELSIF Tx_fin ='0' and flag0 = '0' THEN
			EDO<=1;
		END IF;
		
	ELSIF EDO = 2 THEN -- Write M0 value
		IF Tx_fin ='1' and flag0 = '0' THEN
		   data_out <= std_logic_vector(abs velM0);
			flag0 <= '1';
			Tx_ini <='1';
		ELSIF Tx_fin ='1' and flag0 = '1' THEN
		   EDO <=3;
			flag0 <= '0';
			Tx_ini <='0';
		ELSIF Tx_fin ='0' and flag0 = '0' THEN
			EDO<=2;
		END IF;
		
	ElSIF EDO = 3 THEN -- Write M1 command
		IF Tx_fin ='1' and flag0 = '0' THEN
		   data_out <= ComM1;
			flag0 <= '1';
			Tx_ini <='1';
		ELSIF Tx_fin ='1' and flag0 = '1' THEN
		   EDO <=4;
			flag0 <= '0';
			Tx_ini <='0';
		ELSIF Tx_fin ='0' and flag0 = '0' THEN
			EDO<=3;
		END IF;
		
	ELSIF EDO = 4 THEN -- Write M1 value
		IF Tx_fin ='1' and flag0 = '0' THEN
		   data_out <= std_logic_vector(abs velM1);
			flag0 <= '1';
			Tx_ini <='1';
		ELSIF Tx_fin ='1' and flag0 = '1' THEN
		   EDO <=1;
			flag0 <= '0';
			Tx_ini <='0';
		ELSIF Tx_fin ='0' and flag0 = '0' THEN
			EDO<=4;
		END IF;
	END IF;
END IF;
END PROCESS;
	
end Behavioral;