fixed-point_mult.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fixed_mult is
    Port ( ADC : in  STD_LOGIC_VECTOR (11 downto 0);
           DAC : out  STD_LOGIC_VECTOR (11 downto 0));
end fixed_mult;

architecture Behavioral of fixed_mult is
  -- Señales
  SIGNAL ADC_temp	   : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
  SIGNAL In1_unsigned      : unsigned(15 DOWNTO 0);                -- uint16
  SIGNAL Gain_mul_temp     : unsigned(31 DOWNTO 0) := x"00000000"; -- ufix32_10
  SIGNAL Gain_mul_temp_sr  : unsigned(31 DOWNTO 0) := x"00000000" ;-- ufix32_10
  SIGNAL Gain_out          : unsigned(15 DOWNTO 0);                -- uint16
  --
begin
  ADC_temp(11 downto 0) <= ADC;
  In1_unsigned <= unsigned(ADC_temp); -- Conversión a uint16
  Gain_mul_temp <= to_unsigned(10#329#, 16) * In1_unsigned; -- 0.321 en ufix12_10
  Gain_mul_temp_sr <= shift_right(Gain_mul_temp,10);
  Gain_out <= Gain_mul_temp_sr(15 DOWNTO 0);
  DAC <= std_logic_vector(Gain_out(11 downto 0)); --ufix12_10

end Behavioral;