divisor.vhd

library ieee;
use ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

entity divisor is
port ( pulso : inout std_logic:='0';
       clk   : in std_logic);
        
end entity;

architecture div of divisor is
signal count : integer :=1;
begin
process(clk) begin
   if(clk'event and clk='1') then
      count <=count+1;
      if(count = 25000000) then --count = frec de reloj/frec deseada
         PULSO <= not PULSO;
         count <=1;
      end if;
  end if;
end process;

end architecture;