Last active
March 1, 2024 11:22
-
-
Save retrage/e0377380dfdbcd9aebe68ee360908d3d to your computer and use it in GitHub Desktop.
OpenOCD config for VisionFive 2 with Sipeed RV-Debugger-Plus
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
# REF: https://github.com/orangecms/RV-Debugger-BL702/blob/nezha/tools/openocd/openocd-usb-sipeed.cfg | |
# REF: https://github.com/strangerover2002/visionfive2-/blob/main/u74.cfg | |
# SiPEED USB-JTAG/TTL based on FT2232D | |
adapter driver ftdi | |
ftdi vid_pid 0x0403 0x6010 | |
# http://blog.sipeed.com/p/727.html | |
ftdi channel 0 | |
reset_config trst_only | |
transport select jtag | |
adapter speed 1000 | |
ftdi layout_init 0x0508 0x0f1b | |
ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 | |
ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 | |
jtag newtap e24 cpu -irlen 5 -expected-id 0x07110cfd | |
jtag newtap u74 cpu -irlen 5 -expected-id 0x07110cfd | |
target create e24.cpu0 riscv -chain-position u74.cpu -coreid 0 -rtos hwthread | |
target create u74.cpu1 riscv -chain-position u74.cpu -coreid 1 | |
target create u74.cpu2 riscv -chain-position u74.cpu -coreid 2 | |
target create u74.cpu3 riscv -chain-position u74.cpu -coreid 3 | |
target create u74.cpu4 riscv -chain-position u74.cpu -coreid 4 | |
target smp e24.cpu0 u74.cpu1 u74.cpu2 u74.cpu3 u74.cpu4 #remove for separate harts gdb | |
init |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment