A patch for setup_pll.adb/

stm32f410.patch

diff --git a/arm/stm32/setup_pll.adb b/arm/stm32/setup_pll.adb
index e6b1dcc..29124f5 100644
--- a/arm/stm32/setup_pll.adb
+++ b/arm/stm32/setup_pll.adb
@@ -102,7 +102,7 @@ procedure Setup_Pll is
                        else (if HSE_Enabled then SYSCLK_SRC_HSE
                              else SYSCLK_SRC_HSI));
       SW_Value    : constant CFGR_SW_Field :=
-                      SYSCLK_Source'Enum_Rep (SW);
+        (As_Array => False, Val => SYSCLK_Source'Enum_Rep (SW));
 
       SYSCLK      : constant Integer := (if Activate_PLL
                                          then PLLCLKOUT
@@ -217,10 +217,10 @@ procedure Setup_Pll is
          --  Configure the PLL clock source, multiplication and division
          --  factors
          RCC_Periph.PLLCFGR :=
-           (PLLM   => PLLM,
-            PLLN   => PLLN,
-            PLLP   => PLLP,
-            PLLQ   => PLLQ,
+           (PLLM   => (As_Array => False, Val => PLLM),
+            PLLN   => (As_Array => False, Val => PLLN),
+            PLLP   => (As_Array => False, Val => PLLP),
+            PLLQ   => (As_Array => False, Val => PLLQ),
             PLLSRC => (if HSE_Enabled
                        then PLL_Source'Enum_Rep (PLL_SRC_HSE)
                        else PLL_Source'Enum_Rep (PLL_SRC_HSI)),
@@ -261,7 +261,7 @@ procedure Setup_Pll is
                      Arr      => (1 => To_APB (APB1_PRE),
                                   2 => To_APB (APB2_PRE))),
          RTCPRE  => 16#0#,
-         I2SSRC  => I2S_Clock_Selection'Enum_Rep (I2SSEL_PLL),
+--         I2SSRC  => I2S_Clock_Selection'Enum_Rep (I2SSEL_PLL),
          MCO1    => MC01_Clock_Selection'Enum_Rep (MC01SEL_HSI),
          MCO1PRE => MC0x_Prescaler'Enum_Rep (MC0xPRE_DIV1),
          MCO2    => MC02_Clock_Selection'Enum_Rep (MC02SEL_SYSCLK),
@@ -270,7 +270,7 @@ procedure Setup_Pll is
 
       if Activate_PLL then
          loop
-            exit when RCC_Periph.CFGR.SWS =
+            exit when RCC_Periph.CFGR.SWS.Val =
               SYSCLK_Source'Enum_Rep (SYSCLK_SRC_PLL);
          end loop;
 
--- a/arm/stm32/stm32f40x/s-stm32.adb	2021-04-05 16:22:57.115945680 +0300
+++ b/arm/stm32/stm32f40x/s-stm32.adb	2021-04-05 17:08:53.426869146 +0300
@@ -50,7 +50,7 @@
    function System_Clocks return RCC_System_Clocks
    is
       Source       : constant SYSCLK_Source :=
-                      SYSCLK_Source'Val (RCC_Periph.CFGR.SWS);
+                      SYSCLK_Source'Val (RCC_Periph.CFGR.SWS.Val);
       Result       : RCC_System_Clocks;
 
    begin
@@ -70,9 +70,9 @@
 
          when SYSCLK_SRC_PLL =>
             declare
-               Pllm   : constant UInt32 := UInt32 (RCC_Periph.PLLCFGR.PLLM);
-               Plln   : constant UInt32 := UInt32 (RCC_Periph.PLLCFGR.PLLN);
-               Pllp   : constant UInt32 := UInt32 (RCC_Periph.PLLCFGR.PLLP);
+               Pllm : constant UInt32 := UInt32 (RCC_Periph.PLLCFGR.PLLM.Val);
+               Plln : constant UInt32 := UInt32 (RCC_Periph.PLLCFGR.PLLN.Val);
+               Pllp : constant UInt32 := UInt32 (RCC_Periph.PLLCFGR.PLLP.Val);
                Pllvco : UInt32;
 
             begin