Last active
December 14, 2015 03:59
-
-
Save rigid/5025299 to your computer and use it in GitHub Desktop.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
static void RCC_Config(void) | |
{ | |
/* RCC system reset */ | |
RCC_DeInit(); | |
/* Enable HSE */ | |
RCC_HSEConfig(RCC_HSE_ON); | |
/* Wait till HSE is ready */ | |
ErrorStatus status; | |
if((status = RCC_WaitForHSEStartUp()) == SUCCESS) | |
{ | |
/* Enable Prefetch Buffer */ | |
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); | |
/* Flash 2 wait state */ | |
FLASH_SetLatency(FLASH_Latency_2); | |
/* HCLK = SYSCLK */ | |
RCC_HCLKConfig(RCC_SYSCLK_Div1); | |
/* PCLK2 = HCLK */ | |
RCC_PCLK2Config(RCC_HCLK_Div1); | |
/* PCLK1 = HCLK/2 */ | |
RCC_PCLK1Config(RCC_HCLK_Div2); | |
/* SysTick counter */ | |
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); | |
#ifdef STM32F10X_CL | |
/* Configure PLLs *********************************************************/ | |
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ | |
RCC_PREDIV2Config(RCC_PREDIV2_Div5); | |
RCC_PLL2Config(RCC_PLL2Mul_8); | |
/* Enable PLL2 */ | |
RCC_PLL2Cmd(ENABLE); | |
/* Wait till PLL2 is ready */ | |
while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET); | |
/* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ | |
RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); | |
RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9); | |
#else | |
/* PLLCLK = 8MHz * 9 = 72 MHz */ | |
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); | |
#endif | |
/* Enable PLL */ | |
RCC_PLLCmd(ENABLE); | |
/* Wait till PLL is ready */ | |
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET); | |
/* Select PLL as system clock source */ | |
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); | |
/* Wait till PLL is used as system clock source */ | |
while(RCC_GetSYSCLKSource() != 0x08); | |
} | |
} | |
static void GPIO_Config() | |
{ | |
/** initialize SPI pins and "mode" pin */ | |
GPIO_InitTypeDef gpio = | |
{ | |
.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_4 | | |
GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7, | |
.GPIO_Mode = GPIO_Mode_AF_PP, | |
.GPIO_Speed = GPIO_Speed_50MHz, | |
}; | |
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); | |
/* init pin */ | |
GPIO_Init(GPIOA, &gpio); | |
/* TIM2_CH2 pin (PA.01) configuration */ | |
gpio.GPIO_Pin = GPIO_Pin_1; | |
gpio.GPIO_Mode = GPIO_Mode_IPD; | |
GPIO_Init(GPIOA, &gpio); | |
} | |
/******************************************************************************/ | |
int main(void) | |
{ | |
/* System clocks configuration */ | |
RCC_Config(); | |
/* initialize GPIO */ | |
GPIO_Config(); | |
/**** initialize SPI port */ | |
/* clock */ | |
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); | |
/* SPI config */ | |
SPI_InitTypeDef spi = | |
{ | |
.SPI_Direction = SPI_Direction_1Line_Tx, | |
.SPI_Mode = SPI_Mode_Master, | |
.SPI_DataSize = SPI_DataSize_16b, | |
.SPI_CPOL = SPI_CPOL_High, | |
.SPI_CPHA = SPI_CPHA_2Edge, | |
.SPI_NSS = SPI_NSS_Soft, | |
.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4, | |
.SPI_FirstBit = SPI_FirstBit_MSB, | |
.SPI_CRCPolynomial = 7, | |
}; | |
SPI_Init(SPI1, &spi); | |
/* Enable SPI_MASTER NSS output for master mode */ | |
SPI_SSOutputCmd(SPI1, ENABLE); | |
/* Enable SPI_MASTER */ | |
SPI_Cmd(SPI1, ENABLE); | |
/**** initialize timer */ | |
/* set mode pin high after n SCK pulses. | |
(and low again after 16-n sck pulses) | |
*/ | |
u16 n = 2; | |
/* wrap timer after 16 clock cycles */ | |
#define PERIOD 16 | |
/* clock */ | |
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); | |
/* time base configuration */ | |
TIM_TimeBaseInitTypeDef tim; | |
TIM_TimeBaseStructInit(&tim); | |
tim.TIM_Period = PERIOD, | |
tim.TIM_Prescaler = 0, | |
tim.TIM_ClockDivision = TIM_CKD_DIV1, | |
tim.TIM_CounterMode = TIM_CounterMode_Up, | |
TIM_TimeBaseInit(TIM2, &tim); | |
/** | |
* Figure 121. TI2 external clock connection example | |
* Step 1-4 | |
*/ | |
TIM_TIxExternalClockConfig(TIM2, | |
TIM_TIxExternalCLK1Source_TI2, | |
TIM_ICPolarity_Falling, 0); | |
/* Step 5 */ | |
TIM_SelectInputTrigger(TIM2, TIM_TS_TI2FP2); | |
/* output compare configuration */ | |
TIM_OCInitTypeDef timOC; | |
TIM_OCStructInit(&timOC); | |
timOC.TIM_OCMode = TIM_OCMode_PWM2; | |
timOC.TIM_OutputState = TIM_OutputState_Enable; | |
timOC.TIM_Pulse = n-1; | |
timOC.TIM_OCPolarity = TIM_OCPolarity_High; | |
TIM_OC3Init(TIM2, &timOC); | |
TIM_SelectOnePulseMode(TIM2, TIM_OPMode_Single); | |
u16 d = 0b0100000000000010; | |
while(1) | |
{ | |
/* wait for previous transmit to complete */ | |
while(!(SPI1->SR & SPI_I2S_FLAG_TXE)); | |
/* delay for scope */ | |
for(volatile int i=0; i<2; i++); | |
/* reset timer/capture counter */ | |
TIM2->CR1 &= ~TIM_CR1_CEN; | |
TIM2->CCR1 = 0; | |
TIM2->CNT = 0; | |
TIM2->CR1 |= TIM_CR1_CEN; | |
/* start SPI transfer of 16 bit packet */ | |
SPI1->DR = d; | |
} | |
} |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment