Sample VHDL Code

example.vhd

-- --------------------------------------------------------------------.
--
-- Example VHDL Component Organization
--
--   Title      :  example
--              :
--   Library    :  work
--              :
--   Developers :  Rijul Gupta (rijulg@gmail.com)
--              :
--   Purpose    :  This component is used to demonstrate the
--              :  code organization of a component
--              :
--   License    :  MIT
-- --------------------------------------------------------------------
-- $Revision: #1 $
-- $Date: 25 August 2018 $
-- --------------------------------------------------------------------

-- Importing required libraries
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Declaring the library that this component will live in
library work;

-- declaration: the high-level description of the component
-- The component has 2 input ports reset and clk and 1 
-- output port y 
entity example is
port (reset : in  std_logic;
        clk   : in  std_logic;
        y : out std_logic_vector(31 downto 0));
end example;

-- Here we are defining the behaviour of the component
-- At the beginning we define the signals, components and functions
-- that we intend to use inside this component
-- the actual process that this component executes starts from the
-- "begin" block
architecture behavioral of example is

    -- Signals can be thought of as wires internal to the component
    -- these can be then used inside the component as variables
    signal pc : std_logic_vector(31 downto 0) := x"00000000";
    signal alu_A : std_logic_vector(31 downto 0) := x"00000000";
    signal alu_B : std_logic_vector(31 downto 0) := x"00000000";

    -- This is a sub-component that we will use inside our component
    -- it must have been defined somewhere else in the work library
    -- Here again we define the ports that this subcomponent will be using
    component alu is
    port (alu_func : in  alu_func_t;
            op1      : in  std_logic_vector(31 downto 0);
            op2      : in  std_logic_vector(31 downto 0);
            result   : out std_logic_vector(31 downto 0));
    end component alu;

    -- function aluop
    -- This is an example for a simple function that takes 1 input
    -- and returns 1 output.
    --
    -- Returns an ALU Function based on opcode
    -- @param std_logic_vector opcode (8 bit)
    -- @return alu_func_t 
    function aluop(
        opcode : in std_logic_vector(2 downto 0))
        return alu_func_t is
        begin
            case (opcode) is
                when b"000" => return ALU_ADD;
                when b"001" => return ALU_XOR;
                when others => return ALU_NONE;
            end case;
    end function aluop;

    -- This is the actions that this component performs
    Begin

        -- We are using the sub-component that we had declared earlier here
        -- We are giving it 3 signals/wires as input and 1 signal/wire as
        -- output.
        alu0: alu port map(
            alu_func => alu_func,
            op1 => alu_A,
            op2 => alu_B,
            result => y);

        -- These are a few example statements
        -- the first one is a function call while the rest are 
        -- simple assignment operations.
        -- These will be translated to a hardware operation and will be
        -- converted to a physical wire connection
        alu_func <= aluop(pc(2 downto 0));
        alu_A <= pc;
        alu_B <= pc+1;
        
        -- This is an example process
        -- the following code executes when either reset or clk changes
        -- the code inside it executes sequentially
        acc: process(reset, clk) 
        begin 
            if (reset = '1') then 
                pc <= (others => '0');
            elsif rising_edge(clk) then 
                pc <= pc + 1;
            end if; 
        end process; 

end architecture;