opcode.sh - Searches disassembled code for specific instructions.
| #!/bin/bash | |
| # | |
| # Last update on Nov 05, 2014. | |
| # | |
| # Searches disassembled code for specific instructions. | |
| # | |
| # Opcodes obtained from: https://github.com/Shirk/vim-gas/blob/master/syntax/gas.vim | |
| # | |
| # List of opcodes has been obtained using the following commands and making a few modifications: | |
| # echo '#!/bin/bash' > Opcode_list | |
| # wget -q -O- https://raw.githubusercontent.com/Shirk/vim-gas/master/syntax/gas.vim \ | |
| # | grep -B1 -E 'syn keyword gasOpcode_|syn match gasOpcode' | \ | |
| # sed -e '/^--$/d' -e 's/"-- Section:/\n#/g' \ | |
| # -e 's/syn keyword gasOpcode_\([^\t]*\)*\(\t\)*\(.*\)/Opcode_\1="\${Opcode_\1} \3"/g' \ | |
| # -e 's/Opcode_PENT_3DNOW/Opcode_ATHLON_3DNOW/g' -e 's/\\//g' \ | |
| # -e 's/syn match gasOpcode_\([^\t]*\)*.*\/<\(.*\)>\//Opcode_\1="\${Opcode_\1} \2"/g' \ | |
| # >> Opcode_list | |
| # | |
| # Modify file Opcode_list replacing all occurrences of: | |
| # * Opcode_Base within the section "Tejas New Instructions (SSSE3)" with Opcode_SSSE3 | |
| # * Opcode_Base within the section "Willamette MMX instructions (SSE2 SIMD Integer Instructions)" with Opcode_WILLAMETTE_Base | |
| # return values | |
| EXIT_FOUND=0 | |
| EXIT_NOT_FOUND=1 | |
| EXIT_USAGE=2 | |
| # settings | |
| InstSet_Base="" | |
| Recursive=false | |
| Count_Matching=false | |
| Leading_Separator='\s' | |
| Trailing_Separator='(\s|$)' # $ matches end of line for non-parametric instructions like nop | |
| Case_Insensitive=false | |
| Invert=false | |
| Verbose=false | |
| Stop_After=0 | |
| Line_Numbers=false | |
| Leading_Context=0 | |
| Trailing_Context=0 | |
| Build_Stats=false | |
| # Willamette MMX instructions (SSE2 SIMD Integer Instructions) | |
| Opcode_SSE2="${Opcode_SSE2} movd movdb movdw movdl movdq" | |
| Opcode_SSE2="${Opcode_SSE2} movdqa" | |
| Opcode_SSE2="${Opcode_SSE2} movdqu" | |
| Opcode_SSE2="${Opcode_SSE2} movdq2q" | |
| Opcode_X64_SSE2="${Opcode_X64_SSE2} movq" | |
| Opcode_SSE2="${Opcode_SSE2} movq2dq" | |
| Opcode_SSE2="${Opcode_SSE2} packsswb packsswbb packsswbw packsswbl packsswbq" | |
| Opcode_SSE2="${Opcode_SSE2} packssdw packssdwb packssdww packssdwl packssdwq" | |
| Opcode_SSE2="${Opcode_SSE2} packuswb packuswbb packuswbw packuswbl packuswbq" | |
| Opcode_SSE2="${Opcode_SSE2} paddb paddbb paddbw paddbl paddbq" | |
| Opcode_SSE2="${Opcode_SSE2} paddw paddwb paddww paddwl paddwq" | |
| Opcode_SSE2="${Opcode_SSE2} paddd padddb padddw padddl padddq" | |
| Opcode_SSE2="${Opcode_SSE2} paddq paddqb paddqw paddql paddqq" | |
| Opcode_SSE2="${Opcode_SSE2} paddsb paddsbb paddsbw paddsbl paddsbq" | |
| Opcode_SSE2="${Opcode_SSE2} paddsw paddswb paddsww paddswl paddswq" | |
| Opcode_SSE2="${Opcode_SSE2} paddusb paddusbb paddusbw paddusbl paddusbq" | |
| Opcode_SSE2="${Opcode_SSE2} paddusw padduswb paddusww padduswl padduswq" | |
| Opcode_SSE2="${Opcode_SSE2} pand pandb pandw pandl pandq" | |
| Opcode_SSE2="${Opcode_SSE2} pandn pandnb pandnw pandnl pandnq" | |
| Opcode_SSE2="${Opcode_SSE2} pavgb pavgbb pavgbw pavgbl pavgbq" | |
| Opcode_SSE2="${Opcode_SSE2} pavgw pavgwb pavgww pavgwl pavgwq" | |
| Opcode_SSE2="${Opcode_SSE2} pcmpeqb pcmpeqbb pcmpeqbw pcmpeqbl pcmpeqbq" | |
| Opcode_SSE2="${Opcode_SSE2} pcmpeqw pcmpeqwb pcmpeqww pcmpeqwl pcmpeqwq" | |
| Opcode_SSE2="${Opcode_SSE2} pcmpeqd pcmpeqdb pcmpeqdw pcmpeqdl pcmpeqdq" | |
| Opcode_SSE2="${Opcode_SSE2} pcmpgtb pcmpgtbb pcmpgtbw pcmpgtbl pcmpgtbq" | |
| Opcode_SSE2="${Opcode_SSE2} pcmpgtw pcmpgtwb pcmpgtww pcmpgtwl pcmpgtwq" | |
| Opcode_SSE2="${Opcode_SSE2} pcmpgtd pcmpgtdb pcmpgtdw pcmpgtdl pcmpgtdq" | |
| Opcode_SSE2="${Opcode_SSE2} pextrw pextrwb pextrww pextrwl pextrwq" | |
| Opcode_SSE2="${Opcode_SSE2} pinsrw pinsrwb pinsrww pinsrwl pinsrwq" | |
| Opcode_SSE2="${Opcode_SSE2} pmaddwd pmaddwdb pmaddwdw pmaddwdl pmaddwdq" | |
| Opcode_SSE2="${Opcode_SSE2} pmaxsw pmaxswb pmaxsww pmaxswl pmaxswq" | |
| Opcode_SSE2="${Opcode_SSE2} pmaxub pmaxubb pmaxubw pmaxubl pmaxubq" | |
| Opcode_SSE2="${Opcode_SSE2} pminsw pminswb pminsww pminswl pminswq" | |
| Opcode_SSE2="${Opcode_SSE2} pminub pminubb pminubw pminubl pminubq" | |
| Opcode_SSE2="${Opcode_SSE2} pmovmskb" | |
| Opcode_SSE2="${Opcode_SSE2} pmulhuw pmulhuwb pmulhuww pmulhuwl pmulhuwq" | |
| Opcode_SSE2="${Opcode_SSE2} pmulhw pmulhwb pmulhww pmulhwl pmulhwq" | |
| Opcode_SSE2="${Opcode_SSE2} pmullw pmullwb pmullww pmullwl pmullwq" | |
| Opcode_SSE2="${Opcode_SSE2} pmuludq pmuludqb pmuludqw pmuludql pmuludqq" | |
| Opcode_SSE2="${Opcode_SSE2} por porb porw porl porq" | |
| Opcode_SSE2="${Opcode_SSE2} psadbw psadbwb psadbww psadbwl psadbwq" | |
| Opcode_WILLAMETTE_Base="${Opcode_WILLAMETTE_Base} pshufd pshufdb pshufdw pshufdl pshufdq" | |
| Opcode_WILLAMETTE_Base="${Opcode_WILLAMETTE_Base} pshufhw pshufhwb pshufhww pshufhwl pshufhwq" | |
| Opcode_WILLAMETTE_Base="${Opcode_WILLAMETTE_Base} pshuflw pshuflwb pshuflww pshuflwl pshuflwq" | |
| Opcode_SSE2="${Opcode_SSE2} pslldq pslldqb pslldqw pslldql pslldqq" | |
| Opcode_SSE2="${Opcode_SSE2} psllw psllwb psllww psllwl psllwq" | |
| Opcode_SSE2="${Opcode_SSE2} pslld pslldb pslldw pslldl pslldq" | |
| Opcode_SSE2="${Opcode_SSE2} psllq psllqb psllqw psllql psllqq" | |
| Opcode_SSE2="${Opcode_SSE2} psraw psrawb psraww psrawl psrawq" | |
| Opcode_SSE2="${Opcode_SSE2} psrad psradb psradw psradl psradq" | |
| Opcode_SSE2="${Opcode_SSE2} psrldq psrldqb psrldqw psrldql psrldqq" | |
| Opcode_SSE2="${Opcode_SSE2} psrlw psrlwb psrlww psrlwl psrlwq" | |
| Opcode_SSE2="${Opcode_SSE2} psrld psrldb psrldw psrldl psrldq" | |
| Opcode_SSE2="${Opcode_SSE2} psrlq psrlqb psrlqw psrlql psrlqq" | |
| Opcode_SSE2="${Opcode_SSE2} psubb psubbb psubbw psubbl psubbq" | |
| Opcode_SSE2="${Opcode_SSE2} psubw psubwb psubww psubwl psubwq" | |
| Opcode_SSE2="${Opcode_SSE2} psubd psubdb psubdw psubdl psubdq" | |
| Opcode_SSE2="${Opcode_SSE2} psubq psubqb psubqw psubql psubqq" | |
| Opcode_SSE2="${Opcode_SSE2} psubsb psubsbb psubsbw psubsbl psubsbq" | |
| Opcode_SSE2="${Opcode_SSE2} psubsw psubswb psubsww psubswl psubswq" | |
| Opcode_SSE2="${Opcode_SSE2} psubusb psubusbb psubusbw psubusbl psubusbq" | |
| Opcode_SSE2="${Opcode_SSE2} psubusw psubuswb psubusww psubuswl psubuswq" | |
| Opcode_SSE2="${Opcode_SSE2} punpckhbw punpckhbwb punpckhbww punpckhbwl punpckhbwq" | |
| Opcode_SSE2="${Opcode_SSE2} punpckhwd punpckhwdb punpckhwdw punpckhwdl punpckhwdq" | |
| Opcode_SSE2="${Opcode_SSE2} punpckhdq punpckhdqb punpckhdqw punpckhdql punpckhdqq" | |
| Opcode_SSE2="${Opcode_SSE2} punpckhqdq punpckhqdqb punpckhqdqw punpckhqdql punpckhqdqq" | |
| Opcode_SSE2="${Opcode_SSE2} punpcklbw punpcklbwb punpcklbww punpcklbwl punpcklbwq" | |
| Opcode_SSE2="${Opcode_SSE2} punpcklwd punpcklwdb punpcklwdw punpcklwdl punpcklwdq" | |
| Opcode_SSE2="${Opcode_SSE2} punpckldq punpckldqb punpckldqw punpckldql punpckldqq" | |
| Opcode_SSE2="${Opcode_SSE2} punpcklqdq punpcklqdqb punpcklqdqw punpcklqdql punpcklqdqq" | |
| Opcode_SSE2="${Opcode_SSE2} pxor pxorb pxorw pxorl pxorq" | |
| # Nehalem New Instructions (SSE4.2) | |
| Opcode_X64_SSE42="${Opcode_X64_SSE42} crc32" | |
| Opcode_SSE42="${Opcode_SSE42} pcmpestri pcmpestrib pcmpestriw pcmpestril pcmpestriq" | |
| Opcode_SSE42="${Opcode_SSE42} pcmpestrm pcmpestrmb pcmpestrmw pcmpestrml pcmpestrmq" | |
| Opcode_SSE42="${Opcode_SSE42} pcmpistri pcmpistrib pcmpistriw pcmpistril pcmpistriq" | |
| Opcode_SSE42="${Opcode_SSE42} pcmpistrm pcmpistrmb pcmpistrmw pcmpistrml pcmpistrmq" | |
| Opcode_SSE42="${Opcode_SSE42} pcmpgtq pcmpgtqb pcmpgtqw pcmpgtql pcmpgtqq" | |
| Opcode_NEHALEM_Base="${Opcode_NEHALEM_Base} popcnt" | |
| # Intel new instructions in ??? | |
| Opcode_NEHALEM_Base="${Opcode_NEHALEM_Base} movbe movbeb movbew movbel movbeq" | |
| # AMD XOP, FMA4 and CVT16 instructions (SSE5) | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vcvtph2ps vcvtph2psb vcvtph2psw vcvtph2psl vcvtph2psq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vcvtps2ph vcvtps2phb vcvtps2phw vcvtps2phl vcvtps2phq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmaddpd vfmaddpdb vfmaddpdw vfmaddpdl vfmaddpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmaddps vfmaddpsb vfmaddpsw vfmaddpsl vfmaddpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmaddsd vfmaddsdb vfmaddsdw vfmaddsdl vfmaddsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmaddss vfmaddssb vfmaddssw vfmaddssl vfmaddssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmaddsubpd vfmaddsubpdb vfmaddsubpdw vfmaddsubpdl vfmaddsubpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmaddsubps vfmaddsubpsb vfmaddsubpsw vfmaddsubpsl vfmaddsubpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmsubaddpd vfmsubaddpdb vfmsubaddpdw vfmsubaddpdl vfmsubaddpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmsubaddps vfmsubaddpsb vfmsubaddpsw vfmsubaddpsl vfmsubaddpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmsubpd vfmsubpdb vfmsubpdw vfmsubpdl vfmsubpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmsubps vfmsubpsb vfmsubpsw vfmsubpsl vfmsubpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmsubsd vfmsubsdb vfmsubsdw vfmsubsdl vfmsubsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfmsubss vfmsubssb vfmsubssw vfmsubssl vfmsubssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfnmaddpd vfnmaddpdb vfnmaddpdw vfnmaddpdl vfnmaddpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfnmaddps vfnmaddpsb vfnmaddpsw vfnmaddpsl vfnmaddpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfnmaddsd vfnmaddsdb vfnmaddsdw vfnmaddsdl vfnmaddsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfnmaddss vfnmaddssb vfnmaddssw vfnmaddssl vfnmaddssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfnmsubpd vfnmsubpdb vfnmsubpdw vfnmsubpdl vfnmsubpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfnmsubps vfnmsubpsb vfnmsubpsw vfnmsubpsl vfnmsubpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfnmsubsd vfnmsubsdb vfnmsubsdw vfnmsubsdl vfnmsubsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfnmsubss vfnmsubssb vfnmsubssw vfnmsubssl vfnmsubssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfrczpd vfrczpdb vfrczpdw vfrczpdl vfrczpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfrczps vfrczpsb vfrczpsw vfrczpsl vfrczpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfrczsd vfrczsdb vfrczsdw vfrczsdl vfrczsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vfrczss vfrczssb vfrczssw vfrczssl vfrczssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpcmov vpcmovb vpcmovw vpcmovl vpcmovq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpcomb vpcombb vpcombw vpcombl vpcombq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpcomd vpcomdb vpcomdw vpcomdl vpcomdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpcomq vpcomqb vpcomqw vpcomql vpcomqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpcomub vpcomubb vpcomubw vpcomubl vpcomubq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpcomud vpcomudb vpcomudw vpcomudl vpcomudq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpcomuq vpcomuqb vpcomuqw vpcomuql vpcomuqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpcomuw vpcomuwb vpcomuww vpcomuwl vpcomuwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpcomw vpcomwb vpcomww vpcomwl vpcomwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphaddbd vphaddbdb vphaddbdw vphaddbdl vphaddbdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphaddbq vphaddbqb vphaddbqw vphaddbql vphaddbqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphaddbw vphaddbwb vphaddbww vphaddbwl vphaddbwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphadddq vphadddqb vphadddqw vphadddql vphadddqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphaddubd vphaddubdb vphaddubdw vphaddubdl vphaddubdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphaddubq vphaddubqb vphaddubqw vphaddubql vphaddubqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphaddubwd vphaddubwdb vphaddubwdw vphaddubwdl vphaddubwdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphaddudq vphaddudqb vphaddudqw vphaddudql vphaddudqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphadduwd vphadduwdb vphadduwdw vphadduwdl vphadduwdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphadduwq vphadduwqb vphadduwqw vphadduwql vphadduwqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphaddwd vphaddwdb vphaddwdw vphaddwdl vphaddwdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphaddwq vphaddwqb vphaddwqw vphaddwql vphaddwqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphsubbw vphsubbwb vphsubbww vphsubbwl vphsubbwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphsubdq vphsubdqb vphsubdqw vphsubdql vphsubdqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vphsubwd vphsubwdb vphsubwdw vphsubwdl vphsubwdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacsdd vpmacsddb vpmacsddw vpmacsddl vpmacsddq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacsdqh vpmacsdqhb vpmacsdqhw vpmacsdqhl vpmacsdqhq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacsdql vpmacsdqlb vpmacsdqlw vpmacsdqll vpmacsdqlq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacssdd vpmacssddb vpmacssddw vpmacssddl vpmacssddq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacssdqh vpmacssdqhb vpmacssdqhw vpmacssdqhl vpmacssdqhq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacssdql vpmacssdqlb vpmacssdqlw vpmacssdqll vpmacssdqlq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacsswd vpmacsswdb vpmacsswdw vpmacsswdl vpmacsswdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacssww vpmacsswwb vpmacsswww vpmacsswwl vpmacsswwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacswd vpmacswdb vpmacswdw vpmacswdl vpmacswdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmacsww vpmacswwb vpmacswww vpmacswwl vpmacswwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmadcsswd vpmadcsswdb vpmadcsswdw vpmadcsswdl vpmadcsswdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpmadcswd vpmadcswdb vpmadcswdw vpmadcswdl vpmadcswdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpperm vppermb vppermw vpperml vppermq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vprotb vprotbb vprotbw vprotbl vprotbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vprotd vprotdb vprotdw vprotdl vprotdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vprotq vprotqb vprotqw vprotql vprotqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vprotw vprotwb vprotww vprotwl vprotwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpshab vpshabb vpshabw vpshabl vpshabq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpshad vpshadb vpshadw vpshadl vpshadq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpshaq vpshaqb vpshaqw vpshaql vpshaqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpshaw vpshawb vpshaww vpshawl vpshawq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpshlb vpshlbb vpshlbw vpshlbl vpshlbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpshld vpshldb vpshldw vpshldl vpshldq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpshlq vpshlqb vpshlqw vpshlql vpshlqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} vpshlw vpshlwb vpshlww vpshlwl vpshlwq" | |
| # Generic memory operations | |
| Opcode_KATMAI_Base="${Opcode_KATMAI_Base} prefetchnta prefetchntab prefetchntaw prefetchntal prefetchntaq" | |
| Opcode_KATMAI_Base="${Opcode_KATMAI_Base} prefetcht0 prefetcht0b prefetcht0w prefetcht0l prefetcht0q" | |
| Opcode_KATMAI_Base="${Opcode_KATMAI_Base} prefetcht1 prefetcht1b prefetcht1w prefetcht1l prefetcht1q" | |
| Opcode_KATMAI_Base="${Opcode_KATMAI_Base} prefetcht2 prefetcht2b prefetcht2w prefetcht2l prefetcht2q" | |
| Opcode_KATMAI_Base="${Opcode_KATMAI_Base} sfence" | |
| # Tejas New Instructions (SSSE3) | |
| Opcode_SSSE3="${Opcode_SSSE3} pabsb pabsbb pabsbw pabsbl pabsbq" | |
| Opcode_SSSE3="${Opcode_SSSE3} pabsw pabswb pabsww pabswl pabswq" | |
| Opcode_SSSE3="${Opcode_SSSE3} pabsd pabsdb pabsdw pabsdl pabsdq" | |
| Opcode_SSSE3="${Opcode_SSSE3} palignr palignrb palignrw palignrl palignrq" | |
| Opcode_SSSE3="${Opcode_SSSE3} phaddw phaddwb phaddww phaddwl phaddwq" | |
| Opcode_SSSE3="${Opcode_SSSE3} phaddd phadddb phadddw phadddl phadddq" | |
| Opcode_SSSE3="${Opcode_SSSE3} phaddsw phaddswb phaddsww phaddswl phaddswq" | |
| Opcode_SSSE3="${Opcode_SSSE3} phsubw phsubwb phsubww phsubwl phsubwq" | |
| Opcode_SSSE3="${Opcode_SSSE3} phsubd phsubdb phsubdw phsubdl phsubdq" | |
| Opcode_SSSE3="${Opcode_SSSE3} phsubsw phsubswb phsubsww phsubswl phsubswq" | |
| Opcode_SSSE3="${Opcode_SSSE3} pmaddubsw pmaddubswb pmaddubsww pmaddubswl pmaddubswq" | |
| Opcode_SSSE3="${Opcode_SSSE3} pmulhrsw pmulhrswb pmulhrsww pmulhrswl pmulhrswq" | |
| Opcode_SSSE3="${Opcode_SSSE3} pshufb pshufbb pshufbw pshufbl pshufbq" | |
| Opcode_SSSE3="${Opcode_SSSE3} psignb psignbb psignbw psignbl psignbq" | |
| Opcode_SSSE3="${Opcode_SSSE3} psignw psignwb psignww psignwl psignwq" | |
| Opcode_SSSE3="${Opcode_SSSE3} psignd psigndb psigndw psigndl psigndq" | |
| # Intel Fused Multiply-Add instructions (FMA) | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd132ps vfmadd132psb vfmadd132psw vfmadd132psl vfmadd132psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd132pd vfmadd132pdb vfmadd132pdw vfmadd132pdl vfmadd132pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd312ps vfmadd312psb vfmadd312psw vfmadd312psl vfmadd312psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd312pd vfmadd312pdb vfmadd312pdw vfmadd312pdl vfmadd312pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd213ps vfmadd213psb vfmadd213psw vfmadd213psl vfmadd213psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd213pd vfmadd213pdb vfmadd213pdw vfmadd213pdl vfmadd213pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd123ps vfmadd123psb vfmadd123psw vfmadd123psl vfmadd123psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd123pd vfmadd123pdb vfmadd123pdw vfmadd123pdl vfmadd123pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd231ps vfmadd231psb vfmadd231psw vfmadd231psl vfmadd231psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd231pd vfmadd231pdb vfmadd231pdw vfmadd231pdl vfmadd231pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd321ps vfmadd321psb vfmadd321psw vfmadd321psl vfmadd321psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd321pd vfmadd321pdb vfmadd321pdw vfmadd321pdl vfmadd321pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub132ps vfmaddsub132psb vfmaddsub132psw vfmaddsub132psl vfmaddsub132psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub132pd vfmaddsub132pdb vfmaddsub132pdw vfmaddsub132pdl vfmaddsub132pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub312ps vfmaddsub312psb vfmaddsub312psw vfmaddsub312psl vfmaddsub312psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub312pd vfmaddsub312pdb vfmaddsub312pdw vfmaddsub312pdl vfmaddsub312pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub213ps vfmaddsub213psb vfmaddsub213psw vfmaddsub213psl vfmaddsub213psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub213pd vfmaddsub213pdb vfmaddsub213pdw vfmaddsub213pdl vfmaddsub213pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub123ps vfmaddsub123psb vfmaddsub123psw vfmaddsub123psl vfmaddsub123psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub123pd vfmaddsub123pdb vfmaddsub123pdw vfmaddsub123pdl vfmaddsub123pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub231ps vfmaddsub231psb vfmaddsub231psw vfmaddsub231psl vfmaddsub231psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub231pd vfmaddsub231pdb vfmaddsub231pdw vfmaddsub231pdl vfmaddsub231pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub321ps vfmaddsub321psb vfmaddsub321psw vfmaddsub321psl vfmaddsub321psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmaddsub321pd vfmaddsub321pdb vfmaddsub321pdw vfmaddsub321pdl vfmaddsub321pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub132ps vfmsub132psb vfmsub132psw vfmsub132psl vfmsub132psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub132pd vfmsub132pdb vfmsub132pdw vfmsub132pdl vfmsub132pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub312ps vfmsub312psb vfmsub312psw vfmsub312psl vfmsub312psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub312pd vfmsub312pdb vfmsub312pdw vfmsub312pdl vfmsub312pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub213ps vfmsub213psb vfmsub213psw vfmsub213psl vfmsub213psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub213pd vfmsub213pdb vfmsub213pdw vfmsub213pdl vfmsub213pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub123ps vfmsub123psb vfmsub123psw vfmsub123psl vfmsub123psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub123pd vfmsub123pdb vfmsub123pdw vfmsub123pdl vfmsub123pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub231ps vfmsub231psb vfmsub231psw vfmsub231psl vfmsub231psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub231pd vfmsub231pdb vfmsub231pdw vfmsub231pdl vfmsub231pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub321ps vfmsub321psb vfmsub321psw vfmsub321psl vfmsub321psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub321pd vfmsub321pdb vfmsub321pdw vfmsub321pdl vfmsub321pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd132ps vfmsubadd132psb vfmsubadd132psw vfmsubadd132psl vfmsubadd132psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd132pd vfmsubadd132pdb vfmsubadd132pdw vfmsubadd132pdl vfmsubadd132pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd312ps vfmsubadd312psb vfmsubadd312psw vfmsubadd312psl vfmsubadd312psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd312pd vfmsubadd312pdb vfmsubadd312pdw vfmsubadd312pdl vfmsubadd312pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd213ps vfmsubadd213psb vfmsubadd213psw vfmsubadd213psl vfmsubadd213psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd213pd vfmsubadd213pdb vfmsubadd213pdw vfmsubadd213pdl vfmsubadd213pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd123ps vfmsubadd123psb vfmsubadd123psw vfmsubadd123psl vfmsubadd123psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd123pd vfmsubadd123pdb vfmsubadd123pdw vfmsubadd123pdl vfmsubadd123pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd231ps vfmsubadd231psb vfmsubadd231psw vfmsubadd231psl vfmsubadd231psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd231pd vfmsubadd231pdb vfmsubadd231pdw vfmsubadd231pdl vfmsubadd231pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd321ps vfmsubadd321psb vfmsubadd321psw vfmsubadd321psl vfmsubadd321psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsubadd321pd vfmsubadd321pdb vfmsubadd321pdw vfmsubadd321pdl vfmsubadd321pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd132ps vfnmadd132psb vfnmadd132psw vfnmadd132psl vfnmadd132psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd132pd vfnmadd132pdb vfnmadd132pdw vfnmadd132pdl vfnmadd132pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd312ps vfnmadd312psb vfnmadd312psw vfnmadd312psl vfnmadd312psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd312pd vfnmadd312pdb vfnmadd312pdw vfnmadd312pdl vfnmadd312pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd213ps vfnmadd213psb vfnmadd213psw vfnmadd213psl vfnmadd213psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd213pd vfnmadd213pdb vfnmadd213pdw vfnmadd213pdl vfnmadd213pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd123ps vfnmadd123psb vfnmadd123psw vfnmadd123psl vfnmadd123psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd123pd vfnmadd123pdb vfnmadd123pdw vfnmadd123pdl vfnmadd123pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd231ps vfnmadd231psb vfnmadd231psw vfnmadd231psl vfnmadd231psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd231pd vfnmadd231pdb vfnmadd231pdw vfnmadd231pdl vfnmadd231pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd321ps vfnmadd321psb vfnmadd321psw vfnmadd321psl vfnmadd321psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd321pd vfnmadd321pdb vfnmadd321pdw vfnmadd321pdl vfnmadd321pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub132ps vfnmsub132psb vfnmsub132psw vfnmsub132psl vfnmsub132psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub132pd vfnmsub132pdb vfnmsub132pdw vfnmsub132pdl vfnmsub132pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub312ps vfnmsub312psb vfnmsub312psw vfnmsub312psl vfnmsub312psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub312pd vfnmsub312pdb vfnmsub312pdw vfnmsub312pdl vfnmsub312pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub213ps vfnmsub213psb vfnmsub213psw vfnmsub213psl vfnmsub213psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub213pd vfnmsub213pdb vfnmsub213pdw vfnmsub213pdl vfnmsub213pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub123ps vfnmsub123psb vfnmsub123psw vfnmsub123psl vfnmsub123psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub123pd vfnmsub123pdb vfnmsub123pdw vfnmsub123pdl vfnmsub123pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub231ps vfnmsub231psb vfnmsub231psw vfnmsub231psl vfnmsub231psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub231pd vfnmsub231pdb vfnmsub231pdw vfnmsub231pdl vfnmsub231pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub321ps vfnmsub321psb vfnmsub321psw vfnmsub321psl vfnmsub321psq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub321pd vfnmsub321pdb vfnmsub321pdw vfnmsub321pdl vfnmsub321pdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd132ss vfmadd132ssb vfmadd132ssw vfmadd132ssl vfmadd132ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd132sd vfmadd132sdb vfmadd132sdw vfmadd132sdl vfmadd132sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd312ss vfmadd312ssb vfmadd312ssw vfmadd312ssl vfmadd312ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd312sd vfmadd312sdb vfmadd312sdw vfmadd312sdl vfmadd312sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd213ss vfmadd213ssb vfmadd213ssw vfmadd213ssl vfmadd213ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd213sd vfmadd213sdb vfmadd213sdw vfmadd213sdl vfmadd213sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd123ss vfmadd123ssb vfmadd123ssw vfmadd123ssl vfmadd123ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd123sd vfmadd123sdb vfmadd123sdw vfmadd123sdl vfmadd123sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd231ss vfmadd231ssb vfmadd231ssw vfmadd231ssl vfmadd231ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd231sd vfmadd231sdb vfmadd231sdw vfmadd231sdl vfmadd231sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd321ss vfmadd321ssb vfmadd321ssw vfmadd321ssl vfmadd321ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmadd321sd vfmadd321sdb vfmadd321sdw vfmadd321sdl vfmadd321sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub132ss vfmsub132ssb vfmsub132ssw vfmsub132ssl vfmsub132ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub132sd vfmsub132sdb vfmsub132sdw vfmsub132sdl vfmsub132sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub312ss vfmsub312ssb vfmsub312ssw vfmsub312ssl vfmsub312ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub312sd vfmsub312sdb vfmsub312sdw vfmsub312sdl vfmsub312sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub213ss vfmsub213ssb vfmsub213ssw vfmsub213ssl vfmsub213ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub213sd vfmsub213sdb vfmsub213sdw vfmsub213sdl vfmsub213sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub123ss vfmsub123ssb vfmsub123ssw vfmsub123ssl vfmsub123ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub123sd vfmsub123sdb vfmsub123sdw vfmsub123sdl vfmsub123sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub231ss vfmsub231ssb vfmsub231ssw vfmsub231ssl vfmsub231ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub231sd vfmsub231sdb vfmsub231sdw vfmsub231sdl vfmsub231sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub321ss vfmsub321ssb vfmsub321ssw vfmsub321ssl vfmsub321ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfmsub321sd vfmsub321sdb vfmsub321sdw vfmsub321sdl vfmsub321sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd132ss vfnmadd132ssb vfnmadd132ssw vfnmadd132ssl vfnmadd132ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd132sd vfnmadd132sdb vfnmadd132sdw vfnmadd132sdl vfnmadd132sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd312ss vfnmadd312ssb vfnmadd312ssw vfnmadd312ssl vfnmadd312ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd312sd vfnmadd312sdb vfnmadd312sdw vfnmadd312sdl vfnmadd312sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd213ss vfnmadd213ssb vfnmadd213ssw vfnmadd213ssl vfnmadd213ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd213sd vfnmadd213sdb vfnmadd213sdw vfnmadd213sdl vfnmadd213sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd123ss vfnmadd123ssb vfnmadd123ssw vfnmadd123ssl vfnmadd123ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd123sd vfnmadd123sdb vfnmadd123sdw vfnmadd123sdl vfnmadd123sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd231ss vfnmadd231ssb vfnmadd231ssw vfnmadd231ssl vfnmadd231ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd231sd vfnmadd231sdb vfnmadd231sdw vfnmadd231sdl vfnmadd231sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd321ss vfnmadd321ssb vfnmadd321ssw vfnmadd321ssl vfnmadd321ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmadd321sd vfnmadd321sdb vfnmadd321sdw vfnmadd321sdl vfnmadd321sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub132ss vfnmsub132ssb vfnmsub132ssw vfnmsub132ssl vfnmsub132ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub132sd vfnmsub132sdb vfnmsub132sdw vfnmsub132sdl vfnmsub132sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub312ss vfnmsub312ssb vfnmsub312ssw vfnmsub312ssl vfnmsub312ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub312sd vfnmsub312sdb vfnmsub312sdw vfnmsub312sdl vfnmsub312sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub213ss vfnmsub213ssb vfnmsub213ssw vfnmsub213ssl vfnmsub213ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub213sd vfnmsub213sdb vfnmsub213sdw vfnmsub213sdl vfnmsub213sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub123ss vfnmsub123ssb vfnmsub123ssw vfnmsub123ssl vfnmsub123ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub123sd vfnmsub123sdb vfnmsub123sdw vfnmsub123sdl vfnmsub123sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub231ss vfnmsub231ssb vfnmsub231ssw vfnmsub231ssl vfnmsub231ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub231sd vfnmsub231sdb vfnmsub231sdw vfnmsub231sdl vfnmsub231sdq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub321ss vfnmsub321ssb vfnmsub321ssw vfnmsub321ssl vfnmsub321ssq" | |
| Opcode_FUTURE_FMA="${Opcode_FUTURE_FMA} vfnmsub321sd vfnmsub321sdb vfnmsub321sdw vfnmsub321sdl vfnmsub321sdq" | |
| # Willamette SSE2 Cacheability Instructions | |
| Opcode_SSE2="${Opcode_SSE2} maskmovdqu" | |
| Opcode_SSE2="${Opcode_SSE2} clflush clflushb clflushw clflushl clflushq" | |
| Opcode_SSE2="${Opcode_SSE2} movntdq movntdqb movntdqw movntdql movntdqq" | |
| Opcode_X64_Base="${Opcode_X64_Base} movnti movntib movntiw movntil movntiq" | |
| Opcode_SSE2="${Opcode_SSE2} movntpd movntpdb movntpdw movntpdl movntpdq" | |
| Opcode_SSE2="${Opcode_SSE2} lfence" | |
| Opcode_SSE2="${Opcode_SSE2} mfence" | |
| # Systematic names for the hinting nop instructions | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop0" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop1" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop2" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop3" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop4" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop5" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop6" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop7" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop8" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop9" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop10" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop11" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop12" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop13" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop14" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop15" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop16" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop17" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop18" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop19" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop20" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop21" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop22" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop23" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop24" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop25" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop26" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop27" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop28" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop29" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop30" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop31" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop32" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop33" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop34" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop35" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop36" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop37" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop38" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop39" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop40" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop41" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop42" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop43" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop44" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop45" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop46" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop47" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop48" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop49" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop50" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop51" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop52" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop53" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop54" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop55" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop56" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop57" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop58" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop59" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop60" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop61" | |
| Opcode_X64_Base="${Opcode_X64_Base} hint_nop62" | |
| # Geode (Cyrix) 3DNow! additions | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfrcpv pfrcpvb pfrcpvw pfrcpvl pfrcpvq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfrsqrtv pfrsqrtvb pfrsqrtvw pfrsqrtvl pfrsqrtvq" | |
| # XSAVE group (AVX and extended state) | |
| Opcode_NEHALEM_Base="${Opcode_NEHALEM_Base} xgetbv" | |
| Opcode_NEHALEM_Base="${Opcode_NEHALEM_Base} xsetbv" | |
| Opcode_NEHALEM_Base="${Opcode_NEHALEM_Base} xsave xsaveb xsavew xsavel xsaveq" | |
| Opcode_NEHALEM_Base="${Opcode_NEHALEM_Base} xrstor xrstorb xrstorw xrstorl xrstorq" | |
| # Conventional instructions | |
| Opcode_8086_Base="${Opcode_8086_Base} aaa" | |
| Opcode_8086_Base="${Opcode_8086_Base} aad aadb aadw aadl aadq" | |
| Opcode_8086_Base="${Opcode_8086_Base} aam aamb aamw aaml aamq" | |
| Opcode_8086_Base="${Opcode_8086_Base} aas" | |
| Opcode_386_Base="${Opcode_386_Base} adc adcb adcw adcl adcq" | |
| Opcode_386_Base="${Opcode_386_Base} add addb addw addl addq" | |
| Opcode_386_Base="${Opcode_386_Base} and andb andw andl andq" | |
| Opcode_286_Base="${Opcode_286_Base} arpl" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} bb0_reset" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} bb1_reset" | |
| Opcode_386_Base="${Opcode_386_Base} bound boundb boundw boundl boundq" | |
| Opcode_X64_Base="${Opcode_X64_Base} bsf" | |
| Opcode_X64_Base="${Opcode_X64_Base} bsr" | |
| Opcode_X64_Base="${Opcode_X64_Base} bswap" | |
| Opcode_X64_Base="${Opcode_X64_Base} bt btb btw btl btq" | |
| Opcode_X64_Base="${Opcode_X64_Base} btc btcb btcw btcl btcq" | |
| Opcode_X64_Base="${Opcode_X64_Base} btr btrb btrw btrl btrq" | |
| Opcode_X64_Base="${Opcode_X64_Base} bts btsb btsw btsl btsq" | |
| Opcode_X64_Base="${Opcode_X64_Base} call callb callw calll callq" | |
| Opcode_8086_Base="${Opcode_8086_Base} cbw" | |
| Opcode_386_Base="${Opcode_386_Base} cdq" | |
| Opcode_X64_Base="${Opcode_X64_Base} cdqe" | |
| Opcode_8086_Base="${Opcode_8086_Base} clc" | |
| Opcode_8086_Base="${Opcode_8086_Base} cld" | |
| Opcode_X64_Base="${Opcode_X64_Base} clgi" | |
| Opcode_8086_Base="${Opcode_8086_Base} cli" | |
| Opcode_286_Base="${Opcode_286_Base} clts" | |
| Opcode_8086_Base="${Opcode_8086_Base} cmc" | |
| Opcode_386_Base="${Opcode_386_Base} cmp cmpb cmpw cmpl cmpq" | |
| Opcode_8086_Base="${Opcode_8086_Base} cmpsb" | |
| Opcode_386_Base="${Opcode_386_Base} cmpsd" | |
| Opcode_X64_Base="${Opcode_X64_Base} cmpsq" | |
| Opcode_8086_Base="${Opcode_8086_Base} cmpsw" | |
| Opcode_X64_Base="${Opcode_X64_Base} cmpxchg" | |
| Opcode_486_Base="${Opcode_486_Base} cmpxchg486" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} cmpxchg8b cmpxchg8bb cmpxchg8bw cmpxchg8bl cmpxchg8bq" | |
| Opcode_X64_Base="${Opcode_X64_Base} cmpxchg16b cmpxchg16bb cmpxchg16bw cmpxchg16bl cmpxchg16bq" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} cpuid" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} cpu_read" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} cpu_write" | |
| Opcode_X64_Base="${Opcode_X64_Base} cqo" | |
| Opcode_8086_Base="${Opcode_8086_Base} cwd" | |
| Opcode_386_Base="${Opcode_386_Base} cwde" | |
| Opcode_8086_Base="${Opcode_8086_Base} daa" | |
| Opcode_8086_Base="${Opcode_8086_Base} das" | |
| Opcode_X64_Base="${Opcode_X64_Base} dec" | |
| Opcode_X64_Base="${Opcode_X64_Base} div" | |
| Opcode_P6_Base="${Opcode_P6_Base} dmint" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} emms" | |
| Opcode_186_Base="${Opcode_186_Base} enter enterb enterw enterl enterq" | |
| Opcode_8086_Base="${Opcode_8086_Base} equ" | |
| Opcode_8086_Base="${Opcode_8086_Base} f2xm1" | |
| Opcode_8086_Base="${Opcode_8086_Base} fabs" | |
| Opcode_8086_Base="${Opcode_8086_Base} fadd" | |
| Opcode_8086_Base="${Opcode_8086_Base} faddp" | |
| Opcode_8086_Base="${Opcode_8086_Base} fbld fbldb fbldw fbldl fbldq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fbstp fbstpb fbstpw fbstpl fbstpq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fchs" | |
| Opcode_8086_Base="${Opcode_8086_Base} fclex" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcmovb" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcmovbe" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcmove" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcmovnb" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcmovnbe" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcmovne" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcmovnu" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcmovu" | |
| Opcode_8086_Base="${Opcode_8086_Base} fcom" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcomi" | |
| Opcode_P6_Base="${Opcode_P6_Base} fcomip" | |
| Opcode_8086_Base="${Opcode_8086_Base} fcomp" | |
| Opcode_8086_Base="${Opcode_8086_Base} fcompp" | |
| Opcode_386_Base="${Opcode_386_Base} fcos" | |
| Opcode_8086_Base="${Opcode_8086_Base} fdecstp" | |
| Opcode_8086_Base="${Opcode_8086_Base} fdisi" | |
| Opcode_8086_Base="${Opcode_8086_Base} fdiv" | |
| Opcode_8086_Base="${Opcode_8086_Base} fdivp" | |
| Opcode_8086_Base="${Opcode_8086_Base} fdivr" | |
| Opcode_8086_Base="${Opcode_8086_Base} fdivrp" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} femms" | |
| Opcode_8086_Base="${Opcode_8086_Base} feni" | |
| Opcode_8086_Base="${Opcode_8086_Base} ffree" | |
| Opcode_286_Base="${Opcode_286_Base} ffreep" | |
| Opcode_8086_Base="${Opcode_8086_Base} fiadd fiaddb fiaddw fiaddl fiaddq" | |
| Opcode_8086_Base="${Opcode_8086_Base} ficom ficomb ficomw ficoml ficomq" | |
| Opcode_8086_Base="${Opcode_8086_Base} ficomp ficompb ficompw ficompl ficompq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fidiv fidivb fidivw fidivl fidivq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fidivr fidivrb fidivrw fidivrl fidivrq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fild fildb fildw fildl fildq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fimul fimulb fimulw fimull fimulq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fincstp" | |
| Opcode_8086_Base="${Opcode_8086_Base} finit" | |
| Opcode_8086_Base="${Opcode_8086_Base} fist fistb fistw fistl fistq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fistp fistpb fistpw fistpl fistpq" | |
| Opcode_PRESCOTT_Base="${Opcode_PRESCOTT_Base} fisttp fisttpb fisttpw fisttpl fisttpq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fisub fisubb fisubw fisubl fisubq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fisubr fisubrb fisubrw fisubrl fisubrq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fld" | |
| Opcode_8086_Base="${Opcode_8086_Base} fld1" | |
| Opcode_8086_Base="${Opcode_8086_Base} fldcw fldcwb fldcww fldcwl fldcwq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fldenv fldenvb fldenvw fldenvl fldenvq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fldl2e" | |
| Opcode_8086_Base="${Opcode_8086_Base} fldl2t" | |
| Opcode_8086_Base="${Opcode_8086_Base} fldlg2" | |
| Opcode_8086_Base="${Opcode_8086_Base} fldln2" | |
| Opcode_8086_Base="${Opcode_8086_Base} fldpi" | |
| Opcode_8086_Base="${Opcode_8086_Base} fldz" | |
| Opcode_8086_Base="${Opcode_8086_Base} fmul" | |
| Opcode_8086_Base="${Opcode_8086_Base} fmulp" | |
| Opcode_8086_Base="${Opcode_8086_Base} fnclex" | |
| Opcode_8086_Base="${Opcode_8086_Base} fndisi" | |
| Opcode_8086_Base="${Opcode_8086_Base} fneni" | |
| Opcode_8086_Base="${Opcode_8086_Base} fninit" | |
| Opcode_8086_Base="${Opcode_8086_Base} fnop" | |
| Opcode_8086_Base="${Opcode_8086_Base} fnsave fnsaveb fnsavew fnsavel fnsaveq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fnstcw fnstcwb fnstcww fnstcwl fnstcwq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fnstenv fnstenvb fnstenvw fnstenvl fnstenvq" | |
| Opcode_286_Base="${Opcode_286_Base} fnstsw" | |
| Opcode_8086_Base="${Opcode_8086_Base} fpatan" | |
| Opcode_8086_Base="${Opcode_8086_Base} fprem" | |
| Opcode_386_Base="${Opcode_386_Base} fprem1" | |
| Opcode_8086_Base="${Opcode_8086_Base} fptan" | |
| Opcode_8086_Base="${Opcode_8086_Base} frndint" | |
| Opcode_8086_Base="${Opcode_8086_Base} frstor frstorb frstorw frstorl frstorq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fsave fsaveb fsavew fsavel fsaveq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fscale" | |
| Opcode_286_Base="${Opcode_286_Base} fsetpm" | |
| Opcode_386_Base="${Opcode_386_Base} fsin" | |
| Opcode_386_Base="${Opcode_386_Base} fsincos" | |
| Opcode_8086_Base="${Opcode_8086_Base} fsqrt" | |
| Opcode_8086_Base="${Opcode_8086_Base} fst" | |
| Opcode_8086_Base="${Opcode_8086_Base} fstcw fstcwb fstcww fstcwl fstcwq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fstenv fstenvb fstenvw fstenvl fstenvq" | |
| Opcode_8086_Base="${Opcode_8086_Base} fstp" | |
| Opcode_286_Base="${Opcode_286_Base} fstsw" | |
| Opcode_8086_Base="${Opcode_8086_Base} fsub" | |
| Opcode_8086_Base="${Opcode_8086_Base} fsubp" | |
| Opcode_8086_Base="${Opcode_8086_Base} fsubr" | |
| Opcode_8086_Base="${Opcode_8086_Base} fsubrp" | |
| Opcode_8086_Base="${Opcode_8086_Base} ftst" | |
| Opcode_386_Base="${Opcode_386_Base} fucom" | |
| Opcode_P6_Base="${Opcode_P6_Base} fucomi" | |
| Opcode_P6_Base="${Opcode_P6_Base} fucomip" | |
| Opcode_386_Base="${Opcode_386_Base} fucomp" | |
| Opcode_386_Base="${Opcode_386_Base} fucompp" | |
| Opcode_8086_Base="${Opcode_8086_Base} fxam" | |
| Opcode_8086_Base="${Opcode_8086_Base} fxch" | |
| Opcode_8086_Base="${Opcode_8086_Base} fxtract" | |
| Opcode_8086_Base="${Opcode_8086_Base} fyl2x" | |
| Opcode_8086_Base="${Opcode_8086_Base} fyl2xp1" | |
| Opcode_8086_Base="${Opcode_8086_Base} hlt" | |
| Opcode_386_Base="${Opcode_386_Base} ibts" | |
| Opcode_386_Base="${Opcode_386_Base} icebp" | |
| Opcode_X64_Base="${Opcode_X64_Base} idiv" | |
| Opcode_X64_Base="${Opcode_X64_Base} imul imulb imulw imull imulq" | |
| Opcode_386_Base="${Opcode_386_Base} in" | |
| Opcode_X64_Base="${Opcode_X64_Base} inc incb incw incl incq" | |
| Opcode_Base="${Opcode_Base} incbin" | |
| Opcode_186_Base="${Opcode_186_Base} insb" | |
| Opcode_386_Base="${Opcode_386_Base} insd" | |
| Opcode_186_Base="${Opcode_186_Base} insw" | |
| Opcode_8086_Base="${Opcode_8086_Base} int intb intw intl intq" | |
| Opcode_386_Base="${Opcode_386_Base} int01" | |
| Opcode_386_Base="${Opcode_386_Base} int1" | |
| Opcode_8086_Base="${Opcode_8086_Base} int03" | |
| Opcode_8086_Base="${Opcode_8086_Base} int3" | |
| Opcode_8086_Base="${Opcode_8086_Base} into" | |
| Opcode_486_Base="${Opcode_486_Base} invd" | |
| Opcode_486_Base="${Opcode_486_Base} invlpg invlpgb invlpgw invlpgl invlpgq" | |
| Opcode_X86_64_Base="${Opcode_X86_64_Base} invlpga" | |
| Opcode_8086_Base="${Opcode_8086_Base} iret" | |
| Opcode_386_Base="${Opcode_386_Base} iretd" | |
| Opcode_X64_Base="${Opcode_X64_Base} iretq" | |
| Opcode_8086_Base="${Opcode_8086_Base} iretw" | |
| Opcode_8086_Base="${Opcode_8086_Base} jcxz jcxzb jcxzw jcxzl jcxzq" | |
| Opcode_386_Base="${Opcode_386_Base} jecxz jecxzb jecxzw jecxzl jecxzq" | |
| Opcode_X64_Base="${Opcode_X64_Base} jrcxz jrcxzb jrcxzw jrcxzl jrcxzq" | |
| Opcode_X64_Base="${Opcode_X64_Base} jmp jmpb jmpw jmpl jmpq" | |
| Opcode_IA64_Base="${Opcode_IA64_Base} jmpe" | |
| Opcode_8086_Base="${Opcode_8086_Base} lahf" | |
| Opcode_X64_Base="${Opcode_X64_Base} lar" | |
| Opcode_386_Base="${Opcode_386_Base} lds ldsb ldsw ldsl ldsq" | |
| Opcode_X64_Base="${Opcode_X64_Base} lea leab leaw leal leaq" | |
| Opcode_186_Base="${Opcode_186_Base} leave" | |
| Opcode_386_Base="${Opcode_386_Base} les lesb lesw lesl lesq" | |
| Opcode_X64_Base="${Opcode_X64_Base} lfence" | |
| Opcode_386_Base="${Opcode_386_Base} lfs lfsb lfsw lfsl lfsq" | |
| Opcode_286_Base="${Opcode_286_Base} lgdt lgdtb lgdtw lgdtl lgdtq" | |
| Opcode_386_Base="${Opcode_386_Base} lgs lgsb lgsw lgsl lgsq" | |
| Opcode_286_Base="${Opcode_286_Base} lidt lidtb lidtw lidtl lidtq" | |
| Opcode_286_Base="${Opcode_286_Base} lldt" | |
| Opcode_286_Base="${Opcode_286_Base} lmsw" | |
| Opcode_386_Base="${Opcode_386_Base} loadall" | |
| Opcode_286_Base="${Opcode_286_Base} loadall286" | |
| Opcode_8086_Base="${Opcode_8086_Base} lodsb" | |
| Opcode_386_Base="${Opcode_386_Base} lodsd" | |
| Opcode_X64_Base="${Opcode_X64_Base} lodsq" | |
| Opcode_8086_Base="${Opcode_8086_Base} lodsw" | |
| Opcode_X64_Base="${Opcode_X64_Base} loop loopb loopw loopl loopq" | |
| Opcode_X64_Base="${Opcode_X64_Base} loope loopeb loopew loopel loopeq" | |
| Opcode_X64_Base="${Opcode_X64_Base} loopne loopneb loopnew loopnel loopneq" | |
| Opcode_X64_Base="${Opcode_X64_Base} loopnz loopnzb loopnzw loopnzl loopnzq" | |
| Opcode_X64_Base="${Opcode_X64_Base} loopz loopzb loopzw loopzl loopzq" | |
| Opcode_X64_Base="${Opcode_X64_Base} lsl" | |
| Opcode_386_Base="${Opcode_386_Base} lss lssb lssw lssl lssq" | |
| Opcode_286_Base="${Opcode_286_Base} ltr" | |
| Opcode_X64_Base="${Opcode_X64_Base} mfence" | |
| Opcode_PRESCOTT_Base="${Opcode_PRESCOTT_Base} monitor" | |
| Opcode_386_Base="${Opcode_386_Base} mov movb movw movl movq" | |
| Opcode_X64_SSE="${Opcode_X64_SSE} movd" | |
| Opcode_X64_MMX="${Opcode_X64_MMX} movq" | |
| Opcode_8086_Base="${Opcode_8086_Base} movsb" | |
| Opcode_386_Base="${Opcode_386_Base} movsd" | |
| Opcode_X64_Base="${Opcode_X64_Base} movsq" | |
| Opcode_8086_Base="${Opcode_8086_Base} movsw" | |
| Opcode_X64_Base="${Opcode_X64_Base} movsx" | |
| Opcode_X64_Base="${Opcode_X64_Base} movsxd" | |
| Opcode_X64_Base="${Opcode_X64_Base} movsx" | |
| Opcode_X64_Base="${Opcode_X64_Base} movzx" | |
| Opcode_X64_Base="${Opcode_X64_Base} mul" | |
| Opcode_PRESCOTT_Base="${Opcode_PRESCOTT_Base} mwait" | |
| Opcode_X64_Base="${Opcode_X64_Base} neg" | |
| Opcode_X64_Base="${Opcode_X64_Base} nop" | |
| Opcode_X64_Base="${Opcode_X64_Base} not" | |
| Opcode_386_Base="${Opcode_386_Base} or orb orw orl orq" | |
| Opcode_386_Base="${Opcode_386_Base} out" | |
| Opcode_186_Base="${Opcode_186_Base} outsb" | |
| Opcode_386_Base="${Opcode_386_Base} outsd" | |
| Opcode_186_Base="${Opcode_186_Base} outsw" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} packssdw packssdwb packssdww packssdwl packssdwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} packsswb packsswbb packsswbw packsswbl packsswbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} packuswb packuswbb packuswbw packuswbl packuswbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} paddb paddbb paddbw paddbl paddbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} paddd padddb padddw padddl padddq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} paddsb paddsbb paddsbw paddsbl paddsbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} paddsiw paddsiwb paddsiww paddsiwl paddsiwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} paddsw paddswb paddsww paddswl paddswq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} paddusb paddusbb paddusbw paddusbl paddusbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} paddusw padduswb paddusww padduswl padduswq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} paddw paddwb paddww paddwl paddwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pand pandb pandw pandl pandq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pandn pandnb pandnw pandnl pandnq" | |
| Opcode_8086_Base="${Opcode_8086_Base} pause" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} paveb pavebb pavebw pavebl pavebq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pavgusb pavgusbb pavgusbw pavgusbl pavgusbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pcmpeqb pcmpeqbb pcmpeqbw pcmpeqbl pcmpeqbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pcmpeqd pcmpeqdb pcmpeqdw pcmpeqdl pcmpeqdq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pcmpeqw pcmpeqwb pcmpeqww pcmpeqwl pcmpeqwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pcmpgtb pcmpgtbb pcmpgtbw pcmpgtbl pcmpgtbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pcmpgtd pcmpgtdb pcmpgtdw pcmpgtdl pcmpgtdq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pcmpgtw pcmpgtwb pcmpgtww pcmpgtwl pcmpgtwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pdistib pdistibb pdistibw pdistibl pdistibq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pf2id pf2idb pf2idw pf2idl pf2idq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfacc pfaccb pfaccw pfaccl pfaccq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfadd pfaddb pfaddw pfaddl pfaddq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfcmpeq pfcmpeqb pfcmpeqw pfcmpeql pfcmpeqq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfcmpge pfcmpgeb pfcmpgew pfcmpgel pfcmpgeq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfcmpgt pfcmpgtb pfcmpgtw pfcmpgtl pfcmpgtq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfmax pfmaxb pfmaxw pfmaxl pfmaxq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfmin pfminb pfminw pfminl pfminq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfmul pfmulb pfmulw pfmull pfmulq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfrcp pfrcpb pfrcpw pfrcpl pfrcpq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfrcpit1 pfrcpit1b pfrcpit1w pfrcpit1l pfrcpit1q" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfrcpit2 pfrcpit2b pfrcpit2w pfrcpit2l pfrcpit2q" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfrsqit1 pfrsqit1b pfrsqit1w pfrsqit1l pfrsqit1q" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfrsqrt pfrsqrtb pfrsqrtw pfrsqrtl pfrsqrtq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfsub pfsubb pfsubw pfsubl pfsubq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfsubr pfsubrb pfsubrw pfsubrl pfsubrq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pi2fd pi2fdb pi2fdw pi2fdl pi2fdq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmachriw pmachriwb pmachriww pmachriwl pmachriwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmaddwd pmaddwdb pmaddwdw pmaddwdl pmaddwdq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmagw pmagwb pmagww pmagwl pmagwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmulhriw pmulhriwb pmulhriww pmulhriwl pmulhriwq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pmulhrwa pmulhrwab pmulhrwaw pmulhrwal pmulhrwaq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmulhrwc pmulhrwcb pmulhrwcw pmulhrwcl pmulhrwcq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmulhw pmulhwb pmulhww pmulhwl pmulhwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmullw pmullwb pmullww pmullwl pmullwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmvgezb pmvgezbb pmvgezbw pmvgezbl pmvgezbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmvlzb pmvlzbb pmvlzbw pmvlzbl pmvlzbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmvnzb pmvnzbb pmvnzbw pmvnzbl pmvnzbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pmvzb pmvzbb pmvzbw pmvzbl pmvzbq" | |
| Opcode_386_Base="${Opcode_386_Base} pop popb popw popl popq" | |
| Opcode_186_Base="${Opcode_186_Base} popa" | |
| Opcode_386_Base="${Opcode_386_Base} popad" | |
| Opcode_186_Base="${Opcode_186_Base} popaw" | |
| Opcode_8086_Base="${Opcode_8086_Base} popf" | |
| Opcode_386_Base="${Opcode_386_Base} popfd popfl" | |
| Opcode_X64_Base="${Opcode_X64_Base} popfq" | |
| Opcode_8086_Base="${Opcode_8086_Base} popfw" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} por porb porw porl porq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} prefetch prefetchb prefetchw prefetchl prefetchq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} prefetchw prefetchwb prefetchww prefetchwl prefetchwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pslld pslldb pslldw pslldl pslldq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psllq psllqb psllqw psllql psllqq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psllw psllwb psllww psllwl psllwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psrad psradb psradw psradl psradq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psraw psrawb psraww psrawl psrawq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psrld psrldb psrldw psrldl psrldq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psrlq psrlqb psrlqw psrlql psrlqq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psrlw psrlwb psrlww psrlwl psrlwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psubb psubbb psubbw psubbl psubbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psubd psubdb psubdw psubdl psubdq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psubsb psubsbb psubsbw psubsbl psubsbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psubsiw psubsiwb psubsiww psubsiwl psubsiwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psubsw psubswb psubsww psubswl psubswq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psubusb psubusbb psubusbw psubusbl psubusbq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psubusw psubuswb psubusww psubuswl psubuswq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} psubw psubwb psubww psubwl psubwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} punpckhbw punpckhbwb punpckhbww punpckhbwl punpckhbwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} punpckhdq punpckhdqb punpckhdqw punpckhdql punpckhdqq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} punpckhwd punpckhwdb punpckhwdw punpckhwdl punpckhwdq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} punpcklbw punpcklbwb punpcklbww punpcklbwl punpcklbwq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} punpckldq punpckldqb punpckldqw punpckldql punpckldqq" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} punpcklwd punpcklwdb punpcklwdw punpcklwdl punpcklwdq" | |
| Opcode_X64_Base="${Opcode_X64_Base} push pushb pushw pushl pushq" | |
| Opcode_186_Base="${Opcode_186_Base} pusha" | |
| Opcode_386_Base="${Opcode_386_Base} pushad" | |
| Opcode_186_Base="${Opcode_186_Base} pushaw" | |
| Opcode_8086_Base="${Opcode_8086_Base} pushf" | |
| Opcode_386_Base="${Opcode_386_Base} pushfd" | |
| Opcode_X64_Base="${Opcode_X64_Base} pushfq" | |
| Opcode_8086_Base="${Opcode_8086_Base} pushfw" | |
| Opcode_PENT_MMX="${Opcode_PENT_MMX} pxor pxorb pxorw pxorl pxorq" | |
| Opcode_X64_Base="${Opcode_X64_Base} rcl rclb rclw rcll rclq" | |
| Opcode_X64_Base="${Opcode_X64_Base} rcr rcrb rcrw rcrl rcrq" | |
| Opcode_P6_Base="${Opcode_P6_Base} rdshr" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} rdmsr" | |
| Opcode_P6_Base="${Opcode_P6_Base} rdpmc" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} rdtsc" | |
| Opcode_X86_64_Base="${Opcode_X86_64_Base} rdtscp" | |
| Opcode_8086_Base="${Opcode_8086_Base} ret retb retw retl retq" | |
| Opcode_8086_Base="${Opcode_8086_Base} retf retfb retfw retfl retfq" | |
| Opcode_8086_Base="${Opcode_8086_Base} retn retnb retnw retnl retnq" | |
| Opcode_X64_Base="${Opcode_X64_Base} rol rolb rolw roll rolq" | |
| Opcode_X64_Base="${Opcode_X64_Base} ror rorb rorw rorl rorq" | |
| Opcode_P6_Base="${Opcode_P6_Base} rdm" | |
| Opcode_486_Base="${Opcode_486_Base} rsdc rsdcb rsdcw rsdcl rsdcq" | |
| Opcode_486_Base="${Opcode_486_Base} rsldt rsldtb rsldtw rsldtl rsldtq" | |
| Opcode_PENTM_Base="${Opcode_PENTM_Base} rsm" | |
| Opcode_486_Base="${Opcode_486_Base} rsts rstsb rstsw rstsl rstsq" | |
| Opcode_8086_Base="${Opcode_8086_Base} sahf" | |
| Opcode_X64_Base="${Opcode_X64_Base} sal salb salw sall salq" | |
| Opcode_8086_Base="${Opcode_8086_Base} salc" | |
| Opcode_X64_Base="${Opcode_X64_Base} sar sarb sarw sarl sarq" | |
| Opcode_386_Base="${Opcode_386_Base} sbb sbbb sbbw sbbl sbbq" | |
| Opcode_8086_Base="${Opcode_8086_Base} scasb" | |
| Opcode_386_Base="${Opcode_386_Base} scasd" | |
| Opcode_X64_Base="${Opcode_X64_Base} scasq" | |
| Opcode_8086_Base="${Opcode_8086_Base} scasw" | |
| Opcode_X64_Base="${Opcode_X64_Base} sfence" | |
| Opcode_286_Base="${Opcode_286_Base} sgdt sgdtb sgdtw sgdtl sgdtq" | |
| Opcode_X64_Base="${Opcode_X64_Base} shl shlb shlw shll shlq" | |
| Opcode_X64_Base="${Opcode_X64_Base} shld" | |
| Opcode_X64_Base="${Opcode_X64_Base} shr shrb shrw shrl shrq" | |
| Opcode_X64_Base="${Opcode_X64_Base} shrd" | |
| Opcode_286_Base="${Opcode_286_Base} sidt sidtb sidtw sidtl sidtq" | |
| Opcode_X64_Base="${Opcode_X64_Base} sldt" | |
| Opcode_X64_Base="${Opcode_X64_Base} skinit" | |
| Opcode_386_Base="${Opcode_386_Base} smi" | |
| Opcode_P6_Base="${Opcode_P6_Base} smint" | |
| Opcode_486_Base="${Opcode_486_Base} smintold" | |
| Opcode_386_Base="${Opcode_386_Base} smsw" | |
| Opcode_8086_Base="${Opcode_8086_Base} stc" | |
| Opcode_8086_Base="${Opcode_8086_Base} std" | |
| Opcode_X64_Base="${Opcode_X64_Base} stgi" | |
| Opcode_8086_Base="${Opcode_8086_Base} sti" | |
| Opcode_8086_Base="${Opcode_8086_Base} stosb" | |
| Opcode_386_Base="${Opcode_386_Base} stosd stosl" | |
| Opcode_X64_Base="${Opcode_X64_Base} stosq" | |
| Opcode_8086_Base="${Opcode_8086_Base} stosw" | |
| Opcode_X64_Base="${Opcode_X64_Base} str" | |
| Opcode_386_Base="${Opcode_386_Base} sub subb subw subl subq" | |
| Opcode_486_Base="${Opcode_486_Base} svdc svdcb svdcw svdcl svdcq" | |
| Opcode_486_Base="${Opcode_486_Base} svldt svldtb svldtw svldtl svldtq" | |
| Opcode_486_Base="${Opcode_486_Base} svts svtsb svtsw svtsl svtsq" | |
| Opcode_X64_Base="${Opcode_X64_Base} swapgs" | |
| Opcode_P6_Base="${Opcode_P6_Base} syscall" | |
| Opcode_P6_Base="${Opcode_P6_Base} sysenter" | |
| Opcode_P6_Base="${Opcode_P6_Base} sysexit" | |
| Opcode_P6_Base="${Opcode_P6_Base} sysret" | |
| Opcode_386_Base="${Opcode_386_Base} test testb testw testl testq" | |
| Opcode_186_Base="${Opcode_186_Base} ud0" | |
| Opcode_186_Base="${Opcode_186_Base} ud1" | |
| Opcode_186_Base="${Opcode_186_Base} ud2b" | |
| Opcode_186_Base="${Opcode_186_Base} ud2" | |
| Opcode_186_Base="${Opcode_186_Base} ud2a" | |
| Opcode_386_Base="${Opcode_386_Base} umov" | |
| Opcode_286_Base="${Opcode_286_Base} verr" | |
| Opcode_286_Base="${Opcode_286_Base} verw" | |
| Opcode_8086_Base="${Opcode_8086_Base} fwait" | |
| Opcode_486_Base="${Opcode_486_Base} wbinvd" | |
| Opcode_P6_Base="${Opcode_P6_Base} wrshr" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} wrmsr" | |
| Opcode_X64_Base="${Opcode_X64_Base} xadd" | |
| Opcode_386_Base="${Opcode_386_Base} xbts" | |
| Opcode_X64_Base="${Opcode_X64_Base} xchg" | |
| Opcode_8086_Base="${Opcode_8086_Base} xlatb" | |
| Opcode_8086_Base="${Opcode_8086_Base} xlat" | |
| Opcode_386_Base="${Opcode_386_Base} xor xorb xorw xorl xorq" | |
| Opcode_X64_Base="${Opcode_X64_Base} cmovcc" | |
| Opcode_8086_Base="${Opcode_8086_Base} j(e|ne|a|ae|b|be|nbe|g|ge|ng|nge|l|le||z|nz|c|nc|d|nd|o|no|p|np|s|ns)[bwlq]?" | |
| Opcode_386_Base="${Opcode_386_Base} set(e|ne|a|ae|b|be|nbe|g|ge|ng|nge|l|le||z|nz|c|nc|d|nd|o|no|p|np|s|ns)[bwlq]?" | |
| # VIA (Centaur) security instructions | |
| Opcode_PENT_Base="${Opcode_PENT_Base} xstore" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} xcryptecb" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} xcryptcbc" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} xcryptctr" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} xcryptcfb" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} xcryptofb" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} montmul" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} xsha1" | |
| Opcode_PENT_Base="${Opcode_PENT_Base} xsha256" | |
| # Intel AVX Carry-Less Multiplication instructions (CLMUL) | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpclmullqlqdq vpclmullqlqdqb vpclmullqlqdqw vpclmullqlqdql vpclmullqlqdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpclmulhqlqdq vpclmulhqlqdqb vpclmulhqlqdqw vpclmulhqlqdql vpclmulhqlqdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpclmullqhqdq vpclmullqhqdqb vpclmullqhqdqw vpclmullqhqdql vpclmullqhqdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpclmulhqhqdq vpclmulhqhqdqb vpclmulhqhqdqw vpclmulhqhqdql vpclmulhqhqdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpclmulqdq vpclmulqdqb vpclmulqdqw vpclmulqdql vpclmulqdqq" | |
| # AMD SSE5 instructions | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fmaddps fmaddpsb fmaddpsw fmaddpsl fmaddpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fmaddpd fmaddpdb fmaddpdw fmaddpdl fmaddpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fmaddss fmaddssb fmaddssw fmaddssl fmaddssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fmaddsd fmaddsdb fmaddsdw fmaddsdl fmaddsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fmsubps fmsubpsb fmsubpsw fmsubpsl fmsubpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fmsubpd fmsubpdb fmsubpdw fmsubpdl fmsubpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fmsubss fmsubssb fmsubssw fmsubssl fmsubssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fmsubsd fmsubsdb fmsubsdw fmsubsdl fmsubsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fnmaddps fnmaddpsb fnmaddpsw fnmaddpsl fnmaddpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fnmaddpd fnmaddpdb fnmaddpdw fnmaddpdl fnmaddpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fnmaddss fnmaddssb fnmaddssw fnmaddssl fnmaddssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fnmaddsd fnmaddsdb fnmaddsdw fnmaddsdl fnmaddsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fnmsubps fnmsubpsb fnmsubpsw fnmsubpsl fnmsubpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fnmsubpd fnmsubpdb fnmsubpdw fnmsubpdl fnmsubpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fnmsubss fnmsubssb fnmsubssw fnmsubssl fnmsubssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} fnmsubsd fnmsubsdb fnmsubsdw fnmsubsdl fnmsubsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comeqps comeqpsb comeqpsw comeqpsl comeqpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comltps comltpsb comltpsw comltpsl comltpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comleps comlepsb comlepsw comlepsl comlepsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunordps comunordpsb comunordpsw comunordpsl comunordpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comuneqps comuneqpsb comuneqpsw comuneqpsl comuneqpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunltps comunltpsb comunltpsw comunltpsl comunltpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunleps comunlepsb comunlepsw comunlepsl comunlepsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comordps comordpsb comordpsw comordpsl comordpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comueqps comueqpsb comueqpsw comueqpsl comueqpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comultps comultpsb comultpsw comultpsl comultpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comuleps comulepsb comulepsw comulepsl comulepsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comfalseps comfalsepsb comfalsepsw comfalsepsl comfalsepsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comneqps comneqpsb comneqpsw comneqpsl comneqpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comnltps comnltpsb comnltpsw comnltpsl comnltpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comnleps comnlepsb comnlepsw comnlepsl comnlepsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comtrueps comtruepsb comtruepsw comtruepsl comtruepsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comps compsb compsw compsl compsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comeqpd comeqpdb comeqpdw comeqpdl comeqpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comltpd comltpdb comltpdw comltpdl comltpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comlepd comlepdb comlepdw comlepdl comlepdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunordpd comunordpdb comunordpdw comunordpdl comunordpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comuneqpd comuneqpdb comuneqpdw comuneqpdl comuneqpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunltpd comunltpdb comunltpdw comunltpdl comunltpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunlepd comunlepdb comunlepdw comunlepdl comunlepdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comordpd comordpdb comordpdw comordpdl comordpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comueqpd comueqpdb comueqpdw comueqpdl comueqpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comultpd comultpdb comultpdw comultpdl comultpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comulepd comulepdb comulepdw comulepdl comulepdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comfalsepd comfalsepdb comfalsepdw comfalsepdl comfalsepdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comneqpd comneqpdb comneqpdw comneqpdl comneqpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comnltpd comnltpdb comnltpdw comnltpdl comnltpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comnlepd comnlepdb comnlepdw comnlepdl comnlepdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comtruepd comtruepdb comtruepdw comtruepdl comtruepdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} compd compdb compdw compdl compdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comeqss comeqssb comeqssw comeqssl comeqssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comltss comltssb comltssw comltssl comltssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comless comlessb comlessw comlessl comlessq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunordss comunordssb comunordssw comunordssl comunordssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comuneqss comuneqssb comuneqssw comuneqssl comuneqssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunltss comunltssb comunltssw comunltssl comunltssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunless comunlessb comunlessw comunlessl comunlessq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comordss comordssb comordssw comordssl comordssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comueqss comueqssb comueqssw comueqssl comueqssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comultss comultssb comultssw comultssl comultssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comuless comulessb comulessw comulessl comulessq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comfalsess comfalsessb comfalsessw comfalsessl comfalsessq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comneqss comneqssb comneqssw comneqssl comneqssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comnltss comnltssb comnltssw comnltssl comnltssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comnless comnlessb comnlessw comnlessl comnlessq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comtruess comtruessb comtruessw comtruessl comtruessq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comss comssb comssw comssl comssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comeqsd comeqsdb comeqsdw comeqsdl comeqsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comltsd comltsdb comltsdw comltsdl comltsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comlesd comlesdb comlesdw comlesdl comlesdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunordsd comunordsdb comunordsdw comunordsdl comunordsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comuneqsd comuneqsdb comuneqsdw comuneqsdl comuneqsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunltsd comunltsdb comunltsdw comunltsdl comunltsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comunlesd comunlesdb comunlesdw comunlesdl comunlesdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comordsd comordsdb comordsdw comordsdl comordsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comueqsd comueqsdb comueqsdw comueqsdl comueqsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comultsd comultsdb comultsdw comultsdl comultsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comulesd comulesdb comulesdw comulesdl comulesdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comfalsesd comfalsesdb comfalsesdw comfalsesdl comfalsesdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comneqsd comneqsdb comneqsdw comneqsdl comneqsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comnltsd comnltsdb comnltsdw comnltsdl comnltsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comnlesd comnlesdb comnlesdw comnlesdl comnlesdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comtruesd comtruesdb comtruesdw comtruesdl comtruesdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} comsd comsdb comsdw comsdl comsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomltb pcomltbb pcomltbw pcomltbl pcomltbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomleb pcomlebb pcomlebw pcomlebl pcomlebq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgtb pcomgtbb pcomgtbw pcomgtbl pcomgtbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgeb pcomgebb pcomgebw pcomgebl pcomgebq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomeqb pcomeqbb pcomeqbw pcomeqbl pcomeqbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomneqb pcomneqbb pcomneqbw pcomneqbl pcomneqbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomfalseb pcomfalsebb pcomfalsebw pcomfalsebl pcomfalsebq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomtrueb pcomtruebb pcomtruebw pcomtruebl pcomtruebq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomb pcombb pcombw pcombl pcombq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomltw pcomltwb pcomltww pcomltwl pcomltwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomlew pcomlewb pcomleww pcomlewl pcomlewq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgtw pcomgtwb pcomgtww pcomgtwl pcomgtwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgew pcomgewb pcomgeww pcomgewl pcomgewq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomeqw pcomeqwb pcomeqww pcomeqwl pcomeqwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomneqw pcomneqwb pcomneqww pcomneqwl pcomneqwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomfalsew pcomfalsewb pcomfalseww pcomfalsewl pcomfalsewq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomtruew pcomtruewb pcomtrueww pcomtruewl pcomtruewq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomw pcomwb pcomww pcomwl pcomwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomltd pcomltdb pcomltdw pcomltdl pcomltdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomled pcomledb pcomledw pcomledl pcomledq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgtd pcomgtdb pcomgtdw pcomgtdl pcomgtdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomged pcomgedb pcomgedw pcomgedl pcomgedq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomeqd pcomeqdb pcomeqdw pcomeqdl pcomeqdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomneqd pcomneqdb pcomneqdw pcomneqdl pcomneqdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomfalsed pcomfalsedb pcomfalsedw pcomfalsedl pcomfalsedq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomtrued pcomtruedb pcomtruedw pcomtruedl pcomtruedq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomd pcomdb pcomdw pcomdl pcomdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomltq pcomltqb pcomltqw pcomltql pcomltqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomleq pcomleqb pcomleqw pcomleql pcomleqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgtq pcomgtqb pcomgtqw pcomgtql pcomgtqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgeq pcomgeqb pcomgeqw pcomgeql pcomgeqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomeqq pcomeqqb pcomeqqw pcomeqql pcomeqqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomneqq pcomneqqb pcomneqqw pcomneqql pcomneqqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomfalseq pcomfalseqb pcomfalseqw pcomfalseql pcomfalseqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomtrueq pcomtrueqb pcomtrueqw pcomtrueql pcomtrueqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomq pcomqb pcomqw pcomql pcomqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomltub pcomltubb pcomltubw pcomltubl pcomltubq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomleub pcomleubb pcomleubw pcomleubl pcomleubq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgtub pcomgtubb pcomgtubw pcomgtubl pcomgtubq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgeub pcomgeubb pcomgeubw pcomgeubl pcomgeubq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomequb pcomequbb pcomequbw pcomequbl pcomequbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomnequb pcomnequbb pcomnequbw pcomnequbl pcomnequbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomfalseub pcomfalseubb pcomfalseubw pcomfalseubl pcomfalseubq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomtrueub pcomtrueubb pcomtrueubw pcomtrueubl pcomtrueubq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomub pcomubb pcomubw pcomubl pcomubq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomltuw pcomltuwb pcomltuww pcomltuwl pcomltuwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomleuw pcomleuwb pcomleuww pcomleuwl pcomleuwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgtuw pcomgtuwb pcomgtuww pcomgtuwl pcomgtuwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgeuw pcomgeuwb pcomgeuww pcomgeuwl pcomgeuwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomequw pcomequwb pcomequww pcomequwl pcomequwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomnequw pcomnequwb pcomnequww pcomnequwl pcomnequwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomfalseuw pcomfalseuwb pcomfalseuww pcomfalseuwl pcomfalseuwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomtrueuw pcomtrueuwb pcomtrueuww pcomtrueuwl pcomtrueuwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomuw pcomuwb pcomuww pcomuwl pcomuwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomltud pcomltudb pcomltudw pcomltudl pcomltudq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomleud pcomleudb pcomleudw pcomleudl pcomleudq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgtud pcomgtudb pcomgtudw pcomgtudl pcomgtudq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgeud pcomgeudb pcomgeudw pcomgeudl pcomgeudq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomequd pcomequdb pcomequdw pcomequdl pcomequdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomnequd pcomnequdb pcomnequdw pcomnequdl pcomnequdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomfalseud pcomfalseudb pcomfalseudw pcomfalseudl pcomfalseudq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomtrueud pcomtrueudb pcomtrueudw pcomtrueudl pcomtrueudq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomud pcomudb pcomudw pcomudl pcomudq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomltuq pcomltuqb pcomltuqw pcomltuql pcomltuqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomleuq pcomleuqb pcomleuqw pcomleuql pcomleuqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgtuq pcomgtuqb pcomgtuqw pcomgtuql pcomgtuqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomgeuq pcomgeuqb pcomgeuqw pcomgeuql pcomgeuqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomequq pcomequqb pcomequqw pcomequql pcomequqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomnequq pcomnequqb pcomnequqw pcomnequql pcomnequqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomfalseuq pcomfalseuqb pcomfalseuqw pcomfalseuql pcomfalseuqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomtrueuq pcomtrueuqb pcomtrueuqw pcomtrueuql pcomtrueuqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcomuq pcomuqb pcomuqw pcomuql pcomuqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} permps permpsb permpsw permpsl permpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} permpd permpdb permpdw permpdl permpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pcmov pcmovb pcmovw pcmovl pcmovq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pperm ppermb ppermw pperml ppermq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacssww pmacsswwb pmacsswww pmacsswwl pmacsswwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacsww pmacswwb pmacswww pmacswwl pmacswwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacsswd pmacsswdb pmacsswdw pmacsswdl pmacsswdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacswd pmacswdb pmacswdw pmacswdl pmacswdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacssdd pmacssddb pmacssddw pmacssddl pmacssddq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacsdd pmacsddb pmacsddw pmacsddl pmacsddq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacssdql pmacssdqlb pmacssdqlw pmacssdqll pmacssdqlq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacsdql pmacsdqlb pmacsdqlw pmacsdqll pmacsdqlq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacssdqh pmacssdqhb pmacssdqhw pmacssdqhl pmacssdqhq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmacsdqh pmacsdqhb pmacsdqhw pmacsdqhl pmacsdqhq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmadcsswd pmadcsswdb pmadcsswdw pmadcsswdl pmadcsswdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pmadcswd pmadcswdb pmadcswdw pmadcswdl pmadcswdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} protb protbb protbw protbl protbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} protw protwb protww protwl protwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} protd protdb protdw protdl protdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} protq protqb protqw protql protqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pshlb pshlbb pshlbw pshlbl pshlbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pshlw pshlwb pshlww pshlwl pshlwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pshld pshldb pshldw pshldl pshldq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pshlq pshlqb pshlqw pshlql pshlqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pshab pshabb pshabw pshabl pshabq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pshaw pshawb pshaww pshawl pshawq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pshad pshadb pshadw pshadl pshadq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} pshaq pshaqb pshaqw pshaql pshaqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} frczps frczpsb frczpsw frczpsl frczpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} frczpd frczpdb frczpdw frczpdl frczpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} frczss frczssb frczssw frczssl frczssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} frczsd frczsdb frczsdw frczsdl frczsdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} cvtph2ps cvtph2psb cvtph2psw cvtph2psl cvtph2psq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} cvtps2ph cvtps2phb cvtps2phw cvtps2phl cvtps2phq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phaddbw phaddbwb phaddbww phaddbwl phaddbwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phaddbd phaddbdb phaddbdw phaddbdl phaddbdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phaddbq phaddbqb phaddbqw phaddbql phaddbqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phaddwd phaddwdb phaddwdw phaddwdl phaddwdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phaddwq phaddwqb phaddwqw phaddwql phaddwqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phadddq phadddqb phadddqw phadddql phadddqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phaddubw phaddubwb phaddubww phaddubwl phaddubwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phaddubd phaddubdb phaddubdw phaddubdl phaddubdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phaddubq phaddubqb phaddubqw phaddubql phaddubqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phadduwd phadduwdb phadduwdw phadduwdl phadduwdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phadduwq phadduwqb phadduwqw phadduwql phadduwqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phaddudq phaddudqb phaddudqw phaddudql phaddudqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phsubbw phsubbwb phsubbww phsubbwl phsubbwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phsubwd phsubwdb phsubwdw phsubwdl phsubwdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} phsubdq phsubdqb phsubdqw phsubdql phsubdqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} protb protbb protbw protbl protbq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} protw protwb protww protwl protwq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} protd protdb protdw protdl protdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} protq protqb protqw protql protqq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} roundps roundpsb roundpsw roundpsl roundpsq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} roundpd roundpdb roundpdw roundpdl roundpdq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} roundss roundssb roundssw roundssl roundssq" | |
| Opcode_AMD_SSE5="${Opcode_AMD_SSE5} roundsd roundsdb roundsdw roundsdl roundsdq" | |
| # Introduced in Deschutes but necessary for SSE support | |
| Opcode_P6_SSE="${Opcode_P6_SSE} fxrstor fxrstorb fxrstorw fxrstorl fxrstorq" | |
| Opcode_P6_SSE="${Opcode_P6_SSE} fxsave fxsaveb fxsavew fxsavel fxsaveq" | |
| # Prescott New Instructions (SSE3) | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} addsubpd addsubpdb addsubpdw addsubpdl addsubpdq" | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} addsubps addsubpsb addsubpsw addsubpsl addsubpsq" | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} haddpd haddpdb haddpdw haddpdl haddpdq" | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} haddps haddpsb haddpsw haddpsl haddpsq" | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} hsubpd hsubpdb hsubpdw hsubpdl hsubpdq" | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} hsubps hsubpsb hsubpsw hsubpsl hsubpsq" | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} lddqu lddqub lddquw lddqul lddquq" | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} movddup movddupb movddupw movddupl movddupq" | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} movshdup movshdupb movshdupw movshdupl movshdupq" | |
| Opcode_PRESCOTT_SSE3="${Opcode_PRESCOTT_SSE3} movsldup movsldupb movsldupw movsldupl movsldupq" | |
| # Intel AES instructions | |
| Opcode_SSE="${Opcode_SSE} aesenc aesencb aesencw aesencl aesencq" | |
| Opcode_SSE="${Opcode_SSE} aesenclast aesenclastb aesenclastw aesenclastl aesenclastq" | |
| Opcode_SSE="${Opcode_SSE} aesdec aesdecb aesdecw aesdecl aesdecq" | |
| Opcode_SSE="${Opcode_SSE} aesdeclast aesdeclastb aesdeclastw aesdeclastl aesdeclastq" | |
| Opcode_SSE="${Opcode_SSE} aesimc aesimcb aesimcw aesimcl aesimcq" | |
| Opcode_SSE="${Opcode_SSE} aeskeygenassist aeskeygenassistb aeskeygenassistw aeskeygenassistl aeskeygenassistq" | |
| # Willamette Streaming SIMD instructions (SSE2) | |
| Opcode_SSE2="${Opcode_SSE2} addpd addpdb addpdw addpdl addpdq" | |
| Opcode_SSE2="${Opcode_SSE2} addsd addsdb addsdw addsdl addsdq" | |
| Opcode_SSE2="${Opcode_SSE2} andnpd andnpdb andnpdw andnpdl andnpdq" | |
| Opcode_SSE2="${Opcode_SSE2} andpd andpdb andpdw andpdl andpdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpeqpd cmpeqpdb cmpeqpdw cmpeqpdl cmpeqpdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpeqsd cmpeqsdb cmpeqsdw cmpeqsdl cmpeqsdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmplepd cmplepdb cmplepdw cmplepdl cmplepdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmplesd cmplesdb cmplesdw cmplesdl cmplesdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpltpd cmpltpdb cmpltpdw cmpltpdl cmpltpdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpltsd cmpltsdb cmpltsdw cmpltsdl cmpltsdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpneqpd cmpneqpdb cmpneqpdw cmpneqpdl cmpneqpdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpneqsd cmpneqsdb cmpneqsdw cmpneqsdl cmpneqsdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpnlepd cmpnlepdb cmpnlepdw cmpnlepdl cmpnlepdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpnlesd cmpnlesdb cmpnlesdw cmpnlesdl cmpnlesdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpnltpd cmpnltpdb cmpnltpdw cmpnltpdl cmpnltpdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpnltsd cmpnltsdb cmpnltsdw cmpnltsdl cmpnltsdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpordpd cmpordpdb cmpordpdw cmpordpdl cmpordpdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpordsd cmpordsdb cmpordsdw cmpordsdl cmpordsdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpunordpd cmpunordpdb cmpunordpdw cmpunordpdl cmpunordpdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpunordsd cmpunordsdb cmpunordsdw cmpunordsdl cmpunordsdq" | |
| Opcode_Base="${Opcode_Base} cmppd cmppdb cmppdw cmppdl cmppdq" | |
| Opcode_SSE2="${Opcode_SSE2} cmpsd cmpsdb cmpsdw cmpsdl cmpsdq" | |
| Opcode_SSE2="${Opcode_SSE2} comisd comisdb comisdw comisdl comisdq" | |
| Opcode_SSE2="${Opcode_SSE2} cvtdq2pd cvtdq2pdb cvtdq2pdw cvtdq2pdl cvtdq2pdq" | |
| Opcode_SSE2="${Opcode_SSE2} cvtdq2ps cvtdq2psb cvtdq2psw cvtdq2psl cvtdq2psq" | |
| Opcode_SSE2="${Opcode_SSE2} cvtpd2dq cvtpd2dqb cvtpd2dqw cvtpd2dql cvtpd2dqq" | |
| Opcode_SSE2="${Opcode_SSE2} cvtpd2pi cvtpd2pib cvtpd2piw cvtpd2pil cvtpd2piq" | |
| Opcode_SSE2="${Opcode_SSE2} cvtpd2ps cvtpd2psb cvtpd2psw cvtpd2psl cvtpd2psq" | |
| Opcode_SSE2="${Opcode_SSE2} cvtpi2pd cvtpi2pdb cvtpi2pdw cvtpi2pdl cvtpi2pdq" | |
| Opcode_SSE2="${Opcode_SSE2} cvtps2dq cvtps2dqb cvtps2dqw cvtps2dql cvtps2dqq" | |
| Opcode_SSE2="${Opcode_SSE2} cvtps2pd cvtps2pdb cvtps2pdw cvtps2pdl cvtps2pdq" | |
| Opcode_X64_SSE2="${Opcode_X64_SSE2} cvtsd2si cvtsd2sib cvtsd2siw cvtsd2sil cvtsd2siq" | |
| Opcode_SSE2="${Opcode_SSE2} cvtsd2ss cvtsd2ssb cvtsd2ssw cvtsd2ssl cvtsd2ssq" | |
| Opcode_X64_SSE2="${Opcode_X64_SSE2} cvtsi2sd" | |
| Opcode_SSE2="${Opcode_SSE2} cvtss2sd cvtss2sdb cvtss2sdw cvtss2sdl cvtss2sdq" | |
| Opcode_SSE2="${Opcode_SSE2} cvttpd2pi cvttpd2pib cvttpd2piw cvttpd2pil cvttpd2piq" | |
| Opcode_SSE2="${Opcode_SSE2} cvttpd2dq cvttpd2dqb cvttpd2dqw cvttpd2dql cvttpd2dqq" | |
| Opcode_SSE2="${Opcode_SSE2} cvttps2dq cvttps2dqb cvttps2dqw cvttps2dql cvttps2dqq" | |
| Opcode_X64_SSE2="${Opcode_X64_SSE2} cvttsd2si cvttsd2sib cvttsd2siw cvttsd2sil cvttsd2siq" | |
| Opcode_SSE2="${Opcode_SSE2} divpd divpdb divpdw divpdl divpdq" | |
| Opcode_SSE2="${Opcode_SSE2} divsd divsdb divsdw divsdl divsdq" | |
| Opcode_SSE2="${Opcode_SSE2} maxpd maxpdb maxpdw maxpdl maxpdq" | |
| Opcode_SSE2="${Opcode_SSE2} maxsd maxsdb maxsdw maxsdl maxsdq" | |
| Opcode_SSE2="${Opcode_SSE2} minpd minpdb minpdw minpdl minpdq" | |
| Opcode_SSE2="${Opcode_SSE2} minsd minsdb minsdw minsdl minsdq" | |
| Opcode_SSE2="${Opcode_SSE2} movapd movapdb movapdw movapdl movapdq" | |
| Opcode_SSE2="${Opcode_SSE2} movhpd movhpdb movhpdw movhpdl movhpdq" | |
| Opcode_SSE2="${Opcode_SSE2} movlpd movlpdb movlpdw movlpdl movlpdq" | |
| Opcode_X64_SSE2="${Opcode_X64_SSE2} movmskpd" | |
| Opcode_SSE2="${Opcode_SSE2} movsd movsdb movsdw movsdl movsdq" | |
| Opcode_SSE2="${Opcode_SSE2} movupd movupdb movupdw movupdl movupdq" | |
| Opcode_SSE2="${Opcode_SSE2} mulpd mulpdb mulpdw mulpdl mulpdq" | |
| Opcode_SSE2="${Opcode_SSE2} mulsd mulsdb mulsdw mulsdl mulsdq" | |
| Opcode_SSE2="${Opcode_SSE2} orpd orpdb orpdw orpdl orpdq" | |
| Opcode_SSE2="${Opcode_SSE2} shufpd shufpdb shufpdw shufpdl shufpdq" | |
| Opcode_SSE2="${Opcode_SSE2} sqrtpd sqrtpdb sqrtpdw sqrtpdl sqrtpdq" | |
| Opcode_SSE2="${Opcode_SSE2} sqrtsd sqrtsdb sqrtsdw sqrtsdl sqrtsdq" | |
| Opcode_SSE2="${Opcode_SSE2} subpd subpdb subpdw subpdl subpdq" | |
| Opcode_SSE2="${Opcode_SSE2} subsd subsdb subsdw subsdl subsdq" | |
| Opcode_SSE2="${Opcode_SSE2} ucomisd ucomisdb ucomisdw ucomisdl ucomisdq" | |
| Opcode_SSE2="${Opcode_SSE2} unpckhpd unpckhpdb unpckhpdw unpckhpdl unpckhpdq" | |
| Opcode_SSE2="${Opcode_SSE2} unpcklpd unpcklpdb unpcklpdw unpcklpdl unpcklpdq" | |
| Opcode_SSE2="${Opcode_SSE2} xorpd xorpdb xorpdw xorpdl xorpdq" | |
| # Intel Carry-Less Multiplication instructions (CLMUL) | |
| Opcode_SSE="${Opcode_SSE} pclmullqlqdq pclmullqlqdqb pclmullqlqdqw pclmullqlqdql pclmullqlqdqq" | |
| Opcode_SSE="${Opcode_SSE} pclmulhqlqdq pclmulhqlqdqb pclmulhqlqdqw pclmulhqlqdql pclmulhqlqdqq" | |
| Opcode_SSE="${Opcode_SSE} pclmullqhqdq pclmullqhqdqb pclmullqhqdqw pclmullqhqdql pclmullqhqdqq" | |
| Opcode_SSE="${Opcode_SSE} pclmulhqhqdq pclmulhqhqdqb pclmulhqhqdqw pclmulhqhqdql pclmulhqhqdqq" | |
| Opcode_SSE="${Opcode_SSE} pclmulqdq pclmulqdqb pclmulqdqw pclmulqdql pclmulqdqq" | |
| # New MMX instructions introduced in Katmai | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} maskmovq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} movntq movntqb movntqw movntql movntqq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pavgb pavgbb pavgbw pavgbl pavgbq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pavgw pavgwb pavgww pavgwl pavgwq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pextrw pextrwb pextrww pextrwl pextrwq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pinsrw pinsrwb pinsrww pinsrwl pinsrwq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pmaxsw pmaxswb pmaxsww pmaxswl pmaxswq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pmaxub pmaxubb pmaxubw pmaxubl pmaxubq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pminsw pminswb pminsww pminswl pminswq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pminub pminubb pminubw pminubl pminubq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pmovmskb" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} pmulhuw pmulhuwb pmulhuww pmulhuwl pmulhuwq" | |
| Opcode_KATMAI_MMX="${Opcode_KATMAI_MMX} psadbw psadbwb psadbww psadbwl psadbwq" | |
| Opcode_KATMAI_MMX2="${Opcode_KATMAI_MMX2} pshufw pshufwb pshufww pshufwl pshufwq" | |
| # Intel SMX | |
| Opcode_KATMAI_Base="${Opcode_KATMAI_Base} getsec" | |
| # Katmai Streaming SIMD instructions (SSE -- a.k.a. KNI, XMM, MMX2) | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} addps addpsb addpsw addpsl addpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} addss addssb addssw addssl addssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} andnps andnpsb andnpsw andnpsl andnpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} andps andpsb andpsw andpsl andpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpeqps cmpeqpsb cmpeqpsw cmpeqpsl cmpeqpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpeqss cmpeqssb cmpeqssw cmpeqssl cmpeqssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpleps cmplepsb cmplepsw cmplepsl cmplepsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpless cmplessb cmplessw cmplessl cmplessq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpltps cmpltpsb cmpltpsw cmpltpsl cmpltpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpltss cmpltssb cmpltssw cmpltssl cmpltssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpneqps cmpneqpsb cmpneqpsw cmpneqpsl cmpneqpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpneqss cmpneqssb cmpneqssw cmpneqssl cmpneqssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpnleps cmpnlepsb cmpnlepsw cmpnlepsl cmpnlepsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpnless cmpnlessb cmpnlessw cmpnlessl cmpnlessq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpnltps cmpnltpsb cmpnltpsw cmpnltpsl cmpnltpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpnltss cmpnltssb cmpnltssw cmpnltssl cmpnltssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpordps cmpordpsb cmpordpsw cmpordpsl cmpordpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpordss cmpordssb cmpordssw cmpordssl cmpordssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpunordps cmpunordpsb cmpunordpsw cmpunordpsl cmpunordpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpunordss cmpunordssb cmpunordssw cmpunordssl cmpunordssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpps cmppsb cmppsw cmppsl cmppsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cmpss cmpssb cmpssw cmpssl cmpssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} comiss comissb comissw comissl comissq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cvtpi2ps cvtpi2psb cvtpi2psw cvtpi2psl cvtpi2psq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cvtps2pi cvtps2pib cvtps2piw cvtps2pil cvtps2piq" | |
| Opcode_X64_SSE="${Opcode_X64_SSE} cvtsi2ss" | |
| Opcode_X64_SSE="${Opcode_X64_SSE} cvtss2si cvtss2sib cvtss2siw cvtss2sil cvtss2siq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} cvttps2pi cvttps2pib cvttps2piw cvttps2pil cvttps2piq" | |
| Opcode_X64_SSE="${Opcode_X64_SSE} cvttss2si cvttss2sib cvttss2siw cvttss2sil cvttss2siq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} divps divpsb divpsw divpsl divpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} divss divssb divssw divssl divssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} ldmxcsr ldmxcsrb ldmxcsrw ldmxcsrl ldmxcsrq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} maxps maxpsb maxpsw maxpsl maxpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} maxss maxssb maxssw maxssl maxssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} minps minpsb minpsw minpsl minpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} minss minssb minssw minssl minssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} movaps" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} movhps movhpsb movhpsw movhpsl movhpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} movlhps" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} movlps movlpsb movlpsw movlpsl movlpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} movhlps" | |
| Opcode_X64_SSE="${Opcode_X64_SSE} movmskps" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} movntps movntpsb movntpsw movntpsl movntpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} movss" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} movups" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} mulps mulpsb mulpsw mulpsl mulpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} mulss mulssb mulssw mulssl mulssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} orps orpsb orpsw orpsl orpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} rcpps rcppsb rcppsw rcppsl rcppsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} rcpss rcpssb rcpssw rcpssl rcpssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} rsqrtps rsqrtpsb rsqrtpsw rsqrtpsl rsqrtpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} rsqrtss rsqrtssb rsqrtssw rsqrtssl rsqrtssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} shufps shufpsb shufpsw shufpsl shufpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} sqrtps sqrtpsb sqrtpsw sqrtpsl sqrtpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} sqrtss sqrtssb sqrtssw sqrtssl sqrtssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} stmxcsr stmxcsrb stmxcsrw stmxcsrl stmxcsrq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} subps subpsb subpsw subpsl subpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} subss subssb subssw subssl subssq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} ucomiss ucomissb ucomissw ucomissl ucomissq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} unpckhps unpckhpsb unpckhpsw unpckhpsl unpckhpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} unpcklps unpcklpsb unpcklpsw unpcklpsl unpcklpsq" | |
| Opcode_KATMAI_SSE="${Opcode_KATMAI_SSE} xorps xorpsb xorpsw xorpsl xorpsq" | |
| # Extended Page Tables VMX instructions | |
| Opcode_VMX="${Opcode_VMX} invept inveptb inveptw inveptl inveptq" | |
| Opcode_VMX="${Opcode_VMX} invvpid invvpidb invvpidw invvpidl invvpidq" | |
| # VMX Instructions | |
| Opcode_VMX="${Opcode_VMX} vmcall" | |
| Opcode_VMX="${Opcode_VMX} vmclear vmclearb vmclearw vmclearl vmclearq" | |
| Opcode_VMX="${Opcode_VMX} vmlaunch" | |
| Opcode_X64_VMX="${Opcode_X64_VMX} vmload" | |
| Opcode_X64_VMX="${Opcode_X64_VMX} vmmcall" | |
| Opcode_VMX="${Opcode_VMX} vmptrld vmptrldb vmptrldw vmptrldl vmptrldq" | |
| Opcode_VMX="${Opcode_VMX} vmptrst vmptrstb vmptrstw vmptrstl vmptrstq" | |
| Opcode_X64_VMX="${Opcode_X64_VMX} vmread" | |
| Opcode_VMX="${Opcode_VMX} vmresume" | |
| Opcode_X64_VMX="${Opcode_X64_VMX} vmrun" | |
| Opcode_X64_VMX="${Opcode_X64_VMX} vmsave" | |
| Opcode_X64_VMX="${Opcode_X64_VMX} vmwrite" | |
| Opcode_VMX="${Opcode_VMX} vmxoff" | |
| Opcode_VMX="${Opcode_VMX} vmxon vmxonb vmxonw vmxonl vmxonq" | |
| # Intel AVX AES instructions | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaesenc vaesencb vaesencw vaesencl vaesencq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaesenclast vaesenclastb vaesenclastw vaesenclastl vaesenclastq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaesdec vaesdecb vaesdecw vaesdecl vaesdecq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaesdeclast vaesdeclastb vaesdeclastw vaesdeclastl vaesdeclastq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaesimc vaesimcb vaesimcw vaesimcl vaesimcq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaeskeygenassist vaeskeygenassistb vaeskeygenassistw vaeskeygenassistl vaeskeygenassistq" | |
| # New instructions in Barcelona | |
| Opcode_X64_Base="${Opcode_X64_Base} lzcnt" | |
| # Intel AVX instructions | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaddpd vaddpdb vaddpdw vaddpdl vaddpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaddps vaddpsb vaddpsw vaddpsl vaddpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaddsd vaddsdb vaddsdw vaddsdl vaddsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaddss vaddssb vaddssw vaddssl vaddssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaddsubpd vaddsubpdb vaddsubpdw vaddsubpdl vaddsubpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vaddsubps vaddsubpsb vaddsubpsw vaddsubpsl vaddsubpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vandpd vandpdb vandpdw vandpdl vandpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vandps vandpsb vandpsw vandpsl vandpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vandnpd vandnpdb vandnpdw vandnpdl vandnpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vandnps vandnpsb vandnpsw vandnpsl vandnpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vblendpd vblendpdb vblendpdw vblendpdl vblendpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vblendps vblendpsb vblendpsw vblendpsl vblendpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vblendvpd vblendvpdb vblendvpdw vblendvpdl vblendvpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vblendvps vblendvpsb vblendvpsw vblendvpsl vblendvpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vblendvpd vblendvpdb vblendvpdw vblendvpdl vblendvpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vbroadcastss vbroadcastssb vbroadcastssw vbroadcastssl vbroadcastssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vbroadcastsd vbroadcastsdb vbroadcastsdw vbroadcastsdl vbroadcastsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vbroadcastf128 vbroadcastf128b vbroadcastf128w vbroadcastf128l vbroadcastf128q" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeqpd vcmpeqpdb vcmpeqpdw vcmpeqpdl vcmpeqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpltpd vcmpltpdb vcmpltpdw vcmpltpdl vcmpltpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmplepd vcmplepdb vcmplepdw vcmplepdl vcmplepdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpunordpd vcmpunordpdb vcmpunordpdw vcmpunordpdl vcmpunordpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneqpd vcmpneqpdb vcmpneqpdw vcmpneqpdl vcmpneqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnltpd vcmpnltpdb vcmpnltpdw vcmpnltpdl vcmpnltpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnlepd vcmpnlepdb vcmpnlepdw vcmpnlepdl vcmpnlepdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpordpd vcmpordpdb vcmpordpdw vcmpordpdl vcmpordpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_uqpd vcmpeq_uqpdb vcmpeq_uqpdw vcmpeq_uqpdl vcmpeq_uqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngepd vcmpngepdb vcmpngepdw vcmpngepdl vcmpngepdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngtpd vcmpngtpdb vcmpngtpdw vcmpngtpdl vcmpngtpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpfalsepd vcmpfalsepdb vcmpfalsepdw vcmpfalsepdl vcmpfalsepdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_oqpd vcmpneq_oqpdb vcmpneq_oqpdw vcmpneq_oqpdl vcmpneq_oqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgepd vcmpgepdb vcmpgepdw vcmpgepdl vcmpgepdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgtpd vcmpgtpdb vcmpgtpdw vcmpgtpdl vcmpgtpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmptruepd vcmptruepdb vcmptruepdw vcmptruepdl vcmptruepdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_ospd vcmpeq_ospdb vcmpeq_ospdw vcmpeq_ospdl vcmpeq_ospdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmplt_oqpd vcmplt_oqpdb vcmplt_oqpdw vcmplt_oqpdl vcmplt_oqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmple_oqpd vcmple_oqpdb vcmple_oqpdw vcmple_oqpdl vcmple_oqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpunord_spd vcmpunord_spdb vcmpunord_spdw vcmpunord_spdl vcmpunord_spdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_uspd vcmpneq_uspdb vcmpneq_uspdw vcmpneq_uspdl vcmpneq_uspdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnlt_uqpd vcmpnlt_uqpdb vcmpnlt_uqpdw vcmpnlt_uqpdl vcmpnlt_uqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnle_uqpd vcmpnle_uqpdb vcmpnle_uqpdw vcmpnle_uqpdl vcmpnle_uqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpord_spd vcmpord_spdb vcmpord_spdw vcmpord_spdl vcmpord_spdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_uspd vcmpeq_uspdb vcmpeq_uspdw vcmpeq_uspdl vcmpeq_uspdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnge_uqpd vcmpnge_uqpdb vcmpnge_uqpdw vcmpnge_uqpdl vcmpnge_uqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngt_uqpd vcmpngt_uqpdb vcmpngt_uqpdw vcmpngt_uqpdl vcmpngt_uqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpfalse_ospd vcmpfalse_ospdb vcmpfalse_ospdw vcmpfalse_ospdl vcmpfalse_ospdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_ospd vcmpneq_ospdb vcmpneq_ospdw vcmpneq_ospdl vcmpneq_ospdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpge_oqpd vcmpge_oqpdb vcmpge_oqpdw vcmpge_oqpdl vcmpge_oqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgt_oqpd vcmpgt_oqpdb vcmpgt_oqpdw vcmpgt_oqpdl vcmpgt_oqpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmptrue_uspd vcmptrue_uspdb vcmptrue_uspdw vcmptrue_uspdl vcmptrue_uspdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmppd vcmppdb vcmppdw vcmppdl vcmppdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeqps vcmpeqpsb vcmpeqpsw vcmpeqpsl vcmpeqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpltps vcmpltpsb vcmpltpsw vcmpltpsl vcmpltpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpleps vcmplepsb vcmplepsw vcmplepsl vcmplepsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpunordps vcmpunordpsb vcmpunordpsw vcmpunordpsl vcmpunordpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneqps vcmpneqpsb vcmpneqpsw vcmpneqpsl vcmpneqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnltps vcmpnltpsb vcmpnltpsw vcmpnltpsl vcmpnltpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnleps vcmpnlepsb vcmpnlepsw vcmpnlepsl vcmpnlepsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpordps vcmpordpsb vcmpordpsw vcmpordpsl vcmpordpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_uqps vcmpeq_uqpsb vcmpeq_uqpsw vcmpeq_uqpsl vcmpeq_uqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngeps vcmpngepsb vcmpngepsw vcmpngepsl vcmpngepsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngtps vcmpngtpsb vcmpngtpsw vcmpngtpsl vcmpngtpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpfalseps vcmpfalsepsb vcmpfalsepsw vcmpfalsepsl vcmpfalsepsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_oqps vcmpneq_oqpsb vcmpneq_oqpsw vcmpneq_oqpsl vcmpneq_oqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgeps vcmpgepsb vcmpgepsw vcmpgepsl vcmpgepsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgtps vcmpgtpsb vcmpgtpsw vcmpgtpsl vcmpgtpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmptrueps vcmptruepsb vcmptruepsw vcmptruepsl vcmptruepsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_osps vcmpeq_ospsb vcmpeq_ospsw vcmpeq_ospsl vcmpeq_ospsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmplt_oqps vcmplt_oqpsb vcmplt_oqpsw vcmplt_oqpsl vcmplt_oqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmple_oqps vcmple_oqpsb vcmple_oqpsw vcmple_oqpsl vcmple_oqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpunord_sps vcmpunord_spsb vcmpunord_spsw vcmpunord_spsl vcmpunord_spsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_usps vcmpneq_uspsb vcmpneq_uspsw vcmpneq_uspsl vcmpneq_uspsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnlt_uqps vcmpnlt_uqpsb vcmpnlt_uqpsw vcmpnlt_uqpsl vcmpnlt_uqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnle_uqps vcmpnle_uqpsb vcmpnle_uqpsw vcmpnle_uqpsl vcmpnle_uqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpord_sps vcmpord_spsb vcmpord_spsw vcmpord_spsl vcmpord_spsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_usps vcmpeq_uspsb vcmpeq_uspsw vcmpeq_uspsl vcmpeq_uspsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnge_uqps vcmpnge_uqpsb vcmpnge_uqpsw vcmpnge_uqpsl vcmpnge_uqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngt_uqps vcmpngt_uqpsb vcmpngt_uqpsw vcmpngt_uqpsl vcmpngt_uqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpfalse_osps vcmpfalse_ospsb vcmpfalse_ospsw vcmpfalse_ospsl vcmpfalse_ospsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_osps vcmpneq_ospsb vcmpneq_ospsw vcmpneq_ospsl vcmpneq_ospsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpge_oqps vcmpge_oqpsb vcmpge_oqpsw vcmpge_oqpsl vcmpge_oqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgt_oqps vcmpgt_oqpsb vcmpgt_oqpsw vcmpgt_oqpsl vcmpgt_oqpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmptrue_usps vcmptrue_uspsb vcmptrue_uspsw vcmptrue_uspsl vcmptrue_uspsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpps vcmppsb vcmppsw vcmppsl vcmppsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeqsd vcmpeqsdb vcmpeqsdw vcmpeqsdl vcmpeqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpltsd vcmpltsdb vcmpltsdw vcmpltsdl vcmpltsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmplesd vcmplesdb vcmplesdw vcmplesdl vcmplesdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpunordsd vcmpunordsdb vcmpunordsdw vcmpunordsdl vcmpunordsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneqsd vcmpneqsdb vcmpneqsdw vcmpneqsdl vcmpneqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnltsd vcmpnltsdb vcmpnltsdw vcmpnltsdl vcmpnltsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnlesd vcmpnlesdb vcmpnlesdw vcmpnlesdl vcmpnlesdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpordsd vcmpordsdb vcmpordsdw vcmpordsdl vcmpordsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_uqsd vcmpeq_uqsdb vcmpeq_uqsdw vcmpeq_uqsdl vcmpeq_uqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngesd vcmpngesdb vcmpngesdw vcmpngesdl vcmpngesdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngtsd vcmpngtsdb vcmpngtsdw vcmpngtsdl vcmpngtsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpfalsesd vcmpfalsesdb vcmpfalsesdw vcmpfalsesdl vcmpfalsesdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_oqsd vcmpneq_oqsdb vcmpneq_oqsdw vcmpneq_oqsdl vcmpneq_oqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgesd vcmpgesdb vcmpgesdw vcmpgesdl vcmpgesdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgtsd vcmpgtsdb vcmpgtsdw vcmpgtsdl vcmpgtsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmptruesd vcmptruesdb vcmptruesdw vcmptruesdl vcmptruesdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_ossd vcmpeq_ossdb vcmpeq_ossdw vcmpeq_ossdl vcmpeq_ossdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmplt_oqsd vcmplt_oqsdb vcmplt_oqsdw vcmplt_oqsdl vcmplt_oqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmple_oqsd vcmple_oqsdb vcmple_oqsdw vcmple_oqsdl vcmple_oqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpunord_ssd vcmpunord_ssdb vcmpunord_ssdw vcmpunord_ssdl vcmpunord_ssdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_ussd vcmpneq_ussdb vcmpneq_ussdw vcmpneq_ussdl vcmpneq_ussdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnlt_uqsd vcmpnlt_uqsdb vcmpnlt_uqsdw vcmpnlt_uqsdl vcmpnlt_uqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnle_uqsd vcmpnle_uqsdb vcmpnle_uqsdw vcmpnle_uqsdl vcmpnle_uqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpord_ssd vcmpord_ssdb vcmpord_ssdw vcmpord_ssdl vcmpord_ssdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_ussd vcmpeq_ussdb vcmpeq_ussdw vcmpeq_ussdl vcmpeq_ussdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnge_uqsd vcmpnge_uqsdb vcmpnge_uqsdw vcmpnge_uqsdl vcmpnge_uqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngt_uqsd vcmpngt_uqsdb vcmpngt_uqsdw vcmpngt_uqsdl vcmpngt_uqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpfalse_ossd vcmpfalse_ossdb vcmpfalse_ossdw vcmpfalse_ossdl vcmpfalse_ossdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_ossd vcmpneq_ossdb vcmpneq_ossdw vcmpneq_ossdl vcmpneq_ossdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpge_oqsd vcmpge_oqsdb vcmpge_oqsdw vcmpge_oqsdl vcmpge_oqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgt_oqsd vcmpgt_oqsdb vcmpgt_oqsdw vcmpgt_oqsdl vcmpgt_oqsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmptrue_ussd vcmptrue_ussdb vcmptrue_ussdw vcmptrue_ussdl vcmptrue_ussdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpsd vcmpsdb vcmpsdw vcmpsdl vcmpsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeqss vcmpeqssb vcmpeqssw vcmpeqssl vcmpeqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpltss vcmpltssb vcmpltssw vcmpltssl vcmpltssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpless vcmplessb vcmplessw vcmplessl vcmplessq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpunordss vcmpunordssb vcmpunordssw vcmpunordssl vcmpunordssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneqss vcmpneqssb vcmpneqssw vcmpneqssl vcmpneqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnltss vcmpnltssb vcmpnltssw vcmpnltssl vcmpnltssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnless vcmpnlessb vcmpnlessw vcmpnlessl vcmpnlessq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpordss vcmpordssb vcmpordssw vcmpordssl vcmpordssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_uqss vcmpeq_uqssb vcmpeq_uqssw vcmpeq_uqssl vcmpeq_uqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngess vcmpngessb vcmpngessw vcmpngessl vcmpngessq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngtss vcmpngtssb vcmpngtssw vcmpngtssl vcmpngtssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpfalsess vcmpfalsessb vcmpfalsessw vcmpfalsessl vcmpfalsessq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_oqss vcmpneq_oqssb vcmpneq_oqssw vcmpneq_oqssl vcmpneq_oqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgess vcmpgessb vcmpgessw vcmpgessl vcmpgessq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgtss vcmpgtssb vcmpgtssw vcmpgtssl vcmpgtssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmptruess vcmptruessb vcmptruessw vcmptruessl vcmptruessq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_osss vcmpeq_osssb vcmpeq_osssw vcmpeq_osssl vcmpeq_osssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmplt_oqss vcmplt_oqssb vcmplt_oqssw vcmplt_oqssl vcmplt_oqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmple_oqss vcmple_oqssb vcmple_oqssw vcmple_oqssl vcmple_oqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpunord_sss vcmpunord_sssb vcmpunord_sssw vcmpunord_sssl vcmpunord_sssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_usss vcmpneq_usssb vcmpneq_usssw vcmpneq_usssl vcmpneq_usssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnlt_uqss vcmpnlt_uqssb vcmpnlt_uqssw vcmpnlt_uqssl vcmpnlt_uqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnle_uqss vcmpnle_uqssb vcmpnle_uqssw vcmpnle_uqssl vcmpnle_uqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpord_sss vcmpord_sssb vcmpord_sssw vcmpord_sssl vcmpord_sssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpeq_usss vcmpeq_usssb vcmpeq_usssw vcmpeq_usssl vcmpeq_usssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpnge_uqss vcmpnge_uqssb vcmpnge_uqssw vcmpnge_uqssl vcmpnge_uqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpngt_uqss vcmpngt_uqssb vcmpngt_uqssw vcmpngt_uqssl vcmpngt_uqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpfalse_osss vcmpfalse_osssb vcmpfalse_osssw vcmpfalse_osssl vcmpfalse_osssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpneq_osss vcmpneq_osssb vcmpneq_osssw vcmpneq_osssl vcmpneq_osssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpge_oqss vcmpge_oqssb vcmpge_oqssw vcmpge_oqssl vcmpge_oqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpgt_oqss vcmpgt_oqssb vcmpgt_oqssw vcmpgt_oqssl vcmpgt_oqssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmptrue_usss vcmptrue_usssb vcmptrue_usssw vcmptrue_usssl vcmptrue_usssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcmpss vcmpssb vcmpssw vcmpssl vcmpssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcomisd vcomisdb vcomisdw vcomisdl vcomisdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcomiss vcomissb vcomissw vcomissl vcomissq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtdq2pd vcvtdq2pdb vcvtdq2pdw vcvtdq2pdl vcvtdq2pdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtdq2ps vcvtdq2psb vcvtdq2psw vcvtdq2psl vcvtdq2psq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtpd2dq vcvtpd2dqb vcvtpd2dqw vcvtpd2dql vcvtpd2dqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtpd2ps vcvtpd2psb vcvtpd2psw vcvtpd2psl vcvtpd2psq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtps2dq vcvtps2dqb vcvtps2dqw vcvtps2dql vcvtps2dqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtps2pd vcvtps2pdb vcvtps2pdw vcvtps2pdl vcvtps2pdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtsd2si vcvtsd2sib vcvtsd2siw vcvtsd2sil vcvtsd2siq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtsd2ss vcvtsd2ssb vcvtsd2ssw vcvtsd2ssl vcvtsd2ssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtsi2sd" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtsi2ss" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtss2sd vcvtss2sdb vcvtss2sdw vcvtss2sdl vcvtss2sdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvtss2si vcvtss2sib vcvtss2siw vcvtss2sil vcvtss2siq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvttpd2dq vcvttpd2dqb vcvttpd2dqw vcvttpd2dql vcvttpd2dqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvttps2dq vcvttps2dqb vcvttps2dqw vcvttps2dql vcvttps2dqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvttsd2si vcvttsd2sib vcvttsd2siw vcvttsd2sil vcvttsd2siq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vcvttss2si vcvttss2sib vcvttss2siw vcvttss2sil vcvttss2siq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vdivpd vdivpdb vdivpdw vdivpdl vdivpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vdivps vdivpsb vdivpsw vdivpsl vdivpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vdivsd vdivsdb vdivsdw vdivsdl vdivsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vdivss vdivssb vdivssw vdivssl vdivssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vdppd vdppdb vdppdw vdppdl vdppdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vdpps vdppsb vdppsw vdppsl vdppsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vextractf128 vextractf128b vextractf128w vextractf128l vextractf128q" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vextractps vextractpsb vextractpsw vextractpsl vextractpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vhaddpd vhaddpdb vhaddpdw vhaddpdl vhaddpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vhaddps vhaddpsb vhaddpsw vhaddpsl vhaddpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vhsubpd vhsubpdb vhsubpdw vhsubpdl vhsubpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vhsubps vhsubpsb vhsubpsw vhsubpsl vhsubpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vinsertf128 vinsertf128b vinsertf128w vinsertf128l vinsertf128q" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vinsertps vinsertpsb vinsertpsw vinsertpsl vinsertpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vlddqu vlddqub vlddquw vlddqul vlddquq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vldqqu vldqqub vldqquw vldqqul vldqquq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vlddqu vlddqub vlddquw vlddqul vlddquq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vldmxcsr vldmxcsrb vldmxcsrw vldmxcsrl vldmxcsrq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmaskmovdqu" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmaskmovps vmaskmovpsb vmaskmovpsw vmaskmovpsl vmaskmovpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmaskmovpd vmaskmovpdb vmaskmovpdw vmaskmovpdl vmaskmovpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmaxpd vmaxpdb vmaxpdw vmaxpdl vmaxpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmaxps vmaxpsb vmaxpsw vmaxpsl vmaxpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmaxsd vmaxsdb vmaxsdw vmaxsdl vmaxsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmaxss vmaxssb vmaxssw vmaxssl vmaxssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vminpd vminpdb vminpdw vminpdl vminpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vminps vminpsb vminpsw vminpsl vminpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vminsd vminsdb vminsdw vminsdl vminsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vminss vminssb vminssw vminssl vminssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovapd vmovapdb vmovapdw vmovapdl vmovapdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovaps vmovapsb vmovapsw vmovapsl vmovapsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovq vmovqb vmovqw vmovql vmovqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovd" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovd" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovddup vmovddupb vmovddupw vmovddupl vmovddupq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovdqa vmovdqab vmovdqaw vmovdqal vmovdqaq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovqqa vmovqqab vmovqqaw vmovqqal vmovqqaq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovdqa vmovdqab vmovdqaw vmovdqal vmovdqaq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovdqu vmovdqub vmovdquw vmovdqul vmovdquq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovqqu vmovqqub vmovqquw vmovqqul vmovqquq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovdqu vmovdqub vmovdquw vmovdqul vmovdquq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovhlps" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovhpd vmovhpdb vmovhpdw vmovhpdl vmovhpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovhps vmovhpsb vmovhpsw vmovhpsl vmovhpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovlhps" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovlpd vmovlpdb vmovlpdw vmovlpdl vmovlpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovlps vmovlpsb vmovlpsw vmovlpsl vmovlpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovmskpd vmovmskpdb vmovmskpdw vmovmskpdl vmovmskpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovmskps vmovmskpsb vmovmskpsw vmovmskpsl vmovmskpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovntdq vmovntdqb vmovntdqw vmovntdql vmovntdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovntqq vmovntqqb vmovntqqw vmovntqql vmovntqqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovntdq vmovntdqb vmovntdqw vmovntdql vmovntdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovntdqa vmovntdqab vmovntdqaw vmovntdqal vmovntdqaq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovntpd vmovntpdb vmovntpdw vmovntpdl vmovntpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovntps vmovntpsb vmovntpsw vmovntpsl vmovntpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovsd vmovsdb vmovsdw vmovsdl vmovsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovshdup vmovshdupb vmovshdupw vmovshdupl vmovshdupq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovsldup vmovsldupb vmovsldupw vmovsldupl vmovsldupq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovss vmovssb vmovssw vmovssl vmovssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovupd vmovupdb vmovupdw vmovupdl vmovupdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmovups vmovupsb vmovupsw vmovupsl vmovupsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmpsadbw vmpsadbwb vmpsadbww vmpsadbwl vmpsadbwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmulpd vmulpdb vmulpdw vmulpdl vmulpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmulps vmulpsb vmulpsw vmulpsl vmulpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmulsd vmulsdb vmulsdw vmulsdl vmulsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vmulss vmulssb vmulssw vmulssl vmulssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vorpd vorpdb vorpdw vorpdl vorpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vorps vorpsb vorpsw vorpsl vorpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpabsb vpabsbb vpabsbw vpabsbl vpabsbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpabsw vpabswb vpabsww vpabswl vpabswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpabsd vpabsdb vpabsdw vpabsdl vpabsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpacksswb vpacksswbb vpacksswbw vpacksswbl vpacksswbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpackssdw vpackssdwb vpackssdww vpackssdwl vpackssdwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpackuswb vpackuswbb vpackuswbw vpackuswbl vpackuswbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpackusdw vpackusdwb vpackusdww vpackusdwl vpackusdwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpaddb vpaddbb vpaddbw vpaddbl vpaddbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpaddw vpaddwb vpaddww vpaddwl vpaddwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpaddd vpadddb vpadddw vpadddl vpadddq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpaddq vpaddqb vpaddqw vpaddql vpaddqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpaddsb vpaddsbb vpaddsbw vpaddsbl vpaddsbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpaddsw vpaddswb vpaddsww vpaddswl vpaddswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpaddusb vpaddusbb vpaddusbw vpaddusbl vpaddusbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpaddusw vpadduswb vpaddusww vpadduswl vpadduswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpalignr vpalignrb vpalignrw vpalignrl vpalignrq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpand vpandb vpandw vpandl vpandq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpandn vpandnb vpandnw vpandnl vpandnq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpavgb vpavgbb vpavgbw vpavgbl vpavgbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpavgw vpavgwb vpavgww vpavgwl vpavgwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpblendvb vpblendvbb vpblendvbw vpblendvbl vpblendvbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpblendw vpblendwb vpblendww vpblendwl vpblendwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpestri vpcmpestrib vpcmpestriw vpcmpestril vpcmpestriq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpestrm vpcmpestrmb vpcmpestrmw vpcmpestrml vpcmpestrmq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpistri vpcmpistrib vpcmpistriw vpcmpistril vpcmpistriq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpistrm vpcmpistrmb vpcmpistrmw vpcmpistrml vpcmpistrmq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpeqb vpcmpeqbb vpcmpeqbw vpcmpeqbl vpcmpeqbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpeqw vpcmpeqwb vpcmpeqww vpcmpeqwl vpcmpeqwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpeqd vpcmpeqdb vpcmpeqdw vpcmpeqdl vpcmpeqdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpeqq vpcmpeqqb vpcmpeqqw vpcmpeqql vpcmpeqqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpgtb vpcmpgtbb vpcmpgtbw vpcmpgtbl vpcmpgtbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpgtw vpcmpgtwb vpcmpgtww vpcmpgtwl vpcmpgtwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpgtd vpcmpgtdb vpcmpgtdw vpcmpgtdl vpcmpgtdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpcmpgtq vpcmpgtqb vpcmpgtqw vpcmpgtql vpcmpgtqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermilpd vpermilpdb vpermilpdw vpermilpdl vpermilpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermiltd2pd vpermiltd2pdb vpermiltd2pdw vpermiltd2pdl vpermiltd2pdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermilmo2pd vpermilmo2pdb vpermilmo2pdw vpermilmo2pdl vpermilmo2pdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermilmz2pd vpermilmz2pdb vpermilmz2pdw vpermilmz2pdl vpermilmz2pdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermil2pd vpermil2pdb vpermil2pdw vpermil2pdl vpermil2pdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermilps vpermilpsb vpermilpsw vpermilpsl vpermilpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermiltd2ps vpermiltd2psb vpermiltd2psw vpermiltd2psl vpermiltd2psq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermilmo2ps vpermilmo2psb vpermilmo2psw vpermilmo2psl vpermilmo2psq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermilmz2ps vpermilmz2psb vpermilmz2psw vpermilmz2psl vpermilmz2psq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpermil2ps vpermil2psb vpermil2psw vpermil2psl vpermil2psq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vperm2f128 vperm2f128b vperm2f128w vperm2f128l vperm2f128q" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpextrb vpextrbb vpextrbw vpextrbl vpextrbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpextrw vpextrwb vpextrww vpextrwl vpextrwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpextrd vpextrdb vpextrdw vpextrdl vpextrdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpextrq vpextrqb vpextrqw vpextrql vpextrqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vphaddw vphaddwb vphaddww vphaddwl vphaddwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vphaddd vphadddb vphadddw vphadddl vphadddq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vphaddsw vphaddswb vphaddsww vphaddswl vphaddswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vphminposuw vphminposuwb vphminposuww vphminposuwl vphminposuwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vphsubw vphsubwb vphsubww vphsubwl vphsubwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vphsubd vphsubdb vphsubdw vphsubdl vphsubdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vphsubsw vphsubswb vphsubsww vphsubswl vphsubswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpinsrb vpinsrbb vpinsrbw vpinsrbl vpinsrbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpinsrw vpinsrwb vpinsrww vpinsrwl vpinsrwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpinsrd vpinsrdb vpinsrdw vpinsrdl vpinsrdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpinsrq vpinsrqb vpinsrqw vpinsrql vpinsrqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmaddwd vpmaddwdb vpmaddwdw vpmaddwdl vpmaddwdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmaddubsw vpmaddubswb vpmaddubsww vpmaddubswl vpmaddubswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmaxsb vpmaxsbb vpmaxsbw vpmaxsbl vpmaxsbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmaxsw vpmaxswb vpmaxsww vpmaxswl vpmaxswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmaxsd vpmaxsdb vpmaxsdw vpmaxsdl vpmaxsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmaxub vpmaxubb vpmaxubw vpmaxubl vpmaxubq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmaxuw vpmaxuwb vpmaxuww vpmaxuwl vpmaxuwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmaxud vpmaxudb vpmaxudw vpmaxudl vpmaxudq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpminsb vpminsbb vpminsbw vpminsbl vpminsbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpminsw vpminswb vpminsww vpminswl vpminswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpminsd vpminsdb vpminsdw vpminsdl vpminsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpminub vpminubb vpminubw vpminubl vpminubq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpminuw vpminuwb vpminuww vpminuwl vpminuwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpminud vpminudb vpminudw vpminudl vpminudq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovmskb" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovsxbw vpmovsxbwb vpmovsxbww vpmovsxbwl vpmovsxbwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovsxbd vpmovsxbdb vpmovsxbdw vpmovsxbdl vpmovsxbdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovsxbq vpmovsxbqb vpmovsxbqw vpmovsxbql vpmovsxbqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovsxwd vpmovsxwdb vpmovsxwdw vpmovsxwdl vpmovsxwdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovsxwq vpmovsxwqb vpmovsxwqw vpmovsxwql vpmovsxwqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovsxdq vpmovsxdqb vpmovsxdqw vpmovsxdql vpmovsxdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovzxbw vpmovzxbwb vpmovzxbww vpmovzxbwl vpmovzxbwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovzxbd vpmovzxbdb vpmovzxbdw vpmovzxbdl vpmovzxbdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovzxbq vpmovzxbqb vpmovzxbqw vpmovzxbql vpmovzxbqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovzxwd vpmovzxwdb vpmovzxwdw vpmovzxwdl vpmovzxwdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovzxwq vpmovzxwqb vpmovzxwqw vpmovzxwql vpmovzxwqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmovzxdq vpmovzxdqb vpmovzxdqw vpmovzxdql vpmovzxdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmulhuw vpmulhuwb vpmulhuww vpmulhuwl vpmulhuwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmulhrsw vpmulhrswb vpmulhrsww vpmulhrswl vpmulhrswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmulhw vpmulhwb vpmulhww vpmulhwl vpmulhwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmullw vpmullwb vpmullww vpmullwl vpmullwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmulld vpmulldb vpmulldw vpmulldl vpmulldq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmuludq vpmuludqb vpmuludqw vpmuludql vpmuludqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpmuldq vpmuldqb vpmuldqw vpmuldql vpmuldqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpor vporb vporw vporl vporq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsadbw vpsadbwb vpsadbww vpsadbwl vpsadbwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpshufb vpshufbb vpshufbw vpshufbl vpshufbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpshufd vpshufdb vpshufdw vpshufdl vpshufdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpshufhw vpshufhwb vpshufhww vpshufhwl vpshufhwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpshuflw vpshuflwb vpshuflww vpshuflwl vpshuflwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsignb vpsignbb vpsignbw vpsignbl vpsignbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsignw vpsignwb vpsignww vpsignwl vpsignwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsignd vpsigndb vpsigndw vpsigndl vpsigndq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpslldq vpslldqb vpslldqw vpslldql vpslldqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsrldq vpsrldqb vpsrldqw vpsrldql vpsrldqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsllw vpsllwb vpsllww vpsllwl vpsllwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpslld vpslldb vpslldw vpslldl vpslldq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsllq vpsllqb vpsllqw vpsllql vpsllqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsraw vpsrawb vpsraww vpsrawl vpsrawq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsrad vpsradb vpsradw vpsradl vpsradq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsrlw vpsrlwb vpsrlww vpsrlwl vpsrlwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsrld vpsrldb vpsrldw vpsrldl vpsrldq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsrlq vpsrlqb vpsrlqw vpsrlql vpsrlqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vptest vptestb vptestw vptestl vptestq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsubb vpsubbb vpsubbw vpsubbl vpsubbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsubw vpsubwb vpsubww vpsubwl vpsubwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsubd vpsubdb vpsubdw vpsubdl vpsubdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsubq vpsubqb vpsubqw vpsubql vpsubqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsubsb vpsubsbb vpsubsbw vpsubsbl vpsubsbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsubsw vpsubswb vpsubsww vpsubswl vpsubswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsubusb vpsubusbb vpsubusbw vpsubusbl vpsubusbq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpsubusw vpsubuswb vpsubusww vpsubuswl vpsubuswq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpunpckhbw vpunpckhbwb vpunpckhbww vpunpckhbwl vpunpckhbwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpunpckhwd vpunpckhwdb vpunpckhwdw vpunpckhwdl vpunpckhwdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpunpckhdq vpunpckhdqb vpunpckhdqw vpunpckhdql vpunpckhdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpunpckhqdq vpunpckhqdqb vpunpckhqdqw vpunpckhqdql vpunpckhqdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpunpcklbw vpunpcklbwb vpunpcklbww vpunpcklbwl vpunpcklbwq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpunpcklwd vpunpcklwdb vpunpcklwdw vpunpcklwdl vpunpcklwdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpunpckldq vpunpckldqb vpunpckldqw vpunpckldql vpunpckldqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpunpcklqdq vpunpcklqdqb vpunpcklqdqw vpunpcklqdql vpunpcklqdqq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vpxor vpxorb vpxorw vpxorl vpxorq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vrcpps vrcppsb vrcppsw vrcppsl vrcppsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vrcpss vrcpssb vrcpssw vrcpssl vrcpssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vrsqrtps vrsqrtpsb vrsqrtpsw vrsqrtpsl vrsqrtpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vrsqrtss vrsqrtssb vrsqrtssw vrsqrtssl vrsqrtssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vroundpd vroundpdb vroundpdw vroundpdl vroundpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vroundps vroundpsb vroundpsw vroundpsl vroundpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vroundsd vroundsdb vroundsdw vroundsdl vroundsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vroundss vroundssb vroundssw vroundssl vroundssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vshufpd vshufpdb vshufpdw vshufpdl vshufpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vshufps vshufpsb vshufpsw vshufpsl vshufpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vsqrtpd vsqrtpdb vsqrtpdw vsqrtpdl vsqrtpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vsqrtps vsqrtpsb vsqrtpsw vsqrtpsl vsqrtpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vsqrtsd vsqrtsdb vsqrtsdw vsqrtsdl vsqrtsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vsqrtss vsqrtssb vsqrtssw vsqrtssl vsqrtssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vstmxcsr vstmxcsrb vstmxcsrw vstmxcsrl vstmxcsrq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vsubpd vsubpdb vsubpdw vsubpdl vsubpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vsubps vsubpsb vsubpsw vsubpsl vsubpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vsubsd vsubsdb vsubsdw vsubsdl vsubsdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vsubss vsubssb vsubssw vsubssl vsubssq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vtestps vtestpsb vtestpsw vtestpsl vtestpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vtestpd vtestpdb vtestpdw vtestpdl vtestpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vucomisd vucomisdb vucomisdw vucomisdl vucomisdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vucomiss vucomissb vucomissw vucomissl vucomissq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vunpckhpd vunpckhpdb vunpckhpdw vunpckhpdl vunpckhpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vunpckhps vunpckhpsb vunpckhpsw vunpckhpsl vunpckhpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vunpcklpd vunpcklpdb vunpcklpdw vunpcklpdl vunpcklpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vunpcklps vunpcklpsb vunpcklpsw vunpcklpsl vunpcklpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vxorpd vxorpdb vxorpdw vxorpdl vxorpdq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vxorps vxorpsb vxorpsw vxorpsl vxorpsq" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vzeroall" | |
| Opcode_SANDYBRIDGE_AVX="${Opcode_SANDYBRIDGE_AVX} vzeroupper" | |
| # AMD Enhanced 3DNow! (Athlon) instructions | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pf2iw pf2iwb pf2iww pf2iwl pf2iwq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfnacc pfnaccb pfnaccw pfnaccl pfnaccq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pfpnacc pfpnaccb pfpnaccw pfpnaccl pfpnaccq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pi2fw pi2fwb pi2fww pi2fwl pi2fwq" | |
| Opcode_ATHLON_3DNOW="${Opcode_ATHLON_3DNOW} pswapd pswapdb pswapdw pswapdl pswapdq" | |
| # Penryn New Instructions (SSE4.1) | |
| Opcode_SSE41="${Opcode_SSE41} blendpd blendpdb blendpdw blendpdl blendpdq" | |
| Opcode_SSE41="${Opcode_SSE41} blendps blendpsb blendpsw blendpsl blendpsq" | |
| Opcode_SSE41="${Opcode_SSE41} blendvpd blendvpdb blendvpdw blendvpdl blendvpdq" | |
| Opcode_SSE41="${Opcode_SSE41} blendvps blendvpsb blendvpsw blendvpsl blendvpsq" | |
| Opcode_SSE41="${Opcode_SSE41} dppd dppdb dppdw dppdl dppdq" | |
| Opcode_SSE41="${Opcode_SSE41} dpps dppsb dppsw dppsl dppsq" | |
| Opcode_X64_SSE41="${Opcode_X64_SSE41} extractps extractpsb extractpsw extractpsl extractpsq" | |
| Opcode_SSE41="${Opcode_SSE41} insertps insertpsb insertpsw insertpsl insertpsq" | |
| Opcode_SSE41="${Opcode_SSE41} movntdqa movntdqab movntdqaw movntdqal movntdqaq" | |
| Opcode_SSE41="${Opcode_SSE41} mpsadbw mpsadbwb mpsadbww mpsadbwl mpsadbwq" | |
| Opcode_SSE41="${Opcode_SSE41} packusdw packusdwb packusdww packusdwl packusdwq" | |
| Opcode_SSE41="${Opcode_SSE41} pblendvb pblendvbb pblendvbw pblendvbl pblendvbq" | |
| Opcode_SSE41="${Opcode_SSE41} pblendw pblendwb pblendww pblendwl pblendwq" | |
| Opcode_SSE41="${Opcode_SSE41} pcmpeqq pcmpeqqb pcmpeqqw pcmpeqql pcmpeqqq" | |
| Opcode_X64_SSE41="${Opcode_X64_SSE41} pextrb pextrbb pextrbw pextrbl pextrbq" | |
| Opcode_SSE41="${Opcode_SSE41} pextrd pextrdb pextrdw pextrdl pextrdq" | |
| Opcode_X64_SSE41="${Opcode_X64_SSE41} pextrq pextrqb pextrqw pextrql pextrqq" | |
| Opcode_X64_SSE41="${Opcode_X64_SSE41} pextrw pextrwb pextrww pextrwl pextrwq" | |
| Opcode_SSE41="${Opcode_SSE41} phminposuw phminposuwb phminposuww phminposuwl phminposuwq" | |
| Opcode_SSE41="${Opcode_SSE41} pinsrb pinsrbb pinsrbw pinsrbl pinsrbq" | |
| Opcode_SSE41="${Opcode_SSE41} pinsrd pinsrdb pinsrdw pinsrdl pinsrdq" | |
| Opcode_X64_SSE41="${Opcode_X64_SSE41} pinsrq pinsrqb pinsrqw pinsrql pinsrqq" | |
| Opcode_SSE41="${Opcode_SSE41} pmaxsb pmaxsbb pmaxsbw pmaxsbl pmaxsbq" | |
| Opcode_SSE41="${Opcode_SSE41} pmaxsd pmaxsdb pmaxsdw pmaxsdl pmaxsdq" | |
| Opcode_SSE41="${Opcode_SSE41} pmaxud pmaxudb pmaxudw pmaxudl pmaxudq" | |
| Opcode_SSE41="${Opcode_SSE41} pmaxuw pmaxuwb pmaxuww pmaxuwl pmaxuwq" | |
| Opcode_SSE41="${Opcode_SSE41} pminsb pminsbb pminsbw pminsbl pminsbq" | |
| Opcode_SSE41="${Opcode_SSE41} pminsd pminsdb pminsdw pminsdl pminsdq" | |
| Opcode_SSE41="${Opcode_SSE41} pminud pminudb pminudw pminudl pminudq" | |
| Opcode_SSE41="${Opcode_SSE41} pminuw pminuwb pminuww pminuwl pminuwq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovsxbw pmovsxbwb pmovsxbww pmovsxbwl pmovsxbwq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovsxbd pmovsxbdb pmovsxbdw pmovsxbdl pmovsxbdq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovsxbq pmovsxbqb pmovsxbqw pmovsxbql pmovsxbqq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovsxwd pmovsxwdb pmovsxwdw pmovsxwdl pmovsxwdq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovsxwq pmovsxwqb pmovsxwqw pmovsxwql pmovsxwqq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovsxdq pmovsxdqb pmovsxdqw pmovsxdql pmovsxdqq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovzxbw pmovzxbwb pmovzxbww pmovzxbwl pmovzxbwq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovzxbd pmovzxbdb pmovzxbdw pmovzxbdl pmovzxbdq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovzxbq pmovzxbqb pmovzxbqw pmovzxbql pmovzxbqq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovzxwd pmovzxwdb pmovzxwdw pmovzxwdl pmovzxwdq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovzxwq pmovzxwqb pmovzxwqw pmovzxwql pmovzxwqq" | |
| Opcode_SSE41="${Opcode_SSE41} pmovzxdq pmovzxdqb pmovzxdqw pmovzxdql pmovzxdqq" | |
| Opcode_SSE41="${Opcode_SSE41} pmuldq pmuldqb pmuldqw pmuldql pmuldqq" | |
| Opcode_SSE41="${Opcode_SSE41} pmulld pmulldb pmulldw pmulldl pmulldq" | |
| Opcode_SSE41="${Opcode_SSE41} ptest ptestb ptestw ptestl ptestq" | |
| Opcode_SSE41="${Opcode_SSE41} roundpd roundpdb roundpdw roundpdl roundpdq" | |
| Opcode_SSE41="${Opcode_SSE41} roundps roundpsb roundpsw roundpsl roundpsq" | |
| Opcode_SSE41="${Opcode_SSE41} roundsd roundsdb roundsdw roundsdl roundsdq" | |
| Opcode_SSE41="${Opcode_SSE41} roundss roundssb roundssw roundssl roundssq" | |
| # AMD SSE4A | |
| Opcode_AMD_SSE4A="${Opcode_AMD_SSE4A} extrq" | |
| Opcode_AMD_SSE4A="${Opcode_AMD_SSE4A} insertq" | |
| Opcode_AMD_SSE4A="${Opcode_AMD_SSE4A} movntsd movntsdb movntsdw movntsdl movntsdq" | |
| Opcode_AMD_SSE4A="${Opcode_AMD_SSE4A} movntss movntssb movntssw movntssl movntssq" | |
| # GAS-specific opcodes (unofficial names) belonging to the x64 instruction set. | |
| # They are generated by GNU tools (e.g. GDB, objdump) and specify a variant of ordinal opcodes like NOP and MOV. | |
| # If you do not want these opcodes to be recognized by this script, comment out the following line. | |
| Opcode_X64_GAS="nopw nopl movabs" | |
| # instruction sets | |
| InstSet_X86="8086_Base 186_Base 286_Base 386_Base 486_Base PENT_Base P6_Base KATMAI_Base WILLAMETTE_Base PENTM_Base" | |
| InstSet_IA64="IA64_Base" | |
| InstSet_X64="PRESCOTT_Base X64_Base X86_64_Base NEHALEM_Base X64_GAS" | |
| InstSet_MMX="PENT_MMX KATMAI_MMX X64_MMX" | |
| InstSet_MMX2="KATMAI_MMX2" | |
| InstSet_3DNOW="ATHLON_3DNOW" | |
| InstSet_SSE="KATMAI_SSE P6_SSE X64_SSE" | |
| InstSet_SSE2="SSE2 X64_SSE2" | |
| InstSet_SSE3="PRESCOTT_SSE3" | |
| InstSet_SSSE3="SSSE3" | |
| InstSet_VMX="VMX X64_VMX" | |
| InstSet_SSE4_1="SSE41 X64_SSE41" | |
| InstSet_SSE4_2="SSE42 X64_SSE42" | |
| InstSet_SSE4A="AMD_SSE4A" | |
| InstSet_SSE5="AMD_SSE5" | |
| InstSet_FMA="FUTURE_FMA" | |
| InstSet_AVX="SANDYBRIDGE_AVX" | |
| InstSetDep_X64="X86" | |
| InstSetDep_MMX2="MMX" | |
| InstSetDep_SSE2="SSE" | |
| InstSetDep_SSE3="SSE2" | |
| InstSetDep_SSSE3="SSE3" | |
| InstSetDep_SSE4_1="SSSE3" | |
| InstSetDep_SSE4_2="SSE4_1" | |
| InstSetDep_SSE4A="SSE3" | |
| InstSetDep_SSE5="FMA AVX" # FIXME not reliable | |
| InstSetList="X86 IA64 X64 MMX MMX2 3DNOW SSE SSE2 SSE3 SSSE3 VMX SSE4_1 SSE4_2 SSE4A SSE5 FMA AVX" | |
| # architectures | |
| Arch_8086="8086_Base" | |
| Arch_186="186_Base" | |
| Arch_286="286_Base" | |
| Arch_386="386_Base" | |
| Arch_486="486_Base" | |
| Arch_Pentium="PENT_Base PENT_MMX" # Pentium = P5 architecture | |
| Arch_Athlon="ATHLON_3DNOW" | |
| Arch_Deschutes="P6_Base P6_SSE" # Pentium II | |
| Arch_Katmai="KATMAI_Base KATMAI_MMX KATMAI_MMX2 KATMAI_SSE" # Pentium III | |
| Arch_Willamette="WILLAMETTE_Base SSE2" # original Pentium IV (x86) | |
| Arch_PentiumM="PENTM_Base" | |
| Arch_Prescott="PRESCOTT_Base X64_Base X86_64_Base X64_SSE2 PRESCOTT_SSE3 VMX X64_VMX X64_GAS" # later Pentium IV (x64) with SSE3 (Willamette only implemented SSE2 instructions) and VT (VT-x, aka VMX) | |
| Arch_P6="" | |
| Arch_Barcelona="ATHLON_3DNOW AMD_SSE4A" | |
| Arch_IA64="IA64_Base" # 64-bit Itanium RISC processor; incompatible with x64 architecture | |
| Arch_Penryn="SSSE3 SSE41 X64_SSE41" # later (45nm) Core 2 with SSE4.1 | |
| Arch_Nehalem="NEHALEM_Base SSE42 X64_SSE42" # Core i# | |
| Arch_SandyBridge="SANDYBRIDGE_AVX" | |
| Arch_Haswell="FUTURE_FMA" | |
| Arch_Bulldozer="AMD_SSE5" | |
| ArchDep_8086="" | |
| ArchDep_186="8086" | |
| ArchDep_286="186" | |
| ArchDep_386="286" | |
| ArchDep_486="386" | |
| ArchDep_Pentium="486" | |
| ArchDep_Athlon="Pentium" # FIXME not reliable | |
| ArchDep_Deschutes="Pentium" | |
| ArchDep_Katmai="Deschutes" | |
| ArchDep_Willamette="Katmai" | |
| ArchDep_PentiumM="Willamette" # FIXME Pentium M is a Pentium III modification (with SSE2). Does it support also WILLAMETTE_Base instructions? | |
| ArchDep_Prescott="Willamette" | |
| ArchDep_P6="Prescott" # P6 started with Pentium Pro; FIXME Pentium Pro did not support MMX instructions (introduced again in Pentium II aka Deschutes) | |
| ArchDep_Barcelona="Prescott" # FIXME not reliable | |
| ArchDep_IA64="" | |
| ArchDep_Penryn="P6" | |
| ArchDep_Nehalem="Penryn" | |
| ArchDep_SandyBridge="Nehalem" | |
| ArchDep_Haswell="SandyBridge" | |
| ArchDep_Bulldozer="Haswell" # FIXME not reliable | |
| ArchList="8086 186 286 386 486 Pentium Athlon Deschutes Katmai Willamette PentiumM Prescott P6 Barcelona IA64 Penryn Nehalem SandyBridge Haswell Bulldozer" | |
| usage() { | |
| echo "Usage: $0 OPTIONS" | |
| echo "" | |
| echo " -r set instruction sets recursively according to dependency tree (must precede -a or -s)" | |
| echo " -a set architecture" | |
| echo " -s set instruction set" | |
| echo " -L show list of available architectures" | |
| echo " -l show list of available instruction sets" | |
| echo " -i show base instruction sets of current instruction set (requires -a and/or -s)" | |
| echo " -I show instructions in current instruction set (requires -a and/or -s)" | |
| echo " -c print number of matching instructions instead of normal output" | |
| echo " -f find instruction set of the following instruction (regex allowed)" | |
| echo " -d set leading opcode separator (default '$Leading_Separator')" | |
| echo " -D set trailing opcode separator (default '$Trailing_Separator')" | |
| echo " -C case-insensitive" | |
| echo " -v invert the sense of matching" | |
| echo " -V print all lines, not just the highlighted" | |
| echo " -m stop searching after n matched instructions" | |
| echo " -n print line numbers within the original input" | |
| echo " -B print n instructions of leading context" | |
| echo " -A print n instructions of trailing context" | |
| echo " -h print this help" | |
| echo | |
| echo "Multiple architectures and instruction sets can be used." | |
| echo | |
| echo "Typical usage is:" | |
| echo " objdump -M intel -d FILE | $0 OPTIONS" | |
| echo " objdump -M intel -d FILE | $0 -s SSE2 -s SSE3 -V Highlight SSE2 and SSE3 within FILE." | |
| echo " objdump -M intel -d FILE | tail -n +8 | $0 -r -a Haswell -v -m 1 Find first unknown instruction." | |
| echo " $0 -C -f ADDSD Find which instruction set an opcode belongs to." | |
| echo " $0 -f .*fma.* Find all matching instructions and their instruction sets." | |
| echo | |
| echo "The script uses Intel opcode syntax. When used in conjunction with objdump, \`-M intel' must be set in order to prevent opcode translation using AT&T syntax." | |
| echo | |
| echo "BE AWARE THAT THE LIST OF KNOWN INSTRUCTIONS OR INSTRUCTIONS SUPPORTED BY PARTICULAR ARCHITECTURES (ESPECIALLY AMD'S) IS ONLY TENTATIVE AND MAY CONTAIN MISTAKES!" | |
| kill -TRAP $TOP_PID | |
| } | |
| list_contains() { # Returns 0 if $2 is in array $1, 1 otherwise. | |
| local e | |
| for e in $1; do | |
| [ "$e" = "$2" ] && return 0 | |
| done | |
| return 1 | |
| } | |
| build_instruction_set() { # $1 = enum { Arch, InstSet }, $2 = architecture or instruction set as obtained using -L or -l, $3 = "architecture"/"instruction set" to be used in error message | |
| local e | |
| list_contains "`eval echo \\\$${1}List`" "$2" || (echo "$2 is not a valid $3."; usage) # Test if the architecture/instruction set is valid. | |
| if [ -n "`eval echo \\\$${1}_${2}`" ]; then # Add the instruction set(s) if any. | |
| for e in `eval echo \\\$${1}_${2}`; do # Skip duplicates. | |
| list_contains "$InstSet_Base" $e || InstSet_Base="$e $InstSet_Base" | |
| done | |
| fi | |
| if [ $Recursive = true ]; then | |
| for a in `eval echo \\\$${1}Dep_$2`; do | |
| build_instruction_set $1 $a "$3" | |
| done | |
| fi | |
| InstSet_Base="`echo $InstSet_Base | sed 's/$ *//'`" # Remove trailing space. | |
| } | |
| trap "exit $EXIT_USAGE" TRAP # Allow usage() function to abort script execution. | |
| export TOP_PID=$$ # PID of executing process. | |
| Target_File="" | |
| # Parse command line arguments. | |
| while getopts ":ra:s:LliIcS:f:Fd:D:CvVm:nB:A:h" o; do | |
| case $o in | |
| r) Recursive=true ;; | |
| a) build_instruction_set Arch "$OPTARG" "architecture" ;; | |
| s) build_instruction_set InstSet "$OPTARG" "instruction set" ;; | |
| L) echo $ArchList; exit $EXIT_USAGE ;; | |
| l) echo $InstSetList; exit $EXIT_USAGE ;; | |
| i) | |
| if [ -n "$InstSet_Base" ]; then | |
| echo $InstSet_Base | |
| exit $EXIT_USAGE | |
| else | |
| echo -e "No instruction set or architecture set.\n" | |
| usage | |
| fi | |
| ;; | |
| I) | |
| if [ -n "$InstSet_Base" ]; then | |
| for s in $InstSet_Base; do | |
| echo -ne "\e[31;1m$s:\e[0m " | |
| eval echo "\$Opcode_$s" | |
| done | |
| exit $EXIT_USAGE | |
| else | |
| echo -e "No instruction set or architecture set.\n" | |
| usage | |
| fi | |
| ;; | |
| c) Count_Matching=true ;; | |
| S) Build_Stats=true; Target_File="$OPTARG";; | |
| f) | |
| # Unlike architectures, instruction sets are disjoint. | |
| Found=false | |
| for s in $InstSetList; do | |
| for b in `eval echo \\\$InstSet_$s`; do | |
| Found_In_Base=false | |
| for i in `eval echo \\\$Opcode_$b`; do | |
| if [[ "$i" =~ ^$OPTARG$ ]]; then | |
| $Found_In_Base || echo -ne "Instruction set \e[33;1m$s\e[0m (base instruction set \e[32;1m$b\e[0m):" | |
| echo -ne " \e[31;1m$i\e[0m" | |
| Found_In_Base=true | |
| Found=true | |
| fi | |
| done | |
| $Found_In_Base && echo "" | |
| done | |
| done | |
| if [ $Found = false ]; then | |
| echo -e "Operation code \e[31;1m$OPTARG\e[0m has not been found in the database of known instructions." \ | |
| "Perhaps it is translated using other than Intel syntax. If obtained from objdump, check if the \`-M intel' flag is set." \ | |
| "Be aware that the search is case sensitive by default (you may use the -C flag, otherwise only lower case opcodes are accepted)." | |
| exit $EXIT_NOT_FOUND | |
| else | |
| exit $EXIT_FOUND | |
| fi | |
| ;; | |
| d) Leading_Separator="$OPTARG" ;; | |
| D) Trailing_Separator="$OPTARG" ;; | |
| C) Case_Insensitive=true ;; | |
| v) Invert=true ;; | |
| V) Verbose=true ;; | |
| m) Stop_After=$OPTARG ;; | |
| n) Line_Numbers=true ;; | |
| B) Leading_Context=$OPTARG ;; | |
| A) Trailing_Context=$OPTARG ;; | |
| h) usage ;; | |
| \?) | |
| echo -e "Unknown option: -$OPTARG\n" | |
| usage | |
| ;; | |
| esac | |
| done | |
| shift $((OPTIND-1)) | |
| [ -n "$1" ] && echo -e "Unknown command line parameter: $1\n" && usage | |
| [ -z "$InstSet_Base" ] && [[ $Build_Stats == false ]] && usage | |
| # Create list of grep parameters. | |
| Grep_Params="--color=auto -B $Leading_Context -A $Trailing_Context" | |
| [ $Count_Matching = true ] && Grep_Params="$Grep_Params -c" | |
| [ $Case_Insensitive = true ] && Grep_Params="$Grep_Params -i" | |
| [ $Invert = true ] && Grep_Params="$Grep_Params -v" | |
| [ $Stop_After -gt 0 ] && Grep_Params="$Grep_Params -m $Stop_After" | |
| [ $Line_Numbers = true ] && Grep_Params="$Grep_Params -n" | |
| # Build regular expression for use in grep. | |
| build_regex () { | |
| RegEx="" | |
| for s in $InstSet_Base; do | |
| eval RegEx=\"$RegEx \$Opcode_$s\" | |
| done | |
| # Add leading and trailing opcode separators to prevent false positives. | |
| RegEx="$Leading_Separator`echo $RegEx | sed "s/ /$(echo "$Trailing_Separator"|sed 's/[\/&]/\\\&/g')|$(echo "$Leading_Separator"|sed 's/[\/&]/\\\&/g')/g"`$Trailing_Separator" | |
| [ $Verbose = true -a $Count_Matching = false ] && RegEx="$RegEx|\$" | |
| } | |
| build_regex | |
| # The actual search | |
| if [[ $Build_Stats == true ]]; then | |
| Begin="" | |
| Body="" | |
| End="" | |
| for set in $InstSetList; do | |
| Begin+="c[\"$set\"]=0; " | |
| End+="printf(\"%-6s: %d\n\", \"$set\", c[\"$set\"]); " | |
| InstSet_Base="" | |
| RegEx="" | |
| build_instruction_set InstSet "$set" "instruction set" | |
| build_regex | |
| Body+="/$RegEx/ { ++c[\"$set\"]; } | |
| " | |
| done | |
| objdump -M intel -d "$Target_File" | awk "BEGIN{${Begin}} ${Body} END{${End}}" | |
| elif [ $Count_Matching = true ]; then | |
| awk 'BEGIN{ i=0; } /'"$RegEx"'/{i++;} END{ print i }' | |
| else | |
| grep $Grep_Params -E "$RegEx" && exit $EXIT_FOUND || exit $EXIT_NOT_FOUND | |
| fi |
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