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rindeal/cpuid-dump.c

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CPUID dumper
Raw
cpuid-dump.c
#if !defined(__GNUC__) || ((__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) < 40800)
# error "This program requires GNU C compiler v4.8+!"
#endif
#include <stdio.h>
#include <stdbool.h>
#define PRINT_TEST_CPU_SUPPORT_RESULT(inst) printf("\t%-7s: %d\n", inst, __builtin_cpu_supports(inst)?1:0)
#define PRINT_TEST_CPU_TYPE_RESULT(inst) printf("\t%-12s: %d\n", inst, __builtin_cpu_is(inst)?1:0)
void PrintCpuSupport(void)
{
printf("\nCPU instruction support:\n-------------------------\n");
PRINT_TEST_CPU_SUPPORT_RESULT("cmov");
PRINT_TEST_CPU_SUPPORT_RESULT("mmx");
PRINT_TEST_CPU_SUPPORT_RESULT("popcnt");
PRINT_TEST_CPU_SUPPORT_RESULT("sse");
PRINT_TEST_CPU_SUPPORT_RESULT("sse2");
PRINT_TEST_CPU_SUPPORT_RESULT("sse3");
PRINT_TEST_CPU_SUPPORT_RESULT("ssse3");
PRINT_TEST_CPU_SUPPORT_RESULT("sse4.1");
PRINT_TEST_CPU_SUPPORT_RESULT("sse4.2");
PRINT_TEST_CPU_SUPPORT_RESULT("avx");
PRINT_TEST_CPU_SUPPORT_RESULT("avx2");
}
void PrintCpuType(void)
{
printf("\nCPU type:\n-------------------------\n");
PRINT_TEST_CPU_TYPE_RESULT("intel");
PRINT_TEST_CPU_TYPE_RESULT("atom");
PRINT_TEST_CPU_TYPE_RESULT("core2");
PRINT_TEST_CPU_TYPE_RESULT("corei7");
PRINT_TEST_CPU_TYPE_RESULT("nehalem");
PRINT_TEST_CPU_TYPE_RESULT("westmere");
PRINT_TEST_CPU_TYPE_RESULT("sandybridge");
PRINT_TEST_CPU_TYPE_RESULT("amd");
PRINT_TEST_CPU_TYPE_RESULT("amdfam10h");
PRINT_TEST_CPU_TYPE_RESULT("barcelona");
PRINT_TEST_CPU_TYPE_RESULT("shanghai");
PRINT_TEST_CPU_TYPE_RESULT("istanbul");
PRINT_TEST_CPU_TYPE_RESULT("btver1");
PRINT_TEST_CPU_TYPE_RESULT("amdfam15h");
PRINT_TEST_CPU_TYPE_RESULT("bdver1");
PRINT_TEST_CPU_TYPE_RESULT("bdver2");
PRINT_TEST_CPU_TYPE_RESULT("bdver3");
PRINT_TEST_CPU_TYPE_RESULT("bdver4");
PRINT_TEST_CPU_TYPE_RESULT("btver2");
}
bool
avx_os_support (void)
{
unsigned int eax, edx;
__asm__ ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
return (eax & 6) == 6;
}
void
PrintOsSupport(void)
{
printf("\nOS support:\n-------------------------\n");
printf("\t%-5s: %d\n", "avx", avx_os_support());
}
int main(void)
{
// freopen("env_info.txt", "w", stdout);
PrintCpuSupport();
PrintCpuType();
PrintOsSupport();
return 0;
}
Raw
cpuid-dump2.c
// this version works for GCC < 4.8
#include <stdio.h>
/* Definitions for option handling for IA-32.
Copyright (C) 1988-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef I386_OPTS_H
#define I386_OPTS_H
/* Algorithm to expand string function with. */
enum stringop_alg
{
#undef DEF_ENUM
#define DEF_ENUM
#undef DEF_ALG
#define DEF_ALG(alg, name) alg,
/* Definitions for stringop strategy for IA-32.
Copyright (C) 2013-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the files COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
DEF_ENUM
DEF_ALG (no_stringop, no_stringop)
DEF_ENUM
DEF_ALG (libcall, libcall)
DEF_ENUM
DEF_ALG (rep_prefix_1_byte, rep_byte)
DEF_ENUM
DEF_ALG (rep_prefix_4_byte, rep_4byte)
DEF_ENUM
DEF_ALG (rep_prefix_8_byte, rep_8byte)
DEF_ENUM
DEF_ALG (loop_1_byte, byte_loop)
DEF_ENUM
DEF_ALG (loop, loop)
DEF_ENUM
DEF_ALG (unrolled_loop, unrolled_loop)
DEF_ENUM
DEF_ALG (vector_loop, vector_loop)
last_alg
#undef DEF_ENUM
#undef DEF_ALG
};
/* Available call abi. */
enum calling_abi
{
SYSV_ABI = 0,
MS_ABI = 1
};
enum fpmath_unit
{
FPMATH_387 = 1,
FPMATH_SSE = 2
};
enum tls_dialect
{
TLS_DIALECT_GNU,
TLS_DIALECT_GNU2,
TLS_DIALECT_SUN
};
enum cmodel {
CM_32, /* The traditional 32-bit ABI. */
CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
CM_LARGE, /* No assumptions. */
CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
CM_LARGE_PIC /* No assumptions. */
};
enum pmode {
PMODE_SI, /* Pmode == SImode. */
PMODE_DI /* Pmode == DImode. */
};
enum ix86_align_data {
ix86_align_data_type_compat,
ix86_align_data_type_abi,
ix86_align_data_type_cacheline
};
enum asm_dialect {
ASM_ATT,
ASM_INTEL
};
enum ix86_veclibabi {
ix86_veclibabi_type_none,
ix86_veclibabi_type_svml,
ix86_veclibabi_type_acml
};
enum stack_protector_guard {
SSP_TLS, /* per-thread canary in TLS block */
SSP_GLOBAL /* global canary */
};
#endif
// #include <cpuid.h>
/*
* Copyright (C) 2007-2015 Free Software Foundation, Inc.
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* %ecx */
#define bit_SSE3 (1 << 0)
#define bit_PCLMUL (1 << 1)
#define bit_LZCNT (1 << 5)
#define bit_SSSE3 (1 << 9)
#define bit_FMA (1 << 12)
#define bit_CMPXCHG16B (1 << 13)
#define bit_SSE4_1 (1 << 19)
#define bit_SSE4_2 (1 << 20)
#define bit_MOVBE (1 << 22)
#define bit_POPCNT (1 << 23)
#define bit_AES (1 << 25)
#define bit_XSAVE (1 << 26)
#define bit_OSXSAVE (1 << 27)
#define bit_AVX (1 << 28)
#define bit_F16C (1 << 29)
#define bit_RDRND (1 << 30)
/* %edx */
#define bit_CMPXCHG8B (1 << 8)
#define bit_CMOV (1 << 15)
#define bit_MMX (1 << 23)
#define bit_FXSAVE (1 << 24)
#define bit_SSE (1 << 25)
#define bit_SSE2 (1 << 26)
/* Extended Features */
/* %ecx */
#define bit_LAHF_LM (1 << 0)
#define bit_ABM (1 << 5)
#define bit_SSE4a (1 << 6)
#define bit_PRFCHW (1 << 8)
#define bit_XOP (1 << 11)
#define bit_LWP (1 << 15)
#define bit_FMA4 (1 << 16)
#define bit_TBM (1 << 21)
/* %edx */
#define bit_MMXEXT (1 << 22)
#define bit_LM (1 << 29)
#define bit_3DNOWP (1 << 30)
#define bit_3DNOW (1 << 31)
/* Extended Features (%eax == 7) */
/* %ebx */
#define bit_FSGSBASE (1 << 0)
#define bit_BMI (1 << 3)
#define bit_HLE (1 << 4)
#define bit_AVX2 (1 << 5)
#define bit_BMI2 (1 << 8)
#define bit_RTM (1 << 11)
#define bit_MPX (1 << 14)
#define bit_AVX512F (1 << 16)
#define bit_AVX512DQ (1 << 17)
#define bit_RDSEED (1 << 18)
#define bit_ADX (1 << 19)
#define bit_AVX512IFMA (1 << 21)
#define bit_PCOMMIT (1 << 22)
#define bit_CLFLUSHOPT (1 << 23)
#define bit_CLWB (1 << 24)
#define bit_AVX512PF (1 << 26)
#define bit_AVX512ER (1 << 27)
#define bit_AVX512CD (1 << 28)
#define bit_SHA (1 << 29)
#define bit_AVX512BW (1 << 30)
#define bit_AVX512VL (1 << 31)
/* %ecx */
#define bit_PREFETCHWT1 (1 << 0)
#define bit_AVX512VBMI (1 << 1)
/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
#define bit_BNDREGS (1 << 3)
#define bit_BNDCSR (1 << 4)
/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
#define bit_XSAVEOPT (1 << 0)
#define bit_XSAVEC (1 << 1)
#define bit_XSAVES (1 << 3)
/* Signatures for different CPU implementations as returned in uses
of cpuid with level 0. */
#define signature_AMD_ebx 0x68747541
#define signature_AMD_ecx 0x444d4163
#define signature_AMD_edx 0x69746e65
#define signature_CENTAUR_ebx 0x746e6543
#define signature_CENTAUR_ecx 0x736c7561
#define signature_CENTAUR_edx 0x48727561
#define signature_CYRIX_ebx 0x69727943
#define signature_CYRIX_ecx 0x64616574
#define signature_CYRIX_edx 0x736e4978
#define signature_INTEL_ebx 0x756e6547
#define signature_INTEL_ecx 0x6c65746e
#define signature_INTEL_edx 0x49656e69
#define signature_TM1_ebx 0x6e617254
#define signature_TM1_ecx 0x55504361
#define signature_TM1_edx 0x74656d73
#define signature_TM2_ebx 0x756e6547
#define signature_TM2_ecx 0x3638784d
#define signature_TM2_edx 0x54656e69
#define signature_NSC_ebx 0x646f6547
#define signature_NSC_ecx 0x43534e20
#define signature_NSC_edx 0x79622065
#define signature_NEXGEN_ebx 0x4778654e
#define signature_NEXGEN_ecx 0x6e657669
#define signature_NEXGEN_edx 0x72446e65
#define signature_RISE_ebx 0x65736952
#define signature_RISE_ecx 0x65736952
#define signature_RISE_edx 0x65736952
#define signature_SIS_ebx 0x20536953
#define signature_SIS_ecx 0x20536953
#define signature_SIS_edx 0x20536953
#define signature_UMC_ebx 0x20434d55
#define signature_UMC_ecx 0x20434d55
#define signature_UMC_edx 0x20434d55
#define signature_VIA_ebx 0x20414956
#define signature_VIA_ecx 0x20414956
#define signature_VIA_edx 0x20414956
#define signature_VORTEX_ebx 0x74726f56
#define signature_VORTEX_ecx 0x436f5320
#define signature_VORTEX_edx 0x36387865
#define __cpuid(level, a, b, c, d) \
__asm__ ("cpuid\n\t" \
: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
: "0" (level))
#define __cpuid_count(level, count, a, b, c, d) \
__asm__ ("cpuid\n\t" \
: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
: "0" (level), "2" (count))
/* Return highest supported input value for cpuid instruction. ext can
be either 0x0 or 0x8000000 to return highest supported value for
basic or extended cpuid information. Function returns 0 if cpuid
is not supported or whatever cpuid returns in eax register. If sig
pointer is non-null, then first four bytes of the signature
(as found in ebx register) are returned in location pointed by sig. */
static __inline unsigned int
__get_cpuid_max (unsigned int __ext, unsigned int *__sig)
{
unsigned int __eax, __ebx, __ecx, __edx;
#ifndef __x86_64__
/* See if we can use cpuid. On AMD64 we always can. */
#if __GNUC__ >= 3
__asm__ ("pushf{l|d}\n\t"
"pushf{l|d}\n\t"
"pop{l}\t%0\n\t"
"mov{l}\t{%0, %1|%1, %0}\n\t"
"xor{l}\t{%2, %0|%0, %2}\n\t"
"push{l}\t%0\n\t"
"popf{l|d}\n\t"
"pushf{l|d}\n\t"
"pop{l}\t%0\n\t"
"popf{l|d}\n\t"
: "=&r" (__eax), "=&r" (__ebx)
: "i" (0x00200000));
#else
/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
nor alternatives in i386 code. */
__asm__ ("pushfl\n\t"
"pushfl\n\t"
"popl\t%0\n\t"
"movl\t%0, %1\n\t"
"xorl\t%2, %0\n\t"
"pushl\t%0\n\t"
"popfl\n\t"
"pushfl\n\t"
"popl\t%0\n\t"
"popfl\n\t"
: "=&r" (__eax), "=&r" (__ebx)
: "i" (0x00200000));
#endif
if (!((__eax ^ __ebx) & 0x00200000))
return 0;
#endif
/* Host supports cpuid. Return highest supported cpuid input value. */
__cpuid (__ext, __eax, __ebx, __ecx, __edx);
if (__sig)
*__sig = __ebx;
return __eax;
}
/* Return cpuid data for requested cpuid level, as found in returned
eax, ebx, ecx and edx registers. The function checks if cpuid is
supported and returns 1 for valid cpuid information or 0 for
unsupported cpuid level. All pointers are required to be non-null. */
static __inline int
__get_cpuid (unsigned int __level,
unsigned int *__eax, unsigned int *__ebx,
unsigned int *__ecx, unsigned int *__edx)
{
unsigned int __ext = __level & 0x80000000;
if (__get_cpuid_max (__ext, 0) < __level)
return 0;
__cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
return 1;
}
/* Definitions of target machine for GCC for IA-32.
Copyright (C) 1988-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* The purpose of this file is to define the characteristics of the i386,
independent of assembler syntax or operating system.
Three other files build on this one to describe a specific assembler syntax:
bsd386.h, att386.h, and sun386.h.
The actual tm.h file for a particular system should include
this file, and then the file for the appropriate assembler syntax.
Many macros that specify assembler syntax are omitted entirely from
this file because they really belong in the files for particular
assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
that start with ASM_ or end in ASM_OP. */
/* Redefines for option macros. */
#define TARGET_64BIT TARGET_ISA_64BIT
#define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x)
#define TARGET_MMX TARGET_ISA_MMX
#define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x)
#define TARGET_3DNOW TARGET_ISA_3DNOW
#define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x)
#define TARGET_3DNOW_A TARGET_ISA_3DNOW_A
#define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x)
#define TARGET_SSE TARGET_ISA_SSE
#define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x)
#define TARGET_SSE2 TARGET_ISA_SSE2
#define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x)
#define TARGET_SSE3 TARGET_ISA_SSE3
#define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x)
#define TARGET_SSSE3 TARGET_ISA_SSSE3
#define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x)
#define TARGET_SSE4_1 TARGET_ISA_SSE4_1
#define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x)
#define TARGET_SSE4_2 TARGET_ISA_SSE4_2
#define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x)
#define TARGET_AVX TARGET_ISA_AVX
#define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x)
#define TARGET_AVX2 TARGET_ISA_AVX2
#define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x)
#define TARGET_AVX512F TARGET_ISA_AVX512F
#define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x)
#define TARGET_AVX512PF TARGET_ISA_AVX512PF
#define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x)
#define TARGET_AVX512ER TARGET_ISA_AVX512ER
#define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x)
#define TARGET_AVX512CD TARGET_ISA_AVX512CD
#define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x)
#define TARGET_AVX512DQ TARGET_ISA_AVX512DQ
#define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x)
#define TARGET_AVX512BW TARGET_ISA_AVX512BW
#define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x)
#define TARGET_AVX512VL TARGET_ISA_AVX512VL
#define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x)
#define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI
#define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x)
#define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA
#define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x)
#define TARGET_FMA TARGET_ISA_FMA
#define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x)
#define TARGET_SSE4A TARGET_ISA_SSE4A
#define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x)
#define TARGET_FMA4 TARGET_ISA_FMA4
#define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x)
#define TARGET_XOP TARGET_ISA_XOP
#define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x)
#define TARGET_LWP TARGET_ISA_LWP
#define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x)
#define TARGET_ROUND TARGET_ISA_ROUND
#define TARGET_ABM TARGET_ISA_ABM
#define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x)
#define TARGET_BMI TARGET_ISA_BMI
#define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x)
#define TARGET_BMI2 TARGET_ISA_BMI2
#define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x)
#define TARGET_LZCNT TARGET_ISA_LZCNT
#define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x)
#define TARGET_TBM TARGET_ISA_TBM
#define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x)
#define TARGET_POPCNT TARGET_ISA_POPCNT
#define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x)
#define TARGET_SAHF TARGET_ISA_SAHF
#define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x)
#define TARGET_MOVBE TARGET_ISA_MOVBE
#define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x)
#define TARGET_CRC32 TARGET_ISA_CRC32
#define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x)
#define TARGET_AES TARGET_ISA_AES
#define TARGET_AES_P(x) TARGET_ISA_AES_P(x)
#define TARGET_SHA TARGET_ISA_SHA
#define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x)
#define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT
#define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x)
#define TARGET_XSAVEC TARGET_ISA_XSAVEC
#define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x)
#define TARGET_XSAVES TARGET_ISA_XSAVES
#define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x)
#define TARGET_PCLMUL TARGET_ISA_PCLMUL
#define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x)
#define TARGET_CMPXCHG16B TARGET_ISA_CX16
#define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x)
#define TARGET_FSGSBASE TARGET_ISA_FSGSBASE
#define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x)
#define TARGET_RDRND TARGET_ISA_RDRND
#define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x)
#define TARGET_F16C TARGET_ISA_F16C
#define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x)
#define TARGET_RTM TARGET_ISA_RTM
#define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x)
#define TARGET_HLE TARGET_ISA_HLE
#define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x)
#define TARGET_RDSEED TARGET_ISA_RDSEED
#define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x)
#define TARGET_PRFCHW TARGET_ISA_PRFCHW
#define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x)
#define TARGET_ADX TARGET_ISA_ADX
#define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x)
#define TARGET_FXSR TARGET_ISA_FXSR
#define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x)
#define TARGET_XSAVE TARGET_ISA_XSAVE
#define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x)
#define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT
#define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x)
#define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1
#define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x)
#define TARGET_MPX TARGET_ISA_MPX
#define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x)
#define TARGET_PCOMMIT TARGET_ISA_PCOMMIT
#define TARGET_PCOMMIT_P(x) TARGET_ISA_PCOMMIT_P(x)
#define TARGET_CLWB TARGET_ISA_CLWB
#define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x)
#define TARGET_LP64 TARGET_ABI_64
#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
#define TARGET_X32 TARGET_ABI_X32
#define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
#define TARGET_16BIT TARGET_CODE16
#define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
/* SSE4.1 defines round instructions */
#define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1
#define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
// #include "config/vxworks-dummy.h"
// #include "config/i386/i386-opts.h"
#define MAX_STRINGOP_ALGS 4
/* Specify what algorithm to use for stringops on known size.
When size is unknown, the UNKNOWN_SIZE alg is used. When size is
known at compile time or estimated via feedback, the SIZE array
is walked in order until MAX is greater then the estimate (or -1
means infinity). Corresponding ALG is used then.
When NOALIGN is true the code guaranting the alignment of the memory
block is skipped.
For example initializer:
{{256, loop}, {-1, rep_prefix_4_byte}}
will use loop for blocks smaller or equal to 256 bytes, rep prefix will
be used otherwise. */
struct stringop_algs
{
const enum stringop_alg unknown_size;
const struct stringop_strategy {
const int max;
const enum stringop_alg alg;
int noalign;
} size [MAX_STRINGOP_ALGS];
};
/* Define the specific costs for a given cpu */
struct processor_costs {
const int add; /* cost of an add instruction */
const int lea; /* cost of a lea instruction */
const int shift_var; /* variable shift costs */
const int shift_const; /* constant shift costs */
const int mult_init[5]; /* cost of starting a multiply
in QImode, HImode, SImode, DImode, TImode*/
const int mult_bit; /* cost of multiply per each bit set */
const int divide[5]; /* cost of a divide/mod
in QImode, HImode, SImode, DImode, TImode*/
int movsx; /* The cost of movsx operation. */
int movzx; /* The cost of movzx operation. */
const int large_insn; /* insns larger than this cost more */
const int move_ratio; /* The threshold of number of scalar
memory-to-memory move insns. */
const int movzbl_load; /* cost of loading using movzbl */
const int int_load[3]; /* cost of loading integer registers
in QImode, HImode and SImode relative
to reg-reg move (2). */
const int int_store[3]; /* cost of storing integer register
in QImode, HImode and SImode */
const int fp_move; /* cost of reg,reg fld/fst */
const int fp_load[3]; /* cost of loading FP register
in SFmode, DFmode and XFmode */
const int fp_store[3]; /* cost of storing FP register
in SFmode, DFmode and XFmode */
const int mmx_move; /* cost of moving MMX register. */
const int mmx_load[2]; /* cost of loading MMX register
in SImode and DImode */
const int mmx_store[2]; /* cost of storing MMX register
in SImode and DImode */
const int sse_move; /* cost of moving SSE register. */
const int sse_load[3]; /* cost of loading SSE register
in SImode, DImode and TImode*/
const int sse_store[3]; /* cost of storing SSE register
in SImode, DImode and TImode*/
const int mmxsse_to_integer; /* cost of moving mmxsse register to
integer and vice versa. */
const int l1_cache_size; /* size of l1 cache, in kilobytes. */
const int l2_cache_size; /* size of l2 cache, in kilobytes. */
const int prefetch_block; /* bytes moved to cache for prefetch. */
const int simultaneous_prefetches; /* number of parallel prefetch
operations. */
const int branch_cost; /* Default value for BRANCH_COST. */
const int fadd; /* cost of FADD and FSUB instructions. */
const int fmul; /* cost of FMUL instruction. */
const int fdiv; /* cost of FDIV instruction. */
const int fabs; /* cost of FABS instruction. */
const int fchs; /* cost of FCHS instruction. */
const int fsqrt; /* cost of FSQRT instruction. */
/* Specify what algorithm
to use for stringops on unknown size. */
struct stringop_algs *memcpy, *memset;
const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
load and store. */
const int scalar_load_cost; /* Cost of scalar load. */
const int scalar_store_cost; /* Cost of scalar store. */
const int vec_stmt_cost; /* Cost of any vector operation, excluding
load, store, vector-to-scalar and
scalar-to-vector operation. */
const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
const int vec_align_load_cost; /* Cost of aligned vector load. */
const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
const int vec_store_cost; /* Cost of vector store. */
const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
cost model. */
const int cond_not_taken_branch_cost;/* Cost of not taken branch for
vectorizer cost model. */
};
extern const struct processor_costs *ix86_cost;
extern const struct processor_costs ix86_size_cost;
#define ix86_cur_cost() \
(optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
/* Macros used in the machine description to test the flags. */
/* configure can arrange to change it. */
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC
#endif
#ifndef TARGET_FPMATH_DEFAULT
#define TARGET_FPMATH_DEFAULT \
(TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
#endif
#ifndef TARGET_FPMATH_DEFAULT_P
#define TARGET_FPMATH_DEFAULT_P(x) \
(TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)
#endif
#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
#define TARGET_FLOAT_RETURNS_IN_80387_P(x) TARGET_FLOAT_RETURNS_P(x)
/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
compile-time constant. */
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
#ifdef __x86_64__
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#else
#ifndef TARGET_BI_ARCH
#undef TARGET_64BIT
#undef TARGET_64BIT_P
#if TARGET_64BIT_DEFAULT
#define TARGET_64BIT 1
#define TARGET_64BIT_P(x) 1
#else
#define TARGET_64BIT 0
#define TARGET_64BIT_P(x) 0
#endif
#endif
#endif
#define HAS_LONG_COND_BRANCH 1
#define HAS_LONG_UNCOND_BRANCH 1
#define TARGET_386 (ix86_tune == PROCESSOR_I386)
#define TARGET_486 (ix86_tune == PROCESSOR_I486)
#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
#define TARGET_K6 (ix86_tune == PROCESSOR_K6)
#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
#define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM)
#define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE)
#define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
#define TARGET_KNL (ix86_tune == PROCESSOR_KNL)
#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
#define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
#define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3)
#define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4)
#define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
#define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
/* Feature tests against the various tunings. */
enum ix86_tune_indices {
#undef DEF_TUNE
#define DEF_TUNE(tune, name, selector) tune,
/* Definitions of x86 tunable features.
Copyright (C) 2013-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Tuning for a given CPU XXXX consists of:
- adding new CPU into:
- adding PROCESSOR_XXX to processor_type (in i386.h)
- possibly adding XXX into CPU attribute in i386.md
- adding XXX to processor_alias_table (in i386.c)
- introducing ix86_XXX_cost in i386.c
- Stringop generation table can be build based on test_stringop
- script (once rest of tuning is complete)
- designing a scheduler model in
- XXXX.md file
- Updating ix86_issue_rate and ix86_adjust_cost in i386.md
- possibly updating ia32_multipass_dfa_lookahead, ix86_sched_reorder
and ix86_sched_init_global if those tricks are needed.
- Tunning the flags bellow. Those are split into sections and each
section is very roughly ordered by importance. */
/*****************************************************************************/
/* Scheduling flags. */
/*****************************************************************************/
/* X86_TUNE_SCHEDULE: Enable scheduling. */
DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
m_PENT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
| m_KNL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
on modern chips. Preffer stores affecting whole integer register
over partial stores. For example preffer MOVZBL or MOVQ to load 8bit
value over movb. */
DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
| m_KNL | m_AMD_MULTIPLE | m_GENERIC)
/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
destinations to be 128bit to allow register renaming on 128bit SSE units,
but usually results in one extra microop on 64bit SSE units.
Experimental results shows that disabling this option on P4 brings over 20%
SPECfp regression, while enabling it on K8 brings roughly 2.4% regression
that can be partly masked by careful scheduling of moves. */
DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
| m_BDVER | m_GENERIC)
/* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
are resolved on SSE register parts instead of whole registers, so we may
maintain just lower part of scalar values in proper format leaving the
upper part undefined. */
DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8)
/* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of of flags
set by instructions affecting just some flags (in particular shifts).
This is because Core2 resolves dependencies on whole flags register
and such sequences introduce false dependency on previous instruction
setting full flags.
The flags does not affect generation of INC and DEC that is controlled
by X86_TUNE_USE_INCDEC.
This flag may be dropped from generic once core2-corei5 machines are
rare enough. */
DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
m_CORE2 | m_GENERIC)
/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
partial dependencies. */
DEF_TUNE (X86_TUNE_MOVX, "movx",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_KNL | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GENERIC)
/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
full sized loads. */
DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
| m_KNL | m_AMD_MULTIPLE | m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
conditional jump instruction for 32 bit TARGET.
FIXME: revisit for generic. */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
m_CORE_ALL | m_BDVER)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
conditional jump instruction for TARGET_64BIT.
FIXME: revisit for generic. */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
subsequent conditional jump instruction when the condition jump
check sign flag (SF) or overflow flag (OF). */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER)
/* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
jump instruction when the alu instruction produces the CCFLAG consumed by
the conditional jump instruction. */
DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
m_SANDYBRIDGE | m_HASWELL)
/* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
during reassociation of integer computation. */
DEF_TUNE (X86_TUNE_REASSOC_INT_TO_PARALLEL, "reassoc_int_to_parallel",
m_BONNELL)
/* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
during reassociation of fp computation. */
DEF_TUNE (X86_TUNE_REASSOC_FP_TO_PARALLEL, "reassoc_fp_to_parallel",
m_BONNELL | m_SILVERMONT | m_HASWELL | m_KNL |m_INTEL | m_BDVER1
| m_BDVER2 | m_GENERIC)
/*****************************************************************************/
/* Function prologue, epilogue and function calling sequences. */
/*****************************************************************************/
/* X86_TUNE_ACCUMULATE_OUTGOING_ARGS: Allocate stack space for outgoing
arguments in prologue/epilogue instead of separately for each call
by push/pop instructions.
This increase code size by about 5% in 32bit mode, less so in 64bit mode
because parameters are passed in registers. It is considerable
win for targets without stack engine that prevents multple push operations
to happen in parallel.
FIXME: the flags is incorrectly enabled for amdfam10, Bulldozer,
Bobcat and Generic. This is because disabling it causes large
regression on mgrid due to IRA limitation leading to unecessary
use of the frame pointer in 32bit mode. */
DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL
| m_ATHLON_K8)
/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
considered on critical path. */
DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move",
m_PPRO | m_ATHLON_K8)
/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in epilogues that are
considered on critical path. */
DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
m_PPRO | m_ATHLON_K8)
/* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */
DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
/* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
Some chips, like 486 and Pentium works faster with separate load
and push instructions. */
DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
| m_GENERIC)
/* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
over esp subtraction. */
DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT
| m_K6_GEODE)
/* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
over esp subtraction. */
DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_K6_GEODE)
/* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
over esp addition. */
DEF_TUNE (X86_TUNE_SINGLE_POP, "single_pop", m_386 | m_486 | m_PENT | m_PPRO)
/* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
over esp addition. */
DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT)
/*****************************************************************************/
/* Branch predictor tuning */
/*****************************************************************************/
/* X86_TUNE_PAD_SHORT_FUNCTION: Make every function to be at least 4
instructions long. */
DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_BONNELL)
/* X86_TUNE_PAD_RETURNS: Place NOP before every RET that is a destination
of conditional jump or directly preceded by other jump instruction.
This is important for AND K8-AMDFAM10 because the branch prediction
architecture expect at most one jump per 2 byte window. Failing to
pad returns leads to misaligned return stack. */
DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
m_ATHLON_K8 | m_AMDFAM10 | m_GENERIC)
/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
than 4 branch instructions in the 16 byte window. */
DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL |m_INTEL |
m_ATHLON_K8 | m_AMDFAM10)
/*****************************************************************************/
/* Integer instruction selection tuning */
/*****************************************************************************/
/* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL: Enable software prefetching
at -O3. For the moment, the prefetching seems badly tuned for Intel
chips. */
DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial",
m_K6_GEODE | m_AMD_MULTIPLE)
/* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
on 16-bit immediate moves into memory on Core2 and Corei7. */
DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
/* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
as "add mem, reg". */
DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_PPRO))
/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. */
DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
~(m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
| m_KNL | m_GENERIC))
/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
for DFmode copies */
DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_KNL | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GENERIC))
/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
will impact LEA instruction selection. */
DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
| m_INTEL)
/* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */
DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
m_BONNELL | m_SILVERMONT | m_KNL)
/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
vector path on AMD machines.
FIXME: Do we need to enable this for core? */
DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem",
m_K8 | m_AMDFAM10)
/* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
machines.
FIXME: Do we need to enable this for core? */
DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
m_K8 | m_AMDFAM10)
/* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
a conditional move. */
DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL)
/* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */
DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
/* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
compact prologues and epilogues by issuing a misaligned moves. This
requires target to handle misaligned moves and partial memory stalls
reasonably well.
FIXME: This may actualy be a win on more targets than listed here. */
DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
"misaligned_move_string_pro_epilogues",
m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_GENERIC)
/* X86_TUNE_USE_SAHF: Controls use of SAHF. */
DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_KNL | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
| m_BTVER | m_GENERIC)
/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
~(m_PENT | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL | m_K6))
/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL
| m_AMD_MULTIPLE | m_GENERIC)
/*****************************************************************************/
/* 387 instruction selection tuning */
/*****************************************************************************/
/* X86_TUNE_USE_HIMODE_FIOP: Enables use of x87 instructions with 16bit
integer operand.
FIXME: Why this is disabled for modern chips? */
DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
m_386 | m_486 | m_K6_GEODE)
/* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit
integer operand. */
DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
~(m_PENT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_KNL | m_INTEL | m_AMD_MULTIPLE | m_GENERIC))
/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
/* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */
DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_KNL | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GENERIC)
/*****************************************************************************/
/* SSE instruction selection tuning */
/*****************************************************************************/
/* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
instructions. */
DEF_TUNE (X86_TUNE_VECTORIZE_DOUBLE, "vectorize_double", ~m_BONNELL)
/* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
regs instead of memory. */
DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
m_CORE_ALL)
/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
of a sequence loading registers by parts. */
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_AMDFAM10 | m_BDVER
| m_BTVER | m_SILVERMONT | m_KNL | m_INTEL | m_GENERIC)
/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
of a sequence loading registers by parts. */
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_SILVERMONT
| m_KNL | m_INTEL | m_GENERIC)
/* Use packed single precision instructions where posisble. I.e. movups instead
of movupd. */
DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
m_BDVER)
/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */
DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
m_AMD_MULTIPLE | m_CORE_ALL | m_GENERIC)
/* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
xorps/xorpd and other variants. */
DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_GENERIC)
/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
to SSE registers. If disabled, the moves will be done by storing
the value to memory and reloading. */
DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC, "inter_unit_moves_to_vec",
~(m_AMD_MULTIPLE | m_GENERIC))
/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from SSE
to integer registers. If disabled, the moves will be done by storing
the value to memory and reloading. */
DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC, "inter_unit_moves_from_vec",
~m_ATHLON_K8)
/* X86_TUNE_INTER_UNIT_CONVERSIONS: Enable float<->integer conversions
to use both SSE and integer registers at a same time.
FIXME: revisit importance of this for generic. */
DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
~(m_AMDFAM10 | m_BDVER))
/* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
fp converts to destination register. */
DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
m_SILVERMONT | m_KNL | m_INTEL)
/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
from FP to FP. This form of instructions avoids partial write to the
destination. */
DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS, "use_vector_fp_converts",
m_AMDFAM10)
/* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
from integer to FP. */
DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
/* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */
DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL)
/* X86_TUNE_VECTOR_PARALLEL_EXECUTION: Indicates tunings with ability to
execute 2 or more vector instructions in parallel. */
DEF_TUNE (X86_TUNE_VECTOR_PARALLEL_EXECUTION, "vec_parallel",
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
/* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */
DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
m_SILVERMONT | m_INTEL)
/*****************************************************************************/
/* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
/*****************************************************************************/
/* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if false, unaligned loads are
split. */
DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal",
~(m_NEHALEM | m_SANDYBRIDGE | m_GENERIC))
/* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if false, unaligned stores are
split. */
DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_store_optimal",
~(m_NEHALEM | m_SANDYBRIDGE | m_BDVER | m_GENERIC))
/* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
the auto-vectorizer. */
DEF_TUNE (X86_TUNE_AVX128_OPTIMAL, "avx128_optimal", m_BDVER | m_BTVER2)
/*****************************************************************************/
/* Historical relics: tuning flags that helps a specific old CPU designs */
/*****************************************************************************/
/* X86_TUNE_DOUBLE_WITH_ADD: Use add instead of sal to double value in
an integer register. */
DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386)
/* X86_TUNE_ALWAYS_FANCY_MATH_387: controls use of fancy 387 operations,
such as fsqrt, fprem, fsin, fcos, fsincos etc.
Should be enabled for all targets that always has coprocesor. */
DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387",
~(m_386 | m_486))
/* X86_TUNE_UNROLL_STRLEN: Produce (quite lame) unrolled sequence for
inline strlen. This affects only -minline-all-stringops mode. By
default we always dispatch to a library since our internal strlen
is bad. */
DEF_TUNE (X86_TUNE_UNROLL_STRLEN, "unroll_strlen", ~m_386)
/* X86_TUNE_SHIFT1: Enables use of short encoding of "sal reg" instead of
longer "sal $1, reg". */
DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
/* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
of mozbl/movwl. */
DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and", m_486 | m_PENT)
/* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
and SImode multiply, but 386 and 486 do HImode multiply faster. */
DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
~(m_386 | m_486))
/* X86_TUNE_FAST_PREFIX: Enable demoting some 32bit or 64bit arithmetic
into 16bit/8bit when resulting sequence is shorter. For example
for "and $-65536, reg" to 16bit store of 0. */
DEF_TUNE (X86_TUNE_FAST_PREFIX, "fast_prefix", ~(m_386 | m_486 | m_PENT))
/* X86_TUNE_READ_MODIFY_WRITE: Enable use of read modify write instructions
such as "add $1, mem". */
DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE, "read_modify_write", ~m_PENT)
/* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
than a MOV. */
DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT)
/* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
but one byte longer. */
DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT)
/* X86_TUNE_PARTIAL_REG_STALL: Pentium pro, unlike later chips, handled
use of partial registers by renaming. This improved performance of 16bit
code where upper halves of registers are not used. It also leads to
an penalty whenever a 16bit store is followed by 32bit use. This flag
disables production of such sequences in common cases.
See also X86_TUNE_HIMODE_MATH.
In current implementation the partial register stalls are not eliminated
very well - they can be introduced via subregs synthesized by combine
and can happen in caller/callee saving sequences. */
DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO)
/* X86_TUNE_PROMOTE_QIMODE: When it is cheap, turn 8bit arithmetic to
corresponding 32bit arithmetic. */
DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode",
~m_PPRO)
/* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit artihmetic. Again we avoid
partial register stalls on PentiumPro targets. */
DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS, "promote_hi_regs", m_PPRO)
/* X86_TUNE_HIMODE_MATH: Enable use of 16bit arithmetic.
On PPro this flag is meant to avoid partial register stalls. */
DEF_TUNE (X86_TUNE_HIMODE_MATH, "himode_math", ~m_PPRO)
/* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates
directly to memory. */
DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES, "split_long_moves", m_PPRO)
/* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
DEF_TUNE (X86_TUNE_USE_XCHGB, "use_xchgb", m_PENT4)
/* X86_TUNE_USE_MOV0: Use "mov $0, reg" instead of "xor reg, reg" to clear
integer register. */
DEF_TUNE (X86_TUNE_USE_MOV0, "use_mov0", m_K6)
/* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
operand that cannot be represented using a modRM byte. The XOR
replacement is long decoded, so this split helps here as well. */
DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6)
/* X86_TUNE_AVOID_VECTOR_DECODE: Enable splitters that avoid vector decoded
forms of instructions on K8 targets. */
DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
m_K8)
/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
for bit-manipulation instructions. */
DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi",
m_SANDYBRIDGE | m_HASWELL | m_GENERIC)
/*****************************************************************************/
/* This never worked well before. */
/*****************************************************************************/
/* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
on simulation result. But after P4 was made, no performance benefit
was observed with branch hints. It also increases the code size.
As a result, icc never generates branch hints. */
DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", 0)
/* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic. */
DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", ~0)
/* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit
arithmetic to 32bit via PROMOTE_MODE macro. This code generation scheme
is usually used for RISC targets. */
DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0)
/* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based
on hardware capabilities. Bdver3 hardware has a loop buffer which makes
unrolling small loop less important. For, such architectures we adjust
the unroll factor so that the unrolled loop fits the loop buffer. */
DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
#undef DEF_TUNE
X86_TUNE_LAST
};
extern unsigned char ix86_tune_features[X86_TUNE_LAST];
#define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
#define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
#define TARGET_ZERO_EXTEND_WITH_AND \
ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
#define TARGET_BRANCH_PREDICTION_HINTS \
ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
#define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
#define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
#define TARGET_PARTIAL_FLAG_REG_STALL \
ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
#define TARGET_LCP_STALL \
ix86_tune_features[X86_TUNE_LCP_STALL]
#define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
#define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
#define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
#define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
#define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
#define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
#define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
#define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
#define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
#define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
#define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \
ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES]
#define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
#define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
#define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
#define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
#define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
#define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
#define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
#define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
#define TARGET_INTEGER_DFMODE_MOVES \
ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
#define TARGET_PARTIAL_REG_DEPENDENCY \
ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
#define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
#define TARGET_SSE_TYPELESS_STORES \
ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
#define TARGET_MEMORY_MISMATCH_STALL \
ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
#define TARGET_PROLOGUE_USING_MOVE \
ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
#define TARGET_EPILOGUE_USING_MOVE \
ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
#define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
#define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
#define TARGET_INTER_UNIT_MOVES_TO_VEC \
ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC]
#define TARGET_INTER_UNIT_MOVES_FROM_VEC \
ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC]
#define TARGET_INTER_UNIT_CONVERSIONS \
ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
#define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
#define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
#define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
#define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
#define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
#define TARGET_PAD_SHORT_FUNCTION \
ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
#define TARGET_EXT_80387_CONSTANTS \
ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
#define TARGET_AVOID_VECTOR_DECODE \
ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
#define TARGET_SLOW_IMUL_IMM32_MEM \
ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
#define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
#define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
#define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
#define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
#define TARGET_USE_VECTOR_FP_CONVERTS \
ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
#define TARGET_USE_VECTOR_CONVERTS \
ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
#define TARGET_SLOW_PSHUFB \
ix86_tune_features[X86_TUNE_SLOW_PSHUFB]
#define TARGET_VECTOR_PARALLEL_EXECUTION \
ix86_tune_features[X86_TUNE_VECTOR_PARALLEL_EXECUTION]
#define TARGET_FUSE_CMP_AND_BRANCH_32 \
ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]
#define TARGET_FUSE_CMP_AND_BRANCH_64 \
ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]
#define TARGET_FUSE_CMP_AND_BRANCH \
(TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \
: TARGET_FUSE_CMP_AND_BRANCH_32)
#define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \
ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS]
#define TARGET_FUSE_ALU_AND_BRANCH \
ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH]
#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
#define TARGET_AVOID_LEA_FOR_ADDR \
ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR]
#define TARGET_VECTORIZE_DOUBLE \
ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE]
#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
#define TARGET_AVX128_OPTIMAL \
ix86_tune_features[X86_TUNE_AVX128_OPTIMAL]
#define TARGET_REASSOC_INT_TO_PARALLEL \
ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL]
#define TARGET_REASSOC_FP_TO_PARALLEL \
ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL]
#define TARGET_GENERAL_REGS_SSE_SPILL \
ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]
#define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
#define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \
ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
#define TARGET_ADJUST_UNROLL \
ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
#define TARGET_AVOID_FALSE_DEP_FOR_BMI \
ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
/* Feature tests against the various architecture variations. */
enum ix86_arch_indices {
X86_ARCH_CMOV,
X86_ARCH_CMPXCHG,
X86_ARCH_CMPXCHG8B,
X86_ARCH_XADD,
X86_ARCH_BSWAP,
X86_ARCH_LAST
};
extern unsigned char ix86_arch_features[X86_ARCH_LAST];
#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
/* For sane SSE instruction set generation we need fcomi instruction.
It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
expands to a sequence that includes conditional move. */
#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
extern unsigned char x86_prefetch_sse;
#define TARGET_PREFETCH_SSE x86_prefetch_sse
#define ASSEMBLER_DIALECT (ix86_asm_dialect)
#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
#define TARGET_MIX_SSE_I387 \
((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
#define TARGET_SUN_TLS 0
#ifndef TARGET_64BIT_DEFAULT
#define TARGET_64BIT_DEFAULT 0
#endif
#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
#endif
#define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL)
#define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS)
/* Fence to use after loop using storent. */
// extern tree x86_mfence;
// #define FENCE_FOLLOWING_MOVNT x86_mfence
/* Once GDB has been enhanced to deal with functions without frame
pointers, we can change this to allow for elimination of
the frame pointer in leaf functions. */
#define TARGET_DEFAULT 0
/* Extra bits to force. */
#define TARGET_SUBTARGET_DEFAULT 0
#define TARGET_SUBTARGET_ISA_DEFAULT 0
/* Extra bits to force on w/ 32-bit mode. */
#define TARGET_SUBTARGET32_DEFAULT 0
#define TARGET_SUBTARGET32_ISA_DEFAULT 0
/* Extra bits to force on w/ 64-bit mode. */
#define TARGET_SUBTARGET64_DEFAULT 0
#define TARGET_SUBTARGET64_ISA_DEFAULT 0
/* Replace MACH-O, ifdefs by in-line tests, where possible.
(a) Macros defined in config/i386/darwin.h */
#define TARGET_MACHO 0
#define TARGET_MACHO_BRANCH_ISLANDS 0
#define MACHOPIC_ATT_STUB 0
/* (b) Macros defined in config/darwin.h */
#define MACHO_DYNAMIC_NO_PIC_P 0
#define MACHOPIC_INDIRECT 0
#define MACHOPIC_PURE 0
/* For the RDOS */
#define TARGET_RDOS 0
/* For the Windows 64-bit ABI. */
#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
/* For the Windows 32-bit ABI. */
#define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
/* This is re-defined by cygming.h. */
#define TARGET_SEH 0
/* This is re-defined by cygming.h. */
#define TARGET_PECOFF 0
/* The default abi used by target. */
#define DEFAULT_ABI SYSV_ABI
/* The default TLS segment register used by target. */
#define DEFAULT_TLS_SEG_REG (TARGET_64BIT ? SEG_FS : SEG_GS)
/* Subtargets may reset this to 1 in order to enable 96-bit long double
with the rounding mode forced to 53 bits. */
#define TARGET_96_ROUND_53_LONG_DOUBLE 0
/* -march=native handling only makes sense with compiler running on
an x86 or x86_64 chip. If changing this condition, also change
the condition in driver-i386.c. */
#if defined(__i386__) || defined(__x86_64__)
/* In driver-i386.c. */
extern const char *host_detect_local_cpu (int argc, const char **argv);
#define EXTRA_SPEC_FUNCTIONS \
{ "local_cpu_detect", host_detect_local_cpu },
#define HAVE_LOCAL_CPU_DETECT
#endif
#if TARGET_64BIT_DEFAULT
#define OPT_ARCH64 "!m32"
#define OPT_ARCH32 "m32"
#else
#define OPT_ARCH64 "m64|mx32"
#define OPT_ARCH32 "m64|mx32:;"
#endif
/* Support for configure-time defaults of some command line options.
The order here is important so that -march doesn't squash the
tune or cpu values. */
#define OPTION_DEFAULT_SPECS \
{"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
{"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
{"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
{"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
{"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
{"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
{"arch", "%{!march=*:-march=%(VALUE)}"}, \
{"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
{"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
/* Specs for the compiler proper */
#ifndef CC1_CPU_SPEC
#define CC1_CPU_SPEC_1 ""
#ifndef HAVE_LOCAL_CPU_DETECT
#define CC1_CPU_SPEC CC1_CPU_SPEC_1
#else
#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
"%{march=native:%>march=native %:local_cpu_detect(arch) \
%{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \
%{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"
#endif
#endif
/* Target CPU builtins. */
#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
/* Target Pragmas. */
#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
#ifndef CC1_SPEC
#define CC1_SPEC "%(cc1_cpu) "
#endif
/* This macro defines names of additional specifications to put in the
specs that can be used in various specifications like CC1_SPEC. Its
definition is an initializer with a subgrouping for each command option.
Each subgrouping contains a string constant, that defines the
specification name, and a string constant that used by the GCC driver
program.
Do not define this macro if it does not need to do anything. */
#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif
#define EXTRA_SPECS \
{ "cc1_cpu", CC1_CPU_SPEC }, \
SUBTARGET_EXTRA_SPECS
/* Set the value of FLT_EVAL_METHOD in float.h. When using only the
FPU, assume that the fpcw is set to extended precision; when using
only SSE, rounding is correct; when using both SSE and the FPU,
the rounding precision is indeterminate, since either may be chosen
apparently at random. */
#define TARGET_FLT_EVAL_METHOD \
(TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
/* Whether to allow x87 floating-point arithmetic on MODE (one of
SFmode, DFmode and XFmode) in the current excess precision
configuration. */
#define X87_ENABLE_ARITH(MODE) \
(flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)
/* Likewise, whether to allow direct conversions from integer mode
IMODE (HImode, SImode or DImode) to MODE. */
#define X87_ENABLE_FLOAT(MODE, IMODE) \
(flag_excess_precision == EXCESS_PRECISION_FAST \
|| (MODE) == XFmode \
|| ((MODE) == DFmode && (IMODE) == SImode) \
|| (IMODE) == HImode)
/* target machine storage layout */
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE 32
#define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
#define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE \
(TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80))
#define WIDEST_HARDWARE_FP_SIZE 80
#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
#define MAX_BITS_PER_WORD 64
#else
#define MAX_BITS_PER_WORD 32
#endif
/* Define this if most significant byte of a word is the lowest numbered. */
/* That is true on the 80386. */
#define BITS_BIG_ENDIAN 0
/* Define this if most significant byte of a word is the lowest numbered. */
/* That is not true on the 80386. */
#define BYTES_BIG_ENDIAN 0
/* Define this if most significant word of a multiword number is the lowest
numbered. */
/* Not true for 80386 */
#define WORDS_BIG_ENDIAN 0
/* Width of a word, in units (bytes). */
#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
#ifndef IN_LIBGCC2
#define MIN_UNITS_PER_WORD 4
#endif
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY BITS_PER_WORD
/* Boundary (in *bits*) on which stack pointer should be aligned. */
#define STACK_BOUNDARY \
(TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
/* Stack boundary of the main function guaranteed by OS. */
#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
/* Minimum stack boundary. */
#define MIN_STACK_BOUNDARY (TARGET_64BIT ? (TARGET_SSE ? 128 : 64) : 32)
/* Boundary (in *bits*) on which the stack pointer prefers to be
aligned; the compiler cannot rely on having this alignment. */
#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
/* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
both 32bit and 64bit, to support codes that need 128 bit stack
alignment for SSE instructions, but can't realign the stack. */
#define PREFERRED_STACK_BOUNDARY_DEFAULT 128
/* 1 if -mstackrealign should be turned on by default. It will
generate an alternate prologue and epilogue that realigns the
runtime stack if nessary. This supports mixing codes that keep a
4-byte aligned stack, as specified by i386 psABI, with codes that
need a 16-byte aligned stack, as required by SSE instructions. */
#define STACK_REALIGN_DEFAULT 0
/* Boundary (in *bits*) on which the incoming stack is aligned. */
#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
/* According to Windows x64 software convention, the maximum stack allocatable
in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
instructions allowed to adjust the stack pointer in the epilog, forcing the
use of frame pointer for frames larger than 2 GB. This theorical limit
is reduced by 256, an over-estimated upper bound for the stack use by the
prologue.
We define only one threshold for both the prolog and the epilog. When the
frame size is larger than this threshold, we allocate the area to save SSE
regs, then save them, and then allocate the remaining. There is no SEH
unwind info for this later allocation. */
#define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
mandatory for the 64-bit ABI, and may or may not be true for other
operating systems. */
#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
/* Minimum allocation boundary for the code of a function. */
#define FUNCTION_BOUNDARY 8
/* C++ stores the virtual bit in the lowest bit of function pointers. */
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
/* Minimum size in bits of the largest boundary to which any
and all fundamental data types supported by the hardware
might need to be aligned. No data type wants to be aligned
rounder than this.
Pentium+ prefers DFmode values to be aligned to 64 bit boundary
and Pentium Pro XFmode values at 128 bit boundaries.
When increasing the maximum, also update
TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */
#define BIGGEST_ALIGNMENT \
(TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))
/* Maximum stack alignment. */
#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
/* Alignment value for attribute ((aligned)). It is a constant since
it is the part of the ABI. We shouldn't change it with -mavx. */
#define ATTRIBUTE_ALIGNED_VALUE 128
/* Decide whether a variable of mode MODE should be 128 bit aligned. */
#define ALIGN_MODE_128(MODE) \
((MODE) == XFmode || SSE_REG_MODE_P (MODE))
/* The published ABIs say that doubles should be aligned on word
boundaries, so lower the alignment for structure fields unless
-malign-double is set. */
/* ??? Blah -- this macro is used directly by libobjc. Since it
supports no vector modes, cut out the complexity and fall back
on BIGGEST_FIELD_ALIGNMENT. */
#ifdef IN_TARGET_LIBS
#ifdef __x86_64__
#define BIGGEST_FIELD_ALIGNMENT 128
#else
#define BIGGEST_FIELD_ALIGNMENT 32
#endif
#else
#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
x86_field_alignment (FIELD, COMPUTED)
#endif
/* If defined, a C expression to compute the alignment given to a
constant that is being placed in memory. EXP is the constant
and ALIGN is the alignment that the object would ordinarily have.
The value of this macro is used instead of that alignment to align
the object.
If this macro is not defined, then ALIGN is used.
The typical use of this macro is to increase alignment for string
constants to be word aligned so that `strcpy' calls that copy
constants can be done inline. */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
/* If defined, a C expression to compute the alignment for a static
variable. TYPE is the data type, and ALIGN is the alignment that
the object would ordinarily have. The value of this macro is used
instead of that alignment to align the object.
If this macro is not defined, then ALIGN is used.
One use of this macro is to increase alignment of medium-size
data to make it all fit in fewer cache lines. Another is to
cause character arrays to be word-aligned so that `strcpy' calls
that copy constants to character arrays can be done inline. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
ix86_data_alignment ((TYPE), (ALIGN), true)
/* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates
some alignment increase, instead of optimization only purposes. E.g.
AMD x86-64 psABI says that variables with array type larger than 15 bytes
must be aligned to 16 byte boundaries.
If this macro is not defined, then ALIGN is used. */
#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
ix86_data_alignment ((TYPE), (ALIGN), false)
/* If defined, a C expression to compute the alignment for a local
variable. TYPE is the data type, and ALIGN is the alignment that
the object would ordinarily have. The value of this macro is used
instead of that alignment to align the object.
If this macro is not defined, then ALIGN is used.
One use of this macro is to increase alignment of medium-size
data to make it all fit in fewer cache lines. */
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
/* If defined, a C expression to compute the alignment for stack slot.
TYPE is the data type, MODE is the widest mode available, and ALIGN
is the alignment that the slot would ordinarily have. The value of
this macro is used instead of that alignment to align the slot.
If this macro is not defined, then ALIGN is used when TYPE is NULL,
Otherwise, LOCAL_ALIGNMENT will be used.
One use of this macro is to set alignment of stack slot to the
maximum alignment of all possible modes which the slot may have. */
#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
ix86_local_alignment ((TYPE), (MODE), (ALIGN))
/* If defined, a C expression to compute the alignment for a local
variable DECL.
If this macro is not defined, then
LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
One use of this macro is to increase alignment of medium-size
data to make it all fit in fewer cache lines. */
#define LOCAL_DECL_ALIGNMENT(DECL) \
ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
/* If defined, a C expression to compute the minimum required alignment
for dynamic stack realignment purposes for EXP (a TYPE or DECL),
MODE, assuming normal alignment ALIGN.
If this macro is not defined, then (ALIGN) will be used. */
#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
ix86_minimum_alignment (EXP, MODE, ALIGN)
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
#define STRICT_ALIGNMENT 0
/* If bit field type is int, don't let it cross an int,
and give entire struct the alignment of an int. */
/* Required on the 386 since it doesn't have bit-field insns. */
#define PCC_BITFIELD_TYPE_MATTERS 1
/* Standard register usage. */
/* This processor has special stack-like registers. See reg-stack.c
for details. */
#define STACK_REGS
#define IS_STACK_MODE(MODE) \
(((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \
|| ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \
|| (MODE) == XFmode)
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers.
In the 80386 we give the 8 general purpose registers the numbers 0-7.
We number the floating point registers 8-15.
Note that registers 0-7 can be accessed as a short or int,
while only 0-3 may be used with byte `mov' instructions.
Reg 16 does not correspond to any hardware register, but instead
appears in the RTL as an argument pointer prior to reload, and is
eliminated during reloading in favor of either the stack or frame
pointer. */
#define FIRST_PSEUDO_REGISTER 81
/* Number of hardware registers that go into the DWARF-2 unwind info.
If not defined, equals FIRST_PSEUDO_REGISTER. */
#define DWARF_FRAME_REGISTERS 17
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
On the 80386, the stack pointer is such, as is the arg pointer.
REX registers are disabled for 32bit targets in
TARGET_CONDITIONAL_REGISTER_USAGE. */
#define FIXED_REGISTERS \
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
/*arg,flags,fpsr,fpcr,frame*/ \
1, 1, 1, 1, 1, \
/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* k0, k1, k2, k3, k4, k5, k6, k7*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* b0, b1, b2, b3*/ \
0, 0, 0, 0 }
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
registers that can be used without being saved.
The latter must include the registers where values are returned
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like.
Value is set to 1 if the register is call used unconditionally.
Bit one is set if the register is call used on TARGET_32BIT ABI.
Bit two is set if the register is call used on TARGET_64BIT ABI.
Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.
Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
#define CALL_USED_REGISTERS \
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
{ 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/*arg,flags,fpsr,fpcr,frame*/ \
1, 1, 1, 1, 1, \
/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1, 1, 1, 1, 1, 1, 6, 6, \
/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1, 1, 1, 1, 2, 2, 2, 2, \
/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
6, 6, 6, 6, 6, 6, 6, 6, \
/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
6, 6, 6, 6, 6, 6, 6, 6, \
/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
6, 6, 6, 6, 6, 6, 6, 6, \
/* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* b0, b1, b2, b3*/ \
1, 1, 1, 1 }
/* Order in which to allocate registers. Each register must be
listed once, even those in FIXED_REGISTERS. List frame pointer
late and fixed registers last. Note that, in general, we prefer
registers listed in CALL_USED_REGISTERS, keeping the others
available for storage of persistent values.
The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
so this is just empty initializer for array. */
#define REG_ALLOC_ORDER \
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \
78, 79, 80 }
/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
to be rearranged based on a particular function. When using sse math,
we want to allocate SSE before x87 registers and vice versa. */
#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
Actually there are no two word move instructions for consecutive
registers. And only registers 0-3 may have mov byte instructions
applied to them. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
(STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
|| MASK_REGNO_P (REGNO) || BND_REGNO_P (REGNO) \
? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
: ((MODE) == XFmode \
? (TARGET_64BIT ? 2 : 3) \
: (MODE) == XCmode \
? (TARGET_64BIT ? 4 : 6) \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
? 0 \
: ((MODE) == XFmode || (MODE) == XCmode)) \
: 0)
#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
#define VALID_AVX256_REG_MODE(MODE) \
((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
|| (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
|| (MODE) == V4DFmode)
#define VALID_AVX256_REG_OR_OI_MODE(MODE) \
(VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
#define VALID_AVX512F_SCALAR_MODE(MODE) \
((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \
|| (MODE) == SFmode)
#define VALID_AVX512F_REG_MODE(MODE) \
((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
|| (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
|| (MODE) == V4TImode)
#define VALID_AVX512VL_128_REG_MODE(MODE) \
((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
|| (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode)
#define VALID_SSE2_REG_MODE(MODE) \
((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
|| (MODE) == V2DImode || (MODE) == DFmode)
#define VALID_SSE_REG_MODE(MODE) \
((MODE) == V1TImode || (MODE) == TImode \
|| (MODE) == V4SFmode || (MODE) == V4SImode \
|| (MODE) == SFmode || (MODE) == TFmode)
#define VALID_MMX_REG_MODE_3DNOW(MODE) \
((MODE) == V2SFmode || (MODE) == SFmode)
#define VALID_MMX_REG_MODE(MODE) \
((MODE == V1DImode) || (MODE) == DImode \
|| (MODE) == V2SImode || (MODE) == SImode \
|| (MODE) == V4HImode || (MODE) == V8QImode)
#define VALID_BND_REG_MODE(MODE) \
(TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode)
#define VALID_DFP_MODE_P(MODE) \
((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
#define VALID_FP_MODE_P(MODE) \
((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
|| (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
#define VALID_INT_MODE_P(MODE) \
((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
|| (MODE) == DImode \
|| (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
|| (MODE) == CDImode \
|| (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
|| (MODE) == TFmode || (MODE) == TCmode)))
/* Return true for modes passed in SSE registers. */
#define SSE_REG_MODE_P(MODE) \
((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
|| (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
|| (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
|| (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
|| (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
|| (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \
|| (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
|| (MODE) == V16SFmode)
#define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
#define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
ix86_hard_regno_mode_ok ((REGNO), (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
/* It is possible to write patterns to move flags; but until someone
does it, */
#define AVOID_CCMODE_COPIES
/* Specify the modes required to caller save a given hard regno.
We do this on i386 to prevent flags from being saved at all.
Kill any attempts to combine saving of modes. */
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
(CC_REGNO_P (REGNO) ? VOIDmode \
: (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
: (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
: (MODE) == HImode && !(TARGET_PARTIAL_REG_STALL \
|| MASK_REGNO_P (REGNO)) ? SImode \
: (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO) \
|| MASK_REGNO_P (REGNO)) ? SImode \
: (MODE))
/* The only ABI that saves SSE registers across calls is Win64 (thus no
need to check the current ABI here), and with AVX enabled Win64 only
guarantees that the low 16 bytes are saved. */
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
(SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16)
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */
/* on the 386 the pc register is %eip, and is not usable as a general
register. The ordinary mov instructions won't work */
/* #define PC_REGNUM */
/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM 7
/* Base register for access to local variables of the function. */
#define HARD_FRAME_POINTER_REGNUM 6
/* Base register for access to local variables of the function. */
#define FRAME_POINTER_REGNUM 20
/* First floating point reg */
#define FIRST_FLOAT_REG 8
/* First & last stack-like regs */
#define FIRST_STACK_REG FIRST_FLOAT_REG
#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
#define LAST_SSE_REG (FIRST_SSE_REG + 7)
#define FIRST_MMX_REG (LAST_SSE_REG + 1) /*29*/
#define LAST_MMX_REG (FIRST_MMX_REG + 7)
#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) /*37*/
#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) /*45*/
#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
#define FIRST_EXT_REX_SSE_REG (LAST_REX_SSE_REG + 1) /*53*/
#define LAST_EXT_REX_SSE_REG (FIRST_EXT_REX_SSE_REG + 15) /*68*/
#define FIRST_MASK_REG (LAST_EXT_REX_SSE_REG + 1) /*69*/
#define LAST_MASK_REG (FIRST_MASK_REG + 7) /*76*/
#define FIRST_BND_REG (LAST_MASK_REG + 1) /*77*/
#define LAST_BND_REG (FIRST_BND_REG + 3) /*80*/
/* Override this in other tm.h files to cope with various OS lossage
requiring a frame pointer. */
#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
#define SUBTARGET_FRAME_POINTER_REQUIRED 0
#endif
/* Make sure we can access arbitrary call frames. */
#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
/* Base register for access to arguments of the function. */
#define ARG_POINTER_REGNUM 16
/* Register to hold the addressing base for position independent
code access to data items. We don't use PIC pointer for 64bit
mode. Define the regnum to dummy value to prevent gcc from
pessimizing code dealing with EBX.
To avoid clobbering a call-saved register unnecessarily, we renumber
the pic register when possible. The change is visible after the
prologue has been emitted. */
#define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG)
#define PIC_OFFSET_TABLE_REGNUM \
(ix86_use_pseudo_pic_reg () \
? (pic_offset_table_rtx \
? INVALID_REGNUM \
: REAL_PIC_OFFSET_TABLE_REGNUM) \
: INVALID_REGNUM)
#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
/* This is overridden by <cygwin.h>. */
#define MS_AGGREGATE_RETURN 0
#define KEEP_AGGREGATE_RETURN_POINTER 0
/* Define the classes of registers for register constraints in the
machine description. Also define ranges of constants.
One of the classes must always be named ALL_REGS and include all hard regs.
If there is more than one class, another class must be named NO_REGS
and contain no registers.
The name GENERAL_REGS must be the name of a class (or an alias for
another name such as ALL_REGS). This is the class of registers
that is allowed by "g" or "r" in a register constraint.
Also, registers outside this class are allocated only when
instructions express preferences for them.
The classes must be numbered in nondecreasing order; that is,
a larger-numbered class must never be contained completely
in a smaller-numbered class.
For any two classes, it is very desirable that there be another
class that represents their union.
It might seem that class BREG is unnecessary, since no useful 386
opcode needs reg %ebx. But some systems pass args to the OS in ebx,
and the "b" register constraint is useful in asms for syscalls.
The flags, fpsr and fpcr registers are in no class. */
enum reg_class
{
NO_REGS,
AREG, DREG, CREG, BREG, SIREG, DIREG,
AD_REGS, /* %eax/%edx for DImode */
Q_REGS, /* %eax %ebx %ecx %edx */
NON_Q_REGS, /* %esi %edi %ebp %esp */
INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
CLOBBERED_REGS, /* call-clobbered integer registers */
GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
%r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
FLOAT_REGS,
SSE_FIRST_REG,
NO_REX_SSE_REGS,
SSE_REGS,
EVEX_SSE_REGS,
BND_REGS,
ALL_SSE_REGS,
MMX_REGS,
FP_TOP_SSE_REGS,
FP_SECOND_SSE_REGS,
FLOAT_SSE_REGS,
FLOAT_INT_REGS,
INT_SSE_REGS,
FLOAT_INT_SSE_REGS,
MASK_EVEX_REGS,
MASK_REGS,
ALL_REGS, LIM_REG_CLASSES
};
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
#define INTEGER_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), GENERAL_REGS)
#define FLOAT_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), FLOAT_REGS)
#define SSE_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), ALL_SSE_REGS)
#define MMX_CLASS_P(CLASS) \
((CLASS) == MMX_REGS)
#define MAYBE_INTEGER_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), GENERAL_REGS)
#define MAYBE_FLOAT_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), FLOAT_REGS)
#define MAYBE_SSE_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
#define MAYBE_MMX_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), MMX_REGS)
#define MAYBE_MASK_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), MASK_REGS)
#define Q_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), Q_REGS)
#define MAYBE_NON_Q_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), NON_Q_REGS)
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{ "NO_REGS", \
"AREG", "DREG", "CREG", "BREG", \
"SIREG", "DIREG", \
"AD_REGS", \
"Q_REGS", "NON_Q_REGS", \
"INDEX_REGS", \
"LEGACY_REGS", \
"CLOBBERED_REGS", \
"GENERAL_REGS", \
"FP_TOP_REG", "FP_SECOND_REG", \
"FLOAT_REGS", \
"SSE_FIRST_REG", \
"NO_REX_SSE_REGS", \
"SSE_REGS", \
"EVEX_SSE_REGS", \
"BND_REGS", \
"ALL_SSE_REGS", \
"MMX_REGS", \
"FP_TOP_SSE_REGS", \
"FP_SECOND_SSE_REGS", \
"FLOAT_SSE_REGS", \
"FLOAT_INT_REGS", \
"INT_SSE_REGS", \
"FLOAT_INT_SSE_REGS", \
"MASK_EVEX_REGS", \
"MASK_REGS", \
"ALL_REGS" }
/* Define which registers fit in which classes. This is an initializer
for a vector of HARD_REG_SET of length N_REG_CLASSES.
Note that CLOBBERED_REGS are calculated by
TARGET_CONDITIONAL_REGISTER_USAGE. */
#define REG_CLASS_CONTENTS \
{ { 0x00, 0x0, 0x0 }, \
{ 0x01, 0x0, 0x0 }, /* AREG */ \
{ 0x02, 0x0, 0x0 }, /* DREG */ \
{ 0x04, 0x0, 0x0 }, /* CREG */ \
{ 0x08, 0x0, 0x0 }, /* BREG */ \
{ 0x10, 0x0, 0x0 }, /* SIREG */ \
{ 0x20, 0x0, 0x0 }, /* DIREG */ \
{ 0x03, 0x0, 0x0 }, /* AD_REGS */ \
{ 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
{ 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \
{ 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \
{ 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
{ 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
{ 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \
{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
{ 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
{ 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
{ 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \
{ 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \
{ 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \
{ 0x0, 0x0,0x1e000 }, /* BND_REGS */ \
{ 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \
{ 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \
{ 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \
{ 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \
{ 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \
{ 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \
{ 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \
{ 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
{ 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \
{ 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \
{ 0xffffffff,0xffffffff, 0x1fff } \
}
/* The same information, inverted:
Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
or could index an array. */
#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
/* When this hook returns true for MODE, the compiler allows
registers explicitly used in the rtl to be used as spill registers
but prevents the compiler from extending the lifetime of these
registers. */
#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
#define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
#define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG)
#define GENERAL_REG_P(X) \
(REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
#define GENERAL_REGNO_P(N) \
(IN_RANGE ((N), AX_REG, SP_REG) || REX_INT_REGNO_P (N))
#define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
#define ANY_QI_REGNO_P(N) \
(TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
#define REX_INT_REGNO_P(N) \
IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
#define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
#define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
#define X87_FLOAT_MODE_P(MODE) \
(TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
#define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
#define SSE_REGNO_P(N) \
(IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
|| REX_SSE_REGNO_P (N) \
|| EXT_REX_SSE_REGNO_P (N))
#define REX_SSE_REGNO_P(N) \
IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
#define EXT_REX_SSE_REGNO_P(N) \
IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
#define SSE_REGNO(N) \
((N) < 8 ? FIRST_SSE_REG + (N) \
: (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \
: (FIRST_EXT_REX_SSE_REG + (N) - 16))
#define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
#define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
#define ANY_MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
#define SSE_FLOAT_MODE_P(MODE) \
((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
#define FMA4_VEC_FLOAT_MODE_P(MODE) \
(TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
|| (MODE) == V8SFmode || (MODE) == V4DFmode))
#define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
#define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG)
#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
#define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG)
#define ANY_BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X)))
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS INDEX_REGS
#define BASE_REG_CLASS GENERAL_REGS
/* Place additional restrictions on the register class to use when it
is necessary to be able to hold a value of mode MODE in a reload
register for which class CLASS would ordinarily be used.
We avoid classes containing registers from multiple units due to
the limitation in ix86_secondary_memory_needed. We limit these
classes to their "natural mode" single unit register class, depending
on the unit availability.
Please note that reg_class_subset_p is not commutative, so these
conditions mean "... if (CLASS) includes ALL registers from the
register set." */
#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
(((MODE) == QImode && !TARGET_64BIT \
&& reg_class_subset_p (Q_REGS, (CLASS))) ? Q_REGS \
: (((MODE) == SImode || (MODE) == DImode) \
&& reg_class_subset_p (GENERAL_REGS, (CLASS))) ? GENERAL_REGS \
: (SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH \
&& reg_class_subset_p (SSE_REGS, (CLASS))) ? SSE_REGS \
: (X87_FLOAT_MODE_P (MODE) \
&& reg_class_subset_p (FLOAT_REGS, (CLASS))) ? FLOAT_REGS \
: (CLASS))
/* If we are copying between general and FP registers, we need a memory
location. The same is true for SSE and MMX registers. */
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
/* Get_secondary_mem widens integral modes to BITS_PER_WORD.
There is no need to emit full 64 bit move on 64 bit targets
for integral modes that can be moved using 32 bit move. */
#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
(GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
: MODE)
/* Return a class of registers that cannot change FROM mode to TO mode. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
ix86_cannot_change_mode_class (FROM, TO, CLASS)
/* Stack layout; function entry, exit and calling. */
/* Define this if pushing a word on the stack
makes the stack pointer a smaller address. */
#define STACK_GROWS_DOWNWARD
/* Define this to nonzero if the nominal address of the stack frame
is at the high-address end of the local variables;
that is, each additional local variable allocated
goes at a more negative offset in the frame. */
#define FRAME_GROWS_DOWNWARD 1
/* Offset within stack frame to start allocating local variables at.
If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
first local allocated. Otherwise, it is the offset to the BEGINNING
of the first local allocated. */
#define STARTING_FRAME_OFFSET 0
/* If we generate an insn to push BYTES bytes, this says how many the stack
pointer really advances by. On 386, we have pushw instruction that
decrements by exactly 2 no matter what the position was, there is no pushb.
But as CIE data alignment factor on this arch is -4 for 32bit targets
and -8 for 64bit targets, we need to make sure all stack pointer adjustments
are in multiple of 4 for 32bit targets and 8 for 64bit targets. */
#define PUSH_ROUNDING(BYTES) \
(((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)
/* If defined, the maximum amount of space required for outgoing arguments
will be computed and placed into the variable `crtl->outgoing_args_size'.
No space will be pushed onto the stack for each call; instead, the
function prologue should increase the stack frame size by this amount.
In 32bit mode enabling argument accumulation results in about 5% code size
growth becuase move instructions are less compact than push. In 64bit
mode the difference is less drastic but visible.
FIXME: Unlike earlier implementations, the size of unwind info seems to
actually grow with accumulation. Is that because accumulated args
unwind info became unnecesarily bloated?
With the 64-bit MS ABI, we can generate correct code with or without
accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code
generated without accumulated args is terrible.
If stack probes are required, the space used for large function
arguments on the stack must also be probed, so enable
-maccumulate-outgoing-args so this happens in the prologue. */
#define ACCUMULATE_OUTGOING_ARGS \
((TARGET_ACCUMULATE_OUTGOING_ARGS && optimize_function_for_speed_p (cfun)) \
|| TARGET_STACK_PROBE || TARGET_64BIT_MS_ABI)
/* If defined, a C expression whose value is nonzero when we want to use PUSH
instructions to pass outgoing arguments. */
#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
/* We want the stack and args grow in opposite directions, even if
PUSH_ARGS is 0. */
#define PUSH_ARGS_REVERSED 1
/* Offset of first parameter from the argument pointer register value. */
#define FIRST_PARM_OFFSET(FNDECL) 0
/* Define this macro if functions should assume that stack space has been
allocated for arguments even when their values are passed in registers.
The value of this macro is the size, in bytes, of the area reserved for
arguments passed in registers for the function represented by FNDECL.
This space can be allocated by the caller, or be a part of the
machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
which. */
#define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
(TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
#define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
/* Define the size of the result block used for communication between
untyped_call and untyped_return. The block contains a DImode value
followed by the block used by fnsave and frstor. */
#define APPLY_RESULT_SIZE (8+108)
/* 1 if N is a possible register number for function argument passing. */
#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
hold all necessary information about the function itself
and about the args processed so far, enough to enable macros
such as FUNCTION_ARG to determine where the next arg should go. */
typedef struct ix86_args {
int words; /* # words passed so far */
int nregs; /* # registers available for passing */
int regno; /* next available register number */
int fastcall; /* fastcall or thiscall calling convention
is used */
int sse_words; /* # sse words passed so far */
int sse_nregs; /* # sse registers available for passing */
int warn_avx512f; /* True when we want to warn
about AVX512F ABI. */
int warn_avx; /* True when we want to warn about AVX ABI. */
int warn_sse; /* True when we want to warn about SSE ABI. */
int warn_mmx; /* True when we want to warn about MMX ABI. */
int sse_regno; /* next available sse register number */
int mmx_words; /* # mmx words passed so far */
int mmx_nregs; /* # mmx registers available for passing */
int mmx_regno; /* next available mmx register number */
int maybe_vaarg; /* true for calls to possibly vardic fncts. */
int caller; /* true if it is caller. */
int float_in_sse; /* Set to 1 or 2 for 32bit targets if
SFmode/DFmode arguments should be passed
in SSE registers. Otherwise 0. */
int bnd_regno; /* next available bnd register number */
int bnds_in_bt; /* number of bounds expected in BT. */
int force_bnd_pass; /* number of bounds expected for stdarg arg. */
int stdarg; /* Set to 1 if function is stdarg. */
enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
MS_ABI for ms abi. */
} CUMULATIVE_ARGS;
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
(N_NAMED_ARGS) != -1)
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. */
#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
#define MCOUNT_NAME "_mcount"
#define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
#define PROFILE_COUNT_REGISTER "edx"
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. The value is tested only in
functions that have frame pointers.
No definition is equivalent to always zero. */
/* Note on the 386 it might be more efficient not to define this since
we have to restore it ourselves from the frame pointer, in order to
use pop */
#define EXIT_IGNORE_STACK 1
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts. */
/* On the 386, the trampoline contains two instructions:
mov #STATIC,ecx
jmp FUNCTION
The trampoline is generated entirely at runtime. The operand of JMP
is the address of FUNCTION relative to the instruction following the
JMP (which is 5 bytes long). */
/* Length in units of the trampoline for entering a nested function. */
#define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)
/* Definitions for register eliminations.
This is an array of structures. Each structure initializes one pair
of eliminable registers. The "from" register number is given first,
followed by "to". Eliminations of the same "from" register are listed
in order of preference.
There are two registers that can always be eliminated on the i386.
The frame pointer and the arg pointer can be replaced by either the
hard frame pointer or to the stack pointer, depending upon the
circumstances. The hard frame pointer is not used before reload and
so it is not eligible for elimination. */
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
/* Define the offset between two registers, one to be eliminated, and the other
its replacement, at the start of a routine. */
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
/* Addressing modes, and classification of registers for them. */
/* Macros to check register numbers against specific register classes. */
/* These assume that REGNO is a hard or pseudo reg number.
They give nonzero only if REGNO is a hard reg of the suitable class
or a pseudo reg currently allocated to a suitable hard reg.
Since they use reg_renumber, they are safe only once reg_renumber
has been allocated, which happens in reginfo.c during register
allocation. */
#define REGNO_OK_FOR_INDEX_P(REGNO) \
((REGNO) < STACK_POINTER_REGNUM \
|| REX_INT_REGNO_P (REGNO) \
|| (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
|| REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
#define REGNO_OK_FOR_BASE_P(REGNO) \
(GENERAL_REGNO_P (REGNO) \
|| (REGNO) == ARG_POINTER_REGNUM \
|| (REGNO) == FRAME_POINTER_REGNUM \
|| GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
We have two alternate definitions for each of them.
The usual definition accepts all pseudo regs; the other rejects
them unless they have been allocated suitable hard regs.
The symbol REG_OK_STRICT causes the latter definition to be used.
Most source files want to accept pseudo regs in the hope that
they will get allocated to the class that the insn wants them to be in.
Source files for reload pass need to be strict.
After reload, it makes no difference, since pseudo regs have
been eliminated by then. */
/* Non strict versions, pseudos are ok. */
#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
(REGNO (X) < STACK_POINTER_REGNUM \
|| REX_INT_REGNO_P (REGNO (X)) \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
(GENERAL_REGNO_P (REGNO (X)) \
|| REGNO (X) == ARG_POINTER_REGNUM \
|| REGNO (X) == FRAME_POINTER_REGNUM \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
/* Strict versions, hard registers only */
#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#ifndef REG_OK_STRICT
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
#else
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
#endif
/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
that is a valid memory address for an instruction.
The MODE argument is the machine mode for the MEM expression
that wants to use this address.
The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
except for CONSTANT_ADDRESS_P which is usually machine-independent.
See legitimize_pic_address in i386.c for details as to what
constitutes a legitimate address when -fpic is used. */
#define MAX_REGS_PER_ADDRESS 2
#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
/* Try a machine-dependent way of reloading an illegitimate address
operand. If we find one, push the reload and jump to WIN. This
macro is used in only one place: `find_reloads_address' in reload.c. */
#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \
do { \
if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \
(int)(TYPE), (INDL))) \
goto WIN; \
} while (0)
/* If defined, a C expression to determine the base term of address X.
This macro is used in only one place: `find_base_term' in alias.c.
It is always safe for this macro to not be defined. It exists so
that alias analysis can understand machine-dependent addresses.
The typical use of this macro is to handle addresses containing
a label_ref or symbol_ref within an UNSPEC. */
#define FIND_BASE_TERM(X) ix86_find_base_term (X)
/* Nonzero if the constant value X is a legitimate general operand
when generating PIC code. It is given that flag_pic is on and
that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
#define SYMBOLIC_CONST(X) \
(GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == LABEL_REF \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
/* Max number of args passed in registers. If this is more than 3, we will
have problems with ebx (register #4), since it is a caller save register and
is also used as the pic register in ELF. So for now, don't allow more than
3 registers to be passed in registers. */
/* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
#define X86_64_REGPARM_MAX 6
#define X86_64_MS_REGPARM_MAX 4
#define X86_32_REGPARM_MAX 3
#define REGPARM_MAX \
(TARGET_64BIT \
? (TARGET_64BIT_MS_ABI \
? X86_64_MS_REGPARM_MAX \
: X86_64_REGPARM_MAX) \
: X86_32_REGPARM_MAX)
#define X86_64_SSE_REGPARM_MAX 8
#define X86_64_MS_SSE_REGPARM_MAX 4
#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
#define SSE_REGPARM_MAX \
(TARGET_64BIT \
? (TARGET_64BIT_MS_ABI \
? X86_64_MS_SSE_REGPARM_MAX \
: X86_64_SSE_REGPARM_MAX) \
: X86_32_SSE_REGPARM_MAX)
#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE \
(!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 1
/* Max number of bytes we can move from memory to memory
in one reasonably fast instruction. */
#define MOVE_MAX 16
/* MOVE_MAX_PIECES is the number of bytes at a time which we can
move efficiently, as opposed to MOVE_MAX which is the maximum
number of bytes we can move with a single instruction. */
#define MOVE_MAX_PIECES UNITS_PER_WORD
/* If a memory-to-memory move would take MOVE_RATIO or more simple
move-instruction pairs, we will do a movmem or libcall instead.
Increasing the value will always make code faster, but eventually
incurs high cost in increased code size.
If you don't define this, a reasonable default is used. */
#define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
/* If a clear memory operation would take CLEAR_RATIO or more simple
move-instruction sequences, we will do a clrmem or libcall instead. */
#define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
/* Define if shifts truncate the shift count which implies one can
omit a sign-extension or zero-extension of a shift count.
On i386, shifts do truncate the count. But bit test instructions
take the modulo of the bit offset operand. */
/* #define SHIFT_COUNT_TRUNCATED */
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
is done just by pretending it is already truncated. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
/* A macro to update M and UNSIGNEDP when an object whose type is
TYPE and which has the specified mode and signedness is to be
stored in a register. This macro is only called when TYPE is a
scalar type.
On i386 it is sometimes useful to promote HImode and QImode
quantities to SImode. The choice depends on target type. */
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
do { \
if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
|| ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
(MODE) = SImode; \
} while (0)
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode. */
#define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
/* Specify the machine mode that bounds have. */
#define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode)
/* A C expression whose value is zero if pointers that need to be extended
from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
greater then zero if they are zero-extended and less then zero if the
ptr_extend instruction should be used. */
#define POINTERS_EXTEND_UNSIGNED 1
/* A function address in a call instruction
is a byte address (for indexing purposes)
so give the MEM rtx a byte's mode. */
#define FUNCTION_MODE QImode
/* A C expression for the cost of a branch instruction. A value of 1
is the default; other values are interpreted relative to that. */
#define BRANCH_COST(speed_p, predictable_p) \
(!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
/* An integer expression for the size in bits of the largest integer machine
mode that should actually be used. We allow pairs of registers. */
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
/* Define this macro as a C expression which is nonzero if accessing
less than a word of memory (i.e. a `char' or a `short') is no
faster than accessing a word of memory, i.e., if such access
require more than one instruction or if there is no difference in
cost between byte and (aligned) word loads.
When this macro is not defined, the compiler will access a field by
finding the smallest containing object; when it is defined, a
fullword load will be used if alignment permits. Unless bytes
accesses are faster than word accesses, using word accesses is
preferable since it may eliminate subsequent memory access if
subsequent accesses occur to other fields in the same word of the
structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 0
/* Nonzero if access to memory by shorts is slow and undesirable. */
#define SLOW_SHORT_ACCESS 0
/* Define this macro to be the value 1 if unaligned accesses have a
cost many times greater than aligned accesses, for example if they
are emulated in a trap handler.
When this macro is nonzero, the compiler will act as if
`STRICT_ALIGNMENT' were nonzero when generating code for block
moves. This can cause significantly more instructions to be
produced. Therefore, do not set this macro nonzero if unaligned
accesses only add a cycle or two to the time for a memory access.
If the value of this macro is always zero, it need not be defined. */
/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
/* Define this macro if it is as good or better to call a constant
function address than to call an address kept in a register.
Desirable on the 386 because a CALL with a constant address is
faster than one with a register address. */
#define NO_FUNCTION_CSE
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison.
For floating-point equality comparisons, CCFPEQmode should be used.
VOIDmode should be used in all other cases.
For integer comparisons against zero, reduce to CCNOmode or CCZmode if
possible, to allow for more combinations. */
#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
/* Return nonzero if MODE implies a floating point inequality can be
reversed. */
#define REVERSIBLE_CC_MODE(MODE) 1
/* A C expression whose value is reversed condition code of the CODE for
comparison done in CC_MODE mode. */
#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
/* Control the assembler format that we output, to the extent
this does not vary between assemblers. */
/* How to refer to registers in assembler output.
This sequence is indexed by compiler's hard-register-number (see above). */
/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
For non floating point regs, the following are the HImode names.
For float regs, the stack top is sometimes referred to as "%st(0)"
instead of just "%st". TARGET_PRINT_OPERAND handles this with the
"y" code. */
#define HI_REGISTER_NAMES \
{"ax","dx","cx","bx","si","di","bp","sp", \
"st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
"argp", "flags", "fpsr", "fpcr", "frame", \
"xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
"xmm16", "xmm17", "xmm18", "xmm19", \
"xmm20", "xmm21", "xmm22", "xmm23", \
"xmm24", "xmm25", "xmm26", "xmm27", \
"xmm28", "xmm29", "xmm30", "xmm31", \
"k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \
"bnd0", "bnd1", "bnd2", "bnd3" }
#define REGISTER_NAMES HI_REGISTER_NAMES
/* Table of additional register names to use in user input. */
#define ADDITIONAL_REGISTER_NAMES \
{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
{ "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
{ "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
{ "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
{ "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
{ "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
{ "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \
{ "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \
{ "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \
{ "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \
{ "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \
{ "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \
{ "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \
{ "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \
{ "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \
{ "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \
{ "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \
{ "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \
{ "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \
{ "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \
{ "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \
{ "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} }
/* Note we are omitting these since currently I don't know how
to get gcc to use these, since they want the same but different
number as al, and ax.
*/
#define QI_REGISTER_NAMES \
{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
/* These parallel the array above, and can be used to access bits 8:15
of regs 0 through 3. */
#define QI_HIGH_REGISTER_NAMES \
{"ah", "dh", "ch", "bh", }
/* How to renumber registers for dbx and gdb. */
#define DBX_REGISTER_NUMBER(N) \
(TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
extern int const x86_64_ms_sysv_extra_clobbered_registers[12];
/* Before the prologue, RA is at 0(%esp). */
#define INCOMING_RETURN_ADDR_RTX \
gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
/* After the prologue, RA is at -4(AP) in the current frame. */
#define RETURN_ADDR_RTX(COUNT, FRAME) \
((COUNT) == 0 \
? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
-UNITS_PER_WORD)) \
: gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD)))
/* PC is dbx register 8; let's use that column for RA. */
#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
/* Before the prologue, the top of the frame is at 4(%esp). */
#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
/* Describe how we implement __builtin_eh_return. */
#define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
/* Select a format to encode pointers in exception handling data. CODE
is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
true if the symbol may be affected by dynamic relocations.
??? All x86 object file formats are capable of representing this.
After all, the relocation needed is the same as for the call insn.
Whether or not a particular assembler allows us to enter such, I
guess we'll have to see. */
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
asm_preferred_eh_data_format ((CODE), (GLOBAL))
/* This is how to output an insn to push a register on the stack.
It need not be very fast code. */
#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
do { \
if (TARGET_64BIT) \
asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
else \
asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
} while (0)
/* This is how to output an insn to pop a register from the stack.
It need not be very fast code. */
#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
do { \
if (TARGET_64BIT) \
asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
else \
asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
} while (0)
/* This is how to output an element of a case-vector that is absolute. */
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
ix86_output_addr_vec_elt ((FILE), (VALUE))
/* This is how to output an element of a case-vector that is relative. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
/* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
#define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
{ \
if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
(PTR) += TARGET_AVX ? 1 : 2; \
}
/* A C statement or statements which output an assembler instruction
opcode to the stdio stream STREAM. The macro-operand PTR is a
variable of type `char *' which points to the opcode name in
its "internal" form--the form that is written in the machine
description. */
#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
/* A C statement to output to the stdio stream FILE an assembler
command to pad the location counter to a multiple of 1<<LOG
bytes if it is within MAX_SKIP bytes. */
#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
#undef ASM_OUTPUT_MAX_SKIP_PAD
#define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
if ((LOG) != 0) \
{ \
if ((MAX_SKIP) == 0) \
fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
else \
fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
}
#endif
/* Write the extra assembler code needed to declare a function
properly. */
#undef ASM_OUTPUT_FUNCTION_LABEL
#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
ix86_asm_output_function_label (FILE, NAME, DECL)
/* Under some conditions we need jump tables in the text section,
because the assembler cannot handle label differences between
sections. This is the case for x86_64 on Mach-O for example. */
#define JUMP_TABLES_IN_TEXT_SECTION \
(flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
|| (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
and switch back. For x86 we do this only to save a few bytes that
would otherwise be unused in the text section. */
#define CRT_MKSTR2(VAL) #VAL
#define CRT_MKSTR(x) CRT_MKSTR2(x)
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n\t" \
"call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
TEXT_SECTION_ASM_OP);
/* Default threshold for putting data in large sections
with x86-64 medium memory model */
#define DEFAULT_LARGE_SECTION_THRESHOLD 65536
/* Which processor to tune code generation for. These must be in sync
with processor_target_table in i386.c. */
enum processor_type
{
PROCESSOR_GENERIC = 0,
PROCESSOR_I386, /* 80386 */
PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
PROCESSOR_PENTIUM,
PROCESSOR_PENTIUMPRO,
PROCESSOR_PENTIUM4,
PROCESSOR_NOCONA,
PROCESSOR_CORE2,
PROCESSOR_NEHALEM,
PROCESSOR_SANDYBRIDGE,
PROCESSOR_HASWELL,
PROCESSOR_BONNELL,
PROCESSOR_SILVERMONT,
PROCESSOR_KNL,
PROCESSOR_INTEL,
PROCESSOR_GEODE,
PROCESSOR_K6,
PROCESSOR_ATHLON,
PROCESSOR_K8,
PROCESSOR_AMDFAM10,
PROCESSOR_BDVER1,
PROCESSOR_BDVER2,
PROCESSOR_BDVER3,
PROCESSOR_BDVER4,
PROCESSOR_BTVER1,
PROCESSOR_BTVER2,
PROCESSOR_max
};
extern enum processor_type ix86_tune;
extern enum processor_type ix86_arch;
/* Size of the RED_ZONE area. */
#define RED_ZONE_SIZE 128
/* Reserved area of the red zone for temporaries. */
#define RED_ZONE_RESERVE 8
extern unsigned int ix86_preferred_stack_boundary;
extern unsigned int ix86_incoming_stack_boundary;
/* Smallest class containing REGNO. */
extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
enum ix86_fpcmp_strategy {
IX86_FPCMP_SAHF,
IX86_FPCMP_COMI,
IX86_FPCMP_ARITH
};
/* To properly truncate FP values into integers, we need to set i387 control
word. We can't emit proper mode switching code before reload, as spills
generated by reload may truncate values incorrectly, but we still can avoid
redundant computation of new control word by the mode switching pass.
The fldcw instructions are still emitted redundantly, but this is probably
not going to be noticeable problem, as most CPUs do have fast path for
the sequence.
The machinery is to emit simple truncation instructions and split them
before reload to instructions having USEs of two memory locations that
are filled by this code to old and new control word.
Post-reload pass may be later used to eliminate the redundant fildcw if
needed. */
enum ix86_entity
{
AVX_U128 = 0,
I387_TRUNC,
I387_FLOOR,
I387_CEIL,
I387_MASK_PM,
MAX_386_ENTITIES
};
enum ix86_stack_slot
{
SLOT_TEMP = 0,
SLOT_CW_STORED,
SLOT_CW_TRUNC,
SLOT_CW_FLOOR,
SLOT_CW_CEIL,
SLOT_CW_MASK_PM,
MAX_386_STACK_LOCALS
};
enum avx_u128_state
{
AVX_U128_CLEAN,
AVX_U128_DIRTY,
AVX_U128_ANY
};
/* Define this macro if the port needs extra instructions inserted
for mode switching in an optimizing compilation. */
#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
ix86_optimize_mode_switching[(ENTITY)]
/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
initializer for an array of integers. Each initializer element N
refers to an entity that needs mode switching, and specifies the
number of different modes that might need to be set for this
entity. The position of the initializer in the initializer -
starting counting at zero - determines the integer that is used to
refer to the mode-switched entity in question. */
#define NUM_MODES_FOR_MODE_SWITCHING \
{ AVX_U128_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
/* Avoid renaming of stack registers, as doing so in combination with
scheduling just increases amount of live registers at time and in
the turn amount of fxch instructions needed.
??? Maybe Pentium chips benefits from renaming, someone can try....
Don't rename evex to non-evex sse registers. */
#define HARD_REGNO_RENAME_OK(SRC, TARGET) (!STACK_REGNO_P (SRC) && \
(EXT_REX_SSE_REGNO_P (SRC) == \
EXT_REX_SSE_REGNO_P (TARGET)))
#define FASTCALL_PREFIX '@'
/* Machine specific frame tracking during prologue/epilogue generation. */
#ifndef USED_FOR_TARGET
// struct GTY
// {
// /* This pair tracks the currently active CFA as reg+offset. When reg
// is drap_reg, we don't bother trying to record here the real CFA when
// it might really be a DW_CFA_def_cfa_expression. */
// rtx cfa_reg;
// HOST_WIDE_INT cfa_offset;
// /* The current offset (canonically from the CFA) of ESP and EBP.
// When stack frame re-alignment is active, these may not be relative
// to the CFA. However, in all cases they are relative to the offsets
// of the saved registers stored in ix86_frame. */
// HOST_WIDE_INT sp_offset;
// HOST_WIDE_INT fp_offset;
// The size of the red-zone that may be assumed for the purposes of
// eliding register restore notes in the epilogue. This may be zero
// if no red-zone is in effect, or may be reduced from the real
// red-zone value by a maximum runtime stack re-alignment value.
// int red_zone_offset;
// /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
// value within the frame. If false then the offset above should be
// ignored. Note that DRAP, if valid, *always* points to the CFA and
// thus has an offset of zero. */
// BOOL_BITFIELD sp_valid : 1;
// BOOL_BITFIELD fp_valid : 1;
// BOOL_BITFIELD drap_valid : 1;
// /* Indicate whether the local stack frame has been re-aligned. When
// set, the SP/FP offsets above are relative to the aligned frame
// and not the CFA. */
// BOOL_BITFIELD realigned : 1;
// };
/* Private to winnt.c. */
struct seh_frame_state;
// struct GTY(()) machine_function {
// struct stack_local_entry *stack_locals;
// const char *some_ld_name;
// int varargs_gpr_size;
// int varargs_fpr_size;
// int optimize_mode_switching[MAX_386_ENTITIES];
// /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE
// has been computed for. */
// int use_fast_prologue_epilogue_nregs;
// /* For -fsplit-stack support: A stack local which holds a pointer to
// the stack arguments for a function with a variable number of
// arguments. This is set at the start of the function and is used
// to initialize the overflow_arg_area field of the va_list
// structure. */
// rtx split_stack_varargs_pointer;
// /* This value is used for amd64 targets and specifies the current abi
// to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
// ENUM_BITFIELD(calling_abi) call_abi : 8;
// /* Nonzero if the function accesses a previous frame. */
// BOOL_BITFIELD accesses_prev_frame : 1;
// /* Nonzero if the function requires a CLD in the prologue. */
// BOOL_BITFIELD needs_cld : 1;
// /* Set by ix86_compute_frame_layout and used by prologue/epilogue
// expander to determine the style used. */
// BOOL_BITFIELD use_fast_prologue_epilogue : 1;
// /* If true, the current function needs the default PIC register, not
// an alternate register (on x86) and must not use the red zone (on
// x86_64), even if it's a leaf function. We don't want the
// function to be regarded as non-leaf because TLS calls need not
// affect register allocation. This flag is set when a TLS call
// instruction is expanded within a function, and never reset, even
// if all such instructions are optimized away. Use the
// ix86_current_function_calls_tls_descriptor macro for a better
// approximation. */
// BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
// /* If true, the current function has a STATIC_CHAIN is placed on the
// stack below the return address. */
// BOOL_BITFIELD static_chain_on_stack : 1;
// /* If true, it is safe to not save/restore DRAP register. */
// BOOL_BITFIELD no_drap_save_restore : 1;
// /* During prologue/epilogue generation, the current frame state.
// Otherwise, the frame state at the end of the prologue. */
// struct machine_frame_state fs;
// /* During SEH output, this is non-null. */
// struct seh_frame_state * GTY((skip(""))) seh;
// };
#endif
#define ix86_stack_locals (cfun->machine->stack_locals)
#define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
#define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
#define ix86_current_function_needs_cld (cfun->machine->needs_cld)
#define ix86_tls_descriptor_calls_expanded_in_cfun \
(cfun->machine->tls_descriptor_call_expanded_p)
/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
calls are optimized away, we try to detect cases in which it was
optimized away. Since such instructions (use (reg REG_SP)), we can
verify whether there's any such instruction live by testing that
REG_SP is live. */
#define ix86_current_function_calls_tls_descriptor \
(ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
#define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
/* Control behavior of x86_file_start. */
#define X86_FILE_START_VERSION_DIRECTIVE false
#define X86_FILE_START_FLTUSED false
/* Flag to mark data that is in the large address area. */
#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
#define SYMBOL_REF_FAR_ADDR_P(X) \
((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
/* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
have defined always, to avoid ifdefing. */
#define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
#define SYMBOL_REF_DLLIMPORT_P(X) \
((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
#define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
#define SYMBOL_REF_DLLEXPORT_P(X) \
((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
#define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4)
#define SYMBOL_REF_STUBVAR_P(X) \
((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0)
extern void debug_ready_dispatch (void);
extern void debug_dispatch_window (int);
/* The value at zero is only defined for the BMI instructions
LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0)
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0)
/* Flags returned by ix86_get_callcvt (). */
#define IX86_CALLCVT_CDECL 0x1
#define IX86_CALLCVT_STDCALL 0x2
#define IX86_CALLCVT_FASTCALL 0x4
#define IX86_CALLCVT_THISCALL 0x8
#define IX86_CALLCVT_REGPARM 0x10
#define IX86_CALLCVT_SSEREGPARM 0x20
#define IX86_BASE_CALLCVT(FLAGS) \
((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
| IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
#define RECIP_MASK_NONE 0x00
#define RECIP_MASK_DIV 0x01
#define RECIP_MASK_SQRT 0x02
#define RECIP_MASK_VEC_DIV 0x04
#define RECIP_MASK_VEC_SQRT 0x08
#define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
| RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
#define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
#define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
#define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
#define IX86_HLE_ACQUIRE (1 << 16)
#define IX86_HLE_RELEASE (1 << 17)
/* For switching between functions with different target attributes. */
#define SWITCHABLE_TARGET 1
/*
Local variables:
version-control: t
End:
*/
#include <stdarg.h>
#include <string.h>
#include <stdlib.h>
static inline unsigned long vconcat_length (const char *, va_list);
static inline unsigned long
vconcat_length (const char *first, va_list args)
{
unsigned long length = 0;
const char *arg;
for (arg = first; arg ; arg = va_arg (args, const char *))
length += strlen (arg);
return length;
}
static inline char *
vconcat_copy (char *dst, const char *first, va_list args)
{
char *end = dst;
const char *arg;
for (arg = first; arg ; arg = va_arg (args, const char *))
{
unsigned long length = strlen (arg);
memcpy (end, arg, length);
end += length;
}
*end = '\000';
return dst;
}
/* @undocumented concat_length */
unsigned long
concat_length (const char *first, ...)
{
unsigned long length;
va_list args;
va_start (args, first);
length = vconcat_length (first, args);
va_end (args);
return length;
}
/* @undocumented concat_copy */
char *
concat_copy (char *dst, const char *first, ...)
{
char *save_dst;
va_list args;
va_start (args, first);
vconcat_copy (dst, first, args);
save_dst = dst; /* With K&R C, dst goes out of scope here. */
va_end (args);
return save_dst;
}
char *libiberty_concat_ptr;
/* @undocumented concat_copy2 */
char *
concat_copy2 (const char *first, ...)
{
va_list args;
va_start (args, first);
vconcat_copy (libiberty_concat_ptr, first, args);
va_end (args);
return libiberty_concat_ptr;
}
char *
concat (const char *first, ...)
{
char *newstr;
va_list args;
/* First compute the size of the result and get sufficient memory. */
va_start (args, first);
newstr = (char*)malloc(vconcat_length (first, args) + 1);
va_end (args);
/* Now copy the individual pieces to the result string. */
va_start (args, first);
vconcat_copy (newstr, first, args);
va_end (args);
return newstr;
}
const char *host_detect_local_cpu (int argc, const char **argv);
struct cache_desc
{
unsigned sizekb;
unsigned assoc;
unsigned line;
};
// enum processor_type
// {
// PROCESSOR_GENERIC = 0,
// PROCESSOR_I386, 80386
// PROCESSOR_BDVER4,
// PROCESSOR_BTVER1,
// PROCESSOR_BTVER2,
// PROCESSOR_max
// };
/* Returns command line parameters that describe size and
cache line size of the processor caches. */
static char *
describe_cache (struct cache_desc level1, struct cache_desc level2)
{
char size[100], line[100], size2[100];
/* At the moment, gcc does not use the information
about the associativity of the cache. */
snprintf (size, sizeof (size),
"--param l1-cache-size=%u ", level1.sizekb);
snprintf (line, sizeof (line),
"--param l1-cache-line-size=%u ", level1.line);
snprintf (size2, sizeof (size2),
"--param l2-cache-size=%u ", level2.sizekb);
return concat (size, line, size2, NULL);
}
/* Detect L2 cache parameters using CPUID extended function 0x80000006. */
static void
detect_l2_cache (struct cache_desc *level2)
{
unsigned eax, ebx, ecx, edx;
unsigned assoc;
__cpuid (0x80000006, eax, ebx, ecx, edx);
level2->sizekb = (ecx >> 16) & 0xffff;
level2->line = ecx & 0xff;
assoc = (ecx >> 12) & 0xf;
if (assoc == 6)
assoc = 8;
else if (assoc == 8)
assoc = 16;
else if (assoc >= 0xa && assoc <= 0xc)
assoc = 32 + (assoc - 0xa) * 16;
else if (assoc >= 0xd && assoc <= 0xe)
assoc = 96 + (assoc - 0xd) * 32;
level2->assoc = assoc;
}
/* Returns the description of caches for an AMD processor. */
static const char *
detect_caches_amd (unsigned max_ext_level)
{
unsigned eax, ebx, ecx, edx;
struct cache_desc level1, level2 = {0, 0, 0};
if (max_ext_level < 0x80000005)
return "";
__cpuid (0x80000005, eax, ebx, ecx, edx);
level1.sizekb = (ecx >> 24) & 0xff;
level1.assoc = (ecx >> 16) & 0xff;
level1.line = ecx & 0xff;
if (max_ext_level >= 0x80000006)
detect_l2_cache (&level2);
return describe_cache (level1, level2);
}
/* Decodes the size, the associativity and the cache line size of
L1/L2 caches of an Intel processor. Values are based on
"Intel Processor Identification and the CPUID Instruction"
[Application Note 485], revision -032, December 2007. */
static void
decode_caches_intel (unsigned reg, bool xeon_mp,
struct cache_desc *level1, struct cache_desc *level2)
{
int i;
for (i = 24; i >= 0; i -= 8)
switch ((reg >> i) & 0xff)
{
case 0x0a:
level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
break;
case 0x0c:
level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
break;
case 0x0d:
level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
break;
case 0x0e:
level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
break;
case 0x21:
level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
break;
case 0x24:
level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
break;
case 0x2c:
level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
break;
case 0x39:
level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
break;
case 0x3a:
level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
break;
case 0x3b:
level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
break;
case 0x3c:
level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
break;
case 0x3d:
level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
break;
case 0x3e:
level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
break;
case 0x41:
level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
break;
case 0x42:
level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
break;
case 0x43:
level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
break;
case 0x44:
level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
break;
case 0x45:
level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
break;
case 0x48:
level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
break;
case 0x49:
if (xeon_mp)
break;
level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
break;
case 0x4e:
level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
break;
case 0x60:
level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
break;
case 0x66:
level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
break;
case 0x67:
level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
break;
case 0x68:
level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
break;
case 0x78:
level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
break;
case 0x79:
level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
break;
case 0x7a:
level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
break;
case 0x7b:
level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
break;
case 0x7c:
level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
break;
case 0x7d:
level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
break;
case 0x7f:
level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
break;
case 0x80:
level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
break;
case 0x82:
level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
break;
case 0x83:
level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
break;
case 0x84:
level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
break;
case 0x85:
level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
break;
case 0x86:
level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
break;
case 0x87:
level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
default:
break;
}
}
/* Detect cache parameters using CPUID function 2. */
static void
detect_caches_cpuid2 (bool xeon_mp,
struct cache_desc *level1, struct cache_desc *level2)
{
unsigned regs[4];
int nreps, i;
__cpuid (2, regs[0], regs[1], regs[2], regs[3]);
nreps = regs[0] & 0x0f;
regs[0] &= ~0x0f;
while (--nreps >= 0)
{
for (i = 0; i < 4; i++)
if (regs[i] && !((regs[i] >> 31) & 1))
decode_caches_intel (regs[i], xeon_mp, level1, level2);
if (nreps)
__cpuid (2, regs[0], regs[1], regs[2], regs[3]);
}
}
/* Detect cache parameters using CPUID function 4. This
method doesn't require hardcoded tables. */
enum cache_type
{
CACHE_END = 0,
CACHE_DATA = 1,
CACHE_INST = 2,
CACHE_UNIFIED = 3
};
static void
detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
struct cache_desc *level3)
{
struct cache_desc *cache;
unsigned eax, ebx, ecx, edx;
int count;
for (count = 0;; count++)
{
__cpuid_count(4, count, eax, ebx, ecx, edx);
switch (eax & 0x1f)
{
case CACHE_END:
return;
case CACHE_DATA:
case CACHE_UNIFIED:
{
switch ((eax >> 5) & 0x07)
{
case 1:
cache = level1;
break;
case 2:
cache = level2;
break;
case 3:
cache = level3;
break;
default:
cache = NULL;
}
if (cache)
{
unsigned sets = ecx + 1;
unsigned part = ((ebx >> 12) & 0x03ff) + 1;
cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
cache->line = (ebx & 0x0fff) + 1;
cache->sizekb = (cache->assoc * part
* cache->line * sets) / 1024;
}
}
default:
break;
}
}
}
/* Returns the description of caches for an Intel processor. */
static const char *
detect_caches_intel (bool xeon_mp, unsigned max_level,
unsigned max_ext_level, unsigned *l2sizekb)
{
struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
if (max_level >= 4)
detect_caches_cpuid4 (&level1, &level2, &level3);
else if (max_level >= 2)
detect_caches_cpuid2 (xeon_mp, &level1, &level2);
else
return "";
if (level1.sizekb == 0)
return "";
/* Let the L3 replace the L2. This assumes inclusive caches
and single threaded program for now. */
if (level3.sizekb)
level2 = level3;
/* Intel CPUs are equipped with AMD style L2 cache info. Try this
method if other methods fail to provide L2 cache parameters. */
if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
detect_l2_cache (&level2);
*l2sizekb = level2.sizekb;
return describe_cache (level1, level2);
}
/* This will be called by the spec parser in gcc.c when it sees
a %:local_cpu_detect(args) construct. Currently it will be called
with either "arch" or "tune" as argument depending on if -march=native
or -mtune=native is to be substituted.
It returns a string containing new command line parameters to be
put at the place of the above two options, depending on what CPU
this is executed. E.g. "-march=k8" on an AMD64 machine
for -march=native.
ARGC and ARGV are set depending on the actual arguments given
in the spec. */
const char *host_detect_local_cpu (int argc, const char **argv)
{
enum processor_type processor = PROCESSOR_I386;
const char *cpu = "i386";
const char *cache = "";
const char *options = "";
unsigned int eax, ebx, ecx, edx;
unsigned int max_level, ext_level;
unsigned int vendor;
unsigned int model, family;
unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
/* Extended features */
unsigned int has_lahf_lm = 0, has_sse4a = 0;
unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
unsigned int has_hle = 0, has_rtm = 0;
unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
unsigned int has_pcommit = 0;
bool arch = true;
unsigned int l2sizekb = 0;
max_level = __get_cpuid_max (0, &vendor);
if (max_level < 1)
goto done;
__cpuid (1, eax, ebx, ecx, edx);
model = (eax >> 4) & 0x0f;
family = (eax >> 8) & 0x0f;
if (vendor == signature_INTEL_ebx
|| vendor == signature_AMD_ebx)
{
unsigned int extended_model, extended_family;
extended_model = (eax >> 12) & 0xf0;
extended_family = (eax >> 20) & 0xff;
if (family == 0x0f)
{
family += extended_family;
model += extended_model;
}
else if (family == 0x06)
model += extended_model;
}
has_sse3 = ecx & bit_SSE3;
has_ssse3 = ecx & bit_SSSE3;
has_sse4_1 = ecx & bit_SSE4_1;
has_sse4_2 = ecx & bit_SSE4_2;
has_avx = ecx & bit_AVX;
has_osxsave = ecx & bit_OSXSAVE;
has_cmpxchg16b = ecx & bit_CMPXCHG16B;
has_movbe = ecx & bit_MOVBE;
has_popcnt = ecx & bit_POPCNT;
has_aes = ecx & bit_AES;
has_pclmul = ecx & bit_PCLMUL;
has_fma = ecx & bit_FMA;
has_f16c = ecx & bit_F16C;
has_rdrnd = ecx & bit_RDRND;
has_xsave = ecx & bit_XSAVE;
has_cmpxchg8b = edx & bit_CMPXCHG8B;
has_cmov = edx & bit_CMOV;
has_mmx = edx & bit_MMX;
has_fxsr = edx & bit_FXSAVE;
has_sse = edx & bit_SSE;
has_sse2 = edx & bit_SSE2;
if (max_level >= 7)
{
__cpuid_count (7, 0, eax, ebx, ecx, edx);
has_bmi = ebx & bit_BMI;
has_hle = ebx & bit_HLE;
has_rtm = ebx & bit_RTM;
has_avx2 = ebx & bit_AVX2;
has_bmi2 = ebx & bit_BMI2;
has_fsgsbase = ebx & bit_FSGSBASE;
has_rdseed = ebx & bit_RDSEED;
has_adx = ebx & bit_ADX;
has_avx512f = ebx & bit_AVX512F;
has_avx512er = ebx & bit_AVX512ER;
has_avx512pf = ebx & bit_AVX512PF;
has_avx512cd = ebx & bit_AVX512CD;
has_sha = ebx & bit_SHA;
has_pcommit = ebx & bit_PCOMMIT;
has_clflushopt = ebx & bit_CLFLUSHOPT;
has_clwb = ebx & bit_CLWB;
has_avx512dq = ebx & bit_AVX512DQ;
has_avx512bw = ebx & bit_AVX512BW;
has_avx512vl = ebx & bit_AVX512VL;
has_avx512vl = ebx & bit_AVX512IFMA;
has_prefetchwt1 = ecx & bit_PREFETCHWT1;
has_avx512vl = ecx & bit_AVX512VBMI;
}
if (max_level >= 13)
{
__cpuid_count (13, 1, eax, ebx, ecx, edx);
has_xsaveopt = eax & bit_XSAVEOPT;
has_xsavec = eax & bit_XSAVEC;
has_xsaves = eax & bit_XSAVES;
}
/* Check cpuid level of extended features. */
__cpuid (0x80000000, ext_level, ebx, ecx, edx);
if (ext_level > 0x80000000)
{
__cpuid (0x80000001, eax, ebx, ecx, edx);
has_lahf_lm = ecx & bit_LAHF_LM;
has_sse4a = ecx & bit_SSE4a;
has_abm = ecx & bit_ABM;
has_lwp = ecx & bit_LWP;
has_fma4 = ecx & bit_FMA4;
has_xop = ecx & bit_XOP;
has_tbm = ecx & bit_TBM;
has_lzcnt = ecx & bit_LZCNT;
has_prfchw = ecx & bit_PRFCHW;
has_longmode = edx & bit_LM;
has_3dnowp = edx & bit_3DNOWP;
has_3dnow = edx & bit_3DNOW;
}
/* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */
#define XCR_XFEATURE_ENABLED_MASK 0x0
#define XSTATE_FP 0x1
#define XSTATE_SSE 0x2
#define XSTATE_YMM 0x4
#define XSTATE_OPMASK 0x20
#define XSTATE_ZMM 0x40
#define XSTATE_HI_ZMM 0x80
if (has_osxsave)
asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
: "=a" (eax), "=d" (edx)
: "c" (XCR_XFEATURE_ENABLED_MASK));
/* Check if SSE and YMM states are supported. */
if (!has_osxsave
|| (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
{
has_avx = 0;
has_avx2 = 0;
has_fma = 0;
has_fma4 = 0;
has_f16c = 0;
has_xop = 0;
has_xsave = 0;
has_xsaveopt = 0;
has_xsaves = 0;
has_xsavec = 0;
}
if (!has_osxsave
|| (eax &
(XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM))
!= (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM))
{
has_avx512f = 0;
has_avx512er = 0;
has_avx512pf = 0;
has_avx512cd = 0;
has_avx512dq = 0;
has_avx512bw = 0;
has_avx512vl = 0;
}
if (!arch)
{
if (vendor == signature_AMD_ebx
|| vendor == signature_CENTAUR_ebx
|| vendor == signature_CYRIX_ebx
|| vendor == signature_NSC_ebx)
cache = detect_caches_amd (ext_level);
else if (vendor == signature_INTEL_ebx)
{
bool xeon_mp = (family == 15 && model == 6);
cache = detect_caches_intel (xeon_mp, max_level,
ext_level, &l2sizekb);
}
}
if (vendor == signature_AMD_ebx)
{
unsigned int name;
/* Detect geode processor by its processor signature. */
if (ext_level > 0x80000001)
__cpuid (0x80000002, name, ebx, ecx, edx);
else
name = 0;
if (name == signature_NSC_ebx)
processor = PROCESSOR_GEODE;
else if (has_movbe && family == 22)
processor = PROCESSOR_BTVER2;
else if (has_avx2)
processor = PROCESSOR_BDVER4;
else if (has_xsaveopt)
processor = PROCESSOR_BDVER3;
else if (has_bmi)
processor = PROCESSOR_BDVER2;
else if (has_xop)
processor = PROCESSOR_BDVER1;
else if (has_sse4a && has_ssse3)
processor = PROCESSOR_BTVER1;
else if (has_sse4a)
processor = PROCESSOR_AMDFAM10;
else if (has_sse2 || has_longmode)
processor = PROCESSOR_K8;
else if (has_3dnowp && family == 6)
processor = PROCESSOR_ATHLON;
else if (has_mmx)
processor = PROCESSOR_K6;
else
processor = PROCESSOR_PENTIUM;
}
else if (vendor == signature_CENTAUR_ebx)
{
if (arch)
{
switch (family)
{
case 6:
if (model > 9)
/* Use the default detection procedure. */
processor = PROCESSOR_GENERIC;
else if (model == 9)
cpu = "c3-2";
else if (model >= 6)
cpu = "c3";
else
processor = PROCESSOR_GENERIC;
break;
case 5:
if (has_3dnow)
cpu = "winchip2";
else if (has_mmx)
cpu = "winchip2-c6";
else
processor = PROCESSOR_GENERIC;
break;
default:
/* We have no idea. */
processor = PROCESSOR_GENERIC;
}
}
}
else
{
switch (family)
{
case 4:
processor = PROCESSOR_I486;
break;
case 5:
processor = PROCESSOR_PENTIUM;
break;
case 6:
processor = PROCESSOR_PENTIUMPRO;
break;
case 15:
processor = PROCESSOR_PENTIUM4;
break;
default:
/* We have no idea. */
processor = PROCESSOR_GENERIC;
}
}
switch (processor)
{
case PROCESSOR_I386:
/* Default. */
break;
case PROCESSOR_I486:
cpu = "i486";
break;
case PROCESSOR_PENTIUM:
if (arch && has_mmx)
cpu = "pentium-mmx";
else
cpu = "pentium";
break;
case PROCESSOR_PENTIUMPRO:
switch (model)
{
case 0x1c:
case 0x26:
/* Bonnell. */
cpu = "bonnell";
break;
case 0x37:
case 0x4a:
case 0x4d:
case 0x5a:
case 0x5d:
/* Silvermont. */
cpu = "silvermont";
break;
case 0x0f:
/* Merom. */
case 0x17:
case 0x1d:
/* Penryn. */
cpu = "core2";
break;
case 0x1a:
case 0x1e:
case 0x1f:
case 0x2e:
/* Nehalem. */
cpu = "nehalem";
break;
case 0x25:
case 0x2c:
case 0x2f:
/* Westmere. */
cpu = "westmere";
break;
case 0x2a:
case 0x2d:
/* Sandy Bridge. */
cpu = "sandybridge";
break;
case 0x3a:
case 0x3e:
/* Ivy Bridge. */
cpu = "ivybridge";
break;
case 0x3c:
case 0x3f:
case 0x45:
case 0x46:
/* Haswell. */
cpu = "haswell";
break;
case 0x3d:
case 0x4f:
case 0x56:
/* Broadwell. */
cpu = "broadwell";
break;
case 0x57:
/* Knights Landing. */
cpu = "knl";
break;
default:
if (arch)
{
/* This is unknown family 0x6 CPU. */
/* Assume Knights Landing. */
if (has_avx512f)
cpu = "knl";
/* Assume Broadwell. */
else if (has_adx)
cpu = "broadwell";
else if (has_avx2)
/* Assume Haswell. */
cpu = "haswell";
else if (has_avx)
/* Assume Sandy Bridge. */
cpu = "sandybridge";
else if (has_sse4_2)
{
if (has_movbe)
/* Assume Silvermont. */
cpu = "silvermont";
else
/* Assume Nehalem. */
cpu = "nehalem";
}
else if (has_ssse3)
{
if (has_movbe)
/* Assume Bonnell. */
cpu = "bonnell";
else
/* Assume Core 2. */
cpu = "core2";
}
else if (has_longmode)
/* Perhaps some emulator? Assume x86-64, otherwise gcc
-march=native would be unusable for 64-bit compilations,
as all the CPUs below are 32-bit only. */
cpu = "x86-64";
else if (has_sse3)
/* It is Core Duo. */
cpu = "pentium-m";
else if (has_sse2)
/* It is Pentium M. */
cpu = "pentium-m";
else if (has_sse)
/* It is Pentium III. */
cpu = "pentium3";
else if (has_mmx)
/* It is Pentium II. */
cpu = "pentium2";
else
/* Default to Pentium Pro. */
cpu = "pentiumpro";
}
else
/* For -mtune, we default to -mtune=generic. */
cpu = "generic";
break;
}
break;
case PROCESSOR_PENTIUM4:
if (has_sse3)
{
if (has_longmode)
cpu = "nocona";
else
cpu = "prescott";
}
else
cpu = "pentium4";
break;
case PROCESSOR_GEODE:
cpu = "geode";
break;
case PROCESSOR_K6:
if (arch && has_3dnow)
cpu = "k6-3";
else
cpu = "k6";
break;
case PROCESSOR_ATHLON:
if (arch && has_sse)
cpu = "athlon-4";
else
cpu = "athlon";
break;
case PROCESSOR_K8:
if (arch && has_sse3)
cpu = "k8-sse3";
else
cpu = "k8";
break;
case PROCESSOR_AMDFAM10:
cpu = "amdfam10";
break;
case PROCESSOR_BDVER1:
cpu = "bdver1";
break;
case PROCESSOR_BDVER2:
cpu = "bdver2";
break;
case PROCESSOR_BDVER3:
cpu = "bdver3";
break;
case PROCESSOR_BDVER4:
cpu = "bdver4";
break;
case PROCESSOR_BTVER1:
cpu = "btver1";
break;
case PROCESSOR_BTVER2:
cpu = "btver2";
break;
default:
/* Use something reasonable. */
if (arch)
{
if (has_ssse3)
cpu = "core2";
else if (has_sse3)
{
if (has_longmode)
cpu = "nocona";
else
cpu = "prescott";
}
else if (has_sse2)
cpu = "pentium4";
else if (has_cmov)
cpu = "pentiumpro";
else if (has_mmx)
cpu = "pentium-mmx";
else if (has_cmpxchg8b)
cpu = "pentium";
}
else
cpu = "generic";
}
if (arch)
{
const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
const char *sse = has_sse ? " -msse" : " -mno-sse";
const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
const char *aes = has_aes ? " -maes" : " -mno-aes";
const char *sha = has_sha ? " -msha" : " -mno-sha";
const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
const char *abm = has_abm ? " -mabm" : " -mno-abm";
const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
const char *fma = has_fma ? " -mfma" : " -mno-fma";
const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
const char *xop = has_xop ? " -mxop" : " -mno-xop";
const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
const char *avx = has_avx ? " -mavx" : " -mno-avx";
const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
const char *hle = has_hle ? " -mhle" : " -mno-hle";
const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
const char *adx = has_adx ? " -madx" : " -mno-adx";
const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
const char *pcommit = has_pcommit ? " -mpcommit" : " -mno-pcommit";
options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
sse4a, cx16, sahf, movbe, aes, sha, pclmul,
popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
fxsr, xsave, xsaveopt, avx512f, avx512er,
avx512cd, avx512pf, prefetchwt1, clflushopt,
xsavec, xsaves, avx512dq, avx512bw, avx512vl,
avx512ifma, avx512vbmi, clwb, pcommit, NULL);
}
done:
return concat (cache, "cpu=", cpu, options, NULL);
}
void
print_cpu_vendor()
{
unsigned vendor;
__get_cpuid_max (0, &vendor);
printf("CPU vendor: ");
switch(vendor){
case signature_INTEL_ebx:
printf("intel");
break;
case signature_AMD_ebx:
printf("amd");
break;
default:
printf("unknown");
break;
}
printf("\n");
}
void
print_cache_desc(struct cache_desc * desc)
{
printf("sizekb = %u, assoc = %u, line = %u\n", desc->sizekb, desc->assoc, desc->line);
}
int main(int argc, const char ** argv)
{
struct cache_desc cache_l2 = {0}, cache_l1 = {0};
printf("L2 cache: ");
detect_l2_cache(&cache_l2);
print_cache_desc(&cache_l2);
// printf("L1 cache: ");
// detect_caches_amd(&cache_l1);
// print_cache_desc(&cache_l1);
print_cpu_vendor();
const char * str = host_detect_local_cpu(argc, argv);
printf("%s\n", str);
return 0;
}
Raw
num-core.c
// http://stackoverflow.com/a/29761237/2566213
#include <stdio.h>
#include <stdint.h>
#include <unistd.h>
int
main(void)
{
uint32_t registers[4];
unsigned logicalcpucount;
unsigned physicalcpucount;
logicalcpucount = sysconf( _SC_NPROCESSORS_ONLN );
__asm__ __volatile__ (
"cpuid " :
"=a" (registers[0]),
"=b" (registers[1]),
"=c" (registers[2]),
"=d" (registers[3])
: "a" (1), "c" (0));
unsigned CPUFeatureSet = registers[3];
bool hyperthreading = CPUFeatureSet & (1 << 28);
if (hyperthreading){
physicalcpucount = logicalcpucount / 2;
} else {
physicalcpucount = logicalcpucount;
}
printf("LOGICAL: %i\n", logicalcpucount);
printf("PHYSICAL: %i\n", physicalcpucount);
}
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