FSM in VHDL

main.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

--use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY main IS
	PORT(	clk, reset, btn: IN STD_LOGIC;
		led: OUT STD_LOGIC_VECTOR(7 downto 0)
	);
		
	
END main;

ARCHITECTURE fsm OF main IS
	TYPE state is (S0, S1);
	SIGNAL current_state, next_state: state;
BEGIN

	PROCESS(current_state, btn)
	BEGIN
		CASE current_state is
			WHEN S0 =>
				led <= "00000000"; -- do things for state 0
				IF btn='0' THEN		-- move to state 1 
					next_state <= S1;
				END IF;
			WHEN S1 =>
				led <= "00000001"; -- do things for state 1
				IF btn='0' THEN		-- move to state 0
					next_state <= S0;
				END IF;
		END CASE;
	END PROCESS;

	PROCESS(clk, reset)
	BEGIN
		IF (reset='0') THEN
			current_state <= S0;
		ELSIF (clk'EVENT AND clk='1') THEN
			current_state <= next_state;
		END IF;
	END PROCESS;

END fsm;