DCPU16InstrFormats.td

//===-- DCPU16InstrFormats.td - DCPU16 Instruction Formats -*- tablegen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source 
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
//
// DCPU16 instruction formats
//


// Format specifies the encoding used by the instruction.  This is part of the
// ad-hoc solution used to emit machine instruction encodings by our machine
// code emitter.
class Format<bits<2> val> {
	bits<2> Value = val;
}

def Basic   : Format<0>;
def Special : Format<1>;

class ValMode<bits<6> val> {
	bits<6> Value = val;
}


def ValReg       : ValMode<0>;  // register (includes SP/PC/O)
def ValRegInd    : ValMode<1>;  // [register] (includes SP)
def ValRegOff    : ValMode<2>;  // [next word + register]
def ValImmInd    : ValMode<3>;  // [next word]
def ValImm       : ValMode<4>;  // next word (literal)
def ValLit       : ValMode<5>;  // literal value 0x00-0x1f


// Generic DCPU16 Format
class DCPU16Inst<dag outs, dag ins, Format f,
                 string asmstr> : Instruction {
  field bits<16> Inst;

  let Namespace = "DCPU16";

  dag OutOperandList = outs;
  dag InOperandList  = ins;

  Format Form = f;

  // Define how we want to layout our TargetSpecific information field... This
  // should be kept up-to-date with the fields in the DCPU16InstrInfo.h file.
  let TSFlags{1-0} = Form.Value;

  let AsmString   = asmstr;
}

// DCPU16 Basic Instructions
class BForm<bits<4> opcode, ValMode a, ValMode b, string asmstr, 
            dag outs, dag ins, list<dag> pattern>
  : DCPU16Inst<outs, ins,  Basic, asmstr> {
  let Pattern = pattern;

  ValMode va = a;
  ValMode vb = b;
  
  let Inst{0-3} = opcode;
}

def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;

/*
IBasic: all the different addressing modes.
 r : Register -- X, SP, PC...
 m : Memory -- [X]...
 i : Immediate (0x405)
 a : Address ([0x1234])
 o : Register + Offset ([X+12])
*/

include "InstrMulti.gen"

DCPU16RegisterInfo.td

//===- DCPU16RegisterInfo.td - DCPU16 Register defs ----------*- tblgen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source 
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
//  Declarations that describe the DCPU16 register file
//===----------------------------------------------------------------------===//

class DCPU16Reg<bits<6> num, string n>: Register<n> {
  field bits<6> Num = num;
  let Namespace = "DCPU16";
}

//===----------------------------------------------------------------------===//
//  Registers
//===----------------------------------------------------------------------===//

def A : DCPU16Reg<0x00, "A">;
def B : DCPU16Reg<0x01, "B">;
def C : DCPU16Reg<0x02, "C">;
def X : DCPU16Reg<0x03, "X">;
def Y : DCPU16Reg<0x04, "Y">;
def Z : DCPU16Reg<0x05, "Z">;
def I : DCPU16Reg<0x06, "I">;
def J : DCPU16Reg<0x07, "J">;

def SP : DCPU16Reg<0x1b, "SP">;
def PC : DCPU16Reg<0x1c, "PC">;
def O  : DCPU16Reg<0x1d, "O">;

def GPR : RegisterClass<"DCPU16", [i16], 16,
  (add A, B, C, X, Y, Z, I, J, SP, PC, O)>;

def GPRInd : RegisterClass<"DCPU16", [i16], 16,
  (add A, B, C, X, Y, Z, I, J, SP)>;

def GPROff : RegisterClass<"DCPU16", [i16], 16,
  (add A, B, C, X, Y, Z, I, J)>;

fmtgen.py

modes = [
    ("Reg", "r", "GPRC", ""),
    ("RegInd", "m", "GPRIndC"),
    ("RedOff", "o", "GPRIndOffC"),
    ("Imm", "i", "i16imm"),
    ("IndImm", "a", 1, "i16imm"),
]

valmode = {
    "r": "Reg",
    "m": "RegInd",
    "i": "Imm",
    "a": "ImmInd",
    "o": "RegOff",
}

regclass = {
    "r": "GPR",
    "m": "GPRInd",
    "i": "i16imm",
    "a": "i16imm",
    "o": "GPROff"
}

asmstr = {
    "r": "{0}",
    "m": "[{0}]",
    "i": "{0}",
    "a": "[{0}]",
    "o": "[{0}+{1}]"
}

apat = {
    "r": "{0}:$a",
    "m": "{0}:$a",
    "i": "{0}:$a",
    "a": "addr:$a",
    "o": "(add {0}:$a, i16imm:$ao)"    
}

bpat = {
    "r": "{0}:$b",
    "m": "{0}:$b",
    "i": "{0}:$b",
    "a": "addr:$b",
    "o": "(add {0}:$b, i16imm:$bo)"    
}

print 'multiclass IBasic<bits<4> opc, string OpcStr, SDNode OpNode> {'

for a in "rmao":
    for b in "rmiao":
        va = valmode[a]
        vb = valmode[b]
        astr = asmstr[a].format('$a', '$oa')
        bstr = asmstr[b].format('$b', '$ob')
        ins = ["%s:$a" % regclass[a]]
        if a == "r":
            outs = " %s:$dst" % regclass[a]
        else:
            outs = ''

        if a == 'o':
            ins += ["i16imm:$oa"]

        ins += ["%s:$b" % regclass[b]]
        if b == 'o':
            ins += ["i16imm:$ob"]

        pa = apat[a].format(regclass[a])
        pb = bpat[b].format(regclass[b])

        if a in 'mao':
            pat = "(store (OpNode (load {pa}), {pb}), {pa})".format(pa=pa,pb=pb)
        else:
            pat = "(set {ra}:$dst, (OpNode {pa}, {pb}))".format(ra=regclass[a], pa=pa, pb=pb)

        print '''
    def {a}{b} : BForm<opc, Val{va}, Val{vb}, OpcStr # " {astr}, {bstr}", 
                       (outs{outs}), (ins {ins}),
                       [{pat}]>;'''.format(a=a, b=b, va=va, vb=vb, outs=outs, ins=', '.join(ins),
                        astr=astr, bstr=bstr, pat=pat)

print '}'