gistfile1.txt

diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 32ac6b6b7..c015e618a 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -25,6 +25,7 @@
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 #include <linux/slab.h>
+#include <linux/jiffies.h>
 
 #define TBG_SEL                0x0
 #define DIV_SEL0       0x4
@@ -541,7 +542,7 @@ static void clk_pm_cpu_set_rate_wa(struct clk_pm_cpu *pm_cpu,
         * We are going to L0 with rate >= 1GHz. Check whether we have been at
         * L1 for long enough time. If not, go to L1 for 20ms.
         */
-       if (pm_cpu->l1_expiration && jiffies >= pm_cpu->l1_expiration)
+       if (pm_cpu->l1_expiration && time_is_before_eq_jiffies(pm_cpu->l1_expiration))
                goto invalidate_l1_exp;
 
        regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD,
@@ -551,6 +552,8 @@ static void clk_pm_cpu_set_rate_wa(struct clk_pm_cpu *pm_cpu,
 
 invalidate_l1_exp:
        pm_cpu->l1_expiration = 0;
+
+       pr_info("clk_pm_cpu_set_rate_wa rate %lu to L1\n", rate);
 }
 
 static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -565,10 +568,14 @@ static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
        if (!armada_3700_pm_dvfs_is_enabled(base))
                return -EINVAL;
 
+       pr_info("%pCn requested rate %lu\n", hw, rate);
+
        for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
                unsigned int reg, mask, val,
                        offset = ARMADA_37XX_NB_TBG_DIV_OFF;
 
+               pr_info("%pCn requested rate %lu load_level %u\n", hw, rate, load_level);
+
                armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
 
                regmap_read(base, reg, &val);
@@ -588,6 +595,8 @@ static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
                        if (parent_rate >= 1000*1000*1000)
                                clk_pm_cpu_set_rate_wa(pm_cpu, load_level, rate, base);
 
+                       pr_info("%pCn load_level %u after workaround\n", hw, load_level);
+
                        regmap_update_bits(base, reg, mask, load_level);
 
                        return rate;
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
index c10fc33b2..b712849c2 100644
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
@@ -108,7 +108,7 @@ static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
         * The cpufreq scaling for 1.2 GHz variant of the SOC is currently
         * unstable because we do not know how to configure it properly.
         */
-       /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
+       {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
        {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
        {.cpu_freq_max = 800*1000*1000,  .divider = {1, 2, 3, 4} },
        {.cpu_freq_max = 600*1000*1000,  .divider = {2, 4, 5, 6} },
@@ -496,7 +496,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
                if (ret)
                        goto remove_opp;
 
-
+               dev_info(cpu_dev, "OPP[%u] %lu Hz %lu uV", load_lvl, freq, u_volt);
        }
 
        /* Now that everything is setup, enable the DVFS at hardware level */