Verilog configuration

config.v

config cfg;
  design top;
  instance top.aux_inst.mod_inst use mod2;
endconfig

module top (input a, output b);
  aux aux_inst (.a(a), .b(b));
endmodule

module aux (input a, output b);
  mod1 mod_inst (.a(a), .b(b));
endmodule

module mod1 (input a, output b);
  assign b = ~a;
endmodule

module mod2 (input a, output b);
  assign b = 1'b0;
endmodule