Verilog Code for the Week1 of Logic Design Lab, Contains 1 Example and 2 Questions

week1.v

/**** Example 1 **/
module lab1(x1,x2,x3,f);
input x1,x2,x3;
output f;
and(g,x1,x2);
not(h,x2);
and(k,h,x3);
or(f,g,k);
endmodule

//Behavioural 

module lab1(x1,x2,x3,f);
input x1,x2,x3;
output f;
assign f=(x1&x2)|(~x2&x3);
endmodule

/**** Program 1 ****/

module program1(x1,x2,x3,x4,f);
input x1,x2,x3,x4;
output f;
and(a,x1,x3);
and(b,x2,x4);
not(q,x2);
not(w,x3);
or(c,x1,w);
or(d,q,x4);
or(g,a,b);
and(h,c,d);
or(f,g,h);
endmodule

//Behavioural
module program1b(x1,x2,x3,x4,f);
input x1,x2,x3,x4;
output f;
assign f=((x1&x3)|(x2&x4))|((x1|~x3)&(~x2|x4))
endmodule

/*** Program 2 ***/
module program2(x1,x2,x3,f);
input x1,x2,x3;
output f;
not(q,x1);
not(w,x2);
not(e,x3);
or(a,x3,x2,x1);
or(b,x3,w,q);
or(c,x2,q,e);
or(d,w,e,x1);
and(f,a,b,c,d);
endmodule

//Behavioural
module program2b(x1,x2,x3,f);
input x1,x2,x3;
output f;
assign f=(x3|x2|x1)&(x3|~x2|~x1)&(x2|~x1|~x3)&(~x2|~x3|x1);
endmodule