ARM-843419.md

The following text is verbatim from the ARM Processor Cortex-A53 MPCore Product Revision r0 Software Developers Errata Notice.

Description

When executing in AArch64 state, a load or store instruction which uses the result of an ADRP instruction as a base register, or which uses a base register written by an instruction immediately after an ADRP to the same register, might access an incorrect address.

Configurations affected

All configurations of Cortex-A53 are affected.

Conditions

There are two instruction sequences which can trigger this erratum, both only in AArch64 state.

Sequence 1:

1. An ADRP instruction, which writes to a register Rn.

• This instruction must be located in memory at an address where the bottom 12 bits are equal to 0xFF8 or 0xFFC.

2. A load or store instruction:

• This can be:
  • A single register load or store, of either integer or vector registers
  • Or an STP or STNP, of either integer or vector registers
  • Or an Advanced SIMD ST1 store instruction.
• This must not write to Rn.
• This may optionally read Rn (either as an address register or a data register to be stored).
• If a load, this must access a region of memory which crosses a 64-bit boundary.
• If a store, this must access a region of memory which crosses a 128-bit boundary.

3. There can optionally be one instruction after instruction 2.

• This cannot be a branch.
• This cannot write Rn.
• This may optionally read Rn.

4. A load or store instruction from the "Load/store register (unsigned immediate)" encoding class, using Rn as the base address register.

Sequence 2:

1. An ADRP instruction, which writes to a register Rn.
2. Another instruction which writes to Rn.

• This cannot be a branch or an ADRP.
• This cannot read Rn.

3. Another instruction.

• This cannot be a branch.
• This cannot write Rn.
• This may optionally read Rn.

4. A load or store instruction from the "Load/store register (unsigned immediate)" encoding class, using Rn as the base address register.