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We fit a exponential function for $f$: $f(V) = a \exp(V / s)$ and obtain $a \approx 0.02485702\ \mathrm{A}$ and $s \approx 0.229551831\ \mathrm{V}$. With this the deviation from the measured values from the total model $P(V) = 414\ \mathrm{mW} + V · 130 · f(V)$ is always below $8 \ \mathrm{mW}$, indeed it is atmost $\approx 3.19\ \mathrm{mW}$ and on average $\approx 1.28\ \mathrm{mW}$.

When not taking a fixed offset of $414\ \mathrm{mW}$, but instead also leave this as a variable of the fit, we obtain $\approx 412.3\ \mathrm{mW}$ for the offset, $a \approx 0.0249451511\ \mathrm{A}$ and $s \approx 0.229653915\ \mathrm{V}$ with a maximum error of $\approx 2.28\ \mathrm{mW}$ and a average error of $\approx{0.74}\ \mathrm{mW}$.

use nix::sys::socket::{
recvmmsg, sendmmsg, socket, AddressFamily, MsgFlags, MultHdrs, SockFlag, SockProtocol,
SockType, SockaddrIn,
};
use std::io::{IoSlice, IoSliceMut};
use std::str::FromStr;
fn main() {
let sock_addr = SockaddrIn::from_str("127.0.0.1:6790").unwrap();
#include <cinttypes>
#include <cstdlib>
#include <cstring>
#include <cstdio>
#include <functional>
const uint8_t READ_FAILED = 0;
const uint8_t READ_SUCCESS = 1;
const uint8_t MAX_FIELDS = 8;
const uint32_t FIELDS_BUFFER_SIZE = 512;
#include <cinttypes>
#include <cstdlib>
#include <cstring>
#include <cstdio>
#include <functional>
const uint8_t READ_FAILED = 0;
const uint8_t READ_SUCCESS = 1;
const uint8_t MAX_FIELDS = 8;
const uint32_t FIELDS_BUFFER_SIZE = 512;
diff --git a/src/modules/ws2812.py b/src/modules/ws2812.py
index d369f16..d716201 100644
--- a/src/modules/ws2812.py
+++ b/src/modules/ws2812.py
@@ -64,12 +64,16 @@ class Ws2812Phy:
max_pattern_length = max([sum(pattern) for pattern in self.patterns])
counter = Signal(max=max_pattern_length)
+
+ dummy = Signal(max = len(self.patterns))
diff --git a/src/modules/ws2812.py b/src/modules/ws2812.py
index d369f16..0787e7e 100644
--- a/src/modules/ws2812.py
+++ b/src/modules/ws2812.py
@@ -12,7 +12,7 @@ class Ws2812:
def __init__(self, out, led_number, channels_per_led=3, bits=8):
self.out = out
- self.parallel_in = Array(Array(Signal(bits) for _ in range(channels_per_led)) for _ in range(led_number))
+ self.parallel_in = Array(Array(Array(Signal(bits)) for _ in range(channels_per_led)) for _ in range(led_number))
[
Some(List(MetaList { ident: Ident { sym: fuseable, span: #0 bytes(0..0), is_raw: false },
paren_token: Paren,
nested: [
Meta(List(MetaList {
ident: Ident { sym: virtual_field, span: #0 bytes(0..0), is_raw: false },
paren_token: Paren,
nested: [
Meta(NameValue(MetaNameValue {
ident: Ident { sym: name, span: #0 bytes(0..0), is_raw: false },
@rroohhh
rroohhh / high.yml
Last active September 7, 2018 01:44
access_address:
addr: seq_ctrl_port[0:9]
description: 'When in STANDBY (not streaming) mode: address pointer to the sequencer
RAM.'
writable: true
auto_inc_on_read:
addr: seq_ctrl_port[14:15]
description: If 1 => The access_address is incremented (by 1) after each read operation
from seq_data_port (which returns only1 byte)
max: 1
clks:
ext:
min: 6000000
max: 27000000
vco:
min: 384000000
max: 768000000
plls:
mult:
min: 32
@rroohhh
rroohhh / fooo
Created January 1, 2018 14:27
foo
ZED_5V 4.8828 V
[1f40] +10.1562 mV
[104] +677.08 mA BETA_5V 4.8828 V
[1f40] +1.2891 mV
[021] +85.94 mA HDN 3.2812 V
[1500] +0.0000 mV
[000] +0.00 mA PCIE_N_V 3.2422 V
[14c0] +0.0000 mV
[000] +0.00 mA HDS 3.2031 V
[1480] +0.0000 mV