foo.v

`define CLOCK_HZ 54_000_000

module foo(input wire i_clk);

localparam PRESCALER = `CLOCK_HZ / 50;
reg [$clog2(PRESCALER)-1:0] counter;

always @(posedge i_clk) begin
    // Comparison generates warning:
    // Operator LT expects 32 or 26 bits on the LHS, but LHS's VARREF 'counter' generates 21 bits.
    if (counter < PRESCALER) begin
        counter <= counter + 1;
    end else begin
        counter <= 0;
    end
end

endmodule