Rene Stange rsta2
rsta2
/ gist:0cf5199484305f4d81078dbdd17f75c0
Created
November 21, 2023 10:27
Interrupt routing code
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| // Second level interrupt controller | |
| #define INTC_REG_RW (ARM_RP1_INTC + 0x000) | |
| #define INTC_INT_STAT_LOW (ARM_RP1_INTC + 0x108) | |
| #define INTC_INT_STAT_HIGH (ARM_RP1_INTC + 0x10C) | |
| #define INTC_REG_SET (ARM_RP1_INTC + 0x800) | |
| #define INTC_REG_CLR (ARM_RP1_INTC + 0xC00) | |
| #define MSIX_CFG(irq) (0x008 + (irq)*4) | |
| #define MSIX_CFG_ENABLE BIT (0) | |
| #define MSIX_CFG_TEST BIT (1) // forces interrupt |