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Memtest86 v11.1 Pro Memory and System Info
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| MemTest86 V11.1 Pro Build: 1000 | |
| PassMark Software | |
| www.passmark.com | |
| Memory summary: | |
| Number of RAM slots: 4 | |
| Number of RAM modules: 2 | |
| Number of RAM SPDs detected: 2 | |
| Total Physical Memory: 32609M | |
| RAM Configuration: | |
| Transfer Speed: 6400MT/s | |
| Channel Mode: x2 Channel | |
| Timings: 32-40-40-84 | |
| Voltage: 1.100V | |
| ECC Enabled: No | |
| SPD Details: | |
| -------------- | |
| SPD #: 0 | |
| ============== | |
| RAM Type: DDR5 | |
| Maximum Clock Speed (MHz): 3200 (XMP) | |
| Maximum Transfer Speed (MT/s): DDR5-6410 | |
| Maximum Bandwidth (MB/s): PC5-51200 | |
| Memory Capacity (MB): 16384 | |
| Jedec Manufacture Name: Corsair | |
| SPD Revision: 1.0 | |
| Registered: No | |
| ECC: No | |
| SPD #: 0 | |
| Manufactured: Week 34 of Year 2024 | |
| Module Part #: CMH32GX5M2B6400C32 | |
| Module Revision: 0x0000 | |
| Module Serial #: 00000000 | |
| Module Manufacturing Location: 0x00 | |
| # of Row Addressing Bits: 16 | |
| # of Column Addressing Bits: 10 | |
| # of Banks: 32 | |
| # of Ranks: 1 | |
| Device Width in Bits: 8 | |
| Bus Width in Bits: 32 | |
| Module Voltage: 1.1V | |
| CAS Latencies Supported: 22 28 30 32 36 40 42 | |
| Timings @ Max Frequency (JEDEC): Timings @ Max Frequency (JEDEC) | |
| Maximum Clock Speed (MHz): 2400 | |
| Maximum Transfer Speed (MT/s): DDR5-4800 | |
| Maximum Bandwidth (MB/s): PC5-38400 | |
| Minimum Clock Cycle Time, tCK (ns): 0.416 | |
| Minimum CAS Latency Time, tAA (ns): 16.666 | |
| Minimum RAS to CAS Delay, tRCD (ns): 16.666 | |
| Minimum Row Precharge Time, tRP (ns): 16.666 | |
| Minimum Active to Precharge Time, tRAS (ns): 32.000 | |
| Minimum Row Active to Row Active Delay, tRRD (ns): 0.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns): 48.666 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns): 295.000 | |
| DDR5 Specific SPD Attributes | |
| Maximum Clock Cycle time, tCKmax (ns): 1.010 | |
| Minimum Write Recovery time, tWR (ns): 30.000 | |
| Minimum Recovery Delay time, tRFC2 (ns): 160.000 | |
| Minimum Recovery Delay time, tRFC4 (ns): 130.000 | |
| Minimum Recovery Delay time (diff. logical rank) tRFC1_dlr (ns): 0.000 | |
| Minimum Recovery Delay time (diff. logical rank) tRFC2_dlr (ns): 0.000 | |
| Minimum Recovery Delay time (diff. logical rank) tRFCsb_dlr (ns): 0.000 | |
| Module information SPD revision: 0x10 | |
| SPD present: Yes | |
| SPD device type: SPD5118 | |
| SPD Manufacturer: IDT (Bank: 1, ID: 0xB3) | |
| PMIC 0 present: Yes | |
| PMIC 0 device type: PMIC5100 | |
| PMIC 0 Manufacturer: Monolithic Power Systems Inc (Bank: 12, ID: 0x2A) | |
| PMIC 1 present: No | |
| PMIC 2 present: No | |
| Thermal Sensor 0 present: No | |
| Thermal Sensor 1 present: No | |
| Module Type: UDIMM | |
| Module Height (mm): 44 - 45 | |
| Module Thickness (mm): front 3-4 , back 3-4 | |
| Module reference card: Raw Card A Rev. 0 | |
| # DRAM Rows: 1 | |
| Heat spreader installed: Yes | |
| Operating Temperature Range: XT (0 to + 95 C) | |
| Rank Mix: Symmetrical | |
| Number of Package Ranks per Sub-Channel: 1 | |
| Number of Sub-Channels per DIMM: 2 | |
| Bus width extension per Sub-Channel: 0 bits | |
| Primary bus width per Sub-Channel: 32 bits | |
| DRAM Stepping: 77 | |
| DRAM Manufacture: SK Hynix | |
| SDRAM Package Type: Monolithic SDRAM | |
| SDRAM Density Per Die: 16Gb | |
| SDRAM Column Address Bits: 10 | |
| SDRAM Row Address Bits: 16 | |
| SDRAM Device Width: 8 | |
| SDRAM Bank Groups: 8 | |
| SDRAM Banks Per Bank Group: 4 | |
| First SDRAM RFM RAAMMT: 0X (FGR: 0X) | |
| First SDRAM RFM RAAIMT: 0 (FGR: 0) | |
| First SDRAM RFM Required: no | |
| First SDRAM RFM RAA Counter Decrement per REF command: RAAIMT / 2 | |
| Second SDRAM RFM RAAMMT: 0X (FGR: 0X) | |
| Second SDRAM RFM RAAIMT: 0 (FGR: 0) | |
| Second SDRAM RFM Required: no | |
| Second SDRAM RFM RAA Counter Decrement per REF command: RAAIMT / 2 | |
| First SDRAM ARFM Level A RAAMMT: 0X (FGR: 0X) | |
| First SDRAM ARFM Level A RAAIMT: 0 (FGR: 0) | |
| First SDRAM ARFM Level A supported: no | |
| First SDRAM ARFM Level A RAA Counter Decrement per REF command: RAAIMT / 2 | |
| Second SDRAM ARFM Level A RAAMMT: 0X (FGR: 0X) | |
| Second SDRAM ARFM Level A RAAIMT: 0 (FGR: 0) | |
| Second SDRAM ARFM Level A supported: no | |
| Second SDRAM ARFM Level A RAA Counter Decrement per REF command: RAAIMT / 2 | |
| First SDRAM ARFM Level B RAAMMT: 0X (FGR: 0X) | |
| First SDRAM ARFM Level B RAAIMT: 0 (FGR: 0) | |
| First SDRAM ARFM Level B supported: no | |
| First SDRAM ARFM Level B RAA Counter Decrement per REF command: RAAIMT / 2 | |
| Second SDRAM ARFM Level B RAAMMT: 0X (FGR: 0X) | |
| Second SDRAM ARFM Level B RAAIMT: 0 (FGR: 0) | |
| Second SDRAM ARFM Level B supported: no | |
| Second SDRAM ARFM Level B RAA Counter Decrement per REF command: RAAIMT / 2 | |
| First SDRAM ARFM Level C RAAMMT: 0X (FGR: 0X) | |
| First SDRAM ARFM Level C RAAIMT: 0 (FGR: 0) | |
| First SDRAM ARFM Level C supported: no | |
| First SDRAM ARFM Level C RAA Counter Decrement per REF command: RAAIMT / 2 | |
| Second SDRAM ARFM Level C RAAMMT: 0X (FGR: 0X) | |
| Second SDRAM ARFM Level C RAAIMT: 0 (FGR: 0) | |
| Second SDRAM ARFM Level C supported: no | |
| Second SDRAM ARFM Level C RAA Counter Decrement per REF command: RAAIMT / 2 | |
| sPPR Granularity: One repair element per bank group | |
| sPPR Undo/Lock: supported | |
| Burst length 32: not supported | |
| MBIST/mPPR: not supported | |
| mPPR/hPPR Abort: not supported | |
| PASR: not supported | |
| DCA Types Supported: Device does not support DCA | |
| x4 RMW/ECS Writeback Suppression: not supported | |
| x4 RMW/ECS Writeback Suppression MR selector: MR9 | |
| Bounded Fault: not supported | |
| SDRAM Nominal Voltage, VDDQ: 1.1V | |
| SDRAM Nominal Voltage, VPP: 1.8V | |
| XMP version: 3.0 | |
| PMIC Vendor ID: 0B2A | |
| Number of PMICs on DIMM: 1 | |
| PMIC capabilities: | |
| PMIC has capabilities for OC functions: No | |
| Current PMIC OC is enabled: No | |
| PMIC voltage default step size: 5mV | |
| OC global reset functions: No | |
| Validation and Certification Capabilities: | |
| DIMM is self-certified by DIMM vendor: No | |
| PMIC Component is validated by Intel AVL level: No | |
| XMP revision: 1.2 | |
| XMP Profile 1: "Profile 1" | |
| XMP Certified: No | |
| Recommended number of DIMMs per channel: 1 | |
| Module VPP voltage: 1.8V | |
| Module VDD voltage: 1.4V | |
| Module VDDQ voltage: 1.4V | |
| Memory Controller voltage: 1.2V | |
| Clock speed (MHz): 3200 | |
| Transfer Speed (MT/s): DDR5-6410 | |
| Bandwidth (MB/s): PC5-51200 | |
| Minimum clock cycle time, tCK (ns): 0.312 | |
| Supported CAS latencies: 22 26 28 30 32 36 40 42 46 48 50 52 54 56 | |
| Minimum CAS latency time, tAA (ns): 9.984 | |
| Minimum RAS to CAS delay time, tRCD (ns): 12.480 | |
| Minimum row precharge time, tRP (ns): 12.480 | |
| Minimum active to precharge time, tRAS (ns): 26.208 | |
| Supported timing at highest clock speed: 32-40-40-84 | |
| Minimum Active to Auto-Refresh Delay, tRC (ns): 38.688 | |
| Minimum Write Recovery Time, tWR (ns): 30.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns): 295.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns): 160.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns): 130.000 | |
| Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns): 5.000 (8 nCK) | |
| Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns): 20.000 (32 nCK) | |
| Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns): 10.000 (16 nCK) | |
| Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns): 10.000 (16 nCK) | |
| Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns): 2.500 (4 nCK) | |
| Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns): 5.000 (8 nCK) | |
| Minimum Read to Precharge Command Delay Time, tRTP (ns): 7.500 (12 nCK) | |
| Minimum Four Activate Window, tFAW (ns): 10.000 (32 nCK) | |
| Advanced Memory Overclocking Features | |
| Real-Time Memory Frequency Overclocking: Supported | |
| Intel Dynamic Memory Boost: Supported | |
| System CMD Rate Mode: 2n | |
| Vendor Personality Byte: 0x00 | |
| SPD #: 1 | |
| ============== | |
| RAM Type: DDR5 | |
| Maximum Clock Speed (MHz): 3200 (XMP) | |
| Maximum Transfer Speed (MT/s): DDR5-6410 | |
| Maximum Bandwidth (MB/s): PC5-51200 | |
| Memory Capacity (MB): 16384 | |
| Jedec Manufacture Name: Corsair | |
| SPD Revision: 1.0 | |
| Registered: No | |
| ECC: No | |
| SPD #: 1 | |
| Manufactured: Week 34 of Year 2024 | |
| Module Part #: CMH32GX5M2B6400C32 | |
| Module Revision: 0x0000 | |
| Module Serial #: 00000000 | |
| Module Manufacturing Location: 0x00 | |
| # of Row Addressing Bits: 16 | |
| # of Column Addressing Bits: 10 | |
| # of Banks: 32 | |
| # of Ranks: 1 | |
| Device Width in Bits: 8 | |
| Bus Width in Bits: 32 | |
| Module Voltage: 1.1V | |
| CAS Latencies Supported: 22 28 30 32 36 40 42 | |
| Timings @ Max Frequency (JEDEC): Timings @ Max Frequency (JEDEC) | |
| Maximum Clock Speed (MHz): 2400 | |
| Maximum Transfer Speed (MT/s): DDR5-4800 | |
| Maximum Bandwidth (MB/s): PC5-38400 | |
| Minimum Clock Cycle Time, tCK (ns): 0.416 | |
| Minimum CAS Latency Time, tAA (ns): 16.666 | |
| Minimum RAS to CAS Delay, tRCD (ns): 16.666 | |
| Minimum Row Precharge Time, tRP (ns): 16.666 | |
| Minimum Active to Precharge Time, tRAS (ns): 32.000 | |
| Minimum Row Active to Row Active Delay, tRRD (ns): 0.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns): 48.666 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns): 295.000 | |
| DDR5 Specific SPD Attributes | |
| Maximum Clock Cycle time, tCKmax (ns): 1.010 | |
| Minimum Write Recovery time, tWR (ns): 30.000 | |
| Minimum Recovery Delay time, tRFC2 (ns): 160.000 | |
| Minimum Recovery Delay time, tRFC4 (ns): 130.000 | |
| Minimum Recovery Delay time (diff. logical rank) tRFC1_dlr (ns): 0.000 | |
| Minimum Recovery Delay time (diff. logical rank) tRFC2_dlr (ns): 0.000 | |
| Minimum Recovery Delay time (diff. logical rank) tRFCsb_dlr (ns): 0.000 | |
| Module information SPD revision: 0x10 | |
| SPD present: Yes | |
| SPD device type: SPD5118 | |
| SPD Manufacturer: IDT (Bank: 1, ID: 0xB3) | |
| PMIC 0 present: Yes | |
| PMIC 0 device type: PMIC5100 | |
| PMIC 0 Manufacturer: Monolithic Power Systems Inc (Bank: 12, ID: 0x2A) | |
| PMIC 1 present: No | |
| PMIC 2 present: No | |
| Thermal Sensor 0 present: No | |
| Thermal Sensor 1 present: No | |
| Module Type: UDIMM | |
| Module Height (mm): 44 - 45 | |
| Module Thickness (mm): front 3-4 , back 3-4 | |
| Module reference card: Raw Card A Rev. 0 | |
| # DRAM Rows: 1 | |
| Heat spreader installed: Yes | |
| Operating Temperature Range: XT (0 to + 95 C) | |
| Rank Mix: Symmetrical | |
| Number of Package Ranks per Sub-Channel: 1 | |
| Number of Sub-Channels per DIMM: 2 | |
| Bus width extension per Sub-Channel: 0 bits | |
| Primary bus width per Sub-Channel: 32 bits | |
| DRAM Stepping: 77 | |
| DRAM Manufacture: SK Hynix | |
| SDRAM Package Type: Monolithic SDRAM | |
| SDRAM Density Per Die: 16Gb | |
| SDRAM Column Address Bits: 10 | |
| SDRAM Row Address Bits: 16 | |
| SDRAM Device Width: 8 | |
| SDRAM Bank Groups: 8 | |
| SDRAM Banks Per Bank Group: 4 | |
| First SDRAM RFM RAAMMT: 0X (FGR: 0X) | |
| First SDRAM RFM RAAIMT: 0 (FGR: 0) | |
| First SDRAM RFM Required: no | |
| First SDRAM RFM RAA Counter Decrement per REF command: RAAIMT / 2 | |
| Second SDRAM RFM RAAMMT: 0X (FGR: 0X) | |
| Second SDRAM RFM RAAIMT: 0 (FGR: 0) | |
| Second SDRAM RFM Required: no | |
| Second SDRAM RFM RAA Counter Decrement per REF command: RAAIMT / 2 | |
| First SDRAM ARFM Level A RAAMMT: 0X (FGR: 0X) | |
| First SDRAM ARFM Level A RAAIMT: 0 (FGR: 0) | |
| First SDRAM ARFM Level A supported: no | |
| First SDRAM ARFM Level A RAA Counter Decrement per REF command: RAAIMT / 2 | |
| Second SDRAM ARFM Level A RAAMMT: 0X (FGR: 0X) | |
| Second SDRAM ARFM Level A RAAIMT: 0 (FGR: 0) | |
| Second SDRAM ARFM Level A supported: no | |
| Second SDRAM ARFM Level A RAA Counter Decrement per REF command: RAAIMT / 2 | |
| First SDRAM ARFM Level B RAAMMT: 0X (FGR: 0X) | |
| First SDRAM ARFM Level B RAAIMT: 0 (FGR: 0) | |
| First SDRAM ARFM Level B supported: no | |
| First SDRAM ARFM Level B RAA Counter Decrement per REF command: RAAIMT / 2 | |
| Second SDRAM ARFM Level B RAAMMT: 0X (FGR: 0X) | |
| Second SDRAM ARFM Level B RAAIMT: 0 (FGR: 0) | |
| Second SDRAM ARFM Level B supported: no | |
| Second SDRAM ARFM Level B RAA Counter Decrement per REF command: RAAIMT / 2 | |
| First SDRAM ARFM Level C RAAMMT: 0X (FGR: 0X) | |
| First SDRAM ARFM Level C RAAIMT: 0 (FGR: 0) | |
| First SDRAM ARFM Level C supported: no | |
| First SDRAM ARFM Level C RAA Counter Decrement per REF command: RAAIMT / 2 | |
| Second SDRAM ARFM Level C RAAMMT: 0X (FGR: 0X) | |
| Second SDRAM ARFM Level C RAAIMT: 0 (FGR: 0) | |
| Second SDRAM ARFM Level C supported: no | |
| Second SDRAM ARFM Level C RAA Counter Decrement per REF command: RAAIMT / 2 | |
| sPPR Granularity: One repair element per bank group | |
| sPPR Undo/Lock: supported | |
| Burst length 32: not supported | |
| MBIST/mPPR: not supported | |
| mPPR/hPPR Abort: not supported | |
| PASR: not supported | |
| DCA Types Supported: Device does not support DCA | |
| x4 RMW/ECS Writeback Suppression: not supported | |
| x4 RMW/ECS Writeback Suppression MR selector: MR9 | |
| Bounded Fault: not supported | |
| SDRAM Nominal Voltage, VDDQ: 1.1V | |
| SDRAM Nominal Voltage, VPP: 1.8V | |
| XMP version: 3.0 | |
| PMIC Vendor ID: 0B2A | |
| Number of PMICs on DIMM: 1 | |
| PMIC capabilities: | |
| PMIC has capabilities for OC functions: No | |
| Current PMIC OC is enabled: No | |
| PMIC voltage default step size: 5mV | |
| OC global reset functions: No | |
| Validation and Certification Capabilities: | |
| DIMM is self-certified by DIMM vendor: No | |
| PMIC Component is validated by Intel AVL level: No | |
| XMP revision: 1.2 | |
| XMP Profile 1: "Profile 1" | |
| XMP Certified: No | |
| Recommended number of DIMMs per channel: 1 | |
| Module VPP voltage: 1.8V | |
| Module VDD voltage: 1.4V | |
| Module VDDQ voltage: 1.4V | |
| Memory Controller voltage: 1.2V | |
| Clock speed (MHz): 3200 | |
| Transfer Speed (MT/s): DDR5-6410 | |
| Bandwidth (MB/s): PC5-51200 | |
| Minimum clock cycle time, tCK (ns): 0.312 | |
| Supported CAS latencies: 22 26 28 30 32 36 40 42 46 48 50 52 54 56 | |
| Minimum CAS latency time, tAA (ns): 9.984 | |
| Minimum RAS to CAS delay time, tRCD (ns): 12.480 | |
| Minimum row precharge time, tRP (ns): 12.480 | |
| Minimum active to precharge time, tRAS (ns): 26.208 | |
| Supported timing at highest clock speed: 32-40-40-84 | |
| Minimum Active to Auto-Refresh Delay, tRC (ns): 38.688 | |
| Minimum Write Recovery Time, tWR (ns): 30.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC1 (ns): 295.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFC2 (ns): 160.000 | |
| Minimum Auto-Refresh to Active/Auto-Refresh Delay, tRFCsb (ns): 130.000 | |
| Minimum Read to Read Command Delay Time, Same Bank Group, tCCD_L (ns): 5.000 (8 nCK) | |
| Minimum Write to Write Command Delay Time, Same Bank Group, tCCD_L_WR (ns): 20.000 (32 nCK) | |
| Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group, tCCD_L_WR2 (ns): 10.000 (16 nCK) | |
| Minimum Write to Read Command Delay Time, Same Bank Group, tCCD_L_WTR (ns): 10.000 (16 nCK) | |
| Minimum Write to Read Command Delay Time, Different Bank Group, tCCD_S_WTR (ns): 2.500 (4 nCK) | |
| Minimum Active to Active Command Delay Time, Same Bank Group, tRRD_L (ns): 5.000 (8 nCK) | |
| Minimum Read to Precharge Command Delay Time, tRTP (ns): 7.500 (12 nCK) | |
| Minimum Four Activate Window, tFAW (ns): 10.000 (32 nCK) | |
| Advanced Memory Overclocking Features | |
| Real-Time Memory Frequency Overclocking: Supported | |
| Intel Dynamic Memory Boost: Supported | |
| System CMD Rate Mode: 2n | |
| Vendor Personality Byte: 0x00 | |
| SMBIOS Details: | |
| -------------- | |
| Memory Device #: 0 | |
| ============== | |
| Empty slot | |
| Memory Device #: 1 | |
| ============== | |
| Total Width: 64 bits | |
| Data Width: 64 bits | |
| Size: 16384 MB | |
| Form Factor: DIMM | |
| Device Set: 0 | |
| Device Locator: Controller0-DIMM1 | |
| Bank Locator: BANK 0 | |
| Memory Type: DDR5 | |
| Type Detail: Synchronous | |
| Speed: 6400MT/s | |
| Manufacturer: Corsair | |
| Serial Number: 00000000 | |
| Asset Tag: 9876543210 | |
| Part Number: CMH32GX5M2B6400C32 | |
| Attributes: 00000001 | |
| Configured Memory Speed: 6400MT/s | |
| Minimum Voltage: 1100 mV | |
| Maximum Voltage: 1400 mV | |
| Configured Voltage: 1100 mV | |
| Memory Technology: DRAM | |
| Memory Operating Mode Capability: Unknown | |
| Firmware Version: | |
| Module Manufacturer ID: 9E02 | |
| Module Product ID: N/A | |
| Memory Subsystem Controller Manufacturer ID: N/A | |
| Memory Subsystem Controller Product ID: N/A | |
| Non Volatile Size: N/A | |
| Volatile Size: 17179869184 MB | |
| Cache Size: N/A | |
| Logical Size: N/A | |
| Memory Device #: 2 | |
| ============== | |
| Empty slot | |
| Memory Device #: 3 | |
| ============== | |
| Total Width: 64 bits | |
| Data Width: 64 bits | |
| Size: 16384 MB | |
| Form Factor: DIMM | |
| Device Set: 0 | |
| Device Locator: Controller1-DIMM1 | |
| Bank Locator: BANK 0 | |
| Memory Type: DDR5 | |
| Type Detail: Synchronous | |
| Speed: 6400MT/s | |
| Manufacturer: Corsair | |
| Serial Number: 00000000 | |
| Asset Tag: 9876543210 | |
| Part Number: CMH32GX5M2B6400C32 | |
| Attributes: 00000001 | |
| Configured Memory Speed: 6400MT/s | |
| Minimum Voltage: 1100 mV | |
| Maximum Voltage: 1400 mV | |
| Configured Voltage: 1100 mV | |
| Memory Technology: DRAM | |
| Memory Operating Mode Capability: Unknown | |
| Firmware Version: | |
| Module Manufacturer ID: 9E02 | |
| Module Product ID: N/A | |
| Memory Subsystem Controller Manufacturer ID: N/A | |
| Memory Subsystem Controller Product ID: N/A | |
| Non Volatile Size: N/A | |
| Volatile Size: 17179869184 MB | |
| Cache Size: N/A | |
| Logical Size: N/A |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| MemTest86 V11.1 Pro Build: 1000 | |
| PassMark Software | |
| www.passmark.com | |
| System Information | |
| ============================================= | |
| System: | |
| Manufacturer: ASUS | |
| Product Name: System Product Name | |
| Version: System Version | |
| Serial Number: System Serial Number | |
| BIOS: | |
| Vendor: American Megatrends Inc. | |
| Version: 4101 | |
| Release Date: 12/03/2024 | |
| Baseboard: | |
| Manufacturer: ASUSTeK COMPUTER INC. | |
| Product Name: ROG STRIX Z690-E GAMING WIFI | |
| Version: Rev 1.xx | |
| Serial Number: 221213486500354 | |
| CPU Type: 13th Gen Intel Core i5-13600KF | |
| CPU Clock: 3533 MHz [Turbo: 5148.3 MHz] | |
| L1 Cache: 32 x 80K (675590 MB/s) | |
| L2 Cache: 8 x 2048K (126400 MB/s) | |
| L3 Cache: 24576K (57434 MB/s) | |
| Memory: | |
| Total Physical Memory: 32609M (27053 MB/s) | |
| RAM Configuration: DDR5 6400MT/s / x2 Channel / 32-40-40-84 / 1.100V | |
| Number of RAM SPDs detected: 2 | |
| SPD #0: 16GB DDR5 XMP 1Rx8 PC5-51200 | |
| Vendor Part Info: Corsair CMH32GX5M2B6400C32 | |
| JEDEC Profile: 4800MT/s 40-40-40-77 1.1V | |
| XMP Profile 1: 6400MT/s 32-40-40-84 1.4V | |
| SPD #1: 16GB DDR5 XMP 1Rx8 PC5-51200 | |
| Vendor Part Info: Corsair CMH32GX5M2B6400C32 | |
| JEDEC Profile: 4800MT/s 40-40-40-77 1.1V | |
| XMP Profile 1: 6400MT/s 32-40-40-84 1.4V | |
| Number of RAM slots: 4 | |
| Number of RAM modules: 2 | |
| DIMM A1: Empty | |
| DIMM A2: 16GB DDR5 1Rx8 PC5-51200 | |
| Vendor Part Info: Corsair CMH32GX5M2B6400C32 00000000 | |
| SMBIOS Profile: 6400MT/s 1.1V | |
| DIMM B1: Empty | |
| DIMM B2: 16GB DDR5 1Rx8 PC5-51200 | |
| Vendor Part Info: Corsair CMH32GX5M2B6400C32 00000000 | |
| SMBIOS Profile: 6400MT/s 1.1V |
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