nor_in.sch

gistfile1.txt

v 20110115 2
C 41400 47900 1 0 0 ibis_io.sym
{
T 40700 47250 5 10 1 1 0 0 1
value=LVCMOS18_F_12 spec={v6_spec} start_on=0
T 41600 49900 5 10 0 0 0 0 1
symversion=1.0
T 41600 49750 5 10 1 1 0 0 1
refdes=X_V6_IN
}
C 50700 48100 1 0 0 gnd-1.sym
C 52100 48100 1 0 0 gnd-1.sym
N 42900 49700 43400 49700 4
N 42900 47900 45500 47900 4
C 45900 48300 1 0 1 ibis_ebd-1.sym
{
T 47500 49650 5 10 1 1 0 6 1
value=VIRTEX_6_flash_mosi spec={v6_spec}
T 45700 50300 5 10 0 0 0 6 1
symversion=1.0
T 46200 49050 5 10 1 1 0 6 1
refdes=X_V6_IN_PKG
}
N 45100 48800 44100 48800 4
{
T 44100 48900 5 10 1 1 0 0 1
netname=v6_in_die
}
N 46800 48800 45900 48800 4
{
T 46000 48900 5 10 1 1 0 0 1
netname=v6_in_pin
}
C 53200 48300 1 0 0 ibis_ebd-1.sym
{
T 51300 49350 5 10 1 1 0 0 1
value=N25Q128A11BF840F_DQ0 spec={n25q_spec}
T 53400 50300 5 10 0 0 0 0 1
symversion=1.0
T 52900 49050 5 10 1 1 0 0 1
refdes=X_N25Q_IN_PKG
}
N 53200 48800 52600 48800 4
{
T 52400 48500 5 10 1 1 0 0 1
netname=n25q_in_pin
}
N 55300 48800 54000 48800 4
{
T 54300 48900 5 10 1 1 0 0 1
netname=n25q_in_die
}
C 55800 49700 1 0 0 generic-power.sym
{
T 56000 49950 5 10 1 1 0 3 1
net=Vcc_n25q:1
}
C 56200 47900 1 180 0 generic-power.sym
{
T 56000 47650 5 10 1 1 180 3 1
net=Vss_n25q:1
}
C 43600 49700 1 0 1 generic-power.sym
{
T 43400 49950 5 10 1 1 0 3 1
net=Vcc_v6:1
}
N 45500 48300 45500 47900 4
N 41400 48400 40700 48400 4
{
T 40700 48400 5 10 1 1 0 0 1
netname=high
}
N 41400 49200 40400 49200 4
{
T 40400 49200 5 10 1 1 0 0 1
netname=pattern
}
N 58000 48800 58900 48800 4
{
T 58000 48800 5 10 1 1 0 0 1
netname=n25q_in
}
C 42200 45700 1 0 0 spice-directive-1.sym
{
T 42300 46000 5 10 0 1 0 0 1
device=directive
T 42200 46100 5 10 1 1 0 0 1
refdes=A_IN
T 42100 45900 5 10 1 1 180 6 7
value=.lib n25q128a11bf8.lib DQ_30_ohm
.lib virtex6.lib LVCMOS18_F_12
.lib n25q128a11bf8.lib N25Q128A11BF840F
.lib top.lib VIRTEX_6

.model pattern d_state(clk_delay=1f reset_delay=1f state_file="pattern.in" input_load=0 clk_load=0 reset_load=0)
A_pattern Null ~clk_60MHz low [pattern] pattern
}
N 56000 47900 56500 47900 4
C 50400 48400 1 0 0 tline.sym
{
T 51300 48800 5 10 0 1 0 0 1
device=T-Line
T 51250 48350 5 10 1 1 0 0 1
refdes=Y_IN1
T 50800 49100 5 10 1 1 0 0 1
value=m55 len=18.5m
}
C 58000 47900 1 0 1 ibis_io.sym
{
T 58700 47250 5 10 1 1 0 6 1
value=DQ_30_ohm spec={n25q_spec}
T 57800 49900 5 10 0 0 0 6 1
symversion=1.0
T 57800 49750 5 10 1 1 0 6 1
refdes=X_N25Q_IN
}
N 56000 49700 56500 49700 4
N 58700 48400 58000 48400 4
{
T 58300 48400 5 10 1 1 0 0 1
netname=low
}
C 49200 48700 1 0 0 resistor-1.sym
{
T 49500 49100 5 10 0 0 0 0 1
device=RESISTOR
T 49200 49000 5 10 1 1 0 0 1
refdes=R_in
T 49700 49000 5 10 1 1 0 0 1
value=100
}
C 47100 48100 1 0 0 gnd-1.sym
C 46800 48400 1 0 0 tline.sym
{
T 47700 48800 5 10 0 1 0 0 1
device=T-Line
T 47650 48350 5 10 1 1 0 0 1
refdes=Y_IN0
T 47200 49100 5 10 1 1 0 0 1
value=m55 len=6m
}
C 48500 48100 1 0 0 gnd-1.sym
N 49000 48800 49200 48800 4
N 50100 48800 50400 48800 4
C 43300 47600 1 0 0 gnd-1.sym
C 53500 48000 1 0 0 gnd-1.sym