nor_clock.sch

gistfile1.txt

v 20110115 2
C 41400 47900 1 0 0 ibis_io.sym
{
T 40700 47250 5 10 1 1 0 0 1
value=LVCMOS18_F_12 spec={v6_spec} start_on=0
T 41600 49900 5 10 0 0 0 0 1
symversion=1.0
T 41600 49750 5 10 1 1 0 0 1
refdes=X_V6_CK
}
C 58500 47900 1 0 1 ibis_input.sym
{
T 56800 47650 5 10 1 1 0 0 1
value=CLK_BUF spec={n25q_spec}
T 58300 49900 5 10 0 0 0 6 1
symversion=1.0
T 58300 49750 5 10 1 1 0 6 1
refdes=X_N25Q_CK
}
C 50900 48100 1 0 0 gnd-1.sym
C 52300 48100 1 0 0 gnd-1.sym
N 42900 49700 43400 49700 4
N 42900 47900 45500 47900 4
C 45900 48300 1 0 1 ibis_ebd-1.sym
{
T 47500 49650 5 10 1 1 0 6 1
value=VIRTEX_6_cclk_0 spec={v6_spec}
T 45700 50300 5 10 0 0 0 6 1
symversion=1.0
T 46200 49050 5 10 1 1 0 6 1
refdes=X_V6_CK_PKG
}
N 45100 48800 44100 48800 4
{
T 44100 48900 5 10 1 1 0 0 1
netname=v6_ck_die
}
N 47000 48800 45900 48800 4
{
T 46000 48900 5 10 1 1 0 0 1
netname=v6_ck_pin
}
C 53700 48300 1 0 0 ibis_ebd-1.sym
{
T 51800 49350 5 10 1 1 0 0 1
value=N25Q128A11BF840F_C spec={n25q_spec}
T 53900 50300 5 10 0 0 0 0 1
symversion=1.0
T 53400 49050 5 10 1 1 0 0 1
refdes=X_N25Q_CK_PKG
}
N 53700 48800 52800 48800 4
{
T 52500 48900 5 10 1 1 0 0 1
netname=n25q_ck_pin
}
N 55800 48800 54500 48800 4
{
T 54800 48900 5 10 1 1 0 0 1
netname=n25q_ck_die
}
C 56300 49700 1 0 0 generic-power.sym
{
T 56500 49950 5 10 1 1 0 3 1
net=Vcc_n25q:1
}
C 56700 47900 1 180 0 generic-power.sym
{
T 56500 47650 5 10 1 1 180 3 1
net=Vss_n25q:1
}
C 43600 49700 1 0 1 generic-power.sym
{
T 43400 49950 5 10 1 1 0 3 1
net=Vcc_v6:1
}
N 45500 48300 45500 47900 4
N 41400 48400 40700 48400 4
{
T 40700 48400 5 10 1 1 0 0 1
netname=high
}
N 41400 49200 40400 49200 4
{
T 40400 49200 5 10 1 1 0 0 1
netname=clk_60MHz
}
N 58500 48800 59400 48800 4
{
T 58500 48800 5 10 1 1 0 0 1
netname=n25q_ck_in
}
C 42200 45700 1 0 0 spice-directive-1.sym
{
T 42300 46000 5 10 0 1 0 0 1
device=directive
T 42200 46100 5 10 1 1 0 0 1
refdes=A_CK
T 42100 45900 5 10 1 1 180 6 9
value=.lib n25q128a11bf8.lib CLK_BUF
.lib virtex6.lib LVCMOS18_F_12
.lib n25q128a11bf8.lib N25Q128A11BF840F
.lib top.lib VIRTEX_6

.model clock_60MHz d_osc(rise_delay=1f fall_delay=1f cntl_array=[0 1] freq_array=[60Meg 60Meg])
A_clock_60MHz 0 clk_60MHz clock_60MHz

x_ck_hold n25q_ck_in n25q_ck_held hold
}
C 50600 48400 1 0 0 tline.sym
{
T 51500 48800 5 10 0 1 0 0 1
device=T-Line
T 51450 48350 5 10 1 1 0 0 1
refdes=Y_CK1
T 51000 49100 5 10 1 1 0 0 1
value=m55 len=2m
}
C 47300 48100 1 0 0 gnd-1.sym
C 48700 48100 1 0 0 gnd-1.sym
C 47000 48400 1 0 0 tline.sym
{
T 47900 48800 5 10 0 1 0 0 1
device=T-Line
T 47850 48350 5 10 1 1 0 0 1
refdes=Y_CK0
T 47400 49100 5 10 1 1 0 0 1
value=m55 len=80.3m
}
N 49200 48800 50000 48800 4
C 50100 47800 1 90 0 resistor-1.sym
{
T 49700 48100 5 10 0 0 90 0 1
device=RESISTOR
T 49300 48400 5 10 1 1 0 0 1
refdes=R_ck0
T 49300 48000 5 10 1 1 0 0 1
value=150
}
C 50100 48900 1 90 0 resistor-1.sym
{
T 49700 49200 5 10 0 0 90 0 1
device=RESISTOR
T 49300 49400 5 10 1 1 0 0 1
refdes=R_ck1
T 49300 49100 5 10 1 1 0 0 1
value=150
}
N 50000 48700 50000 48900 4
C 49900 47500 1 0 0 gnd-1.sym
C 49800 49800 1 0 0 vcc-1.sym
N 50000 48800 50600 48800 4
C 43300 47600 1 0 0 gnd-1.sym
C 54000 48000 1 0 0 gnd-1.sym