nor_select.sch

gistfile1.txt

v 20110115 2
C 41400 47900 1 0 0 ibis_io.sym
{
T 40700 47250 5 10 1 1 0 0 1
value=LVCMOS18_F_12 spec={v6_spec} start_on=0
T 41600 49900 5 10 0 0 0 0 1
symversion=1.0
T 41600 49750 5 10 1 1 0 0 1
refdes=X_V6_S
}
C 57500 47900 1 0 1 ibis_input.sym
{
T 55800 47650 5 10 1 1 0 0 1
value=CS_BUF spec={n25q_spec}
T 57300 49900 5 10 0 0 0 6 1
symversion=1.0
T 57400 49750 5 10 1 1 0 6 1
refdes=X_N25Q_S
}
C 50200 48100 1 0 0 gnd-1.sym
C 51600 48100 1 0 0 gnd-1.sym
N 42900 49700 43400 49700 4
N 42900 47900 45500 47900 4
C 45900 48300 1 0 1 ibis_ebd-1.sym
{
T 47500 49650 5 10 1 1 0 6 1
value=VIRTEX_6_fcs_b spec={v6_spec}
T 45700 50300 5 10 0 0 0 6 1
symversion=1.0
T 46200 49050 5 10 1 1 0 6 1
refdes=X_V6_S_PKG
}
N 45100 48800 44100 48800 4
{
T 44100 48900 5 10 1 1 0 0 1
netname=v6_s_die
}
N 46400 48800 45900 48800 4
{
T 46000 48900 5 10 1 1 0 0 1
netname=v6_s_pin
}
C 52700 48300 1 0 0 ibis_ebd-1.sym
{
T 50800 49350 5 10 1 1 0 0 1
value=N25Q128A11BF840F_Sc spec={n25q_spec}
T 52900 50300 5 10 0 0 0 0 1
symversion=1.0
T 52400 49050 5 10 1 1 0 0 1
refdes=X_N25Q_S_PKG
}
N 52700 48800 52100 48800 4
{
T 51900 48500 5 10 1 1 0 0 1
netname=n25q_s_pin
}
N 54800 48800 53500 48800 4
{
T 53800 48900 5 10 1 1 0 0 1
netname=n25q_s_die
}
C 55300 49700 1 0 0 generic-power.sym
{
T 55500 49950 5 10 1 1 0 3 1
net=Vcc_n25q:1
}
C 55700 47900 1 180 0 generic-power.sym
{
T 55500 47650 5 10 1 1 180 3 1
net=Vss_n25q:1
}
C 43600 49700 1 0 1 generic-power.sym
{
T 43400 49950 5 10 1 1 0 3 1
net=Vcc_v6:1
}
N 45500 48300 45500 47900 4
N 41400 48400 40700 48400 4
{
T 40700 48400 5 10 1 1 0 0 1
netname=high
}
N 41400 49200 40400 49200 4
{
T 40400 49300 5 10 1 1 0 0 1
netname=clk_30MHz
}
N 57500 48800 58400 48800 4
{
T 57500 48800 5 10 1 1 0 0 1
netname=n25q_s_in
}
C 42200 45700 1 0 0 spice-directive-1.sym
{
T 42300 46000 5 10 0 1 0 0 1
device=directive
T 42200 46100 5 10 1 1 0 0 1
refdes=A_S
T 42100 45900 5 10 1 1 180 6 11
value=.lib n25q128a11bf8.lib CS_BUF
.lib virtex6.lib LVCMOS18_F_12
.lib n25q128a11bf8.lib N25Q128A11BF840F
.lib top.lib VIRTEX_6

.model clock_30MHz d_osc(rise_delay=1f fall_delay=1f cntl_array=[0 1] freq_array=[30Meg 30Meg])
A_clock_30MHz 0 clk_30MHz clock_30MHz

.model delay_5n d_buffer(rise_delay=5n fall_delay=5n input_load=0)
A_select_delay clk_30MHz select_out delay_5n

}
C 49900 48400 1 0 0 tline.sym
{
T 50800 48800 5 10 0 1 0 0 1
device=T-Line
T 50750 48350 5 10 1 1 0 0 1
refdes=Y_S1
T 50300 49100 5 10 1 1 0 0 1
value=m55 len=6.3m
}
C 48700 48700 1 0 0 resistor-1.sym
{
T 49000 49100 5 10 0 0 0 0 1
device=RESISTOR
T 48900 49000 5 10 1 1 0 0 1
refdes=R_s
T 49300 49000 5 10 1 1 0 0 1
value=100
}
N 49600 48800 49900 48800 4
C 46700 48100 1 0 0 gnd-1.sym
C 46400 48400 1 0 0 tline.sym
{
T 47300 48800 5 10 0 1 0 0 1
device=T-Line
T 47250 48350 5 10 1 1 0 0 1
refdes=Y_S0
T 46800 49100 5 10 1 1 0 0 1
value=m55 len=5.9m
}
C 48100 48100 1 0 0 gnd-1.sym
N 48600 48800 48700 48800 4
C 43300 47600 1 0 0 gnd-1.sym
C 53000 48000 1 0 0 gnd-1.sym