russdill

#!/bin/sh

CLOCK=162
LATCH=161
DATA=145
PIN_MUX=uart2_rts
PIN_MUX_VAL=4

gpio_init()
{

russdill

#!/usr/bin/env python
#
#  pnp.py
#
#  Copyright (C) 2012 Russ Dill <Russ.Dill@asu.edu>
#
#  This program is free software: you can redistribute it and/or modify
#  it under the terms of the GNU General Public License as published by
#  the Free Software Foundation, either version 2 of the License, or
#  (at your option) any later version.

russdill

/* Copyright 2012, Russ.Dill@asu.edu
 * Released under LGPLv2 or later */
#include <math.h>

#include "config.h"
#include "data.h"
#include "rtree.h"
#include "mirror.h"
#include "remove.h"
#include "select.h"

russdill

#!/usr/bin/python

import xml.etree.ElementTree as ET
import sys

try:
	tree = ET.parse(sys.argv[1])
except:
	tree = ET.parse(sys.stdin)
root = tree.getroot()

russdill

#!/usr/bin/python

import socket
import select
import fcntl
import struct
import errno
import os
import asyncore
import sys

russdill

`timescale 1ns / 1ps

module nonzero_cla #(
	parameter N = 7,
	parameter W = 6		/* Number of inputs per LUT */
) (
	input [N-1:0] in,
	output out
);
	if (N <= W)

russdill

`timescale 1ns / 1ps

module xor_cla #(
	parameter N = 4,
	parameter W = 6
) (
	input [N-1:0] in,
	output out,
	output outn
);

russdill

v 20110115 2
C 40900 50700 1 0 0 spice-directive-1.sym
{
T 41000 51000 5 10 0 1 0 0 1
device=directive
T 41000 51100 5 10 1 1 0 0 1
refdes=Misc
T 40900 50900 5 10 1 1 180 6 27
value=.model pulldown d_pulldown(load=0)
.model pullup d_pullup(load=0)

russdill

v 20110115 2
C 50500 35800 1 180 0 generic-power.sym
{
T 50300 35550 5 10 1 1 180 3 1
net=Vss_n25q:1
}
C 50100 37800 1 0 0 generic-power.sym
{
T 50300 38050 5 10 1 1 0 3 1
net=Vcc_n25q:1

russdill

v 20110115 2
C 41400 47900 1 0 0 ibis_io.sym
{
T 40700 47250 5 10 1 1 0 0 1
value=LVCMOS18_F_12 spec={v6_spec} start_on=0
T 41600 49900 5 10 0 0 0 0 1
symversion=1.0
T 41600 49750 5 10 1 1 0 0 1
refdes=X_V6_S
}