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@rygorous
rygorous / gist:5534382
Last active December 17, 2015 02:19 — forked from anonymous/gist:5534375
Instruction decode/dispatch variants

Okay, here's the different op splitting/fusing strategies for different cores, as far as I've been able to discern them:

  • Pentium: Complex instructions are U-pipe only but execute directly, they don't get split.
  • Atom (Bonnel/Saltwell): Certain complex instructions don't get split.
  • Pentium Pro/2/3: All ops get split into, tracked as, and executed as uOps.
  • Pentium 4: This never happened.
  • Pentium M/Core: All ops get split into uOps. Post-split, the core can fuse two types of multi-uOp sequences into a larger fused op used for tracking:
  • For stores, address generation + actual store uOps can get fused.
/**
* @author mrdoob / http://mrdoob.com/
* @author mraleph / http://mrale.ph/
* @author ryg / http://farbrausch.de/~fg
*/
THREE.SoftwareRenderer = function () {
console.log( 'THREE.SoftwareRenderer', THREE.REVISION );