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ryo/rk3588.netbsd.log

Created August 21, 2022 20:05
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netbsd/evbarm on rk3588 evb on 2022-08-22
Raw
rk3588.netbsd.log
[ 1.000000] SMCCC: Version 0x10002 (SMC)
[ 1.000000] pool redzone disabled for 'pcache'
[ 1.000000] pool redzone disabled for 'kmem-02048'
[ 1.000000] pool redzone disabled for 'kmem-04096'
[ 1.000000] Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
[ 1.000000] 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017,
[ 1.000000] 2018, 2019, 2020, 2021, 2022
[ 1.000000] The NetBSD Foundation, Inc. All rights reserved.
[ 1.000000] Copyright (c) 1982, 1986, 1989, 1991, 1993
[ 1.000000] The Regents of the University of California. All rights reserved.
[ 1.000000] NetBSD 9.99.99 (GENERIC64.RK3588) #380: Mon Aug 22 05:01:25 JST 2022
[ 1.000000] ryo@subq:/usr/src/sys/arch/evbarm/compile/GENERIC64.RK3588
[ 1.000000] total memory = 16086 MB
[ 1.000000] avail memory = 15507 MB
[ 1.000000] pool redzone disabled for 'buf2k'
[ 1.000000] pool redzone disabled for 'buf4k'
[ 1.000000] pool redzone disabled for 'buf32k'
[ 1.000000] pool redzone disabled for 'buf64k'
[ 1.000000] entropy: no seed from bootloader
[ 1.000000] pool redzone disabled for 'sigacts'
[ 1.000000] pool redzone disabled for 'mclpl'
[ 1.000000] timecounter: Timecounters tick every 10.000 msec
[ 1.000000] Kernelized RAIDframe activated
[ 1.000000] armfdt0 (root)
[ 1.000000] simplebus0 at armfdt0: Rockchip RK3588 EVB4 LP4 V10 Board
[ 1.000000] simplebus0: set default config for clocks
[ 1.000000] simplebus1 at simplebus0 (/clocks)
[ 1.000000] simplebus0: set default config for cpus
[ 1.000000] cpus0 at simplebus0 (/cpus)
[ 1.000000] simplebus0: set default config for chosen
[ 1.000000] simplebus2 at simplebus0 (/chosen)
[ 1.000000] simplebus0: set default config for psci
[ 1.000000] psci0 at simplebus0 (/psci): PSCI 1.1
[ 1.000000] cpus0: set default config for cpu@0
[ 1.000000] cpu0 at cpus0 (/cpus/cpu@0): Arm Cortex-A55 r2p0 (v8.2-A+), id 0x0
[ 1.000000] cpu0: package 0, core 0, smt 0
[ 1.000000] cpu0: IC enabled, DC enabled, EL0/EL1 stack Alignment check enabled
[ 1.000000] cpu0: Cache Writeback Granule 16B, Exclusives Reservation Granule 16B
[ 1.000000] cpu0: Dcache line 64, Icache line 64, DIC=0, IDC=0, LoUU=0, LoC=3, LoUIS=0
[ 1.000000] cpu0: L1 32KB/64B 4-way (128 set) VIPT Instruction cache
[ 1.000000] cpu0: L1 32KB/64B 4-way (128 set) PIPT Data cache
[ 1.000000] cpu0: L2 128KB/64B 4-way (512 set) PIPT Unified cache
[ 1.000000] cpu0: L3 4096KB/64B 16-way (4096 set) PIPT Unified cache
[ 1.000000] cpu0: midr=0x412fd050 mpidr=0x81000000
[ 1.000000] cpu0: revID=0x0, 4k table, 16k table, 64k table, 16bit ASID
[ 1.000000] cpu0: auxID=0x100010211120, GICv3, FP, CRC32, SHA1, SHA256, AES+PMULL, NEON, rounding, NaN propagation, denormals, 32x64bitRegs, Fused Multiply-Add
[ 1.000000] cpufreqdt0 at cpu0
[ 1.000000] cpus0: set default config for cpu@100
[ 1.000000] cpu1 at cpus0 (/cpus/cpu@100): Arm Cortex-A55 r2p0 (v8.2-A+), id 0x100
[ 1.000000] cpu1: package 0, core 1, smt 0
[ 1.000000] cpu1: IC enabled, DC enabled, EL0/EL1 stack Alignment check enabled
[ 1.000000] cpu1: Cache Writeback Granule 16B, Exclusives Reservation Granule 16B
[ 1.000000] cpu1: Dcache line 64, Icache line 64, DIC=0, IDC=0, LoUU=0, LoC=3, LoUIS=0
[ 1.000000] cpu1: L1 32KB/64B 4-way (128 set) VIPT Instruction cache
[ 1.000000] cpu1: L1 32KB/64B 4-way (128 set) PIPT Data cache
[ 1.000000] cpu1: L2 128KB/64B 4-way (512 set) PIPT Unified cache
[ 1.000000] cpu1: L3 4096KB/64B 16-way (4096 set) PIPT Unified cache
[ 1.000000] cpu1: midr=0x412fd050 mpidr=0x81000100
[ 1.000000] cpu1: revID=0x0, 4k table, 16k table, 64k table, 16bit ASID
[ 1.000000] cpu1: auxID=0x100010211120, GICv3, FP, CRC32, SHA1, SHA256, AES+PMULL, NEON, rounding, NaN propagation, denormals, 32x64bitRegs, Fused Multiply-Add
[ 1.000000] cpufreqdt1 at cpu1
[ 1.000000] cpus0: set default config for cpu@200
[ 1.000000] cpu2 at cpus0 (/cpus/cpu@200): Arm Cortex-A55 r2p0 (v8.2-A+), id 0x200
[ 1.000000] cpu2: package 0, core 2, smt 0
[ 1.000000] cpu2: IC enabled, DC enabled, EL0/EL1 stack Alignment check enabled
[ 1.000000] cpu2: Cache Writeback Granule 16B, Exclusives Reservation Granule 16B
[ 1.000000] cpu2: Dcache line 64, Icache line 64, DIC=0, IDC=0, LoUU=0, LoC=3, LoUIS=0
[ 1.000000] cpu2: L1 32KB/64B 4-way (128 set) VIPT Instruction cache
[ 1.000000] cpu2: L1 32KB/64B 4-way (128 set) PIPT Data cache
[ 1.000000] cpu2: L2 128KB/64B 4-way (512 set) PIPT Unified cache
[ 1.000000] cpu2: L3 4096KB/64B 16-way (4096 set) PIPT Unified cache
[ 1.000000] cpu2: midr=0x412fd050 mpidr=0x81000200
[ 1.000000] cpu2: revID=0x0, 4k table, 16k table, 64k table, 16bit ASID
[ 1.000000] cpu2: auxID=0x100010211120, GICv3, FP, CRC32, SHA1, SHA256, AES+PMULL, NEON, rounding, NaN propagation, denormals, 32x64bitRegs, Fused Multiply-Add
[ 1.000000] cpufreqdt2 at cpu2
[ 1.000000] cpus0: set default config for cpu@300
[ 1.000000] cpu3 at cpus0 (/cpus/cpu@300): Arm Cortex-A55 r2p0 (v8.2-A+), id 0x300
[ 1.000000] cpu3: package 0, core 3, smt 0
[ 1.000000] cpu3: IC enabled, DC enabled, EL0/EL1 stack Alignment check enabled
[ 1.000000] cpu3: Cache Writeback Granule 16B, Exclusives Reservation Granule 16B
[ 1.000000] cpu3: Dcache line 64, Icache line 64, DIC=0, IDC=0, LoUU=0, LoC=3, LoUIS=0
[ 1.000000] cpu3: L1 32KB/64B 4-way (128 set) VIPT Instruction cache
[ 1.000000] cpu3: L1 32KB/64B 4-way (128 set) PIPT Data cache
[ 1.000000] cpu3: L2 128KB/64B 4-way (512 set) PIPT Unified cache
[ 1.000000] cpu3: L3 4096KB/64B 16-way (4096 set) PIPT Unified cache
[ 1.000000] cpu3: midr=0x412fd050 mpidr=0x81000300
[ 1.000000] cpu3: revID=0x0, 4k table, 16k table, 64k table, 16bit ASID
[ 1.000000] cpu3: auxID=0x100010211120, GICv3, FP, CRC32, SHA1, SHA256, AES+PMULL, NEON, rounding, NaN propagation, denormals, 32x64bitRegs, Fused Multiply-Add
[ 1.000000] cpufreqdt3 at cpu3
[ 1.000000] cpus0: set default config for cpu@400
[ 1.000000] cpu4 at cpus0 (/cpus/cpu@400): Arm Cortex-A76 r4p0 (v8.2-A+), id 0x400
[ 1.000000] cpu4: package 0, core 4, smt 0
[ 1.000000] cpu4: IC enabled, DC enabled, EL0/EL1 stack Alignment check enabled
[ 1.000000] cpu4: Cache Writeback Granule 16B, Exclusives Reservation Granule 16B
[ 1.000000] cpu4: Dcache line 64, Icache line 64, DIC=0, IDC=1, LoUU=0, LoC=3, LoUIS=0
[ 1.000000] cpu4: L1 64KB/64B 4-way (256 set) PIPT Instruction cache
[ 1.000000] cpu4: L1 64KB/64B 4-way (256 set) PIPT Data cache
[ 1.000000] cpu4: L2 512KB/64B 8-way (1024 set) PIPT Unified cache
[ 1.000000] cpu4: L3 4096KB/64B 16-way (4096 set) PIPT Unified cache
[ 1.000000] cpu4: midr=0x414fd0b0 mpidr=0x81000400
[ 1.000000] cpu4: revID=0x0, 4k table, 16k table, 64k table, 16bit ASID
[ 1.000000] cpu4: auxID=0x100010211120, CSV3, CSV2, GICv3, FP, CRC32, SHA1, SHA256, AES+PMULL, NEON, rounding, NaN propagation, denormals, 32x64bitRegs, Fused Multiply-Add
[ 1.000000] cpufreqdt4 at cpu4
[ 1.000000] cpus0: set default config for cpu@500
[ 1.000000] cpu5 at cpus0 (/cpus/cpu@500): Arm Cortex-A76 r4p0 (v8.2-A+), id 0x500
[ 1.000000] cpu5: package 0, core 5, smt 0
[ 1.000000] cpu5: IC enabled, DC enabled, EL0/EL1 stack Alignment check enabled
[ 1.000000] cpu5: Cache Writeback Granule 16B, Exclusives Reservation Granule 16B
[ 1.000000] cpu5: Dcache line 64, Icache line 64, DIC=0, IDC=1, LoUU=0, LoC=3, LoUIS=0
[ 1.000000] cpu5: L1 64KB/64B 4-way (256 set) PIPT Instruction cache
[ 1.000000] cpu5: L1 64KB/64B 4-way (256 set) PIPT Data cache
[ 1.000000] cpu5: L2 512KB/64B 8-way (1024 set) PIPT Unified cache
[ 1.000000] cpu5: L3 4096KB/64B 16-way (4096 set) PIPT Unified cache
[ 1.000000] cpu5: midr=0x414fd0b0 mpidr=0x81000500
[ 1.000000] cpu5: revID=0x0, 4k table, 16k table, 64k table, 16bit ASID
[ 1.000000] cpu5: auxID=0x100010211120, CSV3, CSV2, GICv3, FP, CRC32, SHA1, SHA256, AES+PMULL, NEON, rounding, NaN propagation, denormals, 32x64bitRegs, Fused Multiply-Add
[ 1.000000] cpufreqdt5 at cpu5
[ 1.000000] cpus0: set default config for cpu@600
[ 1.000000] cpu6 at cpus0 (/cpus/cpu@600): Arm Cortex-A76 r4p0 (v8.2-A+), id 0x600
[ 1.000000] cpu6: package 0, core 6, smt 0
[ 1.000000] cpu6: IC enabled, DC enabled, EL0/EL1 stack Alignment check enabled
[ 1.000000] cpu6: Cache Writeback Granule 16B, Exclusives Reservation Granule 16B
[ 1.000000] cpu6: Dcache line 64, Icache line 64, DIC=0, IDC=1, LoUU=0, LoC=3, LoUIS=0
[ 1.000000] cpu6: L1 64KB/64B 4-way (256 set) PIPT Instruction cache
[ 1.000000] cpu6: L1 64KB/64B 4-way (256 set) PIPT Data cache
[ 1.000000] cpu6: L2 512KB/64B 8-way (1024 set) PIPT Unified cache
[ 1.000000] cpu6: L3 4096KB/64B 16-way (4096 set) PIPT Unified cache
[ 1.000000] cpu6: midr=0x414fd0b0 mpidr=0x81000600
[ 1.000000] cpu6: revID=0x0, 4k table, 16k table, 64k table, 16bit ASID
[ 1.000000] cpu6: auxID=0x100010211120, CSV3, CSV2, GICv3, FP, CRC32, SHA1, SHA256, AES+PMULL, NEON, rounding, NaN propagation, denormals, 32x64bitRegs, Fused Multiply-Add
[ 1.000000] cpufreqdt6 at cpu6
[ 1.000000] cpus0: set default config for cpu@700
[ 1.000000] cpu7 at cpus0 (/cpus/cpu@700): Arm Cortex-A76 r4p0 (v8.2-A+), id 0x700
[ 1.000000] cpu7: package 0, core 7, smt 0
[ 1.000000] cpu7: IC enabled, DC enabled, EL0/EL1 stack Alignment check enabled
[ 1.000000] cpu7: Cache Writeback Granule 16B, Exclusives Reservation Granule 16B
[ 1.000000] cpu7: Dcache line 64, Icache line 64, DIC=0, IDC=1, LoUU=0, LoC=3, LoUIS=0
[ 1.000000] cpu7: L1 64KB/64B 4-way (256 set) PIPT Instruction cache
[ 1.000000] cpu7: L1 64KB/64B 4-way (256 set) PIPT Data cache
[ 1.000000] cpu7: L2 512KB/64B 8-way (1024 set) PIPT Unified cache
[ 1.000000] cpu7: L3 4096KB/64B 16-way (4096 set) PIPT Unified cache
[ 1.000000] cpu7: midr=0x414fd0b0 mpidr=0x81000700
[ 1.000000] cpu7: revID=0x0, 4k table, 16k table, 64k table, 16bit ASID
[ 1.000000] cpu7: auxID=0x100010211120, CSV3, CSV2, GICv3, FP, CRC32, SHA1, SHA256, AES+PMULL, NEON, rounding, NaN propagation, denormals, 32x64bitRegs, Fused Multiply-Add
[ 1.000000] cpufreqdt7 at cpu7
[ 1.000000] simplebus0: set default config for interrupt-controller@fe600000
[ 1.000000] gicvthree0 at simplebus0 (/interrupt-controller@fe600000): GICv3
[ 1.000000] gicvthree0: 8 redistributors
[ 1.000000] gicvthree0: iidr 0x0201743b, cpuif non-secure, dist non-secure, priority shift 4, pmr shift 4, quirks 0
[ 1.000000] gicvthree0: redist 0: cpu 0.0.0.0
[ 1.000000] gicvthree0: redist 1: cpu 0.0.1.0
[ 1.000000] gicvthree0: redist 2: cpu 0.0.2.0
[ 1.000000] gicvthree0: redist 3: cpu 0.0.3.0
[ 1.000000] gicvthree0: redist 4: cpu 0.0.4.0
[ 1.000000] gicvthree0: redist 5: cpu 0.0.5.0
[ 1.000000] gicvthree0: redist 6: cpu 0.0.6.0
[ 1.000000] gicvthree0: redist 7: cpu 0.0.7.0
[ 1.000000] gicvthree0: ITS [#0] Devices table @ 0x291000/0x80000, Cacheable WA WB, Inner shareable
[ 1.000000] gicvthree0: ITS [#1] Collections table @ 0x311000/0x1000, Cacheable WA WB, Inner shareable
[ 1.000000] gicvthree0: ITS @ 0xfe640000
[ 1.000000] gicvthree0: ITS [#0] Devices table @ 0x321000/0x80000, Cacheable WA WB, Inner shareable
[ 1.000000] gicvthree0: ITS [#1] Collections table @ 0x3a1000/0x1000, Cacheable WA WB, Inner shareable
[ 1.000000] gicvthree0: ITS @ 0xfe660000
[ 1.000000] simplebus0: set default config for syscon@fd594000
[ 1.000000] syscon0 at simplebus0 (/syscon@fd594000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd590000
[ 1.000000] syscon1 at simplebus0 (/syscon@fd590000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd592000
[ 1.000000] syscon2 at simplebus0 (/syscon@fd592000): System Controller Registers
[ 1.000000] simplebus0: set default config for power-management@fd8d8000
[ 1.000000] syscon3 at simplebus0 (/power-management@fd8d8000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5a0000
[ 1.000000] syscon4 at simplebus0 (/syscon@fd5a0000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5d0000
[ 1.000000] syscon5 at simplebus0 (/syscon@fd5d0000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5d8000
[ 1.000000] syscon6 at simplebus0 (/syscon@fd5d8000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5dc000
[ 1.000000] syscon7 at simplebus0 (/syscon@fd5dc000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5ac000
[ 1.000000] syscon8 at simplebus0 (/syscon@fd5ac000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5b0000
[ 1.000000] syscon9 at simplebus0 (/syscon@fd5b0000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf72000
[ 1.000000] syscon10 at simplebus0 (/qos@fdf72000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf72200
[ 1.000000] syscon11 at simplebus0 (/qos@fdf72200): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf72400
[ 1.000000] syscon12 at simplebus0 (/qos@fdf72400): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf70000
[ 1.000000] syscon13 at simplebus0 (/qos@fdf70000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf71000
[ 1.000000] syscon14 at simplebus0 (/qos@fdf71000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf35000
[ 1.000000] syscon15 at simplebus0 (/qos@fdf35000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf35200
[ 1.000000] syscon16 at simplebus0 (/qos@fdf35200): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf35400
[ 1.000000] syscon17 at simplebus0 (/qos@fdf35400): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf35600
[ 1.000000] syscon18 at simplebus0 (/qos@fdf35600): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf62000
[ 1.000000] syscon19 at simplebus0 (/qos@fdf62000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf63000
[ 1.000000] syscon20 at simplebus0 (/qos@fdf63000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf60000
[ 1.000000] syscon21 at simplebus0 (/qos@fdf60000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf60200
[ 1.000000] syscon22 at simplebus0 (/qos@fdf60200): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf60400
[ 1.000000] syscon23 at simplebus0 (/qos@fdf60400): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf61000
[ 1.000000] syscon24 at simplebus0 (/qos@fdf61000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf61200
[ 1.000000] syscon25 at simplebus0 (/qos@fdf61200): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf61400
[ 1.000000] syscon26 at simplebus0 (/qos@fdf61400): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf66000
[ 1.000000] syscon27 at simplebus0 (/qos@fdf66000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf66200
[ 1.000000] syscon28 at simplebus0 (/qos@fdf66200): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf66400
[ 1.000000] syscon29 at simplebus0 (/qos@fdf66400): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf66600
[ 1.000000] syscon30 at simplebus0 (/qos@fdf66600): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf66800
[ 1.000000] syscon31 at simplebus0 (/qos@fdf66800): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf66a00
[ 1.000000] syscon32 at simplebus0 (/qos@fdf66a00): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf66c00
[ 1.000000] syscon33 at simplebus0 (/qos@fdf66c00): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf66e00
[ 1.000000] syscon34 at simplebus0 (/qos@fdf66e00): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf64000
[ 1.000000] syscon35 at simplebus0 (/qos@fdf64000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf67000
[ 1.000000] syscon36 at simplebus0 (/qos@fdf67000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf82000
[ 1.000000] syscon37 at simplebus0 (/qos@fdf82000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf82200
[ 1.000000] syscon38 at simplebus0 (/qos@fdf82200): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf80000
[ 1.000000] syscon39 at simplebus0 (/qos@fdf80000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf81000
[ 1.000000] syscon40 at simplebus0 (/qos@fdf81000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf81200
[ 1.000000] syscon41 at simplebus0 (/qos@fdf81200): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf40400
[ 1.000000] syscon42 at simplebus0 (/qos@fdf40400): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf40500
[ 1.000000] syscon43 at simplebus0 (/qos@fdf40500): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf40600
[ 1.000000] syscon44 at simplebus0 (/qos@fdf40600): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf40800
[ 1.000000] syscon45 at simplebus0 (/qos@fdf40800): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf41000
[ 1.000000] syscon46 at simplebus0 (/qos@fdf41000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf41100
[ 1.000000] syscon47 at simplebus0 (/qos@fdf41100): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf40000
[ 1.000000] syscon48 at simplebus0 (/qos@fdf40000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf40200
[ 1.000000] syscon49 at simplebus0 (/qos@fdf40200): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf36000
[ 1.000000] syscon50 at simplebus0 (/qos@fdf36000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf3e200
[ 1.000000] syscon51 at simplebus0 (/qos@fdf3e200): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf3e000
[ 1.000000] syscon52 at simplebus0 (/qos@fdf3e000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf3e400
[ 1.000000] syscon53 at simplebus0 (/qos@fdf3e400): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf3e600
[ 1.000000] syscon54 at simplebus0 (/qos@fdf3e600): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf39000
[ 1.000000] syscon55 at simplebus0 (/qos@fdf39000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf3d800
[ 1.000000] syscon56 at simplebus0 (/qos@fdf3d800): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5a2000
[ 1.000000] syscon57 at simplebus0 (/syscon@fd5a2000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd58c000
[ 1.000000] syscon58 at simplebus0 (/syscon@fd58c000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5a4000
[ 1.000000] syscon59 at simplebus0 (/syscon@fd5a4000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5a8000
[ 1.000000] syscon60 at simplebus0 (/syscon@fd5a8000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd58a000
[ 1.000000] syscon61 at simplebus0 (/syscon@fd58a000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5e0000
[ 1.000000] syscon62 at simplebus0 (/syscon@fd5e0000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5c8000
[ 1.000000] syscon63 at simplebus0 (/syscon@fd5c8000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5a6000
[ 1.000000] syscon64 at simplebus0 (/syscon@fd5a6000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5e8000
[ 1.000000] syscon65 at simplebus0 (/syscon@fd5e8000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5ec000
[ 1.000000] syscon66 at simplebus0 (/syscon@fd5ec000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5b4000
[ 1.000000] syscon67 at simplebus0 (/syscon@fd5b4000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5bc000
[ 1.000000] syscon68 at simplebus0 (/syscon@fd5bc000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5c4000
[ 1.000000] syscon69 at simplebus0 (/syscon@fd5c4000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5f0000
[ 1.000000] syscon70 at simplebus0 (/syscon@fd5f0000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5d4000
[ 1.000000] syscon71 at simplebus0 (/syscon@fd5d4000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5e4000
[ 1.000000] syscon72 at simplebus0 (/syscon@fd5e4000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5cc000
[ 1.000000] syscon73 at simplebus0 (/syscon@fd5cc000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5b5000
[ 1.000000] syscon74 at simplebus0 (/syscon@fd5b5000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5c0000
[ 1.000000] syscon75 at simplebus0 (/syscon@fd5c0000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd5b8000
[ 1.000000] syscon76 at simplebus0 (/syscon@fd5b8000): System Controller Registers
[ 1.000000] simplebus1: set default config for spll
[ 1.000000] fclock0 at simplebus1 (/clocks/spll): 702000000 Hz fixed clock (spll)
[ 1.000000] simplebus1: set default config for xin32k
[ 1.000000] fclock1 at simplebus1 (/clocks/xin32k): 32768 Hz fixed clock (xin32k)
[ 1.000000] simplebus1: set default config for xin24m
[ 1.000000] fclock2 at simplebus1 (/clocks/xin24m): 24000000 Hz fixed clock (xin24m)
[ 1.000000] simplebus0: set default config for syscon@fd588000
[ 1.000000] syscon77 at simplebus0 (/syscon@fd588000): System Controller Registers
[ 1.000000] simplebus0: set default config for syscon@fd598000
[ 1.000000] syscon78 at simplebus0 (/syscon@fd598000): System Controller Registers
[ 1.000000] simplebus0: set default config for qos@fdf67200
[ 1.000000] syscon79 at simplebus0 (/qos@fdf67200): System Controller Registers
[ 1.000000] simplebus0: set default config for clock-controller@fd7c0000
[ 1.000000] rkcru0 at simplebus0 (/clock-controller@fd7c0000): RK3588 CRU
[ 1.000000] rkcru0: 1 b0pll <- xin24m pll 1200000000 Hz
[ 1.000000] rkcru0: 2 b1pll <- xin24m pll 1200000000 Hz
[ 1.000000] rkcru0: 3 lpll <- xin24m pll 1200000000 Hz
[ 1.000000] rkcru0: 4 v0pll <- xin24m pll 1188000000 Hz
[ 1.000000] rkcru0: 5 aupll <- xin24m pll 786431998 Hz
[ 1.000000] rkcru0: 6 cpll <- xin24m pll 1500000000 Hz
[ 1.000000] rkcru0: 7 gpll <- xin24m pll 1188000000 Hz
[ 1.000000] rkcru0: 8 npll <- xin24m pll 850000000 Hz
[ 1.000000] rkcru0: 9 ppll <- xin24m pll 100000000 Hz
[ 1.000000] rkcru0: 10 armclk_l <- lpll arm 1200000000 Hz
[ 1.000000] rkcru0: 11 armclk_b01 <- b0pll arm 1200000000 Hz
[ 1.000000] rkcru0: 11 armclk_b23 <- b1pll arm 1200000000 Hz
[ 1.000000] rkcru0: 20 pclk_bigcore0_root <- clk_50m_src comp 50000000 Hz
[ 1.000000] rkcru0: 21 pclk_bigcore0_pvtm <- pclk_bigcore0_root gate 50000000 Hz
[ 1.000000] rkcru0: 710 clk_bigcore0_pvtm <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 711 clk_core_bigcore0_pvtm <- armclk_b01 gate 1200000000 Hz
[ 1.000000] rkcru0: 22 pclk_bigcore1_root <- clk_50m_src comp 50000000 Hz
[ 1.000000] rkcru0: 23 pclk_bigcore1_pvtm <- pclk_bigcore1_root gate 50000000 Hz
[ 1.000000] rkcru0: 712 clk_bigcore1_pvtm <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 713 clk_core_bigcore1_pvtm <- armclk_b23 gate 1200000000 Hz
[ 1.000000] rkcru0: 234 clk_50m_src <- cpll comp 50000000 Hz
[ 1.000000] rkcru0: 235 clk_100m_src <- cpll comp 100000000 Hz
[ 1.000000] rkcru0: 236 clk_150m_src <- cpll comp 150000000 Hz
[ 1.000000] rkcru0: 237 clk_200m_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 238 clk_250m_src <- cpll comp 250000000 Hz
[ 1.000000] rkcru0: 239 clk_300m_src <- cpll comp 300000000 Hz
[ 1.000000] rkcru0: 240 clk_350m_src <- spll comp 351000000 Hz
[ 1.000000] rkcru0: 241 clk_400m_src <- gpll comp 396000000 Hz
[ 1.000000] rkcru0: 242 clk_450m_src <- gpll comp 475200000 Hz
[ 1.000000] rkcru0: 243 clk_500m_src <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 244 clk_600m_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 245 clk_650m_src <- lpll comp 400000000 Hz
[ 1.000000] rkcru0: 246 clk_700m_src <- spll comp 702000000 Hz
[ 1.000000] rkcru0: 247 clk_800m_src <- aupll comp 786431998 Hz
[ 1.000000] rkcru0: 248 clk_1000m_src <- cpll comp 1000000000 Hz
[ 1.000000] rkcru0: 249 clk_1200m_src <- gpll comp 1188000000 Hz
[ 1.000000] rkcru0: 250 aclk_top_m300_root <- clk_300m_src comp 300000000 Hz
[ 1.000000] rkcru0: 251 aclk_top_m500_root <- clk_500m_src comp 500000000 Hz
[ 1.000000] rkcru0: 252 aclk_top_m400_root <- clk_400m_src comp 396000000 Hz
[ 1.000000] rkcru0: 253 aclk_top_s200_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 254 aclk_top_s400_root <- clk_400m_src comp 396000000 Hz
[ 1.000000] rkcru0: 270 aclk_top_root <- aupll comp 786431998 Hz
[ 1.000000] rkcru0: 271 pclk_top_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 272 aclk_low_top_root <- gpll comp 396000000 Hz
[ 1.000000] rkcru0: 255 clk_mipi_camaraout_m0 <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 256 clk_mipi_camaraout_m1 <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 257 clk_mipi_camaraout_m2 <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 258 clk_mipi_camaraout_m3 <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 259 clk_mipi_camaraout_m4 <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 260 mclk_gmac0_out <- cpll comp 50000000 Hz
[ 1.000000] rkcru0: 261 refclko25m_eth0_out <- cpll comp 25000000 Hz
[ 1.000000] rkcru0: 262 refclko25m_eth1_out <- cpll comp 25000000 Hz
[ 1.000000] rkcru0: 263 clk_cifout_out <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 264 pclk_mipi_dcphy0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 265 pclk_mipi_dcphy1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 268 pclk_csiphy0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 269 pclk_csiphy1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 273 pclk_cru <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 0 sclk_dsu <- gpll comp 1188000000 Hz
[ 1.000000] rkcru0: 0 atclk_dsu <- sclk_dsu comp 297000000 Hz
[ 1.000000] rkcru0: 0 gicclk_dsu <- sclk_dsu comp 297000000 Hz
[ 1.000000] rkcru0: 0 aclkmp_dsu <- sclk_dsu comp 396000000 Hz
[ 1.000000] rkcru0: 0 aclkm_dsu <- sclk_dsu comp 594000000 Hz
[ 1.000000] rkcru0: 0 aclks_dsu <- sclk_dsu comp 396000000 Hz
[ 1.000000] rkcru0: 0 periph_dsu <- sclk_dsu comp 297000000 Hz
[ 1.000000] rkcru0: 0 cntclk_dsu <- periph_dsu comp 99000000 Hz
[ 1.000000] rkcru0: 0 tsclk_dsu <- periph_dsu comp 99000000 Hz
[ 1.000000] rkcru0: 24 pclk_dsu_s_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 25 pclk_dsu_root <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 26 pclk_dsu_ns_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 27 pclk_litcore_pvtm <- pclk_dsu_ns_root gate 100000000 Hz
[ 1.000000] rkcru0: 28 pclk_dbg <- pclk_dsu_root gate 198000000 Hz
[ 1.000000] rkcru0: 29 pclk_dsu <- pclk_dsu_root gate 198000000 Hz
[ 1.000000] rkcru0: 30 pclk_s_daplite <- pclk_dsu_ns_root gate 100000000 Hz
[ 1.000000] rkcru0: 31 pclk_m_daplite <- pclk_dsu_root gate 198000000 Hz
[ 1.000000] rkcru0: 714 clk_litcore_pvtm <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 715 clk_core_litcore_pvtm <- armclk_l gate 1200000000 Hz
[ 1.000000] rkcru0: 60 hclk_audio_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 61 pclk_audio_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 34 hclk_i2s2_2ch <- hclk_audio_root gate 198000000 Hz
[ 1.000000] rkcru0: 35 hclk_i2s3_2ch <- hclk_audio_root gate 198000000 Hz
[ 1.000000] rkcru0: 36 clk_i2s2_2ch_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 37 clk_i2s2_2ch_frac <- clk_i2s2_2ch_src comp 0 Hz
[ 1.000000] rkcru0: 38 clk_i2s2_2ch mux rk_cru_clock_get_rate: no parent for clk_i2s2_2ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 39 mclk_i2s2_2ch <- clk_i2s2_2ch gate rk_cru_clock_get_rate: no parent for clk_i2s2_2ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 40 i2s2_2ch_mclkout mux rk_cru_clock_get_rate: no parent for i2s2_2ch_mclkout
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 42 clk_i2s3_2ch_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 43 clk_i2s3_2ch_frac <- clk_i2s3_2ch_src comp 0 Hz
[ 1.000000] rkcru0: 44 clk_i2s3_2ch mux rk_cru_clock_get_rate: no parent for clk_i2s3_2ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 45 mclk_i2s3_2ch <- clk_i2s3_2ch gate rk_cru_clock_get_rate: no parent for clk_i2s3_2ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 41 clk_dac_acdcdig <- mclk_i2s3_2ch gate rk_cru_clock_get_rate: no parent for clk_i2s3_2ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 46 i2s3_2ch_mclkout mux rk_cru_clock_get_rate: no parent for i2s3_2ch_mclkout
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 47 pclk_acdcdig <- pclk_audio_root gate 100000000 Hz
[ 1.000000] rkcru0: 48 hclk_i2s0_8ch <- hclk_audio_root gate 198000000 Hz
[ 1.000000] rkcru0: 49 clk_i2s0_8ch_tx_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 50 clk_i2s0_8ch_tx_frac <- clk_i2s0_8ch_tx_src comp 0 Hz
[ 1.000000] rkcru0: 52 clk_i2s0_8ch_tx mux rk_cru_clock_get_rate: no parent for clk_i2s0_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 51 mclk_i2s0_8ch_tx <- clk_i2s0_8ch_tx gate rk_cru_clock_get_rate: no parent for clk_i2s0_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 53 clk_i2s0_8ch_rx_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 54 clk_i2s0_8ch_rx_frac <- clk_i2s0_8ch_rx_src comp 0 Hz
[ 1.000000] rkcru0: 56 clk_i2s0_8ch_rx mux rk_cru_clock_get_rate: no parent for clk_i2s0_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 55 mclk_i2s0_8ch_rx <- clk_i2s0_8ch_rx gate rk_cru_clock_get_rate: no parent for clk_i2s0_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 57 i2s0_8ch_mclkout mux rk_cru_clock_get_rate: no parent for i2s0_8ch_mclkout
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 58 hclk_pdm1 <- hclk_audio_root gate 198000000 Hz
[ 1.000000] rkcru0: 59 mclk_pdm1 <- cpll comp 300000000 Hz
[ 1.000000] rkcru0: 62 hclk_spdif0 <- hclk_audio_root gate 198000000 Hz
[ 1.000000] rkcru0: 63 clk_spdif0_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 64 clk_spdif0_frac <- clk_spdif0_src comp 0 Hz
[ 1.000000] rkcru0: 66 clk_spdif0 mux rk_cru_clock_get_rate: no parent for clk_spdif0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 65 mclk_spdif0 <- clk_spdif0 gate rk_cru_clock_get_rate: no parent for clk_spdif0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 68 hclk_spdif1 <- hclk_audio_root gate 198000000 Hz
[ 1.000000] rkcru0: 69 clk_spdif1_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 70 clk_spdif1_frac <- clk_spdif1_src comp 0 Hz
[ 1.000000] rkcru0: 67 clk_spdif1 mux rk_cru_clock_get_rate: no parent for clk_spdif1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 71 mclk_spdif1 <- clk_spdif1 gate rk_cru_clock_get_rate: no parent for clk_spdif1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 72 aclk_av1_root <- gpll comp 396000000 Hz
[ 1.000000] rkcru0: 74 pclk_av1_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 123 aclk_bus_root <- cpll comp 375000000 Hz
[ 1.000000] rkcru0: 76 pclk_mailbox0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 77 pclk_mailbox1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 78 pclk_mailbox2 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 79 pclk_pmu2 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 80 pclk_pmucm0_intmux <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 81 pclk_ddrcm0_intmux <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 83 pclk_pwm1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 84 clk_pwm1 <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 85 clk_pwm1_capture <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 86 pclk_pwm2 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 87 clk_pwm2 <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 88 clk_pwm2_capture <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 89 pclk_pwm3 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 90 clk_pwm3 <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 91 clk_pwm3_capture <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 92 pclk_bustimer0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 93 pclk_bustimer1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 94 clk_bus_timer_root <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 95 clk_bustimer0 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 96 clk_bustimer1 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 97 clk_bustimer2 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 98 clk_bustimer3 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 99 clk_bustimer4 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 100 clk_bustimer5 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 101 clk_bustimer6 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 102 clk_bustimer7 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 103 clk_bustimer8 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 104 clk_bustimer9 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 105 clk_bustimer10 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 106 clk_bustimer11 <- clk_bus_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 107 pclk_wdt0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 108 tclk_wdt0 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 111 pclk_can0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 112 clk_can0 <- gpll comp 99000000 Hz
[ 1.000000] rkcru0: 113 pclk_can1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 114 clk_can1 <- gpll comp 99000000 Hz
[ 1.000000] rkcru0: 115 pclk_can2 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 116 clk_can2 <- gpll comp 99000000 Hz
[ 1.000000] rkcru0: 117 aclk_decom <- aclk_bus_root gate 375000000 Hz
[ 1.000000] rkcru0: 118 pclk_decom <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 119 dclk_decom <- gpll comp 396000000 Hz
[ 1.000000] rkcru0: 120 aclk_dmac0 <- aclk_bus_root gate 375000000 Hz
[ 1.000000] rkcru0: 121 aclk_dmac1 <- aclk_bus_root gate 375000000 Hz
[ 1.000000] rkcru0: 122 aclk_dmac2 <- aclk_bus_root gate 375000000 Hz
[ 1.000000] rkcru0: 124 aclk_gic <- aclk_bus_root gate 375000000 Hz
[ 1.000000] rkcru0: 125 pclk_gpio1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 126 dbclk_gpio1 <- xin24m comp 12000000 Hz
[ 1.000000] rkcru0: 127 pclk_gpio2 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 128 dbclk_gpio2 <- xin24m comp 12000000 Hz
[ 1.000000] rkcru0: 129 pclk_gpio3 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 130 dbclk_gpio3 <- xin24m comp 12000000 Hz
[ 1.000000] rkcru0: 131 pclk_gpio4 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 132 dbclk_gpio4 <- xin24m comp 12000000 Hz
[ 1.000000] rkcru0: 133 pclk_i2c1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 134 pclk_i2c2 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 135 pclk_i2c3 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 136 pclk_i2c4 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 137 pclk_i2c5 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 138 pclk_i2c6 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 139 pclk_i2c7 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 140 pclk_i2c8 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 141 clk_i2c1 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 142 clk_i2c2 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 143 clk_i2c3 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 144 clk_i2c4 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 145 clk_i2c5 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 146 clk_i2c6 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 147 clk_i2c7 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 148 clk_i2c8 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 149 pclk_otpc_ns <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 150 clk_otpc_ns <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 151 clk_otpc_arb <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 153 clk_otp_phy_g <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 152 clk_otpc_auto_rd_g <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 156 pclk_saradc <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 157 clk_saradc <- xin24m comp 1000000 Hz
[ 1.000000] rkcru0: 158 pclk_spi0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 159 pclk_spi1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 160 pclk_spi2 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 161 pclk_spi3 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 162 pclk_spi4 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 163 clk_spi0 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 164 clk_spi1 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 165 clk_spi2 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 166 clk_spi3 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 167 clk_spi4 <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 168 aclk_spinlock <- aclk_bus_root gate 375000000 Hz
[ 1.000000] rkcru0: 169 pclk_tsadc <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 170 clk_tsadc <- xin24m comp 2000000 Hz
[ 1.000000] rkcru0: 171 pclk_uart1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 172 pclk_uart2 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 173 pclk_uart3 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 174 pclk_uart4 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 175 pclk_uart5 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 176 pclk_uart6 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 177 pclk_uart7 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 178 pclk_uart8 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 179 pclk_uart9 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 180 clk_uart1_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 181 clk_uart1_frac <- clk_uart1_src comp 0 Hz
[ 1.000000] rkcru0: 182 clk_uart1 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 183 sclk_uart1 <- clk_uart1 gate 24000000 Hz
[ 1.000000] rkcru0: 184 clk_uart2_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 185 clk_uart2_frac <- clk_uart2_src comp 0 Hz
[ 1.000000] rkcru0: 186 clk_uart2 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 187 sclk_uart2 <- clk_uart2 gate 24000000 Hz
[ 1.000000] rkcru0: 188 clk_uart3_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 189 clk_uart3_frac <- clk_uart3_src comp 0 Hz
[ 1.000000] rkcru0: 190 clk_uart3 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 191 sclk_uart3 <- clk_uart3 gate 24000000 Hz
[ 1.000000] rkcru0: 192 clk_uart4_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 193 clk_uart4_frac <- clk_uart4_src comp 0 Hz
[ 1.000000] rkcru0: 194 clk_uart4 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 195 sclk_uart4 <- clk_uart4 gate 24000000 Hz
[ 1.000000] rkcru0: 196 clk_uart5_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 197 clk_uart5_frac <- clk_uart5_src comp 0 Hz
[ 1.000000] rkcru0: 198 clk_uart5 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 199 sclk_uart5 <- clk_uart5 gate 24000000 Hz
[ 1.000000] rkcru0: 200 clk_uart6_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 201 clk_uart6_frac <- clk_uart6_src comp 0 Hz
[ 1.000000] rkcru0: 202 clk_uart6 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 203 sclk_uart6 <- clk_uart6 gate 24000000 Hz
[ 1.000000] rkcru0: 204 clk_uart7_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 205 clk_uart7_frac <- clk_uart7_src comp 0 Hz
[ 1.000000] rkcru0: 206 clk_uart7 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 207 sclk_uart7 <- clk_uart7 gate 24000000 Hz
[ 1.000000] rkcru0: 208 clk_uart8_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 209 clk_uart8_frac <- clk_uart8_src comp 0 Hz
[ 1.000000] rkcru0: 210 clk_uart8 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 211 sclk_uart8 <- clk_uart8 gate 24000000 Hz
[ 1.000000] rkcru0: 212 clk_uart9_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 213 clk_uart9_frac <- clk_uart9_src comp 0 Hz
[ 1.000000] rkcru0: 214 clk_uart9 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 215 sclk_uart9 <- clk_uart9 gate 24000000 Hz
[ 1.000000] rkcru0: 216 aclk_center_root <- clk_700m_src comp 702000000 Hz
[ 1.000000] rkcru0: 217 aclk_center_low_root <- clk_500m_src comp 500000000 Hz
[ 1.000000] rkcru0: 218 hclk_center_root <- clk_400m_src comp 396000000 Hz
[ 1.000000] rkcru0: 219 pclk_center_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 220 aclk_dma2ddr <- aclk_center_root gate 702000000 Hz
[ 1.000000] rkcru0: 221 aclk_ddr_sharemem <- aclk_center_low_root gate 500000000 Hz
[ 1.000000] rkcru0: 222 aclk_center_s200_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 223 aclk_center_s400_root <- clk_400m_src comp 396000000 Hz
[ 1.000000] rkcru0: 224 fclk_ddr_cm0_core <- hclk_center_root gate 396000000 Hz
[ 1.000000] rkcru0: 225 clk_ddr_timer_root <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 226 clk_ddr_timer0 <- clk_ddr_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 227 clk_ddr_timer1 <- clk_ddr_timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 228 tclk_wdt_ddr <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 228 clk_ddr_cm0_rtc <- xin32k comp 32768 Hz
[ 1.000000] rkcru0: 230 pclk_wdt <- pclk_center_root gate 100000000 Hz
[ 1.000000] rkcru0: 231 pclk_timer <- pclk_center_root gate 100000000 Hz
[ 1.000000] rkcru0: 232 pclk_dma2ddr <- pclk_center_root gate 100000000 Hz
[ 1.000000] rkcru0: 233 pclk_sharemem <- pclk_center_root gate 100000000 Hz
[ 1.000000] rkcru0: 275 clk_gpu_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 276 clk_gpu <- clk_gpu_src gate 198000000 Hz
[ 1.000000] rkcru0: 277 clk_gpu_coregroup <- clk_gpu_src gate 198000000 Hz
[ 1.000000] rkcru0: 278 clk_gpu_stacks <- clk_gpu_src comp 198000000 Hz
[ 1.000000] rkcru0: 280 clk_gpu_pvtm <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 281 clk_core_gpu_pvtm <- clk_gpu_src gate 198000000 Hz
[ 1.000000] rkcru0: 283 aclk_isp1_root <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 284 hclk_isp1_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 285 clk_isp1_core <- spll comp 702000000 Hz
[ 1.000000] rkcru0: 286 clk_isp1_core_marvin <- clk_isp1_core gate 702000000 Hz
[ 1.000000] rkcru0: 287 clk_isp1_core_vicap <- clk_isp1_core gate 702000000 Hz
[ 1.000000] rkcru0: 303 hclk_npu_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 304 clk_npu_dsu0 <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 305 pclk_npu_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 290 aclk_npu1 <- clk_npu_dsu0 gate 750000000 Hz
[ 1.000000] rkcru0: 291 hclk_npu1 <- hclk_npu_root gate 198000000 Hz
[ 1.000000] rkcru0: 292 aclk_npu2 <- clk_npu_dsu0 gate 750000000 Hz
[ 1.000000] rkcru0: 293 hclk_npu2 <- hclk_npu_root gate 198000000 Hz
[ 1.000000] rkcru0: 294 hclk_npu_cm0_root <- clk_400m_src comp 396000000 Hz
[ 1.000000] rkcru0: 295 fclk_npu_cm0_core <- hclk_npu_cm0_root gate 396000000 Hz
[ 1.000000] rkcru0: 296 clk_npu_cm0_rtc <- xin32k comp 32768 Hz
[ 1.000000] rkcru0: 297 pclk_npu_pvtm <- pclk_npu_root gate 100000000 Hz
[ 1.000000] rkcru0: 298 pclk_npu_grf <- pclk_npu_root gate 100000000 Hz
[ 1.000000] rkcru0: 299 clk_npu_pvtm <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 300 clk_core_npu_pvtm <- clk_npu_dsu0 gate 750000000 Hz
[ 1.000000] rkcru0: 301 aclk_npu0 <- clk_npu_dsu0 gate 750000000 Hz
[ 1.000000] rkcru0: 302 hclk_npu0 <- hclk_npu_root gate 198000000 Hz
[ 1.000000] rkcru0: 306 pclk_npu_timer <- pclk_npu_root gate 100000000 Hz
[ 1.000000] rkcru0: 307 clk_nputimer_root <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 308 clk_nputimer0 <- clk_nputimer_root gate 24000000 Hz
[ 1.000000] rkcru0: 309 clk_nputimer1 <- clk_nputimer_root gate 24000000 Hz
[ 1.000000] rkcru0: 310 pclk_npu_wdt <- pclk_npu_root gate 100000000 Hz
[ 1.000000] rkcru0: 311 tclk_npu_wdt <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 320 hclk_nvm_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 321 aclk_nvm_root <- cpll comp 300000000 Hz
[ 1.000000] rkcru0: 313 aclk_emmc <- aclk_nvm_root gate 300000000 Hz
[ 1.000000] rkcru0: 314 cclk_emmc <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 315 bclk_emmc <- cpll comp 300000000 Hz
[ 1.000000] rkcru0: 316 tmclk_emmc <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 317 sclk_sfc <- gpll comp 79200000 Hz
[ 1.000000] rkcru0: 322 clk_gmac0_ptp_ref <- cpll comp 100000000 Hz
[ 1.000000] rkcru0: 323 clk_gmac1_ptp_ref <- cpll comp 100000000 Hz
[ 1.000000] rkcru0: 324 clk_gmac_125m <- cpll comp 125000000 Hz
[ 1.000000] rkcru0: 325 clk_gmac_50m <- cpll comp 50000000 Hz
[ 1.000000] rkcru0: 361 aclk_pcie_root <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 362 aclk_php_root <- gpll comp 396000000 Hz
[ 1.000000] rkcru0: 358 pclk_php_root <- clk_150m_src comp 150000000 Hz
[ 1.000000] rkcru0: 326 aclk_php_gic_its <- aclk_pcie_root gate 500000000 Hz
[ 1.000000] rkcru0: 363 aclk_pcie_bridge <- aclk_pcie_root gate 500000000 Hz
[ 1.000000] rkcru0: 327 aclk_mmu_pcie <- aclk_pcie_bridge gate 500000000 Hz
[ 1.000000] rkcru0: 328 aclk_mmu_php <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 329 aclk_pcie_4l_dbi <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 330 aclk_pcie_2l_dbi <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 331 aclk_pcie_1l0_dbi <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 332 aclk_pcie_1l1_dbi <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 333 aclk_pcie_1l2_dbi <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 334 aclk_pcie_4l_mstr <- aclk_mmu_pcie gate 500000000 Hz
[ 1.000000] rkcru0: 335 aclk_pcie_2l_mstr <- aclk_mmu_pcie gate 500000000 Hz
[ 1.000000] rkcru0: 336 aclk_pcie_1l0_mstr <- aclk_mmu_pcie gate 500000000 Hz
[ 1.000000] rkcru0: 337 aclk_pcie_1l1_mstr <- aclk_mmu_pcie gate 500000000 Hz
[ 1.000000] rkcru0: 338 aclk_pcie_1l2_mstr <- aclk_mmu_pcie gate 500000000 Hz
[ 1.000000] rkcru0: 339 aclk_pcie_4l_slv <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 340 aclk_pcie_2l_slv <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 341 aclk_pcie_1l0_slv <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 342 aclk_pcie_1l1_slv <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 343 aclk_pcie_1l2_slv <- aclk_php_root gate 396000000 Hz
[ 1.000000] rkcru0: 344 pclk_pcie_4l <- pclk_php_root gate 150000000 Hz
[ 1.000000] rkcru0: 345 pclk_pcie_2l <- pclk_php_root gate 150000000 Hz
[ 1.000000] rkcru0: 347 pclk_pcie_1l0 <- pclk_php_root gate 150000000 Hz
[ 1.000000] rkcru0: 348 pclk_pcie_1l1 <- pclk_php_root gate 150000000 Hz
[ 1.000000] rkcru0: 349 pclk_pcie_1l2 <- pclk_php_root gate 150000000 Hz
[ 1.000000] rkcru0: 350 clk_pcie_aux0 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 351 clk_pcie_aux1 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 352 clk_pcie_aux2 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 353 clk_pcie_aux3 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 354 clk_pcie_aux4 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 355 clk_pipephy0_ref <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 356 clk_pipephy1_ref <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 357 clk_pipephy2_ref <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 359 pclk_gmac0 <- pclk_php_root gate 150000000 Hz
[ 1.000000] rkcru0: 360 pclk_gmac1 <- pclk_php_root gate 150000000 Hz
[ 1.000000] rkcru0: 364 aclk_gmac0 <- aclk_mmu_php gate 396000000 Hz
[ 1.000000] rkcru0: 365 aclk_gmac1 <- aclk_mmu_php gate 396000000 Hz
[ 1.000000] rkcru0: 366 clk_pmalive0 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 367 clk_pmalive1 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 368 clk_pmalive2 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 369 aclk_sata0 <- aclk_mmu_php gate 396000000 Hz
[ 1.000000] rkcru0: 370 aclk_sata1 <- aclk_mmu_php gate 396000000 Hz
[ 1.000000] rkcru0: 371 aclk_sata2 <- aclk_mmu_php gate 396000000 Hz
[ 1.000000] rkcru0: 372 clk_rxoob0 <- cpll comp 50000000 Hz
[ 1.000000] rkcru0: 373 clk_rxoob1 <- cpll comp 50000000 Hz
[ 1.000000] rkcru0: 374 clk_rxoob2 <- cpll comp 50000000 Hz
[ 1.000000] rkcru0: 375 aclk_usb3otg2 <- aclk_mmu_php gate 396000000 Hz
[ 1.000000] rkcru0: 376 suspend_clk_usb3otg2 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 377 ref_clk_usb3otg2 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 378 clk_utmi_otg2 <- clk_150m_src comp 30000000 Hz
[ 1.000000] rkcru0: 389 pclk_pcie_combo_pipe_phy0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 390 pclk_pcie_combo_pipe_phy1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 391 pclk_pcie_combo_pipe_phy2 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 392 pclk_pcie_combo_pipe_phy <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 395 clk_rga3_1_core <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 396 aclk_rga3_root <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 397 hclk_rga3_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 393 hclk_rga3_1 <- hclk_rga3_root gate 198000000 Hz
[ 1.000000] rkcru0: 394 aclk_rga3_1 <- aclk_rga3_root gate 750000000 Hz
[ 1.000000] rkcru0: 0 hclk_rkvdec0_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 0 aclk_rkvdec0_root <- aupll comp 786431998 Hz
[ 1.000000] rkcru0: 398 aclk_rkvdec_ccu <- aupll comp 786431998 Hz
[ 1.000000] rkcru0: 401 clk_rkvdec0_ca <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 402 clk_rkvdec0_hevc_ca <- clk_1000m_src comp 1000000000 Hz
[ 1.000000] rkcru0: 403 clk_rkvdec0_core <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 0 hclk_rkvdec1_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 0 aclk_rkvdec1_root <- aupll comp 786431998 Hz
[ 1.000000] rkcru0: 406 clk_rkvdec1_ca <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 407 clk_rkvdec1_hevc_ca <- clk_1000m_src comp 1000000000 Hz
[ 1.000000] rkcru0: 408 clk_rkvdec1_core <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 0 hclk_sdio_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 410 cclk_src_sdio <- gpll comp 297000000 Hz
[ 1.000000] rkcru0: 411 aclk_usb_root <- cpll comp 300000000 Hz
[ 1.000000] rkcru0: 412 hclk_usb_root <- clk_150m_src comp 150000000 Hz
[ 1.000000] rkcru0: 418 suspend_clk_usb3otg0 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 419 ref_clk_usb3otg0 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 421 suspend_clk_usb3otg1 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 422 ref_clk_usb3otg1 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 444 aclk_vdpu_root <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 445 aclk_vdpu_low_root <- clk_400m_src comp 396000000 Hz
[ 1.000000] rkcru0: 446 hclk_vdpu_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 447 aclk_jpeg_decoder_root <- spll comp 702000000 Hz
[ 1.000000] rkcru0: 425 hclk_iep2p0 <- hclk_vdpu_root gate 198000000 Hz
[ 1.000000] rkcru0: 427 clk_iep2p0_core <- gpll comp 396000000 Hz
[ 1.000000] rkcru0: 429 hclk_jpeg_encoder0 <- hclk_vdpu_root gate 198000000 Hz
[ 1.000000] rkcru0: 431 hclk_jpeg_encoder1 <- hclk_vdpu_root gate 198000000 Hz
[ 1.000000] rkcru0: 433 hclk_jpeg_encoder2 <- hclk_vdpu_root gate 198000000 Hz
[ 1.000000] rkcru0: 435 hclk_jpeg_encoder3 <- hclk_vdpu_root gate 198000000 Hz
[ 1.000000] rkcru0: 437 hclk_jpeg_decoder <- hclk_vdpu_root gate 198000000 Hz
[ 1.000000] rkcru0: 438 hclk_rga2 <- hclk_vdpu_root gate 198000000 Hz
[ 1.000000] rkcru0: 439 aclk_rga2 <- aclk_vdpu_root gate 750000000 Hz
[ 1.000000] rkcru0: 440 clk_rga2_core <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 441 hclk_rga3_0 <- hclk_vdpu_root gate 198000000 Hz
[ 1.000000] rkcru0: 442 aclk_rga3_0 <- aclk_vdpu_root gate 750000000 Hz
[ 1.000000] rkcru0: 443 clk_rga3_0_core <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 449 hclk_vpu <- hclk_vdpu_root gate 198000000 Hz
[ 1.000000] rkcru0: 455 hclk_rkvenc1_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 456 aclk_rkvenc1_root <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 450 hclk_rkvenc0_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 451 aclk_rkvenc0_root <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 452 hclk_rkvenc0 <- hclk_rkvenc0_root gate 198000000 Hz
[ 1.000000] rkcru0: 453 aclk_rkvenc0 <- aclk_rkvenc0_root gate 500000000 Hz
[ 1.000000] rkcru0: 454 clk_rkvenc0_core <- aupll comp 786431998 Hz
[ 1.000000] rkcru0: 459 clk_rkvenc1_core <- aupll comp 786431998 Hz
[ 1.000000] rkcru0: 480 aclk_vi_root <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 481 hclk_vi_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 482 pclk_vi_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 460 iclk_csihost01 <- clk_400m_src comp 396000000 Hz
[ 1.000000] rkcru0: 461 iclk_csihost0 <- iclk_csihost01 gate 396000000 Hz
[ 1.000000] rkcru0: 462 iclk_csihost1 <- iclk_csihost01 gate 396000000 Hz
[ 1.000000] rkcru0: 463 pclk_csi_host_0 <- pclk_vi_root gate 100000000 Hz
[ 1.000000] rkcru0: 464 pclk_csi_host_1 <- pclk_vi_root gate 100000000 Hz
[ 1.000000] rkcru0: 465 pclk_csi_host_2 <- pclk_vi_root gate 100000000 Hz
[ 1.000000] rkcru0: 466 pclk_csi_host_3 <- pclk_vi_root gate 100000000 Hz
[ 1.000000] rkcru0: 467 pclk_csi_host_4 <- pclk_vi_root gate 100000000 Hz
[ 1.000000] rkcru0: 468 pclk_csi_host_5 <- pclk_vi_root gate 100000000 Hz
[ 1.000000] rkcru0: 469 aclk_fisheye0 <- aclk_vi_root gate 750000000 Hz
[ 1.000000] rkcru0: 470 hclk_fisheye0 <- hclk_vi_root gate 198000000 Hz
[ 1.000000] rkcru0: 471 clk_fisheye0_core <- spll comp 702000000 Hz
[ 1.000000] rkcru0: 472 aclk_fisheye1 <- aclk_vi_root gate 750000000 Hz
[ 1.000000] rkcru0: 473 hclk_fisheye1 <- hclk_vi_root gate 198000000 Hz
[ 1.000000] rkcru0: 474 clk_fisheye1_core <- spll comp 702000000 Hz
[ 1.000000] rkcru0: 475 clk_isp0_core <- spll comp 702000000 Hz
[ 1.000000] rkcru0: 476 clk_isp0_core_marvin <- clk_isp0_core gate 702000000 Hz
[ 1.000000] rkcru0: 477 clk_isp0_core_vicap <- clk_isp0_core gate 702000000 Hz
[ 1.000000] rkcru0: 478 aclk_isp0 <- aclk_vi_root gate 750000000 Hz
[ 1.000000] rkcru0: 479 hclk_isp0 <- hclk_vi_root gate 198000000 Hz
[ 1.000000] rkcru0: 483 dclk_vicap <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 484 aclk_vicap <- aclk_vi_root gate 750000000 Hz
[ 1.000000] rkcru0: 485 hclk_vicap <- hclk_vi_root gate 198000000 Hz
[ 1.000000] rkcru0: 499 aclk_vo0_root <- gpll comp 396000000 Hz
[ 1.000000] rkcru0: 500 hclk_vo0_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 501 hclk_vo0_s_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 502 pclk_vo0_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 503 pclk_vo0_s_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 486 pclk_dp0 <- pclk_vo0_root gate 100000000 Hz
[ 1.000000] rkcru0: 487 pclk_dp1 <- pclk_vo0_root gate 100000000 Hz
[ 1.000000] rkcru0: 488 pclk_s_dp0 <- pclk_vo0_s_root gate 100000000 Hz
[ 1.000000] rkcru0: 489 pclk_s_dp1 <- pclk_vo0_s_root gate 100000000 Hz
[ 1.000000] rkcru0: 490 clk_dp0 <- aclk_vo0_root gate 396000000 Hz
[ 1.000000] rkcru0: 491 clk_dp1 <- aclk_vo0_root gate 396000000 Hz
[ 1.000000] rkcru0: 492 hclk_hdcp_key0 <- hclk_vo0_s_root gate 198000000 Hz
[ 1.000000] rkcru0: 495 pclk_hdcp0 <- pclk_vo0_root gate 100000000 Hz
[ 1.000000] rkcru0: 497 aclk_trng0 <- aclk_vo0_root gate 396000000 Hz
[ 1.000000] rkcru0: 498 pclk_trng0 <- pclk_vo0_root gate 100000000 Hz
[ 1.000000] rkcru0: 504 pclk_vo0grf <- pclk_vo0_root gate 100000000 Hz
[ 1.000000] rkcru0: 505 clk_i2s4_8ch_tx_src <- aupll comp 65535999 Hz
[ 1.000000] rkcru0: 506 clk_i2s4_8ch_tx_frac <- clk_i2s4_8ch_tx_src comp 0 Hz
[ 1.000000] rkcru0: 508 clk_i2s4_8ch_tx mux rk_cru_clock_get_rate: no parent for clk_i2s4_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 507 mclk_i2s4_8ch_tx <- clk_i2s4_8ch_tx gate rk_cru_clock_get_rate: no parent for clk_i2s4_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 511 clk_i2s8_8ch_tx_src <- aupll comp 65535999 Hz
[ 1.000000] rkcru0: 512 clk_i2s8_8ch_tx_frac <- clk_i2s8_8ch_tx_src comp 0 Hz
[ 1.000000] rkcru0: 514 clk_i2s8_8ch_tx mux rk_cru_clock_get_rate: no parent for clk_i2s8_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 513 mclk_i2s8_8ch_tx <- clk_i2s8_8ch_tx gate rk_cru_clock_get_rate: no parent for clk_i2s8_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 517 clk_spdif2_dp0_src <- aupll comp 393215999 Hz
[ 1.000000] rkcru0: 518 clk_spdif2_dp0_frac <- clk_spdif2_dp0_src comp 0 Hz
[ 1.000000] rkcru0: 520 clk_spdif2_dp0 <- clk_spdif2_dp0_src mux 393215999 Hz
[ 1.000000] rkcru0: 519 mclk_spdif2_dp0 <- clk_spdif2_dp0 gate 393215999 Hz
[ 1.000000] rkcru0: 521 mclk_spdif2 <- clk_spdif2_dp0 gate 393215999 Hz
[ 1.000000] rkcru0: 523 clk_spdif5_dp1_src <- aupll comp 393215999 Hz
[ 1.000000] rkcru0: 524 clk_spdif5_dp1_frac <- clk_spdif5_dp1_src comp 0 Hz
[ 1.000000] rkcru0: 526 clk_spdif5_dp1 <- clk_spdif5_dp1_src mux 393215999 Hz
[ 1.000000] rkcru0: 525 mclk_spdif5_dp1 <- clk_spdif5_dp1 gate 393215999 Hz
[ 1.000000] rkcru0: 527 mclk_spdif5 <- clk_spdif5_dp1 gate 393215999 Hz
[ 1.000000] rkcru0: 716 clk_aux16m_0 <- gpll comp 8027027 Hz
[ 1.000000] rkcru0: 717 clk_aux16m_1 <- gpll comp 8027027 Hz
[ 1.000000] rkcru0: 551 clk_hdmitrx_refsrc <- cpll comp 428571429 Hz
[ 1.000000] rkcru0: 554 aclk_hdcp1_root <- clk_hdmitrx_refsrc comp 428571429 Hz
[ 1.000000] rkcru0: 555 aclk_hdmirx_root <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 556 hclk_vo1_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 557 hclk_vo1_s_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 558 pclk_vo1_root <- clk_150m_src comp 150000000 Hz
[ 1.000000] rkcru0: 559 pclk_vo1_s_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 619 aclk_vop_root <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 620 aclk_vop_low_root <- clk_400m_src comp 396000000 Hz
[ 1.000000] rkcru0: 621 hclk_vop_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 622 pclk_vop_root <- clk_100m_src comp 100000000 Hz
[ 1.000000] rkcru0: 611 aclk_vo1usb_top_root <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 612 hclk_vo1usb_top_root <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 638 aclk_vop_sub_src <- aclk_vop_root mux 500000000 Hz
[ 1.000000] rkcru0: 528 pclk_edp0 <- pclk_vo1_root gate 150000000 Hz
[ 1.000000] rkcru0: 529 clk_edp0_24m <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 530 clk_edp0_200m <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 531 pclk_edp1 <- pclk_vo1_root gate 150000000 Hz
[ 1.000000] rkcru0: 532 clk_edp1_24m <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 533 clk_edp1_200m <- clk_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 534 hclk_hdcp_key1 <- hclk_vo1_s_root gate 198000000 Hz
[ 1.000000] rkcru0: 537 pclk_hdcp1 <- pclk_vo1_root gate 150000000 Hz
[ 1.000000] rkcru0: 538 aclk_hdmirx <- aclk_hdmirx_root gate 500000000 Hz
[ 1.000000] rkcru0: 539 pclk_hdmirx <- pclk_vo1_root gate 150000000 Hz
[ 1.000000] rkcru0: 540 clk_hdmirx_ref <- aclk_hdcp1_root gate 428571429 Hz
[ 1.000000] rkcru0: 541 clk_hdmirx_aud_src <- gpll comp 297000000 Hz
[ 1.000000] rkcru0: 542 clk_hdmirx_aud_frac <- clk_hdmirx_aud_src comp 0 Hz
[ 1.000000] rkcru0: 543 clk_hdmirx_aud gate rk_cru_clock_get_rate: no parent for clk_hdmirx_aud
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 545 pclk_hdmitx0 <- pclk_vo1_root gate 150000000 Hz
[ 1.000000] rkcru0: 546 clk_hdmitx0_earc <- cpll comp 100000000 Hz
[ 1.000000] rkcru0: 547 clk_hdmitx0_ref <- aclk_hdcp1_root gate 428571429 Hz
[ 1.000000] rkcru0: 548 pclk_hdmitx1 <- pclk_vo1_root gate 150000000 Hz
[ 1.000000] rkcru0: 549 clk_hdmitx1_earc <- cpll comp 100000000 Hz
[ 1.000000] rkcru0: 550 clk_hdmitx1_ref <- aclk_hdcp1_root gate 428571429 Hz
[ 1.000000] rkcru0: 552 aclk_trng1 <- aclk_hdcp1_root gate 428571429 Hz
[ 1.000000] rkcru0: 553 pclk_trng1 <- pclk_vo1_root gate 150000000 Hz
[ 1.000000] rkcru0: 0 pclk_vo1grf <- pclk_vo1_root gate 150000000 Hz
[ 1.000000] rkcru0: 560 pclk_s_edp0 <- pclk_vo1_s_root gate 100000000 Hz
[ 1.000000] rkcru0: 561 pclk_s_edp1 <- pclk_vo1_s_root gate 100000000 Hz
[ 1.000000] rkcru0: 562 pclk_s_hdmirx <- pclk_vo1_s_root gate 100000000 Hz
[ 1.000000] rkcru0: 564 clk_i2s10_8ch_rx_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 565 clk_i2s10_8ch_rx_frac <- clk_i2s10_8ch_rx_src comp 0 Hz
[ 1.000000] rkcru0: 566 clk_i2s10_8ch_rx mux rk_cru_clock_get_rate: no parent for clk_i2s10_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 567 mclk_i2s10_8ch_rx <- clk_i2s10_8ch_rx gate rk_cru_clock_get_rate: no parent for clk_i2s10_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 569 clk_i2s7_8ch_rx_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 570 clk_i2s7_8ch_rx_frac <- clk_i2s7_8ch_rx_src comp 0 Hz
[ 1.000000] rkcru0: 571 clk_i2s7_8ch_rx mux rk_cru_clock_get_rate: no parent for clk_i2s7_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 572 mclk_i2s7_8ch_rx <- clk_i2s7_8ch_rx gate rk_cru_clock_get_rate: no parent for clk_i2s7_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 575 clk_i2s9_8ch_rx_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 576 clk_i2s9_8ch_rx_frac <- clk_i2s9_8ch_rx_src comp 0 Hz
[ 1.000000] rkcru0: 577 clk_i2s9_8ch_rx mux rk_cru_clock_get_rate: no parent for clk_i2s9_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 578 mclk_i2s9_8ch_rx <- clk_i2s9_8ch_rx gate rk_cru_clock_get_rate: no parent for clk_i2s9_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 579 clk_i2s5_8ch_tx_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 580 clk_i2s5_8ch_tx_frac <- clk_i2s5_8ch_tx_src comp 0 Hz
[ 1.000000] rkcru0: 581 clk_i2s5_8ch_tx mux rk_cru_clock_get_rate: no parent for clk_i2s5_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 582 mclk_i2s5_8ch_tx <- clk_i2s5_8ch_tx gate rk_cru_clock_get_rate: no parent for clk_i2s5_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 585 clk_i2s6_8ch_tx_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 586 clk_i2s6_8ch_tx_frac <- clk_i2s6_8ch_tx_src comp 0 Hz
[ 1.000000] rkcru0: 587 clk_i2s6_8ch_tx mux rk_cru_clock_get_rate: no parent for clk_i2s6_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 588 mclk_i2s6_8ch_tx <- clk_i2s6_8ch_tx gate rk_cru_clock_get_rate: no parent for clk_i2s6_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 589 clk_i2s6_8ch_rx_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 590 clk_i2s6_8ch_rx_frac <- clk_i2s6_8ch_rx_src comp 0 Hz
[ 1.000000] rkcru0: 591 clk_i2s6_8ch_rx mux rk_cru_clock_get_rate: no parent for clk_i2s6_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 592 mclk_i2s6_8ch_rx <- clk_i2s6_8ch_rx gate rk_cru_clock_get_rate: no parent for clk_i2s6_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 593 i2s6_8ch_mclkout mux rk_cru_clock_get_rate: no parent for i2s6_8ch_mclkout
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 596 clk_spdif3_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 597 clk_spdif3_frac <- clk_spdif3_src comp 0 Hz
[ 1.000000] rkcru0: 598 clk_spdif3 <- clk_spdif3_src mux 198000000 Hz
[ 1.000000] rkcru0: 599 mclk_spdif3 <- clk_spdif3 gate 198000000 Hz
[ 1.000000] rkcru0: 601 clk_spdif4_src <- gpll comp 198000000 Hz
[ 1.000000] rkcru0: 602 clk_spdif4_frac <- clk_spdif4_src comp 0 Hz
[ 1.000000] rkcru0: 603 clk_spdif4 <- clk_spdif4_src mux 198000000 Hz
[ 1.000000] rkcru0: 604 mclk_spdif4 <- clk_spdif4 gate 198000000 Hz
[ 1.000000] rkcru0: 606 mclk_spdifrx0 <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 608 mclk_spdifrx1 <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 610 mclk_spdifrx2 <- cpll comp 500000000 Hz
[ 1.000000] rkcru0: 613 clk_hdmihdp0 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 614 clk_hdmihdp1 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 615 pclk_hdptx0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 616 pclk_hdptx1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 617 pclk_usbdpphy0 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 618 pclk_usbdpphy1 <- pclk_top_root gate 100000000 Hz
[ 1.000000] rkcru0: 623 hclk_vop <- hclk_vop_root gate 198000000 Hz
[ 1.000000] rkcru0: 624 aclk_vop <- aclk_vop_sub_src gate 500000000 Hz
[ 1.000000] rkcru0: 625 dclk_vop0_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 626 dclk_vop1_src <- gpll comp 594000000 Hz
[ 1.000000] rkcru0: 627 dclk_vop2_src <- v0pll comp 594000000 Hz
[ 1.000000] rkcru0: 628 dclk_vop0 <- dclk_vop0_src comp 594000000 Hz
[ 1.000000] rkcru0: 629 dclk_vop1 <- dclk_vop1_src comp 594000000 Hz
[ 1.000000] rkcru0: 630 dclk_vop2 <- dclk_vop2_src comp 594000000 Hz
[ 1.000000] rkcru0: 631 dclk_vop3 <- cpll comp 125000000 Hz
[ 1.000000] rkcru0: 632 pclk_dsihost0 <- pclk_vop_root gate 100000000 Hz
[ 1.000000] rkcru0: 633 pclk_dsihost1 <- pclk_vop_root gate 100000000 Hz
[ 1.000000] rkcru0: 634 clk_dsihost0 <- spll comp 351000000 Hz
[ 1.000000] rkcru0: 635 clk_dsihost1 <- spll comp 351000000 Hz
[ 1.000000] rkcru0: 636 clk_vop_pmu <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 637 aclk_vop_doby <- aclk_vop_root gate 500000000 Hz
[ 1.000000] rkcru0: 639 clk_usbdp_phy0_immortal <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 640 clk_usbdp_phy1_immortal <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 695 clk_ref_pipe_phy0_osc_src <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 696 clk_ref_pipe_phy1_osc_src <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 697 clk_ref_pipe_phy2_osc_src <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 698 clk_ref_pipe_phy0_pll_src <- ppll comp 100000000 Hz
[ 1.000000] rkcru0: 699 clk_ref_pipe_phy1_pll_src <- ppll comp 100000000 Hz
[ 1.000000] rkcru0: 700 clk_ref_pipe_phy2_pll_src <- ppll comp 100000000 Hz
[ 1.000000] rkcru0: 701 clk_ref_pipe_phy0 <- clk_ref_pipe_phy0_osc_src mux 24000000 Hz
[ 1.000000] rkcru0: 702 clk_ref_pipe_phy1 <- clk_ref_pipe_phy1_osc_src mux 24000000 Hz
[ 1.000000] rkcru0: 703 clk_ref_pipe_phy2 <- clk_ref_pipe_phy2_osc_src mux 24000000 Hz
[ 1.000000] rkcru0: 661 clk_pmu1_300m_src <- clk_300m_src comp 300000000 Hz
[ 1.000000] rkcru0: 662 clk_pmu1_400m_src <- clk_400m_src comp 396000000 Hz
[ 1.000000] rkcru0: 658 clk_pmu1_50m_src <- clk_pmu1_400m_src comp 49500000 Hz
[ 1.000000] rkcru0: 659 clk_pmu1_100m_src <- clk_pmu1_400m_src comp 99000000 Hz
[ 1.000000] rkcru0: 660 clk_pmu1_200m_src <- clk_pmu1_400m_src comp 198000000 Hz
[ 1.000000] rkcru0: 663 hclk_pmu1_root <- clk_pmu1_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 664 pclk_pmu1_root <- clk_pmu1_100m_src comp 99000000 Hz
[ 1.000000] rkcru0: 665 pclk_pmu0_root <- pclk_pmu1_root gate 99000000 Hz
[ 1.000000] rkcru0: 666 hclk_pmu_cm0_root <- clk_pmu1_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 641 clk_pmu0 <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 642 pclk_pmu0 <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 643 pclk_pmu0ioc <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 644 pclk_gpio0 <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 645 dbclk_gpio0 <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 646 pclk_i2c0 <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 647 clk_i2c0 <- clk_pmu1_200m_src comp 198000000 Hz
[ 1.000000] rkcru0: 648 hclk_i2s1_8ch <- hclk_pmu1_root gate 198000000 Hz
[ 1.000000] rkcru0: 649 clk_i2s1_8ch_tx_src <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 650 clk_i2s1_8ch_tx_frac <- clk_i2s1_8ch_tx_src comp 0 Hz
[ 1.000000] rkcru0: 651 clk_i2s1_8ch_tx mux rk_cru_clock_get_rate: no parent for clk_i2s1_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 652 mclk_i2s1_8ch_tx <- clk_i2s1_8ch_tx gate rk_cru_clock_get_rate: no parent for clk_i2s1_8ch_tx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 653 clk_i2s1_8ch_rx_src <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 654 clk_i2s1_8ch_rx_frac <- clk_i2s1_8ch_rx_src comp 0 Hz
[ 1.000000] rkcru0: 655 clk_i2s1_8ch_rx mux rk_cru_clock_get_rate: no parent for clk_i2s1_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 656 mclk_i2s1_8ch_rx <- clk_i2s1_8ch_rx gate rk_cru_clock_get_rate: no parent for clk_i2s1_8ch_rx
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 657 i2s1_8ch_mclkout mux rk_cru_clock_get_rate: no parent for i2s1_8ch_mclkout
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 667 pclk_pmu1 <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 668 clk_ddr_fail_safe <- clk_pmu0 gate 24000000 Hz
[ 1.000000] rkcru0: 669 clk_pmu1 <- clk_pmu0 gate 24000000 Hz
[ 1.000000] rkcru0: 670 hclk_pdm0 <- hclk_pmu1_root gate 198000000 Hz
[ 1.000000] rkcru0: 671 mclk_pdm0 <- clk_pmu1_300m_src comp 300000000 Hz
[ 1.000000] rkcru0: 672 hclk_vad <- hclk_pmu1_root gate 198000000 Hz
[ 1.000000] rkcru0: 673 fclk_pmu_cm0_core <- hclk_pmu_cm0_root gate 198000000 Hz
[ 1.000000] rkcru0: 674 clk_pmu_cm0_rtc <- xin32k comp 32768 Hz
[ 1.000000] rkcru0: 675 pclk_pmu1_ioc <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 676 pclk_pmu1pwm <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 677 clk_pmu1pwm <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 678 clk_pmu1pwm_capture <- xin24m gate 24000000 Hz
[ 1.000000] rkcru0: 679 pclk_pmu1timer <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 680 clk_pmu1timer_root <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 681 clk_pmu1timer0 <- clk_pmu1timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 682 clk_pmu1timer1 <- clk_pmu1timer_root gate 24000000 Hz
[ 1.000000] rkcru0: 683 clk_uart0_src <- cpll comp 750000000 Hz
[ 1.000000] rkcru0: 684 clk_uart0_frac <- clk_uart0_src comp 0 Hz
[ 1.000000] rkcru0: 685 clk_uart0 <- xin24m mux 24000000 Hz
[ 1.000000] rkcru0: 686 sclk_uart0 <- clk_uart0 gate 24000000 Hz
[ 1.000000] rkcru0: 687 pclk_uart0 <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 688 pclk_pmu1wdt <- pclk_pmu0_root gate 99000000 Hz
[ 1.000000] rkcru0: 689 tclk_pmu1wdt <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 690 clk_cr_para <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 693 clk_usb2phy_hdptxrxphy_ref <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 694 clk_usbdpphy_mipidcpphy_ref <- xin24m comp 24000000 Hz
[ 1.000000] rkcru0: 718 clk_phy0_ref_alt_p <- ppll gate 100000000 Hz
[ 1.000000] rkcru0: 719 clk_phy0_ref_alt_m <- ppll gate 100000000 Hz
[ 1.000000] rkcru0: 720 clk_phy1_ref_alt_p <- ppll gate 100000000 Hz
[ 1.000000] rkcru0: 721 clk_phy1_ref_alt_m <- ppll gate 100000000 Hz
[ 1.000000] rkcru0: 605 hclk_spdifrx0 gate rk_cru_clock_get_rate: no parent for hclk_spdifrx0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 607 hclk_spdifrx1 gate rk_cru_clock_get_rate: no parent for hclk_spdifrx1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 609 hclk_spdifrx2 gate rk_cru_clock_get_rate: no parent for hclk_spdifrx2
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 600 hclk_spdif4 gate rk_cru_clock_get_rate: no parent for hclk_spdif4
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 595 hclk_spdif3 gate rk_cru_clock_get_rate: no parent for hclk_spdif3
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 594 hclk_i2s6_8ch gate rk_cru_clock_get_rate: no parent for hclk_i2s6_8ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 584 hclk_i2s5_8ch gate rk_cru_clock_get_rate: no parent for hclk_i2s5_8ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 574 hclk_i2s9_8ch gate rk_cru_clock_get_rate: no parent for hclk_i2s9_8ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 568 hclk_i2s7_8ch gate rk_cru_clock_get_rate: no parent for hclk_i2s7_8ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 563 hclk_i2s10_8ch gate rk_cru_clock_get_rate: no parent for hclk_i2s10_8ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 535 aclk_hdcp1 gate rk_cru_clock_get_rate: no parent for aclk_hdcp1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 536 hclk_hdcp1 gate rk_cru_clock_get_rate: no parent for hclk_hdcp1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 522 hclk_spdif5_dp1 gate rk_cru_clock_get_rate: no parent for hclk_spdif5_dp1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 516 hclk_spdif2_dp0 gate rk_cru_clock_get_rate: no parent for hclk_spdif2_dp0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 510 hclk_i2s8_8ch gate rk_cru_clock_get_rate: no parent for hclk_i2s8_8ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 496 hclk_i2s4_8ch gate rk_cru_clock_get_rate: no parent for hclk_i2s4_8ch
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 493 aclk_hdcp0 gate rk_cru_clock_get_rate: no parent for aclk_hdcp0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 494 hclk_hdcp0 gate rk_cru_clock_get_rate: no parent for hclk_hdcp0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 457 hclk_rkvenc1 gate rk_cru_clock_get_rate: no parent for hclk_rkvenc1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 458 aclk_rkvenc1 gate rk_cru_clock_get_rate: no parent for aclk_rkvenc1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 448 aclk_vpu gate rk_cru_clock_get_rate: no parent for aclk_vpu
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 426 aclk_iep2p0 gate rk_cru_clock_get_rate: no parent for aclk_iep2p0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 428 aclk_jpeg_encoder0 gate rk_cru_clock_get_rate: no parent for aclk_jpeg_encoder0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 430 aclk_jpeg_encoder1 gate rk_cru_clock_get_rate: no parent for aclk_jpeg_encoder1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 432 aclk_jpeg_encoder2 gate rk_cru_clock_get_rate: no parent for aclk_jpeg_encoder2
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 434 aclk_jpeg_encoder3 gate rk_cru_clock_get_rate: no parent for aclk_jpeg_encoder3
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 436 aclk_jpeg_decoder gate rk_cru_clock_get_rate: no parent for aclk_jpeg_decoder
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 420 aclk_usb3otg1 gate rk_cru_clock_get_rate: no parent for aclk_usb3otg1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 413 hclk_host0 gate rk_cru_clock_get_rate: no parent for hclk_host0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 414 hclk_host_arb0 gate rk_cru_clock_get_rate: no parent for hclk_host_arb0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 415 hclk_host1 gate rk_cru_clock_get_rate: no parent for hclk_host1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 416 hclk_host_arb1 gate rk_cru_clock_get_rate: no parent for hclk_host_arb1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 417 aclk_usb3otg0 gate rk_cru_clock_get_rate: no parent for aclk_usb3otg0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 409 hclk_sdio gate rk_cru_clock_get_rate: no parent for hclk_sdio
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 404 hclk_rkvdec1 gate rk_cru_clock_get_rate: no parent for hclk_rkvdec1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 405 aclk_rkvdec1 gate rk_cru_clock_get_rate: no parent for aclk_rkvdec1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 399 hclk_rkvdec0 gate rk_cru_clock_get_rate: no parent for hclk_rkvdec0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 400 aclk_rkvdec0 gate rk_cru_clock_get_rate: no parent for aclk_rkvdec0
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 387 clk_pcie4l_pipe gate rk_cru_clock_get_rate: no parent for clk_pcie4l_pipe
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 388 clk_pcie2l_pipe gate rk_cru_clock_get_rate: no parent for clk_pcie2l_pipe
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 379 clk_pipephy0_pipe_g gate rk_cru_clock_get_rate: no parent for clk_pipephy0_pipe_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 380 clk_pipephy1_pipe_g gate rk_cru_clock_get_rate: no parent for clk_pipephy1_pipe_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 381 clk_pipephy2_pipe_g gate rk_cru_clock_get_rate: no parent for clk_pipephy2_pipe_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 382 clk_pipephy0_pipe_asic_g gate rk_cru_clock_get_rate: no parent for clk_pipephy0_pipe_asic_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 383 clk_pipephy1_pipe_asic_g gate rk_cru_clock_get_rate: no parent for clk_pipephy1_pipe_asic_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 384 clk_pipephy2_pipe_asic_g gate rk_cru_clock_get_rate: no parent for clk_pipephy2_pipe_asic_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 385 clk_pipephy2_pipe_u3_g gate rk_cru_clock_get_rate: no parent for clk_pipephy2_pipe_u3_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 386 clk_pcie1l2_pipe <- clk_pipephy0_pipe_g gate rk_cru_clock_get_rate: no parent for clk_pipephy0_pipe_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 708 clk_pcie1l0_pipe <- clk_pipephy1_pipe_g gate rk_cru_clock_get_rate: no parent for clk_pipephy1_pipe_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 709 clk_pcie1l1_pipe <- clk_pipephy2_pipe_g gate rk_cru_clock_get_rate: no parent for clk_pipephy2_pipe_g
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 318 hclk_sfc gate rk_cru_clock_get_rate: no parent for hclk_sfc
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 319 hclk_sfc_xip gate rk_cru_clock_get_rate: no parent for hclk_sfc_xip
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 312 hclk_emmc gate rk_cru_clock_get_rate: no parent for hclk_emmc
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 288 aclk_isp1 gate rk_cru_clock_get_rate: no parent for aclk_isp1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 289 hclk_isp1 gate rk_cru_clock_get_rate: no parent for hclk_isp1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 75 pclk_av1 gate rk_cru_clock_get_rate: no parent for pclk_av1
[ 1.000000] 0 Hz
[ 1.000000] rkcru0: 73 aclk_av1 gate rk_cru_clock_get_rate: no parent for aclk_av1
[ 1.000000] 0 Hz
[ 1.000000] simplebus0: set default config for timer
[ 1.000000] gtmr0 at simplebus0 (/timer): Generic Timer
[ 1.000000] gtmr0: interrupting on GICv3 irq 27
[ 1.000000] armgtmr0 at gtmr0: Generic Timer (24000 kHz, virtual)
[ 1.000000] timecounter: Timecounter "armgtmr0" frequency 24000000 Hz quality 500
[ 1.000003] simplebus0: set default config for pinctrl
[ 1.000003] rkiomux0 at simplebus0 (/pinctrl): RK3588 IOMUX control
[ 1.000003] rkgpio0 at rkiomux0: GPIO (gpio@fd8a0000)
[ 1.000003] gpio0 at rkgpio0: 32 pins
[ 1.000003] rkgpio1 at rkiomux0: GPIO (gpio@fec20000)
[ 1.000003] gpio1 at rkgpio1: 32 pins
[ 1.000003] rkgpio2 at rkiomux0: GPIO (gpio@fec30000)
[ 1.000003] gpio2 at rkgpio2: 32 pins
[ 1.000003] rkgpio3 at rkiomux0: GPIO (gpio@fec40000)
[ 1.000003] gpio3 at rkgpio3: 32 pins
[ 1.000003] rkgpio4 at rkiomux0: GPIO (gpio@fec50000)
[ 1.000003] gpio4 at rkgpio4: 32 pins
[ 1.000003] simplebus0: set default config for i2c@fd880000
[ 1.000003] rkiic0 at simplebus0 (/i2c@fd880000): Rockchip I2C (100000 Hz)
[ 1.000003] iic0 at rkiic0: I2C bus
[ 1.000003] rk8602 (rockchip,rk8602) at iic0 addr 0x42 not configured
[ 1.000003] rk8603 (rockchip,rk8603) at iic0 addr 0x43 not configured
[ 1.000003] simplebus0: set default config for i2c@feac0000
[ 1.000003] rkiic1 at simplebus0 (/i2c@feac0000): Rockchip I2C (100000 Hz)
[ 1.000003] iic1 at rkiic1: I2C bus
[ 1.000003] fusb302 (fcs,fusb302) at iic1 addr 0x22 not configured
[ 1.000003] hym8563 (haoyu,hym8563) at iic1 addr 0x51 not configured
[ 1.000003] simplebus0: set default config for vcc5v0-sys
[ 1.000003] fregulator0 at simplebus0 (/vcc5v0-sys): vcc5v0_sys
[ 1.000003] simplebus0: set default config for i2c@fea90000
[ 1.000003] rkiic2 at simplebus0 (/i2c@fea90000): Rockchip I2C (100000 Hz)
[ 1.000003] iic2 at rkiic2: I2C bus
[ 1.000003] rk8602 (rockchip,rk8602) at iic2 addr 0x42 not configured
[ 1.000003] simplebus0: set default config for vcc3v3-lcd0-n
[ 1.000003] fregulator1 at simplebus0 (/vcc3v3-lcd0-n): vcc3v3_lcd0_n
[ 1.000003] simplebus0: set default config for vcc3v3-pcie30
[ 1.000003] fregulator2 at simplebus0 (/vcc3v3-pcie30): vcc3v3_pcie30
[ 1.000003] simplebus0: set default config for vbus5v0-typec
[ 1.000003] fregulator3 at simplebus0 (/vbus5v0-typec): vbus5v0_typec
[ 1.000003] simplebus0: set default config for vcc-1v1-nldo-s3
[ 1.000003] fregulator4 at simplebus0 (/vcc-1v1-nldo-s3): vcc_1v1_nldo_s3
[ 1.000003] simplebus0: set default config for vcc12v-dcin
[ 1.000003] fregulator5 at simplebus0 (/vcc12v-dcin): vcc12v_dcin
[ 1.000003] simplebus0: set default config for vcc5v0-usbdcin
[ 1.000003] fregulator6 at simplebus0 (/vcc5v0-usbdcin): vcc5v0_usbdcin
[ 1.000003] simplebus0: set default config for vcc5v0-usb
[ 1.000003] fregulator7 at simplebus0 (/vcc5v0-usb): vcc5v0_usb
[ 1.000003] simplebus0: set default config for i2c@fec90000
[ 1.000003] rkiic3 at simplebus0 (/i2c@fec90000): Rockchip I2C (100000 Hz)
[ 1.000003] iic3 at rkiic3: I2C bus
[ 1.000003] rt5640 (realtek,rt5640) at iic3 addr 0x1c not configured
[ 1.000003] simplebus0: set default config for serial@fd890000
[ 1.000003] com0 at simplebus0 (/serial@fd890000): DesignWare APB UART, 64-byte FIFO
[ 1.000003] com0: interrupting on GICv3 irq 363
[ 1.000003] simplebus0: set default config for serial@feb50000
[ 1.000003] com1 at simplebus0 (/serial@feb50000): DesignWare APB UART, 64-byte FIFO
[ 1.000003] com1: console
[ 1.000003] com1: interrupting on GICv3 irq 365
[ 1.000003] simplebus0: set default config for serial@feb90000
[ 1.000003] com2 at simplebus0 (/serial@feb90000): DesignWare APB UART, 64-byte FIFO
[ 1.000003] com2: interrupting on GICv3 irq 369
[ 1.000003] simplebus0: set default config for serial@feba0000
[ 1.000003] com3 at simplebus0 (/serial@feba0000): DesignWare APB UART, 64-byte FIFO
[ 1.000003] com3: interrupting on GICv3 irq 370
[ 1.000003] simplebus0: set default config for serial@febb0000
[ 1.000003] com4 at simplebus0 (/serial@febb0000): DesignWare APB UART, 64-byte FIFO
[ 1.000003] com4: interrupting on GICv3 irq 371
[ 1.000003] simplebus0: set default config for serial@febc0000
[ 1.000003] com5 at simplebus0 (/serial@febc0000): DesignWare APB UART, 64-byte FIFO
[ 1.000003] com5: interrupting on GICv3 irq 372
[ 1.000003] simplebus0: set default config for i2c@fec80000
[ 1.000003] rkiic4 at simplebus0 (/i2c@fec80000): Rockchip I2C (100000 Hz)
[ 1.000003] iic4 at rkiic4: I2C bus
[ 1.000003] goodix_ts (goodix,gt9xx) at iic4 addr 0x5d not configured
[ 1.000003] simplebus0: set default config for pcie20-avdd0v85
[ 1.000003] fregulator8 at simplebus0 (/pcie20-avdd0v85): pcie20_avdd0v85
[ 1.000003] simplebus0: set default config for pcie20-avdd1v8
[ 1.000003] fregulator9 at simplebus0 (/pcie20-avdd1v8): pcie20_avdd1v8
[ 1.000003] simplebus0: set default config for pcie30-avdd1v8
[ 1.000003] fregulator10 at simplebus0 (/pcie30-avdd1v8): pcie30_avdd1v8
[ 1.000003] simplebus0: set default config for pcie30-avdd0v75
[ 1.000003] fregulator11 at simplebus0 (/pcie30-avdd0v75): pcie30_avdd0v75
[ 1.000003] simplebus0: set default config for display-subsystem
[ 1.000003] rkdrm0 at simplebus0 (/display-subsystem)
[ 1.000003] syscon5: set default config for usb2-phy@0
[ 1.000003] rkusb0 at syscon5 (/syscon@fd5d0000/usb2-phy@0): USB2 PHY
[ 1.000003] rkusbphy0 at rkusb0: USB2 OTG port
[ 1.000003] syscon6: set default config for usb2-phy@8000
[ 1.000003] rkusb1 at syscon6 (/syscon@fd5d8000/usb2-phy@8000): USB2 PHY
[ 1.000003] rkusbphy1 at rkusb1: USB2 host port
[ 1.000003] syscon7: set default config for usb2-phy@c000
[ 1.000003] rkusb2 at syscon7 (/syscon@fd5dc000/usb2-phy@c000): USB2 PHY
[ 1.000003] rkusbphy2 at rkusb2: USB2 host port
[ 1.000003] syscon71: set default config for usb2-phy@4000
[ 1.000003] rkusb3 at syscon71 (/syscon@fd5d4000/usb2-phy@4000): USB2 PHY
[ 1.000003] simplebus1: set default config for hclk_nvm@fd7c087c
[ 1.000003] /clocks/hclk_nvm@fd7c087c at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for hclk_vo0@fd7c08dc
[ 1.000003] /clocks/hclk_vo0@fd7c08dc at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for hclk_vo1@fd7c08ec
[ 1.000003] /clocks/hclk_vo1@fd7c08ec at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus0: set default config for firmware
[ 1.000003] simplebus0: set default config for cluster0-opp-table
[ 1.000003] /cluster0-opp-table at simplebus0 <operating-points-v2> not configured
[ 1.000003] simplebus0: set default config for spi@feb20000
[ 1.000003] rkspi0 at simplebus0 (/spi@feb20000): SPI
[ 1.000003] rkspi0: interrupting on GICv3 irq 360
[ 1.000003] spi0 at rkspi0: SPI bus
[ 1.000003] slave 0 not configured
[ 1.000003] simplebus0: set default config for cluster1-opp-table
[ 1.000003] /cluster1-opp-table at simplebus0 <operating-points-v2> not configured
[ 1.000003] simplebus0: set default config for cluster2-opp-table
[ 1.000003] /cluster2-opp-table at simplebus0 <operating-points-v2> not configured
[ 1.000003] simplebus0: set default config for otp@fecc0000
[ 1.000003] /otp@fecc0000 at simplebus0 <rockchip,rk3588-otp> not configured
[ 1.000003] simplebus0: set default config for vop@fdd90000
[ 1.000003] /vop@fdd90000 at simplebus0 <rockchip,rk3588-vop> not configured
[ 1.000003] simplebus0: set default config for reserved-memory
[ 1.000003] simplebus0: set default config for dfi@fe060000
[ 1.000003] /dfi@fe060000 at simplebus0 <rockchip,rk3588-dfi> not configured
[ 1.000003] simplebus0: set default config for dmc-opp-table
[ 1.000003] /dmc-opp-table at simplebus0 <operating-points-v2> not configured
[ 1.000003] simplebus0: set default config for sram@10f000
[ 1.000003] /sram@10f000 at simplebus0 <mmio-sram> not configured
[ 1.000003] simplebus0: set default config for tsadc@fec00000
[ 1.000003] /tsadc@fec00000 at simplebus0 <rockchip,rk3588-tsadc> not configured
[ 1.000003] simplebus0: set default config for thermal-zones
[ 1.000003] simplebus0: set default config for gpu@fb000000
[ 1.000003] /gpu@fb000000 at simplebus0 <arm,mali-bifrost> not configured
[ 1.000003] syscon3: set default config for power-controller
[ 1.000003] /power-management@fd8d8000/power-controller at syscon3 <rockchip,rk3588-power-controller> not configured
[ 1.000003] simplebus0: set default config for gpu-opp-table
[ 1.000003] /gpu-opp-table at simplebus0 <operating-points-v2> not configured
[ 1.000003] simplebus0: set default config for phy@fed80000
[ 1.000003] /phy@fed80000 at simplebus0 <rockchip,rk3588-usbdp-phy> not configured
[ 1.000003] simplebus0: set default config for phy@fee20000
[ 1.000003] /phy@fee20000 at simplebus0 <rockchip,rk3588-naneng-combphy> not configured
[ 1.000003] simplebus1: set default config for pclk_vo0_grf@fd7c08dc
[ 1.000003] /clocks/pclk_vo0_grf@fd7c08dc at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for pclk_vo1_grf@fd7c08ec
[ 1.000003] /clocks/pclk_vo1_grf@fd7c08ec at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus0: set default config for dma-controller@fea10000
[ 1.000003] /dma-controller@fea10000 at simplebus0 <arm,pl330> <arm,primecell> not configured
[ 1.000003] simplebus0: set default config for npu-opp-table
[ 1.000003] /npu-opp-table at simplebus0 <operating-points-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdab9000
[ 1.000003] /iommu@fdab9000 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdb50800
[ 1.000003] /iommu@fdb50800 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for mpp-srv
[ 1.000003] /mpp-srv at simplebus0 <rockchip,mpp-service> not configured
[ 1.000003] simplebus0: set default config for iommu@fdb60f00
[ 1.000003] /iommu@fdb60f00 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdb70f00
[ 1.000003] /iommu@fdb70f00 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdb90480
[ 1.000003] /iommu@fdb90480 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdba0800
[ 1.000003] /iommu@fdba0800 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for jpege-ccu
[ 1.000003] /jpege-ccu at simplebus0 <rockchip,vpu-encoder-v2-ccu> not configured
[ 1.000003] simplebus0: set default config for iommu@fdba4800
[ 1.000003] /iommu@fdba4800 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdba8800
[ 1.000003] /iommu@fdba8800 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdbac800
[ 1.000003] /iommu@fdbac800 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdbb0800
[ 1.000003] /iommu@fdbb0800 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdbdf000
[ 1.000003] /iommu@fdbdf000 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for rkvenc-ccu
[ 1.000003] /rkvenc-ccu at simplebus0 <rockchip,rkv-encoder-v2-ccu> not configured
[ 1.000003] simplebus0: set default config for iommu@fdbef000
[ 1.000003] /iommu@fdbef000 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdc38700
[ 1.000003] /iommu@fdc38700 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for rkvdec-ccu@fdc30000
[ 1.000003] /rkvdec-ccu@fdc30000 at simplebus0 <rockchip,rkv-decoder-v2-ccu> not configured
[ 1.000003] simplebus0: set default config for sram@fd600000
[ 1.000003] /sram@fd600000 at simplebus0 <mmio-sram> not configured
[ 1.000003] simplebus0: set default config for iommu@fdc48700
[ 1.000003] /iommu@fdc48700 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for iommu@fdca0000
[ 1.000003] /iommu@fdca0000 at simplebus0 <rockchip,iommu-av1> not configured
[ 1.000003] simplebus0: set default config for hdmiphy@fed60000
[ 1.000003] /hdmiphy@fed60000 at simplebus0 <rockchip,rk3588-hdptx-phy-hdmi> not configured
[ 1.000003] simplebus0: set default config for hdmiphy@fed70000
[ 1.000003] /hdmiphy@fed70000 at simplebus0 <rockchip,rk3588-hdptx-phy-hdmi> not configured
[ 1.000003] simplebus0: set default config for iommu@fdd97e00
[ 1.000003] /iommu@fdd97e00 at simplebus0 <rockchip,iommu-v2> not configured
[ 1.000003] simplebus0: set default config for dp@fde50000
[ 1.000003] /dp@fde50000 at simplebus0 <rockchip,rk3588-dp> not configured
[ 1.000003] simplebus0: set default config for hdmi@fde80000
[ 1.000003] /hdmi@fde80000 at simplebus0 <rockchip,rk3588-dw-hdmi> not configured
[ 1.000003] simplebus0: set default config for hdmi@fdea0000
[ 1.000003] /hdmi@fdea0000 at simplebus0 <rockchip,rk3588-dw-hdmi> not configured
[ 1.000003] simplebus0: set default config for dsi@fde20000
[ 1.000003] /dsi@fde20000 at simplebus0 <rockchip,rk3588-mipi-dsi2> not configured
[ 1.000003] simplebus0: set default config for dma-controller@fea30000
[ 1.000003] /dma-controller@fea30000 at simplebus0 <arm,pl330> <arm,primecell> not configured
[ 1.000003] simplebus0: set default config for dma-controller@fed10000
[ 1.000003] /dma-controller@fed10000 at simplebus0 <arm,pl330> <arm,primecell> not configured
[ 1.000003] simplebus0: set default config for phy@feda0000
[ 1.000003] /phy@feda0000 at simplebus0 <rockchip,rk3588-mipi-dcphy> not configured
[ 1.000003] simplebus0: set default config for backlight
[ 1.000003] pwmbacklight0 at simplebus0 (/backlight)autoconfiguration error: : couldn't acquire pwm
[ 1.000003] simplebus0: set default config for pcie@fe180000
[ 1.000003] /pcie@fe180000 at simplebus0 <rockchip,rk3588-pcie> <snps,dw-pcie> not configured
[ 1.000003] simplebus0: set default config for pcie@fe190000
[ 1.000003] /pcie@fe190000 at simplebus0 <rockchip,rk3588-pcie> <snps,dw-pcie> not configured
[ 1.000003] simplebus0: set default config for phy@fee00000
[ 1.000003] /phy@fee00000 at simplebus0 <rockchip,rk3588-naneng-combphy> not configured
[ 1.000003] simplebus0: set default config for ethernet@fe1c0000
[ 1.000003] eqos0 at simplebus0 (/ethernet@fe1c0000): DesignWare EQOS ver 0x51 (0x30)
[ 1.000003] eqos0: hw features 1a1173f7 111e01e8 11041041 0c370031
[ 1.000003] eqos0: using 32-bit DMA
[ 1.000003] eqos0: Ethernet address 10:8b:b2:1e:ed:d6
[ 1.000003] eqos0: TX ring @ 0x3A6000, RX ring @ 0x4AE000
[ 1.000003] rgephy0 at eqos0 phy 0: RTL8211F 1000BASE-T media interface
[ 1.000003] rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, auto
[ 1.000003] rgephy1 at eqos0 phy 1: RTL8211F 1000BASE-T media interface
[ 1.000003] rgephy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, auto
[ 1.000003] eqos0: interrupting on GICv3 irq 266
[ 1.000003] simplebus0: set default config for usbdrd3_0
[ 1.000003] xhci0 at simplebus0 (/usbdrd3_0)autoconfiguration error: : host is not default mode
[ 1.000003] simplebus0: set default config for saradc@fec10000
[ 1.000003] /saradc@fec10000 at simplebus0 <rockchip,rk3588-saradc> not configured
[ 1.000003] simplebus0: set default config for phy@fed90000
[ 1.000003] /phy@fed90000 at simplebus0 <rockchip,rk3588-usbdp-phy> not configured
[ 1.000003] simplebus0: set default config for pcie@fe150000
[ 1.000003] /pcie@fe150000 at simplebus0 <rockchip,rk3588-pcie> <snps,dw-pcie> not configured
[ 1.000003] simplebus0: set default config for phy@fee80000
[ 1.000003] /phy@fee80000 at simplebus0 <rockchip,rk3588-pcie3-phy> not configured
[ 1.000003] simplebus0: set default config for pcie@fe170000
[ 1.000003] /pcie@fe170000 at simplebus0 <rockchip,rk3588-pcie> <snps,dw-pcie> not configured
[ 1.000003] simplebus0: set default config for phy@fee10000
[ 1.000003] /phy@fee10000 at simplebus0 <rockchip,rk3588-naneng-combphy> not configured
[ 1.000003] simplebus0: set default config for i2s@fddf0000
[ 1.000003] /i2s@fddf0000 at simplebus0 <rockchip,rk3588-i2s-tdm> not configured
[ 1.000003] simplebus0: set default config for i2s@fddf4000
[ 1.000003] /i2s@fddf4000 at simplebus0 <rockchip,rk3588-i2s-tdm> not configured
[ 1.000003] simplebus0: set default config for i2s@fe470000
[ 1.000003] /i2s@fe470000 at simplebus0 <rockchip,rk3588-i2s-tdm> not configured
[ 1.000003] simplebus0: set default config for pwm@fd8b0010
[ 1.000003] /pwm@fd8b0010 at simplebus0 <rockchip,rk3588-pwm> <rockchip,rk3328-pwm> not configured
[ 1.000003] simplebus1: set default config for aclk_vdpu_low_pre@fd7c08b0
[ 1.000003] /clocks/aclk_vdpu_low_pre@fd7c08b0 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for hclk_usb@fd7c08a8
[ 1.000003] /clocks/hclk_usb@fd7c08a8 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for aclk_usb@fd7c08a8
[ 1.000003] /clocks/aclk_usb@fd7c08a8 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for hclk_isp1_pre@fd7c0868
[ 1.000003] /clocks/hclk_isp1_pre@fd7c0868 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for aclk_isp1_pre@fd7c0868
[ 1.000003] /clocks/aclk_isp1_pre@fd7c0868 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for aclk_rkvdec0_pre@fd7c08a0
[ 1.000003] /clocks/aclk_rkvdec0_pre@fd7c08a0 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for hclk_rkvdec0_pre@fd7c08a0
[ 1.000003] /clocks/hclk_rkvdec0_pre@fd7c08a0 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for aclk_rkvdec1_pre@fd7c08a4
[ 1.000003] /clocks/aclk_rkvdec1_pre@fd7c08a4 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for hclk_rkvdec1_pre@fd7c08a4
[ 1.000003] /clocks/hclk_rkvdec1_pre@fd7c08a4 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for aclk_jpeg_decoder_pre@fd7c08b0
[ 1.000003] /clocks/aclk_jpeg_decoder_pre@fd7c08b0 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for aclk_rkvenc1_pre@fd7c08c0
[ 1.000003] /clocks/aclk_rkvenc1_pre@fd7c08c0 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for hclk_rkvenc1_pre@fd7c08c0
[ 1.000003] /clocks/hclk_rkvenc1_pre@fd7c08c0 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for aclk_hdcp0_pre@fd7c08dc
[ 1.000003] /clocks/aclk_hdcp0_pre@fd7c08dc at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for aclk_hdcp1_pre@fd7c08ec
[ 1.000003] /clocks/aclk_hdcp1_pre@fd7c08ec at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for pclk_av1_pre@fd7c0910
[ 1.000003] /clocks/pclk_av1_pre@fd7c0910 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for aclk_av1_pre@fd7c0910
[ 1.000003] /clocks/aclk_av1_pre@fd7c0910 at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus1: set default config for hclk_sdio_pre@fd7c092c
[ 1.000003] /clocks/hclk_sdio_pre@fd7c092c at simplebus1 <rockchip,rk3588-clock-gate-link> not configured
[ 1.000003] simplebus0: set default config for arm-pmu
[ 1.000003] armpmu0 at simplebus0 (/arm-pmu): Performance Monitor Unit
[ 1.000003] simplebus0: set default config for dmc
[ 1.000003] /dmc at simplebus0 <rockchip,rk3588-dmc> not configured
[ 1.000003] simplebus0: set default config for rockchip-suspend
[ 1.000003] /rockchip-suspend at simplebus0 <rockchip,pm-rk3588> not configured
[ 1.000003] simplebus0: set default config for rockchip-system-monitor
[ 1.000003] /rockchip-system-monitor at simplebus0 <rockchip,system-monitor> not configured
[ 1.000003] simplebus0: set default config for usb@fc800000
[ 1.000003] ehci0 at simplebus0 (/usb@fc800000): EHCI
[ 1.000003] ehci0: interrupting on GICv3 irq 247
[ 1.000003] ehci0: EHCI version 1.0
[ 1.000003] ehci0: 1 companion controller, 1 port
[ 1.000003] ehci0: Using DMA subregion for control data structures
[ 1.000003] usb0 at ehci0: USB revision 2.0
[ 1.000003] simplebus0: set default config for usb@fc840000
[ 1.000003] /usb@fc840000 at simplebus0 <generic-ohci> not configured
[ 1.000003] simplebus0: set default config for usb@fc880000
[ 1.000003] ehci1 at simplebus0 (/usb@fc880000): EHCI
[ 1.000003] ehci1: interrupting on GICv3 irq 250
[ 1.000003] ehci1: EHCI version 1.0
[ 1.000003] ehci1: 1 companion controller, 1 port
[ 1.000003] ehci1: Using DMA subregion for control data structures
[ 1.000003] usb1 at ehci1: USB revision 2.0
[ 1.000003] simplebus0: set default config for usb@fc8c0000
[ 1.000003] /usb@fc8c0000 at simplebus0 <generic-ohci> not configured
[ 1.000003] syscon77: set default config for reboot-mode
[ 1.000003] /syscon@fd588000/reboot-mode at syscon77 <syscon-reboot-mode> not configured
[ 1.000003] simplebus0: set default config for npu@fdab0000
[ 1.000003] /npu@fdab0000 at simplebus0 <rockchip,rk3588-rknpu> not configured
[ 1.000003] simplebus0: set default config for vdpu@fdb50400
[ 1.000003] /vdpu@fdb50400 at simplebus0 <rockchip,vpu-decoder-v2> not configured
[ 1.000003] simplebus0: set default config for rga@fdb60000
[ 1.000003] /rga@fdb60000 at simplebus0 <rockchip,rga3_core0> not configured
[ 1.000003] simplebus0: set default config for rga@fdb70000
[ 1.000003] /rga@fdb70000 at simplebus0 <rockchip,rga3_core1> not configured
[ 1.000003] simplebus0: set default config for rga@fdb80000
[ 1.000003] /rga@fdb80000 at simplebus0 <rockchip,rga2_core0> not configured
[ 1.000003] simplebus0: set default config for jpegd@fdb90000
[ 1.000003] /jpegd@fdb90000 at simplebus0 <rockchip,rkv-jpeg-decoder-v1> not configured
[ 1.000003] simplebus0: set default config for jpege-core@fdba0000
[ 1.000003] /jpege-core@fdba0000 at simplebus0 <rockchip,vpu-encoder-v2-core> not configured
[ 1.000003] simplebus0: set default config for jpege-core@fdba4000
[ 1.000003] /jpege-core@fdba4000 at simplebus0 <rockchip,vpu-encoder-v2-core> not configured
[ 1.000003] simplebus0: set default config for jpege-core@fdba8000
[ 1.000003] /jpege-core@fdba8000 at simplebus0 <rockchip,vpu-encoder-v2-core> not configured
[ 1.000003] simplebus0: set default config for jpege-core@fdbac000
[ 1.000003] /jpege-core@fdbac000 at simplebus0 <rockchip,vpu-encoder-v2-core> not configured
[ 1.000003] simplebus0: set default config for iep@fdbb0000
[ 1.000003] /iep@fdbb0000 at simplebus0 <rockchip,iep-v2> not configured
[ 1.000003] simplebus0: set default config for rkvenc-core@fdbd0000
[ 1.000003] /rkvenc-core@fdbd0000 at simplebus0 <rockchip,rkv-encoder-v2-core> not configured
[ 1.000003] simplebus0: set default config for rkvenc-core@fdbe0000
[ 1.000003] /rkvenc-core@fdbe0000 at simplebus0 <rockchip,rkv-encoder-v2-core> not configured
[ 1.000003] simplebus0: set default config for rkvdec-core@fdc38000
[ 1.000003] /rkvdec-core@fdc38000 at simplebus0 <rockchip,rkv-decoder-v2> not configured
[ 1.000003] simplebus0: set default config for rkvdec-core@fdc48000
[ 1.000003] /rkvdec-core@fdc48000 at simplebus0 <rockchip,rkv-decoder-v2> not configured
[ 1.000003] simplebus0: set default config for mmc@fe2c0000
[ 1.000003] dwcmmc0 at simplebus0 (/mmc@fe2c0000)autoconfiguration error: : couldn't get clock biu
[ 1.000003] simplebus0: set default config for mmc@fe2e0000
[ 1.000003] /mmc@fe2e0000 at simplebus0 <rockchip,rk3588-dwcmshc> <rockchip,dwcmshc-sdhci> not configured
[ 1.000003] simplebus0: set default config for rng@fe378000
[ 1.000003] /rng@fe378000 at simplebus0 <rockchip,trngv1> not configured
[ 1.000003] simplebus0: set default config for hwspinlock@fe5a0000
[ 1.000003] /hwspinlock@fe5a0000 at simplebus0 <rockchip,hwspinlock> not configured
[ 1.000003] simplebus0: set default config for can@fea50000
[ 1.000003] /can@fea50000 at simplebus0 <rockchip,can-2.0> not configured
[ 1.000003] simplebus0: set default config for can@fea60000
[ 1.000003] /can@fea60000 at simplebus0 <rockchip,can-2.0> not configured
[ 1.000003] simplebus0: set default config for timer@feae0000
[ 1.000003] /timer@feae0000 at simplebus0 <rockchip,rk3588-timer> <rockchip,rk3288-timer> not configured
[ 1.000003] simplebus0: set default config for usbdrd3_1
[ 1.000003] xhci1 at simplebus0 (/usbdrd3_1): DesignWare USB3 XHCI (rev. 3.00a)
[ 1.000003] xhci1: interrupting on GICv3 irq 253
[ 1.000003] xhci1: xHCI version 1.10
[ 1.000003] xhci1: hcs1=2000140 hcs2=c0000f1 hcs3=7ff000a
[ 1.000003] xhci1: hcc=0x220fe64<XECP=0x220,MAXPSA=0xf,CFC,SEC,SPC,LTC,LHRC,CSZ>
[ 1.000003] xhci1: xECP 880
[ 1.000003] xhci1: hcc2=0x2f<CIC,CTC,FSC,CMC,U3C>
[ 1.000003] xhci1: ECR: 0x00000401
[ 1.000003] xhci1: ECR: 0x02000402
[ 1.000003] xhci1: SP: 0x02000402 0x20425355 0x00180101 0x00000000
[ 1.000003] xhci1: hs ports 1 - 1
[ 1.000003] xhci1: ECR: 0x03000002
[ 1.000003] xhci1: SP: 0x03000002 0x20425355 0x00000102 0x00000000
[ 1.000003] xhci1: ss ports 2 - 2
[ 1.000003] xhci1: PAGESIZE 0x00000001
[ 1.000003] xhci1: sc_pgsz 0x00001000
[ 1.000003] xhci1: sc_maxslots 0x00000040
[ 1.000003] xhci1: sc_maxports 2
[ 1.000003] xhci1: sc_maxspbuf 1
[ 1.000003] xhci1: eventst: 0x0000000000206f80 0xffffc0044db66f80 2000
[ 1.000003] xhci1: dcbaa: 0x0000000000207000 0xffffc0044db67000 2000
[ 1.000003] xhci1: current IMOD 0
[ 1.000003] xhci1: USBCMD 0x00000005
[ 1.000003] usb2 at xhci1: USB revision 3.0
[ 1.000003] usb3 at xhci1: USB revision 2.0
[ 1.000003] simplebus0: set default config for hdmirx-controller@fdee0000
[ 1.000003] /hdmirx-controller@fdee0000 at simplebus0 <rk3588,hdmirx-ctrler> <rockchip,hdmirx-ctrler> not configured
[ 1.000003] simplebus0: set default config for adc-keys
[ 1.000003] /adc-keys at simplebus0 <adc-keys> not configured
[ 1.000003] simplebus0: set default config for hdmi0-sound
[ 1.000003] /hdmi0-sound at simplebus0 <rockchip,hdmi> not configured
[ 1.000003] simplebus0: set default config for hdmi1-sound
[ 1.000003] /hdmi1-sound at simplebus0 <rockchip,hdmi> not configured
[ 1.000003] simplebus0: set default config for leds
[ 1.000003] gpioleds0 at simplebus0 (/leds): work
[ 1.000003] simplebus0: set default config for cspmu@fd10c000
[ 1.000003] /cspmu@fd10c000 at simplebus0 <rockchip,cspmu> not configured
[ 1.000003] simplebus0: set default config for debug@fd104000
[ 1.000003] /debug@fd104000 at simplebus0 <rockchip,debug> not configured
[ 1.000003] simplebus0: set default config for fiq-debugger
[ 1.000003] /fiq-debugger at simplebus0 <rockchip,fiq-debugger> not configured
[ 1.000003] simplebus0: set default config for ramoops@110000
[ 1.000003] /ramoops@110000 at simplebus0 <ramoops> not configured
[ 1.000003] simplebus0: set default config for rpdzkj_config
[ 1.000003] /rpdzkj_config at simplebus0 <rp_config> not configured
[ 1.000003] simplebus0: set default config for rk-headset
[ 1.000003] /rk-headset at simplebus0 <rockchip_headset> not configured
[ 1.000003] simplebus0: set default config for wireless-bluetooth
[ 1.000003] /wireless-bluetooth at simplebus0 <bluetooth-platdata> not configured
[ 1.000003] simplebus0: set default config for wireless-wlan
[ 1.000003] /wireless-wlan at simplebus0 <wlan-platdata> not configured
[ 1.000003] simplebus0: set default config for memory
[ 1.000003] simplebus0: set default config for aliases
[ 1.000003] simplebus0: set default config for cpuinfo
[ 1.000003] /cpuinfo at simplebus0 <rockchip,cpuinfo> not configured
[ 1.000003] simplebus0: set default config for pvtm@fda40000
[ 1.000003] /pvtm@fda40000 at simplebus0 <rockchip,rk3588-bigcore0-pvtm> not configured
[ 1.000003] simplebus0: set default config for pvtm@fda50000
[ 1.000003] /pvtm@fda50000 at simplebus0 <rockchip,rk3588-bigcore1-pvtm> not configured
[ 1.000003] simplebus0: set default config for pvtm@fda60000
[ 1.000003] /pvtm@fda60000 at simplebus0 <rockchip,rk3588-litcore-pvtm> not configured
[ 1.000003] simplebus0: set default config for pvtm@fdaf0000
[ 1.000003] /pvtm@fdaf0000 at simplebus0 <rockchip,rk3588-npu-pvtm> not configured
[ 1.000003] simplebus0: set default config for pvtm@fdb30000
[ 1.000003] /pvtm@fdb30000 at simplebus0 <rockchip,rk3588-gpu-pvtm> not configured
[ 1.000003] simplebus0: set default config for test-power
[ 1.000003] simplebus0: set default config for rt5640-sound
[ 1.000003] ausoc0 at simplebus0 (/rt5640-sound): rockchip,rt5640-codec
[ 1.000003] simplebus0: set default config for rp_power
[ 1.000003] /rp_power at simplebus0 <rp_power> not configured
[ 1.000003] simplebus0: set default config for rp_gpio
[ 1.000003] /rp_gpio at simplebus0 <rp_gpio> not configured
[ 1.000003] simplebus0: set default config for __symbols__
[ 1.000003] rkdrm0: autoconfiguration error: no display interface ports configured
[ 1.000003] rkdrm0: autoconfiguration error: couldn't register DRM device: -6
[ 1.000003] ausoc0: autoconfiguration error: couldn't acquire cpu dai on rt5640-sound node
[ 1.000003] timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
[ 1.000003] UVM: using package allocation scheme, 1 package(s) per bucket
[ 1.644461] cpufreqdt0: autoconfiguration error: couldn't acquire cpu-supply
[ 1.654462] cpufreqdt1: autoconfiguration error: couldn't acquire clock
[ 1.654462] cpufreqdt2: autoconfiguration error: couldn't acquire clock
[ 1.654462] cpufreqdt3: autoconfiguration error: couldn't acquire clock
[ 1.664461] cpufreqdt4: autoconfiguration error: couldn't acquire cpu-supply
[ 1.664461] cpufreqdt5: autoconfiguration error: couldn't acquire clock
[ 1.674462] cpufreqdt6: autoconfiguration error: couldn't acquire cpu-supply
[ 1.674462] cpufreqdt7: autoconfiguration error: couldn't acquire clock
[ 1.684462] uhub0 at usb2: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
[ 1.694463] uhub0: 1 port with 1 removable, self powered
[ 1.694463] uhub1 at usb3: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
[ 1.704462] uhub1: 1 port with 1 removable, self powered
[ 1.714463] uhub2 at usb1: NetBSD (0x0000) EHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 1
[ 1.724464] uhub2: 1 port with 1 removable, self powered
[ 1.724464] uhub3 at usb0: NetBSD (0x0000) EHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 1
[ 1.734465] uhub3: 1 port with 1 removable, self powered
[ 1.744465] IPsec: Initialized Security Association Processing.
[ 1.744465] WARNING: system needs entropy for security; see entropy(7)
[ 1.754465] aes: ARMv8.0-AES
[ 1.754465] chacha: Portable C ChaCha
[ 1.764465] adiantum: self-test passed
[ 1.764465] aes_ccm: self-test passed
[ 1.764465] blake2s: self-test passed
[ 1.774465] crypto: assign driver 0, flags 2
[ 1.774465] crypto: driver 0 registers alg 1 flags 0 maxoplen 0
[ 1.784466] crypto: driver 0 registers alg 2 flags 0 maxoplen 0
[ 1.784466] crypto: driver 0 registers alg 3 flags 0 maxoplen 0
[ 1.794466] crypto: driver 0 registers alg 4 flags 0 maxoplen 0
[ 1.794466] crypto: driver 0 registers alg 5 flags 0 maxoplen 0
[ 1.804467] crypto: driver 0 registers alg 26 flags 0 maxoplen 0
[ 1.814467] crypto: driver 0 registers alg 27 flags 0 maxoplen 0
[ 1.814467] crypto: driver 0 registers alg 29 flags 0 maxoplen 0
[ 1.824467] crypto: driver 0 registers alg 33 flags 0 maxoplen 0
[ 1.824467] crypto: driver 0 registers alg 17 flags 0 maxoplen 0
[ 1.834468] crypto: driver 0 registers alg 6 flags 0 maxoplen 0
[ 1.844468] crypto: driver 0 registers alg 19 flags 0 maxoplen 0
[ 1.844468] crypto: driver 0 registers alg 7 flags 0 maxoplen 0
[ 1.854469] crypto: driver 0 registers alg 20 flags 0 maxoplen 0
[ 1.854469] crypto: driver 0 registers alg 15 flags 0 maxoplen 0
[ 1.864469] crypto: driver 0 registers alg 24 flags 0 maxoplen 0
[ 1.874469] crypto: driver 0 registers alg 25 flags 0 maxoplen 0
[ 1.874469] crypto: driver 0 registers alg 8 flags 0 maxoplen 0
[ 1.884470] crypto: driver 0 registers alg 21 flags 0 maxoplen 0
[ 1.884470] crypto: driver 0 registers alg 16 flags 0 maxoplen 0
[ 1.894470] crypto: driver 0 registers alg 9 flags 0 maxoplen 0
[ 1.904470] crypto: driver 0 registers alg 10 flags 0 maxoplen 0
[ 1.904470] crypto: driver 0 registers alg 13 flags 0 maxoplen 0
[ 1.914471] crypto: driver 0 registers alg 14 flags 0 maxoplen 0
[ 1.914471] crypto: driver 0 registers alg 28 flags 0 maxoplen 0
[ 1.924471] crypto: driver 0 registers alg 30 flags 0 maxoplen 0
[ 1.934472] crypto: driver 0 registers alg 31 flags 0 maxoplen 0
[ 1.934472] crypto: driver 0 registers alg 32 flags 0 maxoplen 0
[ 1.944472] crypto: driver 0 registers alg 11 flags 0 maxoplen 0
[ 1.944472] crypto: driver 0 registers alg 18 flags 0 maxoplen 0
[ 1.954472] crypto: driver 0 registers alg 23 flags 0 maxoplen 0
[ 1.964473] crypto: driver 0 registers alg 22 flags 0 maxoplen 0
[ 1.964473] cgd: self-test aes-xts-256
[ 1.974473] cgd: self-test aes-xts-512
[ 1.974473] cgd: self-test aes-cbc-128
[ 1.974473] cgd: self-test aes-cbc-256
[ 1.984473] cgd: self-test 3des-cbc-192
[ 1.984473] cgd: self-test blowfish-cbc-448
[ 1.984473] cgd: self-test aes-cbc-128 (encblkno8)
[ 1.994474] cgd: self-tests passed
[ 1.994474] Searching for RAID components...
[ 2.004474] rf_buildroothack: rootspec eqos0
[ 2.004474] WARNING: 14 errors while detecting hardware; check system log.
[ 2.014474] boot device: <unknown>
[ 2.014474] root on eqos0
[ 2.023570] nfs_boot: trying DHCP/BOOTP
[ 8.364708] nfs_boot: DHCP next-server: 0.0.0.0
[ 8.364708] nfs_boot: my_name=rk3588
[ 8.374710] nfs_boot: my_domain=lab.nerv.org
[ 8.374710] nfs_boot: my_addr=172.17.4.107
[ 8.374710] nfs_boot: my_mask=255.255.0.0
[ 8.384709] nfs_boot: gateway=172.17.4.40
[ 17.385040] root on 172.17.4.40:/src/boot/rk3588
[ 17.385040] root file system type: nfs
[ 17.395041] kern.module.path=/stand/evbarm/9.99.99/modules
[ 17.395041] WARNING: no TOD clock present
[ 17.405041] WARNING: using filesystem time
[ 17.412243] WARNING: CHECK AND RESET THE DATE!
[ 18.345094] WARNING: consolidating less than full entropy
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