Created
April 29, 2022 16:07
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% cpuctl -v identify 0; cpuctl -v identify 4 | |
cpu0: MIDR_EL1: 0x611f0221 | |
cpu0: MPIDR_EL1: 0x0000000080000000 | |
cpu0: ID_AA64DFR0_EL1: 0x0000000010305f09 | |
cpu0: ID_AA64DFR1_EL1: 0x0000000000000000 | |
cpu0: ID_AA64ISAR0_EL1: 0x0221100110212120 | |
cpu0: ID_AA64ISAR1_EL1: 0x0000011110211202 | |
cpu0: ID_AA64MMFR0_EL1: 0x000012120f100001 | |
cpu0: ID_AA64MMFR1_EL1: 0x0000000011212100 | |
cpu0: ID_AA64MMFR2_EL1: 0x1201111100001011 | |
cpu0: ID_AA64PFR0_EL1: 0x1101000010110111 | |
cpu0: ID_AA64PFR1_EL1: 0x00000020 | |
cpu0: ID_AA64ZFR0_EL1: 0x0000000000000000 | |
cpu0: MVFR0_EL1: 0x00000000 | |
cpu0: MVFR1_EL1: 0x00000000 | |
cpu0: MVFR2_EL1: 0x00000000 | |
cpu0: CLIDR_EL1: 0x0000000081000023 | |
cpu0: CTR_EL0: 0x0000000084448004 | |
cpu0: Apple Inc., M1 Icestorm r1p1 (Apple Apple Silicon core) | |
cpu0: revision: 0x00000000 | |
cpu0: multiprocessor affinity: Affinity-Level: 0-0-0-0 | |
cpu0: multiprocessor affinity: Multiprocessor system | |
cpu0: multiprocessor affinity: Core Independent | |
cpu0: isa features 0: AES: 0x2: AESE/AESD/AESMC/AESIMC+PMULL/PMULL2 | |
cpu0: isa features 0: SHA1: 0x1: SHA1C/SHA1P/SHA1M/SHA1H/SHA1SU0/SHA1SU1 | |
cpu0: isa features 0: SHA2: 0x2: SHA256H/SHA256H2/SHA256SU0/SHA256SU1/SHA512H/SHA512H2/SHA512SU0/SHA512SU1 | |
cpu0: isa features 0: CRC32: 0x1: CRC32B/CRC32H/CRC32W/CRC32X/CRC32CB/CRC32CH/CRC32CW/CRC32CX | |
cpu0: isa features 0: Atomic: 0x2: LDADD/LDCLR/LDEOR/LDSET/LDSMAX/LDSMIN/LDUMAX/LDUMIN/CAS/CASP/SWP | |
cpu0: isa features 0: RDM: 0x1: SQRDMLAH/SQRDMLSH | |
cpu0: isa features 0: SHA3: 0x1: EOR3/RAX1/XAR/BCAX | |
cpu0: isa features 0: SM3: 0x0: No SM3 | |
cpu0: isa features 0: SM4: 0x0: No SM4 | |
cpu0: isa features 0: DP: 0x1: UDOT/SDOT | |
cpu0: isa features 0: FHM: 0x1: FMLAL/FMLSL | |
cpu0: isa features 0: TS: 0x2: CFINV/RMIF/SETF16/SETF8/AXFLAG/XAFLAG | |
cpu0: isa features 0: TLBI: 0x2: Outer shareable and TLB range maintenance instructions | |
cpu0: isa features 0: RNDR: 0x0: No RNDR/RNDRRS | |
cpu0: isa features 1: DPB: 0x2: DC CVAP/DC CVADP | |
cpu0: isa features 1: APA: 0x0: No Architected Address Authentication algorithm | |
cpu0: isa features 1: API: 0x2: EnhancedPAC | |
cpu0: isa features 1: JSCVT: 0x1: FJCVTZS | |
cpu0: isa features 1: FCMA: 0x1: FCMLA/FCADD | |
cpu0: isa features 1: LRCPC: 0x2: LDAPR/LDAPUR/STLUR | |
cpu0: isa features 1: GPA: 0x0: No Architected Generic Authentication algorithm | |
cpu0: isa features 1: GPI: 0x1: Generic Authentication algorithm implemented | |
cpu0: isa features 1: FRINTTS: 0x1: FRINT32Z/FRINT32X/FRINT64Z/FRINT64X | |
cpu0: isa features 1: SB: 0x1: SB | |
cpu0: isa features 1: SPECRES: 0x1: CFP RCTX/DVP RCTX/CPP RCTX | |
cpu0: isa features 1: BF16: 0x0: No BFloat16 | |
cpu0: isa features 1: DGH: 0x0: Data Gathering Hint not implemented | |
cpu0: isa features 1: I8MM: 0x0: No Int8 matrix | |
cpu0: isa features 1: XS: 0x0: No XS/nXS qualifier | |
cpu0: isa features 1: LS64: 0x0: No LS64 | |
cpu0: memory model 0: PARange: 0x1: 36bits/64GB | |
cpu0: memory model 0: ASIDBit: 0x0: 8bits | |
cpu0: memory model 0: BigEnd: 0x0: No mixed-endian | |
cpu0: memory model 0: SNSMem: 0x0: No distinction B/W Secure and Non-secure Memory | |
cpu0: memory model 0: BigEndEL0: 0x0: No mixed-endian at EL0 | |
cpu0: memory model 0: TGran16: 0x1: 16KB granule | |
cpu0: memory model 0: TGran64: 0xf: No 64KB granule | |
cpu0: memory model 0: TGran4: 0x0: 4KB granule | |
cpu0: memory model 0: TGran16_2: 0x2: 16KB granule at stage2 | |
cpu0: memory model 0: TGran64_2: 0x1: No 64KB granule at stage2 | |
cpu0: memory model 0: TGran4_2: 0x2: 4KB granule at stage2 | |
cpu0: memory model 0: ExS: 0x1: Non-context synchronizing exception entry and exit are supported | |
cpu0: memory model 0: FGT: 0x0: fine-grained trap controls not implemented | |
cpu0: memory model 0: ECV: 0x0: Enhanced Counter Virtualization not implemented | |
cpu0: memory model 1: HAFDBS: 0x0: Access and Dirty flags not supported | |
cpu0: memory model 1: VMIDBits: 0x0: 8bits | |
cpu0: memory model 1: VH: 0x1: Virtualization Host Extensions supported | |
cpu0: memory model 1: HPDS: 0x2: Disabling of hierarchical controls supported, plus PTD | |
cpu0: memory model 1: LO: 0x1: LORegions supported | |
cpu0: memory model 1: PAN: 0x2: PAN supported, and instructions supported | |
cpu0: memory model 1: SpecSEI: 0x1: SError interrupt supported | |
cpu0: memory model 1: XNX: 0x1: Distinction between EL0 and EL1 XN control at stage2 supported | |
cpu0: memory model 1: TWED: 0x0: Configurable delayed trapping of WFE is not supported | |
cpu0: memory model 1: ETS: 0x0: Enhanced Translation Synchronization not supported | |
cpu0: memory model 1: HCX: 0x0: HCRX_EL2 not supported | |
cpu0: memory model 1: AFP: 0x0: FPCR.{AH,FIZ,NEP} fields not supported | |
cpu0: memory model 1: nTLBPA: 0x0: might include non-coherent caches | |
cpu0: processor feature 0: EL0: 0x1: AArch64 | |
cpu0: processor feature 0: EL1: 0x1: AArch64 | |
cpu0: processor feature 0: EL2: 0x1: AArch64 | |
cpu0: processor feature 0: EL3: 0x0: No EL3 | |
cpu0: processor feature 0: FP: 0x1: Floating Point including half-precision support | |
cpu0: processor feature 0: AdvSIMD: 0x1: Advanced SIMD including half-precision support | |
cpu0: processor feature 0: GIC: 0x0: GIC CPU interface sysregs not implemented | |
cpu0: processor feature 0: RAS: 0x1: Reliability/Availability/Serviceability supported | |
cpu0: processor feature 0: SVE: 0x0: Scalable Vector Extensions not implemented | |
cpu0: processor feature 0: SEL2: 0x0: Secure EL2 not implemented | |
cpu0: processor feature 0: MPAM: 0x0: Memory Partitioning and Monitoring not implemented | |
cpu0: processor feature 0: AMU: 0x0: Activity Monitors Extension not implemented | |
cpu0: processor feature 0: DIT: 0x1: Data-Independent Timing guaranteed by PSTATE.DIT | |
cpu0: processor feature 0: CSV2: 0x1: Branch prediction maybe not Spectred | |
cpu0: processor feature 0: CSV3: 0x1: Faults maybe not Spectred | |
cpu0: processor feature 1: BT: 0x0: Branch Target Identification not implemented | |
cpu0: processor feature 1: SSBS: 0x2: Speculative Store Bypassing control implemented, plus MSR/MRS | |
cpu0: processor feature 1: MTE: 0x0: Memory Tagging Extension not implemented | |
cpu0: processor feature 1: RAS_frac: 0x0: Regular RAS | |
cpu0: processor feature 1: MPAM_frac: 0x0: MPAM not implemented, or v1.0 | |
cpu0: processor feature 1: CSV2_frac: 0x0: not disclosed | |
cpu0: debug feature 0: CTX_CMPs: 2 context-aware breakpoints | |
cpu0: debug feature 0: WRPs: 4 watchpoints | |
cpu0: debug feature 0: BRPs: 6 breakpoints | |
cpu0: debug feature 0: DebugVer: 0x9: ARMv8.4 debug architecture | |
cpu0: debug feature 0: TraceVer: 0x0: Trace supported | |
cpu0: debug feature 0: PMUVer: 0xf: implementation defined | |
cpu0: debug feature 0: PMSVer: 0x0: Statistical Profiling Extension not implemented | |
cpu0: debug feature 0: DoubleLock: 0x0: OS Double Lock implemented | |
cpu0: debug feature 0: TraceFilt: 0x0: ARMv8.4 Self-hosted Trace Extension not implemented | |
cpu0: debug feature 0: MTPMU: 0x0: Multi-threaded PMU extension not implemented, or implementation defined | |
cpu0: media and VFP features 0: SIMDreg: 0x0: No SIMD | |
cpu0: media and VFP features 0: FPSP: 0x0: No VFP support single precision | |
cpu0: media and VFP features 0: FPDP: 0x0: No VFP support double precision | |
cpu0: media and VFP features 0: FPTrap: 0x0: No floating point exception trapping support | |
cpu0: media and VFP features 0: FPDivide: 0x0: VDIV not supported | |
cpu0: media and VFP features 0: FPSqrt: 0x0: VSQRT not supported | |
cpu0: media and VFP features 0: FPShVec: 0x0: Short Vectors not supported | |
cpu0: media and VFP features 0: FPRound: 0x0: Only Round to Nearest mode | |
cpu0: media and VFP features 1: FPFtZ: 0x0: only the Flush-to-Zero | |
cpu0: media and VFP features 1: FPDNan: 0x0: Default NaN | |
cpu0: media and VFP features 1: SIMDLS: 0x0: No Advanced SIMD Load/Store | |
cpu0: media and VFP features 1: SIMDInt: 0x0: No Advanced SIMD Integer | |
cpu0: media and VFP features 1: SIMDSP: 0x0: No Advanced SIMD single precision | |
cpu0: media and VFP features 1: SIMDHP: 0x0: No Advanced SIMD half precision | |
cpu0: media and VFP features 1: FPHP: 0x0: No half precision conversion | |
cpu0: media and VFP features 1: SIMDFMAC: 0x0: No Fused Multiply-Accumulate | |
cpu0: media and VFP features 2: SIMDMisc: 0x0: No miscellaneous features | |
cpu0: media and VFP features 2: FPMisc: 0x0: No miscellaneous features | |
cpu0: cache level: L1: 0x3: Instruction and Data cache | |
cpu0: cache level: L2: 0x4: Unified cache | |
cpu0: cache level: L3: 0x0: None | |
cpu0: cache level: L4: 0x0: None | |
cpu0: cache level: L5: 0x0: None | |
cpu0: cache level: L6: 0x0: None | |
cpu0: cache level: L7: 0x0: None | |
cpu0: cache level: LoUU: 0x0: 0 | |
cpu0: cache level: LoC: 0x1: 1 | |
cpu0: cache level: LoUIS: 0x0: 0 | |
cpu0: cache level: ICB: 0x2: 2 | |
cpu0: cache type: IminLine: 0x4: 64 | |
cpu0: cache type: DminLine: 0x4: 64 | |
cpu0: cache type: L1 Icache policy: 0x2: VIPT | |
cpu0: cache type: ERG: 0x4: 64 | |
cpu0: cache type: CWG: 0x4: 64 | |
cpu0: cache type: DIC: 0x0: 0 | |
cpu0: cache type: IDC: 0x0: 0 | |
cpu4: MIDR_EL1: 0x611f0231 | |
cpu4: MPIDR_EL1: 0x0000000080010100 | |
cpu4: ID_AA64DFR0_EL1: 0x0000000010305f09 | |
cpu4: ID_AA64DFR1_EL1: 0x0000000000000000 | |
cpu4: ID_AA64ISAR0_EL1: 0x0221100110212120 | |
cpu4: ID_AA64ISAR1_EL1: 0x0000011110211202 | |
cpu4: ID_AA64MMFR0_EL1: 0x000012120f100001 | |
cpu4: ID_AA64MMFR1_EL1: 0x0000000011212100 | |
cpu4: ID_AA64MMFR2_EL1: 0x1201111100001011 | |
cpu4: ID_AA64PFR0_EL1: 0x1101000010110111 | |
cpu4: ID_AA64PFR1_EL1: 0x00000020 | |
cpu4: ID_AA64ZFR0_EL1: 0x0000000000000000 | |
cpu4: MVFR0_EL1: 0x00000000 | |
cpu4: MVFR1_EL1: 0x00000000 | |
cpu4: MVFR2_EL1: 0x00000000 | |
cpu4: CLIDR_EL1: 0x0000000081000023 | |
cpu4: CTR_EL0: 0x0000000084448004 | |
cpu4: Apple Inc., M1 Firestorm r1p1 (Apple Apple Silicon core) | |
cpu4: revision: 0x00000000 | |
cpu4: multiprocessor affinity: Affinity-Level: 0-1-1-0 | |
cpu4: multiprocessor affinity: Multiprocessor system | |
cpu4: multiprocessor affinity: Core Independent | |
cpu4: isa features 0: AES: 0x2: AESE/AESD/AESMC/AESIMC+PMULL/PMULL2 | |
cpu4: isa features 0: SHA1: 0x1: SHA1C/SHA1P/SHA1M/SHA1H/SHA1SU0/SHA1SU1 | |
cpu4: isa features 0: SHA2: 0x2: SHA256H/SHA256H2/SHA256SU0/SHA256SU1/SHA512H/SHA512H2/SHA512SU0/SHA512SU1 | |
cpu4: isa features 0: CRC32: 0x1: CRC32B/CRC32H/CRC32W/CRC32X/CRC32CB/CRC32CH/CRC32CW/CRC32CX | |
cpu4: isa features 0: Atomic: 0x2: LDADD/LDCLR/LDEOR/LDSET/LDSMAX/LDSMIN/LDUMAX/LDUMIN/CAS/CASP/SWP | |
cpu4: isa features 0: RDM: 0x1: SQRDMLAH/SQRDMLSH | |
cpu4: isa features 0: SHA3: 0x1: EOR3/RAX1/XAR/BCAX | |
cpu4: isa features 0: SM3: 0x0: No SM3 | |
cpu4: isa features 0: SM4: 0x0: No SM4 | |
cpu4: isa features 0: DP: 0x1: UDOT/SDOT | |
cpu4: isa features 0: FHM: 0x1: FMLAL/FMLSL | |
cpu4: isa features 0: TS: 0x2: CFINV/RMIF/SETF16/SETF8/AXFLAG/XAFLAG | |
cpu4: isa features 0: TLBI: 0x2: Outer shareable and TLB range maintenance instructions | |
cpu4: isa features 0: RNDR: 0x0: No RNDR/RNDRRS | |
cpu4: isa features 1: DPB: 0x2: DC CVAP/DC CVADP | |
cpu4: isa features 1: APA: 0x0: No Architected Address Authentication algorithm | |
cpu4: isa features 1: API: 0x2: EnhancedPAC | |
cpu4: isa features 1: JSCVT: 0x1: FJCVTZS | |
cpu4: isa features 1: FCMA: 0x1: FCMLA/FCADD | |
cpu4: isa features 1: LRCPC: 0x2: LDAPR/LDAPUR/STLUR | |
cpu4: isa features 1: GPA: 0x0: No Architected Generic Authentication algorithm | |
cpu4: isa features 1: GPI: 0x1: Generic Authentication algorithm implemented | |
cpu4: isa features 1: FRINTTS: 0x1: FRINT32Z/FRINT32X/FRINT64Z/FRINT64X | |
cpu4: isa features 1: SB: 0x1: SB | |
cpu4: isa features 1: SPECRES: 0x1: CFP RCTX/DVP RCTX/CPP RCTX | |
cpu4: isa features 1: BF16: 0x0: No BFloat16 | |
cpu4: isa features 1: DGH: 0x0: Data Gathering Hint not implemented | |
cpu4: isa features 1: I8MM: 0x0: No Int8 matrix | |
cpu4: isa features 1: XS: 0x0: No XS/nXS qualifier | |
cpu4: isa features 1: LS64: 0x0: No LS64 | |
cpu4: memory model 0: PARange: 0x1: 36bits/64GB | |
cpu4: memory model 0: ASIDBit: 0x0: 8bits | |
cpu4: memory model 0: BigEnd: 0x0: No mixed-endian | |
cpu4: memory model 0: SNSMem: 0x0: No distinction B/W Secure and Non-secure Memory | |
cpu4: memory model 0: BigEndEL0: 0x0: No mixed-endian at EL0 | |
cpu4: memory model 0: TGran16: 0x1: 16KB granule | |
cpu4: memory model 0: TGran64: 0xf: No 64KB granule | |
cpu4: memory model 0: TGran4: 0x0: 4KB granule | |
cpu4: memory model 0: TGran16_2: 0x2: 16KB granule at stage2 | |
cpu4: memory model 0: TGran64_2: 0x1: No 64KB granule at stage2 | |
cpu4: memory model 0: TGran4_2: 0x2: 4KB granule at stage2 | |
cpu4: memory model 0: ExS: 0x1: Non-context synchronizing exception entry and exit are supported | |
cpu4: memory model 0: FGT: 0x0: fine-grained trap controls not implemented | |
cpu4: memory model 0: ECV: 0x0: Enhanced Counter Virtualization not implemented | |
cpu4: memory model 1: HAFDBS: 0x0: Access and Dirty flags not supported | |
cpu4: memory model 1: VMIDBits: 0x0: 8bits | |
cpu4: memory model 1: VH: 0x1: Virtualization Host Extensions supported | |
cpu4: memory model 1: HPDS: 0x2: Disabling of hierarchical controls supported, plus PTD | |
cpu4: memory model 1: LO: 0x1: LORegions supported | |
cpu4: memory model 1: PAN: 0x2: PAN supported, and instructions supported | |
cpu4: memory model 1: SpecSEI: 0x1: SError interrupt supported | |
cpu4: memory model 1: XNX: 0x1: Distinction between EL0 and EL1 XN control at stage2 supported | |
cpu4: memory model 1: TWED: 0x0: Configurable delayed trapping of WFE is not supported | |
cpu4: memory model 1: ETS: 0x0: Enhanced Translation Synchronization not supported | |
cpu4: memory model 1: HCX: 0x0: HCRX_EL2 not supported | |
cpu4: memory model 1: AFP: 0x0: FPCR.{AH,FIZ,NEP} fields not supported | |
cpu4: memory model 1: nTLBPA: 0x0: might include non-coherent caches | |
cpu4: processor feature 0: EL0: 0x1: AArch64 | |
cpu4: processor feature 0: EL1: 0x1: AArch64 | |
cpu4: processor feature 0: EL2: 0x1: AArch64 | |
cpu4: processor feature 0: EL3: 0x0: No EL3 | |
cpu4: processor feature 0: FP: 0x1: Floating Point including half-precision support | |
cpu4: processor feature 0: AdvSIMD: 0x1: Advanced SIMD including half-precision support | |
cpu4: processor feature 0: GIC: 0x0: GIC CPU interface sysregs not implemented | |
cpu4: processor feature 0: RAS: 0x1: Reliability/Availability/Serviceability supported | |
cpu4: processor feature 0: SVE: 0x0: Scalable Vector Extensions not implemented | |
cpu4: processor feature 0: SEL2: 0x0: Secure EL2 not implemented | |
cpu4: processor feature 0: MPAM: 0x0: Memory Partitioning and Monitoring not implemented | |
cpu4: processor feature 0: AMU: 0x0: Activity Monitors Extension not implemented | |
cpu4: processor feature 0: DIT: 0x1: Data-Independent Timing guaranteed by PSTATE.DIT | |
cpu4: processor feature 0: CSV2: 0x1: Branch prediction maybe not Spectred | |
cpu4: processor feature 0: CSV3: 0x1: Faults maybe not Spectred | |
cpu4: processor feature 1: BT: 0x0: Branch Target Identification not implemented | |
cpu4: processor feature 1: SSBS: 0x2: Speculative Store Bypassing control implemented, plus MSR/MRS | |
cpu4: processor feature 1: MTE: 0x0: Memory Tagging Extension not implemented | |
cpu4: processor feature 1: RAS_frac: 0x0: Regular RAS | |
cpu4: processor feature 1: MPAM_frac: 0x0: MPAM not implemented, or v1.0 | |
cpu4: processor feature 1: CSV2_frac: 0x0: not disclosed | |
cpu4: debug feature 0: CTX_CMPs: 2 context-aware breakpoints | |
cpu4: debug feature 0: WRPs: 4 watchpoints | |
cpu4: debug feature 0: BRPs: 6 breakpoints | |
cpu4: debug feature 0: DebugVer: 0x9: ARMv8.4 debug architecture | |
cpu4: debug feature 0: TraceVer: 0x0: Trace supported | |
cpu4: debug feature 0: PMUVer: 0xf: implementation defined | |
cpu4: debug feature 0: PMSVer: 0x0: Statistical Profiling Extension not implemented | |
cpu4: debug feature 0: DoubleLock: 0x0: OS Double Lock implemented | |
cpu4: debug feature 0: TraceFilt: 0x0: ARMv8.4 Self-hosted Trace Extension not implemented | |
cpu4: debug feature 0: MTPMU: 0x0: Multi-threaded PMU extension not implemented, or implementation defined | |
cpu4: media and VFP features 0: SIMDreg: 0x0: No SIMD | |
cpu4: media and VFP features 0: FPSP: 0x0: No VFP support single precision | |
cpu4: media and VFP features 0: FPDP: 0x0: No VFP support double precision | |
cpu4: media and VFP features 0: FPTrap: 0x0: No floating point exception trapping support | |
cpu4: media and VFP features 0: FPDivide: 0x0: VDIV not supported | |
cpu4: media and VFP features 0: FPSqrt: 0x0: VSQRT not supported | |
cpu4: media and VFP features 0: FPShVec: 0x0: Short Vectors not supported | |
cpu4: media and VFP features 0: FPRound: 0x0: Only Round to Nearest mode | |
cpu4: media and VFP features 1: FPFtZ: 0x0: only the Flush-to-Zero | |
cpu4: media and VFP features 1: FPDNan: 0x0: Default NaN | |
cpu4: media and VFP features 1: SIMDLS: 0x0: No Advanced SIMD Load/Store | |
cpu4: media and VFP features 1: SIMDInt: 0x0: No Advanced SIMD Integer | |
cpu4: media and VFP features 1: SIMDSP: 0x0: No Advanced SIMD single precision | |
cpu4: media and VFP features 1: SIMDHP: 0x0: No Advanced SIMD half precision | |
cpu4: media and VFP features 1: FPHP: 0x0: No half precision conversion | |
cpu4: media and VFP features 1: SIMDFMAC: 0x0: No Fused Multiply-Accumulate | |
cpu4: media and VFP features 2: SIMDMisc: 0x0: No miscellaneous features | |
cpu4: media and VFP features 2: FPMisc: 0x0: No miscellaneous features | |
cpu4: cache level: L1: 0x3: Instruction and Data cache | |
cpu4: cache level: L2: 0x4: Unified cache | |
cpu4: cache level: L3: 0x0: None | |
cpu4: cache level: L4: 0x0: None | |
cpu4: cache level: L5: 0x0: None | |
cpu4: cache level: L6: 0x0: None | |
cpu4: cache level: L7: 0x0: None | |
cpu4: cache level: LoUU: 0x0: 0 | |
cpu4: cache level: LoC: 0x1: 1 | |
cpu4: cache level: LoUIS: 0x0: 0 | |
cpu4: cache level: ICB: 0x2: 2 | |
cpu4: cache type: IminLine: 0x4: 64 | |
cpu4: cache type: DminLine: 0x4: 64 | |
cpu4: cache type: L1 Icache policy: 0x2: VIPT | |
cpu4: cache type: ERG: 0x4: 64 | |
cpu4: cache type: CWG: 0x4: 64 | |
cpu4: cache type: DIC: 0x0: 0 | |
cpu4: cache type: IDC: 0x0: 0 |
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