gistfile1.txt

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use iEEE.std_logic_arith.all;
use iEEE.std_logic_unsigned."+";

use IEEE.std_logic_textio.all;
library std;
use std.textio.all;

entity vsync_strace is
    generic (
        CONTROLLER_ID : std_logic_vector(3 downto 0) := "0000"
    );
    port (
        axis_aclk    : in std_logic;
        axis_aresetn : in std_logic;

        s_vsync : in std_logic;
        m_vsync : out std_logic;

        s_ctrl_axis_tready  : out std_logic;
        s_ctrl_axis_tdata   : in std_logic_vector(31 downto 0);
        s_ctrl_axis_tvalid  : in std_logic;

        m_ctrl_axis_tvalid  : out std_logic;
        m_ctrl_axis_tdata   : out std_logic_vector(31 downto 0);
        m_ctrl_axis_tready  : in std_logic
    );
end vsync_strace;

architecture arch_implement of vsync_strace is
    signal this_controller_id : std_logic_vector(3 downto 0) := CONTROLLER_ID;

    ------------------------------------------------
    signal counter : std_logic_vector(31 downto 0);

    ------------------------------------------------
    signal m_ctrl_axis_tvalid_reg : std_logic := '0';

    signal m_ctrl_axis_tdata_reg : std_logic_vector (31 downto 0) := ( others => '0' );

    signal over_flow_error_n : std_logic_vector(13 downto 0) := ( others => '0' );
    signal over_flow_error_flag : std_logic := '0';

    signal no_produce_data_flag : std_logic := '0';
    signal still_fill_flag : std_logic;
    ------------------------------------------------
begin
        process(axis_aclk)
        begin
        if (rising_edge(axis_aclk)) then
            if ( axis_aresetn = '0') then
                counter <= ( others => '0' ) ;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    ----------------------------------------------------------------
    no_produce_data_flag <= not s_vsync;

    still_fill_flag <= '1' when m_ctrl_axis_tvalid_reg = '1' and m_ctrl_axis_tready = '0' else '0';
    s_ctrl_axis_tready <= no_produce_data_flag and not still_fill_flag;

        process(axis_aclk)
        begin
        if (rising_edge(axis_aclk)) then
            if ( axis_aresetn = '0') then
                m_ctrl_axis_tvalid_reg <= '0';

                over_flow_error_n <= ( others => '0' );
                over_flow_error_flag <= '0';
            else
                if s_vsync = '1' then
                    -- snap it!!
                    m_ctrl_axis_tvalid_reg <= '1';

                    m_ctrl_axis_tdata_reg(31 downto 28) <= this_controller_id;
                    m_ctrl_axis_tdata_reg(27) <= '1';
                    m_ctrl_axis_tdata_reg(26) <= '1';
                    m_ctrl_axis_tdata_reg(25 downto 0) <= counter(25 downto 0);

                    if still_fill_flag = '1' then
                        over_flow_error_flag <= '1';
                        over_flow_error_n <= over_flow_error_n + 1;
                    end if;
                else
                    if still_fill_flag = '1' then
                        m_ctrl_axis_tvalid_reg <= '1';
                    else
                        m_ctrl_axis_tvalid_reg <= s_ctrl_axis_tvalid;
                        m_ctrl_axis_tdata_reg <= s_ctrl_axis_tdata;
                    end if;
                end if;
            end if;
        end if;
    end process;

    m_ctrl_axis_tvalid <= m_ctrl_axis_tvalid_reg;
    m_ctrl_axis_tdata  <= m_ctrl_axis_tdata_reg;

    ----------------------------------------------------------------
    m_vsync <= s_vsync;

end arch_implement;