Icarus Verilog scenario file for oneshottmr.v

scenario.sv

//////////////////////////////////////////////////////////////
// module :oneshottmr_sim
/////////////////////////////////////////////////////////////
`timescale 1ns/1ps

module oneshottmr_sim;

// Create clock
parameter CLK_E_1MHz = 1000; // ns

// Inputs, Outputs
logic       clk;
logic       rst_n;
logic       trigger;
output      reg tc_n;

// Device under test
oneshottmr  dut(
  .clk        (clk    ),
  .reset_n   (rst_n   ),
  .trigger   (trigger ), // nouse
  .q_n       (tc_n    )  // nouse
);

initial begin
  clk   = 'b0;
  rst_n = 'b1;
  trigger = 'b0;
  #1000; 
  rst_n = 'b0;
  #1000; 
  rst_n = 'b1;
  #8000; 
  trigger = 'b1;
  #3000;
  trigger = 'b0;
end

// clock
always #(CLK_E_1MHz/2) begin
  clk <= ~clk;
end

///////////////////////////////////////////////////
// Test case
///////////////////////////////////////////////////
initial begin

  $dumpfile("scenario.vcd");
  $dumpvars(0, oneshottmr_sim);

  $display("start sim");

  #50000;

  $finish;

end

endmodule