Created
April 28, 2024 04:13
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Icarus Verilog sim execution script for oneshottmr.v
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TOP_MODULE=oneshottmr_sim | |
OUT_FILE=test.out | |
# compile | |
iverilog -g2012 \ | |
-o ${OUT_FILE} \ | |
-s ${TOP_MODULE} ./scenario.sv ../src/oneshottmr.v | |
# ./oneshottmr_orig.v | |
# ../src/oneshottmr.v | |
# simulation | |
vvp ${OUT_FILE} | |
# gtkwave scenario.vcd |
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