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Reference Manual RM0410 and Datasheet DS11532 of STM32F76x in ASCII (best seen in raw text)
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DS11532.txt
=== Cover #1 ===
Features
Includes ST state-of-the-art patented
technology
• Core: Arm® 32-bit Cortex®-M7 CPU with
DPFPU, ART Accelerator and L1-cache:
16 Kbytes I/D cache, allowing 0-wait state
execution from embedded Flash and external
memories, up to 216 MHz, MPU,
462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions.
• Memories
– Up to 2 Mbytes of Flash memory organized
into two banks allowing read-while-write
– SRAM: 512 Kbytes (including 128 Kbytes
of data TCM RAM for critical real-time data)
+ 16 Kbytes of instruction TCM RAM (for
critical real-time routines) + 4 Kbytes of
backup SRAM
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
• Dual mode Quad-SPI
• Graphics
– Chrom-ART Accelerator (DMA2D),
graphical hardware accelerator enabling
enhanced graphical user interface
– Hardware JPEG codec
– LCD-TFT controller supporting up to XGA
resolution
– MIPI® DSI host controller supporting up to
720p 30 Hz resolution
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– Dedicated USB power
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low-power
– Sleep, Stop and Standby modes
– VBAT supply for RTC, 32×32 bit backup
registers + 4 Kbytes backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
• Digital filters for sigma delta modulator
(DFSDM), 8 channels / 4 filters
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
• Up to 18 timers: up to thirteen 16-bit (1x low-
power 16-bit timer available in Stop mode) and
two 32-bit timers, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. All 15 timers
running up to 216 MHz. 2x watchdogs, SysTick
timer
• Debug mode
– SWD and JTAG interfaces
– Cortex®-M7 Trace Macrocell™
• Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 108 MHz
– Up to 166 5 V-tolerant I/Os
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #2 ===
• Up to 28 communication interfaces
– Up to 4 I²C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (12.5 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to 6 SPIs (up to 54 Mbit/s), 3 with
muxed simplex I²S for audio
– 2 x SAIs (serial audio interface)
– 3 × CANs (2.0B Active) and 2x SDMMCs
– SPDIFRX interface
– HDMI-CEC
– MDIO slave interface
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit camera interface up to 54 Mbyte/s
• True random number generator
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
Table 1. Device summary
+-------------+------------------------------------------------------------------+
| Reference | Part number |
+=============+==================================================================+
| STM32F765xx | STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, |
| | STM32F765IG, STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG |
+-------------+------------------------------------------------------------------+
| STM32F767xx | STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, |
| | STM32F767NI, STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI |
+-------------+------------------------------------------------------------------+
| STM32F768Ax | STM32F768AI |
+-------------+------------------------------------------------------------------+
| STM32F769xx | STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, |
| | STM32F769II, STM32F769NG, STM32F769NI |
+-------------+------------------------------------------------------------------+
=== Introduction STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #14 ===
1 Introduction
This document provides information on STM32F765xx, STM32F767xx, STM32F768Ax and
STM32F769xx microcontrollers, such as description, functional overview, pin assignment
and definition, electrical characteristics, packaging, and ordering information.
This document should be read in conjunction with the STM32F765xx, STM32F767xx,
STM32F768Ax and STM32F769xx reference manual (RM0410), available from the
STMicroelectronics website www.st.com.
For information on the Arm®⁽ᵃ⁾ Cortex®-M7 core, please refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description #15 ===
2 Description
The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are based
on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 216 MHz
frequency. The Cortex®-M7 core features a floating point unit (FPU) which supports Arm®
double-precision and single-precision data-processing instructions and data types. It also
implements a full set of DSP instructions and a memory protection unit (MPU) which
enhances the application security.
The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices incorporate
high-speed embedded memories with a Flash memory up to 2 Mbytes, 512 Kbytes of
SRAM (including 128 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of
instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in
the lowest power modes, and an extensive range of enhanced I/Os and peripherals
connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi
layer AXI interconnect supporting internal and external memories access.
All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-
purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-
bit timers, a true random number generator (RNG). They also feature standard and
advanced communication interfaces:
- Up to four I2Cs
- Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock to
allow synchronization.
- Four USARTs plus four UARTs
- An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI)
- Three CANs
- Two SAI serial audio interfaces
- Two SDMMC host interfaces
- Ethernet and camera interfaces
- LCD-TFT display controller
- Chrom-ART Accelerator
- SPDIFRX interface
- HDMI-CEC
Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors.
The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices operate in
the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply
inputs for USB (OTG_FS and OTG_HS) and SDMMC2 (clock, command and 4-bit data) are
available on all the packages except LQFP100 for a greater power supply choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A
comprehensive set of power-saving mode allows the design of low-power applications.
=== Description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #16 ===
The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices offer
devices in 11 packages ranging from 100 pins to 216 pins. The set of included peripherals
changes with the device chosen.
These features make the STM32F765xx, STM32F767xx, STM32F768Ax and
STM32F769xx microcontrollers suitable for a wide range of applications:
- Motor drive and application control
- Medical equipment
- Industrial applications: PLC, inverters, circuit breakers
- Printers, and scanners
- Alarm systems, video intercom, and HVAC
- Home audio appliances
- Mobile applications, Internet of Things
- Wearable devices: smartwatches
The following table lists the peripherals available on each part number.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description #19 ===
Full compatibility throughout the family
The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are fully
pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different
peripherals, and reaching higher performances (higher frequency) for a greater degree of
freedom during the development cycle.
Figure 1 gives compatible board designs between the STM32F7xx and STM32F4xx
families.
Figure 1. Compatible board design for LQFP100 package
The STM32F76x LQFP144, LQFP176, LQFP208, TFBGA216, UFBGA176 packages are
fully pin to pin compatible with STM32F4xx devices.
=== Description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #20 ===
Figure 2. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #21 ===
3 Functional overview
3.1 Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering an outstanding computational performance and low interrupt latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
– Six-stage dual-issue pipeline
– Dynamic branch prediction
– Harvard caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
– 64-bit AXI4 interface
– 64-bit ITCM interface
– 2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
• Tightly Coupled Memory (TCM) interface.
• Harvard instruction and data caches and AXI master (AXIM) interface.
• Dedicated low-latency AHB-Lite peripheral (AHBP) interface.
The processor supports a set of DSP instructions which allow an efficient signal processing
and a complex algorithm execution.
It supports single and double precision FPU (floating point unit), speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 2 shows the general block diagram of the STM32F76xxx family.
Note: The Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #22 ===
3.3 Embedded Flash memory
The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices embed a
Flash memory of up to 2 Mbytes available for storing programs and data. The Flash
interface features:
• Single /or Dual bank operating modes,
• Read-While-Write (RWW) in Dual bank mode.
3.4 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5 Embedded SRAM
All the devices feature:
• System SRAM up to 512 Kbytes:
– SRAM1 on AHB bus Matrix: 368 Kbytes
– SRAM2 on AHB bus Matrix: 16 Kbytes
– DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 128 Kbytes for
critical real-time data.
• Instruction RAM (ITCM-RAM) 16 Kbytes:
– It is mapped on TCM interface and reserved only for CPU Execution/Instruction
useful for critical real-time routines.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific
AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at
CPU clock speed with 0 wait states.
• 4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #23 ===
3.6 AXI-AHB bus matrix
The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx system architecture
is based on 2 sub-systems:
• An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
– 3x AXI to 32-bit AHB bridges connected to AHB bus matrix
– 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory
• A multi-AHB Bus-Matrix
– The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs,
Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM,
FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 3. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx AXI-AHB
bus matrix architecture⁽¹⁾
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #24 ===
3.7 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. The configuration is made by software and the transfer sizes
between the source and the destination are independent.
The DMA can be used with the main peripherals:
• SPI and I²S
• I²C
• USART
• General-purpose, basic and advanced-control timers TIMx
• DAC
• SDMMC
• Camera interface (DCMI)
• ADC
• SAI
• SPDIFRX
• Quad-SPI
• HDMI-CEC
• JPEG codec
• DFSDM1
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #25 ===
3.8 Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
• The NOR/PSRAM memory controller
• The NAND/memory controller
• The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16-,32-bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
• The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.9 Quad-SPI memory interface (QUADSPI)
All the devices embed a Quad-SPI memory interface, which is a specialized communication
interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:
• Direct mode through registers
• External Flash status register polling mode
• Memory mapped mode.
Up to 256 Mbytes external Flash are memory mapped, supporting 8, 16 and 32-bit access.
Code execution is supported.
The opcode and the frame format are fully programmable. The communication can be either
in Single Data Rate or Dual Data Rate.
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #26 ===
3.10 LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
• 2 display layers with dedicated FIFO (64x32-bit)
• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
• Up to 8 input color formats selectable per layer
• Flexible blending between two layers using alpha value (per pixel or constant)
• Flexible programmable parameters for each layer
• Color keying (transparency color)
• Up to 4 programmable interrupt events
3.11 Chrom-ART Accelerator (DMA2D)
The Chrom-Art Accelerator (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
• Rectangle filling with a fixed color
• Rectangle copy
• Rectangle copy with pixel format conversion
• Rectangle composition with blending and pixel format conversion
Various image format codings are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
3.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M7 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #27 ===
3.13 JPEG codec (JPEG)
The JPEG codec provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features:
• 8-bit/channel pixel depths
• Single clock per pixel encoding and decoding
• Support for JPEG header generation and parsing
• Up to four programmable quantization tables
• Fully programmable Huffman tables (two AC and two DC)
• Fully programmable minimum coded unit (MCU)
• Encode/decode support (non simultaneous)
• Single clock Huffman coding and decoding
• Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
• Stallable design
• Support for single, greyscale component
• Functionality to enable/disable header processing
• Internal register interface
• Fully synchronous design
• Configured for high-speed decode mode
3.14 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 25 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.
3.15 Clocks and startup
On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock can be monitored for failure. If a failure is detected, the system automatically
switches back to the internal RC oscillator and a software interrupt is generated (if enabled).
This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.
Similarly, full interrupt management of the PLL clock entry is available when necessary (for
example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #28 ===
The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio
class performance. In this case, the I²S and SAI master clock can generate all standard
sampling frequencies from 8 kHz to 192 kHz.
3.16 Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
• All Flash address space mapped on ITCM or AXIM interface
• All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
• The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to STM32 microcontroller system memory boot mode
application note (AN2606) for details.
3.17 Power supply schemes
• VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
• VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 3.18.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
• VDDSDMMC can be connected either to VDD or an external independent power supply
(1.8 to 3.6V) for SDMMC2 pins (clock, command, and 4-bit data). For example, when
the device is powered at 1.8V, an independent power supply 2.7V can be connected to
VDDSDMMC.When the VDDSDMMC is connected to a separated power supply, it is
independent from VDD or VDDA but it must be the last supply to be provided and the first
to disappear. The following conditions VDDSDMMC must be respected:
– During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower
than VDD
– During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always
lower than VDD
– The VDDSDMMC rising and falling time rate specifications must be respected
– In operating mode phase, VDDSDMMC could be lower or higher than VDD:
All associated GPIOs powered by VDDSDMMC are operating between
VDDSDMMC_MIN and VDDSDMMC_MAX.
• VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers (refer to Figure 4 and Figure 5). For example, when the
device is powered at 1.8V, an independent power supply 3.3V can be connected to
VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent
from VDD or VDDA but it must be the last supply to be provided and the first to
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #29 ===
disappear. The following conditions VDDUSB must be respected:
– During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
– During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
– The VDDUSB rising and falling time rate specifications must be respected
– In operating mode phase, VDDUSB could be lower or higher than VDD:
- If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
- The VDDUSB supply both USB transceiver (USB OTG_HS and USB OTG_FS). If
only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
- If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
VDDUSB are operating between VDD_MIN and VDD_MAX.
Figure 4. VDDUSB connected to VDD power supply
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #30 ===
Figure 5. VDDUSB connected to external power supply
The DSI (Display Serial Interface) sub-system uses several power supply pins which are
independent from the other supply pins:
• VDDDSI is an independent DSI power supply dedicated for DSI Regulator and
MIPI D-PHY. This supply must be connected to global VDD.
• The VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected
externally to VDD12DSI.
• The VDD12DSI pin is used to supply the MIPI D-PHY, and to supply the clock and data
lanes pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin.
• The VSSDSI pin is an isolated supply ground used for DSI sub-system.
• If the DSI functionality is not used at all, then:
– The VDDDSI pin must be connected to global VDD.
– The VCAPDSI pin must be connected externally to VDD12DSI but the external
capacitor is no more needed.
– The VSSDSI pin must be grounded.
3.18 Power supply supervisor
3.18.1 Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #31 ===
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.18.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be
connected to VSS. Refer to Figure 6: Power supply supervisor interconnection with internal
reset OFF.
Figure 6. Power supply supervisor interconnection with internal reset OFF
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 7).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• VBAT functionality is no more available and VBAT pin should be connected to VDD.
All the packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to VSS.
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #32 ===
Figure 7. PDR_ON control with internal reset OFF
3.19 Voltage regulator
The regulator has four operating modes:
• Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
• Regulator OFF
3.19.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
• MR mode used in Run/sleep modes or in Stop modes
– In Run/Sleep modes
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
– In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #33 ===
• LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
– LPR operates in normal mode (default mode when LPR is ON)
– LPR operates in under-drive mode (reduced leakage mode).
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin.
All packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode⁽¹⁾
+-------------------+----------+------------+-----------+--------------+
| Voltage regulator | Run mode | Sleep mode | Stop mode | Standby mode |
| configuration | | | | |
+===================+==========+============+===========+==============+
| Normal mode | MR | MR | MR or LPR | - |
+-------------------+----------+------------+-----------+--------------+
| Over-drive | MR | MR | - | - |
| mode⁽²⁾ | | | | |
+-------------------+----------+------------+-----------+--------------+
| Under-drive mode | - | - | MR or LPR | - |
+-------------------+----------+------------+-----------+--------------+
| Power-down | - | - | - | Yes |
| mode | | | | |
+-------------------+----------+------------+-----------+--------------+
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
3.19.2 Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors should
be replaced by two 100 nF decoupling capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In the regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
• The over-drive and under-drive modes are not available.
• The Standby mode is not available.
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #34 ===
Figure 8. Regulator OFF
The following conditions must be respected:
• VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
• If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9).
• Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 10).
• If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #35 ===
Figure 9. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1,VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1,VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #36 ===
3.19.3 Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
1. Available only on dedicated part number. Refer to Section 8: Ordering information.
3.20 Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Three anti-tamper detection pins with programmable filter.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #37 ===
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator(LSE)
• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE) divided by 32
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
3.21 Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in stop mode):
– Normal mode (default mode when MR or LPR is enabled)
– Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup and
LPTIM1 asynchronous interrupt).
Table 5. Voltage regulator modes in stop mode
+-------------------+------------------------+---------------------------+
| Voltage regulator | Main regulator (MR) | Low-power regulator (LPR) |
| configuration | | |
+===================+========================+===========================+
| Normal mode | MR ON | LPR ON |
+-------------------+------------------------+---------------------------+
| Under-drive mode | MR in under-drive mode | LPR in under-drive mode |
+-------------------+------------------------+---------------------------+
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #38 ===
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11),
or an RTC alarm / wakeup / tamper /time stamp event occurs.
The Standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
3.22 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When the PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is
no more available and the VBAT pin should be connected to VDD.
3.23 Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #39 ===
Table 6. Timer feature comparison
+----------+--------+------------+---------+-----------+------------+----------+---------+-----------+----------+
| Timer | Timer | Counter | Counter | Prescaler | DMA | Capture/ | Complem | Max | Max |
| type | | resolution | type | factor | request | compare | entary | interface | timer |
| | | | | | generation | channels | output | clock | clock |
| | | | | | | | | (MHz) | (MHz)⁽¹⁾ |
+==========+========+============+=========+===========+============+==========+=========+===========+==========+
| Advanced | TIM1, | 16-bit | Up, | Any | Yes | 4 | Yes | 108 | 216 |
| -control | TIM8 | | Down, | integer | | | | | |
| | | | Up/down | between 1 | | | | | |
| | | | | and 65536 | | | | | |
+----------+--------+------------+---------+-----------+------------+----------+---------+-----------+----------+
| General | TIM2, | 32-bit | Up, | Any | Yes | 4 | No | 54 | 108/216 |
| purpose | TIM5 | | Down, | integer | | | | | |
| | | | Up/down | between 1 | | | | | |
| | | | | and 65536 | | | | | |
| +--------+------------+---------+-----------+------------+----------+---------+-----------+----------+
| | TIM3, | 16-bit | Up, | Any | Yes | 4 | No | 54 | 108/216 |
| | TIM4 | | Down, | integer | | | | | |
| | | | Up/down | between 1 | | | | | |
| | | | | and 65536 | | | | | |
| +--------+------------+---------+-----------+------------+----------+---------+-----------+----------+
| | TIM9 | 16-bit | Up | Any | No | 2 | No | 108 | 216 |
| | | | | integer | | | | | |
| | | | | between 1 | | | | | |
| | | | | and 65536 | | | | | |
| +--------+------------+---------+-----------+------------+----------+---------+-----------+----------+
| | TIM10, | 16-bit | Up | Any | No | 1 | No | 108 | 216 |
| | TIM11 | | | integer | | | | | |
| | | | | between 1 | | | | | |
| | | | | and 65536 | | | | | |
| +--------+------------+---------+-----------+------------+----------+---------+-----------+----------+
| | TIM12 | 16-bit | Up | Any | No | 2 | No | 54 | 108/216 |
| | | | | integer | | | | | |
| | | | | between 1 | | | | | |
| | | | | and 65536 | | | | | |
| +--------+------------+---------+-----------+------------+----------+---------+-----------+----------+
| | TIM13, | 16-bit | Up | Any | No | 1 | No | 54 | 108/216 |
| | TIM14 | | | integer | | | | | |
| | | | | between 1 | | | | | |
| | | | | and 65536 | | | | | |
+----------+--------+------------+---------+-----------+------------+----------+---------+-----------+----------+
| Basic | TIM6, | 16-bit | Up | Any | Yes | 0 | No | 54 | 108/216 |
| | TIM7 | | | integer | | | | | |
| | | | | between 1 | | | | | |
| | | | | and 65536 | | | | | |
+----------+--------+------------+---------+-----------+------------+----------+---------+-----------+----------+
1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR
register.
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #40 ===
3.23.1 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.23.2 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F76xxx
devices (see Table 6 for differences).
• TIM2, TIM3, TIM4, TIM5
The STM32F76xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
• TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
3.23.3 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #41 ===
3.23.4 Low-power timer (LPTIM1)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous / one-shot mode
• Selectable software / hardware input trigger
• Selectable clock source:
• Internal clock source: LSE, LSI, HSI or APB clock
• External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
• Programmable digital glitch filter
• Encoder mode
3.23.5 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.23.6 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.23.7 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
• A 24-bit downcounter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #42 ===
3.24 Inter-integrated circuit interface (I²C)
The devices embed 4 I2C. Refer to table Table 7: I2C implementation for the features
implementation.
The I²C bus interface handles communications between the microcontroller and the serial
I²C bus. It controls all I²C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I²C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBusᵀᴹ) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 7. I2C implementation
+--------------------------------------------------------------+------+------+------+------+
| I2C features⁽¹⁾ | I2C1 | I2C2 | I2C3 | I2C4 |
+==============================================================+======+======+======+======+
| Standard-mode (up to 100 kbit/s) | X | X | X | X |
+--------------------------------------------------------------+------+------+------+------+
| Fast-mode (up to 400 kbit/s) | X | X | X | X |
+--------------------------------------------------------------+------+------+------+------+
| Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) | X | X | X | X |
+--------------------------------------------------------------+------+------+------+------+
| Programmable analog and digital noise filters | X | X | X | X |
+--------------------------------------------------------------+------+------+------+------+
| SMBus/PMBus hardware support | X | X | X | X |
+--------------------------------------------------------------+------+------+------+------+
| Independent clock | X | X | X | X |
+--------------------------------------------------------------+------+------+------+------+
1. X: supported.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #43 ===
3.25 Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed USART. Refer to Table 8: USART implementation for the features
implementation.
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format.
The USART peripheral supports:
• Full-duplex asynchronous communications
• Configurable oversampling method by 16 or 8 to give flexibility between speed and
clock tolerance
• Dual clock domain allowing convenient baud rate programming independent from the
PCLK reprogramming
• A common programmable transmit and receive baud rate of up to 27 Mbit/s when the
USART clock source is system clock frequency (max is 216 MHz) and oversampling by
8 is used.
• Auto baud rate detection
• Programmable data word length (7 or 8 or 9 bits) word length
• Programmable data order with MSB-first or LSB-first shifting
• Programmable parity (odd, even, no parity)
• Configurable stop bits (1 or 1.5 or 2 stop bits)
• Synchronous mode and clock output for synchronous communications
• Single-wire half-duplex communications
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Multiprocessor communications
• LIN master synchronous break send capability and LIN slave break detection capability
• IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode
• Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in
the ISO/IEC 7816-3 standard )
• Support for Modbus communication
Table 8 summarizes the implementation of all U(S)ARTs instances
Table 8. USART implementation
+------------------------------------+--------------+-------------+
| features⁽¹⁾ | USART1/2/3/6 | UART4/5/7/8 |
+====================================+==============+=============+
| Data Length | 7, 8 and 9 bits |
+------------------------------------+--------------+-------------+
| Hardware flow control for modem | X | X |
+------------------------------------+--------------+-------------+
| Continuous communication using DMA | X | X |
+------------------------------------+--------------+-------------+
| Multiprocessor communication | X | X |
+------------------------------------+--------------+-------------+
| Synchronous mode | X | - |
+------------------------------------+--------------+-------------+
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #44 ===
Table 8. USART implementation (continued)
+---------------------------------------+--------------+-------------+
| features⁽¹⁾ | USART1/2/3/6 | UART4/5/7/8 |
+=======================================+==============+=============+
| Smartcard mode | X | - |
+---------------------------------------+--------------+-------------+
| Single-wire half-duplex communication | X | X |
+---------------------------------------+--------------+-------------+
| IrDA SIR ENDEC block | X | X |
+---------------------------------------+--------------+-------------+
| LIN mode | X | X |
+---------------------------------------+--------------+-------------+
| Dual clock domain | X | X |
+---------------------------------------+--------------+-------------+
| Receiver timeout interrupt | X | X |
+---------------------------------------+--------------+-------------+
| Modbus communication | X | X |
+---------------------------------------+--------------+-------------+
| Auto baud rate detection | X | X |
+---------------------------------------+--------------+-------------+
| Driver Enable | X | X |
+---------------------------------------+--------------+-------------+
1. X: supported.
3.26 Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 54 Mbits/s,
SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be
served by the DMA controller.
Three standard I²S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I²S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
3.27 Serial audio interface (SAI)
The devices embed two serial audio interfaces.
The serial audio interface is based on two independent audio subblocks which can operate
as transmitter or receiver with their FIFO. Many audio protocols are supported by each
block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output,
supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be
configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #45 ===
SAI1 and SAI2 can be served by the DMA controller
3.28 SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main features of the SPDIFRX are the following:
• Up to 4 inputs available
• Automatic symbol rate detection
• Maximum symbol rate: 12.288 MHz
• Stereo stream from 32 to 192 kHz supported
• Supports Audio IEC-60958 and IEC-61937, consumer applications
• Parity bit management
• Communication using DMA for audio samples
• Communication using DMA for control and user channel information
• Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal is available, the SPDIFRX re-samples the incoming signal, decodes the
manchester stream, recognizes frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that is used to compute the exact sample rate for clock drift algorithms.
3.29 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I²S and SAI applications. It allows
to achieve error-free I²S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I²S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I²S/SAI flow with an external PLL (or Codec output).
3.30 Audio and LCD PLL (PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #46 ===
3.31 SD/SDIO/MMC card host interface (SDMMC)
SDMMC host interfaces are available, that support the MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDMMC Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a
stack of MMC4.1 or previous.
The SDMMC can be served by the DMA controller
3.32 Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and
group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #47 ===
3.33 Controller area network (bxCAN)
The three CANs are compliant with the 2.0A and B (active) specifications with a bit rate up
to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for CAN1 and CAN2. 512 bytes of SRAM
are dedicated for CAN3.
3.34 Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
• 12 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Battery Charging Specification Revision 1.2 support
• Internal FS OTG PHY support
• HNP/SNP/IP inside (no need for any external resistor)
For the OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.35 Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed a USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 Mbit/s) and features a UTMI low-pin interface
(ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 8 bidirectional endpoints
• 16 host channels with periodic OUT support
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #48 ===
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Battery Charging Specification Revision 1.2 support
• Internal FS OTG PHY support
• External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.36 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.37 Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbytes/s in 8-bit mode at 54 MHz. It
features:
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports continuous mode or snapshot (a single frame) mode
• Capability to automatically crop the image
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #49 ===
3.38 Management Data Input/Output (MDIO) slaves
The devices embed a MDIO slave interface it includes the following features:
• 32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
– 32 x 16-bit firmware read/write, MDIO read-only output data registers
– 32 x 16-bit firmware read-only, MDIO write-only input data registers
• Configurable slave (port) address
• Independently maskable interrupts/events:
– MDIO Register write
– MDIO Register read
– MDIO protocol error
• Able to operate in and wake up from STOP mode
3.39 Random number generator (RNG)
All the devices embed an RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.
3.40 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
A fast I/O handling allows a maximum I/O toggling up to 108 MHz.
3.41 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #50 ===
3.42 Digital filter for Sigma-Delta Modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM
peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to
perform digital filtering of the received data streams (which represent analog value on Σ∆
modulators inputs). The DFSDM can also interface PDM (Pulse Density Modulation)
microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM
features optional parallel data stream inputs from microcontrollers memory (through
DMA/CPU transfers into DFSDM). The DFSDM transceivers support several serial interface
formats (to support various Σ∆ modulators). The DFSDM digital filter modules perform
digital processing according user selected filter parameters with up to 24-bit final ADC
resolution.
The DFSDM peripheral supports:
• 8 multiplexed input digital serial channels:
– Configurable SPI interface to connect various SD modulator(s)
– Configurable Manchester coded 1 wire interface support
– PDM (Pulse Density Modulation) microphone input support
– Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– Clock output for SD modulator(s): 0..20 MHz
• Alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
– internal sources: device memory data streams (DMA)
• 4 digital filter modules with adjustable digital signal processing:
– Sincxfilter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– integrator: oversampling ratio (1..256)
• Up to 24-bit output data resolution, signed output data format
• Automatic data offset correction (offset stored in register by user)
• Continuous or single conversion
• Start-of-conversion triggered by:
– Software trigger
– Internal timers
– External events
– Start-of-conversion synchronously with first digital filter module (DFSDM0)
• Analog watchdog feature:
– Low value and high value data threshold registers
– Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– Input from final output data or from selected input digital serial channels
– Continuous monitoring independently from standard conversion
• Short circuit detector to detect saturated analog input values (bottom and top range):
– Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
– Monitoring continuously each input serial channel
• Break signal generation on analog watchdog event or on short circuit detector event
• Extremes detector:
– Storage of minimum and maximum values of final conversion data
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #51 ===
– Refreshed by software
• DMA capability to read the final conversion data
• Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
• “regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority
Table 9. DFSDM implementation
+------------------------------------------------------+--------+
| DFSDM features | DFSDM1 |
+======================================================+========+
| Number of filters: x (DFSDM_FLTx) | 4 |
+------------------------------------------------------+--------+
| Number of input transceivers/channels: y (DFSDM_CHy) | 8 |
+------------------------------------------------------+--------+
| Internal ADC parallel input support | - |
+------------------------------------------------------+--------+
| Number of external triggers (JEXTSEL size) | 32 |
+------------------------------------------------------+--------+
| ID register support | - |
+------------------------------------------------------+--------+
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #52 ===
3.43 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with the temperature.
The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.44 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
• Two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
3.45 Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins
could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.46 Embedded Trace Macrocell™
The Arm embedded trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F76xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview #53 ===
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
3.47 DSI Host (DSIHOST)
The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
These interfaces are as follows:
• LTDC interface:
– Used to transmit information in Video mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
– Through a customized for mode, this interface can be used to transmit information
in full bandwidth in the Adapted Command mode (DBI).
• APB slave interface:
– Allows the transmission of generic information in Command mode, and follows a
proprietary register interface.
– Can operate concurrently with either LTDC interface in either Video mode or
Adapted Command mode.
• Video mode pattern generator:
– Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli.
The DSI Host main features:
• Compliant with MIPI® Alliance standards
• Interface with MIPI® D-PHY
• Supports all commands defined in the MIPI® Alliance specification for DCS:
– Transmission of all Command mode packets through the APB interface
– Transmission of commands in low-power and high-speed during Video mode
• Supports up to two D-PHY data lanes
• Bidirectional communication and escape mode support through data lane 0
• Supports non-continuous clock in D-PHY clock lane for additional power saving
• Supports Ultra Low-power mode with PLL disabled
• ECC and Checksum capabilities
• Support for End of Transmission Packet (EoTp)
• Fault recovery schemes
• 3D transmission support
• Configurable selection of system interfaces:
– AMBA APB for control and optional support for Generic and DCS commands
– Video Mode interface through LTDC
– Adapted Command mode interface through LTDC
• Independently programmable Virtual Channel ID in
=== Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #54 ===
– Video mode
– Adapted Command mode
– APB Slave
Video Mode interfaces features:
• LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB
• Programmable polarity of all LTDC interface signals
• Maximum resolution is limited by available DSI physical link bandwidth:
– Number of lanes: 2
– Maximum speed per lane: 500 Mbps1Gbps
Adapted interface features
Support for sending large amounts of data through the memory_write_start(WMS) and
memory_write_continue(WMC) DCS commands
• LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB
Video mode pattern generator:
• Vertical and horizontal color bar generation without LTDC stimuli
• BER pattern without LTDC stimuli
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #55 ===
4 Pinouts and pin description
Figure 11. STM32F76xxx LQFP100 pinout
1. The above figure shows the package top view.
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #56 ===
Figure 12. STM32F76xxx TFBGA100 pinout
1. The above figure shows the package top view.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #57 ===
Figure 13. STM32F76xxx LQFP144 pinout
1. The above figure shows the package top view.
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #58 ===
Figure 14. STM32F76xxx LQFP176 pinout
1. The above figure shows the package top view.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #59 ===
Figure 15. STM32F769xx LQFP176 pinout
1. The above figure shows the package top view.
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #60 ===
Figure 16. STM32F76xxx UFBGA176 ballout
1. The above figure shows the package top view.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #61 ===
Figure 17. STM32F769Ax/STM32F768Ax WLCSP180 ballout
1. NC ball must not be connected to GND nor to VDD.
2. The above figure shows the package top view.
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #62 ===
Figure 18. STM32F76xxx LQFP208 pinout
1. The above figure shows the package top view.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #63 ===
Figure 19. STM32F769xx LQFP208 pinout
1. The above figure shows the package top view.
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #64 ===
Figure 20. STM32F76xxx TFBGA216 ballout
1. The above figure shows the package top view.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #65 ===
Figure 21. STM32F769xx TFBGA216 ballout
1. The above figure shows the package top view.
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #66 ===
Table 10. Legend/abbreviations used in the pinout table
+---------------+------------------------------+-------------------------------------------------------------------+
| Name | Abbreviation | Definition |
+===============+==============================+===================================================================+
| Pin name | Unless otherwise specified in brackets below the pin name, the pin function during and after |
| | reset is the same as the actual pin name |
+---------------+------------------------------+-------------------------------------------------------------------+
| Pin type | S | Supply pin |
| +------------------------------+-------------------------------------------------------------------+
| | I | Input only pin |
| +------------------------------+-------------------------------------------------------------------+
| | I/O | Input / output pin |
+---------------+------------------------------+-------------------------------------------------------------------+
| I/O structure | FT | 5 V tolerant I/O |
| +------------------------------+-------------------------------------------------------------------+
| | TTa | 3.3 V tolerant I/O directly connected to ADC |
| +------------------------------+-------------------------------------------------------------------+
| | B | Dedicated BOOT pin |
| +------------------------------+-------------------------------------------------------------------+
| | RST | Bidirectional reset pin with weak pull-up resistor |
+---------------+------------------------------+-------------------------------------------------------------------+
| Notes | Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset |
+---------------+--------------------------------------------------------------------------------------------------+
| Alternate | Functions selected through GPIOx_AFR registers |
| functions | |
+---------------+--------------------------------------------------------------------------------------------------+
| Additional | Functions directly selected/enabled through peripheral registers |
| functions | |
+---------------+--------------------------------------------------------------------------------------------------+
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions
+-------------------------------------------------+-----+-----+----+---+------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+------------------------------+------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+---+---+----+---+---+----+-----+---+---+----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+---+---+----+---+---+----+-----+---+---+----+-----+-----+----+---+------------------------+------------+
| A3 | 1 | 1 | A2 | 1 | 1 | A3 | E10 | 1 | 1 | A3 | PE2 | I/O | FT | - | TRACECLK, SPI4_SCK, | - |
| | | | | | | | | | | | | | | | SAI1_MCLK_A, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO2, | |
| | | | | | | | | | | | | | | | ETH_MII_TXD3, FMC_A23, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+---+---+----+---+---+----+-----+---+---+----+-----+-----+----+---+------------------------+------------+
| B3 | 2 | 2 | A1 | 2 | 2 | A2 | F10 | 2 | 2 | A2 | PE3 | I/O | FT | - | TRACED0, SAI1_SD_B, | - |
| | | | | | | | | | | | | | | | FMC_A19, EVENTOUT | |
+----+---+---+----+---+---+----+-----+---+---+----+-----+-----+----+---+------------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #67 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+-----------------------------------------------------+----------+-----+----+-----+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+--------------------------------+--------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+---+---+----+----+----+----+-----+----+----+----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| C3 | 3 | 3 | B1 | 3 | 3 | A1 | C12 | 3 | 3 | A1 | PE4 | I/O | FT | - | TRACED1, SPI4_NSS, | - |
| | | | | | | | | | | | | | | | SAI1_FS_A, | |
| | | | | | | | | | | | | | | | DFSDM1_DATIN3, FMC_A20, | |
| | | | | | | | | | | | | | | | DCMI_D4, LCD_B0, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| D3 | 4 | 4 | B2 | 4 | 4 | B1 | D12 | 4 | 4 | B1 | PE5 | I/O | FT | - | TRACED2, TIM9_CH1, | - |
| | | | | | | | | | | | | | | | SPI4_MISO, SAI1_SCK_A, | |
| | | | | | | | | | | | | | | | DFSDM1_CKIN3, FMC_A21, | |
| | | | | | | | | | | | | | | | DCMI_D6, LCD_G0, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| E3 | 5 | 5 | B3 | 5 | 5 | B2 | E11 | 5 | 5 | B2 | PE6 | I/O | FT | - | TRACED3, TIM1_BKIN2, | - |
| | | | | | | | | | | | | | | | TIM9_CH2, SPI4_MOSI, | |
| | | | | | | | | | | | | | | | SAI1_SD_A, SAI2_MCLK_B, | |
| | | | | | | | | | | | | | | | FMC_A22, DCMI_D7, | |
| | | | | | | | | | | | | | | | LCD_G1, EVENTOUT | |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| - | - | - | - | - | - | G6 | - | - | - | G6 | VSS | S | - | - | - | - |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| - | - | - | - | - | - | F5 | - | - | - | F5 | VDD | S | - | - | - | - |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| B2 | 6 | 6 | C1 | 6 | 6 | C1 | C13 | 6 | 6 | C1 | VBAT | S | - | - | - | - |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| - | - | - | D2 | 7 | 7 | C2 | NC | 7 | 7 | C2 | PI8 | I/O | FT | (2) | EVENTOUT | RTC_TAMP2/ |
| | | | | | | | | | | | | | | | | RTC_TS/ |
| | | | | | | | | | | | | | | | | WKUP5 |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| A2 | 7 | 7 | D1 | 8 | 8 | D1 | D13 | 8 | 8 | D1 | PC13 | I/O | FT | (2) | EVENTOUT | RTC_TAMP1/ |
| | | | | | | | | | | | | | | | | RTC_TS/ |
| | | | | | | | | | | | | | | | | RTC_OUT/ |
| | | | | | | | | | | | | | | | | WKUP4 |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| A1 | 8 | 8 | E1 | 9 | 9 | E1 | E12 | 9 | 9 | E1 | PC14- | I/O | FT | (2) | EVENTOUT | OSC32_IN |
| | | | | | | | | | | | OSC32_IN | | | (3) | | |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| B1 | 9 | 9 | F1 | 10 | 10 | F1 | E13 | 10 | 10 | F1 | PC15- | I/O | FT | (2) | EVENTOUT | OSC32_OUT |
| | | | | | | | | | | | OSC32_O | | | (3) | | |
| | | | | | | | | | | | UT | | | | | |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| - | - | - | - | - | - | G5 | - | - | - | G5 | VDD | S | - | - | - | - |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| - | - | - | D3 | 11 | 11 | E4 | G10 | 11 | 11 | E4 | PI9 | I/O | FT | - | UART4_RX, CAN1_RX, | - |
| | | | | | | | | | | | | | | | FMC_D30, LCD_VSYNC, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| - | - | - | E3 | 12 | 12 | D5 | H10 | 12 | 12 | D5 | PI10 | I/O | FT | - | ETH_MII_RX_ER, FMC_D31, | - |
| | | | | | | | | | | | | | | | LCD_HSYNC, EVENTOUT | |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| - | - | - | E4 | 13 | 13 | F3 | F11 | 13 | 13 | F3 | PI11 | I/O | FT | - | LCD_G6, OTG_HS_ULPI_DIR, | WKUP6 |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
| - | - | - | F2 | 14 | 14 | F2 | F13 | 14 | 14 | F2 | VSS | S | - | - | - | - |
+----+---+---+----+----+----+----+-----+----+----+----+----------+-----+----+-----+--------------------------+------------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #68 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+-------------------------------------------------------+--------+-----+----+-----+------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+----------------------------------+--------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+----+----+----+----+----+-----+----+----+----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | - | F3 | 15 | 15 | F4 | F12 | 15 | 15 | F4 | VDD | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 10 | E2 | 16 | 16 | D2 | G11 | 16 | 16 | D2 | PF0 | I/O | FT | - | I2C2_SDA, FMC_A0, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 11 | H3 | 17 | 17 | E2 | G12 | 17 | 17 | E2 | PF1 | I/O | FT | - | I2C2_SCL, FMC_A1, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 12 | H2 | 18 | 18 | G2 | G13 | 18 | 18 | G2 | PF2 | I/O | FT | - | I2C2_SMBA, FMC_A2, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | - | - | - | 19 | E3 | NC | - | 19 | E3 | PI12 | I/O | FT | - | LCD_HSYNC, EVENTOUT | - |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | - | - | - | 20 | G3 | NC | - | 20 | G3 | PI13 | I/O | FT | - | LCD_VSYNC, EVENTOUT | - |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | - | - | - | 21 | H3 | NC | - | 21 | H3 | PI14 | I/O | FT | - | LCD_CLK, EVENTOUT | - |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 13 | J2 | 19 | 22 | H2 | H11 | 19 | 22 | H2 | PF3 | I/O | FT | - | FMC_A3, EVENTOUT | ADC3_IN9 |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 14 | J3 | 20 | 23 | J2 | H12 | 20 | 23 | J2 | PF4 | I/O | FT | - | FMC_A4, EVENTOUT | ADC3_IN14 |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 15 | K3 | 21 | 24 | K3 | H13 | 21 | 24 | K3 | PF5 | I/O | FT | - | FMC_A5, EVENTOUT | ADC3_IN15 |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| C2 | 10 | 16 | G2 | 22 | 25 | H6 | J13 | 22 | 25 | H6 | VSS | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| D2 | 11 | 17 | G3 | 23 | 26 | H5 | J12 | 23 | 26 | H5 | VDD | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 18 | K2 | 24 | 27 | K2 | NC | 24 | 27 | K2 | PF6 | I/O | FT | - | TIM10_CH1, SPI5_NSS, | ADC3_IN4 |
| | | | | | | | | | | | | | | | SAI1_SD_B, UART7_RX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO3, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 19 | K1 | 25 | 28 | K1 | NC | 25 | 28 | K1 | PF7 | I/O | FT | - | TIM11_CH1, SPI5_SCK, | ADC3_IN5 |
| | | | | | | | | | | | | | | | SAI1_MCLK_B, UART7_TX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO2, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 20 | L3 | 26 | 29 | L3 | NC | 26 | 29 | L3 | PF8 | I/O | FT | - | SPI5_MISO, SAI1_SCK_B, | ADC3_IN6 |
| | | | | | | | | | | | | | | | UART7_RTS, TIM13_CH1, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO0, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 21 | L2 | 27 | 30 | L2 | NC | 27 | 30 | L2 | PF9 | I/O | FT | - | SPI5_MOSI, SAI1_FS_B, | ADC3_IN7 |
| | | | | | | | | | | | | | | | UART7_CTS, TIM14_CH1, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO1, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| - | - | 22 | L1 | 28 | 31 | L1 | K11 | 28 | 31 | L1 | PF10 | I/O | FT | - | QUADSPI_CLK, DCMI_D11, | ADC3_IN8 |
| | | | | | | | | | | | | | | | LCD_DE, EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
| C1 | 12 | 23 | G1 | 29 | 32 | G1 | K12 | 29 | 32 | G1 | PH0- | I/O | FT | (3) | EVENTOUT | OSC_IN |
| | | | | | | | | | | | OSC_IN | | | | | |
+----+----+----+----+----+----+----+-----+----+----+----+--------+-----+----+-----+------------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #69 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+-------------------------------------------------------+---------+-----+----+-----+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+----------------------------------+--------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+----+----+----+----+----+-----+----+----+----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| D1 | 13 | 24 | H1 | 30 | 33 | H1 | K13 | 30 | 33 | H1 | PH1- | I/O | FT | (3) | EVENTOUT | OSC_OUT |
| | | | | | | | | | | | OSC_OUT | | | | | |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| E1 | 14 | 25 | J1 | 31 | 34 | J1 | L11 | 31 | 34 | J1 | NRST | I/O | RS | - | - | - |
| | | | | | | | | | | | | | T | | | |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| F1 | 15 | 26 | M2 | 32 | 35 | M2 | L12 | 32 | 35 | M2 | PC0 | I/O | FT | - | DFSDM1_CKIN0, | ADC1_IN10, |
| | | | | | | | | | | | | | | | DFSDM1_DATIN4, | ADC2_IN10, |
| | | | | | | | | | | | | | | | SAI2_FS_B, | ADC3_IN10 |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_STP, | |
| | | | | | | | | | | | | | | | FMC_SDNWE, LCD_R5, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| F2 | 16 | 27 | M3 | 33 | 36 | M3 | L13 | 33 | 36 | M3 | PC1 | I/O | FT | - | TRACED0, DFSDM1_DATIN0, | ADC1_IN11, |
| | | | | | | | | | | | | | | | SPI2_MOSI/I2S2_SD, | ADC2_IN11, |
| | | | | | | | | | | | | | | | SAI1_SD_A, DFSDM1_CKIN4, | ADC3_IN11, |
| | | | | | | | | | | | | | | | ETH_MDC, MDIOS_MDC, | RTC_TAMP3/ |
| | | | | | | | | | | | | | | | EVENTOUT | WKUP3 |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| E2 | 17 | 28 | M4 | 34 | 37 | M4 | NC | 34 | 37 | M4 | PC2 | I/O | FT | - | DFSDM1_CKIN1, SPI2_MISO, | ADC1_IN12, |
| | | | | | | | | | | | | | | | DFSDM1_CKOUT, | ADC2_IN12, |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_DIR, | ADC3_IN12 |
| | | | | | | | | | | | | | | | ETH_MII_TXD2, FMC_SDNE0, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| F3 | 18 | 29 | M5 | 35 | 38 | L4 | NC | 35 | 38 | L4 | PC3 | I/O | FT | - | DFSDM1_DATIN1, | ADC1_IN13, |
| | | | | | | | | | | | | | | | SPI2_MOSI/I2S2_SD, | ADC2_IN13, |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_NXT, | ADC3_IN13 |
| | | | | | | | | | | | | | | | ETH_MII_TX_CLK, | |
| | | | | | | | | | | | | | | | FMC_SDCKE0, EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| - | - | 30 | - | 36 | 39 | J5 | - | 36 | 39 | J5 | VDD | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| - | - | - | - | - | - | J6 | - | - | - | J6 | VSS | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| G1 | 19 | 31 | M1 | 37 | 40 | M1 | M11 | 37 | 40 | M1 | VSSA | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| - | - | - | N1 | - | - | N1 | - | - | - | N1 | VREF- | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| - | 20 | 32 | P1 | 38 | 41 | P1 | - | 38 | 41 | P1 | VREF+ | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| H1 | 21 | 33 | R1 | 39 | 42 | R1 | M12 | 39 | 42 | R1 | VDDA | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
| G2 | 22 | 34 | N3 | 40 | 43 | N3 | M13 | 40 | 43 | N3 | PA0- | I/O | FT | (4) | TIM2_CH1/TIM2_ETR, | ADC1_IN0, |
| | | | | | | | | | | | WKUP | | | | TIM5_CH1, TIM8_ETR, | ADC2_IN0, |
| | | | | | | | | | | | | | | | USART2_CTS, UART4_TX, | ADC3_IN0, |
| | | | | | | | | | | | | | | | SAI2_SD_B, ETH_MII_CRS, | WKUP1 |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+---------+-----+----+-----+--------------------------+------------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #70 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+--------------------------------------------------------+---------+-----+-----+---+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+----------------------------------+---------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+----+----+----+----+----+------+----+----+----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| H2 | 23 | 35 | N2 | 41 | 44 | N2 | J11 | 41 | 44 | N2 | PA1 | I/O | FT | - | TIM2_CH2, TIM5_CH2, | ADC1_IN1, |
| | | | | | | | | | | | | | | | USART2_RTS, UART4_RX, | ADC2_IN1, |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO3, | ADC3_IN1 |
| | | | | | | | | | | | | | | | SAI2_MCLK_B, | |
| | | | | | | | | | | | | | | | ETH_MII_RX_CLK/ETH_RMII_ | |
| | | | | | | | | | | | | | | | REF_CLK, LCD_R2, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| J2 | 24 | 36 | P2 | 42 | 45 | P2 | J10 | 42 | 45 | P2 | PA2 | I/O | FT | - | TIM2_CH3, TIM5_CH3, | ADC1_IN2, |
| | | | | | | | | | | | | | | | TIM9_CH1, USART2_TX, | ADC2_IN2, |
| | | | | | | | | | | | | | | | SAI2_SCK_B, ETH_MDIO, | ADC3_IN2, |
| | | | | | | | | | | | | | | | MDIOS_MDIO, LCD_R1, | WKUP2 |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| - | - | - | F4 | 43 | 46 | K4 | L10 | 43 | 46 | K4 | PH2 | I/O | FT | - | LPTIM1_IN2, | - |
| | | | | | | | | | | | | | | | QUADSPI_BK2_IO0, | |
| | | | | | | | | | | | | | | | SAI2_SCK_B, ETH_MII_CRS, | |
| | | | | | | | | | | | | | | | FMC_SDCKE0, LCD_R0, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| - | - | - | G4 | 44 | 47 | J4 | K10 | 44 | 47 | J4 | PH3 | I/O | FT | - | QUADSPI_BK2_IO1, | - |
| | | | | | | | | | | | | | | | SAI2_MCLK_B, | |
| | | | | | | | | | | | | | | | ETH_MII_COL, FMC_SDNE0, | |
| | | | | | | | | | | | | | | | LCD_R1, EVENTOUT | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| - | - | - | H4 | 45 | 48 | H4 | N12 | 45 | 48 | H4 | PH4 | I/O | FT | - | I2C2_SCL, LCD_G5, | - |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_NXT, LCD_G4, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| - | - | - | J4 | 46 | 49 | J3 | N11 | 46 | 49 | J3 | PH5 | I/O | FT | - | I2C2_SDA, SPI5_NSS, | - |
| | | | | | | | | | | | | | | | FMC_SDNWE, EVENTOUT | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| K2 | 25 | 37 | R2 | 47 | 50 | R2 | M10 | 47 | 50 | R2 | PA3 | I/O | FT | - | TIM2_CH4, TIM5_CH4, | ADC1_IN3, |
| | | | | | | | | | | | | | | | TIM9_CH2, USART2_RX, | ADC2_IN3, |
| | | | | | | | | | | | | | | | LCD_B2, OTG_HS_ULPI_D0, | ADC3_IN3 |
| | | | | | | | | | | | | | | | ETH_MII_COL, LCD_B5, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| J1 | 26 | 38 | - | - | 51 | K6 | J9 | - | 51 | K6 | VSS | S | - | - | - | - |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| E6 | - | - | L4 | 48 | - | L5 | -(5) | 48 | - | L5 | BYPASS_ | I | FT | - | - | - |
| | | | | | | | | | | | REG | | | | | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| K1 | 27 | 39 | K4 | 49 | 52 | K5 | K9 | 49 | 52 | K5 | VDD | S | - | - | - | - |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
| G3 | 28 | 40 | N4 | 50 | 53 | N4 | L9 | 50 | 53 | N4 | PA4 | I/O | TTa | - | SPI1_NSS/I2S1_WS, | ADC1_IN4, |
| | | | | | | | | | | | | | | | SPI3_NSS/I2S3_WS, | ADC2_IN4, |
| | | | | | | | | | | | | | | | USART2_CK, SPI6_NSS, | DAC_OUT1 |
| | | | | | | | | | | | | | | | OTG_HS_SOF, DCMI_HSYNC, | |
| | | | | | | | | | | | | | | | LCD_VSYNC, EVENTOUT | |
+----+----+----+----+----+----+----+------+----+----+----+---------+-----+-----+---+--------------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #71 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+-------------------------------------------------------+-----+-----+-----+---+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+----------------------------------+--------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+----+----+----+----+----+-----+----+----+----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
| H3 | 29 | 41 | P4 | 51 | 54 | P4 | P11 | 51 | 54 | P4 | PA5 | I/O | TTa | - | TIM2_CH1/TIM2_ETR, | ADC1_IN5, |
| | | | | | | | | | | | | | | | TIM8_CH1N, | ADC2_IN5, |
| | | | | | | | | | | | | | | | SPI1_SCK/I2S1_CK, | DAC_OUT2 |
| | | | | | | | | | | | | | | | SPI6_SCK, | |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_CK, LCD_R4, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
| J3 | 30 | 42 | P3 | 52 | 55 | P3 | N10 | 52 | 55 | P3 | PA6 | I/O | FT | - | TIM1_BKIN, TIM3_CH1, | ADC1_IN6, |
| | | | | | | | | | | | | | | | TIM8_BKIN, SPI1_MISO, | ADC2_IN6 |
| | | | | | | | | | | | | | | | SPI6_MISO, TIM13_CH1, | |
| | | | | | | | | | | | | | | | MDIOS_MDC, DCMI_PIXCLK, | |
| | | | | | | | | | | | | | | | LCD_G2, EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
| K3 | 31 | 43 | R3 | 53 | 56 | R3 | M9 | 53 | 56 | R3 | PA7 | I/O | FT | - | TIM1_CH1N, TIM3_CH2, | ADC1_IN7, |
| | | | | | | | | | | | | | | | TIM8_CH1N, | ADC2_IN7 |
| | | | | | | | | | | | | | | | SPI1_MOSI/I2S1_SD, | |
| | | | | | | | | | | | | | | | SPI6_MOSI, TIM14_CH1, | |
| | | | | | | | | | | | | | | | ETH_MII_RX_DV/ETH_RMII_C | |
| | | | | | | | | | | | | | | | RS_DV, FMC_SDNWE, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
| G4 | 32 | 44 | N5 | 54 | 57 | N5 | NC | 54 | 57 | N5 | PC4 | I/O | FT | - | DFSDM1_CKIN2, I2S1_MCK, | ADC1_IN14, |
| | | | | | | | | | | | | | | | SPDIF_RX2, | ADC2_IN14 |
| | | | | | | | | | | | | | | | ETH_MII_RXD0/ETH_RMII_RX | |
| | | | | | | | | | | | | | | | D0, FMC_SDNE0, EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
| H4 | 33 | 45 | P5 | 55 | 58 | P5 | NC | 55 | 58 | P5 | PC5 | I/O | FT | - | DFSDM1_DATIN2, | ADC1_IN15, |
| | | | | | | | | | | | | | | | SPDIF_RX3, | ADC2_IN15 |
| | | | | | | | | | | | | | | | ETH_MII_RXD1/ETH_RMII_RX | |
| | | | | | | | | | | | | | | | D1, FMC_SDCKE0, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
| - | - | - | - | - | 59 | L7 | - | - | 59 | L7 | VDD | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
| - | - | - | - | - | 60 | L6 | - | - | 60 | L6 | VSS | S | - | - | - | - |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
| J4 | 34 | 46 | R5 | 56 | 61 | R5 | P10 | 56 | 61 | R5 | PB0 | I/O | FT | - | TIM1_CH2N, TIM3_CH3, | ADC1_IN8, |
| | | | | | | | | | | | | | | | TIM8_CH2N, | ADC2_IN8 |
| | | | | | | | | | | | | | | | DFSDM1_CKOUT, | |
| | | | | | | | | | | | | | | | UART4_CTS, LCD_R3, | |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_D1, | |
| | | | | | | | | | | | | | | | ETH_MII_RXD2, LCD_G1, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
| K4 | 35 | 47 | R4 | 57 | 62 | R4 | J8 | 57 | 62 | R4 | PB1 | I/O | FT | - | TIM1_CH3N, TIM3_CH4, | ADC1_IN9, |
| | | | | | | | | | | | | | | | TIM8_CH3N, | ADC2_IN9 |
| | | | | | | | | | | | | | | | DFSDM1_DATIN1, LCD_R6, | |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_D2, | |
| | | | | | | | | | | | | | | | ETH_MII_RXD3, LCD_G0, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+-----+----+----+----+-----+-----+-----+---+--------------------------+------------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #72 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+------------------------------------------------------+------+-----+----+---+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+----------------------------------+-------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+----+----+----+----+----+----+----+----+----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| G5 | 36 | 48 | M6 | 58 | 63 | M5 | J7 | 58 | 63 | M5 | PB2 | I/O | FT | - | SAI1_SD_A, | - |
| | | | | | | | | | | | | | | | SPI3_MOSI/I2S3_SD, | |
| | | | | | | | | | | | | | | | QUADSPI_CLK, | |
| | | | | | | | | | | | | | | | DFSDM1_CKIN1, EVENTOUT | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 64 | G4 | NC | - | 64 | G4 | PI15 | I/O | FT | - | LCD_G2, LCD_R0, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 65 | R6 | NC | - | 65 | R6 | PJ0 | I/O | FT | - | LCD_R7, LCD_R1, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 66 | R7 | NC | - | 66 | R7 | PJ1 | I/O | FT | - | LCD_R2, EVENTOUT | - |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 67 | P7 | NC | - | 67 | P7 | PJ2 | I/O | FT | - | DSI_TE, LCD_R3, EVENTOUT | - |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 68 | N8 | NC | - | 68 | N8 | PJ3 | I/O | FT | - | LCD_R4, EVENTOUT | - |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 69 | M9 | NC | - | 69 | M9 | PJ4 | I/O | FT | - | LCD_R5, EVENTOUT | - |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | 49 | R6 | 59 | 70 | P8 | N9 | 59 | 70 | P8 | PF11 | I/O | FT | - | SPI5_MOSI, SAI2_SD_B, | - |
| | | | | | | | | | | | | | | | FMC_SDNRAS, DCMI_D12, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | 50 | P6 | 60 | 71 | M6 | K7 | 60 | 71 | M6 | PF12 | I/O | FT | - | FMC_A6, EVENTOUT | - |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | 51 | M8 | 61 | 72 | K7 | P9 | 61 | 72 | K7 | VSS | S | - | - | - | - |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | 52 | N8 | 62 | 73 | L8 | M8 | 62 | 73 | L8 | VDD | S | - | - | - | - |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | 53 | N6 | 63 | 74 | N6 | L8 | 63 | 74 | N6 | PF13 | I/O | FT | - | I2C4_SMBA, | - |
| | | | | | | | | | | | | | | | DFSDM1_DATIN6, FMC_A7, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | 54 | R7 | 64 | 75 | P6 | K8 | 64 | 75 | P6 | PF14 | I/O | FT | - | I2C4_SCL, DFSDM1_CKIN6, | - |
| | | | | | | | | | | | | | | | FMC_A8, EVENTOUT | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | 55 | P7 | 65 | 76 | M8 | P8 | 65 | 76 | M8 | PF15 | I/O | FT | - | I2C4_SDA, FMC_A9, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | 56 | N7 | 66 | 77 | N7 | N8 | 66 | 77 | N7 | PG0 | I/O | FT | - | FMC_A10, EVENTOUT | - |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| - | - | 57 | M7 | 67 | 78 | M7 | L7 | 67 | 78 | M7 | PG1 | I/O | FT | - | FMC_A11, EVENTOUT | - |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| H5 | 37 | 58 | R8 | 68 | 79 | R8 | M7 | 68 | 79 | R8 | PE7 | I/O | FT | - | TIM1_ETR, DFSDM1_DATIN2, | - |
| | | | | | | | | | | | | | | | UART7_RX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK2_IO0, FMC_D4, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
| J5 | 38 | 59 | P8 | 69 | 80 | N9 | N7 | 69 | 80 | N9 | PE8 | I/O | FT | - | TIM1_CH1N, DFSDM1_CKIN2, | - |
| | | | | | | | | | | | | | | | UART7_TX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK2_IO1, FMC_D5, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+----+----+----+----+----+----+----+----+------+-----+----+---+--------------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #73 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+---------------------------------------------------------+------+-----+----+---+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+------------------------------------+--------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+----+-----+----+----+-----+----+----+----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| K5 | 39 | 60 | P9 | 70 | 81 | P9 | P7 | 70 | 81 | P9 | PE9 | I/O | FT | - | TIM1_CH1, DFSDM1_CKOUT, | - |
| | | | | | | | | | | | | | | | UART7_RTS, | |
| | | | | | | | | | | | | | | | QUADSPI_BK2_IO2, FMC_D6, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| - | - | 61 | M9 | 71 | 82 | K8 | - | 71 | 82 | K8 | VSS | S | - | - | - | - |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| - | - | 62 | N9 | 72 | 83 | L9 | - | 72 | 83 | L9 | VDD | S | - | - | - | - |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| G6 | 40 | 63 | R9 | 73 | 84 | R9 | J6 | 73 | 84 | R9 | PE10 | I/O | FT | - | TIM1_CH2N, | - |
| | | | | | | | | | | | | | | | DFSDM1_DATIN4, | |
| | | | | | | | | | | | | | | | UART7_CTS, | |
| | | | | | | | | | | | | | | | QUADSPI_BK2_IO3, FMC_D7, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| H6 | 41 | 64 | P10 | 74 | 85 | P10 | K6 | 74 | 85 | P10 | PE11 | I/O | FT | - | TIM1_CH2, SPI4_NSS, | - |
| | | | | | | | | | | | | | | | DFSDM1_CKIN4, SAI2_SD_B, | |
| | | | | | | | | | | | | | | | FMC_D8, LCD_G3, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| J6 | 42 | 65 | R10 | 75 | 86 | R10 | L6 | 75 | 86 | R10 | PE12 | I/O | FT | - | TIM1_CH3N, SPI4_SCK, | - |
| | | | | | | | | | | | | | | | DFSDM1_DATIN5, | |
| | | | | | | | | | | | | | | | SAI2_SCK_B, FMC_D9, | |
| | | | | | | | | | | | | | | | LCD_B4, EVENTOUT | |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| K6 | 43 | 66 | N11 | 76 | 87 | R12 | P6 | 76 | 87 | R12 | PE13 | I/O | FT | - | TIM1_CH3, SPI4_MISO, | - |
| | | | | | | | | | | | | | | | DFSDM1_CKIN5, SAI2_FS_B, | |
| | | | | | | | | | | | | | | | FMC_D10, LCD_DE, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| G7 | 44 | 67 | P11 | 77 | 88 | P11 | N6 | 77 | 88 | P11 | PE14 | I/O | FT | - | TIM1_CH4, SPI4_MOSI, | - |
| | | | | | | | | | | | | | | | SAI2_MCLK_B, FMC_D11, | |
| | | | | | | | | | | | | | | | LCD_CLK, EVENTOUT | |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| H7 | 45 | 68 | R11 | 78 | 89 | R11 | M6 | 78 | 89 | R11 | PE15 | I/O | FT | - | TIM1_BKIN, FMC_D12, | - |
| | | | | | | | | | | | | | | | LCD_R7, EVENTOUT | |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
| J7 | 46 | 69 | R12 | 79 | 90 | P12 | K5 | 79 | 90 | P12 | PB10 | I/O | FT | - | TIM2_CH3, I2C2_SCL, | - |
| | | | | | | | | | | | | | | | SPI2_SCK/I2S2_CK, | |
| | | | | | | | | | | | | | | | DFSDM1_DATIN7, | |
| | | | | | | | | | | | | | | | USART3_TX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_NCS, | |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_D3, | |
| | | | | | | | | | | | | | | | ETH_MII_RX_ER, LCD_G4, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+-----+----+----+-----+----+----+----+-----+------+-----+----+---+--------------------------+------------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #74 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+-----------------------------------------------------------+--------+-----+----+---+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+-------------------------------------+---------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| K7 | 47 | 70 | R13 | 80 | 91 | R13 | L5 | 80 | 91 | R13 | PB11 | I/O | FT | - | TIM2_CH4, I2C2_SDA, | - |
| | | | | | | | | | | | | | | | DFSDM1_CKIN7, | |
| | | | | | | | | | | | | | | | USART3_RX, | |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_D4, | |
| | | | | | | | | | | | | | | | ETH_MII_TX_EN/ETH_RMII_T | |
| | | | | | | | | | | | | | | | X_EN, DSI_TE, LCD_G5, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| F8 | 48 | 71 | M10 | 81 | 92 | L11 | P5 | 81 | 92 | L11 | VCAP_1 | S | - | - | - | - |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | 49 | - | - | - | 93 | K9 | N5 | - | 93 | K9 | VSS | S | - | - | - | - |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | 50 | 72 | N10 | 82 | 94 | L10 | P4 | 82 | 94 | L10 | VDD | S | - | - | - | - |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 95 | M14 | NC | - | 95 | M14 | PJ5 | I/O | FT | - | LCD_R6, EVENTOUT | - |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | M11 | 83 | 96 | P13 | NC | 83 | 96 | P13 | PH6 | I/O | FT | - | I2C2_SMBA, SPI5_SCK, | - |
| | | | | | | | | | | | | | | | TIM12_CH1, ETH_MII_RXD2, | |
| | | | | | | | | | | | | | | | FMC_SDNE1, DCMI_D8, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | N12 | 84 | 97 | N13 | NC | 84 | 97 | N13 | PH7 | I/O | FT | - | I2C3_SCL, SPI5_MISO, | - |
| | | | | | | | | | | | | | | | ETH_MII_RXD3, | |
| | | | | | | | | | | | | | | | FMC_SDCKE1, DCMI_D9, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | M12 | 85 | 98 | P14 | M5 | - | 98 | P14 | PH8 | I/O | FT | - | I2C3_SDA, FMC_D16, | - |
| | | | | | | | | | | | | | | | DCMI_HSYNC, LCD_R2, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | M13 | 86 | 99 | N14 | K4 | - | 99 | N14 | PH9 | I/O | FT | - | I2C3_SMBA, TIM12_CH2, | - |
| | | | | | | | | | | | | | | | FMC_D17, DCMI_D0, | |
| | | | | | | | | | | | | | | | LCD_R3, EVENTOUT | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | L13 | 87 | 100 | P15 | L4 | - | 100 | P15 | PH10 | I/O | FT | - | TIM5_CH1, I2C4_SMBA, | - |
| | | | | | | | | | | | | | | | FMC_D18, DCMI_D1, | |
| | | | | | | | | | | | | | | | LCD_R4, EVENTOUT | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | L12 | 88 | 101 | N15 | M4 | - | 101 | N15 | PH11 | I/O | FT | - | TIM5_CH2, I2C4_SCL, | - |
| | | | | | | | | | | | | | | | FMC_D19, DCMI_D2, | |
| | | | | | | | | | | | | | | | LCD_R5, EVENTOUT | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | K12 | 89 | 102 | M15 | P3 | - | 102 | M15 | PH12 | I/O | FT | - | TIM5_CH3, I2C4_SDA, | - |
| | | | | | | | | | | | | | | | FMC_D20, DCMI_D3, | |
| | | | | | | | | | | | | | | | LCD_R6, EVENTOUT | |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | H12 | 90 | - | K10 | N4 | - | - | K10 | VSS | S | - | - | - | - |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
| - | - | - | J12 | 91 | 103 | K11 | - | - | 103 | K11 | VDD | S | - | - | - | - |
+----+----+----+-----+----+-----+-----+----+----+-----+-----+--------+-----+----+---+--------------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #75 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+------------------------------------------------------------+------+-----+----+---+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+--------------------------------------+---------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+------+-----+----+---+--------------------------+------------+
| K8 | 51 | 73 | P12 | 92 | 104 | L13 | H8 | 85 | 104 | L13 | PB12 | I/O | FT | - | TIM1_BKIN, I2C2_SMBA, | - |
| | | | | | | | | | | | | | | | SPI2_NSS/I2S2_WS, | |
| | | | | | | | | | | | | | | | DFSDM1_DATIN1, | |
| | | | | | | | | | | | | | | | USART3_CK, UART5_RX, | |
| | | | | | | | | | | | | | | | CAN2_RX, | |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_D5, | |
| | | | | | | | | | | | | | | | ETH_MII_TXD0/ETH_RMII_TX | |
| | | | | | | | | | | | | | | | D0, OTG_HS_ID, EVENTOUT | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+------+-----+----+---+--------------------------+------------+
| J8 | 52 | 74 | P13 | 93 | 105 | K14 | J5 | 86 | 105 | K14 | PB13 | I/O | FT | - | TIM1_CH1N, | OTG_HS_VB |
| | | | | | | | | | | | | | | | SPI2_SCK/I2S2_CK, | US |
| | | | | | | | | | | | | | | | DFSDM1_CKIN1, | |
| | | | | | | | | | | | | | | | USART3_CTS, UART5_TX, | |
| | | | | | | | | | | | | | | | CAN2_TX, OTG_HS_ULPI_D6, | |
| | | | | | | | | | | | | | | | ETH_MII_TXD1/ETH_RMII_TX | |
| | | | | | | | | | | | | | | | D1, EVENTOUT | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+------+-----+----+---+--------------------------+------------+
| H10 | 53 | 75 | R14 | 94 | 106 | R14 | N3 | 87 | 106 | R14 | PB14 | I/O | FT | - | TIM1_CH2N, TIM8_CH2N, | - |
| | | | | | | | | | | | | | | | USART1_TX, SPI2_MISO, | |
| | | | | | | | | | | | | | | | DFSDM1_DATIN2, | |
| | | | | | | | | | | | | | | | USART3_RTS, UART4_RTS, | |
| | | | | | | | | | | | | | | | TIM12_CH1, SDMMC2_D0, | |
| | | | | | | | | | | | | | | | OTG_HS_DM, EVENTOUT | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+------+-----+----+---+--------------------------+------------+
| G10 | 54 | 76 | R15 | 95 | 107 | R15 | N2 | 88 | 107 | R15 | PB15 | I/O | FT | - | RTC_REFIN, TIM1_CH3N, | - |
| | | | | | | | | | | | | | | | TIM8_CH3N, USART1_RX, | |
| | | | | | | | | | | | | | | | SPI2_MOSI/I2S2_SD, | |
| | | | | | | | | | | | | | | | DFSDM1_CKIN2, | |
| | | | | | | | | | | | | | | | UART4_CTS, TIM12_CH2, | |
| | | | | | | | | | | | | | | | SDMMC2_D1, OTG_HS_DP, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+------+-----+----+---+--------------------------+------------+
| K9 | 55 | 77 | P15 | 96 | 108 | L15 | M3 | 89 | 108 | L15 | PD8 | I/O | FT | - | DFSDM1_CKIN3, | - |
| | | | | | | | | | | | | | | | USART3_TX, SPDIF_RX1, | |
| | | | | | | | | | | | | | | | FMC_D13, EVENTOUT | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+------+-----+----+---+--------------------------+------------+
| J9 | 56 | 78 | P14 | 97 | 109 | L14 | L3 | 90 | 109 | L14 | PD9 | I/O | FT | - | DFSDM1_DATIN3, | - |
| | | | | | | | | | | | | | | | USART3_RX, FMC_D14, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+------+-----+----+---+--------------------------+------------+
| H9 | 57 | 79 | N15 | 98 | 110 | K15 | M2 | 91 | 110 | K15 | PD10 | I/O | FT | - | DFSDM1_CKOUT, | - |
| | | | | | | | | | | | | | | | USART3_CK, FMC_D15, | |
| | | | | | | | | | | | | | | | LCD_B3, EVENTOUT | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+------+-----+----+---+--------------------------+------------+
| G9 | 58 | 80 | N14 | 99 | 111 | N10 | K3 | 92 | 111 | N10 | PD11 | I/O | FT | - | I2C4_SMBA, USART3_CTS, | - |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO0, | |
| | | | | | | | | | | | | | | | SAI2_SD_A, | |
| | | | | | | | | | | | | | | | FMC_A16/FMC_CLE, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+----+-----+----+-----+-----+----+----+-----+-----+------+-----+----+---+--------------------------+------------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #76 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+--------------------------------------------------------------+----------+-----+----+---+-----------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+---------------------------------------+----------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| K10 | 59 | 81 | N13 | 100 | 112 | M10 | J4 | 93 | 112 | M10 | PD12 | I/O | FT | - | TIM4_CH1, LPTIM1_IN1, | - |
| | | | | | | | | | | | | | | | I2C4_SCL, USART3_RTS, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO1, | |
| | | | | | | | | | | | | | | | SAI2_FS_A, | |
| | | | | | | | | | | | | | | | FMC_A17/FMC_ALE, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| J10 | 60 | 82 | M15 | 101 | 113 | M11 | L2 | 94 | 113 | M11 | PD13 | I/O | FT | - | TIM4_CH2, LPTIM1_OUT, | - |
| | | | | | | | | | | | | | | | I2C4_SDA, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO3, | |
| | | | | | | | | | | | | | | | SAI2_SCK_A, FMC_A18, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | 83 | - | 102 | 114 | J10 | M1 | 95 | 114 | J10 | VSS | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | 84 | J13 | 103 | 115 | J11 | - | 96 | 115 | J11 | VDD | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| H8 | 61 | 85 | M14 | 104 | 116 | L12 | L1 | 97 | 116 | L12 | PD14 | I/O | FT | - | TIM4_CH3, UART8_CTS, | - |
| | | | | | | | | | | | | | | | FMC_D0, EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| G8 | 62 | 86 | L14 | 105 | 117 | K13 | K2 | 98 | 117 | K13 | PD15 | I/O | FT | - | TIM4_CH4, UART8_RTS, | - |
| | | | | | | | | | | | | | | | FMC_D1, EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | 118 | K12 | - | - | - | - | PJ6 | I/O | FT | - | LCD_R7, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | 119 | J12 | - | - | - | - | PJ7 | I/O | FT | - | LCD_G0, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | 120 | H12 | - | - | - | - | PJ8 | I/O | FT | - | LCD_G1, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | 121 | J13 | - | - | - | - | PJ9 | I/O | FT | - | LCD_G2, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | 122 | H13 | - | - | - | - | PJ10 | I/O | FT | - | LCD_G3, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | 123 | G12 | - | - | - | - | PJ11 | I/O | FT | - | LCD_G4, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | 124 | H11 | - | - | - | - | VDD | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | - | - | K1 | 99 | 118 | H11 | VDDDSI | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | 125 | H10 | - | - | - | H10 | VSS | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | - | - | H6 | 100 | 119 | K12 | VCAPDSI | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | - | - | J3 | - | - | G13 | VDD12DSI | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | - | - | J1 | 101 | 120 | J12 | DSI_D0P | I/O | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | - | - | J2 | 102 | 121 | J13 | DSI_D0N | I/O | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | - | - | H5 | 103 | 122 | G12 | VSSDSI | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
| - | - | - | - | - | - | - | H4 | 104 | 123 | H12 | DSI_CKP | I/O | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-----------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #77 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+--------------------------------------------------------------+----------+-----+----+---+-------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+---------------------------------------+----------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | - | - | - | - | - | H3 | 105 | 124 | H13 | DSI_CKN | I/O | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | - | - | - | - | - | - | 106 | 125 | - | VDD12DSI | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | - | - | - | - | - | H1 | 107 | 126 | F12 | DSI_D1P | I/O | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | - | - | - | - | - | H2 | 108 | 127 | F13 | DSI_D1N | I/O | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | - | - | - | - | - | - | 109 | 128 | - | VSSDSI | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | - | - | - | 126 | G13 | - | - | - | - | PK0 | I/O | FT | - | LCD_G5, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | - | - | - | 127 | F12 | - | - | - | - | PK1 | I/O | FT | - | LCD_G6, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | - | - | - | 128 | F13 | - | - | - | - | PK2 | I/O | FT | - | LCD_G7, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | 87 | L15 | 106 | 129 | M13 | H9 | 110 | 129 | M13 | PG2 | I/O | FT | - | FMC_A12, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | 88 | K15 | 107 | 130 | M12 | G9 | 111 | 130 | M12 | PG3 | I/O | FT | - | FMC_A13, EVENTOUT | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | 89 | K14 | 108 | 131 | N12 | G1 | 112 | 131 | N12 | PG4 | I/O | FT | - | FMC_A14/FMC_BA0, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | 90 | K13 | 109 | 132 | N11 | G2 | 113 | 132 | N11 | PG5 | I/O | FT | - | FMC_A15/FMC_BA1, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | 91 | J15 | 110 | 133 | J15 | G3 | 114 | 133 | J15 | PG6 | I/O | FT | - | FMC_NE3, DCMI_D12, | - |
| | | | | | | | | | | | | | | | LCD_R7, EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | 92 | J14 | 111 | 134 | J14 | G4 | 115 | 134 | J14 | PG7 | I/O | FT | - | SAI1_MCLK_A, USART6_CK, | - |
| | | | | | | | | | | | | | | | FMC_INT, DCMI_D13, | |
| | | | | | | | | | | | | | | | LCD_CLK, EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | 93 | H14 | 112 | 135 | H14 | G5 | 116 | 135 | H14 | PG8 | I/O | FT | - | SPI6_NSS, SPDIF_RX2, | - |
| | | | | | | | | | | | | | | | USART6_RTS, | |
| | | | | | | | | | | | | | | | ETH_PPS_OUT, FMC_SDCLK, | |
| | | | | | | | | | | | | | | | LCD_G7, EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| - | - | 94 | G12 | 113 | 136 | G10 | F1 | 117 | 136 | G10 | VSS | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| F6 | - | 95 | H13 | 114 | 137 | G11 | F2 | 118 | 137 | G11 | VDDUSB | S | - | - | - | - |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
| F10 | 63 | 96 | H15 | 115 | 138 | H15 | G6 | 119 | 138 | H15 | PC6 | I/O | FT | - | TIM3_CH1, TIM8_CH1, | - |
| | | | | | | | | | | | | | | | I2S2_MCK, DFSDM1_CKIN3, | |
| | | | | | | | | | | | | | | | USART6_TX, FMC_NWAIT, | |
| | | | | | | | | | | | | | | | SDMMC2_D6, SDMMC1_D6, | |
| | | | | | | | | | | | | | | | DCMI_D0, LCD_HSYNC, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+-------------------------+------------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #78 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+---------------------------------------------------------------+------+-----+----+---+---------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+----------------------------------------+----------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+------+-----+----+---+---------------------------+------------+
| E10 | 64 | 97 | G15 | 116 | 139 | G15 | F3 | 120 | 139 | G15 | PC7 | I/O | FT | - | TIM3_CH2, TIM8_CH2, | - |
| | | | | | | | | | | | | | | | I2S3_MCK, DFSDM1_DATIN3, | |
| | | | | | | | | | | | | | | | USART6_RX, FMC_NE1, | |
| | | | | | | | | | | | | | | | SDMMC2_D7, SDMMC1_D7, | |
| | | | | | | | | | | | | | | | DCMI_D1, LCD_G6, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+------+-----+----+---+---------------------------+------------+
| F9 | 65 | 98 | G14 | 117 | 140 | G14 | G8 | 121 | 140 | G14 | PC8 | I/O | FT | - | TRACED1, TIM3_CH3, | - |
| | | | | | | | | | | | | | | | TIM8_CH3, UART5_RTS, | |
| | | | | | | | | | | | | | | | USART6_CK, | |
| | | | | | | | | | | | | | | | FMC_NE2/FMC_NCE, | |
| | | | | | | | | | | | | | | | SDMMC1_D0, DCMI_D2, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+------+-----+----+---+---------------------------+------------+
| E9 | 66 | 99 | F14 | 118 | 141 | F14 | E1 | 122 | 141 | F14 | PC9 | I/O | FT | - | MCO2, TIM3_CH4, TIM8_CH4, | -- |
| | | | | | | | | | | | | | | | I2C3_SDA, I2S_CKIN, | |
| | | | | | | | | | | | | | | | UART5_CTS, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO0, LCD_G3, | |
| | | | | | | | | | | | | | | | SDMMC1_D1, DCMI_D3, | |
| | | | | | | | | | | | | | | | LCD_B2, EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+------+-----+----+---+---------------------------+------------+
| D9 | 67 | 100 | F15 | 119 | 142 | F15 | E2 | 123 | 142 | F15 | PA8 | I/O | FT | - | MCO1, TIM1_CH1, | - |
| | | | | | | | | | | | | | | | TIM8_BKIN2, I2C3_SCL, | |
| | | | | | | | | | | | | | | | USART1_CK, OTG_FS_SOF, | |
| | | | | | | | | | | | | | | | CAN3_RX, UART7_RX, | |
| | | | | | | | | | | | | | | | LCD_B3, LCD_R6, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+------+-----+----+---+---------------------------+------------+
| C9 | 68 | 101 | E15 | 120 | 143 | E15 | F4 | 124 | 143 | E15 | PA9 | I/O | FT | - | TIM1_CH2, I2C3_SMBA, | OTG_FS_VB |
| | | | | | | | | | | | | | | | SPI2_SCK/I2S2_CK, | US |
| | | | | | | | | | | | | | | | USART1_TX, DCMI_D0, | |
| | | | | | | | | | | | | | | | LCD_R5, EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+------+-----+----+---+---------------------------+------------+
| D10 | 69 | 102 | D15 | 121 | 144 | D15 | F5 | 125 | 144 | D15 | PA10 | I/O | FT | - | TIM1_CH3, USART1_RX, | - |
| | | | | | | | | | | | | | | | LCD_B4, OTG_FS_ID, | |
| | | | | | | | | | | | | | | | MDIOS_MDIO, DCMI_D1, | |
| | | | | | | | | | | | | | | | LCD_B1, EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+------+-----+----+---+---------------------------+------------+
| C10 | 70 | 103 | C15 | 122 | 145 | C15 | E3 | 126 | 145 | C15 | PA11 | I/O | FT | - | TIM1_CH4, | - |
| | | | | | | | | | | | | | | | SPI2_NSS/I2S2_WS, | |
| | | | | | | | | | | | | | | | UART4_RX, USART1_CTS, | |
| | | | | | | | | | | | | | | | CAN1_RX, OTG_FS_DM, | |
| | | | | | | | | | | | | | | | LCD_R4, EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+------+-----+----+---+---------------------------+------------+
| B10 | 71 | 104 | B15 | 123 | 146 | B15 | D1 | 127 | 146 | B15 | PA12 | I/O | FT | - | TIM1_ETR, | - |
| | | | | | | | | | | | | | | | SPI2_SCK/I2S2_CK, | |
| | | | | | | | | | | | | | | | UART4_TX, USART1_RTS, | |
| | | | | | | | | | | | | | | | SAI2_FS_B, CAN1_TX, | |
| | | | | | | | | | | | | | | | OTG_FS_DP, LCD_R5, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+------+-----+----+---+---------------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #79 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+---------------------------------------------------------------+----------+-----+----+---+----------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+----------------------------------------+----------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| A10 | 72 | 105 | A15 | 124 | 147 | A15 | D2 | 128 | 147 | A15 | PA13(JTM | I/O | FT | - | JTMS-SWDIO, EVENTOUT | - |
| | | | | | | | | | | | S-SWDIO) | | | | | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| E7 | 73 | 106 | F13 | 125 | 148 | E11 | C1 | 129 | 148 | E11 | VCAP_2 | S | - | - | - | - |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| E5 | 74 | 107 | F12 | 126 | 149 | F10 | C2 | 130 | 149 | F10 | VSS | S | - | - | - | - |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| F5 | 75 | 108 | G13 | 127 | 150 | F11 | B2 | 131 | 150 | F11 | VDD | S | - | - | - | - |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| - | - | - | E12 | 128 | 151 | E12 | F6 | - | 151 | E12 | PH13 | I/O | FT | - | TIM8_CH1N, UART4_TX, | - |
| | | | | | | | | | | | | | | | CAN1_TX, FMC_D21, | |
| | | | | | | | | | | | | | | | LCD_G2, EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| - | - | - | E13 | 129 | 152 | E13 | F7 | - | 152 | E13 | PH14 | I/O | FT | - | TIM8_CH2N, UART4_RX, | - |
| | | | | | | | | | | | | | | | CAN1_RX, FMC_D22, | |
| | | | | | | | | | | | | | | | DCMI_D4, LCD_G3, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| - | - | - | D13 | 130 | 153 | D13 | E5 | - | 153 | D13 | PH15 | I/O | FT | - | TIM8_CH3N, FMC_D23, | - |
| | | | | | | | | | | | | | | | DCMI_D11, LCD_G4, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| - | - | - | E14 | 131 | 154 | E14 | E4 | 132 | 154 | E14 | PI0 | I/O | FT | - | TIM5_CH4, | - |
| | | | | | | | | | | | | | | | SPI2_NSS/I2S2_WS, | |
| | | | | | | | | | | | | | | | FMC_D24, DCMI_D13, | |
| | | | | | | | | | | | | | | | LCD_G5, EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| - | - | - | D14 | 132 | 155 | D14 | B3 | 133 | 155 | D14 | PI1 | I/O | FT | - | TIM8_BKIN2, | - |
| | | | | | | | | | | | | | | | SPI2_SCK/I2S2_CK, | |
| | | | | | | | | | | | | | | | FMC_D25, DCMI_D8, | |
| | | | | | | | | | | | | | | | LCD_G6, EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| - | - | - | C14 | 133 | 156 | C14 | C3 | - | 156 | C14 | PI2 | I/O | FT | - | TIM8_CH4, SPI2_MISO, | - |
| | | | | | | | | | | | | | | | FMC_D26, DCMI_D9, | |
| | | | | | | | | | | | | | | | LCD_G7, EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| - | - | - | C13 | 134 | 157 | C13 | D3 | 134 | 157 | C13 | PI3 | I/O | FT | - | TIM8_ETR, | - |
| | | | | | | | | | | | | | | | SPI2_MOSI/I2S2_SD, | |
| | | | | | | | | | | | | | | | FMC_D27, DCMI_D10, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| - | - | - | D9 | 135 | - | F9 | - | 135 | - | F9 | VSS | S | - | - | - | - |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| - | - | - | C9 | 136 | 158 | E10 | - | 136 | 158 | E10 | VDD | S | - | - | - | -- |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
| A9 | 76 | 109 | A14 | 137 | 159 | A14 | A3 | 137 | 159 | A14 | PA14(JTC | I/O | FT | - | JTCK-SWCLK, EVENTOUT | - |
| | | | | | | | | | | | K-SWCLK) | | | | | |
+-----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+----------------------+------------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #80 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+--------------------------------------------------------------+-----------+-----+----+---+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+---------------------------------------+----------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
| A8 | 77 | 110 | A13 | 138 | 160 | A13 | F8 | 138 | 160 | A13 | PA15(JTDI | I/O | FT | - | JTDI, TIM2_CH1/TIM2_ETR, | - |
| | | | | | | | | | | | ) | | | | HDMI_CEC, | |
| | | | | | | | | | | | | | | | SPI1_NSS/I2S1_WS, | |
| | | | | | | | | | | | | | | | SPI3_NSS/I2S3_WS, | |
| | | | | | | | | | | | | | | | SPI6_NSS, UART4_RTS, | |
| | | | | | | | | | | | | | | | CAN3_TX, UART7_TX, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
| B9 | 78 | 111 | B14 | 139 | 161 | B14 | B4 | 139 | 161 | B14 | PC10 | I/O | FT | - | DFSDM1_CKIN5, | - |
| | | | | | | | | | | | | | | | SPI3_SCK/I2S3_CK, | |
| | | | | | | | | | | | | | | | USART3_TX, UART4_TX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_IO1, | |
| | | | | | | | | | | | | | | | SDMMC1_D2, DCMI_D8, | |
| | | | | | | | | | | | | | | | LCD_R2, EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
| B8 | 79 | 112 | B13 | 140 | 162 | B13 | C4 | 140 | 162 | B13 | PC11 | I/O | FT | - | DFSDM1_DATIN5, | - |
| | | | | | | | | | | | | | | | SPI3_MISO, USART3_RX, | |
| | | | | | | | | | | | | | | | UART4_RX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK2_NCS, | |
| | | | | | | | | | | | | | | | SDMMC1_D3, DCMI_D4, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
| C8 | 80 | 113 | A12 | 141 | 163 | A12 | D4 | 141 | 163 | A12 | PC12 | I/O | FT | - | TRACED3, | - |
| | | | | | | | | | | | | | | | SPI3_MOSI/I2S3_SD, | |
| | | | | | | | | | | | | | | | USART3_CK, UART5_TX, | |
| | | | | | | | | | | | | | | | SDMMC1_CK, DCMI_D9, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
| D8 | 81 | 114 | B12 | 142 | 164 | B12 | A4 | 142 | 164 | B12 | PD0 | I/O | FT | - | DFSDM1_CKIN6, | - |
| | | | | | | | | | | | | | | | DFSDM1_DATIN7, | |
| | | | | | | | | | | | | | | | UART4_RX, CAN1_RX, | |
| | | | | | | | | | | | | | | | FMC_D2, EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
| E8 | 82 | 115 | C12 | 143 | 165 | C12 | D5 | 143 | 165 | C12 | PD1 | I/O | FT | - | DFSDM1_DATIN6, | -- |
| | | | | | | | | | | | | | | | DFSDM1_CKIN7, UART4_TX, | |
| | | | | | | | | | | | | | | | CAN1_TX, FMC_D3, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
| B7 | 83 | 116 | D12 | 144 | 166 | D12 | D6 | 144 | 166 | D12 | PD2 | I/O | FT | - | TRACED2, TIM3_ETR, | - |
| | | | | | | | | | | | | | | | UART5_RX, SDMMC1_CMD, | |
| | | | | | | | | | | | | | | | DCMI_D11, EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
| C7 | 84 | 117 | D11 | 145 | 167 | C11 | B5 | 145 | 167 | C11 | PD3 | I/O | FT | - | DFSDM1_CKOUT, | - |
| | | | | | | | | | | | | | | | SPI2_SCK/I2S2_CK, | |
| | | | | | | | | | | | | | | | DFSDM1_DATIN0, | |
| | | | | | | | | | | | | | | | USART2_CTS, FMC_CLK, | |
| | | | | | | | | | | | | | | | DCMI_D5, LCD_G7, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
| D7 | 85 | 118 | D10 | 146 | 168 | D11 | A5 | 146 | 168 | D11 | PD4 | I/O | FT | - | DFSDM1_CKIN0, | - |
| | | | | | | | | | | | | | | | USART2_RTS, FMC_NOE, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+-----------+-----+----+---+--------------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #81 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+--------------------------------------------------------------+--------+-----+----+---+---------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+---------------------------------------+----------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| B6 | 86 | 119 | C11 | 147 | 169 | C10 | C5 | 147 | 169 | C10 | PD5 | I/O | FT | - | USART2_TX, FMC_NWE, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| - | - | 120 | D8 | 148 | 170 | F8 | B6 | 148 | 170 | F8 | VSS | S | - | - | - | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| - | - | 121 | C8 | 149 | 171 | E9 | A6 | 149 | 171 | E9 | VDDSDM | S | - | - | - | - |
| | | | | | | | | | | | MC | | | | | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| C6 | 87 | 122 | B11 | 150 | 172 | B11 | E6 | 150 | 172 | B11 | PD6 | I/O | FT | - | DFSDM1_CKIN4, | - |
| | | | | | | | | | | | | | | | SPI3_MOSI/I2S3_SD, | |
| | | | | | | | | | | | | | | | SAI1_SD_A, USART2_RX, | |
| | | | | | | | | | | | | | | | DFSDM1_DATIN1, | |
| | | | | | | | | | | | | | | | SDMMC2_CK, FMC_NWAIT, | |
| | | | | | | | | | | | | | | | DCMI_D10, LCD_B2, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| D6 | 88 | 123 | A11 | 151 | 173 | A11 | E7 | 151 | 173 | A11 | PD7 | I/O | FT | - | DFSDM1_DATIN4, | - |
| | | | | | | | | | | | | | | | SPI1_MOSI/I2S1_SD, | |
| | | | | | | | | | | | | | | | DFSDM1_CKIN1, | |
| | | | | | | | | | | | | | | | USART2_CK, SPDIF_RX0, | |
| | | | | | | | | | | | | | | | SDMMC2_CMD, FMC_NE1, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| - | - | - | - | - | 174 | B10 | NC | - | 174 | B10 | PJ12 | I/O | FT | - | LCD_G3, LCD_B0, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| - | - | - | - | - | 175 | B9 | NC | - | 175 | B9 | PJ13 | I/O | FT | - | LCD_G4, LCD_B1, | - |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| - | - | - | - | - | 176 | C9 | NC | - | 176 | C9 | PJ14 | I/O | FT | - | LCD_B2, EVENTOUT | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| - | - | - | - | - | 177 | D10 | - | - | 177 | D10 | PJ15 | I/O | FT | - | LCD_B3, EVENTOUT | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| - | - | 124 | C10 | 152 | 178 | D9 | C6 | 152 | 178 | D9 | PG9 | I/O | FT | - | SPI1_MISO, SPDIF_RX3, | - |
| | | | | | | | | | | | | | | | USART6_RX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK2_IO2, | |
| | | | | | | | | | | | | | | | SAI2_FS_B, SDMMC2_D0, | |
| | | | | | | | | | | | | | | | FMC_NE2/FMC_NCE, | |
| | | | | | | | | | | | | | | | DCMI_VSYNC, EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| - | - | 125 | B10 | 153 | 179 | C8 | A7 | 153 | 179 | C8 | PG10 | I/O | FT | - | SPI1_NSS/I2S1_WS, LCD_G3, | - |
| | | | | | | | | | | | | | | | SAI2_SD_B, SDMMC2_D1, | |
| | | | | | | | | | | | | | | | FMC_NE3, DCMI_D2, | |
| | | | | | | | | | | | | | | | LCD_B2, EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
| - | - | 126 | B9 | 154 | 180 | B8 | B7 | 154 | 180 | B8 | PG11 | I/O | FT | - | SPI1_SCK/I2S1_CK, | - |
| | | | | | | | | | | | | | | | SPDIF_RX0, SDMMC2_D2, | |
| | | | | | | | | | | | | | | | ETH_MII_TX_EN/ETH_RMII_T | |
| | | | | | | | | | | | | | | | X_EN, DCMI_D3, LCD_B3, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+--------+-----+----+---+---------------------------+------------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #82 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+--------------------------------------------------------------+----------+-----+----+---+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+---------------------------------------+----------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | 127 | B8 | 155 | 181 | C7 | D7 | 155 | 181 | C7 | PG12 | I/O | FT | - | LPTIM1_IN1, SPI6_MISO, | - |
| | | | | | | | | | | | | | | | SPDIF_RX1, USART6_RTS, | |
| | | | | | | | | | | | | | | | LCD_B4, SDMMC2_D3, | |
| | | | | | | | | | | | | | | | FMC_NE4, LCD_B1, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | 128 | A8 | 156 | 182 | B3 | C7 | 156 | 182 | B3 | PG13 | I/O | FT | - | TRACED0, LPTIM1_OUT, | - |
| | | | | | | | | | | | | | | | SPI6_SCK, USART6_CTS, | |
| | | | | | | | | | | | | | | | ETH_MII_TXD0/ETH_RMII_TX | |
| | | | | | | | | | | | | | | | D0, FMC_A24, LCD_R0, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | 129 | A7 | 157 | 183 | A4 | NC | 157 | 183 | A4 | PG14 | I/O | FT | - | TRACED1, LPTIM1_ETR, | - |
| | | | | | | | | | | | | | | | SPI6_MOSI, USART6_TX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK2_IO3, | |
| | | | | | | | | | | | | | | | ETH_MII_TXD1/ETH_RMII_TX | |
| | | | | | | | | | | | | | | | D1, FMC_A25, LCD_B0, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | 130 | D7 | 158 | 184 | F7 | A8 | 158 | 184 | F7 | VSS | S | - | - | - | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | 131 | C7 | 159 | 185 | E8 | B8 | 159 | 185 | E8 | VDD | S | - | - | - | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 186 | D8 | NC | - | 186 | D8 | PK3 | I/O | FT | - | LCD_B4, EVENTOUT | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 187 | D7 | NC | - | 187 | D7 | PK4 | I/O | FT | - | LCD_B5, EVENTOUT | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 188 | C6 | NC | - | 188 | C6 | PK5 | I/O | FT | - | LCD_B6, EVENTOUT | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 189 | C5 | NC | - | 189 | C5 | PK6 | I/O | FT | - | LCD_B7, EVENTOUT | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | - | - | - | 190 | C4 | NC | - | 190 | C4 | PK7 | I/O | FT | - | LCD_DE, EVENTOUT | - |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| - | - | 132 | B7 | 160 | 191 | B7 | F9 | 160 | 191 | B7 | PG15 | I/O | FT | - | USART6_CTS, | - |
| | | | | | | | | | | | | | | | FMC_SDNCAS, DCMI_D13, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| A7 | 89 | 133 | A10 | 161 | 192 | A10 | E8 | 161 | 192 | A10 | PB3 | I/O | FT | - | JTDO/TRACESWO, | - |
| | | | | | | | | | | | (JTDO/ | | | | TIM2_CH2, | |
| | | | | | | | | | | | TRACESW | | | | SPI1_SCK/I2S1_CK, | |
| | | | | | | | | | | | O) | | | | SPI3_SCK/I2S3_CK, | |
| | | | | | | | | | | | | | | | SPI6_SCK, SDMMC2_D2, | |
| | | | | | | | | | | | | | | | CAN3_RX, UART7_RX, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
| A6 | 90 | 134 | A9 | 162 | 193 | A9 | D8 | 162 | 193 | A9 | PB4(NJTR | I/O | FT | - | NJTRST, TIM3_CH1, | - |
| | | | | | | | | | | | ST) | | | | SPI1_MISO, SPI3_MISO, | |
| | | | | | | | | | | | | | | | SPI2_NSS/I2S2_WS, | |
| | | | | | | | | | | | | | | | SPI6_MISO, SDMMC2_D3, | |
| | | | | | | | | | | | | | | | CAN3_TX, UART7_TX, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----------+-----+----+---+--------------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #83 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+------------------------------------------------------------+-------+-----+----+---+--------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+-------------------------------------+----------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+-------+-----+----+---+--------------------------+------------+
| C5 | 91 | 135 | A6 | 163 | 194 | A8 | A9 | 163 | 194 | A8 | PB5 | I/O | FT | - | UART5_RX, TIM3_CH2, | - |
| | | | | | | | | | | | | | | | I2C1_SMBA, | |
| | | | | | | | | | | | | | | | SPI1_MOSI/I2S1_SD, | |
| | | | | | | | | | | | | | | | SPI3_MOSI/I2S3_SD, | |
| | | | | | | | | | | | | | | | SPI6_MOSI, CAN2_RX, | |
| | | | | | | | | | | | | | | | OTG_HS_ULPI_D7, | |
| | | | | | | | | | | | | | | | ETH_PPS_OUT, | |
| | | | | | | | | | | | | | | | FMC_SDCKE1, DCMI_D10, | |
| | | | | | | | | | | | | | | | LCD_G7, EVENTOUT | |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+-------+-----+----+---+--------------------------+------------+
| B5 | 92 | 136 | B6 | 164 | 195 | B6 | B9 | 164 | 195 | B6 | PB6 | I/O | FT | - | UART5_TX, TIM4_CH1, | - |
| | | | | | | | | | | | | | | | HDMI_CEC, I2C1_SCL, | |
| | | | | | | | | | | | | | | | DFSDM1_DATIN5, | |
| | | | | | | | | | | | | | | | USART1_TX, CAN2_TX, | |
| | | | | | | | | | | | | | | | QUADSPI_BK1_NCS, | |
| | | | | | | | | | | | | | | | I2C4_SCL, FMC_SDNE1, | |
| | | | | | | | | | | | | | | | DCMI_D5, EVENTOUT | |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+-------+-----+----+---+--------------------------+------------+
| A5 | 93 | 137 | B5 | 165 | 196 | B5 | C8 | 165 | 196 | B5 | PB7 | I/O | FT | - | TIM4_CH2, I2C1_SDA, | - |
| | | | | | | | | | | | | | | | DFSDM1_CKIN5, | |
| | | | | | | | | | | | | | | | USART1_RX, I2C4_SDA, | |
| | | | | | | | | | | | | | | | FMC_NL, DCMI_VSYNC, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+-------+-----+----+---+--------------------------+------------+
| D5 | 94 | 138 | D6 | 166 | 197 | E6 | A10 | 166 | 197 | E6 | BOOT0 | I | B | - | - | VPP |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+-------+-----+----+---+--------------------------+------------+
| B4 | 95 | 139 | A5 | 167 | 198 | A7 | E9 | 167 | 198 | A7 | PB8 | I/O | FT | - | I2C4_SCL, TIM4_CH3, | - |
| | | | | | | | | | | | | | | | TIM10_CH1, I2C1_SCL, | |
| | | | | | | | | | | | | | | | DFSDM1_CKIN7, UART5_RX, | |
| | | | | | | | | | | | | | | | CAN1_RX, SDMMC2_D4, | |
| | | | | | | | | | | | | | | | ETH_MII_TXD3, SDMMC1_D4, | |
| | | | | | | | | | | | | | | | DCMI_D6, LCD_B6, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+-------+-----+----+---+--------------------------+------------+
| A4 | 96 | 140 | B4 | 168 | 199 | B4 | D9 | 168 | 199 | B4 | PB9 | I/O | FT | - | I2C4_SDA, TIM4_CH4, | - |
| | | | | | | | | | | | | | | | TIM11_CH1, I2C1_SDA, | |
| | | | | | | | | | | | | | | | SPI2_NSS/I2S2_WS, | |
| | | | | | | | | | | | | | | | DFSDM1_DATIN7, UART5_TX, | |
| | | | | | | | | | | | | | | | CAN1_TX, SDMMC2_D5, | |
| | | | | | | | | | | | | | | | I2C4_SMBA, SDMMC1_D5, | |
| | | | | | | | | | | | | | | | DCMI_D7, LCD_B7, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+-------+-----+----+---+--------------------------+------------+
| D4 | 97 | 141 | A4 | 169 | 200 | A6 | C9 | 169 | 200 | A6 | PE0 | I/O | FT | - | TIM4_ETR, LPTIM1_ETR, | - |
| | | | | | | | | | | | | | | | UART8_RX, SAI2_MCLK_A, | |
| | | | | | | | | | | | | | | | FMC_NBL0, DCMI_D2, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+-------+-----+----+---+--------------------------+------------+
| C4 | 98 | 142 | A3 | 170 | 201 | A5 | B10 | 170 | 201 | A5 | PE1 | I/O | FT | - | LPTIM1_IN2, UART8_TX, | - |
| | | | | | | | | | | | | | | | FMC_NBL1, DCMI_D3, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+----+-----+----+-----+-----+----+-----+-----+-----+----+-------+-----+----+---+--------------------------+------------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #84 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+--------------------------------------------------------------+--------+-----+----+---+---------------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+---------------------------------------+----------------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| E4 | 99 | - | D5 | - | 202 | F6 | A11 | - | 202 | F6 | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| F7 | - | 143 | C6 | 171 | 203 | E5 | C10 | 171 | 203 | E5 | PDR_ON | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| F4 | 100 | 144 | C5 | 172 | 204 | E7 | B11 | 172 | 204 | E7 | VDD | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | D4 | 173 | 205 | C3 | D10 | 173 | 205 | C3 | PI4 | I/O | FT | - | TIM8_BKIN, SAI2_MCLK_A, | - |
| | | | | | | | | | | | | | | | FMC_NBL2, DCMI_D5, | |
| | | | | | | | | | | | | | | | LCD_B4, EVENTOUT | |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | C4 | 174 | 206 | D3 | D11 | 174 | 206 | D3 | PI5 | I/O | FT | - | TIM8_CH1, SAI2_SCK_A, | - |
| | | | | | | | | | | | | | | | FMC_NBL3, DCMI_VSYNC, | |
| | | | | | | | | | | | | | | | LCD_B5, EVENTOUT | |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | C3 | 175 | 207 | D6 | C11 | 175 | 207 | D6 | PI6 | I/O | FT | - | TIM8_CH2, SAI2_SD_A, | - |
| | | | | | | | | | | | | | | | FMC_D28, DCMI_D6, LCD_B6, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | C2 | 176 | 208 | D4 | B12 | 176 | 208 | D4 | PI7 | I/O | FT | - | TIM8_CH3, SAI2_FS_A, | - |
| | | | | | | | | | | | | | | | FMC_D29, DCMI_D7, LCD_B7, | |
| | | | | | | | | | | | | | | | EVENTOUT | |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | F6 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | F7 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | F8 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | F9 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | F10 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | G6 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | G7 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | G8 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | G9 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | G10 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | H6 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | H7 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | H8 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | H9 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | H10 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
| - | - | - | J6 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+----+-----+-----+-----+-----+-----+----+-----+-----+-----+----+--------+-----+----+---+---------------------------+------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #85 ===
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
+---------------------------------------------+-----+---+---+---+---------------------+------------+
| Pin Number | t | e | e | s | Alternate functions | Additional |
| | e | p | r | e | | functions |
| | s | y | u | t | | |
| | e | t | t | o | | |
| | r | | c | N | | |
| | | n | u | | | |
+-----------------------------+---------------+ r | i | r | | | |
| STM32F765xx | STM32F768Ax | e | P | t | | | |
| STM32F767xx | STM32F769xx | t | | s | | | |
| | | f | | | | | |
| | | a | | O | | | |
| | | | | / | | | |
| | | n | | I | | | |
| | | o | | | | | |
+---+---+---+-----+---+---+---+---+---+---+---+ i | | | | | |
| 0 | 0 | 4 | 6 | 6 | 8 | 6 | ⁾ | 6 | 8 | 6 | t | | | | | |
| 0 | 0 | 4 | 7 | 7 | 0 | 1 | ¹ | 7 | 0 | 1 | c | | | | | |
| 1 | 1 | 1 | 1 | 1 | 2 | 2 | ⁽ | 1 | 2 | 2 | n | | | | | |
| A | P | P | A | P | P | A | 0 | P | P | A | u | | | | | |
| G | F | F | G | F | F | G | 8 | F | F | G | f | | | | | |
| B | Q | Q | B | Q | Q | B | 1 | Q | Q | B | ( | | | | | |
| F | L | L | F | L | L | F | P | L | L | F | | | | | | |
| T | | | U | | | T | S | | | T | e | | | | | |
| | | | | | | | C | | | | m | | | | | |
| | | | | | | | L | | | | a | | | | | |
| | | | | | | | W | | | | n | | | | | |
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | n | | | | | |
| | | | | | | | | | | | i | | | | | |
| | | | | | | | | | | | P | | | | | |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
| - | - | - | J7 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
| - | - | - | J8 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
| - | - | - | J9 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
| - | - | - | J10 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
| - | - | - | K6 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
| - | - | - | K7 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
| - | - | - | K8 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
| - | - | - | K9 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
| - | - | - | K10 | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
+---+---+---+-----+---+---+---+---+---+---+---+-----+---+---+---+---------------------+------------+
1. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the
output data register to avoid an extra current consumption in low-power modes. list of pins: PI8, PI12, PI13, PI14, PF6,
PF7, PF8, PF9, PC2, PC3, PC4, PC5, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PH6, PH7, PJ12, PJ13, PJ14, PJ15, PG14,
PK3, PK4, PK5, PK6 and PK7.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os
must not be used as a current source (e.g. to drive an LED).
3. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
4. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low).
5. Internally connected to VDD or VSS depending on part number.
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #86 ===
Table 12. FMC pin definition
+----------+--------------+-----------+--------+-------+
| Pin name | NOR/PSRAM/SR | NOR/PSRAM | NAND16 | SDRAM |
| | AM | Mux | | |
+==========+==============+===========+========+=======+
| PF0 | A0 | - | - | A0 |
+----------+--------------+-----------+--------+-------+
| PF1 | A1 | - | - | A1 |
+----------+--------------+-----------+--------+-------+
| PF2 | A2 | - | - | A2 |
+----------+--------------+-----------+--------+-------+
| PF3 | A3 | - | - | A3 |
+----------+--------------+-----------+--------+-------+
| PF4 | A4 | - | - | A4 |
+----------+--------------+-----------+--------+-------+
| PF5 | A5 | - | - | A5 |
+----------+--------------+-----------+--------+-------+
| PF12 | A6 | - | - | A6 |
+----------+--------------+-----------+--------+-------+
| PF13 | A7 | - | - | A7 |
+----------+--------------+-----------+--------+-------+
| PF14 | A8 | - | - | A8 |
+----------+--------------+-----------+--------+-------+
| PF15 | A9 | - | - | A9 |
+----------+--------------+-----------+--------+-------+
| PG0 | A10 | - | - | A10 |
+----------+--------------+-----------+--------+-------+
| PG1 | A11 | - | - | A11 |
+----------+--------------+-----------+--------+-------+
| PG2 | A12 | - | - | A12 |
+----------+--------------+-----------+--------+-------+
| PG3 | A13 | - | - | - |
+----------+--------------+-----------+--------+-------+
| PG4 | A14 | - | - | BA0 |
+----------+--------------+-----------+--------+-------+
| PG5 | A15 | - | - | BA1 |
+----------+--------------+-----------+--------+-------+
| PD11 | A16 | A16 | CLE | - |
+----------+--------------+-----------+--------+-------+
| PD12 | A17 | A17 | ALE | - |
+----------+--------------+-----------+--------+-------+
| PD13 | A18 | A18 | - | - |
+----------+--------------+-----------+--------+-------+
| PE3 | A19 | A19 | - | - |
+----------+--------------+-----------+--------+-------+
| PE4 | A20 | A20 | - | - |
+----------+--------------+-----------+--------+-------+
| PE5 | A21 | A21 | - | - |
+----------+--------------+-----------+--------+-------+
| PE6 | A22 | A22 | - | - |
+----------+--------------+-----------+--------+-------+
| PE2 | A23 | A23 | - | - |
+----------+--------------+-----------+--------+-------+
| PG13 | A24 | A24 | - | - |
+----------+--------------+-----------+--------+-------+
| PG14 | A25 | A25 | - | - |
+----------+--------------+-----------+--------+-------+
| PD14 | D0 | DA0 | D0 | D0 |
+----------+--------------+-----------+--------+-------+
| PD15 | D1 | DA1 | D1 | D1 |
+----------+--------------+-----------+--------+-------+
| PD0 | D2 | DA2 | D2 | D2 |
+----------+--------------+-----------+--------+-------+
| PD1 | D3 | DA3 | D3 | D3 |
+----------+--------------+-----------+--------+-------+
| PE7 | D4 | DA4 | D4 | D4 |
+----------+--------------+-----------+--------+-------+
| PE8 | D5 | DA5 | D5 | D5 |
+----------+--------------+-----------+--------+-------+
| PE9 | D6 | DA6 | D6 | D6 |
+----------+--------------+-----------+--------+-------+
| PE10 | D7 | DA7 | D7 | D7 |
+----------+--------------+-----------+--------+-------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description #87 ===
Table 12. FMC pin definition (continued)
+----------+--------------+-----------+--------+-------+
| Pin name | NOR/PSRAM/SR | NOR/PSRAM | NAND16 | SDRAM |
| | AM | Mux | | |
+==========+==============+===========+========+=======+
| PE11 | D8 | DA8 | D8 | D8 |
+----------+--------------+-----------+--------+-------+
| PE12 | D9 | DA9 | D9 | D9 |
+----------+--------------+-----------+--------+-------+
| PE13 | D10 | DA10 | D10 | D10 |
+----------+--------------+-----------+--------+-------+
| PE14 | D11 | DA11 | D11 | D11 |
+----------+--------------+-----------+--------+-------+
| PE15 | D12 | DA12 | D12 | D12 |
+----------+--------------+-----------+--------+-------+
| PD8 | D13 | DA13 | D13 | D13 |
+----------+--------------+-----------+--------+-------+
| PD9 | D14 | DA14 | D14 | D14 |
+----------+--------------+-----------+--------+-------+
| PD10 | D15 | DA15 | D15 | D15 |
+----------+--------------+-----------+--------+-------+
| PH8 | D16 | - | - | D16 |
+----------+--------------+-----------+--------+-------+
| PH9 | D17 | - | - | D17 |
+----------+--------------+-----------+--------+-------+
| PH10 | D18 | - | - | D18 |
+----------+--------------+-----------+--------+-------+
| PH11 | D19 | - | - | D19 |
+----------+--------------+-----------+--------+-------+
| PH12 | D20 | - | - | D20 |
+----------+--------------+-----------+--------+-------+
| PH13 | D21 | - | - | D21 |
+----------+--------------+-----------+--------+-------+
| PH14 | D22 | - | - | D22 |
+----------+--------------+-----------+--------+-------+
| PH15 | D23 | - | - | D23 |
+----------+--------------+-----------+--------+-------+
| PI0 | D24 | - | - | D24 |
+----------+--------------+-----------+--------+-------+
| PI1 | D25 | - | - | D25 |
+----------+--------------+-----------+--------+-------+
| PI2 | D26 | - | - | D26 |
+----------+--------------+-----------+--------+-------+
| PI3 | D27 | - | - | D27 |
+----------+--------------+-----------+--------+-------+
| PI6 | D28 | - | - | D28 |
+----------+--------------+-----------+--------+-------+
| PI7 | D29 | - | - | D29 |
+----------+--------------+-----------+--------+-------+
| PI9 | D30 | - | - | D30 |
+----------+--------------+-----------+--------+-------+
| PI10 | D31 | - | - | D31 |
+----------+--------------+-----------+--------+-------+
| PD7 | NE1 | NE1 | - | - |
+----------+--------------+-----------+--------+-------+
| PG6 | NE3 | - | - | - |
+----------+--------------+-----------+--------+-------+
| PG9 | NE2 | NE2 | NCE | - |
+----------+--------------+-----------+--------+-------+
| PG10 | NE3 | NE3 | - | - |
+----------+--------------+-----------+--------+-------+
| PG11 | - | - | - | - |
+----------+--------------+-----------+--------+-------+
| PG12 | NE4 | NE4 | - | - |
+----------+--------------+-----------+--------+-------+
| PD3 | CLK | CLK | - | - |
+----------+--------------+-----------+--------+-------+
| PD4 | NOE | NOE | NOE | - |
+----------+--------------+-----------+--------+-------+
| PD5 | NWE | NWE | NWE | - |
+----------+--------------+-----------+--------+-------+
| PD6 | NWAIT | NWAIT | NWAIT | - |
+----------+--------------+-----------+--------+-------+
=== Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #88 ===
Table 12. FMC pin definition (continued)
+----------+--------------+-----------+--------+--------+
| Pin name | NOR/PSRAM/SR | NOR/PSRAM | NAND16 | SDRAM |
| | AM | Mux | | |
+==========+==============+===========+========+========+
| PB7 | NADV | NADV | - | - |
+----------+--------------+-----------+--------+--------+
| PF6 | - | - | - | - |
+----------+--------------+-----------+--------+--------+
| PF7 | - | - | - | - |
+----------+--------------+-----------+--------+--------+
| PF8 | - | - | - | - |
+----------+--------------+-----------+--------+--------+
| PF9 | - | - | - | - |
+----------+--------------+-----------+--------+--------+
| PF10 | - | - | - | - |
+----------+--------------+-----------+--------+--------+
| PG6 | - | - | - | - |
+----------+--------------+-----------+--------+--------+
| PG7 | - | - | INT | - |
+----------+--------------+-----------+--------+--------+
| PE0 | NBL0 | NBL0 | - | NBL0 |
+----------+--------------+-----------+--------+--------+
| PE1 | NBL1 | NBL1 | - | NBL1 |
+----------+--------------+-----------+--------+--------+
| PI4 | NBL2 | - | - | NBL2 |
+----------+--------------+-----------+--------+--------+
| PI5 | NBL3 | - | - | NBL3 |
+----------+--------------+-----------+--------+--------+
| PG8 | - | - | - | SDCLK |
+----------+--------------+-----------+--------+--------+
| PC0 | - | - | - | SDNWE |
+----------+--------------+-----------+--------+--------+
| PF11 | - | - | - | SDNRAS |
+----------+--------------+-----------+--------+--------+
| PG15 | - | - | - | SDNCAS |
+----------+--------------+-----------+--------+--------+
| PH2 | - | - | - | SDCKE0 |
+----------+--------------+-----------+--------+--------+
| PH3 | - | - | - | SDNE0 |
+----------+--------------+-----------+--------+--------+
| PH6 | - | - | - | SDNE1 |
+----------+--------------+-----------+--------+--------+
| PH7 | - | - | - | SDCKE1 |
+----------+--------------+-----------+--------+--------+
| PH5 | - | - | - | SDNWE |
+----------+--------------+-----------+--------+--------+
| PC2 | - | - | - | SDNE0 |
+----------+--------------+-----------+--------+--------+
| PC3 | - | - | - | SDCKE0 |
+----------+--------------+-----------+--------+--------+
| PC6 | NWAIT | NWAIT | NWAIT | - |
+----------+--------------+-----------+--------+--------+
| PB5 | - | - | - | SDCKE1 |
+----------+--------------+-----------+--------+--------+
| PB6 | - | - | - | SDNE1 |
+----------+--------------+-----------+--------+--------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Memory mapping #103 ===
5 Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #104 ===
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 22.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 23.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #105 ===
6.1.6 Power supply scheme
Figure 24. STM32F769xx/STM32F779xx power supply scheme
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #106 ===
Figure 25. STM32F765xx/STM32F767xx/STM32F777xx power supply scheme
1. To connect BYPASS_REG and PDR_ON pins, refer to Section 3.18: Power supply supervisor and
Section 3.19: Voltage regulator.
2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4. VDDA=VDD and VSSA=VSS.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #107 ===
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7 Current consumption measurement
Figure 26. Current consumption measurement scheme
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics, and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. The device mission profile (application
conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission
profiles are available on demand.
Table 14. Voltage characteristics
+-------------+-----------------------------------------------------+-----------+---------+------+
| Symbol | Ratings | Min | Max | Unit |
+=============+=====================================================+===========+=========+======+
| VDD–VSS | External main supply voltage (including VDDA, VDD, | − 0.3 | 4.0 | V |
| | VBAT, VDDUSB, VDDDSI ⁽¹⁾ and VDDSDMMC)⁽²⁾ | | | |
+-------------+-----------------------------------------------------+-----------+---------+ |
| VIN | Input voltage on FT pins⁽³⁾ | VSS − 0.3 | VDD+4.0 | |
| +-----------------------------------------------------+-----------+---------+ |
| | Input voltage on TTa pins | VSS − 0.3 | 4.0 | |
| +-----------------------------------------------------+-----------+---------+ |
| | Input voltage on any other pin | VSS − 0.3 | 4.0 | |
| +-----------------------------------------------------+-----------+---------+ |
| | Input voltage on BOOT pin | VSS | 9.0 | |
+-------------+-----------------------------------------------------+-----------+---------+------+
| |ΔVDDx| | Variations between different VDD power pins | - | 50 | mV |
+-------------+-----------------------------------------------------+-----------+---------+ |
| |VSSX −VSS| | Variations between all the different ground pins⁽⁴⁾ | - | 50 | |
+-------------+-----------------------------------------------------+-----------+---------+------+
| VESD(HBM) | Electrostatic discharge voltage (human body model) | see Section 6.3.18: | - |
| | | Absolute maximum | |
| | | ratings (electrical | |
| | | sensitivity) | |
+-------------+-----------------------------------------------------+---------------------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #108 ===
1. Applicable only for STM32F7x9 sales types.
2. All main power (VDD, VDDA, VDDSDMMC, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
3. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
4. Include VREF- pin.
Table 15. Current characteristics
+---------------+-------------------------------------------------------------------------------------+-------+------+
| Symbol | Ratings | Max. | Unit |
+===============+=====================================================================================+=======+======+
| ΣIVDD | Total current into sum of all VDD_x power lines (source)⁽¹⁾ | 420 | mA |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| Σ IVSS | Total current out of sum of all VSS_x ground lines (sink)⁽¹⁾ | −420 | |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| Σ IVDDUSB | Total current into VDDUSB power line (source) | 25 | |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| Σ IVDDSDMMC | Total current into VDDSDMMC power line (source) | 60 | |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| IVDD | Maximum current into each VDD_x power line (source)⁽¹⁾ | 100 | |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| IVDDSDMMC | Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6] | 100 | |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| IVSS | Maximum current out of each VSS_x ground line (sink)⁽¹⁾ | −100 | |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| IIO | Output current sunk by any I/O and control pin | 25 | |
| +-------------------------------------------------------------------------------------+-------+ |
| | Output current sourced by any I/Os and control pin | −25 | |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| ΣIIO | Total output current sunk by sum of all I/O and control pins ⁽²⁾ | 120 | |
| +-------------------------------------------------------------------------------------+-------+ |
| | Total output current sunk by sum of all USB I/Os | 25 | |
| +-------------------------------------------------------------------------------------+-------+ |
| | Total output current sunk by sum of all SDMMC I/Os | 120 | |
| +-------------------------------------------------------------------------------------+-------+ |
| | Total output current sourced by sum of all I/Os and control pins except USB I/Os⁽²⁾ | −120 | |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| IINJ(PIN) | Injected current on FT, FTf, RST and B pins ⁽³⁾ | −5/+0 | |
| +-------------------------------------------------------------------------------------+-------+ |
| | Injected current on TTa pins⁽⁴⁾ | ±5 | |
+---------------+-------------------------------------------------------------------------------------+-------+ |
| ΣIINJ(PIN)⁽⁴⁾ | Total injected current (sum of all I/O and control pins)⁽⁵⁾ | ±25 | |
+---------------+-------------------------------------------------------------------------------------+-------+------+
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 14: Voltage characteristics for the values of the maximum allowed input voltage.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 16. Thermal characteristics
+--------+------------------------------+--------------+------+
| Symbol | Ratings | Value | Unit |
+========+==============================+==============+======+
| TSTG | Storage temperature range | − 65 to +150 | °C |
+--------+------------------------------+--------------+ |
| TJ | Maximum junction temperature | 125 | |
+--------+------------------------------+--------------+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #109 ===
6.3 Operating conditions
6.3.1 General operating conditions
Table 17. General operating conditions
+------------+--------------------------------+-----------------------------------------+--------+-----+--------+------+
| Symbol | Parameter | Conditions⁽¹⁾ | Min | Typ | Max | Unit |
+============+================================+=========================================+========+=====+========+======+
| fHCLK | Internal AHB clock frequency | Power Scale 3 (VOS[1:0] bits in | 0 | - | 144 | MHz |
| | | PWR_CR register = 0x01), Regulator | | | | |
| | | ON, over-drive OFF | | | | |
| | +---------------------------------+-------+--------+-----+--------+ |
| | | Power Scale 2 (VOS[1:0] bits | Over- | 0 | - | 168 | |
| | | in PWR_CR register = 0x10), | drive | | | | |
| | | Regulator ON | OFF | | | | |
| | | +-------+ +-----+--------+ |
| | | | Over- | | - | 180 | |
| | | | drive | | | | |
| | | | ON | | | | |
| | +---------------------------------+-------+--------+-----+--------+ |
| | | Power Scale 1 (VOS[1:0] bits | Over- | 0 | - | 180 | |
| | | in PWR_CR register= 0x11), | drive | | | | |
| | | Regulator ON | OFF | | | | |
| | | +-------+ +-----+--------+ |
| | | | Over- | | - | 216⁽²⁾ | |
| | | | drive | | | | |
| | | | ON | | | | |
+------------+--------------------------------+---------------------------------+-------+--------+-----+--------+ |
| fPCLK1 | Internal APB1 clock frequency | Over-drive OFF | 0 | - | 45 | |
| | +-----------------------------------------+--------+-----+--------+ |
| | | Over-drive ON | 0 | - | 54 | |
+------------+--------------------------------+-----------------------------------------+--------+-----+--------+ |
| fPCLK2 | Internal APB2 clock frequency | Over-drive OFF | 0 | - | 90 | |
| | +-----------------------------------------+--------+-----+--------+ |
| | | Over-drive ON | 0 | - | 108 | |
+------------+--------------------------------+-----------------------------------------+--------+-----+--------+------+
| VDD | Standard operating voltage | - | 1.7⁽³⁾ | - | 3.6 | V |
+------------+--------------------------------+-----------------------------------------+--------+-----+--------+ |
| VDDA⁽⁴⁾⁽⁵⁾ | Analog operating voltage | MtbthttilV⁽⁶⁾ | 1.7⁽³⁾ | - | 2.4 | |
| | (ADC limited to 1.2 M samples) | | | | | |
| +--------------------------------+---------------------------------+-------+--------+-----+--------+ |
| | Analog operating voltage | Must be the same potential as V | DD | 2.4 | - | 3.6 | |
| | (ADC limited to 2.4 M samples) | | | | | | |
+------------+--------------------------------+---------------------------------+-------+--------+-----+--------+ |
| VDDUSB | USB supply voltage (supply | USB not used | 1.7 | 3.3 | 3.6 | |
| | voltage for PA11,PA12, PB14 +-----------------------------------------+--------+-----+--------+ |
| | and PB15 pins) | USB used | 3.0 | - | 3.6 | |
+------------+--------------------------------+-----------------------------------------+--------+-----+--------+ |
| VBAT | Backup operating voltage | - | 1.65 | - | 3.6 | |
+------------+--------------------------------+---------------------------------+-------+--------+-----+--------+ |
| VDDSDMMC | SDMMC2 supply voltage (supply | It can be different from VDD | - | 1.7 | - | 3.6 | |
| | voltage for PG[12:9] and PD6 | | | | | | |
| | pins) | | | | | | |
+------------+--------------------------------+---------------------------------+-------+--------+-----+--------+ |
| VDDDSI | DSI system operating | - | 1.7 | - | 3.6 | |
+------------+--------------------------------+-----------------------------------------+--------+-----+--------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #110 ===
Table 17. General operating conditions (continued)
+--------+----------------------------------+------------------------------------+-------+------+-------+------+
| Symbol | Parameter | Conditions⁽¹⁾ | Min | Typ | Max | Unit |
+========+==================================+====================================+=======+======+=======+======+
| V12 | Regulator ON: 1.2 V internal | Power Scale 3 ((VOS[1:0] bits in | 1.08 | 1.14 | 1.20 | V |
| | voltage on VCAP_1/VCAP_2 pins | PWR_CR register = 0x01), 144 MHz | | | | |
| | | HCLK max frequency | | | | |
| | +------------------------------------+-------+------+-------+ |
| | | Power Scale 2 ((VOS[1:0] bits in | 1.20 | 1.26 | 1.32 | |
| | | PWR_CR register = 0x10), 168 MHz | | | | |
| | | HCLK max frequency with over-drive | | | | |
| | | OFF or 180 MHz with over-drive ON | | | | |
| | +------------------------------------+-------+------+-------+ |
| | | Power Scale 1 ((VOS[1:0] bits in | 1.26 | 1.32 | 1.40 | |
| | | PWR_CR register = 0x11), 180 MHz | | | | |
| | | HCLK max frequency with over-drive | | | | |
| | | OFF or 216 MHz with over-drive ON | | | | |
| +----------------------------------+------------------------------------+-------+------+-------+ |
| | Regulator OFF: 1.2 V external | Max frequency 144 MHz | 1.10 | 1.14 | 1.20 | |
| | voltage must be supplied from +------------------------------------+-------+------+-------+ |
| | external regulator on | Max frequency 168MHz | 1.20 | 1.26 | 1.32 | |
| | VCAP_1/VCAP_2 pins⁽⁷⁾ +------------------------------------+-------+------+-------+ |
| | | Max frequency 180 MHz | 1.26 | 1.32 | 1.38 | |
+--------+----------------------------------+------------------------------------+-------+------+-------+ |
| VIN | Input voltage on RST and FT | 2 V ≤ VDD ≤ 3.6 V | − 0.3 | - | 5.5 | |
| | pins⁽⁸⁾ +------------------------------------+-------+------+-------+ |
| | | VDD ≤ 2 V | − 0.3 | - | 5.2 | |
| +----------------------------------+------------------------------------+-------+------+-------+ |
| | Input voltage on TTa pins | - | − 0.3 | - | VDDA+ | |
| | | | | | 0.3 | |
| +----------------------------------+------------------------------------+-------+------+-------+ |
| | Input voltage on BOOT pin | - | 0 | - | 9 | |
+--------+----------------------------------+------------------------------------+-------+------+-------+------+
| PD | Power dissipation at TA = 85 °C | LQFP100 | - | - | 465 | mW |
| | for suffix 6 or TA = 105 °C for +------------------------------------+-------+------+-------+ |
| | suffix 7⁽⁹⁾ | WLCSP180 | - | - | 641 | |
| | +------------------------------------+-------+------+-------+ |
| | | LQFP144 | - | - | 500 | |
| | +------------------------------------+-------+------+-------+ |
| | | LQFP176 | - | - | 526 | |
| | +------------------------------------+-------+------+-------+ |
| | | UFBGA176 | - | - | 513 | |
| | +------------------------------------+-------+------+-------+ |
| | | LQFP208 | - | - | 1053 | |
| | +------------------------------------+-------+------+-------+ |
| | | TFBGA216 | - | - | 690 | |
| | +------------------------------------+-------+------+-------+ |
| | | TFBGA100 | - | - | 552 | |
+--------+----------------------------------+------------------------------------+-------+------+-------+------+
| TA | Ambient temperature for 6 suffix | Maximum power dissipation | − 40 | - | 85 | °C |
| | version +------------------------------------+-------+------+-------+ |
| | | Low power dissipation⁽¹⁰⁾ | − 40 | - | 105 | |
| +----------------------------------+------------------------------------+-------+------+-------+------+
| | Ambient temperature for 7 suffix | Maximum power dissipation | − 40 | - | 105 | °C |
| | version +------------------------------------+-------+------+-------+ |
| | | Low power dissipation⁽¹⁰⁾ | − 40 | - | 125 | |
+--------+----------------------------------+------------------------------------+-------+------+-------+------+
| TJ | Junction temperature range | 6 suffix version | − 40 | - | 105 | °C |
| | +------------------------------------+-------+------+-------+ |
| | | 7 suffix version | − 40 | - | 125 | |
+--------+----------------------------------+------------------------------------+-------+------+-------+------+
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. 216 MHz maximum frequency for 6 suffix version (200 MHz maximum frequency for 7 suffix version).
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
4. When the ADC is used, refer to Table 71: ADC characteristics.
5. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #111 ===
6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
7. The over-drive mode is not supported when the internal regulator is OFF.
8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
9. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
10. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Table 18. Limitations depending on the operating power supply range
+--------------+-----------------+----------------+-----------------------+------------------+------------------+
| Operating | ADC operation | Maximum Flash | Maximum HCLK | I/O operation | Possible Flash |
| power supply | | memory access | frequency vs Flash | | memory |
| range | | frequency with | memory wait states | | operations |
| | | no wait states | (1)(2) | | |
| | | (fFlashmax) | | | |
+==============+=================+================+=======================+==================+==================+
| VDD =1.7 to | Conversion time | 20 MHz | 180 MHz with 8 wait | No I/O | 8-bit erase and |
| 2.1 V⁽³⁾ | up to 1.2 Msps | | states and over-drive | compensation | program |
| | | | OFF | | operations only |
+--------------+-----------------+----------------+-----------------------+------------------+------------------+
| VDD = 2.1 to | Conversion time | 22 MHz | 216 MHz with 9 wait | No I/O | 16-bit erase and |
| 2.4 V | up to 1.2 Msps | | states and over-drive | compensation | program |
| | | | ON | | operations |
+--------------+-----------------+----------------+-----------------------+------------------+------------------+
| VDD = 2.4 to | Conversion time | 24 MHz | 216 MHz with 8 wait | I/O compensation | 16-bit erase and |
| 2.7 V | up to 2.4 Msps | | states and over-drive | works | program |
| | | | ON | | operations |
+--------------+-----------------+----------------+-----------------------+------------------+------------------+
| VDD = 2.7 to | Conversion time | 30 MHz | 216 MHz with 6 wait | I/O compensation | 32-bit erase and |
| 3.6 V⁽⁴⁾ | up to 2.4 Msps | | states and over-drive | works | program |
| | | | ON | | operations |
+--------------+-----------------+----------------+-----------------------+------------------+------------------+
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here
does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a
performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+
pins are degraded between 2.7 and 3 V.
6.3.2 VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP1/VCAP2 pins. CEXT is specified in Table 19.
Figure 27. External capacitor CEXT
1. Legend: ESR is the equivalent series resistance.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #112 ===
Table 19. VCAP1/VCAP2 operating conditions⁽¹⁾
+--------+-----------------------------------+------------+
| Symbol | Parameter | Conditions |
+========+===================================+============+
| CEXT | Capacitance of external capacitor | 2.2 µF |
+--------+-----------------------------------+------------+
| ESR | ESR of external capacitor | < 2 Ω |
+--------+-----------------------------------+------------+
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
6.3.3 Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for TA.
Table 20. Operating conditions at power-up / power-down (regulator ON)
+--------+--------------------+-----+-----+------+
| Symbol | Parameter | Min | Max | Unit |
+========+====================+=====+=====+======+
| tVDD | VDD rise time rate | 20 | ∞ | µs/V |
| +--------------------+-----+-----+ |
| | VDD fall time rate | 20 | ∞ | |
+--------+--------------------+-----+-----+------+
6.3.4 Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for TA.
Table 21. Operating conditions at power-up / power-down (regulator OFF)⁽¹⁾
+--------+----------------------------------+------------+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Max | Unit |
+========+==================================+============+=====+=====+======+
| tVDD | VDD rise time rate | Power-up | 20 | ∞ | µs/V |
| +----------------------------------+------------+-----+-----+ |
| | VDD fall time rate | Power-down | 20 | ∞ | |
+--------+----------------------------------+------------+-----+-----+ |
| tVCAP | VCAP_1 and VCAP_2 rise time rate | Power-up | 20 | ∞ | |
| +----------------------------------+------------+-----+-----+ |
| | VCAP_1 and VCAP_2 fall time rate | Power-down | 20 | ∞ | |
+--------+----------------------------------+------------+-----+-----+------+
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
6.3.5 Reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #113 ===
Table 22. Reset and power control block characteristics
+-------------+--------------------------+-----------------------------+------+------+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=============+==========================+=============================+======+======+======+======+
| VPVD | Programmable voltage | PLS[2:0]=000 (rising edge) | 2.09 | 2.14 | 2.19 | V |
| | detector level selection +-----------------------------+------+------+------+------+
| | | PLS[2:0]=000 (falling edge) | 1.98 | 2.04 | 2.08 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=001 (rising edge) | 2.23 | 2.30 | 2.37 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=001 (falling edge) | 2.13 | 2.19 | 2.25 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=010 (rising edge) | 2.39 | 2.45 | 2.51 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=010 (falling edge) | 2.29 | 2.35 | 2.39 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=011 (rising edge) | 2.54 | 2.60 | 2.65 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=011 (falling edge) | 2.44 | 2.51 | 2.56 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=100 (rising edge) | 2.70 | 2.76 | 2.82 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=100 (falling edge) | 2.59 | 2.66 | 2.71 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=101 (rising edge) | 2.86 | 2.93 | 2.99 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=101 (falling edge) | 2.65 | 2.84 | 2.92 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=110 (rising edge) | 2.96 | 3.03 | 3.10 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=110 (falling edge) | 2.85 | 2.93 | 2.99 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=111 (rising edge) | 3.07 | 3.14 | 3.21 | V |
| | +-----------------------------+------+------+------+------+
| | | PLS[2:0]=111 (falling edge) | 2.95 | 3.03 | 3.09 | V |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| VPVDhyst⁽¹⁾ | PVD hysteresis | - | - | 100 | - | mV |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| VPOR/PDR | Power-on/power-down | Falling edge | 1.60 | 1.68 | 1.76 | V |
| | reset threshold +-----------------------------+------+------+------+------+
| | | Rising edge | 1.64 | 1.72 | 1.80 | V |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| VPDRhyst⁽¹⁾ | PDR hysteresis | - | - | 40 | - | mV |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| VBOR1 | Brownout level 1 | Falling edge | 2.13 | 2.19 | 2.24 | V |
| | threshold +-----------------------------+------+------+------+------+
| | | Rising edge | 2.23 | 2.29 | 2.33 | V |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| VBOR2 | Brownout level 2 | Falling edge | 2.44 | 2.50 | 2.56 | V |
| | threshold +-----------------------------+------+------+------+------+
| | | Rising edge | 2.53 | 2.59 | 2.63 | V |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| VBOR3 | Brownout level 3 | Falling edge | 2.75 | 2.83 | 2.88 | V |
| | threshold +-----------------------------+------+------+------+------+
| | | Rising edge | 2.85 | 2.92 | 2.97 | V |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| VBORhyst⁽¹⁾ | BOR hysteresis | - | - | 100 | - | mV |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| TRSTTEMPO | POR reset temporization | - | 0.5 | 1.5 | 3.0 | ms |
| (1)(2) | | | | | | |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| IRUSH⁽¹⁾ | InRush current on | - | - | 160 | 250 | mA |
| | voltage regulator power- | | | | | |
| | on (POR or wakeup | | | | | |
| | from Standby) | | | | | |
+-------------+--------------------------+-----------------------------+------+------+------+------+
| ERUSH⁽¹⁾ | InRush energy on | VDD = 1.7 V, TA = 105 °C, | - | - | 5.4 | µC |
| | voltage regulator power- | IRUSH = 171 mA for 31 µs | | | | |
| | on (POR or wakeup | | | | | |
| | from Standby) | | | | | |
+-------------+--------------------------+-----------------------------+------+------+------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #114 ===
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant
when first instruction is read by the user application code.
6.3.6 Over-drive switching characteristics
When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 23. They are subject to general
operating conditions for TA.
Table 23. Over-drive switching characteristics⁽¹⁾
+-----------+-------------------+---------------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+===================+=====================+=====+=====+=====+======+
| Tod_swen | Over_drive switch | HSI | - | 45 | - | µs |
| | enable time +---------------------+-----+-----+-----+ |
| | | HSE max for 4 MHz | 45 | - | 100 | |
| | | and min for 26 MHz | | | | |
| | +---------------------+-----+-----+-----+ |
| | | External HSE | - | 40 | - | |
| | | 50 MHz | | | | |
+-----------+-------------------+---------------------+-----+-----+-----+ |
| Tod_swdis | Over_drive switch | HSI | - | 20 | - | |
| | disable time +---------------------+-----+-----+-----+ |
| | | HSE max for 4 MHz | 20 | - | 80 | |
| | | and min for 26 MHz. | | | | |
| | +---------------------+-----+-----+-----+ |
| | | External HSE | - | 15 | - | |
| | | 50 MHz | | | | |
+-----------+-------------------+---------------------+-----+-----+-----+------+
1. Guaranteed by design.
6.3.7 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 26: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #115 ===
Typical and maximum current consumption
The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at VDD or VSS (no load).
• All peripherals are disabled except if it is explicitly mentioned.
• The Flash memory access time is adjusted both to fHCLK frequency and VDD range
(see Table 18: Limitations depending on the operating power supply range).
• When the regulator is ON, the voltage scaling and over-drive mode are adjusted to
fHCLK frequency as follows:
– Scale 3 for fHCLK ≤ 144 MHz
– Scale 2 for 144 MHz < fHCLK ≤ 168 MHz
– Scale 1 for 168 MHz < fHCLK ≤ 216 MHz. The over-drive is only ON at 216 MHz.
• When the regulator is OFF, the V12 is provided externally as described in Table 17:
General operating conditions:
• The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
• External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz.
• The typical current consumption values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage
range and for TA= 25 °C unless otherwise specified.
• The maximum values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage range and a
maximum ambient temperature (TA) unless otherwise specified.
• For the voltage range 1.7 V ≤ VDD ≤ 3.6 V, the maximum frequency is 180 MHz.
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON
+--------+------------+-----------------+-------------+-----+---------------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK (MHz) | Typ | Max⁽¹⁾ | Unit |
| | | | | +------------+------------+-------------+ |
| | | | | | TA = 25 °C | TA = 85 °C | TA = 105 °C | |
+--------+------------+-----------------+-------------+-----+------------+------------+-------------+======+
| IDD | Supply | All peripherals | 216 | 193 | 221⁽⁴⁾ | 258⁽⁴⁾ | - | mA |
| | current in | enabled⁽²⁾⁽³⁾ +-------------+-----+------------+------------+-------------+ |
| | RUN mode | | 200 | 179 | 207 | 244 | 279 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 180 | 159 | 176⁽⁴⁾ | 210⁽⁴⁾ | 238⁽⁴⁾ | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 168 | 142 | 156 | 187 | 211 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 144 | 122 | 135 | 167 | 190 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 60 | 49 | 55 | 81 | 103 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 25 | 23 | 28 | 54 | 76 | |
| | +-----------------+-------------+-----+------------+------------+-------------+ |
| | | All peripherals | 216 | 95 | 107⁽⁴⁾ | 153⁽⁴⁾ | - | |
| | | disabled⁽³⁾ +-------------+-----+------------+------------+-------------+ |
| | | | 200 | 88 | 100 | 146 | 180 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 180 | 78 | 88⁽⁴⁾ | 122⁽⁴⁾ | 147⁽⁴⁾ | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 168 | 70 | 78 | 109 | 133 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 144 | 60 | 68 | 99 | 123 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 60 | 24 | 29 | 55 | 76 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 25 | 12 | 16 | 42 | 63 | |
+--------+------------+-----------------+-------------+-----+------------+------------+-------------+------+
1. Guaranteed by characterization results, unless otherwise specified.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #116 ===
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
4. Guaranteed by test in production.
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON
+--------+------------+-----------------+-------------+-----+---------------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK (MHz) | Typ | Max⁽¹⁾ | Unit |
| | | | | +------------+------------+-------------+ |
| | | | | | TA = 25 °C | TA = 85 °C | TA = 105 °C | |
+--------+------------+-----------------+-------------+-----+------------+------------+-------------+======+
| IDD | Supply | All peripherals | 216 | 190 | 219 | 255 | - | mA |
| | current in | enabled⁽²⁾⁽³⁾ +-------------+-----+------------+------------+-------------+ |
| | RUN mode | | 200 | 177 | 205 | 241 | 268 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 180 | 157 | 173 | 208 | 228 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 168 | 139 | 153 | 185 | 204 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 144 | 107 | 117 | 144 | 161 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 60 | 48 | 54 | 81 | 98 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 25 | 23 | 28 | 54 | 71 | |
| | +-----------------+-------------+-----+------------+------------+-------------+ |
| | | All peripherals | 216 | 92 | 104 | 150 | - | |
| | | disabled⁽³⁾ +-------------+-----+------------+------------+-------------+ |
| | | | 200 | 86 | 97 | 143 | 170 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 180 | 76 | 85 | 119 | 140 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 168 | 67 | 75 | 107 | 126 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 144 | 52 | 58 | 84 | 101 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 60 | 23 | 28 | 54 | 71 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 25 | 11 | 15 | 42 | 56 | |
+--------+------------+-----------------+-------------+-----+------------+------------+-------------+------+
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #117 ===
Table 26. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON),
regulator ON
+--------+------------+-----------------+-------------+-----+---------------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK (MHz) | Typ | Max⁽¹⁾ | Unit |
| | | | | +------------+------------+-------------+ |
| | | | | | TA = 25 °C | TA = 85 °C | TA = 105 °C | |
+--------+------------+-----------------+-------------+-----+------------+------------+-------------+======+
| IDD | Supply | All peripherals | 216 | 190 | 219 | 255 | - | mA |
| | current in | enabled⁽²⁾⁽³⁾ +-------------+-----+------------+------------+-------------+ |
| | RUN mode | | 200 | 177 | 204 | 242 | 268 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 180 | 157 | 173 | 208 | 228 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 168 | 139 | 153 | 185 | 204 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 144 | 107 | 117 | 144 | 161 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 60 | 48 | 54 | 81 | 98 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 25 | 23 | 28 | 54 | 71 | |
| | +-----------------+-------------+-----+------------+------------+-------------+ |
| | | All peripherals | 216 | 92 | 104 | 150 | - | |
| | | disabled⁽³⁾ +-------------+-----+------------+------------+-------------+ |
| | | | 200 | 86 | 97 | 143 | 170 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 180 | 76 | 85 | 119 | 140 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 168 | 67 | 75 | 107 | 126 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 144 | 52 | 58 | 84 | 101 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 60 | 23 | 28 | 54 | 71 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 25 | 11 | 15 | 42 | 59 | |
+--------+------------+-----------------+-------------+-----+------------+------------+-------------+------+
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #118 ===
Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (Single bank mode) or SRAM on AXI (L1-cache disabled),
regulator ON
+--------+------------+-----------------+-------------+-----+----------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK (MHz) | Typ | Max⁽¹⁾ | Unit |
| | | | | +-----------+----------+-----------+ |
| | | | | | TA= 25 °C | TA=85 °C | TA=105 °C | |
+--------+------------+-----------------+-------------+-----+-----------+----------+-----------+======+
| IDD | Supply | All peripherals | 216 | 190 | 209 | 255 | - | mA |
| | current in | enabled⁽²⁾⁽³⁾ +-------------+-----+-----------+----------+-----------+ |
| | RUN mode | | 200 | 177 | 194 | 241 | 268 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 180 | 160 | 175 | 211 | 232 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 168 | 144 | 156 | 189 | 209 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 144 | 115 | 125 | 152 | 170 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 60 | 56 | 62 | 89 | 107 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 25 | 27 | 32 | 59 | 79 | |
| | +-----------------+-------------+-----+-----------+----------+-----------+ |
| | | All peripherals | 216 | 92 | 103 | 150 | - | |
| | | disabled⁽³⁾ +-------------+-----+-----------+----------+-----------+ |
| | | | 200 | 86 | 96 | 243 | 171 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 180 | 79 | 87 | 123 | 144 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 168 | 71 | 79 | 111 | 131 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 144 | 60 | 65 | 92 | 110 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 60 | 32 | 36 | 63 | 80 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 25 | 16 | 20 | 46 | 64 | |
+--------+------------+-----------------+-------------+-----+-----------+----------+-----------+------+
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #119 ===
Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (Dual bank mode), regulator ON
+--------+------------+-----------------+-------------+-----+----------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK (MHz) | Typ | Max⁽¹⁾ | Unit |
| | | | | +-----------+----------+-----------+ |
| | | | | | TA= 25 °C | TA=85 °C | TA=105 °C | |
+--------+------------+-----------------+-------------+-----+-----------+----------+-----------+======+
| IDD | Supply | All peripherals | 216 | 176 | 194 | 240 | - | mA |
| | current in | enabled⁽²⁾⁽³⁾ +-------------+-----+-----------+----------+-----------+ |
| | RUN mode | | 200 | 164 | 181 | 227 | 255 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 180 | 149 | 163 | 198 | 220 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 168 | 133 | 145 | 178 | 198 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 144 | 106 | 116 | 143 | 161 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 60 | 54 | 60 | 87 | 105 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 25 | 27 | 31 | 58 | 76 | |
| | +-----------------+-------------+-----+-----------+----------+-----------+ |
| | | All peripherals | 216 | 77 | 88 | 135 | - | |
| | | disabled⁽³⁾ +-------------+-----+-----------+----------+-----------+ |
| | | | 200 | 72 | 82 | 129 | 157 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 180 | 67 | 75 | 110 | 131 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 168 | 60 | 67 | 99 | 120 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 144 | 50 | 56 | 83 | 101 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 60 | 29 | 34 | 60 | 78 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 25 | 15 | 19 | 45 | 63 | |
+--------+------------+-----------------+-------------+-----+-----------+----------+-----------+------+
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #120 ===
Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (Single bank mode) on ITCM interface (ART disabled),
regulator ON
+--------+------------+-----------------+-------------+-----+----------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK (MHz) | Typ | Max⁽¹⁾ | Unit |
| | | | | +-----------+----------+-----------+ |
| | | | | | TA= 25 °C | TA=85 °C | TA=105 °C | |
+--------+------------+-----------------+-------------+-----+-----------+----------+-----------+======+
| IDD | Supply | All peripherals | 216 | 215 | 242 | 281 | - | mA |
| | current in | enabled⁽²⁾⁽³⁾ +-------------+-----+-----------+----------+-----------+ |
| | RUN mode | | 200 | 200 | 218 | 265 | 293 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 180 | 185 | 200 | 237 | 258 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 168 | 166 | 179 | 213 | 233 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 144 | 134 | 144 | 172 | 190 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 60 | 61 | 68 | 95 | 112 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 25 | 29 | 34 | 61 | 78 | |
| | +-----------------+-------------+-----+-----------+----------+-----------+ |
| | | All peripherals | 216 | 118 | 129 | 177 | - | |
| | | disabled⁽³⁾ +-------------+-----+-----------+----------+-----------+ |
| | | | 200 | 110 | 120 | 168 | 196 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 180 | 104 | 113 | 149 | 170 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 168 | 94 | 102 | 135 | 155 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 144 | 79 | 85 | 113 | 130 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 60 | 37 | 42 | 69 | 86 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 25 | 18 | 22 | 48 | 66 | |
+--------+------------+-----------------+-------------+-----+-----------+----------+-----------+------+
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #121 ===
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (Dual bank mode) on ITCM interface (ART disabled),
regulator ON
+--------+------------+-----------------+-------------+-----+----------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK (MHz) | Typ | Max⁽¹⁾ | Unit |
| | | | | +-----------+----------+-----------+ |
| | | | | | TA= 25 °C | TA=85 °C | TA=105 °C | |
+--------+------------+-----------------+-------------+-----+-----------+----------+-----------+======+
| IDD | Supply | All peripherals | 216 | 191 | 218 | 255 | - | mA |
| | current in | enabled⁽²⁾⁽³⁾ +-------------+-----+-----------+----------+-----------+ |
| | RUN mode | | 200 | 178 | 195 | 241 | 269 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 180 | 164 | 179 | 214 | 236 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 168 | 147 | 160 | 192 | 212 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 144 | 121 | 130 | 157 | 175 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 60 | 60 | 66 | 93 | 111 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 25 | 28 | 33 | 59 | 77 | |
| | +-----------------+-------------+-----+-----------+----------+-----------+ |
| | | All peripherals | 216 | 93 | 104 | 150 | - | |
| | | disabled⁽³⁾ +-------------+-----+-----------+----------+-----------+ |
| | | | 200 | 87 | 97 | 144 | 171 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 180 | 83 | 92 | 126 | 148 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 168 | 75 | 82 | 114 | 134 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 144 | 65 | 71 | 97 | 115 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 60 | 35 | 40 | 66 | 84 | |
| | | +-------------+-----+-----------+----------+-----------+ |
| | | | 25 | 16 | 20 | 47 | 64 | |
+--------+------------+-----------------+-------------+-----+-----------+----------+-----------+------+
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #122 ===
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF
+--------+------------+---------------+-------+-------------+-----------------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK | T | Max⁽¹⁾ | Unit |
| | | | (MHz) +-------+-----+-------------+-------------+-------------+ |
| | | | | Ty | p | TA= 25 °C | TA= 85 °C | TA= 105 °C | |
| | | | +-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | | IDD12 | IDD | IDD12 | IDD | IDD12 | IDD | IDD12 | IDD | |
+--------+------------+---------------+-------+-------+-----+-------+-----+-------+-----+-------+-----+======+
| IDD12/ | Supply | All | 180 | 152 | 1 | 167 | 2 | 200 | 2 | 220 | 2 | mA |
| IDD | current in | Peripherals +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | RUN mode | Enabled⁽²⁾⁽³⁾ | 168 | 136 | 1 | 148 | 2 | 179 | 2 | 198 | 2 | |
| | from V12 | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | and VDD | | 144 | 105 | 1 | 115 | 2 | 141 | 2 | 158 | 2 | |
| | supply | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 60 | 47 | 1 | 53 | 2 | 79 | 2 | 96 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 25 | 22 | 1 | 27 | 2 | 53 | 2 | 70 | 2 | |
| | +---------------+-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | All | 180 | 74 | 1 | 83 | 2 | 116 | 2 | 136 | 2 | |
| | | Peripherals +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | Disabled⁽³⁾ | 168 | 65 | 1 | 73 | 2 | 104 | 2 | 123 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 144 | 50 | 1 | 57 | 2 | 83 | 2 | 100 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 60 | 22 | 1 | 27 | 2 | 53 | 2 | 70 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 25 | 10 | 1 | 14 | 2 | 41 | 2 | 58 | 2 | |
+--------+------------+---------------+-------+-------+-----+-------+-----+-------+-----+-------+-----+------+
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
Table 32. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF
+--------+------------+---------------+-------+-------------+-----------------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK | T | Max⁽¹⁾ | Unit |
| | | | (MHz) +-------+-----+-------------+-------------+-------------+ |
| | | | | Ty | p | TA= 25 °C | TA= 85 °C | TA= 105 °C | |
| | | | +-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | | IDD12 | IDD | IDD12 | IDD | IDD12 | IDD | IDD12 | IDD | |
+--------+------------+---------------+-------+-------+-----+-------+-----+-------+-----+-------+-----+======+
| IDD12/ | Supply | All | 180 | 152 | 1 | 167 | 2 | 200 | 2 | 220 | 2 | mA |
| IDD | current in | Peripherals +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | RUN mode | Enabled⁽²⁾⁽³⁾ | 168 | 136 | 1 | 148 | 2 | 179 | 2 | 198 | 2 | |
| | from V12 | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | and VDD | | 144 | 105 | 1 | 115 | 2 | 141 | 2 | 158 | 2 | |
| | supply | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 60 | 47 | 1 | 53 | 2 | 79 | 2 | 96 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 25 | 22 | 1 | 27 | 2 | 53 | 2 | 70 | 2 | |
| | +---------------+-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | All | 180 | 74 | 1 | 82 | 2 | 114 | 2 | 137 | 2 | |
| | | Peripherals +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | Disabled⁽³⁾ | 168 | 65 | 1 | 73 | 2 | 104 | 2 | 123 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 144 | 50 | 1 | 57 | 2 | 83 | 2 | 100 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 60 | 22 | 1 | 27 | 2 | 53 | 2 | 70 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 25 | 10 | 1 | 14 | 2 | 41 | 2 | 58 | 2 | |
+--------+------------+---------------+-------+-------+-----+-------+-----+-------+-----+-------+-----+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #123 ===
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
Table 33. Typical and maximum current consumption in Sleep mode, regulator ON
+--------+------------+-------------+-------------+-----+---------------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK (MHz) | Typ | Max⁽¹⁾ | Unit |
| | | | | +------------+------------+-------------+ |
| | | | | | TA = 25 °C | TA = 85 °C | TA = 105 °C | |
+--------+------------+-------------+-------------+-----+------------+------------+-------------+======+
| IDD | Supply | All | 216 | 128 | 144⁽³⁾ | 190⁽³⁾ | - | mA |
| | current in | peripherals +-------------+-----+------------+------------+-------------+ |
| | Sleep mode | enabled⁽²⁾ | 200 | 119 | 134 | 180 | 214 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 180 | 105 | 118⁽³⁾ | 153⁽³⁾ | 178⁽³⁾ | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 168 | 93 | 105 | 136 | 156 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 144 | 72 | 80 | 107 | 124 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 60 | 33 | 39 | 65 | 82 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 25 | 17 | 21 | 47 | 65 | |
| | +-------------+-------------+-----+------------+------------+-------------+ |
| | | All | 216 | 18 | 25⁽³⁾ | 71⁽³⁾ | - | |
| | | peripherals +-------------+-----+------------+------------+-------------+ |
| | | disabled | 200 | 17 | 24 | 70 | 112 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 180 | 14 | 20⁽³⁾ | 54⁽³⁾ | 75⁽³⁾ | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 168 | 13 | 18 | 49 | 69 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 144 | 10 | 14 | 40 | 58 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 60 | 6 | 10 | 36 | 53 | |
| | | +-------------+-----+------------+------------+-------------+ |
| | | | 25 | 4 | 8 | 34 | 51 | |
+--------+------------+-------------+-------------+-----+------------+------------+-------------+------+
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. Guaranteed by test in production.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #124 ===
Table 34. Typical and maximum current consumption in Sleep mode, regulator OFF
+--------+------------+-------------+-------+-------------+-----------------------------------------+------+
| Symbol | Parameter | Conditions | fHCLK | T | Max⁽¹⁾ | Unit |
| | | | (MHz) +-------+-----+-------------+-------------+-------------+ |
| | | | | Ty | p | TA= 25 °C | TA= 85 °C | TA= 105 °C | |
| | | | +-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | | IDD12 | IDD | IDD12 | IDD | IDD12 | IDD | IDD12 | IDD | |
+--------+------------+-------------+-------+-------+-----+-------+-----+-------+-----+-------+-----+======+
| IDD12/ | Supply | All | 180 | 102 | 1 | 114 | 2 | 148 | 2 | 168 | 2 | mA |
| IDD | current in | Peripherals +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | RUN mode | Enabled⁽²⁾ | 168 | 91 | 1 | 101 | 2 | 132 | 2 | 152 | 2 | |
| | from V12 | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | and VDD | | 144 | 71 | 1 | 78 | 2 | 105 | 2 | 122 | 2 | |
| | supply | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 60 | 32 | 1 | 37 | 2 | 64 | 2 | 81 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 25 | 16 | 1 | 20 | 2 | 46 | 2 | 64 | 2 | |
| | +-------------+-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | All | 180 | 13 | 1 | 18 | 2 | 53 | 2 | 73 | 2 | |
| | | Peripherals +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | Disabled | 168 | 12 | 1 | 16 | 2 | 47 | 2 | 67 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 144 | 9 | 1 | 13 | 2 | 39 | 2 | 56 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 60 | 5 | 1 | 9 | 2 | 35 | 2 | 52 | 2 | |
| | | +-------+-------+-----+-------+-----+-------+-----+-------+-----+ |
| | | | 25 | 3 | 1 | 7 | 2 | 33 | 2 | 50 | 2 | |
+--------+------------+-------------+-------+-------+-----+-------+-----+-------+-----+-------+-----+------+
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
Table 35. Typical and maximum current consumptions in Stop mode
+---------------+-------------------------+------------------------------------+-------+------------------------+------+
| Symbol | Parameter | Conditions | Typ | Max⁽¹⁾ | Unit |
| | | | +========================+ |
| | | | | VDD = 3.6 V | |
| | | +=======+-------+-------+--------+ |
| | | | TA = | TA = | TA = | TA = | |
| | | | 25 °C | 25 °C | 85 °C | 105 °C | |
+===============+=========================+====================================+-------+-------+-------+--------+======+
| IDD_STOP_NM | Supply current in Stop | Flash memory in Stop mode, | 0.55 | 3 | 18 | 27 | mA |
| (normal mode) | mode, main regulator in | all oscillators OFF, no IWDG | | | | | |
| | Run mode +------------------------------------+-------+-------+-------+--------+ |
| | | Flash memory in Deep power | 0.5 | 3 | 18 | 27 | |
| | | down mode, all oscillators OFF | | | | | |
| +-------------------------+------------------------------------+-------+-------+-------+--------+ |
| | Supply current in Stop | Flash memory in Stop mode, all | 0.42 | 2.5 | 15 | 24 | |
| | mode, main regulator in | oscillators OFF, no IWDG | | | | | |
| | Low-power mode +------------------------------------+-------+-------+-------+--------+ |
| | | Flash memory in Deep power | 0.37 | 2.5 | 15 | 24 | |
| | | down mode, all oscillators OFF, no | | | | | |
| | | IWDG | | | | | |
+---------------+-------------------------+------------------------------------+-------+-------+-------+--------+ |
| IDD_STOP_UDM | Supply current in Stop | Regulator in Run mode, Flash | 0.18 | 1.2 | 6 | 10 | |
| (under-drive | mode, main regulator in | memory in Deep power down | | | | | |
| mode) | Low voltage and under- | mode, all oscillators OFF, no | | | | | |
| | drive modes | IWDG | | | | | |
| | +------------------------------------+-------+-------+-------+--------+ |
| | | Regulator in Low-power mode, | 0.13 | 1.1 | 6 | 10 | |
| | | Flash memory in Deep power | | | | | |
| | | down mode, all oscillators OFF, no | | | | | |
| | | IWDG | | | | | |
+---------------+-------------------------+------------------------------------+-------+-------+-------+--------+------+
1. Data based on characterization, tested in production.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #125 ===
Table 36. Typical and maximum current consumptions in Standby mode
+----------+----------------+------------------------------+-----------------------+------------------------+------+
| Symbol | Parameter | Conditions | Typ⁽¹⁾ | Max⁽²⁾ | Unit |
| | | +-----------------------+-------+-------+--------+ |
| | | | TA = 25 °C | TA = | TA = | TA = | |
| | | | | 25 °C | 85 °C | 105 °C | |
| | | +-------+-------+-------+------------------------+ |
| | | | VDD = | VDD= | VDD = | VDD = 3.3 V | |
| | | | 1.7 V | 2.4 V | 3.3 V | | |
+----------+----------------+------------------------------+-------+-------+-------+-------+-------+--------+======+
| IDD_STBY | Supply current | Backup SRAM OFF, RTC and | 1.1 | 1.9 | 2.4 | 5(3) | 18⁽³⁾ | 38⁽³⁾ | µA |
| | in Standby | LSE OFF | | | | | | | |
| | mode +------------------------------+-------+-------+-------+-------+-------+--------+ |
| | | Backup SRAM ON, RTC and | 1.9 | 2.7 | 3.2 | 6(3) | 23⁽³⁾ | 48⁽³⁾ | |
| | | LSE OFF | | | | | | | |
| | +------------------------------+-------+-------+-------+-------+-------+--------+ |
| | | Backup SRAM OFF, RTC ON | 1.7 | 2.7 | 3.5 | 7 | 26 | 55 | |
| | | and LSE in low drive mode | | | | | | | |
| | +------------------------------+-------+-------+-------+-------+-------+--------+ |
| | | Backup SRAM OFF, RTC ON | 1.7 | 2.7 | 3.5 | 7 | 26 | 56 | |
| | | and LSE in medium low drive | | | | | | | |
| | | mode | | | | | | | |
| | +------------------------------+-------+-------+-------+-------+-------+--------+ |
| | | Backup SRAM OFF, RTC ON | 1.8 | 2.8 | 3.6 | 8 | 28 | 57 | |
| | | and LSE in medium high drive | | | | | | | |
| | | mode | | | | | | | |
| | +------------------------------+-------+-------+-------+-------+-------+--------+ |
| | | Backup SRAM OFF, RTC ON | 1.9 | 2.9 | 3.7 | 8 | 28 | 59 | |
| | | and LSE in high drive mode | | | | | | | |
| | +------------------------------+-------+-------+-------+-------+-------+--------+ |
| | | Backup SRAM ON, RTC ON | 2.4 | 3.4 | 4.3 | 8 | 31 | 65 | |
| | | and LSE in low drive mode | | | | | | | |
| | +------------------------------+-------+-------+-------+-------+-------+--------+ |
| | | Backup SRAM ON, RTC ON | 2.4 | 3.5 | 4.3 | 8 | 31 | 65 | |
| | | and LSE in Medium low drive | | | | | | | |
| | | mode | | | | | | | |
| | +------------------------------+-------+-------+-------+-------+-------+--------+ |
| | | Backup SRAM ON, RTC ON | 2.6 | 3.7 | 4.5 | 8 | 33 | 68 | |
| | | and LSE in Medium high drive | | | | | | | |
| | | mode | | | | | | | |
| | +------------------------------+-------+-------+-------+-------+-------+--------+ |
| | | Backup SRAM ON, RTC ON | 2.6 | 3.7 | 4.5 | 9 | 33 | 68 | |
| | | and LSE in High drive mode | | | | | | | |
+----------+----------------+------------------------------+-------+-------+-------+-------+-------+--------+------+
1. The typical current consumption values are given with PDR OFF (internal reset OFF). When the PDR is OFF (internal reset
OFF), the typical current consumption is reduced by additional 1.2 µA.
2. Guaranteed by characterization results, unless otherwise specified.
3. Guaranteed by test in production.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #126 ===
Table 37. Typical and maximum current consumptions in VBAT mode
+----------+----------------+-------------------------------+------------------------+------------------------+------+
| Symbol | Parameter | Conditions⁽¹⁾ | Typ | Max⁽²⁾ | Unit |
| | | +------------------------+-----------+------------+ |
| | | | TA =25 °C | TA =85 °C | TA =105 °C | |
| | | +--------+-------+-------+------------------------+ |
| | | | VBAT = | VBAT= | VBAT= | VBAT = 3.6 V | |
| | | | 1.7 V | 2.4 V | 3.3 V | | |
+----------+----------------+-------------------------------+--------+-------+-------+-----------+------------+======+
| IDD_VBAT | Supply current | Backup SRAM OFF, RTC and | 0.03 | 0.04 | 0.04 | 0.2 | 0.4 | µA |
| | in VBAT mode | LSE OFF | | | | | | |
| | +-------------------------------+--------+-------+-------+-----------+------------+ |
| | | Backup SRAM ON, RTC and | 0.77 | 0.78 | 0.83 | 3.2 | 7.4 | |
| | | LSE OFF | | | | | | |
| | +-------------------------------+--------+-------+-------+-----------+------------+ |
| | | Backup SRAM OFF, RTC ON | 0.62 | 0.8 | 1.13 | 4.4 | 10.2 | |
| | | and LSE in low drive mode | | | | | | |
| | +-------------------------------+--------+-------+-------+-----------+------------+ |
| | | Backup SRAM OFF, RTC ON | 0.65 | 0.83 | 1.17 | 4.6 | 10.6 | |
| | | and LSE in medium low drive | | | | | | |
| | | mode | | | | | | |
| | +-------------------------------+--------+-------+-------+-----------+------------+ |
| | | Backup SRAM OFF, RTC ON | 0.75 | 0.94 | 1.28 | 5.0 | 11.4 | |
| | | and LSE in medium high drive | | | | | | |
| | | mode | | | | | | |
| | +-------------------------------+--------+-------+-------+-----------+------------+ |
| | | Backup SRAM OFF, RTC ON | 0.9 | 1.08 | 1.43 | 5.5 | 12.8 | |
| | | and LSE in high drive mode | | | | | | |
| | +-------------------------------+--------+-------+-------+-----------+------------+ |
| | | Backup SRAM ON, RTC ON and | 1.35 | 1.54 | 1.91 | 7.3 | 17.2 | |
| | | LSE in low drive mode | | | | | | |
| | +-------------------------------+--------+-------+-------+-----------+------------+ |
| | | Backup SRAM ON, RTC ON and | 1.38 | 1.57 | 1.93 | 7.9 | 18.4 | |
| | | LSE in Medium low drive mode | | | | | | |
| | +-------------------------------+--------+-------+-------+-----------+------------+ |
| | | Backup SRAM ON, RTC ON and | 1.53 | 1.73 | 2.11 | 8.0 | 18.7 | |
| | | LSE in Medium high drive mode | | | | | | |
| | +-------------------------------+--------+-------+-------+-----------+------------+ |
| | | Backup SRAM ON, RTC ON and | 1.67 | 1.87 | 2.26 | 9.0 | 21.0 | |
| | | LSE in High drive mode | | | | | | |
+----------+----------------+-------------------------------+--------+-------+-------+-----------+------------+------+
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization results.
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 65: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #127 ===
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 39: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
Table 38. Switching output I/O current consumption⁽¹⁾
+--------+---------------+----------------------+-----------------+-------------+-------------+------+
| Symbol | Parameter | Conditions | I/O toggling | Typ | Typ | Unit |
| | | | frequency (fsw) | VDD = 3.3 V | VDD = 1.8 V | |
| | | | MHz | | | |
+========+===============+======================+=================+=============+=============+======+
| IDDIO | I/O switching | CEXT = 0 pF | 2 | 0.1 | 0.1 | mA |
| | Current | C = CINT + CS + CEXT +-----------------+-------------+-------------+ |
| | | | 8 | 0.4 | 0.2 | |
| | | +-----------------+-------------+-------------+ |
| | | | 25 | 1.1 | 0.7 | |
| | | +-----------------+-------------+-------------+ |
| | | | 50 | 2.4 | 1.3 | |
| | | +-----------------+-------------+-------------+ |
| | | | 60 | 3.1 | 1.6 | |
| | | +-----------------+-------------+-------------+ |
| | | | 84 | 4.3 | 2.4 | |
| | | +-----------------+-------------+-------------+ |
| | | | 90 | 4.9 | 2.6 | |
| | | +-----------------+-------------+-------------+ |
| | | | 100 | 5.4 | 2.8 | |
| | +----------------------+-----------------+-------------+-------------+ |
| | | CEXT = 10 pF | 2 | 0.2 | 0.1 | |
| | | C = CINT + CS + CEXT +-----------------+-------------+-------------+ |
| | | | 8 | 0.6 | 0.3 | |
| | | +-----------------+-------------+-------------+ |
| | | | 25 | 1.8 | 1.1 | |
| | | +-----------------+-------------+-------------+ |
| | | | 50 | 3.1 | 2.3 | |
| | | +-----------------+-------------+-------------+ |
| | | | 60 | 4.6 | 3.4 | |
| | | +-----------------+-------------+-------------+ |
| | | | 84 | 9.7 | 3.6 | |
| | | +-----------------+-------------+-------------+ |
| | | | 90 | 10.12 | 5.2 | |
| | | +-----------------+-------------+-------------+ |
| | | | 100 | 14.92 | 5.4 | |
+--------+---------------+----------------------+-----------------+-------------+-------------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #128 ===
Table 38. Switching output I/O current consumption⁽¹⁾ (continued)
+--------+---------------+----------------------+-----------------+-------------+-------------+------+
| Symbol | Parameter | Conditions | I/O toggling | Typ | Typ | Unit |
| | | | frequency (fsw) | VDD = 3.3 V | VDD = 1.8 V | |
| | | | MHz | | | |
+========+===============+======================+=================+=============+=============+======+
| IDDIO | I/O switching | CEXT = 22 pF | 2 | 0.3 | 0.1 | mA |
| | Current | C = CINT + CS + CEXT +-----------------+-------------+-------------+ |
| | | | 8 | 1.0 | 0.5 | |
| | | +-----------------+-------------+-------------+ |
| | | | 25 | 3.5 | 1.6 | |
| | | +-----------------+-------------+-------------+ |
| | | | 50 | 5.9 | 4.2 | |
| | | +-----------------+-------------+-------------+ |
| | | | 60 | 10.0 | 4.4 | |
| | | +-----------------+-------------+-------------+ |
| | | | 84 | 19.12 | 5.8 | |
| | | +-----------------+-------------+-------------+ |
| | | | 90 | 19.6 | - | |
| | +----------------------+-----------------+-------------+-------------+ |
| | | CEXT = 33 pF | 2 | 0.3 | 0.2 | |
| | | C = CINT + CS + CEXT +-----------------+-------------+-------------+ |
| | | | 8 | 1.3 | 0.7 | |
| | | +-----------------+-------------+-------------+ |
| | | | 25 | 3.5 | 2.3 | |
| | | +-----------------+-------------+-------------+ |
| | | | 50 | 10.26 | 5.19 | |
| | | +-----------------+-------------+-------------+ |
| | | | 60 | 16.53 | - | |
+--------+---------------+----------------------+-----------------+-------------+-------------+------+
1. CINT + CS, PCB board capacitance including the pad pin is estimated to15 pF.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• I/O compensation cell enabled.
• The ART/L1-cache is ON.
• Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
• HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
– fHCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK = 168 MHz (Scale 2),
fHCLK = 144 MHz (Scale 3)
• Ambient operating temperature is 25 °C and VDD=3.3 V.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #129 ===
Table 39. Peripheral current consumption
+------------------------+--------------------------------------------------------+--------+
| Pihl | IDD(Typ)⁽¹⁾ | Unit |
+----------+-------------+------------------+------------------+------------------+ |
| P | eripheral | Scale 1 | Scale 2 | Scale 3 | |
+----------+-------------+------------------+------------------+------------------+========+
| AHB1 | GPIOA | 2.9 | 2.8 | 2.2 | µA/MHz |
| (up to +-------------+------------------+------------------+------------------+ |
| 216 MHz) | GPIOB | 3.0 | 2.9 | 2.2 | |
| +-------------+------------------+------------------+------------------+ |
| | GPIOC | 2.9 | 2.8 | 2.2 | |
| +-------------+------------------+------------------+------------------+ |
| | GPIOD | 3.1 | 3.0 | 2.3 | |
| +-------------+------------------+------------------+------------------+ |
| | GPIOE | 3.1 | 3.0 | 2.3 | |
| +-------------+------------------+------------------+------------------+ |
| | GPIOF | 2.9 | 2.8 | 2.2 | |
| +-------------+------------------+------------------+------------------+ |
| | GPIOG | 2.9 | 2.8 | 2.2 | |
| +-------------+------------------+------------------+------------------+ |
| | GPIOH | 3.1 | 3.1 | 2.4 | |
| +-------------+------------------+------------------+------------------+ |
| | GPIOI | 3.0 | 2.9 | 2.2 | |
| +-------------+------------------+------------------+------------------+ |
| | GPIOJ | 2.9 | 2.9 | 2.2 | |
| +-------------+------------------+------------------+------------------+ |
| | GPIOK | 2.8 | 2.8 | 2.4 | |
| +-------------+------------------+------------------+------------------+ |
| | CRC | 1.0 | 0.9 | 0.8 | |
| +-------------+------------------+------------------+------------------+ |
| | BKPSRAM | 0.9 | 0.9 | 0.7 | |
| +-------------+------------------+------------------+------------------+ |
| | DMA1 | 3.17 x N + 11.63 | 3.08 x N + 11.39 | 2.6 x N + 9.64 | |
| +-------------+------------------+------------------+------------------+ |
| | DMA2 | 3.33 x N + 12.84 | 3.27 x N + 11.84 | 2.75 x N + 10.10 | |
| +-------------+------------------+------------------+------------------+ |
| | DMA2D | 77.7 | 76.3 | 63.5 | |
| +-------------+------------------+------------------+------------------+ |
| | ETH_MAC | 40.1 | 39.5 | 32.8 | |
| | ETH_MAC_TX | | | | |
| | ETH_MAC_RX | | | | |
| | ETH_MAC_PTP | | | | |
| +-------------+------------------+------------------+------------------+ |
| | OTG_HS | 58.5 | 57.4 | 48.1 | |
| +-------------+------------------+------------------+------------------+ |
| | OTG_HS+ULPI | 58.5 | 57.4 | 48.1 | |
+----------+-------------+------------------+------------------+------------------+--------+
| AHB2 | DCMI | 2.9 | 2.8 | 2.1 | µA/MHz |
| (up to +-------------+------------------+------------------+------------------+ |
| 216 MHz) | JPEG | 74.8 | 73.4 | 61.9 | |
| +-------------+------------------+------------------+------------------+ |
| | RNG | 6.7 | 6.7 | 5.4 | |
| +-------------+------------------+------------------+------------------+ |
| | USB_OTG_FS | 32.4 | 31.9 | 26.7 | |
+----------+-------------+------------------+------------------+------------------+--------+
| AHB3 | FMC | 18.6 | 18.2 | 15.1 | µA/MHz |
| (up to +-------------+------------------+------------------+------------------+ |
| 216 MHz) | QSPI | 22.3 | 21.8 | 18.1 | |
+----------+-------------+------------------+------------------+------------------+--------+
| Bus matrix⁽²⁾ | 3.94 | 3.25 | 2.12 | µA/MHz |
+------------------------+------------------+------------------+------------------+--------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #130 ===
Table 39. Peripheral current consumption (continued)
+------------------------+-----------------------------+--------+
| Pihl | IDD(Typ)⁽¹⁾ | Unit |
+---------+--------------+---------+---------+---------+ |
| P | eripheral | Scale 1 | Scale 2 | Scale 3 | |
+---------+--------------+---------+---------+---------+========+
| APB1 | TIM2 | 19.1 | 18.7 | 14.7 | µA/MHz |
| (up to +--------------+---------+---------+---------+ |
| 54 MHz) | TIM3 | 14.6 | 14.0 | 10.6 | |
| +--------------+---------+---------+---------+ |
| | TIM4 | 15.4 | 14.7 | 11.4 | |
| +--------------+---------+---------+---------+ |
| | TIM5 | 18.1 | 17.6 | 13.6 | |
| +--------------+---------+---------+---------+ |
| | TIM6 | 3.1 | 2.7 | 1.4 | |
| +--------------+---------+---------+---------+ |
| | TIM7 | 3.0 | 2.7 | 1.1 | |
| +--------------+---------+---------+---------+ |
| | TIM12 | 8.1 | 7.8 | 5.6 | |
| +--------------+---------+---------+---------+ |
| | TIM13 | 5.4 | 5.1 | 3.1 | |
| +--------------+---------+---------+---------+ |
| | TIM14 | 5.6 | 5.3 | 3.3 | |
| +--------------+---------+---------+---------+ |
| | LPTIM1 | 9.8 | 9.6 | 6.9 | |
| +--------------+---------+---------+---------+ |
| | WWDG | 1.9 | 1.6 | 1,4 | |
| +--------------+---------+---------+---------+ |
| | SPI2/I2S2⁽³⁾ | 3.0 | 2.9 | 1.4 | |
| +--------------+---------+---------+---------+ |
| | SPI3/I2S3⁽³⁾ | 3.0 | 3.3 | 1.4 | |
| +--------------+---------+---------+---------+ |
| | SPDIFRX | 2.4 | 2.0 | 1.7 | |
| +--------------+---------+---------+---------+ |
| | USART2 | 12.6 | 12.7 | 9.2 | |
| +--------------+---------+---------+---------+ |
| | USART3 | 12.4 | 12.4 | 9.4 | |
| +--------------+---------+---------+---------+ |
| | UART4 | 10.7 | 10.9 | 8.1 | |
| +--------------+---------+---------+---------+ |
| | UART5 | 10.7 | 10.7 | 8.1 | |
| +--------------+---------+---------+---------+ |
| | I2C1 | 8.9 | 8.9 | 6.4 | |
| +--------------+---------+---------+---------+ |
| | I2C2 | 8.3 | 8.2 | 6.1 | |
| +--------------+---------+---------+---------+ |
| | I2C3 | 8.1 | 8.2 | 6.1 | |
| +--------------+---------+---------+---------+ |
| | I2C4 | 8.0 | 8.2 | 5.8 | |
| +--------------+---------+---------+---------+ |
| | CAN1 | 6.3 | 6.4 | 4.4 | |
| +--------------+---------+---------+---------+ |
| | CAN2 | 5.7 | 5.8 | 3.9 | |
| +--------------+---------+---------+---------+ |
| | CAN3 | 7.4 | 7.1 | 5.6 | |
| +--------------+---------+---------+---------+ |
| | HDMI-CEC | 2.2 | 1.8 | 1.4 | |
| +--------------+---------+---------+---------+ |
| | PWR | 1.3 | 0.9 | 0.8 | |
| +--------------+---------+---------+---------+ |
| | DAC⁽⁴⁾ | 4.8 | 4.2 | 3.6 | |
| +--------------+---------+---------+---------+ |
| | UART7 | 10.4 | 10.4 | 7.8 | |
| +--------------+---------+---------+---------+ |
| | UART8 | 11.1 | 11.3 | 8.3 | |
+---------+--------------+---------+---------+---------+--------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #131 ===
Table 39. Peripheral current consumption (continued)
+-------------------------+-----------------------------+--------+
| Pihl | IDD(Typ)⁽¹⁾ | Unit |
+----------+--------------+---------+---------+---------+ |
| P | eripheral | Scale 1 | Scale 2 | Scale 3 | |
+----------+--------------+---------+---------+---------+========+
| APB2 | TIM1 | 24.1 | 23.8 | 19.6 | µA/MHz |
| (up to +--------------+---------+---------+---------+ |
| 108 MHz) | TIM8 | 24.5 | 24.2 | 20.0 | |
| +--------------+---------+---------+---------+ |
| | USART1 | 17.7 | 17.4 | 14.3 | |
| +--------------+---------+---------+---------+ |
| | USART6 | 11.9 | 11.8 | 9.4 | |
| +--------------+---------+---------+---------+ |
| | ADC1⁽⁵⁾ | 4.5 | 4.7 | 3.5 | |
| +--------------+---------+---------+---------+ |
| | ADC2⁽⁵⁾ | 4.5 | 4.7 | 3.3 | |
| +--------------+---------+---------+---------+ |
| | ADC3⁽⁵⁾ | 4.5 | 4.6 | 3.3 | |
| +--------------+---------+---------+---------+ |
| | SDMMC1 | 8.4 | 8.3 | 6.9 | |
| +--------------+---------+---------+---------+ |
| | SDMMC2 | 8.2 | 8.2 | 6.4 | |
| +--------------+---------+---------+---------+ |
| | SPI1/I2S1⁽³⁾ | 3.9 | 3.6 | 3.1 | |
| +--------------+---------+---------+---------+ |
| | SPI4 | 3.9 | 3.6 | 3.1 | |
| +--------------+---------+---------+---------+ |
| | SYSCFG | 2.5 | 2.2 | 1.9 | |
| +--------------+---------+---------+---------+ |
| | TIM9 | 8.0 | 8.0 | 6.2 | |
| +--------------+---------+---------+---------+ |
| | TIM10 | 5.0 | 5.1 | 3.7 | |
| +--------------+---------+---------+---------+ |
| | TIM11 | 6.9 | 6.9 | 5.3 | |
| +--------------+---------+---------+---------+ |
| | SPI5 | 2.7 | 2.8 | 1.8 | |
| +--------------+---------+---------+---------+ |
| | SPI6 | 3.1 | 3.2 | 2.2 | |
| +--------------+---------+---------+---------+ |
| | SAI1 | 3.2 | 3.3 | 2.2 | |
| +--------------+---------+---------+---------+ |
| | DFSDM1 | 10.9 | 10.7 | 9.0 | |
| +--------------+---------+---------+---------+ |
| | SAI2 | 3.9 | 3.9 | 2.8 | |
| +--------------+---------+---------+---------+ |
| | MDIO | 7.1 | 7.0 | 5.8 | |
| +--------------+---------+---------+---------+ |
| | LTDC | 51.2 | 50.3 | 41.8 | |
| +--------------+---------+---------+---------+ |
| | DSI | 8.5 | 8.4 | 8.1 | |
+----------+--------------+---------+---------+---------+--------+
1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.
2. The BusMatrix is automatically active when at least one master is ON.
3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.75 mA per DAC channel for the analog part.
5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.73 mA per ADC for the analog part.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #132 ===
6.3.8 Wakeup time from low-power modes
The wakeup times given in Table 40 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 40. Low-power mode wakeup timings
+-------------+-------------------------+-------------------------------------+--------+--------+--------+
| Symbol | Parameter | Conditions | Typ⁽¹⁾ | Max⁽¹⁾ | Unit |
+=============+=========================+=====================================+========+========+========+
| tWUSLEEP⁽²⁾ | Wakeup from Sleep | - | 13 | 13 | CPU |
| | | | | | clock |
| | | | | | cycles |
+-------------+-------------------------+-------------------------------------+--------+--------+--------+
| tWUSTOP⁽²⁾ | Wakeup from Stop mode | Main regulator is ON | 14 | 14.9 | µs |
| | with MR/LP regulator in +-------------------------------------+--------+--------+ |
| | normal mode | Main regulator is ON and Flash | 104.1 | 107.6 | |
| | | memory in Deep power down mode | | | |
| | +-------------------------------------+--------+--------+ |
| | | Low power regulator is ON | 21.4 | 24.2 | |
| | +-------------------------------------+--------+--------+ |
| | | Low power regulator is ON and Flash | 111.5 | 116.5 | |
| | | memory in Deep power down mode | | | |
+-------------+-------------------------+-------------------------------------+--------+--------+ |
| tWUSTOP⁽²⁾ | Wakeup from Stop mode | Main regulator in under-drive mode | 107.4 | 113.2 | |
| | with MR/LP regulator in | (Flash memory in Deep power-down | | | |
| | Under-drive mode | mode) | | | |
| | +-------------------------------------+--------+--------+ |
| | | Low power regulator in under-drive | 112.7 | 120 | |
| | | mode | | | |
| | | (Flash memory in Deep power-down | | | |
| | | mode ) | | | |
+-------------+-------------------------+-------------------------------------+--------+--------+ |
| tWUSTDBY | Wakeup from Standby | Exit Standby mode on rising edge | 308 | 313 | |
| (2) | mode +-------------------------------------+--------+--------+ |
| | | Exit Standby mode on falling edge | 307 | 313 | |
+-------------+-------------------------+-------------------------------------+--------+--------+--------+
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #133 ===
6.3.9 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 65: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 28.
The characteristics given in Table 41 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
Table 41. High-speed external user clock characteristics
+-----------+-------------------------------------+-----------------+--------+-----+--------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+=====================================+=================+========+=====+========+======+
| fHSE_ext | External user clock source | - | 1 | - | 50 | MHz |
| | frequency⁽¹⁾ | | | | | |
+-----------+-------------------------------------+ +--------+-----+--------+------+
| VHSEH | OSC_IN input pin high level voltage | | 0.7VDD | - | ⱽDD | V |
+-----------+-------------------------------------+ +--------+-----+--------+ |
| VHSEL | OSC_IN input pin low level voltage | | ⱽSS | - | 0.3VDD | |
+-----------+-------------------------------------+ +--------+-----+--------+------+
| tw(HSE) | OSC_IN high or low time⁽¹⁾ | | 5 | - | - | ns |
| tw(HSE) | | | | | | |
+-----------+-------------------------------------+ +--------+-----+--------+ |
| tr(HSE) | OSC_IN rise or fall time⁽¹⁾ | | - | - | 10 | |
| tf(HSE) | | | | | | |
+-----------+-------------------------------------+-----------------+--------+-----+--------+------+
| Cin(HSE) | OSC_IN input capacitance⁽¹⁾ | - | - | 5 | - | pF |
+-----------+-------------------------------------+-----------------+--------+-----+--------+------+
| DuCy(HSE) | Duty cycle | - | 45 | - | 55 | % |
+-----------+-------------------------------------+-----------------+--------+-----+--------+------+
| IL | OSC_IN Input leakage current | VSS ≤ VIN ≤ VDD | - | - | ±1 | µA |
+-----------+-------------------------------------+-----------------+--------+-----+--------+------+
1. Guaranteed by design.
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 65: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 29.
The characteristics given in Table 42 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #134 ===
Table 42. Low-speed external user clock characteristics
+-----------+--------------------------------------+-----------------+--------+--------+--------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+======================================+=================+========+========+========+======+
| fLSE_ext | User External clock source | - | - | 32.768 | 1000 | kHz |
| | frequency⁽¹⁾ | | | | | |
+-----------+--------------------------------------+ +--------+--------+--------+------+
| VLSEH | OSC32_IN input pin high level | | 0.7VDD | - | ⱽDD | V |
| | voltage | | | | | |
+-----------+--------------------------------------+ +--------+--------+--------+ |
| VLSEL | OSC32_IN input pin low level voltage | | ⱽSS | - | 0.3VDD | |
+-----------+--------------------------------------+ +--------+--------+--------+------+
| tw(LSE) | OSC32_IN high or low time⁽¹⁾ | | 450 | - | - | ns |
| tf(LSE) | | | | | | |
+-----------+--------------------------------------+ +--------+--------+--------+ |
| tr(LSE) | OSC32_IN rise or fall time⁽¹⁾ | | - | - | 50 | |
| tf(LSE) | | | | | | |
+-----------+--------------------------------------+-----------------+--------+--------+--------+------+
| Cin(LSE) | OSC32_IN input capacitance⁽¹⁾ | - | - | 5 | - | pF |
+-----------+--------------------------------------+-----------------+--------+--------+--------+------+
| DuCy(LSE) | Duty cycle | - | 30 | - | 70 | % |
+-----------+--------------------------------------+-----------------+--------+--------+--------+------+
| IL | OSC32_IN Input leakage current | VSS ≤ VIN ≤ VDD | - | - | ±1 | µA |
+-----------+--------------------------------------+-----------------+--------+--------+--------+------+
1. Guaranteed by design.
Figure 28. High-speed external clock source AC timing diagram
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #135 ===
Figure 29. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 43. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 43. HSE 4-26 MHz oscillator characteristics⁽¹⁾
+-------------+-----------------------------+-------------------+-------+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=============+=============================+===================+=======+=====+=====+======+
| fOSC_IN | Oscillator frequency | - | 4 | - | 26 | MHz |
+-------------+-----------------------------+-------------------+-------+-----+-----+------+
| RF | Feedback resistor | - | - | 200 | - | kΩ |
+-------------+-----------------------------+-------------------+-------+-----+-----+------+
| IDD | HSE current consumption | VDD=3.3 V, | - | 450 | - | µA |
| | | ESR= 30 Ω, | | | | |
| | | CL=5 pF@25 MHz | | | | |
| | +-------------------+-------+-----+-----+ |
| | | VDD=3.3 V, | - | 530 | - | |
| | | ESR= 30 Ω, | | | | |
| | | CL=10 pF@25 MHz | | | | |
+-------------+-----------------------------+-------------------+-------+-----+-----+------+
| ACCHSE⁽²⁾ | HSE accuracy | - | − 500 | - | 500 | ppm |
+-------------+-----------------------------+-------------------+-------+-----+-----+------+
| Gm_crit_max | Maximum critical crystal gm | Startup | - | - | 1 | mA/V |
+-------------+-----------------------------+-------------------+-------+-----+-----+------+
| tSU(HSE⁽³⁾ | Startup time | VDD is stabilized | - | 2 | - | ms |
+-------------+-----------------------------+-------------------+-------+-----+-----+------+
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is guaranteed by characterization results. It is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #136 ===
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 30). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 30. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 44. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 44. LSE oscillator characteristics (fLSE = 32.768 kHz) ⁽¹⁾
+--------+-------------------------+------------------------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+========+=========================+==============================+=====+=====+=====+======+
| IDD | LSE current consumption | LSEDRV[1:0]=00 | - | 250 | - | nA |
| | | Low drive capability | | | | |
| | +------------------------------+-----+-----+-----+ |
| | | LSEDRV[1:0]=10 | - | 300 | - | |
| | | Medium low drive capability | | | | |
| | +------------------------------+-----+-----+-----+ |
| | | LSEDRV[1:0]=01 | - | 370 | - | |
| | | Medium high drive capability | | | | |
| | +------------------------------+-----+-----+-----+ |
| | | LSEDRV[1:0]=11 | - | 480 | - | |
| | | High drive capability | | | | |
+--------+-------------------------+------------------------------+-----+-----+-----+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #137 ===
Table 44. LSE oscillator characteristics (fLSE = 32.768 kHz) ⁽¹⁾ (continued)
+-------------+-----------------------------+------------------------------+-----+-----+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=============+=============================+==============================+=====+=====+======+======+
| Gm_crit_max | Maximum critical crystal gm | LSEDRV[1:0]=00 | - | - | 0.48 | µA/V |
| | | Low drive capability | | | | |
| | +------------------------------+-----+-----+------+ |
| | | LSEDRV[1:0]=10 | - | - | 0.75 | |
| | | Medium low drive capability | | | | |
| | +------------------------------+-----+-----+------+ |
| | | LSEDRV[1:0]=01 | - | - | 1.7 | |
| | | Medium high drive capability | | | | |
| | +------------------------------+-----+-----+------+ |
| | | LSEDRV[1:0]=11 | - | - | 2.7 | |
| | | High drive capability | | | | |
+-------------+-----------------------------+------------------------------+-----+-----+------+------+
| tSU⁽²⁾ | start-up time | VDD is stabilized | - | 2 | - | s |
+-------------+-----------------------------+------------------------------+-----+-----+------+------+
1. Guaranteed by design.
2. Guaranteed by characterization results. tSU is the start-up time measured from the moment it is enabled
(by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 31. Typical application with a 32.768 kHz crystal
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #138 ===
6.3.10 Internal clock source characteristics
The parameters given in Table 45 and Table 46 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 17.
High-speed internal (HSI) RC oscillator
Table 45. HSI oscillator characteristics ⁽¹⁾
+-------------+----------------------------------+-----------------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=============+==================================+=======================+=====+=====+=====+======+
| fHSI | Frequency | - | - | 16 | - | MHz |
+-------------+----------------------------------+-----------------------+-----+-----+-----+------+
| ACCHSI | HSI user trimming step⁽²⁾ | - | - | - | 1 | % |
| +----------------------------------+-----------------------+-----+-----+-----+------+
| | Accuracy of the HSI oscillator | TA = –40 to 105 °C⁽³⁾ | − 8 | - | 4.5 | % |
| | +-----------------------+-----+-----+-----+------+
| | | TA = –10 to 85 °C⁽³⁾ | − 4 | - | 4 | % |
| | +-----------------------+-----+-----+-----+------+
| | | TA = 25 °C⁽⁴⁾ | − 1 | - | 1 | % |
+-------------+----------------------------------+-----------------------+-----+-----+-----+------+
| tsu(HSI)⁽²⁾ | HSI oscillator startup time | - | - | 2.2 | 4 | µs |
+-------------+----------------------------------+-----------------------+-----+-----+-----+------+
| IDD(HSI)⁽²⁾ | HSI oscillator power consumption | - | - | 60 | 80 | µA |
+-------------+----------------------------------+-----------------------+-----+-----+-----+------+
1. VDD = 3.3 V, PLL OFF, TA = –40 to 125 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Factory calibrated, parts not soldered.
Figure 32. ACCHSI versus temperature
1. Guaranteed by characterization results.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #139 ===
Low-speed internal (LSI) RC oscillator
Table 46. LSI oscillator characteristics ⁽¹⁾
+-------------+----------------------------------+-----+-----+-----+------+
| Symbol | Parameter | Min | Typ | Max | Unit |
+=============+==================================+=====+=====+=====+======+
| fLSI⁽²⁾ | Frequency | 17 | 32 | 47 | kHz |
+-------------+----------------------------------+-----+-----+-----+------+
| tsu(LSI)⁽³⁾ | LSI oscillator startup time | - | 15 | 40 | µs |
+-------------+----------------------------------+-----+-----+-----+------+
| IDD(LSI)⁽³⁾ | LSI oscillator power consumption | - | 0.4 | 0.6 | µA |
+-------------+----------------------------------+-----+-----+-----+------+
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by characterization results.
3. Guaranteed by design.
Figure 33. LSI deviation versus temperature
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #140 ===
6.3.11 PLL characteristics
The parameters given in Table 47 and Table 48 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.
Table 47. Main PLL characteristics
+--------------+---------------------------------+--------------------------+---------+------+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+==============+=================================+==========================+=========+======+======+======+
| fPLL_IN | PLL input clock⁽¹⁾ | - | 0.95⁽²⁾ | 1 | 2.10 | MHz |
+--------------+---------------------------------+--------------------------+---------+------+------+ |
| fPLL_OUT | PLL multiplier output clock | - | 24 | - | 216 | |
+--------------+---------------------------------+--------------------------+---------+------+------+ |
| fPLL48_OUT | 48 MHz PLL multiplier output | - | - | 48 | 75 | |
| | clock | | | | | |
+--------------+---------------------------------+--------------------------+---------+------+------+ |
| fVCO_OUT | PLL VCO output | - | 100 | - | 432 | |
+--------------+---------------------------------+--------------------------+---------+------+------+------+
| tLOCK | PLL lock time | VCO freq = 192 MHz | 75 | - | 200 | µs |
| | |--------------------------+---------+------+------+ |
| | | VCO freq = 432 MHz | 100 | - | 300 | |
+--------------+---------------------------------+-----------------+--------+---------+------+------+------+
| Jitter⁽³⁾ | Cycle-to-cycle jitter | System clock | RMS | - | 25 | - | ps |
| | | 216 MHz +--------+---------+------+------+ |
| | | | peak | - | ±150 | - | |
| | | | to | | | | |
| | | | peak | | | | |
| +---------------------------------+ +--------+---------+------+------+ |
| | Period Jitter | | RMS | - | 15 | - | |
| | | +--------+---------+------+------+ |
| | | | peak | - | ±200 | - | |
| | | | to | | | | |
| | | | peak | | | | |
| +---------------------------------+-----------------+--------+---------+------+------+ |
| | Main clock output (MCO) for | Cycle to cycle at 50 MHz | - | 32 | - | |
| | RMII Ethernet | on 1000 samples | | | | |
| +---------------------------------+--------------------------+---------+------+------+ |
| | Main clock output (MCO) for MII | Cycle to cycle at 25 MHz | - | 40 | - | |
| | Ethernet | on 1000 samples | | | | |
| +---------------------------------+--------------------------+---------+------+------+ |
| | Bit Time CAN jitter | Cycle to cycle at 1 MHz | - | 330 | - | |
| | | on 1000 samples | | | | |
+--------------+---------------------------------+--------------------------+---------+------+------+------+
| IDD(PLL)⁽⁴⁾ | PLL power consumption on VDD | VCO freq = 192 MHz | 0.15 | - | 0.40 | mA |
| | | VCO freq = 432 MHz | 0.45 | | 0.75 | |
+--------------+---------------------------------+--------------------------+---------+------+------+------+
| IDDA(PLL)⁽⁴⁾ | PLL power consumption on VDDA | VCO freq = 192 MHz | 0.30 | - | 0.40 | mA |
| | | VCO freq = 432 MHz | 0.55 | | 0.85 | |
+--------------+---------------------------------+--------------------------+---------+------+------+------+
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization results.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #141 ===
Table 48. PLLI2S characteristics
+-----------------+------------------------------------+--------------------------+---------+------+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=================+====================================+==========================+=========+======+======+======+
| fPLLI2S_IN | PLLI2S input clock⁽¹⁾ | - | 0.95⁽²⁾ | 1 | 2.10 | MHz |
+-----------------+------------------------------------+--------------------------+---------+------+------+ |
| fPLLI2SP_OUT | PLLI2S multiplier output clock for | - | - | - | 216 | |
| | SPDIFRX | | | | | |
+-----------------+------------------------------------+--------------------------+---------+------+------+ |
| fPLLI2SQ_OUT | PLLI2S multiplier output clock for | - | - | - | 216 | |
| | SAI | | | | | |
+-----------------+------------------------------------+--------------------------+---------+------+------+ |
| fPLLI2SR_OUT | PLLI2S multiplier output clock for | - | - | - | 216 | |
| | I2S | | | | | |
+-----------------+------------------------------------+--------------------------+---------+------+------+ |
| fVCO_OUT | PLLI2S VCO output | - | 100 | - | 432 | |
+-----------------+------------------------------------+--------------------------+---------+------+------+------+
| tLOCK | PLLI2S lock time | VCO freq = 192 MHz | 75 | - | 200 | µs |
| | +--------------------------+---------+------+------+ |
| | | VCO freq = 432 MHz | 100 | - | 300 | |
+-----------------+------------------------------------+-------------------+------+---------+------+------+------+
| Jitter⁽³⁾ | Master I2S clock jitter | Cycle to cycle at | RMS | - | 90 | - | - |
| | | 12.288 MHz on +------+---------+------+------+------+
| | | 48KHz period, | peak | - | ±280 | - | ps |
| | | N=432, R=5 | to | | | | |
| | | | peak | | | | |
| | +-------------------+------+---------+------+------+------+
| | | Average frequency of | - | 90 | - | ps |
| | | 12.288 MHz | | | | |
| | | N = 432, R = 5 | | | | |
| | | on 1000 samples | | | | |
| +------------------------------------+--------------------------+---------+------+------+------+
| | WS I2S clock jitter | Cycle to cycle at 48 KHz | - | 400 | - | ps |
| | | on 1000 samples | | | | |
+-----------------+------------------------------------+--------------------------+---------+------+------+------+
| IDD(PLLI2S)⁽⁴⁾ | PLLI2S power consumption on | VCO freq = 192 MHz | 0.15 | - | 0.40 | mA |
| | VDD | VCO freq = 432 MHz | 0.45 | | 0.75 | |
+-----------------+------------------------------------+--------------------------+---------+------+------+------+
| IDDA(PLLI2S)⁽⁴⁾ | PLLI2S power consumption on | VCO freq = 192 MHz | 0.30 | - | 0.40 | mA |
| | VDDA | VCO freq = 432 MHz | 0.55 | | 0.85 | |
+-----------------+------------------------------------+--------------------------+---------+------+------+------+
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Table 49. PLLISAI characteristics
+--------------+--------------------------------+------------+---------+-----+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+==============+================================+============+=========+=====+======+======+
| fPLLSAI_IN | PLLSAI input clock⁽¹⁾ | - | 0.95⁽²⁾ | 1 | 2.10 | MHz |
+--------------+--------------------------------+------------+---------+-----+------+ |
| fPLLSAIP_OUT | PLLSAI multiplier output clock | - | - | 48 | 75 | |
| | for 48 MHz | | | | | |
+--------------+--------------------------------+------------+---------+-----+------+ |
| fPLLSAIQ_OUT | PLLSAI multiplier output clock | - | - | - | 216 | |
| | for SAI | | | | | |
+--------------+--------------------------------+------------+---------+-----+------+ |
| fPLLSAIR_OUT | PLLSAI multiplier output clock | - | - | - | 216 | |
| | for LCD-TFT | | | | | |
+--------------+--------------------------------+------------+---------+-----+------+ |
| fVCO_OUT | PLLSAI VCO output | - | 100 | - | 432 | |
+--------------+--------------------------------+------------+---------+-----+------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #142 ===
Table 49. PLLISAI characteristics (continued)
+-----------------+-----------------------------+--------------------------+------+------+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=================+=============================+==========================+======+======+======+======+
| tLOCK | PLLSAI lock time | VCO freq = 192 MHz | 75 | - | 200 | µs |
| | +--------------------------+------+------+------+ |
| | | VCO freq = 432 MHz | 100 | - | 300 | |
+-----------------+-----------------------------+-------------------+------+------+------+------+------+
| Jitter⁽³⁾ | Master SAI clock jitter | Cycle to cycle at | RMS | - | 90 | - | - |
| | | 12.288 MHz on +------+------+------+------+------+
| | | 48KHz period, | peak | - | ±280 | - | ps |
| | | N=432, R=5 | to | | | | |
| | | | peak | | | | |
| | +-------------------+------+------+------+------+------+
| | | Average frequency of | - | 90 | - | ps |
| | | 12.288 MHz | | | | |
| | | N = 432, R = 5 | | | | |
| | | on 1000 samples | | | | |
| +-----------------------------+--------------------------+------+------+------+------+
| | FS clock jitter | Cycle to cycle at 48 KHz | - | 400 | - | ps |
| | | on 1000 samples | | | | |
+-----------------+-----------------------------+--------------------------+------+------+------+------+
| IDD(PLLSAI)⁽⁴⁾ | PLLSAI power consumption on | VCO freq = 192 MHz | 0.15 | - | 0.40 | mA |
| | VDD | VCO freq = 432 MHz | 0.45 | | 0.75 | |
+-----------------+-----------------------------+--------------------------+------+------+------+------+
| IDDA(PLLSAI)⁽⁴⁾ | PLLSAI power consumption on | VCO freq = 192 MHz | 0.30 | - | 0.40 | mA |
| | VDDA | VCO freq = 432 MHz | 0.55 | | 0.85 | |
+-----------------+-----------------------------+--------------------------+------+------+------+------+
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 61: EMI characteristics). It is available only on the main PLL.
Table 50. SSCG parameters constraint
+-------------------+-----------------------+------+-----+---------+------+
| Symbol | Parameter | Min | Typ | Max⁽¹⁾ | Unit |
+===================+=======================+======+=====+=========+======+
| fMod | Modulation frequency | - | - | 10 | KHz |
+-------------------+-----------------------+------+-----+---------+------+
| md | Peak modulation depth | 0.25 | - | 2 | % |
+-------------------+-----------------------+------+-----+---------+------+
| MODEPER * INCSTEP | - | - | - | 2¹⁵ − 1 | - |
+-------------------+-----------------------+------+-----+---------+------+
1. Guaranteed by design.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER= round[ fPLL_IN ⁄ (4× fMod ) ]
fPLL_IN and fMod must be expressed in Hz.
As an example:
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #143 ===
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
MODEPER= round[ 10⁶ ⁄ (4× 10³ ) ] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP= round[(( 2¹⁵ – 1 ) × md× PLLN ) ⁄ (100× 5 × MODEPER ) ]
fVCO_OUT must be expressed in MHz.
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP= round[(( 2¹⁵ – 1 ) × 2× 240 ) ⁄ (100× 5 × 250 ) ] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
mdquantized%= ( MODEPER× INCSTEP × 100 × 5 ) ⁄ ((2¹⁵ – 1 ) × PLLN )
As a result:
mdquantized%=( 250× 126 × 100 × 5 ) ⁄ ((2¹⁵ – 1 ) × 240 ) = 2.002%(peak)
Figure 34 and Figure 35 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.
Figure 34. PLL output clock waveforms in center spread mode
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #144 ===
Figure 35. PLL output clock waveforms in down spread mode
6.3.13 MIPI D-PHY characteristics
The parameters given in Table 51 and Table 52 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.
Table 51. MIPI D-PHY characteristics⁽¹⁾
+-------------+-------------------------------------+------------+-----+-----+---------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=============+=====================================+============+=====+=====+=========+======+
| Hi-Speed Input/Output Characteristics |
+-------------+-------------------------------------+------------+-----+-----+---------+------+
| UINST | UI instantaneous | - | 2 | - | 12.5 | ns |
+-------------+-------------------------------------+------------+-----+-----+---------+------+
| VCMTX | HS transmit common mode | - | 150 | 200 | 250 | mV |
| | voltage | | | | | |
+-------------+-------------------------------------+------------+-----+-----+---------+ |
| |∆VCMTX| | VCMTX mismatch when output | - | - | - | 5 | |
| | is Differential-1 or Differential-0 | | | | | |
+-------------+-------------------------------------+------------+-----+-----+---------+ |
| |VOD| | HS transmit differential voltage | - | 140 | 200 | 270 | |
+-------------+-------------------------------------+------------+-----+-----+---------+ |
| |∆VOD| | VOD mismatch when output is | - | - | - | 14 | |
| | Differential-1 or Differential-0 | | | | | |
+-------------+-------------------------------------+------------+-----+-----+---------+ |
| VOHHS | HS output high voltage | - | - | - | 360 | |
+-------------+-------------------------------------+------------+-----+-----+---------+------+
| ZOS | Single ended output | - | 40 | 50 | 62.5 | Ω |
| | impedance | | | | | |
+-------------+-------------------------------------+------------+-----+-----+---------+------+
| ∆ZOS | Single ended output | - | - | - | 10 | % |
| | impedance mismatch | | | | | |
+-------------+-------------------------------------+------------+-----+-----+---------+------+
| tHSr & tHSf | 20%-80% rise and fall time | - | 100 | - | 0.35*UI | ps |
+-------------+-------------------------------------+------------+-----+-----+---------+------+
| LP Receiver Input Characteristics |
+-------------+-------------------------------------+------------+-----+-----+---------+------+
| VIL | Logic 0 input voltage (not in | - | - | - | 550 | mV |
| | ULP State) | | | | | |
+-------------+-------------------------------------+------------+-----+-----+---------+ |
| VIL-ULPS | Logic 0 input voltage in ULP | - | - | - | 300 | |
| | State | | | | | |
+-------------+-------------------------------------+------------+-----+-----+---------+ |
| VIH | Input high level voltage | - | 880 | - | - | |
+-------------+-------------------------------------+------------+-----+-----+---------+ |
| Vhys | Voltage hysteresis | - | 25 | - | - | |
+-------------+-------------------------------------+------------+-----+-----+---------+------+
| LP Emitter Output Characteristics |
+---------------------------------------------------------------------------------------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #145 ===
Table 51. MIPI D-PHY characteristics⁽¹⁾ (continued)
+----------+------------------------------+------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+==========+==============================+============+=====+=====+=====+======+
| VIL | Output low level voltage | - | 1.1 | 1.2 | 1.2 | V |
+----------+------------------------------+------------+-----+-----+-----+------+
| VIL-ULPS | Output high level voltage | - | -50 | - | 50 | mV |
+----------+------------------------------+------------+-----+-----+-----+------+
| VIH | Output impedance of LP | - | 110 | - | - | Ω |
| | transmitter | | | | | |
+----------+------------------------------+------------+-----+-----+-----+------+
| Vhys | 15%-85% rise and fall time | - | - | - | 25 | ns |
+----------+------------------------------+------------+-----+-----+-----+------+
| LP Contention Detector Characteristics |
+----------+------------------------------+------------+-----+-----+-----+------+
| VILCD | Logic 0 contention threshold | - | - | - | 200 | mV |
+----------+------------------------------+------------+-----+-----+-----+ |
| VIHCD | Logic 0 contention threshold | - | 450 | - | - | |
+----------+------------------------------+------------+-----+-----+-----+------+
1. Guaranteed based on test during characterization.
Table 52. MIPI D-PHY AC characteristics LP mode and HS/LP
transitions⁽¹⁾
+--------------+------------------------------------+------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+==============+====================================+============+=====+=====+=====+======+
| TLPX | Transmitted length of any Low- | - | 50 | - | - | ns |
| | Power state period | | | | | |
+--------------+------------------------------------+------------+-----+-----+-----+ |
| TCLK-PREPARE | Time that the transmitter drives | - | 38 | - | 95 | |
| | the Clock Lane LP-00 Line | | | | | |
| | state immediately before the | | | | | |
| | HS-0 Line state starting the HS | | | | | |
| | transmission. | | | | | |
+--------------+------------------------------------+------------+-----+-----+-----+ |
| TCLK-PREPARE | Time that the transmitter drives | - | 300 | - | - | |
| + | the HS-0 state prior to starting | | | | | |
| TCLK-ZERO | the clock. | | | | | |
+--------------+------------------------------------+------------+-----+-----+-----+------+
| TCLK-PRE | Time that the HS clock shall be | - | 8 | - | - | UI |
| | driven by the transmitter prior to | | | | | |
| | any associated Data Lane | | | | | |
| | beginning the transition from | | | | | |
| | LP to HS mode. | | | | | |
+--------------+------------------------------------+------------+-----+-----+-----+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #146 ===
Table 52. MIPI D-PHY AC characteristics LP mode and HS/LP
transitions⁽¹⁾ (continued)
+-------------+----------------------------------+------------+------------+-----+---------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=============+==================================+============+============+=====+=========+======+
| TCLK-POST | Time that the transmitter | - | 62+52*UI | - | - | ns |
| | continues to send HS clock | | | | | |
| | after the last associated Data | | | | | |
| | Lane has transitioned to LP | | | | | |
| | Mode. | | | | | |
+-------------+----------------------------------+------------+------------+-----+---------+ |
| TCLK-TRAIL | Time that the transmitter drives | - | 60 | - | - | |
| | the HS-0 state after the last | | | | | |
| | payload clock bit of an HS | | | | | |
| | transmission burst. | | | | | |
+-------------+----------------------------------+------------+------------+-----+---------+ |
| THS-PREPARE | Time that the transmitter drives | - | 40+4*UI | - | 85+6*UI | |
| | the Data Lane LP-00 Line state | | | | | |
| | immediately before the HS-0 | | | | | |
| | Line state starting the HS | | | | | |
| | transmission. | | | | | |
+-------------+----------------------------------+------------+------------+-----+---------+ |
| THS-PREPARE | THS-PREPARE+ Time that the | - | 145+10*UI | - | - | |
| + | transmitter drives the HS-0 | | | | | |
| THS-ZERO | state prior to transmitting the | | | | | |
| | Sync sequence. | | | | | |
+-------------+----------------------------------+------------+------------+-----+---------+ |
| THS-TRAIL | Time that the transmitter drives | - | Max | - | - | |
| | the flipped differential state | | (n*8*UI, | | | |
| | after last payload data bit of a | | 60+n*4*UI) | | | |
| | HS transmission burst. | | | | | |
+-------------+----------------------------------+------------+------------+-----+---------+ |
| THS-EXIT | Time that the transmitter drives | - | 100 | - | - | |
| | LP-11 following a HS burst. | | | | | |
+-------------+----------------------------------+------------+------------+-----+---------+ |
| TREOT | 30%-85% rise time and fall time | - | - | - | 35 | |
+-------------+----------------------------------+------------+------------+-----+---------+ |
| TEOT | Transmitted time interval from | - | - | - | 105+ | |
| | the start of THS-TRAIL or | | | | n*12UI | |
| | TCLK-TRAIL, to the start of the | | | | | |
| | LP-11 state following a HS | | | | | |
| | burst. | | | | | |
+-------------+----------------------------------+------------+------------+-----+---------+------+
1. Guaranteed based on test during characterization.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #147 ===
Figure 36. MIPI D-PHY HS/LP clock lane transition timing diagram
Figure 37. MIPI D-PHY HS/LP data lane transition timing diagram
6.3.14 MIPI D-PHY PLL characteristics
The parameters given in Table 53 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.
Table 53. DSI-PLL characteristics⁽¹⁾
+------------+-----------------------------+------------+-------+-----+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+============+=============================+============+=======+=====+======+======+
| fPLL_IN | PLL input clock | - | 4 | - | 100 | MHz |
+------------+-----------------------------+------------+-------+-----+------+ |
| fPLL_INFIN | PFD input clock | - | 4 | - | 25 | |
+------------+-----------------------------+------------+-------+-----+------+ |
| fPLL_OUT | PLL multiplier output clock | - | 31.25 | - | 500 | |
+------------+-----------------------------+------------+-------+-----+------+ |
| fVCO_OUT | PLL VCO output | - | 500 | - | 1000 | |
+------------+-----------------------------+------------+-------+-----+------+------+
| tLOCK | PLL lock time | - | - | - | 200 | µs |
+------------+-----------------------------+------------+-------+-----+------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #148 ===
Table 53. DSI-PLL characteristics⁽¹⁾ (continued)
+----------+--------------------------------+---------------------+-----+------+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+==========+================================+=====================+=====+======+======+======+
| IDD(PLL) | PLL power consumption on VDD12 | fVCO_OUT = 500 MHz | - | 0.55 | 0.70 | mA |
| | +---------------------+-----+------+------+ |
| | | fVCO_OUT = 600 MHz | - | 0.65 | 0.80 | |
| | +---------------------+-----+------+------+ |
| | | fVCO_OUT = 1000 MHz | - | 0.95 | 1.20 | |
+----------+--------------------------------+---------------------+-----+------+------+------+
1. Based on test during characterization.
6.3.15 MIPI D-PHY regulator characteristics
The parameters given in Table 54 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.
Table 54. DSI regulator characteristics⁽¹⁾
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+======================================+==================================+======+======+======+======+
| VDD12DSI | 1.2 V internal voltage on VDD12DSI | - | 1.15 | 1.20 | 1.30 | V |
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
| CEXT | External capacitor on VCAPDSI | - | 1.1 | 2.2 | 3.3 | μF |
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
| ESR | External Serial Resistor | - | 0 | 25 | 600 | mΩ |
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
| IDDDSIREG | Regulator power consumption | - | 100 | 120 | 125 | µA |
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
| IDDDSI | DSI system (regulator, PLL and | Ultra Low Power Mode | - | 290 | 600 | µA |
| | D-PHY) current consumption on VDDDSI | (Reg. ON + PLL OFF) | | | | |
| | +----------------------------------+------+------+------+ |
| | | Stop State | - | 290 | 600 | |
| | | (Reg. ON + PLL OFF) | | | | |
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
| IDDDSILP | DSI system current consumption on | 10 MHz escape clock | - | 4.3 | 5.0 | mA |
| | VDDDSI in LP mode communication⁽²⁾ | (Reg. ON + PLL OFF) | | | | |
| | +----------------------------------+------+------+------+ |
| | | 20 MHz escape clock | - | 4.3 | 5.0 | |
| | | (Reg. ON + PLL OFF) | | | | |
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
| IDDDSIHS | DSI system (regulator, PLL and | 300 Mbps - 1 data lane | - | 8.0 | 8.8 | mA |
| | D-PHY) current consumption on VDDDSI | (Reg. ON + PLL ON) | | | | |
| | in HS mode communication⁽³⁾ +----------------------------------+------+------+------+ |
| | | 300 Mbps - 2data lane | - | 11.4 | 12.5 | |
| | | (Reg. ON + PLL ON) | | | | |
| | +----------------------------------+------+------+------+ |
| | | 500 Mbps - 1 data lane | - | 13.5 | 14.7 | |
| | | (Reg. ON + PLL ON) | | | | |
| | +----------------------------------+------+------+------+ |
| | | 500 Mbps - 2data lane | - | 18.0 | 19.6 | |
| | | (Reg. ON + PLL ON) | | | | |
| +--------------------------------------+----------------------------------+------+------+------+ |
| | DSI system (regulator, PLL and | 500 Mbps - 2data lane | - | 21.4 | 23.3 | |
| | D-PHY) current consumption on VDDDSI | (Reg. ON + PLL ON) | | | | |
| | in HS mode with CLK like payload | | | | | |
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
| tWAKEUP | Startup delay | CEXT = 2.2 µF | - | 110 | - | µs |
| | +----------------------------------+------+------+------+ |
| | | CEXT = 3.3 µF | - | - | 160 | |
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
| IINRUSH | Inrush current on VDDDSI | External capacitor load at start | - | 60 | 200 | mA |
+-----------+--------------------------------------+----------------------------------+------+------+------+------+
1. Based on test during characterization.
2. Values based on an average traffic in LP Command Mode.
3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #149 ===
6.3.16 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 55. Flash memory characteristics
+--------+----------------+----------------------------------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+========+================+========================================+=====+=====+=====+======+
| IDD | Supply current | Write / Erase 8-bit mode, VDD = 1.7 V | - | 14 | - | mA |
| | +----------------------------------------+-----+-----+-----+ |
| | | Write / Erase 16-bit mode, VDD = 2.1 V | - | 17 | - | |
| | +----------------------------------------+-----+-----+-----+ |
| | | Write / Erase 32-bit mode, VDD = 3.3 V | - | 24 | - | |
+--------+----------------+----------------------------------------+-----+-----+-----+------+
Table 56. Flash memory programming (single bank configuration
nDBANK=1)
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| Symbol | Parameter | Conditions | Min⁽¹⁾ | Typ | Max⁽¹⁾ | Unit |
+=============+============================+============================+========+======+========+======+
| tprog | Word programming time | Program/erase parallelism | - | 16 | 100⁽²⁾ | µs |
| | | (PSIZE) = x 8/16/32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| tERASE32KB | Sector (32 KB) erase time | Program/erase | - | 400 | 800 | ms |
| | | parallelism (PSIZE) = x 8 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 250 | 600 | |
| | | parallelism (PSIZE) = x 16 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 200 | 500 | |
| | | parallelism (PSIZE) = x 32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| tERASE128KB | Sector (128 KB) erase time | Program/erase | - | 1100 | 2400 | ms |
| | | parallelism (PSIZE) = x 8 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 800 | 1400 | |
| | | parallelism (PSIZE) = x 16 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 500 | 1100 | |
| | | parallelism (PSIZE) = x 32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| tERASE256KB | Sector (256 KB) erase time | Program/erase | - | 2.1 | 4 | s |
| | | parallelism (PSIZE) = x 8 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 1.5 | 2.6 | |
| | | parallelism (PSIZE) = x 16 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 1 | 2 | |
| | | parallelism (PSIZE) = x 32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| tME | Mass erase time | Program/erase | - | 16 | 32 | s |
| | | parallelism (PSIZE) = x 8 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 11 | 22 | |
| | | parallelism (PSIZE) = x 16 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 8 | 16 | |
| | | parallelism (PSIZE) = x 32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #150 ===
Table 56. Flash memory programming (single bank configuration
nDBANK=1) (continued)
+--------+---------------------+--------------------------+--------+-----+--------+------+
| Symbol | Parameter | Conditions | Min⁽¹⁾ | Typ | Max⁽¹⁾ | Unit |
+========+=====================+==========================+========+=====+========+======+
| Vprog | Programming voltage | 32-bit program operation | 2.7 | - | 3 | V |
| | +--------------------------+--------+-----+--------+------+
| | | 16-bit program operation | 2.1 | - | 3.6 | V |
| | +--------------------------+--------+-----+--------+------+
| | | 8-bit program operation | 1.7 | - | 3.6 | V |
+--------+---------------------+--------------------------+--------+-----+--------+------+
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 100K erase operations.
Table 57. Flash memory programming (dual bank configuration
nDBANK=0)
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| Symbol | Parameter | Conditions | Min⁽¹⁾ | Typ | Max⁽¹⁾ | Unit |
+=============+============================+============================+========+======+========+======+
| tprog | Word programming time | Program/erase parallelism | - | 16 | 100⁽²⁾ | µs |
| | | (PSIZE) = x 8/16/32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| tERASE16KB | Sector (16 KB) erase time | Program/erase | - | 400 | 800 | ms |
| | | parallelism (PSIZE) = x 8 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 250 | 600 | |
| | | parallelism (PSIZE) = x 16 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 200 | 500 | |
| | | parallelism (PSIZE) = x 32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| tERASE64KB | Sector (64 KB) erase time | Program/erase | - | 1100 | 2400 | ms |
| | | parallelism (PSIZE) = x 8 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 800 | 1400 | |
| | | parallelism (PSIZE) = x 16 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 500 | 1100 | |
| | | parallelism (PSIZE) = x 32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| tERASE128KB | Sector (128 KB) erase time | Program/erase | - | 2.1 | 4 | s |
| | | parallelism (PSIZE) = x 8 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 1.5 | 2.6 | |
| | | parallelism (PSIZE) = x 16 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 1 | 2 | |
| | | parallelism (PSIZE) = x 32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
| tME | Mass erase time | Program/erase | - | 16 | 32 | s |
| | | parallelism (PSIZE) = x 8 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 11 | 22 | |
| | | parallelism (PSIZE) = x 16 | | | | |
| | +----------------------------+--------+------+--------+ |
| | | Program/erase | - | 8 | 16 | |
| | | parallelism (PSIZE) = x 32 | | | | |
+-------------+----------------------------+----------------------------+--------+------+--------+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #151 ===
Table 57. Flash memory programming (dual bank configuration
nDBANK=0) (continued)
+--------+---------------------+----------------------------+--------+-----+--------+------+
| Symbol | Parameter | Conditions | Min⁽¹⁾ | Typ | Max⁽¹⁾ | Unit |
+========+=====================+============================+========+=====+========+======+
| tBE | Bank erase time | Program/erase | - | 16 | 32 | s |
| | | parallelism (PSIZE) = x 8 | | | | |
| | +----------------------------+--------+-----+--------+ |
| | | Program/erase | - | 11 | 22 | |
| | | parallelism (PSIZE) = x 16 | | | | |
| | +----------------------------+--------+-----+--------+ |
| | | Program/erase | - | 8 | 16 | |
| | | parallelism (PSIZE) = x 32 | | | | |
+--------+---------------------+----------------------------+--------+-----+--------+------+
| Vprog | Programming voltage | 32-bit program operation | 2.7 | - | 3 | V |
| | +----------------------------+--------+-----+--------+------+
| | | 16-bit program operation | 2.1 | - | 3.6 | V |
| | +----------------------------+--------+-----+--------+------+
| | | 8-bit program operation | 1.7 | - | 3.6 | V |
+--------+---------------------+----------------------------+--------+-----+--------+------+
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 100K erase operations.
Table 58. Flash memory programming with VPP
+-------------+----------------------------+------------------+--------+-----+--------+------+
| Symbol | Parameter | Conditions | Min⁽¹⁾ | Typ | Max⁽¹⁾ | Unit |
+=============+============================+==================+========+=====+========+======+
| tprog | Double word programming | TA = 0 to +40 °C | - | 16 | 100⁽²⁾ | µs |
+-------------+----------------------------+ VDD = 3.3 V +--------+-----+--------+------+
| tERASE32KB | Sector (32 KB) erase time | VPP = 8.5 V | - | 180 | - | ms |
+-------------+----------------------------+ +--------+-----+--------+ |
| tERASE128KB | Sector (128 KB) erase time | | - | 450 | - | |
+-------------+----------------------------+ +--------+-----+--------+ |
| tERASE256KB | Sector (256 KB) erase time | | - | 900 | - | |
+-------------+----------------------------+ +--------+-----+--------+------+
| tME | Mass erase time | | - | 6.9 | - | s |
+-------------+----------------------------+------------------+--------+-----+--------+------+
| Vprog | Programming voltage | - | 2.7 | - | 3.6 | V |
+-------------+----------------------------+------------------+--------+-----+--------+------+
| VPP | VPP voltage range | - | 7 | - | 9 | V |
+-------------+----------------------------+------------------+--------+-----+--------+------+
| IPP | Minimum current sunk on | - | 10 | - | - | mA |
| | the VPP pin | | | | | |
+-------------+----------------------------+------------------+--------+-----+--------+------+
| tVPP⁽³⁾ | Cumulative time during | - | - | - | 1 | hour |
| | which VPP is applied | | | | | |
+-------------+----------------------------+------------------+--------+-----+--------+------+
1. Guaranteed by design.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
Table 59. Flash memory endurance and data retention
+--------+----------------+-----------------------------------------+--------+---------+
| Symbol | Parameter | Conditions | Value | Unit |
| | | +========+ |
| | | | Min⁽¹⁾ | |
+========+================+=========================================+--------+=========+
| NEND | Endurance | TA = –40 to +85 °C (6 suffix versions) | 10 | kcycles |
| | | TA = –40 to +105 °C (7 suffix versions) | | |
+--------+----------------+-----------------------------------------+--------+---------+
| tRET | Data retention | 1 kcycle⁽²⁾ at TA = 85 °C | 30 | Years |
| | +-----------------------------------------+--------+ |
| | | 1 kcycle ⁽²⁾ at TA = 105 °C | 10 | |
| | +-----------------------------------------+--------+ |
| | | 10 kcycles⁽²⁾ at TA = 55 °C | 20 | |
+--------+----------------+-----------------------------------------+--------+---------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #152 ===
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
6.3.17 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 60. They are based on the EMS levels and classes
defined in application note AN1709.
Table 60. EMS characteristics
+--------+------------------------------------------------+-----------------------------------+--------+
| Symbol | Parameter | Conditions | Level/ |
| | | | Class |
+========+================================================+===================================+========+
| VFESD | Voltage limits to be applied on any I/O pin to | VDD = 3.3 V, TA = +25 °C, fHCLK = | 2B |
| | induce a functional disturbance | 216 MHz, conforms to IEC 61000- | |
| | | 4-2 | |
+--------+------------------------------------------------+-----------------------------------+--------+
| VFTB | Fast transient voltage burst limits to be | VDD = 3.3 V, TA =+25 °C, fHCLK = | 5A |
| | applied through 100 pF on VDD and VSS | 168 MHz, conforms to IEC 61000- | |
| | pins to induce a functional disturbance | 4-2 | |
+--------+------------------------------------------------+-----------------------------------+--------+
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #153 ===
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 61. EMI characteristics
+--------+------------+-----------------------------------------------+------------------+-------------+------+
| Symbol | Parameter | Conditions | Monitored | Max vs. | Unit |
| | | | frequency band | [fHSE/fCPU] | |
| | | | +=============+ |
| | | | | 8/200 MHz | |
+========+============+===============================================+==================+-------------+======+
| SEMI | Peak level | VDD = 3.6 V, TA = 25 °C, TFBGA216 package, | 0.1 to 30 MHz | 5 | dBµV |
| | | conforming to IEC61967-2 ART/L1-cache ON, +------------------+-------------+ |
| | | over-drive ON, all peripheral clocks enabled, | 30 to 130 MHz | 10 | |
| | | clock dithering disabled. +------------------+-------------+ |
| | | | 130 MHz to 1 GHz | 18 | |
| | | +------------------+-------------+ |
| | | | 1 GHz to 2 GHz | 10 | |
| | | +------------------+-------------+------+
| | | | EMI Level | 3.5 | - |
| | +-----------------------------------------------+------------------+-------------+------+
| | | VDD = 3.6 V, TA = 25 °C, TFBGA216 package, | 0.1 to 30 MHz | 2 | dBµV |
| | | conforming to IEC61967-2 ART/L1-cache ON, +------------------+-------------+ |
| | | over-drive ON, all peripheral clocks enabled, | 30 to 130 MHz | 9 | |
| | | clock dithering enabled. +------------------+-------------+ |
| | | | 130 MHz to 1 GHz | 14 | |
| | | +------------------+-------------+ |
| | | | 1 GHz to 2 GHz | 9 | |
| | | +------------------+-------------+------+
| | | | EMI Level | 3 | - |
+--------+------------+-----------------------------------------------+------------------+-------------+------+
6.3.18 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/ESDA/JEDEC JS-001-2012 and ANSI/ESD S5.3.1-2009 standards.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #154 ===
Table 62. ESD absolute maximum ratings
+-----------+-------------------------+--------------------------------------------+-------+----------+------+
| Symbol | Ratings | Conditions | Class | Maximum | Unit |
| | | | | value⁽¹⁾ | |
+===========+=========================+============================================+=======+==========+======+
| VESD(HBM) | Electrostatic discharge | TA = +25 °C conforming to ANSI/ESDA/JEDEC | 2 | 2000 | V |
| | voltage (human body | JS-001-2012 | | | |
| | model) | | | | |
+-----------+-------------------------+--------------------------------------------+-------+----------+ |
| VESD(CDM) | Electrostatic discharge | TA = +25 °C conforming to ANSI/ESD S5.3.1- | 3 | 250 | |
| | voltage (charge device | 2009, all packages except TFBGA100 | | | |
| | model) +--------------------------------------------+-------+----------+ |
| | | TA = +25 °C conforming to ANSI/ESD S5.3.1- | 4 | 500 | |
| | | 2009, TFBGA100 package | | | |
+-----------+-------------------------+--------------------------------------------+-------+----------+------+
1. Guaranteed by characterization results.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 63. Electrical sensitivities
+--------+-----------------------+------------------------------------+------------+
| Symbol | Parameter | Conditions | Class |
+========+=======================+====================================+============+
| LU | Static latch-up class | TA = +105 °C conforming to JESD78A | II level A |
+--------+-----------------------+------------------------------------+------------+
6.3.19 I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during the normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when an abnormal injection accidentally happens, susceptibility tests are performed
on a sample basis during the device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
A negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 64.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #155 ===
Table 64. I/O current injection susceptibility
+--------+-------------------------------------------------------+---------------------------+------+
| Symbol | Description | Functional susceptibility | Unit |
| | +-------------+-------------+ |
| | | Negative | Positive | |
| | | injection | injection | |
+--------+-------------------------------------------------------+-------------+-------------+======+
| IINJ | Injected current on BOOT0, DSI_D0P, DSI_D0N, DSI_D1P, | − 0 | 0 | mA |
| | DSI_D1N, DSI_CKP, DSI_CKN pin | | | |
| +-------------------------------------------------------+-------------+-------------+ |
| | Injected current on NRST pin | − 0 | NA⁽¹⁾ | |
| +-------------------------------------------------------+-------------+-------------+ |
| | Injected current on PC0, PC2, PH1_OSCOUT pins | − 0 | NA⁽¹⁾ | |
| +-------------------------------------------------------+-------------+-------------+ |
| | Injected current on any other FT pin | − 5 | NA⁽¹⁾ | |
| +-------------------------------------------------------+-------------+-------------+ |
| | Injected current on any other pins | − 5 | +5 | |
+--------+-------------------------------------------------------+-------------+-------------+------+
1. Injection is not possible.
Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.20 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 65: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 17. All I/Os are
CMOS and TTL compliant.
Table 65. I/O static characteristics
+--------+----------------------------+----------------------+----------------+-----+------------------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+========+============================+======================+================+=====+==================+======+
| VIL | FT, TTa and NRST I/O input | 1.7 V≤ VDD≤ 3.6 V | - | - | 0.35VDD −0.04⁽¹⁾ | V |
| | low level voltage | | | +------------------+ |
| | | | | | 0.3VDD⁽²⁾ | |
| +----------------------------+----------------------+----------------+-----+------------------+ |
| | BOOT I/O input low level | 1.75 V≤ VDD ≤ 3.6 V, | - | - | 0.1VDD+0.1⁽¹⁾ | |
| | voltage | –40 °C≤ TA ≤ 105 °C | | | | |
| | +----------------------+----------------+-----| | |
| | | 1.7 V≤ VDD ≤ 3.6 V, | - | - | | |
| | | 0 °C≤ TA ≤ 105 °C | | | | |
+--------+----------------------------+----------------------+----------------+-----+------------------+------+
| VIH | FT, TTa and NRST I/O input | 1.7 V≤ VDD≤ 3.6 V | 0.45VDD+0.3⁽¹⁾ | - | - | V |
| | high level voltage⁽⁵⁾ | |----------------+ | | |
| | | | 0.7VDD⁽²⁾ | | | |
| +----------------------------+----------------------+----------------+-----+------------------+ |
| | BOOT I/O input high level | 1.75 V≤ VDD ≤ 3.6 V, | 0.17VDD+0.7⁽¹⁾ | - | - | |
| | voltage | –40 °C≤ TA ≤ 105 °C | | | | |
| | +----------------------+ | | | |
| | | 1.7 V≤ VDD ≤ 3.6 V, | | | | |
| | | 0 °C≤ TA ≤ 105 °C | | | | |
+--------+----------------------------+----------------------+----------------+-----+------------------+------+
| VHYS | FT, TTa and NRST I/O input | 1.7 V≤ VDD≤ 3.6 V | 10%VDD⁽³⁾ | - | - | V |
| | hysteresis | | | | | |
| +----------------------------+----------------------+----------------+-----+------------------+ |
| | BOOT I/O input hysteresis | 1.75 V≤ VDD ≤ 3.6 V, | 0.1 | - | - | |
| | | –40 °C≤ TA ≤ 105 °C | | | | |
| | +----------------------+ | | | |
| | | 1.7 V≤ VDD ≤ 3.6 V, | | | | |
| | | 0 °C≤ TA ≤ 105 °C | | | | |
+--------+----------------------------+----------------------+----------------+-----+------------------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #156 ===
Table 65. I/O static characteristics (continued)
+--------+-------------------------------+-----------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+========+===============================+=================+=====+=====+=====+======+
| Ilkg | I/O input leakage current ⁽⁴⁾ | VSS ≤ VIN ≤ VDD | - | - | ±1 | µA |
| +-------------------------------+-----------------+-----+-----+-----+ |
| | I/O FT input leakage current | VIN = 5 V | - | - | 3 | |
| | (5) | | | | | |
+--------+----------------+--------------+-----------------+-----+-----+-----+------+
| RPU | Weak pull-up | All pins | VIN = VSS | 30 | 40 | 50 | kΩ |
| | equivalent | except for | | | | | |
| | resistor⁽⁶⁾ | PA10/PB12 | | | | | |
| | | (OTG_FS_I | | | | | |
| | | D,OTG_HS_ | | | | | |
| | | ID) | | | | | |
| | +--------------+ +-----+-----+-----+ |
| | | PA10/PB12 | | 7 | 10 | 14 | |
| | | (OTG_FS_I | | | | | |
| | | D,OTG_HS_ | | | | | |
| | | ID) | | | | | |
+--------+----------------+--------------+-----------------+-----+-----+-----+ |
| RPD | Weak pull- | All pins | VIN = VDD | 30 | 40 | 50 | |
| | down | except for | | | | | |
| | equivalent | PA10/PB12 | | | | | |
| | resistor⁽⁷⁾ | (OTG_FS_I | | | | | |
| | | D,OTG_HS_ | | | | | |
| | | ID) | | | | | |
| | +--------------+ +-----+-----+-----+ |
| | | PA10/PB12 | | 7 | 10 | 14 | |
| | | (OTG_FS_I | | | | | |
| | | D,OTG_HS_ | | | | | |
| | | ID) | | | | | |
+--------+----------------+--------------+-----------------+-----+-----+-----+------+
| CIO⁽⁸⁾ | I/O pin capacitance | - | - | 5 | - | pF |
+--------+-------------------------------+-----------------+-----+-----+-----+------+
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 64: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 64: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 38.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #157 ===
Figure 38. FT I/O input characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which
can sink or source up to ±3mA. When using the PC13 to PC15 and PI8 GPIOs in output
mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 15).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 15).
Output voltage levels
Unless otherwise specified, the parameters given in Table 66 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 17. All I/Os are CMOS and TTL compliant.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #158 ===
Table 66. Output voltage characteristics
+---------+------------------------------------------+---------------------+------------+--------+------+
| Symbol | Parameter | Conditions | Min | Max | Unit |
+=========+==========================================+=====================+============+========+======+
| VOL⁽¹⁾ | Output low level voltage for an I/O pin | CMOS port⁽²⁾ | - | 0.4 | V |
| | | IIO = +8 mA | | | |
| | | 2.7 V ≤ VDD ≤ 3.6 V | | | |
+---------+------------------------------------------+---------------------+------------+--------+ |
| VOH ⁽³⁾ | Output high level voltage for an I/O pin | CMOS port⁽²⁾ | VDD − 0.4 | - | |
| | except PC14 | IIO = -8 mA | | | |
| | | 2.7 V ≤ VDD ≤ 3.6 V | | | |
+---------+------------------------------------------+---------------------+------------+--------+ |
| VOH⁽³⁾ | Output high level voltage for PC14 | CMOS port⁽²⁾ | VDD − 0.4 | - | |
| | | IIO = -2 mA | | | |
| | | 2.7 V ≤ VDD ≤ 3.6 V | | | |
+---------+------------------------------------------+---------------------+------------+--------+------+
| VOL ⁽¹⁾ | Output low level voltage for an I/O pin | TTL port⁽²⁾ | - | 0.4 | V |
| | | IIO =+8mA | | | |
| | | 2.7 V ≤ VDD ≤ 3.6 V | | | |
+---------+------------------------------------------+---------------------+------------+--------+ |
| VOH ⁽³⁾ | Output high level voltage for an I/O pin | TTL port⁽²⁾ | 2.4 | - | |
| | except PC14 | IIO =-8mA | | | |
| | | 2.7 V ≤ VDD ≤ 3.6 V | | | |
+---------+------------------------------------------+---------------------+------------+--------+------+
| VOL⁽¹⁾ | Output low level voltage for an I/O pin | IIO = +20 mA | - | 1.3⁽⁴⁾ | V |
| | | 2.7 V ≤ VDD ≤ 3.6 V | | | |
+---------+------------------------------------------+---------------------+------------+--------+ |
| VOH⁽³⁾ | Output high level voltage for an I/O pin | IIO = -20 mA | VDD−1.3⁽⁴⁾ | - | |
| | except PC14 | 2.7 V ≤ VDD ≤ 3.6 V | | | |
+---------+------------------------------------------+---------------------+------------+--------+------+
| VOL⁽¹⁾ | Output low level voltage for an I/O pin | IIO = +6 mA | - | 0.4⁽⁴⁾ | V |
| | | 1.8 V ≤ VDD ≤ 3.6 V | | | |
+---------+------------------------------------------+---------------------+------------+--------+ |
| VOH⁽³⁾ | Output high level voltage for an I/O pin | IIO = -6 mA | VDD−0.4⁽⁴⁾ | - | |
| | except PC14 | 1.8 V ≤ VDD ≤ 3.6 V | | | |
+---------+------------------------------------------+---------------------+------------+--------+------+
| VOL⁽¹⁾ | Output low level voltage for an I/O pin | IIO = +4 mA | - | 0.4⁽⁵⁾ | V |
| | | 1.7 V ≤ VDD ≤ 3.6V | | | |
+---------+------------------------------------------+---------------------+------------+--------+ |
| VOH ⁽³⁾ | Output high level voltage for an I/O pin | IIO = -4 mA | VDD−0.4⁽⁵⁾ | - | |
| | except PC14 | 1.7 V ≤ VDD ≤ 3.6V | | | |
+---------+------------------------------------------+---------------------+------------+--------+ |
| VOH⁽³⁾ | Output high level voltage for PC14 | IIO = -1 mA | VDD−0.4⁽⁵⁾ | - | |
| | | 1.7 V ≤ VDD ≤ 3.6V | | | |
+---------+------------------------------------------+---------------------+------------+--------+------+
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data.
5. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 39 and
Table 67, respectively.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #159 ===
Unless otherwise specified, the parameters given in Table 67 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.
Table 67. I/O AC characteristics⁽¹⁾⁽²⁾
+-----------+-------------+-------------------------------+----------------------------+-----+-----+--------+------+
| OSPEEDRy | Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
| [1:0] bit | | | | | | | |
| value⁽¹⁾ | | | | | | | |
+===========+=============+===============================+============================+=====+=====+========+======+
| 00 | fmax(IO)out | Maximum frequency⁽³⁾ | CL = 50 pF, VDD ≥ 2.7 V | - | - | 4 | MHz |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 50 pF, VDD ≥ 1.7 V | - | - | 2 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 2.7 V | - | - | 8 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 1.8 V | - | - | 4 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 1.7 V | - | - | 3 | |
| +-------------+-------------------------------+----------------------------+-----+-----+--------+------+
| | tf(IO)out/ | Output high to low level fall | CL = 50 pF, VDD = 1.7 V to | - | - | 100 | ns |
| | tr(IO)out | time and output low to high | 3.6 V | | | | |
| | | level rise time | | | | | |
+-----------+-------------+-------------------------------+----------------------------+-----+-----+--------+------+
| 01 | fmax(IO)out | Maximum frequency⁽³⁾ | CL = 50 pF, VDD≥ 2.7 V | - | - | 25 | MHz |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 50 pF, VDD≥ 1.8 V | - | - | 12.5 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 50 pF, VDD≥ 1.7 V | - | - | 10 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 2.7 V | - | - | 50 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD≥ 1.8 V | - | - | 20 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD≥ 1.7 V | - | - | 12.5 | |
| +-------------+-------------------------------+----------------------------+-----+-----+--------+------+
| | tf(IO)out/ | Output high to low level fall | CL = 50 pF, VDD ≥ 2.7 V | - | - | 10 | ns |
| | tr(IO)out | time and output low to high +----------------------------+-----+-----+--------+ |
| | | level rise time | CL = 10 pF, VDD ≥ 2.7 V | - | - | 6 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 50 pF, VDD ≥ 1.7 V | - | - | 20 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 1.7 V | - | - | 10 | |
+-----------+-------------+-------------------------------+----------------------------+-----+-----+--------+------+
| 10 | fmax(IO)out | Maximum frequency⁽³⁾ | CL = 40 pF, VDD ≥ 2.7 V | - | - | 50⁽⁴⁾ | MHz |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 2.7 V | - | - | 100⁽⁴⁾ | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 40 pF, VDD ≥ 1.7 V | - | - | 25 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 1.8 V | - | - | 50 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 1.7 V | - | - | 42.5 | |
| +-------------+-------------------------------+----------------------------+-----+-----+--------+------+
| | tf(IO)out/ | Output high to low level fall | CL = 40 pF, VDD ≥2.7 V | - | - | 6 | ns |
| | tr(IO)out | time and output low to high +----------------------------+-----+-----+--------+ |
| | | level rise time | CL = 10 pF, VDD ≥ 2.7 V | - | - | 4 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 40 pF, VDD ≥ 1.7 V | - | - | 10 | |
| | | +----------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 1.7 V | - | - | 6 | |
+-----------+-------------+-------------------------------+----------------------------+-----+-----+--------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #160 ===
Table 67. I/O AC characteristics⁽¹⁾⁽²⁾ (continued)
+-----------+-------------+---------------------------------+-------------------------+-----+-----+--------+------+
| OSPEEDRy | Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
| [1:0] bit | | | | | | | |
| value⁽¹⁾ | | | | | | | |
+===========+=============+=================================+=========================+=====+=====+========+======+
| 11 | fmax(IO)out | Maximum frequency⁽³⁾ | CL = 30 pF, VDD ≥ 2.7 V | - | - | 100⁽⁴⁾ | MHz |
| | | +-------------------------+-----+-----+--------+ |
| | | | CL = 30 pF, VDD ≥ 1.8 V | - | - | 50 | |
| | | +-------------------------+-----+-----+--------+ |
| | | | CL = 30 pF, VDD ≥ 1.7 V | - | - | 42.5 | |
| | | +-------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD≥ 2.7 V | - | - | 180⁽⁴⁾ | |
| | | +-------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 1.8 V | - | - | 100 | |
| | | +-------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 1.7 V | - | - | 72.5 | |
| +-------------+---------------------------------+-------------------------+-----+-----+--------+------+
| | tf(IO)out/ | Output high to low level fall | CL = 30 pF, VDD ≥ 2.7 V | - | - | 4 | ns |
| | tr(IO)out | time and output low to high +-------------------------+-----+-----+--------+ |
| | | level rise time | CL = 30 pF, VDD ≥1.8 V | - | - | 6 | |
| | | +-------------------------+-----+-----+--------+ |
| | | | CL = 30 pF, VDD ≥1.7 V | - | - | 7 | |
| | | +-------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥ 2.7 V | - | - | 2.5 | |
| | | +-------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥1.8 V | - | - | 3.5 | |
| | | +-------------------------+-----+-----+--------+ |
| | | | CL = 10 pF, VDD ≥1.7 V | - | - | 4 | |
+-----------+-------------+---------------------------------+-------------------------+-----+-----+--------+------+
| - | tEXTIpw | Pulse width of external signals | - | 10 | - | - | ns |
| | | detected by the EXTI | | | | | |
| | | controller | | | | | |
+-----------+-------------+---------------------------------+-------------------------+-----+-----+--------+------+
1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F76xxx and STM32F77xxx reference
manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 39.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Figure 39. I/O AC characteristics definition
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #161 ===
6.3.21 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 65: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 68 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.
Table 68. NRST pin characteristics
+--------------+-------------------------------------+-----------------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+==============+=====================================+=======================+=====+=====+=====+======+
| RPU | Weak pull-up equivalent resistor⁽¹⁾ | VIN = VSS | 30 | 40 | 50 | kΩ |
+--------------+-------------------------------------+-----------------------+-----+-----+-----+------+
| VF(NRST)⁽²⁾ | NRST Input filtered pulse | - | - | - | 100 | ns |
+--------------+-------------------------------------+-----------------------+-----+-----+-----+------+
| VNF(NRST)⁽²⁾ | NRST Input not filtered pulse | VDD > 2.7 V | 300 | - | - | ns |
+--------------+-------------------------------------+-----------------------+-----+-----+-----+------+
| TNRST_OUT | Generated reset pulse duration | Internal Reset source | 20 | - | - | µs |
+--------------+-------------------------------------+-----------------------+-----+-----+-----+------+
1. Trehseis tpaunclle-u mpu isst dbee smiginnimedu mw i(t~h1 a0 %tru oer dreesr)is.tance in series with a switchable PMOS. This PMOS contribution to the series
2. Guaranteed by design.
Figure 40. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 65. Otherwise the reset is not taken into account by the device.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #162 ===
6.3.22 TIM timer characteristics
The parameters given in Table 69 are guaranteed by design.
Refer to Section 6.3.20: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 69. TIMx characteristics⁽¹⁾⁽²⁾
+------------+-------------------------+-------------------------+-----+------------+----------+
| Symbol | Parameter | Conditions⁽³⁾ | Min | Max | Unit |
+============+=========================+=========================+=====+============+==========+
| tres(TIM) | Timer resolution time | AHB/APBx prescaler=1 | 1 | - | tTIMxCLK |
| | | or 2 or 4, fTIMxCLK = | | | |
| | | 216 MHz | | | |
| | |-------------------------+-----+------------+----------+
| | | AHB/APBx | 1 | - | tTIMxCLK |
| | | prescaler>4, fTIMxCLK = | | | |
| | | 100 MHz | | | |
+------------+-------------------------+-------------------------+-----+------------+----------+
| fEXT | Timer external clock | fTIMxCLK = 216 MHz | 0 | fTIMxCLK/2 | MHz |
| | frequency on CH1 to CH4 | | | | |
+------------+-------------------------+ +-----+------------+----------+
| | Timer resolution | | - | 16/32 | bit |
+------------+-------------------------+-------------------------+-----+------------+----------+
| tMAX_COUNT | Maximum possible count | - | - | 65536 × | tTIMxCLK |
| | with 32-bit counter | | | 65536 | |
+------------+-------------------------+-------------------------+-----+------------+----------+
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK =
4x PCLKx.
6.3.23 RTC characteristics
Table 70. RTC characteristics
+--------+-------------------------------+--------------------------+-----+-----+
| Symbol | Parameter | Conditions | Min | Max |
+========+===============================+==========================+=====+=====+
| - | fPCLK1/RTCCLK frequency ratio | Any read/write operation | 4 | - |
| | | from/to an RTC register | | |
+--------+-------------------------------+--------------------------+-----+-----+
6.3.24 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 71 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 17.
Table 71. ADC characteristics
+--------+----------------------------+------------------------+--------+-----+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+========+============================+========================+========+=====+======+======+
| VDDA | Power supply | VDDA − VREF+ < 1.2 V | 1.7⁽¹⁾ | - | 3.6 | V |
+--------+----------------------------| +--------+-----+------+------+
| VREF+ | Positive reference voltage | | 1.7⁽¹⁾ | - | ⱽDDA | V |
+--------+----------------------------+------------------------+--------+-----+------+------+
| fADC | ADC clock frequency | VDDA = 1.7⁽¹⁾ to 2.4 V | 0.6 | 15 | 18 | MHz |
| | +------------------------+--------+-----+------+------+
| | | VDDA = 2.4 to 3.6 V | 0.6 | 30 | 36 | MHz |
+--------+----------------------------+------------------------+--------+-----+------+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #163 ===
Table 71. ADC characteristics (continued)
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+============+==================================+=========================+==================+======+========+========+
| fTRIG⁽²⁾ | External trigger frequency | fADC = 30 MHz, | - | - | 1764 | kHz |
| | | 12-bit resolution | | | | |
| | +-------------------------+------------------+------+--------+--------+
| | | - | - | - | 17 | 1/fADC |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| VAIN | Conversion voltage range⁽³⁾ | - | 0 | - | ⱽREF+ | V |
| | | | (VSSA or VREF- | | | |
| | | | tied to ground) | | | |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| RAIN⁽²⁾ | External input impedance | See Equation 1 for | - | - | 50 | kΩ |
| | | details | | | | |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| RADC⁽²⁾⁽⁴⁾ | Sampling switch resistance | - | 1.5 | - | 6 | kΩ |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| CADC⁽²⁾ | Internal sample and hold | - | - | 4 | 7 | pF |
| | capacitor | | | | | |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| tlat⁽²⁾ | Injection trigger conversion | fADC = 30 MHz | - | - | 0.100 | µs |
| | latency +-------------------------+------------------+------+--------+--------+
| | | - | - | - | 3⁽⁵⁾ | 1/fADC |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| tlatr⁽²⁾ | Regular trigger conversion | fADC = 30 MHz | - | - | 0.067 | µs |
| | latency +-------------------------+------------------+------+--------+--------+
| | | - | - | - | 2⁽⁵⁾ | 1/fADC |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| tS⁽²⁾ | Sampling time | fADC = 30 MHz | 0.100 | - | 16 | µs |
| | +-------------------------+------------------+------+--------+--------+
| | | - | 3 | - | 480 | 1/fADC |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| tSTAB⁽²⁾ | Power-up time | - | - | 2 | 3 | µs |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| tCONV⁽²⁾ | Total conversion time (including | fADC = 30 MHz | 0.50 | - | 16.40 | µs |
| | sampling time) | 12-bit resolution | | | | |
| | +-------------------------+------------------+------+--------+--------+
| | | fADC = 30 MHz | 0.43 | - | 16.34 | µs |
| | | 10-bit resolution | | | | |
| | +-------------------------+------------------+------+--------+--------+
| | | fADC = 30 MHz | 0.37 | - | 16.27 | µs |
| | | 8-bit resolution | | | | |
| | +-------------------------+------------------+------+--------+--------+
| | | fADC = 30 MHz | 0.30 | - | 16.20 | µs |
| | | 6-bit resolution | | | | |
| | +-------------------------+------------------+------+--------+--------+
| | | 9 to 492 (tS for sampling +n-bit resolution for successive | 1/fADC |
| | | approximation) | |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
| fS⁽²⁾ | Sampling rate | 12-bit resolution | - | - | 2.4 | Msps |
| | (fADC = 36 MHz, and | Single ADC | | | | |
| | tS = 3 ADC cycles) +-------------------------+------------------+------+--------+--------+
| | | 12-bit resolution | - | - | 4.5 | Msps |
| | | Interleave Dual ADC | | | | |
| | | mode | | | | |
| | +-------------------------+------------------+------+--------+--------+
| | | 12-bit resolution | - | - | 7.2 | Msps |
| | | Interleave Triple ADC | | | | |
| | | mode | | | | |
+------------+----------------------------------+-------------------------+------------------+------+--------+--------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #164 ===
Table 71. ADC characteristics (continued)
+-----------+---------------------------+------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+===========================+============+=====+=====+=====+======+
| IVREF+⁽²⁾ | ADC VREF DC current | - | - | 300 | 500 | µA |
| | consumption in conversion | | | | | |
| | mode | | | | | |
+-----------+---------------------------+------------+-----+-----+-----+------+
| IVDDA⁽²⁾ | ADC VDDA DC current | - | - | 1.6 | 1.8 | mA |
| | consumption in conversion | | | | | |
| | mode | | | | | |
+-----------+---------------------------+------------+-----+-----+-----+------+
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
2. Guaranteed by characterization results.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 71.
Equation 1: RAIN max formula
R = -------------------(--k------–----- 0----.--5- ---- ) ------------------- –R
ᴬᴵᴺ fADC × CADC × ln(2ᴺ ⁺ ² ) ᴬᴰᶜ
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
Table 72. ADC static accuracy at fADC = 18 MHz
+--------+------------------------------+---------------------+-----+--------+------+
| Symbol | Parameter | Test conditions | Typ | Max⁽¹⁾ | Unit |
+========+==============================+=====================+=====+========+======+
| ET | Total unadjusted error | fADC =18 MHz | ±3 | ±4 | LSB |
+--------+------------------------------+ VDDA = 1.7 to 3.6 V +-----+--------+ |
| EO | Offset error | VREF = 1.7 to 3.6 V | ±2 | ±3 | |
+--------+------------------------------+ VDDA − VREF < 1.2 V +-----+--------+ |
| EG | Gain error | | ±1 | ±3 | |
+--------+------------------------------+ +-----+--------+ |
| ED | Differential linearity error | | ±1 | ±2 | |
+--------+------------------------------+ +-----+--------+ |
| EL | Integral linearity error | | ±2 | ±3 | |
+--------+------------------------------+---------------------+-----+--------+------+
1. Guaranteed by characterization results.
Table 73. ADC static accuracy at fADC = 30 MHz
+--------+------------------------------+----------------------+------+--------+------+
| Symbol | Parameter | Test conditions | Typ | Max⁽¹⁾ | Unit |
+========+==============================+======================+======+========+======+
| ET | Total unadjusted error | fADC = 30 MHz, | ±2 | ±5 | LSB |
+--------+------------------------------+ RAIN < 10 kΩ, +------+--------+ |
| EO | Offset error | VDDA = 2.4 to 3.6 V, | ±1.5 | ±2.5 | |
+--------+------------------------------+ VREF = 1.7 to 3.6 V, +------+--------+ |
| EG | Gain error | VDDA − VREF < 1.2 V | ±1.5 | ±4 | |
+--------+------------------------------+ +------+--------+ |
| ED | Differential linearity error | | ±1 | ±2 | |
+--------+------------------------------+ +------+--------+ |
| EL | Integral linearity error | | ±1.5 | ±3 | |
+--------+------------------------------+----------------------+------+--------+------+
1. Guaranteed by characterization results.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #165 ===
Table 74. ADC static accuracy at fADC = 36 MHz
+--------+------------------------------+----------------------+-----+--------+------+
| Symbol | Parameter | Test conditions | Typ | Max⁽¹⁾ | Unit |
+========+==============================+======================+=====+========+======+
| ET | Total unadjusted error | fADC =36 MHz, | ±4 | ±7 | LSB |
+--------+------------------------------+ VDDA = 2.4 to 3.6 V, +-----+--------+ |
| EO | Offset error | VREF = 1.7 to 3.6 V | ±2 | ±3 | |
+--------+------------------------------+ VDDA − VREF < 1.2 V +-----+--------+ |
| EG | Gain error | | ±3 | ±6 | |
+--------+------------------------------+ +-----+--------+ |
| ED | Differential linearity error | | ±2 | ±3 | |
+--------+------------------------------+ +-----+--------+ |
| EL | Integral linearity error | | ±3 | ±6 | |
+--------+------------------------------+----------------------+-----+--------+------+
1. Guaranteed by characterization results.
Table 75. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions⁽¹⁾
+--------+--------------------------------------+--------------------------+------+------+-----+------+
| Symbol | Parameter | Test conditions | Min | Typ | Max | Unit |
+========+======================================+==========================+======+======+=====+======+
| ENOB | Effective number of bits | fADC =18 MHz | 10.3 | 10.4 | - | bits |
+--------+--------------------------------------+ VDDA = VREF+= 1.7 V +------+------+-----+------+
| SINAD | Signal-to-noise and distortion ratio | Input Frequency = 20 KHz | 64 | 64.2 | - | dB |
+--------+--------------------------------------+ Temperature = 25 °C +------+------+-----+ |
| SNR | Signal-to-noise ratio | | 64 | 65 | - | |
+--------+--------------------------------------+ +------+------+-----+ |
| THD | Total harmonic distortion | | − 67 | − 72 | - | |
+--------+--------------------------------------+--------------------------+------+------+-----+------+
1. Guaranteed by characterization results.
Table 76. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions⁽¹⁾
+--------+--------------------------------------+--------------------------+------+------+-----+------+
| Symbol | Parameter | Test conditions | Min | Typ | Max | Unit |
+========+======================================+==========================+======+======+=====+======+
| ENOB | Effective number of bits | fADC =36 MHz | 10.6 | 10.8 | - | bits |
+--------+--------------------------------------+ VDDA = VREF+ = 3.3 V +------+------+-----+------+
| SINAD | Signal-to noise and distortion ratio | Input Frequency = 20 KHz | 66 | 67 | - | dB |
+--------+--------------------------------------+ Temperature = 25 °C +------+------+-----+ |
| SNR | Signal-to noise ratio | | 64 | 68 | - | |
+--------+--------------------------------------+ +------+------+-----+ |
| THD | Total harmonic distortion | | − 70 | − 72 | - | |
+--------+--------------------------------------+--------------------------+------+------+-----+------+
1. Guaranteed by characterization results.
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.20 does not affect the ADC accuracy.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #166 ===
Figure 41. ADC accuracy characteristics
1. See also Table 73.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 42. Typical connection diagram using the ADC
1. Refer to Table 71 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #167 ===
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 43 or Figure 44,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 43. Power supply and reference decoupling (VREF+ not connected to VDDA)
1. VREF+ input is available on all packages except TFBGA100 whereas the VREF– s available only on
UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA.
Figure 44. Power supply and reference decoupling (VREF+ connected to VDDA)
1. VREF+ input is available on all packages except TFBGA100 whereas the VREF– s available only on
UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #168 ===
6.3.25 Temperature sensor characteristics
Table 77. Temperature sensor characteristics
+--------------+----------------------------------------------------------------+-----+------+-----+-------+
| Symbol | Parameter | Min | Typ | Max | Unit |
+==============+================================================================+=====+======+=====+=======+
| TL⁽¹⁾ | VSENSE linearity with temperature | - | ±1 | ±2 | °C |
+--------------+----------------------------------------------------------------+-----+------+-----+-------+
| Avg_Slope⁽¹⁾ | Average slope | - | 2.5 | - | mV/°C |
+--------------+----------------------------------------------------------------+-----+------+-----+-------+
| V25⁽¹⁾ | Voltage at 25 °C | - | 0.76 | - | V |
+--------------+----------------------------------------------------------------+-----+------+-----+-------+
| tSTART⁽²⁾ | Startup time | - | 6 | 10 | µs |
+--------------+----------------------------------------------------------------+-----+------+-----+-------+
| TS_temp⁽²⁾ | ADC sampling time when reading the temperature (1 °C accuracy) | 10 | - | - | µs |
+--------------+----------------------------------------------------------------+-----+------+-----+-------+
1. Guaranteed by characterization results.
2. Guaranteed by design.
Table 78. Temperature sensor calibration values
+---------+----------------------------------------------------------------+---------------------------+
| Symbol | Parameter | Memory address |
+=========+================================================================+===========================+
| TS_CAL1 | TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V | 0x1FF0 F44C - 0x1FF0 F44D |
+---------+----------------------------------------------------------------+---------------------------+
| TS_CAL2 | TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V | 0x1FF0 F44E - 0x1FF0 F44F |
+---------+----------------------------------------------------------------+---------------------------+
6.3.26 VBAT monitoring characteristics
Table 79. VBAT monitoring characteristics
+---------------+-----------------------------------------+-----+-----+-----+------+
| Symbol | Parameter | Min | Typ | Max | Unit |
+===============+=========================================+=====+=====+=====+======+
| R | | - | 50 | - | KΩ |
+---------------+-----------------------------------------+-----+-----+-----+------+
| Q | Ratio on VBAT measurement | - | 4 | - | - |
+---------------+-----------------------------------------+-----+-----+-----+------+
| Er⁽¹⁾ | Error on Q | –1 | - | +1 | % |
+---------------+-----------------------------------------+-----+-----+-----+------+
| TS_vbat⁽²⁾⁽²⁾ | ADC sampling time when reading the VBAT | 5 | - | - | µs |
| | 1 mV accuracy | | | | |
+---------------+-----------------------------------------+-----+-----+-----+------+
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.27 Reference voltage
The parameters given in Table 80 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.
Table 80. internal reference voltage
+---------------+--------------------------------------------+-----------------------+------+------+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===============+============================================+=======================+======+======+======+======+
| VREFINT | Internal reference voltage | –40 °C < TA < +105 °C | 1.18 | 1.21 | 1.24 | V |
+---------------+--------------------------------------------+-----------------------+------+------+------+------+
| TS_vrefint⁽¹⁾ | ADC sampling time when reading the | - | 10 | - | - | µs |
| | internal reference voltage | | | | | |
+---------------+--------------------------------------------+-----------------------+------+------+------+------+
| VREFINT_s⁽²⁾ | Internal reference voltage spread over the | VDD = 3V ± 10mV | - | 3 | 5 | mV |
| | temperature range | | | | | |
+---------------+--------------------------------------------+-----------------------+------+------+------+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #169 ===
Table 80. internal reference voltage (continued)
+-----------+-------------------------+------------+-----+-----+-----+--------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+=========================+============+=====+=====+=====+========+
| TCoeff⁽²⁾ | Temperature coefficient | - | - | 30 | 50 | ppm/°C |
+-----------+-------------------------+------------+-----+-----+-----+--------+
| tSTART⁽²⁾ | Startup time | - | - | 6 | 10 | µs |
+-----------+-------------------------+------------+-----+-----+-----+--------+
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
Table 81. Internal reference voltage calibration values
+------------+--------------------------------------------------------+---------------------------+
| Symbol | Parameter | Memory address |
+============+========================================================+===========================+
| VREFIN_CAL | Raw data acquired at temperature of 30 °C VDDA = 3.3 V | 0x1FF0 F44A - 0x1FF0 F44B |
+------------+--------------------------------------------------------+---------------------------+
6.3.28 DAC electrical characteristics
Table 82. DAC characteristics
+----------+-------------------------------+--------+-----+---------+------+------------------------------------------+
| Symbol | Parameter | Min | Typ | Max | Unit | Comments |
+==========+===============================+========+=====+=========+======+==========================================+
| VDDA | Analog supply voltage | 1.7⁽¹⁾ | - | 3.6 | V | - |
+----------+-------------------------------+--------+-----+---------+------+------------------------------------------+
| VREF+ | Reference supply voltage | 1.7⁽¹⁾ | - | 3.6 | V | VREF+ ≤ VDDA |
+----------+-------------------------------+--------+-----+---------+------+------------------------------------------+
| VSSA | Ground | 0 | - | 0 | V | - |
+----------+----------------+--------------+--------+-----+---------+------+------------------------------------------+
| RLOAD⁽²⁾ | with buffer ON | Connected to | 5 | - | - | kΩ | - |
| | | VSSA | | | | | |
| | +--------------+--------+-----+---------+ | |
| | | Connected to | 25 | - | - | | |
| | | VDDA | | | | | |
+----------+----------------+--------------+--------+-----+---------+------+------------------------------------------+
| RO⁽²⁾ | Impedance output with buffer | - | - | 15 | kΩ | When the buffer is OFF, the Minimum |
| | OFF | | | | | resistive load between DAC_OUT and |
| | | | | | | VSS to have a 1% accuracy is 1.5 MΩ |
+----------+-------------------------------+--------+-----+---------+------+------------------------------------------+
| CLOAD⁽²⁾ | Capacitive load | - | - | 50 | pF | Maximum capacitive load at DAC_OUT |
| | | | | | | pin (when the buffer is ON). |
+----------+-------------------------------+--------+-----+---------+------+------------------------------------------+
| DAC_OUT | Lower DAC_OUT voltage | 0.2 | - | - | V | It gives the maximum output excursion of |
| min⁽²⁾ | with buffer ON | | | | | the DAC. |
+----------+-------------------------------+--------+-----+---------+------+ It corresponds to 12-bit input code |
| DAC_OUT | Higher DAC_OUT voltage | - | - | VDDA − | V | (0x0E0) to (0xF1C) at VREF+ = 3.6 V and |
| max⁽²⁾ | with buffer ON | | | 0.2 | | (0x1C7) to (0xE38) at VREF+ = 1.7 V |
+----------+-------------------------------+--------+-----+---------+------+------------------------------------------+
| DAC_OUT | Lower DAC_OUT voltage | - | 0.5 | - | mV | It gives the maximum output excursion of |
| min⁽²⁾ | with buffer OFF | | | | | the DAC. |
+----------+-------------------------------+--------+-----+---------+------+ |
| DAC_OUT | Higher DAC_OUT voltage | - | - | VREF+ − | V | |
| max⁽²⁾ | with buffer OFF | | | 1LSB | | |
+----------+-------------------------------+--------+-----+---------+------+------------------------------------------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #170 ===
Table 82. DAC characteristics (continued)
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
| Symbol | Parameter | Min | Typ | Max | Unit | Comments |
+==============+==================================+=====+=====+======+======+============================================+
| IVREF+⁽⁴⁾ | DAC DC VREF current | - | 170 | 240 | µA | With no load, worst code (0x800) at |
| | consumption in quiescent | | | | | VREF+ = 3.6 V in terms of DC |
| | mode (Standby mode) | | | | | consumption on the inputs |
| | +-----+-----+------+ +--------------------------------------------+
| | | - | 50 | 75 | | With no load, worst code (0xF1C) at |
| | | | | | | VREF+ = 3.6 V in terms of DC |
| | | | | | | consumption on the inputs |
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
| IDDA⁽⁴⁾ | DAC DC VDDA current | - | 280 | 380 | µA | With no load, middle code (0x800) on the |
| | consumption in quiescent | | | | | inputs |
| | mode⁽³⁾ +-----+-----+------+------+--------------------------------------------+
| | | - | 475 | 625 | µA | With no load, worst code (0xF1C) at |
| | | | | | | VREF+ = 3.6 V in terms of DC |
| | | | | | | consumption on the inputs |
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
| DNL⁽⁴⁾ | Differential non linearity | - | - | ±0.5 | LSB | Given for the DAC in 10-bit configuration. |
| | Difference between two +-----+-----+------+------+--------------------------------------------+
| | consecutive code-1LSB) | - | - | ±2 | LSB | Given for the DAC in 12-bit configuration. |
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
| INL⁽⁴⁾ | Integral non linearity | - | - | ±1 | LSB | Given for the DAC in 10-bit configuration. |
| | (difference between | | | | | |
| | measured value at Code i | | | | | |
| | and the value at Code i on a +-----+-----+------+------+--------------------------------------------+
| | line drawn between Code 0 | - | - | ±4 | LSB | Given for the DAC in 12-bit configuration. |
| | and last Code 1023) | | | | | |
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
| Offset⁽⁴⁾ | Offset error | - | - | ±10 | mV | Given for the DAC in 12-bit configuration |
| | (difference between +-----+-----+------+------+--------------------------------------------+
| | measured value at Code | - | - | ±3 | LSB | Given for the DAC in 10-bit at VREF+ = |
| | (0x800) and the ideal value = | | | | | 3.6 V |
| | VREF+/2) +-----+-----+------+------+--------------------------------------------+
| | | - | - | ±12 | LSB | Given for the DAC in 12-bit at VREF+ = |
| | | | | | | 3.6 V |
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
| Gain | Gain error | - | - | ±0.5 | % | Given for the DAC in 12-bit configuration |
| error⁽⁴⁾ | | | | | | |
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
| tSETTLING⁽⁴⁾ | Settling time (full scale: for a | - | 3 | 6 | µs | CLOAD ≤ 50 pF, |
| | 10-bit input code transition | | | | | RLOAD ≥ 5 kΩ |
| | between the lowest and the | | | | | |
| | highest input codes when | | | | | |
| | DAC_OUT reaches final | | | | | |
| | value ±4LSB | | | | | |
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
| THD⁽⁴⁾ | Total Harmonic Distortion | - | - | - | dB | CLOAD ≤ 50 pF, |
| | Buffer ON | | | | | RLOAD ≥ 5 kΩ |
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
| Update | Max frequency for a correct | - | - | 1 | MS/s | CLOAD ≤ 50 pF, |
| rate⁽²⁾ | DAC_OUT change when | | | | | RLOAD ≥ 5 kΩ |
| | small variation in the input | | | | | |
| | code (from code i to i+1LSB) | | | | | |
+--------------+----------------------------------+-----+-----+------+------+--------------------------------------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #171 ===
Table 82. DAC characteristics (continued)
+------------+------------------------------+-----+-----+-----+------+---------------------------------------+
| Symbol | Parameter | Min | Typ | Max | Unit | Comments |
+============+==============================+=====+=====+=====+======+=======================================+
| tWAKEUP⁽⁴⁾ | Wakeup time from off state | - | 6.5 | 10 | µs | CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ |
| | (Setting the ENx bit in the | | | | | input code between lowest and highest |
| | DAC Control register) | | | | | possible ones. |
+------------+------------------------------+-----+-----+-----+------+---------------------------------------+
| PSRR+ ⁽²⁾ | Power supply rejection ratio | - | –67 | –40 | dB | No RLOAD, CLOAD = 50 pF |
| | (to VDDA) (static DC | | | | | |
| | measurement) | | | | | |
+------------+------------------------------+-----+-----+-----+------+---------------------------------------+
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization results.
Figure 45. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
6.3.29 Communications interfaces
I²C interface characteristics
The I²C interface meets the timings requirements of the I²C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
• Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
The I²C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0410 reference manual) and when the I2CCLK frequency is greater
than the minimum shown in the table below:
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #172 ===
Table 83. Minimum I2CCLK frequency in all I2C modes
+-----------+-----------+------------------------------------+-----+------+
| Symbol | Parameter | Condition | Min | Unit |
+-----------+-----------+----------------+-------------------+-----+------+
| f(I2CCLK) | I2CCLK | Standard-mode | - | 2 | MHz |
| | frequency +----------------+-------------------+-----+ |
| | | Fast-mode | Analog filter ON | 8 | |
| | | | DNF=0 | | |
| | | +-------------------+-----+ |
| | | | Analog filter OFF | 9 | |
| | | | DNF=1 | | |
| | +----------------+-------------------+-----+ |
| | | Fast-mode Plus | Analog filter ON | 16 | |
| | | | DNF=0 | | |
| | | +-------------------+-----+ |
| | | | Analog filter OFF | 16 | |
| | | | DNF=1 | | |
+-----------+-----------+----------------+-------------------+-----+------+
The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but is still present.
• The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
Tr(SDA/SCL)=0.8473xRpxCload
Rp(min)= (VDD-VOL(max))/IOL(max)
Where Rp is the I2C lines pull-up. Refer to Section 6.3.20: I/O port characteristics for the
I2C I/Os characteristics.
All I²C SDA and SCL I/Os embed an analog filter. Refer to Table 84 for the analog filter
characteristics:
Table 84. I2C analog filter characteristics⁽¹⁾
+--------+-------------------------------------+-------+-------+------+
| Symbol | Parameter | Min | Max | Unit |
+========+=====================================+=======+=======+======+
| tAF | Maximum pulse width of spikes that | 50⁽²⁾ | 70⁽³⁾ | ns |
| | are suppressed by the analog filter | | | |
+--------+-------------------------------------+-------+-------+------+
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #173 ===
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 85 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 85. SPI dynamic characteristics⁽¹⁾
+-----------+-----------------------+-----------------------------+-----------+-------+-----------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+=======================+=============================+===========+=======+===========+======+
| fSCK | SPI clock frequency | Master mode | - | - | 54⁽²⁾ | MHz |
| 1/tc(SCK) | | SPI1,4,5,6 | | | | |
| | | 2.7≤VDD≤3.6 | | | | |
| | +-----------------------------+ | +-----------+ |
| | | Master mode | | | 27 | |
| | | SPI1,4,5,6 | | | | |
| | | 1.71≤VDD≤3.6 | | | | |
| | +-----------------------------+ | +-----------+ |
| | | Master transmitter mode | | | 54 | |
| | | SPI1,4,5,6 | | | | |
| | | 1.71≤VDD≤3.6 | | | | |
| | +-----------------------------+ | +-----------+ |
| | | Slave receiver mode | | | 54 | |
| | | SPI1,4,5,6 | | | | |
| | | 1.71≤VDD≤3.6 | | | | |
| | +-----------------------------+ | +-----------+ |
| | | Slave mode transmitter/full | | | 50⁽³⁾ | |
| | | duplex | | | | |
| | | SPI1,4,5,6 | | | | |
| | | 2.7≤VDD≤3.6 | | | | |
| | +-----------------------------+ | +-----------+ |
| | | Slave mode transmitter/full | | | 37⁽³⁾ | |
| | | duplex | | | | |
| | | SPI1,4,5,6 | | | | |
| | | 1.71≤VDD≤3.6 | | | | |
| | +-----------------------------+ | +-----------+ |
| | | Master & Slave mode | | | 27 | |
| | | SPI2,3 | | | | |
| | | 1.71≤VDD≤3.6 | | | | |
+-----------+-----------------------+-----------------------------+-----------+-------+-----------+------+
| tsu(NSS) | NSS setup time | Slave mode, SPI presc = 2 | 4*TPLCK | - | - | ns |
+-----------+-----------------------+-----------------------------+-----------+-------+-----------+ |
| th(NSS) | NSS hold time | Slave mode, SPI presc = 2 | 2*TPLCK | - | - | |
+-----------+-----------------------+-----------------------------+-----------+-------+-----------+ |
| tw(SCKH) | SCK high and low time | Master mode | TPLCK - 2 | ᵀPLCK | TPLCK + 2 | |
| tw(SCKL) | | | | | | |
+-----------+-----------------------+-----------------------------+-----------+-------+-----------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #174 ===
Table 85. SPI dynamic characteristics⁽¹⁾ (continued)
+----------+--------------------------+--------------------------+-------+-----+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+==========+==========================+==========================+=======+=====+======+======+
| tsu(MI) | Data input setup time | Master mode | 5 | - | - | ns |
| | | | 10⁽⁴⁾ | | | |
+----------+ +--------------------------+-------+-----+------+ |
| tsu(SI) | | Slave mode | 4.5 | - | - | |
+----------+--------------------------+--------------------------+-------+-----+------+ |
| th(MI) | Data input hold time | Master mode | 2 | - | - | |
| | | | 0⁽⁴⁾ | | | |
+----------+ +--------------------------+-------+-----+------+ |
| th(SI) | | Slave mode | 2 | - | - | |
+----------+--------------------------+--------------------------+-------+-----+------+ |
| ta(SO) | Data output access time | Slave mode | 7 | - | 21 | |
+----------+--------------------------+--------------------------+-------+-----+------+ |
| tdis(SO) | Data output disable time | Slave mode | 5 | - | 12 | |
+----------+--------------------------+--------------------------+-------+-----+------+ |
| tv(SO) | Data output valid time | Slave mode 2.7≤VDD≤3.6V | - | 6.5 | 10 | |
| | +--------------------------+-------+-----+------+ |
| | | Slave mode 1.71≤VDD≤3.6V | - | 6.5 | 13.5 | |
+----------+ +--------------------------+-------+-----+------+ |
| tv(MO) | | Master mode | - | 2 | 6 | |
+----------+--------------------------+--------------------------+-------+-----+------+ |
| th(SO) | Data output hold time | Slave mode | 4.5 | - | - | |
| | | 1.71≤VDD≤3.6V | | | | |
+----------+ +--------------------------+-------+-----+------+ |
| th(MO) | | Master mode | 0 | - | - | |
+----------+--------------------------+--------------------------+-------+-----+------+------+
1. Guaranteed by characterization results.
2. Excepting SPI1 with SCK IO pin mapped on PA5. In this configuration, Maximum achievable frequency is 40MHz.
3. Maximum Frequency of Slave Transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK
level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having
Tsu(MI)=0 while signal Duty(SCK)=50%.
4. Only for SPI6.
Figure 46. SPI timing diagram - slave mode and CPHA = 0
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #175 ===
Figure 47. SPI timing diagram - slave mode and CPHA = 1⁽¹⁾
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 48. SPI timing diagram - master mode⁽¹⁾
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #176 ===
I²S interface characteristics
Unless otherwise specified, the parameters given in Table 86 for the I²S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Table 86. I²S dynamic characteristics⁽¹⁾
+------------+--------------------------------+----------------------------------------+--------+-----------+------+
| Symbol | Parameter | Conditions | Min | Max | Unit |
+============+================================+========================================+========+===========+======+
| fMCK | I2S Main clock output | - | 256x8K | 256xFs⁽²⁾ | MHz |
+------------+--------------------------------+----------------------------------------+--------+-----------+------+
| fCK | I2S clock frequency | Master data | - | 64xFs | MHz |
| | +----------------------------------------+--------+-----------+ |
| | | Slave data | - | 64xFs | |
+------------+--------------------------------+----------------------------------------+--------+-----------+------+
| DCK | I2S clock frequency duty cycle | Slave receiver | 30 | 70 | % |
+------------+--------------------------------+----------------------------------------+--------+-----------+------+
| tv(WS) | WS valid time | Master mode | - | 3 | ns |
+------------+--------------------------------+----------------------------------------+--------+-----------+ |
| th(WS) | WS hold time | Master mode | 0 | - | |
+------------+--------------------------------+----------------------------------------+--------+-----------+ |
| tsu(WS) | WS setup time | Slave mode | 5 | - | |
+------------+--------------------------------+----------------------------------------+--------+-----------+ |
| th(WS) | WS hold time | Slave mode | 2 | - | |
+------------+--------------------------------+----------------------------------------+--------+-----------+ |
| tsu(SD_MR) | Data input setup time | Master receiver | 2.5 | - | |
+------------+ +----------------------------------------+--------+-----------+ |
| tsu(SD_SR) | | Slave receiver | 2.5 | - | |
+------------+--------------------------------+----------------------------------------+--------+-----------+ |
| th(SD_MR) | Data input hold time | Master receiver | 3.5 | - | |
+------------+ +----------------------------------------+--------+-----------+ |
| th(SD_SR) | | Slave receiver | 2 | - | |
+------------+--------------------------------+----------------------------------------+--------+-----------+ |
| tv(SD_ST) | Data output valid time | Slave transmitter (after enable edge) | - | 12 | |
+------------+ +----------------------------------------+--------+-----------+ |
| tv(SD_MT) | | Master transmitter (after enable edge) | - | 3 | |
+------------+--------------------------------+----------------------------------------+--------+-----------+ |
| th(SD_ST) | Data output hold time | Slave transmitter (after enable edge) | 5 | - | |
+------------+ +----------------------------------------+--------+-----------+ |
| th(SD_MT) | | Master transmitter (after enable edge) | 0 | - | |
+------------+--------------------------------+----------------------------------------+--------+-----------+------+
1. Guaranteed by characterization results.
2. The maximum value of 256xFs is 49.152 MHz (APB1 maximum frequency).
Note: Refer to RM0410 reference manual I2S section for more details about the sampling
frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The
values of these parameters might be slightly impacted by the source clock precision. DCK
depends mainly on the value of ODD bit. The digital contribution leads to a minimum value
of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS
maximum value is supported for each mode/condition.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #177 ===
Figure 49. I²S slave timing diagram (Philips protocol)⁽¹⁾
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 50. I²S master timing diagram (Philips protocol)⁽¹⁾
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #178 ===
JATG/SWD characteristics
Unless otherwise specified, the parameters given in Table 87 for JTAG/SWD are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 87. Dynamics characteristics: JTAG characteristics
+-----------+-----------------------+-----------------+-----------+-------+-----------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+=======================+=================+===========+=======+===========+======+
| Fpp | TCK clock frequency | 2.7V <VDD< 3.6V | - | - | 40 | MHz |
+-----------+ +-----------------+-----------+-------+-----------+ |
| 1/tc(TCK) | | 1.71 <VDD< 3.6V | - | - | 35 | |
+-----------+-----------------------+-----------------+-----------+-------+-----------+------+
| tw(TCKH) | SCK high and low time | - | TPCLK − 1 | TPCLK | TPCLK + 1 | ns |
+-----------+ | | | | | |
| tw(TCKL) | | | | | | |
+-----------+-----------------------+-----------------+-----------+-------+-----------+ |
| tsu(TMS) | TMS input setup time | - | 3 | - | - | |
+-----------+-----------------------+-----------------+-----------+-------+-----------+ |
| th(TMS) | TMS input hold time | - | 0 | - | - | |
+-----------+-----------------------+-----------------+-----------+-------+-----------+ |
| tsu(TDI) | TDI input setup time | - | 0.5 | - | - | |
+-----------+-----------------------+-----------------+-----------+-------+-----------+ |
| th(TDI) | TDI input hold time | - | 2 | - | - | |
+-----------+-----------------------+-----------------+-----------+-------+-----------+ |
| tov (TDO) | TDO output valid time | 2.7V <VDD< 3.6V | - | 9 | 11 | |
| | +-----------------+-----------+-------+-----------+ |
| | | 1.71 <VDD< 3.6V | - | 9 | 13 | |
+-----------+-----------------------+-----------------+-----------+-------+-----------+ |
| toh(TDO) | TDO output hold time | - | 7.5 | - | - | |
+-----------+-----------------------+-----------------+-----------+-------+-----------+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #179 ===
Table 88. Dynamics characteristics: SWD characteristics
+-------------+-------------------------+-----------------+-----------+-------+-----------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=============+=========================+=================+===========+=======+===========+======+
| Fpp | SWCLK clock frequency | 2.7V <VDD< 3.6V | - | - | 80 | MHz |
+-------------+ +-----------------+-----------+-------+-----------+ |
| 1/tc(SWCLK) | | 1.71 <VDD< 3.6V | - | - | 50 | |
+-------------+-------------------------+-----------------+-----------+-------+-----------+------+
| tw(SWCLKH) | SCK high and low time | - | TPCLK − 1 | TPCLK | TPCLK + 1 | ns |
+-------------+ | | | | | |
| tw(SWCLKL) | | | | | | |
+-------------+-------------------------+-----------------+-----------+-------+-----------+ |
| tsu(SWDIO) | SWDIO input setup time | - | 3.5 | - | - | |
+-------------+-------------------------+-----------------+-----------+-------+-----------+ |
| th(SWDIO) | SWDIO input hold time | - | 0 | - | - | |
+-------------+-------------------------+-----------------+-----------+-------+-----------+ |
| tov (SWDIO) | SWDIO output valid time | 2.7V <VDD< 3.6V | - | 11 | 12 | |
| | +-----------------+-----------+-------+-----------+ |
| | | 1.71 <VDD< 3.6V | - | 11 | 16.5 | |
+-------------+-------------------------+-----------------+-----------+-------+-----------+ |
| toh(SWDIO) | SWDIO output hold time | - | 9 | - | - | |
+-------------+-------------------------+-----------------+-----------+-------+-----------+------+
JTAG/SWD timing diagrams
Figure 51. JTAG timing diagram
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #180 ===
Figure 52. SWD timing diagram
SAI characteristics:
Unless otherwise specified, the parameters given in Table 89 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 89. SAI characteristics⁽¹⁾
+--------------+------------------------+----------------------+----------+-----------+------+
| Symbol | Parameter | Conditions | Min | Max | Unit |
+==============+========================+======================+==========+===========+======+
| fMCK | SAI Main clock output | - | 256 x 8K | 256xFs | MHz |
+--------------+------------------------+----------------------+----------+-----------+------+
| FCK | SAI clock frequency⁽²⁾ | Master data: 32 bits | - | 128xFs⁽³⁾ | MHz |
| | +----------------------+----------+-----------+ |
| | | Slave data: 32 bits | - | 128xFs | |
+--------------+------------------------+----------------------+----------+-----------+------+
| tv(FS) | FS valid time | Master mode | - | 15 | ns |
| | | 2.7≤VDD≤3.6V | | | |
| | +----------------------+----------+-----------+ |
| | | Master mode | - | 20 | |
| | | 1.71≤VDD≤3.6V | | | |
+--------------+------------------------+----------------------+----------+-----------+ |
| tsu(FS) | FS setup time | Slave mode | 7 | - | |
+--------------+------------------------+----------------------+----------+-----------+ |
| th(FS) | FS hold time | Master mode | 1 | - | |
| | +----------------------+----------+-----------+ |
| | | Slave mode | 1 | - | |
+--------------+------------------------+----------------------+----------+-----------+ |
| tsu(SD_A_MR) | Data input setup time | Master receiver | 3 | - | |
+--------------+ +----------------------+----------+-----------+ |
| tsu(SD_B_SR) | | Slave receiver | 3.5 | - | |
+--------------+------------------------+----------------------+----------+-----------+ |
| th(SD_A_MR) | Data input hold time | Master receiver | 5 | - | |
+--------------+ +----------------------+----------+-----------+ |
| th(SD_B_SR) | | Slave receiver | 1 | - | |
+--------------+------------------------+----------------------+----------+-----------+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #181 ===
Table 89. SAI characteristics⁽¹⁾ (continued)
+-------------+------------------------+----------------------------------------+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Max | Unit |
+=============+========================+========================================+=====+=====+======+
| tv(SD_B_ST) | Data output valid time | Slave transmitter (after enable edge) | - | 12 | ns |
| | | 2.7≤VDD≤3.6V | | | |
| | +----------------------------------------+-----+-----+ |
| | | Slave transmitter (after enable edge) | - | 20 | |
| | | 1.71≤VDD≤3.6V | | | |
+-------------+------------------------+----------------------------------------+-----+-----+ |
| th(SD_B_MT) | Data output hold time | Slave transmitter (after enable edge) | 5 | - | |
+-------------+------------------------+----------------------------------------+-----+-----+ |
| tv(SD_MT)_A | Data output valid time | Master transmitter (after enable edge) | - | 15 | |
| | | 2.7≤VDD≤3.6V | | | |
| | +----------------------------------------+-----+-----+ |
| | | Master transmitter (after enable edge) | - | 20 | |
| | | 1.71≤VDD≤3.6V | | | |
+-------------+------------------------+----------------------------------------+-----+-----+ |
| th(SD_A_MT) | Data output hold time | Master transmitter (after enable edge) | 5 | - | |
+-------------+------------------------+----------------------------------------+-----+-----+------+
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192kHz.
Figure 53. SAI master timing waveforms
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #182 ===
Figure 54. SAI slave timing waveforms
USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Table 90. USB OTG full speed startup time
+-------------+---------------------------------------------+-----+------+
| Symbol | Parameter | Max | Unit |
+=============+=============================================+=====+======+
| tSTARTUP⁽¹⁾ | USB OTG full speed transceiver startup time | 1 | µs |
+-------------+---------------------------------------------+-----+------+
1. Guaranteed by design.
Table 91. USB OTG full speed DC electrical characteristics
+------------------+--------------------------------+--------------------------+--------+------+------+------+
| Symbol | Parameter | Conditions | Min. | Typ. | Max. | Unit |
| | | | (1) | | (1) | |
+--------+---------+--------------------------------+--------------------------+--------+------+------+------+
| Input | VDDUSB | USB OTG full speed | - | 3.0⁽²⁾ | - | 3.6 | V |
| levels | | transceiver operating | | | | | |
| | | voltage | | | | | |
| +---------+--------------------------------+--------------------------+--------+------+------+------+
| | VDI⁽³⁾ | Differential input sensitivity | I(USB_FS_DP/DM, | 0.2 | - | - | V |
| | | | USB_HS_DP/DM) | | | | |
| +---------+--------------------------------+--------------------------+--------+------+------+ |
| | VCM ⁽³⁾ | Differential common mode | Includes VDI range | 0.8 | - | 2.5 | |
| | | range | | | | | |
| +---------+--------------------------------+--------------------------+--------+------+------+ |
| | VSE⁽³⁾ | Single ended receiver | - | 1.3 | - | 2.0 | |
| | | threshold | | | | | |
+--------+---------+--------------------------------+--------------------------+--------+------+------+------+
| Output | VOL | Static output level low | RL of 1.5 kΩ to 3.6 V⁽⁴⁾ | - | - | 0.3 | V |
| levels +---------+--------------------------------+--------------------------+--------+------+------+ |
| | VOH | Static output level high | RL of 15 kΩ to VSS⁽⁴⁾ | 2.8 | - | 3.6 | |
+--------+---------+--------------------------------+--------------------------+--------+------+------+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #183 ===
Table 91. USB OTG full speed DC electrical characteristics (continued)
+--------+------------------------+------------+------+------+------+------+
| Symbol | Parameter | Conditions | Min. | Typ. | Max. | Unit |
| | | | (1) | | (1) | |
+========+========================+============+======+======+======+======+
| RPD | PA11, PA12, PB14, PB15 | VIN = VDD | 17 | 21 | 24 | kΩ |
| | (USB_FS_DP/DM, | | | | | |
| | USB_HS_DP/DM) | | | | | |
| +------------------------+ +------+------+------+ |
| | PA9, PB13 | | 2.4 | 5.2 | 8 | |
| | (OTG_FS_VBUS, | | | | | |
| | OTG_HS_VBUS) | | | | | |
+--------+------------------------+------------+------+------+------+ |
| RPU | PA12, PB15 (USB_FS_DP, | VIN = VSS | 1.5 | 1.8 | 2.1 | |
| | USB_HS_DP) | | | | | |
| +------------------------+------------+------+------+------+ |
| | PA9, PB13 | VIN = VSS | 0.55 | 0.95 | 1.35 | |
| | (OTG_FS_VBUS, | | | | | |
| | OTG_HS_VBUS) | | | | | |
+--------+------------------------+------------+------+------+------+------+
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDDUSB voltage range.
3. Guaranteed by design.
4. RL is the load connected on the USB OTG full speed drivers.
Note: When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.
Figure 55. USB OTG full speed timings: definition of data signal rise and fall time
Table 92. USB OTG full speed electrical characteristics⁽¹⁾
+-------------------------------------------------------------------------------+
| Driver characteristics |
+--------+---------------------------------+-----------------+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Max | Unit |
+--------+---------------------------------+-----------------+-----+-----+------+
| tr | Rise time⁽²⁾ | CL = 50 pF | 4 | 20 | ns |
+--------+---------------------------------+-----------------+-----+-----+------+
| tf | Fall time⁽²⁾ | CL = 50 pF | 4 | 20 | ns |
+--------+---------------------------------+-----------------+-----+-----+------+
| trfm | Rise/ fall time matching | tr/tf | 90 | 110 | % |
+--------+---------------------------------+-----------------+-----+-----+------+
| VCRS | Output signal crossover voltage | - | 1.3 | 2.0 | V |
+--------+---------------------------------+-----------------+-----+-----+------+
| ZDRV | Output driver impedance⁽³⁾ | Driving high or | 28 | 44 | Ω |
| | | low | | | |
+--------+---------------------------------+-----------------+-----+-----+------+
1. Guaranteed by design.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #184 ===
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
USB high speed (HS) characteristics
Unless otherwise specified, the parameters given in Table 95 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 94
and VDD supply voltage conditions summarized in Table 93, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
• Capacitive load C = 20 pF, unless otherwise specified
• Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Table 93. USB HS DC electrical characteristics
+-------------------+------------------------------+---------+---------+------+
| Symbol | Parameter | Min.⁽¹⁾ | Max.⁽¹⁾ | Unit |
+-------------+-----+------------------------------+---------+---------+------+
| Input level | VDD | USB OTG HS operating voltage | 1.7 | 3.6 | V |
+-------------+-----+------------------------------+---------+---------+------+
1. All the voltages are measured from the local ground potential.
Table 94. USB HS clock timing parameters⁽¹⁾
+-------------+-------------------------------------------------+--------+-----+--------+------+
| Symbol | Parameter | Min | Typ | Max | Unit |
+=============+=================================================+========+=====+========+======+
| - | fHCLK value to guarantee proper operation of | 30 | - | - | MHz |
| | USB HS interface | | | | |
+-------------+----------------------------------+--------------+--------+-----+--------+------+
| FSTART_8BIT | Frequency (first transition) | 8-bit ±10% | 54 | 60 | 66 | MHz |
+-------------+----------------------------------+--------------+--------+-----+--------+------+
| FSTEADY | Frequency (steady state) ±500 ppm | 59.97 | 60 | 60.03 | MHz |
+-------------+----------------------------------+--------------+--------+-----+--------+------+
| DSTART_8BIT | Duty cycle (first transition) | 8-bit ±10% | 40 | 50 | 60 | % |
+-------------+----------------------------------+--------------+--------+-----+--------+------+
| DSTEADY | Duty cycle (steady state) ±500 ppm | 49.975 | 50 | 50.025 | % |
+-------------+-------------------------------------------------+--------+-----+--------+------+
| tSTEADY | Time to reach the steady state frequency and | - | - | 1.4 | ms |
| | duty cycle after the first transition | | | | |
+-------------+----------------------------------+--------------+--------+-----+--------+------+
| tSTART_DEV | Clock startup time after the | Peripheral | - | - | 5.6 | ms |
+-------------+ de-assertion of SuspendM +--------------+--------+-----+--------+ |
| tSTART_HOST | | Host | - | - | - | |
+-------------+----------------------------------+--------------+--------+-----+--------+------+
| tPREP | PHY preparation time after the first transition | - | - | - | µs |
| | of the input clock | | | | |
+-------------+-------------------------------------------------+--------+-----+--------+------+
1. Guaranteed by design.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #185 ===
Figure 56. ULPI timing diagram
Table 95. Dynamic characteristics: USB ULPI⁽¹⁾
+---------+--------------------------------------------+-----------------------+------+------+------+------+
| Symbol | Parameter | Conditions | Min. | Typ. | Max. | Unit |
+=========+============================================+=======================+======+======+======+======+
| tSC | Control in (ULPI_DIR, ULPI_NXT) setup time | - | 2 | - | - | ns |
+---------+--------------------------------------------+-----------------------+------+------+------+ |
| tHC | Control in (ULPI_DIR, ULPI_NXT) hold time | - | 1.5 | - | - | |
+---------+--------------------------------------------+-----------------------+------+------+------+ |
| tSD | Data in setup time | - | 2 | - | - | |
+---------+--------------------------------------------+-----------------------+------+------+------+ |
| tHD | Data in hold time | - | 1 | - | - | |
+---------+--------------------------------------------+-----------------------+------+------+------+ |
| tDC/tDD | Data/control output delay | 2.7 V < VDD < 3.6 V, | - | 6.5 | 8 | |
| | | CL = 20 pF | | | | |
| | +-----------------------+------+------+------+ |
| | | - | - | 6.5 | 11 | |
| | +-----------------------+------+ | | |
| | | 1.7 V < V DD < 3.6 V, | - | | | |
| | | CL = 15 pF | | | | |
+---------+--------------------------------------------+-----------------------+------+------+------+------+
1. Guaranteed by characterization results.
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 96, Table 97 and Table 98 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Table 96 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 57 shows the corresponding timing diagram.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #186 ===
Figure 57. Ethernet SMI timing diagram
Table 96. Dynamics characteristics: Ethernet MAC signals for SMI⁽¹⁾
+-----------+--------------------------+-----------+-------------+-----------+------+
| Symbol | Parameter | Min | Typ | Max | Unit |
+===========+==========================+===========+=============+===========+======+
| tMDC | MDC cycle time(2.38 MHz) | 400 | 400 | 403 | ns |
+-----------+--------------------------+-----------+-------------+-----------+ |
| Td(MDIO) | Write data valid time | THCLK + 1 | THCLK + 1.5 | THCLK + 3 | |
+-----------+--------------------------+-----------+-------------+-----------+ |
| tsu(MDIO) | Read data setup time | 12.5 | - | - | |
+-----------+--------------------------+-----------+-------------+-----------+ |
| th(MDIO) | Read data hold time | 0 | - | - | |
+-----------+--------------------------+-----------+-------------+-----------+------+
1. Guaranteed by characterization results.
Table 97 gives the list of Ethernet MAC signals for the RMII and Figure 58 shows the
corresponding timing diagram.
Figure 58. Ethernet RMII timing diagram
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #187 ===
Table 97. Dynamics characteristics: Ethernet MAC signals for RMII⁽¹⁾
+----------+----------------------------------+-----+-----+------+------+
| Symbol | Parameter | Min | Typ | Max | Unit |
+==========+==================================+=====+=====+======+======+
| tsu(RXD) | Receive data setup time | 1 | - | - | ns |
+----------+----------------------------------+-----+-----+------+ |
| tih(RXD) | Receive data hold time | 2 | - | - | |
+----------+----------------------------------+-----+-----+------+ |
| tsu(CRS) | Carrier sense setup time | 2 | - | - | |
+----------+----------------------------------+-----+-----+------+ |
| tih(CRS) | Carrier sense hold time | 2 | - | - | |
+----------+----------------------------------+-----+-----+------+ |
| td(TXEN) | Transmit enable valid delay time | 7.5 | 8 | 12 | |
+----------+----------------------------------+-----+-----+------+ |
| td(TXD) | Transmit data valid delay time | 7 | 7.5 | 12.5 | |
+----------+----------------------------------+-----+-----+------+------+
1. Guaranteed by characterization results.
Table 98 gives the list of Ethernet MAC signals for MII and Figure 58 shows the
corresponding timing diagram.
Figure 59. Ethernet MII timing diagram
Table 98. Dynamics characteristics: Ethernet MAC signals for MII⁽¹⁾
+----------+----------------------------------+-----+-----+-----+------+
| Symbol | Parameter | Min | Typ | Max | Unit |
+==========+==================================+=====+=====+=====+======+
| tsu(RXD) | Receive data setup time | 1 | - | - | ns |
+----------+----------------------------------+-----+-----+-----+ |
| tih(RXD) | Receive data hold time | 2.5 | - | - | |
+----------+----------------------------------+-----+-----+-----+ |
| tsu(DV) | Data valid setup time | 1.5 | - | - | |
+----------+----------------------------------+-----+-----+-----+ |
| tih(DV) | Data valid hold time | 0.5 | - | - | |
+----------+----------------------------------+-----+-----+-----+ |
| tsu(ER) | Error setup time | 2.5 | - | - | |
+----------+----------------------------------+-----+-----+-----+ |
| tih(ER) | Error hold time | 0.5 | - | - | |
+----------+----------------------------------+-----+-----+-----+ |
| td(TXEN) | Transmit enable valid delay time | 8 | 10 | 13 | |
+----------+----------------------------------+-----+-----+-----+ |
| td(TXD) | Transmit data valid delay time | 7.5 | 9 | 13 | |
+----------+----------------------------------+-----+-----+-----+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #188 ===
1. Guaranteed by characterization results.
Table 99. MDIO Slave timing parameters
+-----------+------------------------------------------------+-----+-----+-----+------+
| Symbol | Parameter | Min | Typ | Max | Unit |
+===========+================================================+=====+=====+=====+======+
| FsDC | Management Data clock | - | - | 40 | MHz |
+-----------+------------------------------------------------+-----+-----+-----+------+
| td(MDIO) | Management Data input/output output valid time | 7 | 8 | 20 | ns |
+-----------+------------------------------------------------+-----+-----+-----+ |
| tsu(MDIO) | Management Data input/output setup time | 4 | - | - | |
+-----------+------------------------------------------------+-----+-----+-----+ |
| th(MDIO) | Management Data input/output hold time | 1 | - | - | |
+-----------+------------------------------------------------+-----+-----+-----+------+
The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at
least 1.5 times the MDC frequency: FPCLK2 ≥ 1.5 * FMDC
Figure 60. MDIO Slave timing diagram
CAN (controller area network) interface
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
6.3.30 FMC characteristics
Unless otherwise specified, the parameters given in Table 100 to Table 113 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5VDD
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #189 ===
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 61 through Figure 64 represent asynchronous waveforms and Table 100 through
Table 107 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capcitive load CL = 30 pF
In all timing tables, the THCLK is the HCLK clock period
Figure 61. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #190 ===
Table 100. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings⁽¹⁾⁽²⁾
+---------------+---------------------------------------+------------+------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===============+=======================================+============+============+======+
| tw(NE) | FMC_NE low time | 2THCLK − 1 | 2 THCLK +1 | ns |
+---------------+---------------------------------------+------------+------------+ |
| tv(NOE_NE) | FMC_NEx low to FMC_NOE low | 0 | 0.5 | |
+---------------+---------------------------------------+------------+------------+ |
| tw(NOE) | FMC_NOE low time | 2THCLK − 1 | 2THCLK + 1 | |
+---------------+---------------------------------------+------------+------------+ |
| th(NE_NOE) | FMC_NOE high to FMC_NE high hold time | 0 | - | |
+---------------+---------------------------------------+------------+------------+ |
| tv(A_NE) | FMC_NEx low to FMC_A valid | - | 0.5 | |
+---------------+---------------------------------------+------------+------------+ |
| th(A_NOE) | Address hold time after FMC_NOE high | 0 | - | |
+---------------+---------------------------------------+------------+------------+ |
| tv(BL_NE) | FMC_NEx low to FMC_BL valid | - | 0.5 | |
+---------------+---------------------------------------+------------+------------+ |
| th(BL_NOE) | FMC_BL hold time after FMC_NOE high | 0 | - | |
+---------------+---------------------------------------+------------+------------+ |
| tsu(Data_NE) | Data to FMC_NEx high setup time | THCLK − 1 | - | |
+---------------+---------------------------------------+------------+------------+ |
| tsu(Data_NOE) | Data to FMC_NOEx high setup time | THCLK − 1 | - | |
+---------------+---------------------------------------+------------+------------+ |
| th(Data_NOE) | Data hold time after FMC_NOE high | 0 | - | |
+---------------+---------------------------------------+------------+------------+ |
| th(Data_NE) | Data hold time after FMC_NEx high | 0 | - | |
+---------------+---------------------------------------+------------+------------+ |
| tv(NADV_NE) | FMC_NEx low to FMC_NADV low | - | 0 | |
+---------------+---------------------------------------+------------+------------+ |
| tw(NADV) | FMC_NADV low time | - | THCLK + 1 | |
+---------------+---------------------------------------+------------+------------+------+
1. CL = 30 pF.
2. Guaranteed by characterization results.
Table 101. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT
timings⁽¹⁾
+---------------+-------------------------------------------+-------------+-----------+------+
| Symbol | Parameter | Min | Max | Unit |
+===============+===========================================+=============+===========+======+
| tw(NE) | FMC_NE low time | 7THCLK +1 | 7THCLK +1 | ns |
+---------------+-------------------------------------------+-------------+-----------+ |
| tw(NOE) | FMC_NWE low time | 5THCLK −1 | 5THCLK +1 | |
+---------------+-------------------------------------------+-------------+-----------+ |
| tw(NWAIT) | FMC_NWAIT low time | THCLK −0.5 | - | |
+---------------+-------------------------------------------+-------------+-----------+ |
| tsu(NWAIT_NE) | FMC_NWAIT valid before FMC_NEx high | 5THCLK +1.5 | - | |
+---------------+-------------------------------------------+-------------+-----------+ |
| th(NE_NWAIT) | FMC_NEx hold time after FMC_NWAIT invalid | 4THCLK+1 | - | |
+---------------+-------------------------------------------+-------------+-----------+------+
1. Guaranteed by characterization results.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #191 ===
Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 102. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings⁽¹⁾
+--------------+---------------------------------------+-------------+-------------+------+
| Symbol | Parameter | Min | Max | Unit |
+==============+=======================================+=============+=============+======+
| tw(NE) | FMC_NE low time | 3THCLK − 1 | 3THCLK + 1 | ns |
+--------------+---------------------------------------+-------------+-------------+ |
| tv(NWE_NE) | FMC_NEx low to FMC_NWE low | THCLK − 1 | THCLK + 0.5 | |
+--------------+---------------------------------------+-------------+-------------+ |
| tw(NWE) | FMC_NWE low time | THCLK − 1.5 | THCLK + 0.5 | |
+--------------+---------------------------------------+-------------+-------------+ |
| th(NE_NWE) | FMC_NWE high to FMC_NE high hold time | THCLK | - | |
+--------------+---------------------------------------+-------------+-------------+ |
| tv(A_NE) | FMC_NEx low to FMC_A valid | - | 0 | |
+--------------+---------------------------------------+-------------+-------------+ |
| th(A_NWE) | Address hold time after FMC_NWE high | THCLK − 0.5 | - | |
+--------------+---------------------------------------+-------------+-------------+ |
| tv(BL_NE) | FMC_NEx low to FMC_BL valid | - | 0.5 | |
+--------------+---------------------------------------+-------------+-------------+ |
| th(BL_NWE) | FMC_BL hold time after FMC_NWE high | THCLK − 0.5 | - | |
+--------------+---------------------------------------+-------------+-------------+ |
| tv(Data_NE) | Data to FMC_NEx low to Data valid | - | THCLK + 2 | |
+--------------+---------------------------------------+-------------+-------------+ |
| th(Data_NWE) | Data hold time after FMC_NWE high | THCLK+0.5 | - | |
+--------------+---------------------------------------+-------------+-------------+ |
| tv(NADV_NE) | FMC_NEx low to FMC_NADV low | - | 0 | |
+--------------+---------------------------------------+-------------+-------------+ |
| tw(NADV) | FMC_NADV low time | - | THCLK + 1 | |
+--------------+---------------------------------------+-------------+-------------+------+
1. Guaranteed by characterization results.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #192 ===
Table 103. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT
timings⁽¹⁾
+---------------+-------------------------------------+--------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===============+=====================================+==============+==============+======+
| tw(NE) | FMC_NE low time | 8THCLK − 1 | 8THCLK + 1 | ns |
+---------------+-------------------------------------+--------------+--------------+ |
| tw(NWE) | FMC_NWE low time | 6THCLK − 1.5 | 6THCLK + 0.5 | |
+---------------+-------------------------------------+--------------+--------------+ |
| tsu(NWAIT_NE) | FMC_NWAIT valid before FMC_NEx high | 6THCLK − 1 | - | |
+---------------+-------------------------------------+--------------+--------------+ |
| th(NE_NWAIT) | FMC_NEx hold time after FMC_NWAIT | 4THCLK + 2 | - | |
| | invalid | | | |
+---------------+-------------------------------------+--------------+--------------+------+
1. Guaranteed by characterization results.
Figure 63. Asynchronous multiplexed PSRAM/NOR read waveforms
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #193 ===
Table 104. Asynchronous multiplexed PSRAM/NOR read timings⁽¹⁾
+---------------+---------------------------------------+-------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===============+=======================================+=============+==============+======+
| tw(NE) | FMC_NE low time | 3THCLK − 1 | 3THCLK + 1 | ns |
+---------------+---------------------------------------+-------------+--------------+ |
| tv(NOE_NE) | FMC_NEx low to FMC_NOE low | 2THCLK | 2THCLK + 0.5 | |
+---------------+---------------------------------------+-------------+--------------+ |
| ttw(NOE) | FMC_NOE low time | THCLK − 1 | THCLK + 1 | |
+---------------+---------------------------------------+-------------+--------------+ |
| th(NE_NOE) | FMC_NOE high to FMC_NE high hold time | 0 | - | |
+---------------+---------------------------------------+-------------+--------------+ |
| tv(A_NE) | FMC_NEx low to FMC_A valid | - | 0.5 | |
+---------------+---------------------------------------+-------------+--------------+ |
| tv(NADV_NE) | FMC_NEx low to FMC_NADV low | 0 | 0.5 | |
+---------------+---------------------------------------+-------------+--------------+ |
| tw(NADV) | FMC_NADV low time | THCLK − 0.5 | THCLK+1 | |
+---------------+---------------------------------------+-------------+--------------+ |
| th(AD_NADV) | FMC_AD(address) valid hold time after | THCLK + 0.5 | - | |
| | FMC_NADV high) | | | |
+---------------+---------------------------------------+-------------+--------------+ |
| th(A_NOE) | Address hold time after FMC_NOE high | THCLK − 0.5 | - | |
+---------------+---------------------------------------+-------------+--------------+ |
| th(BL_NOE) | FMC_BL time after FMC_NOE high | 0 | - | |
+---------------+---------------------------------------+-------------+--------------+ |
| tv(BL_NE) | FMC_NEx low to FMC_BL valid | - | 0.5 | |
+---------------+---------------------------------------+-------------+--------------+ |
| tsu(Data_NE) | Data to FMC_NEx high setup time | THCLK − 1 | - | |
+---------------+---------------------------------------+-------------+--------------+ |
| tsu(Data_NOE) | Data to FMC_NOE high setup time | THCLK − 1 | - | |
+---------------+---------------------------------------+-------------+--------------+ |
| th(Data_NE) | Data hold time after FMC_NEx high | 0 | - | |
+---------------+---------------------------------------+-------------+--------------+ |
| th(Data_NOE) | Data hold time after FMC_NOE high | 0 | - | |
+---------------+---------------------------------------+-------------+--------------+------+
1. Guaranteed by characterization results.
Table 105. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings⁽¹⁾
+---------------+-------------------------------------+--------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===============+=====================================+==============+==============+======+
| tw(NE) | FMC_NE low time | 8THCLK − 1 | 8THCLK + 1 | ns |
+---------------+-------------------------------------+--------------+--------------+ |
| tw(NOE) | FMC_NWE low time | 5THCLK − 1.5 | 5THCLK + 0.5 | |
+---------------+-------------------------------------+--------------+--------------+ |
| tsu(NWAIT_NE) | FMC_NWAIT valid before FMC_NEx high | 5THCLK + 1.5 | - | |
+---------------+-------------------------------------+--------------+--------------+ |
| th(NE_NWAIT) | FMC_NEx hold time after FMC_NWAIT | 4THCLK+ 1 | - | |
| | invalid | | | |
+---------------+-------------------------------------+--------------+--------------+------+
1. Guaranteed by characterization results.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #194 ===
Figure 64. Asynchronous multiplexed PSRAM/NOR write waveforms
Table 106. Asynchronous multiplexed PSRAM/NOR write timings⁽¹⁾
+---------------+---------------------------------------+--------------+-------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===============+=======================================+==============+=============+======+
| tw(NE) | FMC_NE low time | 4THCLK − 1 | 4THCLK + 1 | ns |
+---------------+---------------------------------------+--------------+-------------+ |
| tv(NWE_NE) | FMC_NEx low to FMC_NWE low | THCLK − 1 | THCLK + 0.5 | |
+---------------+---------------------------------------+--------------+-------------+ |
| tw(NWE) | FMC_NWE low time | 2THCLK − 0.5 | 2THCLK+ 0.5 | |
+---------------+---------------------------------------+--------------+-------------+ |
| th(NE_NWE) | FMC_NWE high to FMC_NE high hold time | THCLK − 0.5 | - | |
+---------------+---------------------------------------+--------------+-------------+ |
| tv(A_NE) | FMC_NEx low to FMC_A valid | - | 0 | |
+---------------+---------------------------------------+--------------+-------------+ |
| tv(NADV_NE) | FMC_NEx low to FMC_NADV low | 0 | 0.5 | |
+---------------+---------------------------------------+--------------+-------------+ |
| tw(NADV) | FMC_NADV low time | ᵀHCLK | THCLK+ 1 | |
+---------------+---------------------------------------+--------------+-------------+ |
| th(AD_NADV) | FMC_AD(adress) valid hold time after | THCLK − 0.5 | - | |
| | FMC_NADV high) | | | |
+---------------+---------------------------------------+--------------+-------------+ |
| th(A_NWE) | Address hold time after FMC_NWE high | THCLK + 0.5 | - | |
+---------------+---------------------------------------+--------------+-------------+ |
| th(BL_NWE) | FMC_BL hold time after FMC_NWE high | THCLK − 0.5 | - | |
+---------------+---------------------------------------+--------------+-------------+ |
| tv(BL_NE) | FMC_NEx low to FMC_BL valid | - | 0.5 | |
+---------------+---------------------------------------+--------------+-------------+ |
| tv(Data_NADV) | FMC_NADV high to Data valid | - | THCLK + 2 | |
+---------------+---------------------------------------+--------------+-------------+ |
| th(Data_NWE) | Data hold time after FMC_NWE high | THCLK + 0.5 | - | |
+---------------+---------------------------------------+--------------+-------------+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #195 ===
1. Guaranteed by characterization results.
Table 107. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings⁽¹⁾
+---------------+-------------------------------------+--------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===============+=====================================+==============+==============+======+
| tw(NE) | FMC_NE low time | 9THCLK – 1 | 9THCLK + 1 | ns |
+---------------+-------------------------------------+--------------+--------------+ |
| tw(NWE) | FMC_NWE low time | 7THCLK – 0.5 | 7THCLK + 0.5 | |
+---------------+-------------------------------------+--------------+--------------+ |
| tsu(NWAIT_NE) | FMC_NWAIT valid before FMC_NEx high | 6THCLK + 2 | - | |
+---------------+-------------------------------------+--------------+--------------+ |
| th(NE_NWAIT) | FMC_NEx hold time after FMC_NWAIT | 4THCLK – 1 | - | |
| | invalid | | | |
+---------------+-------------------------------------+--------------+--------------+------+
1. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 65 through Figure 68 represent synchronous waveforms and Table 108 through
Table 111 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable;
• MemoryType = FMC_MemoryType_CRAM;
• WriteBurst = FMC_WriteBurst_Enable;
• CLKDivision = 1;
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
• CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all the timing tables, the THCLK is the HCLK clock period.
– For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 100 MHz at CL=20 pF or 90 MHz at
CL=30 pF (on FMC_CLK).
– For 1.71 V≤ VDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK).
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #196 ===
Figure 65. Synchronous multiplexed NOR/PSRAM read timings
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #197 ===
Table 108. Synchronous multiplexed NOR/PSRAM read timings⁽¹⁾
+-----------------+----------------------------------------------+-------------+-----+------+
| Symbol | Parameter | Min | Max | Unit |
+=================+==============================================+=============+=====+======+
| tw(CLK) | FMC_CLK period | 2THCLK− 0.5 | - | ns |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKL-NExL) | FMC_CLK low to FMC_NEx low (x=0..2) | - | 2 | |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKH_NExH) | FMC_CLK high to FMC_NEx high (x= 0…2) | THCLK + 0.5 | - | |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKL-NADVL) | FMC_CLK low to FMC_NADV low | - | 1. | |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKL-NADVH) | FMC_CLK low to FMC_NADV high | 0 | - | |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKL-AV) | FMC_CLK low to FMC_Ax valid (x=16…25) | - | 2.5 | |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKH-AIV) | FMC_CLK high to FMC_Ax invalid (x=16…25) | ᵀHCLK | - | |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKL-NOEL) | FMC_CLK low to FMC_NOE low | - | 1.5 | |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKH-NOEH) | FMC_CLK high to FMC_NOE high | THCLK − 0.5 | - | |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKL-ADV) | FMC_CLK low to FMC_AD[15:0] valid | - | 3 | |
+-----------------+----------------------------------------------+-------------+-----+ |
| td(CLKL-ADIV) | FMC_CLK low to FMC_AD[15:0] invalid | 0 | - | |
+-----------------+----------------------------------------------+-------------+-----+ |
| tsu(ADV-CLKH) | FMC_A/D[15:0] valid data before FMC_CLK high | 2.5 | - | |
+-----------------+----------------------------------------------+-------------+-----+ |
| th(CLKH-ADV) | FMC_A/D[15:0] valid data after FMC_CLK high | 2.5 | - | |
+-----------------+----------------------------------------------+-------------+-----+ |
| tsu(NWAIT-CLKH) | FMC_NWAIT valid before FMC_CLK high | 3 | - | |
+-----------------+----------------------------------------------+-------------+-----+ |
| th(CLKH-NWAIT) | FMC_NWAIT valid after FMC_CLK high | 2.5 | - | |
+-----------------+----------------------------------------------+-------------+-----+------+
1. Guaranteed by characterization results.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #198 ===
Figure 66. Synchronous multiplexed PSRAM write timings
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #199 ===
Table 109. Synchronous multiplexed PSRAM write timings⁽¹⁾
+-----------------+--------------------------------------------+--------------+------+------+
| Symbol | Parameter | Min | Max | Unit |
+=================+============================================+==============+======+======+
| tw(CLK) | FMC_CLK period | 2THCLK − 0.5 | - | ns |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKL-NExL) | FMC_CLK low to FMC_NEx low (x=0..2) | - | 2 | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKH-NExH) | FMC_CLK high to FMC_NEx high (x= 0…2) | THCLK + 0.5 | - | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKL-NADVL) | FMC_CLK low to FMC_NADV low | - | 1 | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKL-NADVH) | FMC_CLK low to FMC_NADV high | 0 | - | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKL-AV) | FMC_CLK low to FMC_Ax valid (x=16…25) | - | 2 .5 | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKH-AIV) | FMC_CLK high to FMC_Ax invalid (x=16…25) | ᵀHCLK | - | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKL-NWEL) | FMC_CLK low to FMC_NWE low | - | 1.5 | |
+-----------------+--------------------------------------------+--------------+------+ |
| t(CLKH-NWEH) | FMC_CLK high to FMC_NWE high | THCLK + 0.5 | - | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKL-ADV) | FMC_CLK low to FMC_AD[15:0] valid | - | 3 | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKL-ADIV) | FMC_CLK low to FMC_AD[15:0] invalid | 0 | - | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKL-DATA) | FMC_A/D[15:0] valid data after FMC_CLK low | - | 3.5 | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKL-NBLL) | FMC_CLK low to FMC_NBL low | - | 2 | |
+-----------------+--------------------------------------------+--------------+------+ |
| td(CLKH-NBLH) | FMC_CLK high to FMC_NBL high | THCLK + 0.5 | - | |
+-----------------+--------------------------------------------+--------------+------+ |
| tsu(NWAIT-CLKH) | FMC_NWAIT valid before FMC_CLK high | 2 | - | |
+-----------------+--------------------------------------------+--------------+------+ |
| th(CLKH-NWAIT) | FMC_NWAIT valid after FMC_CLK high | 3.5 | - | |
+-----------------+--------------------------------------------+--------------+------+------+
1. Guaranteed by characterization results.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #200 ===
Figure 67. Synchronous non-multiplexed NOR/PSRAM read timings
Table 110. Synchronous non-multiplexed NOR/PSRAM read timings⁽¹⁾
+----------------+--------------------------------------------+--------------+-----+------+
| Symbol | Parameter | Min | Max | Unit |
+================+============================================+==============+=====+======+
| tw(CLK) | FMC_CLK period | 2THCLK − 0.5 | - | ns |
+----------------+--------------------------------------------+--------------+-----+ |
| t(CLKL-NExL) | FMC_CLK low to FMC_NEx low (x=0..2) | - | 2 | |
+----------------+--------------------------------------------+--------------+-----+ |
| td(CLKH-NExH) | FMC_CLK high to FMC_NEx high (x= 0…2) | THCLK + 0.5 | - | |
+----------------+--------------------------------------------+--------------+-----+ |
| td(CLKL-NADVL) | FMC_CLK low to FMC_NADV low | - | 0.5 | |
+----------------+--------------------------------------------+--------------+-----+ |
| td(CLKL-NADVH) | FMC_CLK low to FMC_NADV high | 0 | - | |
+----------------+--------------------------------------------+--------------+-----+ |
| td(CLKL-AV) | FMC_CLK low to FMC_Ax valid (x=16…25) | - | 2.5 | |
+----------------+--------------------------------------------+--------------+-----+ |
| td(CLKH-AIV) | FMC_CLK high to FMC_Ax invalid (x=16…25) | ᵀHCLK | - | |
+----------------+--------------------------------------------+--------------+-----+ |
| td(CLKL-NOEL) | FMC_CLK low to FMC_NOE low | - | 1.5 | |
+----------------+--------------------------------------------+--------------+-----+ |
| td(CLKH-NOEH) | FMC_CLK high to FMC_NOE high | THCLK + 0.5 | - | |
+----------------+--------------------------------------------+--------------+-----+ |
| tsu(DV-CLKH) | FMC_D[15:0] valid data before FMC_CLK high | 2.5 | - | |
+----------------+--------------------------------------------+--------------+-----+ |
| th(CLKH-DV) | FMC_D[15:0] valid data after FMC_CLK high | 2.5 | - | |
+----------------+--------------------------------------------+--------------+-----+ |
| t(NWAIT-CLKH) | FMC_NWAIT valid before FMC_CLK high | 3 | - | |
+----------------+--------------------------------------------+--------------+-----+ |
| th(CLKH-NWAIT) | FMC_NWAIT valid after FMC_CLK high | 2.5 | - | |
+----------------+--------------------------------------------+--------------+-----+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #201 ===
1. Guaranteed by characterization results.
Figure 68. Synchronous non-multiplexed PSRAM write timings
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #202 ===
Table 111. Synchronous non-multiplexed PSRAM write timings⁽¹⁾
+-----------------+------------------------------------------+--------------+-----+------+
| Symbol | Parameter | Min | Max | Unit |
+=================+==========================================+==============+=====+======+
| t(CLK) | FMC_CLK period | 2THCLK − 0.5 | - | ns |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKL-NExL) | FMC_CLK low to FMC_NEx low (x=0..2) | - | 2 | |
+-----------------+------------------------------------------+--------------+-----+ |
| t(CLKH-NExH) | FMC_CLK high to FMC_NEx high (x= 0…2) | THCLK + 0.5 | - | |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKL-NADVL) | FMC_CLK low to FMC_NADV low | - | 0.5 | |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKL-NADVH) | FMC_CLK low to FMC_NADV high | 0 | - | |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKL-AV) | FMC_CLK low to FMC_Ax valid (x=16…25) | - | 2.5 | |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKH-AIV) | FMC_CLK high to FMC_Ax invalid (x=16…25) | ᵀHCLK | - | |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKL-NWEL) | FMC_CLK low to FMC_NWE low | - | 1.5 | |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKH-NWEH) | FMC_CLK high to FMC_NWE high | THCLK + 1 | - | |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKL-Data) | FMC_D[15:0] valid data after FMC_CLK low | - | 3.5 | |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKL-NBLL) | FMC_CLK low to FMC_NBL low | - | 2 | |
+-----------------+------------------------------------------+--------------+-----+ |
| td(CLKH-NBLH) | FMC_CLK high to FMC_NBL high | THCLK + 1 | - | |
+-----------------+------------------------------------------+--------------+-----+ |
| tsu(NWAIT-CLKH) | FMC_NWAIT valid before FMC_CLK high | 2 | - | |
+-----------------+------------------------------------------+--------------+-----+ |
| th(CLKH-NWAIT) | FMC_NWAIT valid after FMC_CLK high | 3.5 | - | |
+-----------------+------------------------------------------+--------------+-----+------+
1. Guaranteed by characterization results.
NAND controller waveforms and timings
Figure 69 through Figure 72 represent synchronous waveforms, and Table 112 and
Table 113 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
• COM.FMC_SetupTime = 0x01;
• COM.FMC_WaitSetupTime = 0x03;
• COM.FMC_HoldSetupTime = 0x02;
• COM.FMC_HiZSetupTime = 0x01;
• ATT.FMC_SetupTime = 0x01;
• ATT.FMC_WaitSetupTime = 0x03;
• ATT.FMC_HoldSetupTime = 0x02;
• ATT.FMC_HiZSetupTime = 0x01;
• Bank = FMC_Bank_NAND;
• MemoryDataWidth = FMC_MemoryDataWidth_16b;
• ECC = FMC_ECC_Enable;
• ECCPageSize = FMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #203 ===
Figure 69. NAND controller waveforms for read access
Figure 70. NAND controller waveforms for write access
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #204 ===
Figure 71. NAND controller waveforms for common memory read access
Figure 72. NAND controller waveforms for common memory write access
Table 112. Switching characteristics for NAND Flash read cycles⁽¹⁾
+-------------+--------------------------------------------+--------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+=============+============================================+==============+==============+======+
| tw(N0E) | FMC_NOE low width | 4THCLK − 0.5 | 4THCLK + 0.5 | ns |
+-------------+--------------------------------------------+--------------+--------------+ |
| tsu(D-NOE) | FMC_D[15-0] valid data before FMC_NOE high | 11 | - | |
+-------------+--------------------------------------------+--------------+--------------+ |
| th(NOE-D) | FMC_D[15-0] valid data after FMC_NOE high | 0 | - | |
+-------------+--------------------------------------------+--------------+--------------+ |
| td(ALE-NOE) | FMC_ALE valid before FMC_NOE low | - | 3THCLK + 1 | |
+-------------+--------------------------------------------+--------------+--------------+ |
| th(NOE-ALE) | FMC_NWE high to FMC_ALE invalid | 4THCLK − 2 | - | |
+-------------+--------------------------------------------+--------------+--------------+------+
1. Guaranteed by characterization results.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #205 ===
Table 113. Switching characteristics for NAND Flash write cycles⁽¹⁾
+-------------+---------------------------------------+--------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+=============+=======================================+==============+==============+======+
| tw(NWE) | FMC_NWE low width | 4THCLK − 0.5 | 4THCLK + 0.5 | ns |
+-------------+---------------------------------------+--------------+--------------+ |
| tv(NWE-D) | FMC_NWE low to FMC_D[15-0] valid | 0 | - | |
+-------------+---------------------------------------+--------------+--------------+ |
| th(NWE-D) | FMC_NWE high to FMC_D[15-0] invalid | 2THCLK − 1 | - | |
+-------------+---------------------------------------+--------------+--------------+ |
| td(D-NWE) | FMC_D[15-0] valid before FMC_NWE high | 5THCLK − 1 | - | |
+-------------+---------------------------------------+--------------+--------------+ |
| td(ALE-NWE) | FMC_ALE valid before FMC_NWE low | - | 3THCLK + 1 | |
+-------------+---------------------------------------+--------------+--------------+ |
| th(NWE-ALE) | FMC_NWE high to FMC_ALE invalid | 2THCLK − 2 | - | |
+-------------+---------------------------------------+--------------+--------------+------+
1. Guaranteed by characterization results.
SDRAM waveforms and timings
• CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
– For 3.0 V≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 100 MHz at CL=20 pF (on
FMC_SDCLK).
– For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on FMC_SDCLK).
– For 1.71 V≤ VDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on
FMC_SDCLK).
Figure 73. SDRAM read access waveforms (CL = 1)
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #206 ===
Table 114. SDRAM read timings⁽¹⁾
+-------------------+------------------------+--------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===================+========================+==============+==============+======+
| tw(SDCLK) | FMC_SDCLK period | 2THCLK − 0.5 | 2THCLK + 0.5 | ns |
+-------------------+------------------------+--------------+--------------+ |
| tsu(SDCLKH _Data) | Data input setup time | 2.5 | - | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKH_Data) | Data input hold time | 0.5 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_Add) | Address valid time | - | 3.5 | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL- SDNE) | Chip select valid time | - | 1.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL_SDNE) | Chip select hold time | 0.5 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_SDNRAS) | SDNRAS valid time | - | 1 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL_SDNRAS) | SDNRAS hold time | 0.5 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_SDNCAS) | SDNCAS valid time | - | 0.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL_SDNCAS) | SDNCAS hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+------+
1. Guaranteed by characterization results.
Table 115. LPSDR SDRAM read timings⁽¹⁾
+-------------------+------------------------+--------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===================+========================+==============+==============+======+
| tW(SDCLK) | FMC_SDCLK period | 2THCLK − 0.5 | 2THCLK + 0.5 | ns |
+-------------------+------------------------+--------------+--------------+ |
| tsu(SDCLKH_Data) | Data input setup time | 1 | - | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKH_Data) | Data input hold time | 3.5 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_Add) | Address valid time | - | 2.5 | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_SDNE) | Chip select valid time | - | 2.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL_SDNE) | Chip select hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_SDNRAS | SDNRAS valid time | - | 0.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL_SDNRAS) | SDNRAS hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_SDNCAS) | SDNCAS valid time | - | 1.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL_SDNCAS) | SDNCAS hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+------+
1. Guaranteed by characterization results.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #207 ===
Figure 74. SDRAM write access waveforms
Table 116. SDRAM write timings⁽¹⁾
+-------------------+------------------------+--------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===================+========================+==============+==============+======+
| tw(SDCLK) | FMC_SDCLK period | 2THCLK − 0.5 | 2THCLK + 0.5 | ns |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL _Data) | Data output valid time | - | 3 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL _Data) | Data output hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_Add) | Address valid time | - | 3.5 | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_SDNWE) | SDNWE valid time | - | 1.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL_SDNWE) | SDNWE hold time | 0.5 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_ SDNE) | Chip select valid time | - | 1.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL-_SDNE) | Chip select hold time | 0.5 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_SDNRAS) | SDNRAS valid time | - | 1 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL_SDNRAS) | SDNRAS hold time | 0.5 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_SDNCAS) | SDNCAS valid time | - | 1 | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_SDNCAS) | SDNCAS hold time | 0.5 | - | |
+-------------------+------------------------+--------------+--------------+------+
1. Guaranteed by characterization results.
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #208 ===
Table 117. LPSDR SDRAM write timings⁽¹⁾
+-------------------+------------------------+--------------+--------------+------+
| Symbol | Parameter | Min | Max | Unit |
+===================+========================+==============+==============+======+
| tw(SDCLK) | FMC_SDCLK period | 2THCLK − 0.5 | 2THCLK + 0.5 | ns |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL _Data) | Data output valid time | - | 2.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL _Data) | Data output hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL_Add) | Address valid time | - | 2.5 | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL-SDNWE) | SDNWE valid time | - | 2.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL-SDNWE) | SDNWE hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL- SDNE) | Chip select valid time | - | 0.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL- SDNE) | Chip select hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL-SDNRAS) | SDNRAS valid time | - | 1.5 | |
+-------------------+------------------------+--------------+--------------+ |
| th(SDCLKL-SDNRAS) | SDNRAS hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL-SDNCAS) | SDNCAS valid time | - | 1.5 | |
+-------------------+------------------------+--------------+--------------+ |
| td(SDCLKL-SDNCAS) | SDNCAS hold time | 0 | - | |
+-------------------+------------------------+--------------+--------------+------+
1. Guaranteed by characterization results.
6.3.31 Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 118 and Table 119 for Quad-SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 17: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #209 ===
Table 118. QUADSPI characteristics in SDR mode⁽¹⁾
+------------+------------------------+------------------+-------------+-----+-------------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+============+========================+==================+=============+=====+=============+======+
| Fck1/t(CK) | QUADSPI clock | 2.7 V≤ VDD<3.6 V | - | - | 108 | MHz |
| | frequency | CL=20 pF | | | | |
| | +------------------+-------------+-----+-------------+ |
| | | 1.71 V<VDD<3.6 V | - | - | 100 | |
| | | CL=15 pF | | | | |
+------------+------------------------+------------------+-------------+-----+-------------+------+
| tw(CKH) | QUADSPI clock high and | - | t(CK)/2 - 1 | - | t(CK)/2 | ns |
+------------+ low time | +-------------+-----+-------------+ |
| tw(CKL) | | | t(CK)/2 | - | t(CK)/2 + 1 | |
+------------+------------------------+------------------+-------------+-----+-------------+ |
| ts(IN) | Data input setup time | 2.7 V<VDD<3.6 V | 1.5 | - | - | |
| | +------------------+-------------+-----+-------------+ |
| | | 1.71 V<VDD<3.6 V | 1.5 | - | - | |
+------------+------------------------+------------------+-------------+-----+-------------+ |
| th(IN) | Data input hold time | 2.7 V<VDD<3.6 V | 1.5 | - | - | |
| | +------------------+-------------+-----+-------------+ |
| | | 1.71 V<VDD<3.6 V | 2 | - | - | |
+------------+------------------------+------------------+-------------+-----+-------------+ |
| tv(OUT) | Data output valid time | 2.7 V<VDD<3.6 V | - | 1.5 | 2 | |
| | +------------------+-------------+-----+-------------+ |
| | | 1.71 V<VDD<3.6 V | - | 1.5 | 3.5 | |
+------------+------------------------+------------------+-------------+-----+-------------+ |
| th(OUT) | Data output hold time | - | 0.5 | - | - | |
+------------+------------------------+------------------+-------------+-----+-------------+------+
1. Guaranteed by characterization results.
Table 119. QUADSPI characteristics in DDR mode⁽¹⁾
+------------+---------------+------------------+-----+-----+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+============+===============+==================+=====+=====+=====+======+
| Fck1/t(CK) | QUADSPI clock | 2.7 V<VDD<3.6 V | - | - | 80 | MHz |
| | frequency | CL=20 pF | | | | |
| | +------------------+-----+-----+-----+ |
| | | 1.8 V<VDD<3.6 V | - | - | 80 | |
| | | CL=15 pF | | | | |
| | +------------------+-----+-----+-----+ |
| | | 1.71 V<VDD<3.6 V | - | - | 80 | |
| | | CL=10 pF | | | | |
+------------+---------------+------------------+-----+-----+-----+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #210 ===
Table 119. QUADSPI characteristics in DDR mode⁽¹⁾ (continued)
+-----------+------------------------+------------------+-------------+-----------+---------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+========================+==================+=============+===========+=========+======+
| tw(CKH) | QUADSPI clock high | - | t(CK)/2 - 1 | - | t(CK)/2 | ns |
+-----------+ and low time | +-------------+-----------+---------+ |
| tw(CKL) | | | t(CK)/2 | - | t(CK)/2 | |
| | | | | | + 1 | |
+-----------+------------------------+------------------+-------------+-----------+---------+ |
| ts(IN), | Data input setup time | 1.71 V<VDD<3.6 V | 1.75 | - | - | |
| tsf(IN) | | | | | | |
+-----------+------------------------+------------------+-------------+-----------+---------+ |
| thr(IN), | Data input hold time | 2.7 V<VDD<3.6 V | 1 | - | - | |
| thf(IN) | +------------------+-------------+-----------+---------+ |
| | | 1.71 V<VDD<3.6 V | 2 | - | - | |
+-----------+------------------------+------------------+-------------+-----------+---------+ |
| tvr(OUT), | Data output valid time | 2.7 V<VDD<3.6 V | - | 8.5 | 10 | |
| tvf(OUT) | +------------------+-------------+-----------+---------+ |
| | | 1.71 V<VDD<3.6 V | - | 8 | 12 | |
| | | DHHC=0 | | | | |
| | +------------------+-------------+-----------+---------+ |
| | | DHHC=1 | - | THCLK/2 + | THCLK/2 | |
| | | Pres=1, 2... | | 1.5 | + 2.5 | |
+-----------+------------------------+------------------+-------------+-----------+---------+ |
| thr(OUT), | Data output hold time | DHHC=0 | 7.5 | - | - | |
| thf(OUT) | +------------------+-------------+-----------+---------+ |
| | | DHHC=1 | THCLK/2 | - | - | |
| | | Pres=1, 2... | + 0.5 | | | |
+-----------+------------------------+------------------+-------------+-----------+---------+------+
1. Guaranteed by characterization results.
Figure 75. Quad-SPI timing diagram - SDR mode
Figure 76. Quad-SPI timing diagram - DDR mode
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #211 ===
6.3.32 Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 120 for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
Table 120. DCMI characteristics⁽¹⁾
+-------------+----------------------------------------+-----+-----+------+
| Symbol | Parameter | Min | Max | Unit |
+=============+========================================+=====+=====+======+
| - | Frequency ratio DCMI_PIXCLK/fHCLK | - | 0.4 | - |
+-------------+----------------------------------------+-----+-----+------+
| DCMI_PIXCLK | Pixel clock input | - | 54 | MHz |
+-------------+----------------------------------------+-----+-----+------+
| DPixel | Pixel clock input duty cycle | 30 | 70 | % |
+-------------+----------------------------------------+-----+-----+------+
| tsu(DATA) | Data input setup time | 2 | - | ns |
+-------------+----------------------------------------+-----+-----+ |
| th(DATA) | Data input hold time | 0.5 | - | |
+-------------+----------------------------------------+-----+-----+ |
| tsu(HSYNC) | DCMI_HSYNC/DCMI_VSYNC input setup time | 2.5 | - | |
| tsu(VSYNC) | | | | |
+-------------+----------------------------------------+-----+-----+ |
| th(HSYNC) | DCMI_HSYNC/DCMI_VSYNC input hold time | 3 | - | |
| th(VSYNC) | | | | |
+-------------+----------------------------------------+-----+-----+------+
1. Guaranteed by characterization results.
Figure 77. DCMI timing diagram
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #212 ===
6.3.33 LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 121 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
Table 121. LTDC characteristics ⁽¹⁾
+------------+----------------------------------+---------------+---------------+------+
| Symbol | Parameter | Min | Max | Unit |
+============+==================================+===============+===============+======+
| fCLK | LTDC clock output frequency | - | 83 | MHz |
+------------+----------------------------------+---------------+---------------+------+
| DCLK | LTDC clock output duty cycle | 45 | 55 | % |
+------------+----------------------------------+---------------+---------------+------+
| tw(CLKH), | Clock High time, low time | tw(CLK)/2−0.5 | tw(CLK)/2+0.5 | ns |
| tw(CLKL) | | | | |
+------------+----------------------------------+---------------+---------------+ |
| tv(DATA) | Data output valid time | - | 6 | |
+------------+----------------------------------+---------------+---------------+ |
| th(DATA) | Data output hold time | 0 | - | |
+------------+----------------------------------+---------------+---------------+ |
| tv(HSYNC), | HSYNC/VSYNC/DE output valid time | - | 3.5 | |
| tv(VSYNC), | | | | |
| tv(DE) | | | | |
+------------+----------------------------------+---------------+---------------+ |
| th(HSYNC), | HSYNC/VSYNC/DE output hold time | 0.5 | - | |
| th(VSYNC), | | | | |
| th(DE) | | | | |
+------------+----------------------------------+---------------+---------------+------+
1. Guaranteed by characterization results.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #213 ===
Figure 78. LCD-TFT horizontal timing diagram
Figure 79. LCD-TFT vertical timing diagram
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #214 ===
6.3.34 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 122 for DFSDM are derived from
tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage
summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30pF
• Measurement points are done at CMOS levels: 0.5 x VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM1_CKINx, DFSDM1_DATINx, DFSDM1_CKOUT for
DFSDM1).
Table 122. DFSDM measured timing 1.71-3.6V
+-----------+----------------+---------------------------+-----+-----+---------------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+===========+================+===========================+=====+=====+===============+======+
| fDFSDMCLK | DFSDM clock | 1.71 < VDD < 3.6 V | - | - | ᶠSYSCLK | MHz |
+-----------+----------------+---------------------------+-----+-----+---------------+ |
| fCKIN | Input clock | SPI mode (SITP[1:0]=0,1), | - | - | 20 | |
| (1/TCKIN) | frequency | External clock mode | | | (fDFSDMCLK/4) | |
| | | (SPICKSEL[1:0]=0), | | | | |
| | | 1.71 < VDD < 3.6 V | | | | |
| | +---------------------------+-----+-----+---------------+ |
| | | SPI mode (SITP[1:0]=0,1), | - | - | 20 | |
| | | External clock mode | | | (fDFSDMCLK/4) | |
| | | (SPICKSEL[1:0]=0), | | | | |
| | | 2.7 < VDD < 3.6 V | | | | |
| | +---------------------------+-----+-----+---------------+ |
| | | SPI mode (SITP[1:0]=0,1), | - | - | 20 | |
| | | Internal clock mode | | | (fDFSDMCLK/4) | |
| | | (SPICKSEL[1:0]≠0), | | | | |
| | | 1.71 < VDD < 3.6 V | | | | |
| | +---------------------------+-----+-----+---------------+ |
| | | SPI mode (SITP[1:0]=0,1), | - | - | 20 | |
| | | Internal clock mode | | | (fDFSDMCLK/4) | |
| | | (SPICKSEL[1:0]≠0), | | | | |
| | | 2.7 < VDD < 3.6 V | | | | |
+-----------+----------------+---------------------------+-----+-----+---------------+ |
| fCKOUT | Output clock | 1.71 < VDD < 3.6 V | - | - | 20 | |
| | frequency | | | | | |
+-----------+----------------+---------------------------+-----+-----+---------------+------+
| DuCyCKOUT | Output clock | 1.71 < VDD < 3.6 V | 45 | 50 | 55 | % |
| | frequency duty | | | | | |
| | cycle | | | | | |
+-----------+----------------+---------------------------+-----+-----+---------------+------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #215 ===
Table 122. DFSDM measured timing 1.71-3.6V (continued)
+-------------+-------------------+---------------------------+---------------+---------+--------------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=============+===================+===========================+===============+=========+==============+======+
| twh(CKIN) | Input clock high | SPI mode (SITP[1:0]=0,1), | TCKIN/2 - 0.5 | TCKIN/2 | - | ns |
| twl(CKIN) | and low time | External clock mode | | | | |
| | | (SPICKSEL[1:0]=0), | | | | |
| | | 1.71 < VDD < 3.6 V | | | | |
+-------------+-------------------+---------------------------+---------------+---------+--------------+ |
| tsu | Data input setup | SPI mode (SITP[1:0]=0,1), | 2 | - | - | |
| | time | External clock mode | | | | |
| | | (SPICKSEL[1:0]=0), | | | | |
| | | 1.71 < VDD < 3.6 V | | | | |
+-------------+-------------------+---------------------------+---------------+---------+--------------+ |
| th | Data input hold | SPI mode (SITP[1:0]=0,1), | 3 | - | - | |
| | time | External clock mode | | | | |
| | | (SPICKSEL[1:0]=0), | | | | |
| | | 1.71 < VDD < 3.6 V | | | | |
+-------------+-------------------+---------------------------+---------------+---------+--------------+ |
| TManchester | Manchester data | Manchester mode | (CKOUTDIV+1) | - | (2*CKOUTDIV) | |
| | period (recovered | (SITP[1:0]=2,3), | * TDFSDMCLK | | * TDFSDMCLK | |
| | clock period) | Internal clock mode | | | | |
| | | (SPICKSEL[1:0]≠0), | | | | |
| | | 1.71 < VDD < 3.6 V | | | | |
+-------------+-------------------+---------------------------+---------------+---------+--------------+------+
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #216 ===
6.3.35 DFSDM timing diagrams
Figure 80. Channel transceiver timing diagrams
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics #217 ===
6.3.36 SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 123 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Figure 81. SDIO high-speed mode
Figure 82. SD default mode
=== Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #218 ===
Table 123. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V⁽¹⁾
+---------+---------------------------------------+-------------+-----+------+-----+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=========+=======================================+=============+=====+======+=====+======+
| fPP | Clock frequency in data transfer mode | - | 0 | - | 50 | MHz |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| - | SDMMC_CK/fPCLK2 frequency ratio | - | - | - | 8/3 | - |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| tW(CKL) | Clock low time | fpp =50 MHz | 9.5 | 10.5 | - | ns |
+---------+---------------------------------------+-------------+-----+------+-----+ |
| tW(CKH) | Clock high time | fpp =50 MHz | 8.5 | 9.5 | - | |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| CMD, D inputs (referenced to CK) in MMC and SD HS mode |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| tISU | Input setup time HS | fpp =50 MHz | 4.5 | - | - | ns |
+---------+---------------------------------------+-------------+-----+------+-----+ |
| tIH | Input hold time HS | fpp =50 MHz | 1.5 | - | - | |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| CMD, D outputs (referenced to CK) in MMC and SD HS mode |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| tOV | Output valid time HS | fpp =50 MHz | - | 11 | 12 | ns |
+---------+---------------------------------------+-------------+-----+------+-----+ |
| tOH | Output hold time HS | fpp =50 MHz | 9 | - | - | |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| CMD, D inputs (referenced to CK) in SD default mode |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| tISUD | Input setup time SD | fpp =25 MHz | 4.5 | - | - | ns |
+---------+---------------------------------------+-------------+-----+------+-----+ |
| tIHD | Input hold time SD | fpp =25 MHz | 1.5 | - | - | |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| CMD, D outputs (referenced to CK) in SD default mode |
+---------+---------------------------------------+-------------+-----+------+-----+------+
| tOVD | Output valid default time SD | fpp =25 MHz | - | 0.5 | 1.5 | ns |
+---------+---------------------------------------+-------------+-----+------+-----+ |
| tOHD | Output hold default time SD | fpp =25 MHz | 0 | - | - | |
+---------+---------------------------------------+-------------+-----+------+-----+------+
1. Guaranteed by characterization results.
Table 124. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V⁽¹⁾⁽²⁾
+---------+---------------------------------------+-------------+-----+------+------+------+
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
+=========+=======================================+=============+=====+======+======+======+
| fPP | Clock frequency in data transfer mode | - | 0 | - | 50 | MHz |
+---------+---------------------------------------+-------------+-----+------+------+------+
| - | SDMMC_CK/fPCLK2 frequency ratio | - | - | - | 8/3 | - |
+---------+---------------------------------------+-------------+-----+------+------+------+
| tW(CKL) | Clock low time | fpp =50 MHz | 9.5 | 10.5 | - | ns |
+---------+---------------------------------------+-------------+-----+------+------+ |
| tW(CKH) | Clock high time | fpp =50 MHz | 8.5 | 9.5 | - | |
+---------+---------------------------------------+-------------+-----+------+------+------+
| CMD, D inputs (referenced to CK) in eMMC mode |
+---------+---------------------------------------+-------------+-----+------+------+------+
| tISU | Input setup time HS | fpp =50 MHz | 4 | - | - | ns |
+---------+---------------------------------------+-------------+-----+------+------+ |
| tIH | Input hold time HS | fpp =50 MHz | 3 | - | - | |
+---------+---------------------------------------+-------------+-----+------+------+------+
| CMD, D outputs (referenced to CK) in eMMC mode |
+---------+---------------------------------------+-------------+-----+------+------+------+
| tOV | Output valid time HS | fpp =50 MHz | - | 11 | 15.5 | ns |
+---------+---------------------------------------+-------------+-----+------+------+ |
| tOH | Output hold time HS | fpp =50 MHz | 9.5 | - | - | |
+---------+---------------------------------------+-------------+-----+------+------+------+
1. Guaranteed by characterization results.
2. Cload = 20 pF.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #219 ===
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1 LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 83. LQFP100 outline
1. Drawing is not to scale.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #220 ===
Table 125. LQPF100 mechanical data
+--------+--------------------------+--------------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +--------+--------+--------+--------+--------+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+--------+--------+--------+--------+--------+--------+
| A | - | - | 1.600 | - | - | 0.0630 |
+--------+--------+--------+--------+--------+--------+--------+
| A1 | 0.050 | - | 0.150 | 0.0020 | - | 0.0059 |
+--------+--------+--------+--------+--------+--------+--------+
| A2 | 1.350 | 1.400 | 1.450 | 0.0531 | 0.0551 | 0.0571 |
+--------+--------+--------+--------+--------+--------+--------+
| b | 0.170 | 0.220 | 0.270 | 0.0067 | 0.0087 | 0.0106 |
+--------+--------+--------+--------+--------+--------+--------+
| c | 0.090 | - | 0.200 | 0.0035 | - | 0.0079 |
+--------+--------+--------+--------+--------+--------+--------+
| D | 15.800 | 16.000 | 16.200 | 0.6220 | 0.6299 | 0.6378 |
+--------+--------+--------+--------+--------+--------+--------+
| D1 | 13.800 | 14.000 | 14.200 | 0.5433 | 0.5512 | 0.5591 |
+--------+--------+--------+--------+--------+--------+--------+
| D3 | - | 12.000 | - | - | 0.4724 | - |
+--------+--------+--------+--------+--------+--------+--------+
| E | 15.800 | 16.000 | 16.200 | 0.6220 | 0.6299 | 0.6378 |
+--------+--------+--------+--------+--------+--------+--------+
| E1 | 13.800 | 14.000 | 14.200 | 0.5433 | 0.5512 | 0.5591 |
+--------+--------+--------+--------+--------+--------+--------+
| E3 | - | 12.000 | - | - | 0.4724 | - |
+--------+--------+--------+--------+--------+--------+--------+
| e | - | 0.500 | - | - | 0.0197 | - |
+--------+--------+--------+--------+--------+--------+--------+
| L | 0.450 | 0.600 | 0.750 | 0.0177 | 0.0236 | 0.0295 |
+--------+--------+--------+--------+--------+--------+--------+
| L1 | - | 1.000 | - | - | 0.0394 | - |
+--------+--------+--------+--------+--------+--------+--------+
| k | 0° | 3.5° | 7° | 0° | 3.5° | 7° |
+--------+--------+--------+--------+--------+--------+--------+
| ccc | - | - | 0.080 | - | - | 0.0031 |
+--------+--------+--------+--------+--------+--------+--------+
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 84. LQFP100 recommended footprint
1. Dimensions are expressed in millimeters.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #221 ===
LQFP100 device making
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 85. LQFP100 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #222 ===
7.2 TFBGA100 package information
TFBGA100 is a 100-ball, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package.
Figure 86. TFBGA100 outline
1. Drawing is not to scale.
Table 126. TFBGA100 mechanical data
+--------+-----------------------+--------------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +-------+-------+-------+--------+--------+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+-------+-------+-------+--------+--------+--------+
| A | - | - | 1.100 | - | - | 0.0433 |
+--------+-------+-------+-------+--------+--------+--------+
| A1 | 0.150 | - | - | 0.0059 | - | - |
+--------+-------+-------+-------+--------+--------+--------+
| A2 | - | 0.760 | - | - | 0.0299 | - |
+--------+-------+-------+-------+--------+--------+--------+
| b | 0.350 | 0.400 | 0.450 | 0.0138 | 0.0157 | 0.0177 |
+--------+-------+-------+-------+--------+--------+--------+
| D | 7.850 | 8.000 | 8.150 | 0.3091 | 0.3150 | 0.3209 |
+--------+-------+-------+-------+--------+--------+--------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #223 ===
Table 126. TFBGA100 mechanical data (continued)
+--------+-----------------------+--------------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +-------+-------+-------+--------+--------+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+-------+-------+-------+--------+--------+--------+
| D1 | - | 7.200 | - | - | 0.2835 | - |
+--------+-------+-------+-------+--------+--------+--------+
| E | 7.850 | 8.000 | 8.150 | 0.3091 | 0.3150 | 0.3209 |
+--------+-------+-------+-------+--------+--------+--------+
| E1 | - | 7.200 | - | - | 0.2835 | - |
+--------+-------+-------+-------+--------+--------+--------+
| e | - | 0.800 | - | - | 0.0315 | - |
+--------+-------+-------+-------+--------+--------+--------+
| F | - | 0.400 | - | - | 0.0157 | - |
+--------+-------+-------+-------+--------+--------+--------+
| G | - | 0.400 | - | - | 0.0157 | - |
+--------+-------+-------+-------+--------+--------+--------+
| ddd | - | - | 0.100 | - | - | 0.0039 |
+--------+-------+-------+-------+--------+--------+--------+
| eee | - | - | 0.150 | - | - | 0.0059 |
+--------+-------+-------+-------+--------+--------+--------+
| fff | - | - | 0.080 | - | - | 0.0031 |
+--------+-------+-------+-------+--------+--------+--------+
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 87. TFBGA100 recommended footprint
1. Dimensions are expressed in millimeters.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #224 ===
Table 127. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA)
+-------------------+-----------------------------------------+
| Dimension | Recommended values |
+===================+=========================================+
| Pitch | 0.8 |
+-------------------+-----------------------------------------+
| Dpad | 0.400 mm |
+-------------------+-----------------------------------------+
| Dsm | 0.470 mm typ (depends on the soldermask |
| | registration tolerance) |
+-------------------+-----------------------------------------+
| Stencil opening | 0.400 mm |
+-------------------+-----------------------------------------+
| Stencil thickness | Between 0.100 mm and 0.125 mm |
+-------------------+-----------------------------------------+
| Pad trace width | 0.120 mm |
+-------------------+-----------------------------------------+
TFBGA100 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 88. TFBGA100 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #225 ===
7.3 LQFP144 package information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 89. LQFP144 outline
1. Drawing is not to scale.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #226 ===
Table 128. LQFP144 mechanical data
+--------+--------------------------+--------------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +--------+--------+--------+--------+--------+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+--------+--------+--------+--------+--------+--------+
| A | - | - | 1.600 | - | - | 0.0630 |
+--------+--------+--------+--------+--------+--------+--------+
| A1 | 0.050 | - | 0.150 | 0.0020 | - | 0.0059 |
+--------+--------+--------+--------+--------+--------+--------+
| A2 | 1.350 | 1.400 | 1.450 | 0.0531 | 0.0551 | 0.0571 |
+--------+--------+--------+--------+--------+--------+--------+
| b | 0.170 | 0.220 | 0.270 | 0.0067 | 0.0087 | 0.0106 |
+--------+--------+--------+--------+--------+--------+--------+
| c | 0.090 | - | 0.200 | 0.0035 | - | 0.0079 |
+--------+--------+--------+--------+--------+--------+--------+
| D | 21.800 | 22.000 | 22.200 | 0.8583 | 0.8661 | 0.874 |
+--------+--------+--------+--------+--------+--------+--------+
| D1 | 19.800 | 20.000 | 20.200 | 0.7795 | 0.7874 | 0.7953 |
+--------+--------+--------+--------+--------+--------+--------+
| D3 | - | 17.500 | - | - | 0.689 | - |
+--------+--------+--------+--------+--------+--------+--------+
| E | 21.800 | 22.000 | 22.200 | 0.8583 | 0.8661 | 0.8740 |
+--------+--------+--------+--------+--------+--------+--------+
| E1 | 19.800 | 20.000 | 20.200 | 0.7795 | 0.7874 | 0.7953 |
+--------+--------+--------+--------+--------+--------+--------+
| E3 | - | 17.500 | - | - | 0.6890 | - |
+--------+--------+--------+--------+--------+--------+--------+
| e | - | 0.500 | - | - | 0.0197 | - |
+--------+--------+--------+--------+--------+--------+--------+
| L | 0.450 | 0.600 | 0.750 | 0.0177 | 0.0236 | 0.0295 |
+--------+--------+--------+--------+--------+--------+--------+
| L1 | - | 1.000 | - | - | 0.0394 | - |
+--------+--------+--------+--------+--------+--------+--------+
| k | 0° | 3.5° | 7° | 0° | 3.5° | 7° |
+--------+--------+--------+--------+--------+--------+--------+
| ccc | - | - | 0.080 | - | - | 0.0031 |
+--------+--------+--------+--------+--------+--------+--------+
1. Values in inches are converted from mm and rounded to 4 decimal digits.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #227 ===
Figure 90. LQFP144 recommended footprint
1. Dimensions are expressed in millimeters.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #228 ===
LQFP144 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 91. LQFP144 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #229 ===
7.4 LQFP176 package information
LQFP176 is a 176-pin, 24 x 24 mm low-profile quad flat package.
Figure 92. LQFP176 outline
1. Drawing is not to scale.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #230 ===
Table 129. LQFP176 mechanical data
+--------+-------------------------+--------------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +--------+-------+--------+--------+--------+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+--------+-------+--------+--------+--------+--------+
| A | - | - | 1.600 | - | - | 0.0630 |
+--------+--------+-------+--------+--------+--------+--------+
| A1 | 0.050 | - | 0.150 | 0.0020 | - | 0.0059 |
+--------+--------+-------+--------+--------+--------+--------+
| A2 | 1.350 | - | 1.450 | 0.0531 | - | 0.0060 |
+--------+--------+-------+--------+--------+--------+--------+
| b | 0.170 | - | 0.270 | 0.0067 | - | 0.0106 |
+--------+--------+-------+--------+--------+--------+--------+
| C | 0.090 | - | 0.200 | 0.0035 | - | 0.0079 |
+--------+--------+-------+--------+--------+--------+--------+
| D | 23.900 | - | 24.100 | 0.9409 | - | 0.9488 |
+--------+--------+-------+--------+--------+--------+--------+
| E | 23.900 | - | 24.100 | 0.9409 | - | 0.9488 |
+--------+--------+-------+--------+--------+--------+--------+
| e | - | 0.500 | - | - | 0.0197 | - |
+--------+--------+-------+--------+--------+--------+--------+
| HD | 25.900 | - | 26.100 | 1.0200 | - | 1.0276 |
+--------+--------+-------+--------+--------+--------+--------+
| HE | 25.900 | - | 26.100 | 1.0200 | - | 1.0276 |
+--------+--------+-------+--------+--------+--------+--------+
| L | 0.450 | - | 0.750 | 0.0177 | - | 0.0295 |
+--------+--------+-------+--------+--------+--------+--------+
| L1 | - | 1.000 | - | - | 0.0394 | - |
+--------+--------+-------+--------+--------+--------+--------+
| ZD | - | 1.250 | - | - | 0.0492 | - |
+--------+--------+-------+--------+--------+--------+--------+
| ZE | - | 1.250 | - | - | 0.0492 | - |
+--------+--------+-------+--------+--------+--------+--------+
| ccc | - | - | 0.080 | - | - | 0.0031 |
+--------+--------+-------+--------+--------+--------+--------+
| k | 0 ° | - | 7 ° | 0 ° | - | 7 ° |
+--------+--------+-------+--------+--------+--------+--------+
1. Values in inches are converted from mm and rounded to 4 decimal digits.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #231 ===
Figure 93. LQFP176 recommended footprint
1. Dimensions are expressed in millimeters.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #232 ===
LQFP176 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 94. LQFP176 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #233 ===
7.5 UFBGA176+25 package information
UFBGA176+25 is a 176+25-ball, 10 x 10 mm, 0.65 mm ultra profile fine pitch ball grid array
package.
Figure 95. UFBGA176+25 outline
1. Drawing is not to scale.
Table 130. UFBGA176+25 mechanical data
+--------+-------------------------+--------------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +-------+--------+--------+--------+--------+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+-------+--------+--------+--------+--------+--------+
| A | 0.460 | 0.530 | 0.600 | 0.0181 | 0.0209 | 0.0236 |
+--------+-------+--------+--------+--------+--------+--------+
| A1 | 0.050 | 0.080 | 0.110 | 0.002 | 0.0031 | 0.0043 |
+--------+-------+--------+--------+--------+--------+--------+
| A2 | 0.400 | 0.450 | 0.500 | 0.0157 | 0.0177 | 0.0197 |
+--------+-------+--------+--------+--------+--------+--------+
| b | 0.230 | 0.280 | 0.330 | 0.0091 | 0.0110 | 0.0130 |
+--------+-------+--------+--------+--------+--------+--------+
| D | 9.950 | 10.000 | 10.050 | 0.3917 | 0.3937 | 0.3957 |
+--------+-------+--------+--------+--------+--------+--------+
| E | 9.950 | 10.000 | 10.050 | 0.3917 | 0.3937 | 0.3957 |
+--------+-------+--------+--------+--------+--------+--------+
| e | - | 0.650 | - | - | 0.0256 | - |
+--------+-------+--------+--------+--------+--------+--------+
| F | 0.400 | 0.450 | 0.500 | 0.0157 | 0.0177 | 0.0197 |
+--------+-------+--------+--------+--------+--------+--------+
| ddd | - | - | 0.080 | - | - | 0.0031 |
+--------+-------+--------+--------+--------+--------+--------+
| eee | - | - | 0.150 | - | - | 0.0059 |
+--------+-------+--------+--------+--------+--------+--------+
| fff | - | - | 0.080 | - | - | 0.0031 |
+--------+-------+--------+--------+--------+--------+--------+
1. Values in inches are converted from mm and rounded to 4 decimal digits.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #234 ===
Figure 96. UFBGA176+25 recommended footprint
Table 131. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
+-------------------+-----------------------------------------------+
| Dimension | Recommended values |
+===================+===============================================+
| Pitch | 0.65 mm |
+-------------------+-----------------------------------------------+
| Dpad | 0.300 mm |
+-------------------+-----------------------------------------------+
| Dsm | 0.400 mm typ. (depends on the soldermask reg- |
| | istration tolerance) |
+-------------------+-----------------------------------------------+
| Stencil opening | 0.300 mm |
+-------------------+-----------------------------------------------+
| Stencil thickness | Between 0.100 mm and 0.125 mm |
+-------------------+-----------------------------------------------+
| Pad trace width | 0.100 mm |
+-------------------+-----------------------------------------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #235 ===
UFBGA176+25 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 97. UFBGA176+25 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #236 ===
7.6 WLCSP180 package information
WLCSP180 is a 180-bump, 5.5 x 6 mm wafer level chip scale package.
Figure 98. WLCSP180 outline
1. Drawing is not to scale.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #237 ===
Table 132. WLCSP180 mechanical data
+--------+-----------------------+--------------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +-------+-------+-------+--------+--------+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+-------+-------+-------+--------+--------+--------+
| A | 0.525 | 0.555 | 0.585 | 0.0207 | 0.0219 | 0.230 |
+--------+-------+-------+-------+--------+--------+--------+
| A1 | - | 0.175 | - | - | 0.0069 | - |
+--------+-------+-------+-------+--------+--------+--------+
| A2 | - | 0.380 | - | - | 0.0150 | - |
+--------+-------+-------+-------+--------+--------+--------+
| A3 | - | 0.025 | - | - | 0.0010 | - |
+--------+-------+-------+-------+--------+--------+--------+
| b⁽²⁾ | 0.220 | 0.250 | 0.280 | 0.0087 | 0.0098 | 0.0110 |
+--------+-------+-------+-------+--------+--------+--------+
| D | 5.502 | 5.537 | 5.572 | 0.2166 | 0.2180 | 0.2194 |
+--------+-------+-------+-------+--------+--------+--------+
| E | 6.060 | 6.095 | 6.130 | 0.2386 | 0.2400 | 0.2413 |
+--------+-------+-------+-------+--------+--------+--------+
| e | - | 0.400 | - | - | 0.0157 | - |
+--------+-------+-------+-------+--------+--------+--------+
| e1 | - | 4.800 | - | - | 0.1890 | - |
+--------+-------+-------+-------+--------+--------+--------+
| e2 | - | 5.200 | - | - | 0.2047 | - |
+--------+-------+-------+-------+--------+--------+--------+
| F | - | 0.368 | - | - | 0.0145 | - |
+--------+-------+-------+-------+--------+--------+--------+
| G | - | 0.477 | - | - | 0.0188 | - |
+--------+-------+-------+-------+--------+--------+--------+
| aaa | - | 0.110 | - | - | 0.0043 | - |
+--------+-------+-------+-------+--------+--------+--------+
| bbb | - | 0.110 | - | - | 0.0043 | - |
+--------+-------+-------+-------+--------+--------+--------+
| ccc | - | 0.110 | - | - | 0.0043 | - |
+--------+-------+-------+-------+--------+--------+--------+
| ddd | - | 0.050 | - | - | 0.0020 | - |
+--------+-------+-------+-------+--------+--------+--------+
| eee | - | 0.050 | - | - | 0.0020 | - |
+--------+-------+-------+-------+--------+--------+--------+
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 99. WLCSP180 recommended footprint
1. Dimensions are expressed in millimeters.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #238 ===
Table 133. WLCSP180 recommended PCB design rules (0.4 mm pitch)
+-------------------+------------------------------------------+
| Dimension | Recommended values |
+===================+==========================================+
| Pitch | 0.4 |
+-------------------+------------------------------------------+
| Dpad | 0.225 mm |
+-------------------+------------------------------------------+
| Dsm | 0.290 mm typ. (depends on the soldermask |
| | registration tolerance) |
+-------------------+------------------------------------------+
| Stencil opening | 0.250 mm |
+-------------------+------------------------------------------+
| Stencil thickness | 0.1 mm |
+-------------------+------------------------------------------+
WLCSP180 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 100. WLCSP180 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #239 ===
7.7 LQFP208 package information
LQFP208 is a 208-pin, 28 x 28 mm low-profile quad flat package.
Figure 101. LQFP208 outline
1. Drawing is not to scale.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #240 ===
Table 134. LQFP208 mechanical data
+--------+--------------------------+--------------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +--------+--------+--------+--------+--------+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+--------+--------+--------+--------+--------+--------+
| A | - | - | 1.600 | -- | - | 0.0630 |
+--------+--------+--------+--------+--------+--------+--------+
| A1 | 0.050 | - | 0.150 | 0.0020 | - | 0.0059 |
+--------+--------+--------+--------+--------+--------+--------+
| A2 | 1.350 | 1.400 | 1.450 | 0.0531 | 0.0551 | 0.0571 |
+--------+--------+--------+--------+--------+--------+--------+
| b | 0.170 | 0.220 | 0.270 | 0.0067 | 0.0087 | 0.0106 |
+--------+--------+--------+--------+--------+--------+--------+
| c | 0.090 | - | 0.200 | 0.0035 | - | 0.0079 |
+--------+--------+--------+--------+--------+--------+--------+
| D | 29.800 | 30.000 | 30.200 | 1.1732 | 1.1811 | 1.1890 |
+--------+--------+--------+--------+--------+--------+--------+
| D1 | 27.800 | 28.000 | 28.200 | 1.0945 | 1.1024 | 1.1102 |
+--------+--------+--------+--------+--------+--------+--------+
| D3 | - | 25.500 | - | - | 1.0039 | - |
+--------+--------+--------+--------+--------+--------+--------+
| E | 29.800 | 30.000 | 30.200 | 1.1732 | 1.1811 | 1.1890 |
+--------+--------+--------+--------+--------+--------+--------+
| E1 | 27.800 | 28.000 | 28.200 | 1.0945 | 1.1024 | 1.1102 |
+--------+--------+--------+--------+--------+--------+--------+
| E3 | - | 25.500 | - | - | 1.0039 | - |
+--------+--------+--------+--------+--------+--------+--------+
| e | - | 0.500 | - | - | 0.0197 | - |
+--------+--------+--------+--------+--------+--------+--------+
| L | 0.450 | 0.600 | 0.750 | 0.0177 | 0.0236 | 0.0295 |
+--------+--------+--------+--------+--------+--------+--------+
| L1 | - | 1.000 | - | - | 0.0394 | - |
+--------+--------+--------+--------+--------+--------+--------+
| k | 0° | 3.5° | 7.0° | 0° | 3.5° | 7.0° |
+--------+--------+--------+--------+--------+--------+--------+
| ccc | - | - | 0.080 | - | - | 0.0031 |
+--------+--------+--------+--------+--------+--------+--------+
1. Values in inches are converted from mm and rounded to 4 decimal digits.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #241 ===
Figure 102. LQFP208 recommended footprint
1. Dimensions are expressed in millimeters.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #242 ===
LQFP208 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 103. LQFP208 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #243 ===
7.8 TFBGA216 package information
TFBGA216 is a 216-ball, 13 x 13 mm x 0.8 mm ultra profile fine pitch ball grid array
package.
Figure 104. TFBGA216 outline
1. Drawing is not to scale.
Table 135. TFBGA216 mechanical data
+--------+--------------------------+--------------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +--------+--------+--------+--------+--------+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+--------+--------+--------+--------+--------+--------+
| A | - | - | 1.100 | - | - | 0.0433 |
+--------+--------+--------+--------+--------+--------+--------+
| A1 | 0.150 | - | - | 0.0059 | - | - |
+--------+--------+--------+--------+--------+--------+--------+
| A2 | - | 0.760 | - | - | 0.0299 | - |
+--------+--------+--------+--------+--------+--------+--------+
| b | 0.350 | 0.400 | 0.450 | 0.0138 | 0.0157 | 0.0177 |
+--------+--------+--------+--------+--------+--------+--------+
| D | 12.850 | 13.000 | 13.150 | 0.5118 | 0.5118 | 0.5177 |
+--------+--------+--------+--------+--------+--------+--------+
| D1 | - | 11.200 | - | - | 0.4409 | - |
+--------+--------+--------+--------+--------+--------+--------+
| E | 12.850 | 13.000 | 13.150 | 0.5118 | 0.5118 | 0.5177 |
+--------+--------+--------+--------+--------+--------+--------+
| E1 | - | 11.200 | - | - | 0.4409 | - |
+--------+--------+--------+--------+--------+--------+--------+
| e | - | 0.800 | - | - | 0.0315 | - |
+--------+--------+--------+--------+--------+--------+--------+
| F | - | 0.900 | - | - | 0.0354 | - |
+--------+--------+--------+--------+--------+--------+--------+
| G | - | 0.900 | - | - | 0.0354 | - |
+--------+--------+--------+--------+--------+--------+--------+
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #244 ===
Table 135. TFBGA216 mechanical data (continued)
+--------+-------------------+--------------------+
| Symbol | millimeters | inches⁽¹⁾ |
| +-----+-----+-------+-----+-----+--------+
| | Min | Typ | Max | Min | Typ | Max |
+========+-----+-----+-------+-----+-----+--------+
| ddd | - | - | 0.100 | - | - | 0.0039 |
+--------+-----+-----+-------+-----+-----+--------+
| eee | - | - | 0.150 | - | - | 0.0059 |
+--------+-----+-----+-------+-----+-----+--------+
| fff | - | - | 0.080 | - | - | 0.0031 |
+--------+-----+-----+-------+-----+-----+--------+
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 105. TFBGA216 recommended footprint
Table 136. TFBGA216 recommended PCB design rules (0.8 mm pitch BGA)
+-------------------+-----------------------------------------------+
| Dimension | Recommended values |
+===================+===============================================+
| Pitch | 0.8 |
+-------------------+-----------------------------------------------+
| Dpad | 0.400 mm |
+-------------------+-----------------------------------------------+
| Dsm | 0.470 mm typ. (depends on the soldermask reg- |
| | istration tolerance) |
+-------------------+-----------------------------------------------+
| Stencil opening | 0.400 mm |
+-------------------+-----------------------------------------------+
| Stencil thickness | Between 0.100 mm and 0.125 mm |
+-------------------+-----------------------------------------------+
| Pad trace width | 0.120 mm |
+-------------------+-----------------------------------------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information #245 ===
TFBGA216 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 106. TFBGA216 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
=== Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #246 ===
7.9 Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 137. Package thermal characteristics
+--------+--------------------------------------+-------+------+
| Symbol | Parameter | Value | Unit |
+========+======================================+=======+======+
| ΘJA | Thermal resistance junction-ambient | 43 | °C/W |
| | LQFP100 - 14 × 14 mm / 0.5 mm pitch | | |
| +--------------------------------------+-------+ |
| | Thermal resistance junction-ambient | 36.2 | |
| | TFBGA100 - 8 × 8 mm / 0.8 mm pitch | | |
| +--------------------------------------+-------+ |
| | Thermal resistance junction-ambient | 30 | |
| | WLCSP180 - 0.4 mm pitch | | |
| +--------------------------------------+-------+ |
| | Thermal resistance junction-ambient | 40 | |
| | LQFP144 - 20 × 20 mm / 0.5 mm pitch | | |
| +--------------------------------------+-------+ |
| | Thermal resistance junction-ambient | 38 | |
| | LQFP176 - 24 × 24 mm / 0.5 mm pitch | | |
| +--------------------------------------+-------+ |
| | Thermal resistance junction-ambient | 19 | |
| | LQFP208 - 28 × 28 mm / 0.5 mm pitch | | |
| +--------------------------------------+-------+ |
| | Thermal resistance junction-ambient | 39 | |
| | UFBGA176 - 10× 10 mm / 0.5 mm pitch | | |
| +--------------------------------------+-------+ |
| | Thermal resistance junction-ambient | 29 | |
| | TFBGA216 - 13 × 13 mm / 0.8 mm pitch | | |
+--------+--------------------------------------+-------+------+
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Ordering information #247 ===
8 Ordering information
Table 138. Ordering information scheme
Example: STM32 F 76x V G T 6 xxx
+---+---+---+---+---+---+---+
| | | | | | | |
+===+ | | | | | |
| | | | | | | |
+---+===+ | | | | |
| | | | | | |
+-------+===+ | | | |
| | | | | |
+-----------+===+ | | |
| | | | |
+---------------+===+ | |
| | | |
+-------------------+===+ |
| | |
+-----------------------+===+
xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
=== Recommendations when using internal reset OFF STM32F765xx STM32F767xx STM32F768Ax #248 ===
Appendix A Recommendations when using internal reset
OFF
When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• VBAT functionality is no more available and VBAT pin should be connected to VDD
• The over-drive mode is not supported
A.1 Operating conditions
Table 139. Limitations depending on the operating power supply range
+-------------+------------+--------------+--------------------+---------------+-----------------+
| Operating | ADC | Maximum | Maximum Flash | I/O operation | Possible Flash |
| power | operation | Flash | memory access | | memory |
| supply | | memory | frequency with | | operations |
| range | | access | wait states ⁽¹⁾⁽²⁾ | | |
| | | frequency | | | |
| | | with no wait | | | |
| | | states | | | |
| | | (fFlashmax) | | | |
+=============+============+==============+====================+===============+=================+
| VDD =1.7 to | Conversion | 20 MHz | 168 MHz with 8 | – No I/O | 8-bit erase and |
| 2.1 V⁽³⁾ | time up to | | wait states and | compensation | program |
| | 1.2 Msps | | over-drive OFF | | operations only |
+-------------+------------+--------------+--------------------+---------------+-----------------+
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states
given here does not impact the execution speed from the Flash memory since the ART accelerator or L1-
cache allows to achieve a performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 3.18.1: Internal reset ON).
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Revision history #249 ===
Revision history
Table 140. Document revision history
+-------------+----------+------------------------------------------------------------------------+
| Date | Revision | Changes |
+=============+==========+========================================================================+
| 21-Mar-2016 | 1 | Initial release. |
+-------------+----------+------------------------------------------------------------------------+
| 26-Apr-2016 | 2 | DFSDM replaced by DFSDM1 in: |
| | | – Table 11: STM32F765xx, STM32F767xx, STM32F768Ax and |
| | | STM32F769xx pin and ball definitions. |
| | | – Table 13: STM32F765xx, STM32F767xx, STM32F768Ax and |
| | | STM32F769xx alternate function mapping. |
| | | – Section 6.3.34: Digital filter for Sigma-Delta Modulators (DFSDM) |
| | | characteristics. |
| | | Updated Table 2: STM32F765xx, STM32F767xx, STM32F768Ax and |
| | | STM32F769xx features and peripheral counts adding DFSDM1 |
| | | features. |
| | | Updated Table 39: Peripheral current consumption adding DFSDM1 |
| | | current consumption. |
| | | Updated cover in 2 pages. |
| | | Update cover replacing for SPI ‘up to 50 Mbit/s’ by ‘up to 54 Mbit/s’. |
+-------------+----------+------------------------------------------------------------------------+
| 06-May-2016 | 3 | Updated Table 2: STM32F765xx, STM32F767xx, STM32F768Ax and |
| | | STM32F769xx features and peripheral counts GPIO number. |
| | | Updated Table 13: STM32F765xx, STM32F767xx, STM32F768Ax and |
| | | STM32F769xx alternate function mapping adding CAN3_RX alternate |
| | | function on PA8/AF11. |
+-------------+----------+------------------------------------------------------------------------+
| 22-Dec-2016 | 4 | Updated Table 97: Dynamics characteristics: Ethernet MAC signals for |
| | | RMII. |
| | | Updated Table 71: ADC characteristics sampling rate. |
| | | Updated all the notes removing ‘not tested in production’. |
| | | Updated Figure 46: SPI timing diagram - slave mode and CPHA = 0 |
| | | and Figure 47: SPI timing diagram - slave mode and CPHA = 1⁽¹⁾ with |
| | | modified NSS timing waveforms (among other changes). |
| | | Updated Table 121: LTDC characteristics clock output frequency at |
| | | 65 MHz. |
| | | Updated Section 6.2: Absolute maximum ratings. |
| | | Updated Section 7: Package information adding information about |
| | | other optional marking or inset/upset marks. |
+-------------+----------+------------------------------------------------------------------------+
=== Revision history STM32F765xx STM32F767xx STM32F768Ax STM32F769xx #250 ===
Table 140. Document revision history (continued)
+-------------+----------+------------------------------------------------------------------------------+
| Date | Revision | Changes |
+=============+==========+==============================================================================+
| 09-Aug-2017 | 5 | Updated note 1 below all the package device marking figures. |
| | | Updated cover title. |
| | | Updated Section 1: Introduction. |
| | | Updated Section 3.47: DSI Host (DSIHOST) video mode interface |
| | | features. |
| | | Added Table 9: DFSDM implementation. |
| | | Updated Figure 11: STM32F76xxx LQFP100 pinout pin 43 and pin 44. |
| | | Updated Table 64: I/O current injection susceptibility note by ‘injection is |
| | | not possible’. |
| | | Updated Table 121: LTDC characteristics LTDC clock frequency at |
| | | 83 MHz. |
| | | Updated Table 71: ADC characteristics RADC min at 1.5 Kohm. |
| | | Updated Figure 40: Recommended NRST pin protection note about the |
| | | 0.1uF capacitor. |
| | | Updated Table 82: DAC characteristics RLOAD feature. |
+-------------+----------+------------------------------------------------------------------------------+
| 11-Sep-2017 | 6 | Added TFBGA100 package: |
| | | – Updated cover page. |
| | | – Updated Table 2: STM32F765xx, STM32F767xx, STM32F768Ax and |
| | | STM32F769xx features and peripheral counts. |
| | | – Updated Table 4: Regulator ON/OFF and internal reset ON/OFF |
| | | availability. |
| | | – Added Figure 12: STM32F76xxx TFBGA100 pinout. |
| | | – Updated Table 11: STM32F765xx, STM32F767xx, STM32F768Ax |
| | | and STM32F769xx pin and ball definitions. |
| | | – Updated Table 17: General operating conditions. |
| | | – Updated Table 62: ESD absolute maximum ratings. |
| | | – Updated note below Figure 43: Power supply and reference |
| | | decoupling (VREF+ not connected to VDDA). |
| | | – Updated note below Figure 44: Power supply and reference |
| | | decoupling (VREF+ connected to VDDA). |
| | | – Added Section 7.2: TFBGA100 package information. |
| | | – Updated Table 137: Package thermal characteristics. |
+-------------+----------+------------------------------------------------------------------------------+
=== STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Revision history #251 ===
Table 140. Document revision history (continued)
+-------------+----------+---------------------------------------------------------------------+
| Date | Revision | Changes |
+=============+==========+=====================================================================+
| 11-Feb-2021 | 7 | Added Section 1: Introduction. |
| | | Updated: |
| | | – Figure 3: STM32F765xx, STM32F767xx, STM32F768Ax and |
| | | STM32F769xx AXI-AHB bus matrix architecture⁽¹⁾ APB2 connection. |
| | | – Figure 25: STM32F765xx/STM32F767xx/STM32F777xx power |
| | | supply scheme title. |
| | | – Section 5: Memory mapping. |
| | | – Figure 40: Recommended NRST pin protection note 2. |
| | | – Table 45: HSI oscillator characteristics note 1. |
| | | – Table 85: SPI dynamic characteristics. |
| | | – Table 98: Dynamics characteristics: Ethernet MAC signals for MII. |
| | | – Table 108: Synchronous multiplexed NOR/PSRAM read timings. |
| | | – Table 110: Synchronous non-multiplexed NOR/PSRAM read timings. |
| | | – Table 114: SDRAM read timings. |
| | | – Table 115: LPSDR SDRAM read timings. |
| | | – Table 118: QUADSPI characteristics in SDR mode. |
| | | – Table 119: QUADSPI characteristics in DDR mode. |
| | | – Table 123: Dynamic characteristics: SD / MMC characteristics, |
| | | VDD=2.7V to 3.6V. |
| | | – Table 124: Dynamic characteristics: eMMC characteristics, |
| | | VDD=1.71V to 1.9V. |
| | | – Section 7: Package information. |
| | | – Figure 95: UFBGA176+25 outline. |
+-------------+----------+---------------------------------------------------------------------+
Raw
RM0410.txt
This file has been truncated, but you can view the full file.
=== Cover #1 ===
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32F76xxx and STM32F77xxx microcontroller memory and peripherals.
The STM32F76xxx and STM32F77xxx is a family of microcontrollers with different memory
sizes, packages and peripherals.
For ordering information, mechanical and electrical device characteristics refer to the
datasheets.
For information on the Arm® Cortex®-M7 with FPU core, refer to the Cortex®-M7 with FPU
Technical Reference Manual.
Related documents
Available from STMicroelectronics web site www.st.com:
• STM32F76xxx and STM32F77xxx datasheets
• STM32F7 Series Cortex®-M7 processor programming manual (PM0253)
=== Documentation conventions RM0410 #69 ===
1 Documentation conventions
1.1 General information
The STM32F76xxx and STM32F77xxx devices have an Arm®⁽ᵃ⁾ Cortex®-M7 core.
1.2 List of abbreviations for registers
The following abbreviations⁽ᵇ⁾ are used in register descriptions:
read/write (rw) Software can read and write to this bit.
read-only (r) Software can only read this bit.
write-only (w) Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo) Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STM microcontrollers, some of them may not be
used in the current document.
=== RM0410 Documentation conventions #70 ===
1.3 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
• The CPU core integrates two debug ports:
– JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
– SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols, refer to the Cortex®-M7 Technical
Reference Manual.
• Word: data of 32-bit length.
• Half-word: data of 16-bit length.
• Byte: data of 8-bit length.
• Double word: data of 64-bit length.
• IAP (in-application programming): IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
• ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
• Option bytes: product configuration bits stored in the Flash memory.
• AHB: advanced high-performance bus.
• AHBS: AHB Slave bus.
• AXIM: AXI master bus.
• ITCM: Instruction Tighly Coupled Memory.
• DTCM: Data Tighly Coupled Memory.
• CPU: refers to the Cortex®-M7 core.
1.4 Peripheral availability
For peripheral availability and number across all sales types, refer to the particular device
datasheet.
=== System and memory overview RM0410 #71 ===
2 System and memory overview
2.1 System architecture
The main system architecture is based on 2 sub-systems:
• An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
– 1x AXI to 64-bit AHB bridge connected to the embedded flash
– 3x AXI to 32bit AHB bridge connected to AHB bus matrix
• A multi-AHB Bus-Matrix
Figure 1. System architecture for STM32F76xxx and STM32F77xxx devices
=== RM0410 System and memory overview #72 ===
The multi-AHB Bus-Matrix interconnects all the masters and slaves and it consists on:
– 32-bit multi-AHB Bus-Matrix
– 64-bit multi-AHB Bus-Matrix: It interconnects the 64-bit AHB bus from CPU
through the AXI to AHB bridge and the 32-bit AHB bus from GP DMAs and
peripheral DMAs upsized to 64-bit to the internal flash.
The multi AHB bus matrix interconnects:
• 12 bus masters:
– 3x32-bit AHB bus Cortex®-M7 AXI Master bus 64-bits, splitted 4 masters through
the AXI to AHB bridge.
– 1x64-bit AHB bus connected to the embedded flash
– Cortex® -M7 AHB Peripherals bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus
– Ethernet DMA bus
– USB OTG HS DMA bus
– LCD Controller DMA-bus
– Chrom-Art Accelerator™ (DMA2D) memory bus
• Eight bus slaves:
– the embedded Flash on AHB bus (for Flash read/write access, for code execution
and data access)
– Cortex®-M7 AHBS slave interface for DMAs data transfer on DTCM RAM only.
– Main internal SRAM1 (368 KB)
– Auxiliary internal SRAM2 (16 KB)
– AHB1peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals
– FMC
– Quad-SPI
2.1.1 Multi AHB BusMatrix
The multi AHB BusMatrix manages the access arbitration between masters. The arbitration
uses a round-robin algorithm.
It provides access from a master to a slave, enabling concurrent access and efficient
operation even when several high-speed peripherals work simultaneously.
The DTCM and ITCM RAMs (tightly coupled memories) are not part of the bus matrix.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific
AHB slave bus of the CPU.
The instruction TCM RAM is reserved only for CPU. it is accessed at CPU clock speed with
0 wait states. The architecture is shown in Figure 1.
2.1.2 AHB/APB bridges (APB)
The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between
the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.
=== System and memory overview RM0410 #73 ===
Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies,
and to Table 1 for the address mapping of AHB and APB peripherals.
After each device reset, all peripheral clocks are disabled (except for the SRAM, DTCM,
ITCM RAM and Flash memory interface). Before using a peripheral you have to enable its
clock in the RCC_AHBxENR or RCC_APBxENR register.
Note: When a 16- or an 8-bit access is performed on an APB register, the access is transformed
into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
2.1.3 CPU AXIM bus
This bus connects the Cortex®-M7 with FPU core to the multi-AHB Bus-Matrix through AXI
to AHB bridge. There are 4 AXI bus targets:
– CPU AXI bus access 1: The target of this AXI bus is the external memory FMC
containing code or data. For the NAND Bank mapped at address 0x8000 0000 to
0x8FFF FFFF, the MPU memory attribute for this space must be reconfigured by
software to Device.
– CPU AXI bus access 2: The target of this AXI bus is the external memory Quad-
SPI containing code or data.
– CPU AXI bus access 3: The target of this AXI bus is the internal SRAMs (SRAM1
and SRAM2) containing code or data.
– CPU AXI bus access 4: The target of this AXI bus is the embedded Flash mapped
on AXI interface containing code or data.
2.1.4 ITCM bus
This bus is used by the Cortex®-M7 and AHBS for instruction fetches and data access on
the embedded flash mapped on ITCM interface and instruction fetches and data access on
ITCM RAM.
2.1.5 DTCM bus
This bus is used by the Cortex®-M7 for data access on the DTCM RAM. It can be also used
for instruction fetches.
2.1.6 CPU AHBS bus
This bus connects the AHB Slave bus of the Cortex®-M7 to the BusMatrix. This bus is used
by DMAs and Peripherals DMAs for Data transfer on DTCM RAM only.
The ITCM bus is not accessible on AHBS. So the DMA data transfer to/from ITCM RAM is
not supported. For DMA transfer to/from Flash on ITCM interface, all the transfers are
forced through AHB bus
2.1.7 AHB peripheral bus
This bus connects the AHB Peripheral bus of the Cortex®-M7 to the BusMatrix. This bus is
used by the core to perform all data accesses to peripherals.
The target of this bus is the AHB1 peripherals including the APB peripherals and the AHB2
peripherals.
=== RM0410 System and memory overview #74 ===
2.1.8 DMA memory bus
This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7) internal Flash
memory and external memories through the FMC or Quad-SPI.
2.1.9 DMA peripheral bus
This bus connects the DMA peripheral master bus interface to the AHB-to-APB bridges or
the BusMatrix. This bus is used by the DMA to access peripherals or to perform memory-to-
memory transfers. The targets of this bus are the APB peripherals plus AHB peripherals and
data memories (internal SRAM1, SRAM2 and DTCM internal Flash memory and external
memories through the FMC or Quad-SPI) for DMA2.
2.1.10 Ethernet DMA bus
This bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by
the Ethernet DMA to load/store data to a memory. The targets of this bus are data
memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7)
internal Flash memory, and external memories through the FMC or Quad-SPI.
2.1.11 USB OTG HS DMA bus
This bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is
used by the USB OTG DMA to load/store data to a memory. The targets of this bus are data
memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7),
internal Flash memory, and external memories through the FMC or Quad-SPI.
2.1.12 LCD-TFT controller DMA bus
This bus connects the LCD controller DMA master interface to the BusMatrix. It is used by
the LCD-TFT DMA to load data from a memory. The targets of this bus are data memories:
internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7), external
memories through FMC or Quad-SPI, and internal Flash memory.
2.1.13 DMA2D bus
This bus connect the DMA2D master interface to the BusMatrix. This bus is used by the
DMA2D graphic Accelerator to load/store data to a memory. The targets of this bus are data
memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7),
external memories through FMC or Quad-SPI, and internal Flash memory.
=== RM0410 #75 ===
2.2 Memory organization
2.2.1 Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into 8 main blocks, of 512 Mbytes each.
=== RM0410 #76 ===
2.2.2 Memory map and register boundary addresses
Figure 2. Memory map
=== RM0410 #77 ===
All the memory map areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
refer to the following table.
The following table gives the boundary addresses of the peripherals available in the
devices.
Table 1. STM32F76xxx and STM32F77xxx register boundary addresses
+---------------------------+----------------------+------+------------------------------------------------+
| Boundary address | Peripheral | Bus | Register map |
+===========================+======================+======+================================================+
| 0xA000 1000 - 0xA0001FFF | QUADSPI Control | AHB3 | Section 14.5.14: QUADSPI register map on |
| | Register | | page 437 |
+---------------------------+----------------------+ +------------------------------------------------+
| 0xA000 0000 - 0xA000 0FFF | FMC control register | | Section 13.8: FMC register map on page 407 |
+---------------------------+----------------------+------+------------------------------------------------+
| 0x5006 0800 - 0x5006 0BFF | RNG | AHB2 | Section 22.8.4: RNG register map on page 770 |
+---------------------------+----------------------+ +------------------------------------------------+
| 0x5006 0400 - 0x5006 07FF | HASH | | Section 24.6.8: HASH register map on page 861 |
+---------------------------+----------------------+ +------------------------------------------------+
| 0x5006 0000 - 0x5006 03FF | CRYP | | Section 23.6.21: CRYP register map on page 837 |
+---------------------------+----------------------+ +------------------------------------------------+
| 0x5005 1000 - 0x5005 1FFF | JPEG | | Section 21.5.11: JPEG codec register map |
+---------------------------+----------------------+ +------------------------------------------------+
| 0x5005 0000 - 0x5005 03FF | DCMI | | Section 18.7.12: DCMI register map on page 589 |
+---------------------------+----------------------+ +------------------------------------------------+
| 0x5000 0000 - 0x5003 FFFF | USB OTG FS | | Section 41.15.61: OTG_FS/OTG_HS register map |
| | | | on page 1691 |
+---------------------------+----------------------+------+------------------------------------------------+
=== RM0410 #78 ===
Table 1. STM32F76xxx and STM32F77xxx register boundary addresses (continued)
+---------------------------+-------------------+------+------------------------------------------------+
| Boundary address | Peripheral | Bus | Register map |
+===========================+===================+======+================================================+
| 0x4004 0000 - 0x4007 FFFF | USB OTG HS | AHB1 | Section 41.15.61: OTG_FS/OTG_HS register map |
| | | | on page 1691 |
+---------------------------+-------------------+ +------------------------------------------------+
| 0x4002 B000 - 0x4002 BBFF | Chrom-ART (DMA2D) | | Section 9.5.21: DMA2D register map on page 311 |
+---------------------------+-------------------+ +------------------------------------------------+
| 0x4002 8000 - 0x4002 93FF | ETHERNET MAC | | Section 42.8.5: Ethernet register maps on |
| | | | page 1882 |
+---------------------------+-------------------+ +------------------------------------------------+
| 0x4002 6400 - 0x4002 67FF | DMA2 | | Section 8.5.11: DMA register map on page 276 |
+---------------------------+-------------------+ | |
| 0x4002 6000 - 0x4002 63FF | DMA1 | | |
+---------------------------+-------------------+ +------------------------------------------------+
| 0x4002 4000 - 0x4002 4FFF | BKPSRAM | | Section 5.3.27: RCC register map on page 217 |
+---------------------------+-------------------+ +------------------------------------------------+
| 0x4002 3C00 - 0x4002 3FFF | Flash interface | | Section 3.7.8: Flash interface register map on |
| | register | | page 116 |
+---------------------------+-------------------+ +------------------------------------------------+
| 0x4002 3800 - 0x4002 3BFF | RCC | | Section 5.3.27: RCC register map on page 217 |
+---------------------------+-------------------+ +------------------------------------------------+
| 0x4002 3000 - 0x4002 33FF | CRC | | Section 12.4.6: CRC register map on page 331 |
+---------------------------+-------------------+ +------------------------------------------------+
| 0x4002 2800 - 0x4002 2BFF | GPIOK | | Section 6.4.11: GPIO register map on page 235 |
+---------------------------+-------------------+ | |
| 0x4002 2400 - 0x4002 27FF | GPIOJ | | |
+---------------------------+-------------------+ +------------------------------------------------+
| 0x4002 2000 - 0x4002 23FF | GPIOI | | Section 6.4.11: GPIO register map on page 235 |
+---------------------------+-------------------+ | |
| 0x4002 1C00 - 0x4002 1FFF | GPIOH | | |
+---------------------------+-------------------+ | |
| 0x4002 1800 - 0x4002 1BFF | GPIOG | | |
+---------------------------+-------------------+ | |
| 0x4002 1400 - 0x4002 17FF | GPIOF | | |
+---------------------------+-------------------+ | |
| 0x4002 1000 - 0x4002 13FF | GPIOE | | |
+---------------------------+-------------------+ | |
| 0x4002 0C00 - 0x4002 0FFF | GPIOD | | |
+---------------------------+-------------------+ | |
| 0x4002 0800 - 0x4002 0BFF | GPIOC | | |
+---------------------------+-------------------+ | |
| 0x4002 0400 - 0x4002 07FF | GPIOB | | |
+---------------------------+-------------------+ | |
| 0x4002 0000 - 0x4002 03FF | GPIOA | | |
+---------------------------+-------------------+------+------------------------------------------------+
=== RM0410 #79 ===
Table 1. STM32F76xxx and STM32F77xxx register boundary addresses (continued)
+---------------------------+--------------------+------+--------------------------------------------------+
| Boundary address | Peripheral | Bus | Register map |
+===========================+====================+======+==================================================+
| 0x4001 7800 - 0x4001 7BFF | MDIOS | APB2 | Section 38.4.10: MDIOS register map on |
| | | | page 1470 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 7400 - 0x4001 77FF | DFSDM1 | | Section 17.8.16: DFSDM register map on |
| | | | page 555 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 6C00 - 0x4001 73FF | DSI Host | | Section 20.17: DSI Host register map on page 737 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 6800 - 0x4001 6BFF | LCD-TFT | | Section 19.7.26: LTDC register map on page 622 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 5C00 - 0x4001 5FFF | SAI2 | | Section 36.5.18: SAI register map on page 1422 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 5800 - 0x4001 5BFF | SAI1 | | Section 36.5.18: SAI register map on page 1422 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 5400 - 0x4001 57FF | SPI6 | | Section 35.9.10: SPI/I2S register map on |
+---------------------------+--------------------+ | page 1368 |
| 0x4001 5000 - 0x4001 53FF | SPI5 | | |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 4800 - 0x4001 4BFF | TIM11 | | Section 27.5.12: TIM10/TIM11/TIM13/TIM14 |
+---------------------------+--------------------+ | register map on page 1078 |
| 0x4001 4400 - 0x4001 47FF | TIM10 | | |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 4000 - 0x4001 43FF | TIM9 | | Section 27.4.13: TIM9/TIM12 register map on |
| | | | page 1068 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 3C00 - 0x4001 3FFF | EXTI | | Section 11.9.7: EXTI register map on page 325 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 3800 - 0x4001 3BFF | SYSCFG | | Section 7.2.9: SYSCFG register map on page 244 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 3400 - 0x4001 37FF | SPI4 | | Section 35.9.10: SPI/I2S register map on |
| | | | page 1368 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 3000 - 0x4001 33FF | SPI1 | | Section 35.9.10: SPI/I2S register map on |
| | | | page 1368 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 2C00 - 0x4001 2FFF | SDMMC1 | | Section 39.8.16: SDMMC register map on |
| | | | page 1529 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 2000 - 0x4001 23FF | ADC1 - ADC2 - ADC3 | | Section 15.13.18: ADC register map on page 483 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 1C00 - 0x4001 1FFF | SDMMC2 | | Section 39.8.16: SDMMC register map on |
| | | | page 1529 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 1400 - 0x4001 17FF | USART6 | | Section 34.8.12: USART register map on |
+---------------------------+--------------------+ | page 1307 |
| 0x4001 1000 - 0x4001 13FF | USART1 | | |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 0400 - 0x4001 07FF | TIM8 | | Section 25.4.27: TIM8 register map on page 958 |
+---------------------------+--------------------+ +--------------------------------------------------+
| 0x4001 0000 - 0x4001 03FF | TIM1 | | Section 25.4.26: TIM1 register map on page 955 |
+---------------------------+--------------------+------+--------------------------------------------------+
=== RM0410 #80 ===
Table 1. STM32F76xxx and STM32F77xxx register boundary addresses (continued)
+---------------------------+---------------------+------+-------------------------------------------------+
| Boundary address | Peripheral | Bus | Register map |
+===========================+=====================+======+=================================================+
| 0x4000 7C00 - 0x4000 7FFF | UART8 | APB1 | Section 34.8.12: USART register map on |
+---------------------------+---------------------+ | page 1307 |
| 0x4000 7800 - 0x4000 7BFF | UART7 | | |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 7400 - 0x4000 77FF | DAC | | Section 16.5.15: DAC register map on page 507 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 7000 - 0x4000 73FF | PWR | | Section 4.4.4: PWR power control register 2 |
| | | | (PWR_CSR2) on page 148 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 6C00 - 0x4000 6FFF | HDMI-CEC | | Section 43.7.7: HDMI-CEC register map on |
| | | | page 1904 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 6800 - 0x4000 6BFF | CAN2 | | Section 40.9.5: bxCAN register map on page 1573 |
+---------------------------+---------------------+ | |
| 0x4000 6400 - 0x4000 67FF | CAN1 | | |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 6000 - 0x4000 63FF | I2C4 | | Section 33.7.12: I2C register map on page 1239 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 5C00 - 0x4000 5FFF | I2C3 | | Section 33.7.12: I2C register map on page 1239 |
+---------------------------+---------------------+ | |
| 0x4000 5800 - 0x4000 5BFF | I2C2 | | |
+---------------------------+---------------------+ | |
| 0x4000 5400 - 0x4000 57FF | I2C1 | | |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 5000 - 0x4000 53FF | UART5 | | Section 34.8.12: USART register map on |
+---------------------------+---------------------+ | page 1307 |
| 0x4000 4C00 - 0x4000 4FFF | UART4 | | |
+---------------------------+---------------------+ | |
| 0x4000 4800 - 0x4000 4BFF | USART3 | | |
+---------------------------+---------------------+ | |
| 0x4000 4400 - 0x4000 47FF | USART2 | | |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 4000 - 0x4000 43FF | SPDIFRX | | Section 37.5.10: SPDIFRX interface register map |
| | | | on page 1456 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 3C00 - 0x4000 3FFF | SPI3 / I2S3 | | Section 35.9.10: SPI/I2S register map on |
+---------------------------+---------------------+ | page 1368 |
| 0x4000 3800 - 0x4000 3BFF | SPI2 / I2S2 | | |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 3400 - 0x4000 37FF | CAN3 | | Section 40.9.5: bxCAN register map on page 1573 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 3000 - 0x4000 33FF | IWDG | | Section 30.4.6: IWDG register map on page 1121 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 2C00 - 0x4000 2FFF | WWDG | | Section 31.4.4: WWDG register map on page 1128 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 2800 - 0x4000 2BFF | RTC & BKP Registers | | Section 32.6.21: RTC register map on page 1172 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 2400 - 0x4000 27FF | LPTIM1 | | Section 29.6.9: LPTIM register map on page 1112 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 2000 - 0x4000 23FF | TIM14 | | Section 27.5.12: TIM10/TIM11/TIM13/TIM14 |
+---------------------------+---------------------+ | register map on page 1078 |
| 0x4000 1C00 - 0x4000 1FFF | TIM13 | | |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 1800 - 0x4000 1BFF | TIM12 | | Section 27.4.13: TIM9/TIM12 register map on |
| | | | page 1068 |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 1400 - 0x4000 17FF | TIM7 | | Section 28.4.9: TIM6/TIM7 register map on |
+---------------------------+---------------------+ | page 1092 |
| 0x4000 1000 - 0x4000 13FF | TIM6 | | |
+---------------------------+---------------------+ +-------------------------------------------------+
| 0x4000 0C00 - 0x4000 0FFF | TIM5 | | Section 26.4.21: TIMx register map on page 1028 |
+---------------------------+---------------------+ | |
| 0x4000 0800 - 0x4000 0BFF | TIM4 | | |
+---------------------------+---------------------+ | |
| 0x4000 0400 - 0x4000 07FF | TIM3 | | |
+---------------------------+---------------------+ | |
| 0x4000 0000 - 0x4000 03FF | TIM2 | | |
+---------------------------+---------------------+------+-------------------------------------------------+
=== RM0410 #81 ===
2.3 Embedded SRAM
The STM32F76xxx and STM32F77xxx feature:
• System SRAM up to 512 Kbytes including Data TCM RAM 128 Kbytes
• Instruction RAM (ITCM-RAM) 16 Kbytes.
• 4 Kbytes of backup SRAM (see section 5.1.2: Battery backup domain)
The embedded SRAM is divided into up to four blocks:
• System SRAM:
– SRAM1 mapped at address 0x2002 0000 and accessible by all AHB masters from
AHB bus Matrix.
– SRAM2 mapped at address 0x2007 C000 and accessible by all AHB masters from
AHB bus Matrix.
– DTCM-RAM on TCM interface (Tightly Coupled Memory interface) mapped at
address 0x2000 0000 and accessible by all AHB masters from AHB bus Matrix but
through a specific AHB slave bus of the CPU.
• Instruction SRAM:
– Instruction RAM (ITCM-RAM) mapped at address 0x0000 0000 and accessible
only by CPU.
The SRAM1 and SRAM2 can be accessed as bytes, half-words (16 bits) or full words (32
bits). While DTCM and ITCM RAMs can be accessed as bytes, half-words (16 bits), full
words (32 bits) or double words (64 bits).
2.4 Flash memory overview
The Flash memory interface manages CPU AXI and TCM accesses to the Flash memory. It
implements the erase and program Flash memory operations and the read and write
protection mechanisms. It accelerates code execution with ART on TCM interface or L1-
Cache on AXIM interface.
The Flash memory is organized as follows:
• A main memory block divided into sectors.
• A second block:
– System memory from which the device boots in System memory boot mode
– 1024 OTP (one-time programmable) bytes for user data.
– Option bytes to configure read and write protection, BOR level, software/hardware
watchdog, boot memory base address and reset when the device is in Standby or
Stop mode.
Refer to Section 3: Embedded Flash memory (FLASH) for more details.
2.5 Boot configuration
In the STM32F76xxx and STM32F77xxx, two different boot areas can be selected through
the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
BOOT_ADD1 option bytes as shown in the Table 2.
=== RM0410 #82 ===
Table 2. Boot modes
+----------------------------+----------------------------------------------------------+
| Boot mode selection | Boot area |
+------+---------------------+ |
| BOOT | Boot address option | |
| | bytes | |
+------+---------------------+==========================================================+
| 0 | BOOT_ADD0[15:0] | Boot address defined by user option byte BOOT_ADD0[15:0] |
| | | ST programmed value: Flash on ITCM at 0x0020 0000 |
+------+---------------------+----------------------------------------------------------+
| 1 | BOOT_ADD1[15:0] | Boot address defined by user option byte BOOT_ADD1[15:0] |
| | | ST programmed value: System bootloader at 0x0010 0000 |
+------+---------------------+----------------------------------------------------------+
The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset
release. It is up to the user to set the BOOT pin after reset.
The BOOT pin is also resampled when the device exits the Standby mode. Consequently,
they must be kept in the required Boot mode configuration when the device is in the Standby
mode.
After startup delay, the selection of the boot area is done before releasing the processor
reset.
The BOOT_ADD0 and BOOT_ADD1 address option bytes allows to program any boot
memory address from 0x0000 0000 to 0x3FFF FFFF which includes:
• All Flash address space mapped on ITCM or AXIM interface
• All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
• The System memory bootloader
The BOOT_ADD0 / BOOT_ADD1 option bytes can be modified after reset in order to boot
from any other boot address after next reset.
If the programmed boot memory address is out of the memory mapped area or a reserved
area, the default boot fetch address is programmed as follows:
– Boot address 0: ITCM-FLASH at 0x0020 0000
– Boot address 1: ITCM-RAM at 0x0000 0000
When flash level 2 protection is enabled, only boot from Flash (on ITCM or AXIM interface)
or system bootloader will be available. If the already programmed boot address in the
BOOT_ADD0 and/or BOOT_ADD1 option bytes is out of the memory range or RAM
address (on ITCM or AXIM) the default fetch will be forced from Flash on ITCM interface at
address 0x00200000.
When the device is in Dual bank mode (nDBANK =0) the application software can either
boot from bank 1 or from bank 2. By default Dual boot is desactivated.
To select boot from the Flash memory bank 2, program the nDBOOT bit in the user option
bytes. When this bit is reset (nDBOOT =0) and the BOOT pin selects an address in the
Flash memory range, the device boots from system memory, and the bootloader jumps to
execute the user application programmed in the Flask memory bank 2. For further details,
please refer to the application note (AN2606).
Embedded bootloader
The embedded bootloader code is located in the system memory. It is programmed by ST
during production. For full information, refer to the application note (AN2606) STM32
microcontroller system memory boot mode.
=== RM0410 #83 ===
By default, when the boot from system bootloader is selected, the code is executed from
TCM interface. It could be executed from AXIM interface by reprogramming the
BOOT_ADDx address option bytes to 0x1FF0 0000.
=== RM0410 Embedded Flash memory (FLASH) #84 ===
3 Embedded Flash memory (FLASH)
3.1 Introduction
The Flash memory interface manages Cortex®-M7 AXI and TCM accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines on ITCM interface (ART Accelerator™).
3.2 Flash main features
• Flash memory read operations with two data width modes supported:
– Single bank mode nDBANK=1: read access of 256 bits
– Dual bank mode nDBANK=0: read access of 128 bits
• Flash memory program/erase operations
• Read / write protections
• Read While Write (RWW) (only possible in dual bank mode nDBANK=0)
• Dual Boot mode (only possible in dual bank mode nDBANK=0)
• ART Accelerator™: 64 cache lines of 128/256 bits on ITCM interface (depending on
read access width)
• Prefetch on TCM instruction code
Figure 3 shows the Flash memory interface connection inside the system architecture.
=== Embedded Flash memory (FLASH) RM0410 #85 ===
Figure 3. Flash memory interface connection inside system architecture
(STM32F76xxx and STM32F77xxx)
=== RM0410 Embedded Flash memory (FLASH) #86 ===
3.3 Flash functional description
3.3.1 Flash memory organization
The Flash memory has the following main features:
• Capacity up to 2 Mbytes, in single bank mode (read width 256 bits) or in dual bank
mode (read width 128 bits)
• Supports dual boot mode thanks to nDBOOT option bit (only in dual bank mode
nDBANK=0)
• 256 bits wide data read in single bank mode or 128 bits wide data read in dual bank
configuration
• Byte, half-word, word and double word write
• Sector, mass erase and bank mass erase (only in dual bank mode)
The Flash memory is organized as follows:
• Main memory organization depends on dual bank configuration bit:
– When the dual bank mode is disabled (nDBANK bit is set), the main memory block
is divided into 4 sectors of 32 Kbytes, 1 Sector of 128 Kbytes, and 7 sectors of 256
Kbytes
– In dual bank mode (nDBANK bit is reset), the main memory is divided into two
banks of 1 Mbyte. Each 1 Mbyte bank is composed of 4 sectors of 16 Kbytes, 1
Sector of 64 Kbytes and 7 sectors of 128 Kbytes
- If nDBANK=1, Size of main memory block: 4 sectors of 32 KBytes, 1 sector of
128 KBytes, 7 sectors of 256 KBytes (reference to memory organization)
- If nDBANK=0, Each 1MB banks is composed of: 4 sectors of 16 KBytes, 1 sector
of 64 KBytes, 7 sectors of 128 KBytes (reference to memory organization)
• Dual bank organization on 1 Mbyte devices
The dual bank feature on 1 Mbyte devices is available. it is enabled by setting the
nDBANK option bit to 0.
To obtain a dual bank Flash memory, the last 512 Kbytes of the single bank (sectors
[8:11]) are re-structured in the same way as the first 512 Kbytes.
The sector numbering of dual bank memory organization is different from the single
bank: the single bank memory contains 12 sectors whereas the dual bank memory
contains 16 sectors (see Table 6).
For erase operation, the right sector numbering must be considered according to
nDBANK option bit.
– When the nDBANK bit is set (single bank mode), the erase operation must be
performed on the default sector number.
– When the nDBANK bit is reset, to perform an erase operation on bank 2, the
sector number must be programmed (sector number from 12 to 19). Refer to
FLASH_CR register for SNB (Sector number) configuration.
Refer to Table 5: 1 Mbyte Flash memory single bank organization (256 bits read
width) and Table 6: 1 Mbyte Flash memory dual bank organization (128 bits read
=== Embedded Flash memory (FLASH) RM0410 #87 ===
width) for details on 1 Mbyte single bank and 1 Mbyte dual bank organizations.
• Information blocks containing:
– System memory from which the device boots in System memory boot mode
– 1024 OTP (one-time programmable) for user data
– The OTP area contains 16 additional bytes used to lock the corresponding OTP
data block.
– Option bytes to configure read and write protection, BOR level, watchdog, boot
memory base address, software/hardware and reset when the device is in
Standby or Stop mode.
On 1 Mbyte devices the main memory block is divided into 4 sectors of 32 Kbytes, 1 sector
of 128 Kbytes, and 3 sectors of 256 Kbytes. The dual bank feature is also available.
To obtain a dual bank Flash memory, the main memory block is re-structured in the a way
that the first and last 512 Kbytes of each bank has the same structure.
The sector numbering of dual bank memory organization is different from the single bank:
the single bank memory contains 8 continuous sector numbers whereas the dual bank
memory contains 16 sectors with discontinuity on sector numbering for each 512 Kbytes
(see Table 5: 1 Mbyte Flash memory single bank organization (256 bits read width)).
For erase operation, the right sector numbering must be considered according to the dual
bank nDBANK option bit.
• When the nDBANK bit is set (single bank configuration), the erase operation must be
performed on the default sector number.
• When the nDBANK bit is reset (dual bank configuration), to perform an erase operation
on bank 2, the sector number must be programmed (sector number from 12 to 19).
Refer to FLASH_CR register for SNB (Sector number) configuration.
The embedded Flash has three main interfaces:
• 64-bits ITCM interface:
– It is connected to the ITCM bus of Cortex-M7 and used for instruction execution
and data read access.
– Write accesses are not supported on ITCM interface
– Supports a unified 64 cache lines (ART accelerator). The cache line size depends
on nDBANK option bit, 256 bits width when in single bank configuration and 128
bits width in dual bank configuration
• 64-bits AHB interface:
– It is connected to the AXI bus of Cortex-M7 through the AHB bus matrix and used
for code execution, read and write accesses.
– DMAs and peripherals DMAs data transfer on Flash are done through the AHB
interface whatever the addressed flash interface TCM or AHB.
• 32-bits AHB register interface:
– It is used for control and status register accesses.
The main memory and information block organization is shown in the following tables:
=== RM0410 Embedded Flash memory (FLASH) #88 ===
Table 3. 2 Mbytes Flash memory single bank organization (256 bits read width)
+-------------------+---------------+---------------------------+---------------------------+------------+
| Block | Name | Bloc base address on AXIM | Block base address | Sector |
| | | interface | on ICTM interface | size |
+===================+===============+===========================+===========================+============+
| Main memory | Sector 0 | 0x0800 0000 - 0x0800 7FFF | 0x0020 0000 - 0x0020 7FFF | 32 KB |
| block +---------------+---------------------------+---------------------------+------------+
| | Sector 1 | 0x0800 8000 - 0x0800 FFFF | 0x0020 8000 - 0x0020 FFFF | 32 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 2 | 0x0801 0000 - 0x0801 7FFF | 0x0021 0000 - 0x0021 7FFF | 32 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 3 | 0x0801 8000 - 0x0801 FFFF | 0x0021 8000 - 0x0021 FFFF | 32 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 4 | 0x0802 0000 - 0x0803 FFFF | 0x0022 0000 - 0x0023 FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 5 | 0x0804 0000 - 0x0807 FFFF | 0x0024 0000 - 0x0027 FFFF | 256 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 6 | 0x0808 0000 - 0x080B FFFF | 0x0028 0000 - 0x002B FFFF | 256 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 7 | 0x080C 0000 - 0x080F FFFF | 0x002C 0000 - 0x002F FFFF | 256 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 8 | 0x0810 0000 - 0x0813 FFFF | 0x0030 0000 - 0x0033 FFFF | 256 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 9 | 0x0814 0000 - 0x0817 FFFF | 0x00340000 - 0x0037 FFFF | 256 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 10 | 0x0818 0000 - 0x081B FFFF | 0x0038 0000 - 0x003B FFFF | 256 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 11 | 0x081C 0000 - 0x081F FFFF | 0x003C 0000 - 0x003F FFFF | 256 KB |
+-------------------+---------------+---------------------------+---------------------------+------------+
| Information block | System memory | 0x1FF0 0000 - 0x1FF0 EDBF | 0x0010 0000 - 0x0010 EDBF | 60 Kbytes |
| +---------------+---------------------------+---------------------------+------------+
| | OTP | 0x1FF0 F000 - 0x1FF0 F41F | 0x0010 F000 - 0x0010 F41F | 1024 bytes |
| +---------------+---------------------------+---------------------------+------------+
| | Option bytes | 0x1FFF 0000 - 0x1FFF 001F | - | 32 bytes |
+-------------------+---------------+---------------------------+---------------------------+------------+
Table 4. 2 Mbytes Flash memory dual bank organization (128 bits read width)
+--------+-----------+---------------------------+---------------------------+--------+
| Block | Name | Bloc base address on AXIM | Block base address | Sector |
| | | interface | on ICTM interface | size |
+========+===========+===========================+===========================+========+
| Bank 1 | Sector 0 | 0x0800 0000 - 0x0800 3FFF | 0x0020 0000 - 0x0020 3FFF | 16 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 1 | 0x0800 4000 - 0x0800 7FFF | 0x0020 4000 - 0x0020 7FFF | 16 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 2 | 0x0800 8000 - 0x0800 BFFF | 0x0020 8000 - 0x0020 BFFF | 16 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 3 | 0x0800 C000 - 0x0800 FFFF | 0x0020 C000 - 0x0020 FFFF | 16 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 4 | 0x0801 0000 - 0x0801 FFFF | 0x0021 0000 - 0x0021 FFFF | 64 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 5 | 0x0802 0000 - 0x0803 FFFF | 0x0022 0000 - 0x0023 FFFF | 128 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 6 | 0x0804 0000 - 0x0805 FFFF | 0x0024 0000 - 0x0025 FFFF | 128 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 7 | 0x0806 0000 - 0x0807 FFFF | 0x0026 0000 - 0x0027 FFFF | 128 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 8 | 0x0808 0000 - 0x0809 FFFF | 0x0028 0000 - 0x0029 FFFF | 128 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 9 | 0x080A 0000 - 0x080B FFFF | 0x002A 0000 - 0x002B FFFF | 128 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 10 | 0x080C 0000 - 0x080E FFFF | 0x002C 0000 - 0x002E FFFF | 128 KB |
| +-----------+---------------------------+---------------------------+--------+
| | Sector 11 | 0x080E 0000 - 0x080F FFFF | 0x002E 0000 - 0x002F FFFF | 128 KB |
+--------+-----------+---------------------------+---------------------------+--------+
=== Embedded Flash memory (FLASH) RM0410 #89 ===
Table 4. 2 Mbytes Flash memory dual bank organization (128 bits read width) (continued)
+-------------------+---------------+---------------------------+---------------------------+------------+
| Block | Name | Bloc base address on AXIM | Block base address | Sector |
| | | interface | on ICTM interface | size |
+===================+===============+===========================+===========================+============+
| Bank 2 | Sector 12 | 0x0810 0000 - 0x0810 3FFF | 0x0030 0000 - 0x0030 3FFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 13 | 0x0810 4000 - 0x0810 7FFF | 0x0030 4000 - 0x0030 7FFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 14 | 0x0810 8000 - 0x0810 BFFF | 0x0030 8000 - 0x0030 BFFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 15 | 0x0810 C000 - 0x0810 FFFF | 0x0030 C000 - 0x0030 FFFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 16 | 0x0811 0000 - 0x0811 FFFF | 0x0031 0000 - 0x0031 FFFF | 64 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 17 | 0x0812 0000 - 0x0813 FFFF | 0x0032 0000 - 0x0033 FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 18 | 0x0814 0000 - 0x0815 FFFF | 0x0034 0000 - 0x0035 FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 19 | 0x0816 0000 - 0x0817 FFFF | 0x0036 0000 - 0x0037 FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 20 | 0x0818 0000 - 0x0819 FFFF | 0x0038 0000 - 0x0039 FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 21 | 0x081A 0000 - 0x081B FFFF | 0x003A 0000 - 0x003B FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 22 | 0x081C 0000 - 0x081E FFFF | 0x003C 0000 - 0x003E FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 23 | 0x081E 0000 - 0x081F FFFF | 0x003E 0000 - 0x003F FFFF | 128 KB |
+-------------------+---------------+---------------------------+---------------------------+------------+
| Information block | System memory | 0x1FF0 0000 - 0x1FF0 EDBF | 0x0010 0000 - 0x0010 EDBF | 60 Kbytes |
| +---------------+---------------------------+---------------------------+------------+
| | OTP | 0x1FF0 F000 - 0x1FF0 F41F | 0x0010 F000 - 0x0010 F41F | 1024 bytes |
| +---------------+---------------------------+---------------------------+------------+
| | Option bytes | 0x1FFF 0000 - 0x1FFF 001F | - | 32 bytes |
+-------------------+---------------+---------------------------+---------------------------+------------+
Table 5. 1 Mbyte Flash memory single bank organization (256 bits read width)
+-------------------+---------------+---------------------------+---------------------------+------------+
| Block | Name | Bloc base address on AXIM | Block base address | Sector |
| | | interface | on ICTM interface | size |
+===================+===============+===========================+===========================+============+
| Main memory | Sector 0 | 0x0800 0000 - 0x0800 7FFF | 0x0020 0000 - 0x0020 7FFF | 32 KB |
| block +---------------+---------------------------+---------------------------+------------+
| | Sector 1 | 0x0800 8000 - 0x0800 FFFF | 0x0020 8000 - 0x0020 FFFF | 32 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 2 | 0x0801 0000 - 0x0801 7FFF | 0x0021 0000 - 0x0021 7FFF | 32 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 3 | 0x0801 8000 - 0x0801 FFFF | 0x0021 8000 - 0x0021 FFFF | 32 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 4 | 0x0802 0000 - 0x0803 FFFF | 0x0022 0000 - 0x0023 FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 5 | 0x0804 0000 - 0x0807 FFFF | 0x0024 0000 - 0x0027 FFFF | 256 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 6 | 0x0808 0000 - 0x080B FFFF | 0x0028 0000 - 0x002B FFFF | 256 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 7 | 0x080C 0000 - 0x080F FFFF | 0x002C 0000 - 0x002F FFFF | 256 KB |
+-------------------+---------------+---------------------------+---------------------------+------------+
| Information block | System memory | 0x1FF0 0000 - 0x1FF0 EDBF | 0x0010 0000 - 0x0010 EDBF | 60 Kbytes |
| +---------------+---------------------------+---------------------------+------------+
| | OTP | 0x1FF0 F000 - 0x1FF0 F41F | 0x0010 F000 - 0x0010 F41F | 1024 bytes |
| +---------------+---------------------------+---------------------------+------------+
| | Option bytes | 0x1FFF 0000 - 0x1FFF 001F | - | 32 bytes |
+-------------------+---------------+---------------------------+---------------------------+------------+
=== RM0410 Embedded Flash memory (FLASH) #90 ===
Table 6. 1 Mbyte Flash memory dual bank organization (128 bits read width)
+-------------------+---------------+---------------------------+---------------------------+------------+
| Block | Name | Bloc base address on AXIM | Block base address | Sector |
| | | interface | on ICTM interface | size |
+===================+===============+===========================+===========================+============+
| Bank1 | Sector 0 | 0x0800 0000 - 0x0800 3FFF | 0x0020 0000 - 0x0020 3FFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 1 | 0x0800 4000 - 0x0800 7FFF | 0x0020 4000 - 0x0020 7FFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 2 | 0x0800 8000 - 0x0800 BFFF | 0x0020 8000 - 0x0020 BFFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 3 | 0x0800 C000 - 0x0800 FFFF | 0x0020 C000 - 0x0020 FFFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 4 | 0x0801 0000 - 0x0801 FFFF | 0x0021 0000 - 0x0021 FFFF | 64 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 5 | 0x0802 0000 - 0x0803 FFFF | 0x0022 0000 - 0x0023 FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 6 | 0x0804 0000 - 0x0805 FFFF | 0x0024 0000 - 0x0025 FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 7 | 0x0806 0000 - 0x0807 FFFF | 0x0026 0000 - 0x0027 FFFF | 128 KB |
+-------------------+---------------+---------------------------+---------------------------+------------+
| Bank 2 | Sector 12 | 0x0808 0000 - 0x0808 3FFF | 0x0028 0000 - 0x0028 3FFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 13 | 0x0808 4000 - 0x0808 7FFF | 0x0028 4000 - 0x0028 7FFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 14 | 0x0808 8000 - 0x0808 BFFF | 0x0028 8000 - 0x0028 BFFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 15 | 0x0808 C000 - 0x0808 FFFF | 0x0028 C000 - 0x0028 FFFF | 16 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 16 | 0x0809 0000 - 0x0809 FFFF | 0x0029 0000 - 0x0029 FFFF | 64 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 17 | 0x080A 0000 - 0x080B FFFF | 0x002A 0000 - 0x002B FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 18 | 0x080C 0000 - 0x080E FFFF | 0x002C 0000 - 0x002E FFFF | 128 KB |
| +---------------+---------------------------+---------------------------+------------+
| | Sector 19 | 0x080E 0000 - 0x080F FFFF | 0x002E 0000 - 0x002F FFFF | 128 KB |
+-------------------+---------------+---------------------------+---------------------------+------------+
| Information block | System memory | 0x1FF0 0000 - 0x1FF0 EDBF | 0x0010 0000 - 0x0010 EDBF | 60 Kbytes |
| +---------------+---------------------------+---------------------------+------------+
| | OTP | 0x1FF0 F000 - 0x1FF0 F41F | 0x0010 F000 - 0x0010 F41F | 1024 bytes |
| +---------------+---------------------------+---------------------------+------------+
| | Option bytes | 0x1FFF 0000 - 0x1FFF 001F | - | 32 bytes |
+-------------------+---------------+---------------------------+---------------------------+------------+
3.3.2 Read access latency
To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the supply voltage of the device.
The correspondence between wait states and CPU clock frequency is given in Table 13 and
Table 7.
Note: - When VOS[1:0] = '0x01', the maximum value of fHCLK is 144 MHz.
- When VOS[1:0] = '0x10', the maximum value of fHCLK is 168 MHz. It can be extended to
180 MHz by activating the over-drive mode.
- When VOS[1:0] = '0x11, the maximum value of fHCLK is 180 MHz. It can be extended to
216 MHz by activating the over-drive mode.
- The over-drive mode is not available when VDD ranges from 1.8 to 2.1 V.
Refer to Section 4.1.6: Voltage regulator for details on how to activate the over-drive mode.
=== Embedded Flash memory (FLASH) RM0410 #91 ===
Table 7. Number of wait states according to CPU clock (HCLK) frequency
+----------------------+---------------------------------------------------------------------------+
| Wait states (WS) | HCLK (MHz) |
| (LATENCY) +------------------+------------------+------------------+------------------+
| | Voltage range | Voltage range | Voltage range | Voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
+======================+------------------+------------------+------------------+------------------+
| 0 WS (1 CPU cycle) | 0 < HCLK ≤ 30 | 0 < HCLK ≤ 24 | 0 < HCLK ≤ 22 | 0 < HCLK ≤ 20 |
+----------------------+------------------+------------------+------------------+------------------+
| 1 WS (2 CPU cycles) | 30 < HCLK ≤ 60 | 24 < HCLK ≤ 48 | 22 < HCLK ≤ 44 | 20 < HCLK ≤ 40 |
+----------------------+------------------+------------------+------------------+------------------+
| 2 WS (3 CPU cycles) | 60 < HCLK ≤ 90 | 48 < HCLK ≤ 72 | 44 < HCLK ≤ 66 | 40 < HCLK ≤ 60 |
+----------------------+------------------+------------------+------------------+------------------+
| 3 WS (4 CPU cycles) | 90 < HCLK ≤ 120 | 72 < HCLK ≤ 96 | 66 < HCLK ≤ 88 | 60 < HCLK ≤ 80 |
+----------------------+------------------+------------------+------------------+------------------+
| 4 WS (5 CPU cycles) | 120 < HCLK ≤ 150 | 96 < HCLK ≤ 120 | 88 < HCLK ≤ 110 | 80 < HCLK ≤ 100 |
+----------------------+------------------+------------------+------------------+------------------+
| 5 WS (6 CPU cycles) | 150 < HCLK ≤ 180 | 120 < HCLK ≤ 144 | 110 < HCLK ≤ 132 | 100 < HCLK ≤ 120 |
+----------------------+------------------+------------------+------------------+------------------+
| 6 WS (7 CPU cycles) | 180 < HCLK ≤ 210 | 144 <HCLK ≤ 168 | 132 < HCLK ≤ 154 | 120 < HCLK ≤ 140 |
+----------------------+------------------+------------------+------------------+------------------+
| 7 WS (8 CPU cycles) | 210 < HCLK ≤ 216 | 168 < HCLK ≤ 192 | 154 < HCLK ≤ 176 | 140 < HCLK ≤ 160 |
+----------------------+------------------+------------------+------------------+------------------+
| 8 WS (9 CPU cycles) | - | 192 < HCLK ≤ 216 | 176 < HCLK ≤ 198 | 160 < HCLK ≤ 180 |
+----------------------+------------------+------------------+------------------+------------------+
| 9 WS (10 CPU cycles) | - | - | 198 < HCLK ≤ 216 | - |
+----------------------+------------------+------------------+------------------+------------------+
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of
wait states to access the Flash memory with the CPU frequency.
Increasing the CPU frequency
1. Program the new number of wait states to the LATENCY bits in the FLASH_ACR
register
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register
3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Decreasing the CPU frequency
1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register
4. Program the new number of wait states to the LATENCY bits in FLASH_ACR
5. Check that the new number of wait states is used to access the Flash memory by
reading the FLASH_ACR register
Note: A change in CPU clock configuration or wait state (WS) configuration may not be effective
straight away. To make sure that the current CPU clock frequency is the one you have
=== RM0410 Embedded Flash memory (FLASH) #92 ===
configured, you can check the AHB prescaler factor and clock source status values. To
make sure that the number of WS you have programmed is effective, you can read the
FLASH_ACR register.
Instruction prefetch
Depending on Flash dual bank mode configuration, each flash read operation provides:
In case of single bank mode (nDBANK option bit is set) 256 bits representing 8 instructions
of 32 bits to 16 instructions of 16 bits according to the program launched. So, in case of
sequential code, at least 8 CPU cycles are needed to execute the previous instruction line
read.
When in dual bank mode (nDBANK option bit is reset) 128 bits representing 4 instructions of
32 bits to 8 instructions of 16 bits according to the program launched. So, in case of
sequential code, at least 4 CPU cycles are needed to execute the previous instruction line
read. The prefetch on ITCM bus allows to read the sequential next line of instructions in the
flash while the current instruction line is requested by the CPU. The prefetch can be enabled
by setting the PRFTEN bit of the FLASH_ACR register. This feature is useful if at least one
Wait State is needed to access the flash. When the code is not sequential (branch), the
instruction may not be present neither in the current instruction line used nor in the
prefetched instruction line. In this case (miss), the penalty in term of number of cycles is at
least equal to the number of Wait States.
Adaptive real-time memory accelerator (ART Accelerator™)
The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard Arm® Cortex®-M7 with FPU processors. It balances the inherent
performance advantage of the Arm® Cortex®-M7 with FPU over Flash memory
technologies, which normally requires the processor to wait for the Flash memory at higher
operating frequencies.
To release the processor full performance, the accelerator implements a unified cache of an
instruction and branch cache which increases program execution speed from the Flash
memory. Based on CoreMark benchmark, the performance achieved thanks to the ART
accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU
frequency up to 216 MHz.
The ART accelerator is available only for flash access on ITCM interface.
To limit the time lost due to jumps, it is possible to retain 64 lines of 256 bits (when in single
bank mode configuration nDBANK=1 or 128 bits in dual bank configuration with
nDBANK=0) in the ART accelerator. This feature can be enabled by setting the ARTEN bit
of the FLASH_CR register. The ART Accelerator is unified, it contains instruction as well as
data literal pools. Each time a miss occurs (requested data not present in the current data
line used or in the instruction cache memory), the read line is copied in the instruction cache
memory of ART. If a data contained in the instruction cache memory is requested by the
CPU, the data is provided without inserting delay. Once all the cache memory lines are
filled, the LRU (Least Recently Used) policy is used to determine the line to replace in the
memory cache. This feature is particularly useful in case of code containing loops.
Note: Data in user configuration sector are not cacheable.
=== Embedded Flash memory (FLASH) RM0410 #93 ===
3.3.3 Flash program and erase operations
For any Flash memory program operation (erase or program), the CPU clock frequency
(HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a
device reset occurs during a Flash memory operation.
Any attempt to read the Flash memory while it is being written or erased, causes the bus to
stall. Read operations are processed correctly once the program operation has completed.
This means that code or data fetches cannot be performed while a write/erase operation is
ongoing.
3.3.4 Unlocking the Flash control register
After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the
Flash memory against possible unwanted operations due, for example, to electric
disturbances. The following sequence is used to unlock this register:
1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
2. Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)
Any wrong sequence will return a bus error and lock up the FLASH_CR register until the
next reset.
The FLASH_CR register can be locked again by software by setting the LOCK bit in the
FLASH_CR register.
Note: The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR
register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall
until the BSY bit is cleared.
3.3.5 Program/erase parallelism
The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It
represents the number of bytes to be programmed each time a write operation occurs to the
Flash memory. PSIZE is limited by the supply voltage and by whether the external VPP
supply is used or not. It must therefore be correctly configured in the FLASH_CR register
before any programming/erasing operation.
A Flash memory erase operation can only be performed by sector, bank or for the whole
Flash memory (mass erase). The erase time depends on PSIZE programmed value. For
more details on the erase time, refer to the electrical characteristics section of the device
datasheet.
Table 8 provides the correct PSIZE values.
Table 8. Program/erase parallelism
+------------------+---------------------------+---------------+---------------+---------------+---------------+
| | Voltage range 2.7 - 3.6 V | Voltage range | Voltage range | Voltage range | Voltage range |
| | with External VPP | 2.7 - 3.6 V | 2.4 - 2.7 V | 2.1 - 2.4 V | 1.8 V - 2.1 V |
+==================+===========================+===============+===============+===============+===============+
| Parallelism size | x64 | x32 | x16 | x8 |
+------------------+---------------------------+---------------+-------------------------------+---------------+
| PSIZE(1:0) | 11 | 10 | 01 | 00 |
+------------------+---------------------------+---------------+-------------------------------+---------------+
=== RM0410 Embedded Flash memory (FLASH) #94 ===
Note: Any program or erase operation started with inconsistent program parallelism/voltage range
settings may lead to unpredicted results. Even if a subsequent read operation indicates that
the logical value was effectively written to the memory, this value may not be retained.
To use VPP, an external high-voltage supply (between 8 and 9 V) must be applied to the VPP
pad. The external supply must be able to sustain this voltage range even if the DC
consumption exceeds 10 mA. It is advised to limit the use of VPP to initial programming on
the factory line. The VPP supply must not be applied for more than an hour, otherwise the
Flash memory might be damaged.
3.3.6 Switching from single bank to dual bank configuration
It is possible to use main Flash either in single bank mode (256 bits read width) or dual bank
mode (128 bits read width) thanks to nDBANK option bit. However, it is highly
recommended to use the following sequence when switching from a mode to an other.
Activating dual bank mode (switching from nDBANK=1 to nDBANK=0)
When switching from one Flash mode to another (single to dual Bank) it is recommended to
execute code from SRAM or use bootloader. To avoid reading corrupted data from Flash
when the memory organization is changed any access (CPU or DMAs) to Flash memory
should be avoided before reprogramming.
1. Depending on execution path:
If ITCM path is used for code execution:
a) Disable ART accelerator and/or prefetch if they are enabled (for ART accelerator
reset PRFTEN and ARTEN bits in FLASH_ACR register
b) Flush ART accelerator if it was ON (set then reset ARTCRST bit in FLASH_ACR
register)
If AXIM path is used for code execution Disable and Clean Cache (CPU internal caches
clean and invalidation is needed).
2. Change nDBANK option bit value from 0 to 1 and reset all write protection (refer to
Section 3.4.2: Option bytes programming)
Note: The memory organization is changed and previously data in Flash memory is corrupted.
3. Program new application:
a) Erase needed memory (Sectors, or Mass erase)
b) Reprogram the Flash memory
c) If needed set write protection following write protection schema (refer to
Section 3.5.2: Write protections)
-> the new software is ready to be run using bank configuration
De-activating dual bank mode (switching from nDBANK=0 to nDBANK=1)
When switching from one Flash mode to another (dual to single Bank) it is recommended to
execute code from SRAM or use bootloader. To avoid reading corrupted data from Flash
when memory organization is changed any access (CPU or DMAs) to Flash memory should
be avoided before reprogramming.
=== Embedded Flash memory (FLASH) RM0410 #95 ===
1. Depending on execution path:
If ITCM path is used for code execution:
a) Disable ART accelerator and/or prefetch if they are enabled (for ART accelerator
reset PRFTEN and ARTEN bits in FLASH_ACR register
b) Flush ART accelerator if it was ON (set then reset ARTCRST bit in FLASH_ACR
register)
If AXIM path is used for code execution Disable and Clean Cache (CPU internal caches
clean and invalidation is needed)
2. Change nDBANK option bit value from 0 to 1 and reset all write protection (refer to
Section 3.4.2: Option bytes programming)
Note: The memory organization is changed and previously data in Flash memory is corrupted.
3. Program new application:
a) Erase needed memory (Sectors, or Mass erase)
b) Reprogram the Flash memory
c) If needed set write protection following write protection schema (refer to
Section 3.5.2: Write protections)
-> The new software is ready to be run using single bank configuration
3.3.7 Flash erase sequences
The Flash memory erase operation can be performed at sector level, at bank level (bank
mass erase when dual bank mode is enabled nDBANK=0) or on the whole Flash memory
(Mass Erase). Mass Erase does not affect the OTP sector or the configuration sector.
Sector Erase
To erase a sector, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2. Set the SER bit and select the sector out of the 8 in the main memory block) you wish
to erase (SNB) in the FLASH_CR register
3. Set the STRT bit in the FLASH_CR register
4. Wait for the BSY bit to be cleared
Bank Mass Erase (available only in dual bank mode when nDBANK=0)
To perform mass erase on Bank 1 or Bank 2, the procedure below should be followed:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2. Set accordingly MER/MER1 OR MER2 bit in the FLASH_CR register
3. Set the STRT bit in the FLASH_CR register
4. Wait for the BSY bit to be reset
5. Reset accordingly MER/MER1 OR MER2 bit in the FLASH_CR register
=== RM0410 Embedded Flash memory (FLASH) #96 ===
Mass Erase
To perform Mass Erase, the following sequence is recommended depending on nDBANK
option bit:
• When dual bank mode is active (nDBANK=0) :
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2. Set the MER/MER1 AND MER2 bit in the FLASH_CR register
3. Set the STRT bit in the FLASH_CR register
4. Wait for the BSY bit to be reset
5. Reset the MER/MER1 AND MER2 bit in the FLASH_CR register
• When single bank mode is active (nDBANK=1) :
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2. Set the MER/MER1 bit in the FLASH_CR register
3. Set the STRT bit in the FLASH_CR register
4. Wait for the BSY bit to be cleared If MERx and SER bits are both set in the FLASH_CR
register, mass erase is performed.
Note: If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.
If both MERx and SER bits are reset and the STRT bit is set, an unpredictable behavior may
occur without generating any error flag. This condition should be forbidden.
Note: When setting the STRT bit in the FLASH_CR register and before polling the BSY bit to be
cleared, the software can issue a DSB instruction to guarantee the completion of a previous
access to FLASH_CR register.
3.3.8 Flash programming sequences
Standard programming
The Flash memory programming sequence is as follows:
1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2. Set the PG bit in the FLASH_CR register
3. Perform the data write operation(s) to the desired memory address (inside main
memory block or OTP area):
– Byte access in case of x8 parallelism
– Half-word access in case of x16 parallelism
– Word access in case of x32 parallelism
– Double word access in case of x64 parallelism
4. Wait for the BSY bit to be cleared.
Note: Successive write operations are possible without the need of an erase operation when
changing bits from ‘1’ to ‘0’. Writing ‘1’ requires a Flash memory erase operation.
If an erase and a program operation are requested simultaneously, the erase operation is
performed first.
=== Embedded Flash memory (FLASH) RM0410 #97 ===
Note: After performing a data write operation and before polling the BSY bit to be cleared, the
software can issue a DSB instruction to guarantee the completion of a previous data write
operation.
Programming errors
In case of error, the Flash operation (programming or erasing) is aborted with one of the
following errors:
• PGAERR: Alignment Programming error
It is not allowed to program data to the Flash memory that would cross the 128-bit row
boundary. In such a case, the write operation is not performed and the program
alignment error flag (PGAERR) is set in the FLASH_SR register.
• PGEPRR: Programming parallelism error
The write access type (byte, half-word, word or double word) must correspond to the
type of parallelism chosen (x8, x16, x32 or x64). If not, the write operation is not
performed and the program parallelism error flag (PGPERR) is set in the FLASH_SR
register.
• ERSERR: Erase sequence error
When an erase operation to the flash is performed by the code while the control
register has not been correctly configured, the ERSERR error flag is set
• WRPERR: Write Protection Error
WRPERR is set if one of the following conditions occurs:
– Attempt to program or erase in a write protected area (WRP)
– Attempt to program or erase the system memory area.
– A write in the OTP area which is already locked
– Attempt to modify the option bytes when the read protection (RDP) is set to Level
– The Flash memory is read protected and an intrusion is detected
If a part of code is programmed in the flash, the user must guarantee that this part of code
has not been executed since the last reset. If this condition can not be filled safely, it is
recommended to flush the Caches.
a) ART accelerator flush and/or desactivate is performed by setting respectively the
bits ARTRST and/or ARTEN of the FLASH_CR register.
b) Perform CPU Cache maintenance operations
If a flash program or erase operation hits one or several data section already loaded in the
cache, it is the responsibility of the user to guarantee that these data will not be accessed
during code execution. Therefore during these operations, it is recommended to flush and/or
deactivate the Caches.
Note: Data coherency between caches and Flash memory is the responsibility of the user code
Note: The ART cache can be flushed only if the ART accelerator is disabled (ARTEN = 0).
Read-while-write (RWW)
Thanks to the dual bank mode (active when nDBANK option bit is 0), the Flash memory
structure allows read-while-write operations. This feature allows to perform a read operation
from one bank while an erase or program operation is performed to the other bank.
=== RM0410 Embedded Flash memory (FLASH) #98 ===
Note: Write-while-write operations are not allowed. As an exampled, It is not possible to perform
an erase or program operation on one bank while erasing or programming the other one,
except mass erase which erase both banks at same time
Read from bank 1 while erasing bank 2
While executing a program code from bank 1, it is possible to perform an erase operation on
bank 2 (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register (BSY is active when erase/program operation is on going to bank
1 or bank 2)
2. Set MER/MER1 or MER2 bit in the FLASH_CR register
3. Set the STRT bit in the FLASH_CR register
4. Wait for the BSY bit to be reset (or use the EOP interrupt).
Note: When setting the STRT bit in the FLASH_CR register and before polling the BSY bit to be
cleared, the software can issue a DSB instruction to guarantee the completion of a previous
access to FLASH_CR register.
Read from bank 1 while programming bank 2
While executing a program code (instruction fetch) from bank 1,it is possible to perform an
program operation to the bank 2 (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register (BSY is active when erase/program operation is on going on bank
1 or bank 2)
2. Set the PG bit in the FLASH_CR register
3. Perform the data write operation(s) to the desired memory address inside main
memory block or OTP area
4. Wait for the BSY bit to be reset.
Note: After performing a data write operation and before polling the BSY bit to be cleared, the
software can issue a DSB instruction to guarantee the completion of a previous data write
operation.
3.3.9 Flash Interrupts
Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables
interrupt generation when an erase or program operation ends, that is when the busy bit
(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this
case, the end of operation (EOP) bit in the FLASH_SR register is set.
If an error occurs during a program, an erase, or a read operation request, one of the
following error flags is set in the FLASH_SR register:
• PGAERR, PGPERR, ERSERR (Program error flags)
• WRPERR (Protection error flag)
In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_CR register, an
interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.
=== Embedded Flash memory (FLASH) RM0410 #99 ===
Table 9. Flash interrupt request
+------------------------+------------------------+--------------------+
| Interrupt event | Event flag | Enable control bit |
+========================+========================+====================+
| End of operation | EOP | EOPIE |
+------------------------+------------------------+--------------------+
| Write protection error | WRPERR | ERRIE |
+------------------------+------------------------+--------------------+
| Programming error | PGAERR, PGPERR, ERSERR | ERRIE |
+------------------------+------------------------+--------------------+
3.4 FLASH Option bytes
3.4.1 Option bytes description
The option bytes are configured by the end user depending on the application requirements.
Table 10 shows the organization of these bytes inside the information block.
The option bytes can be read from the user configuration memory locations or from the
Option byte registers:
• Flash option control register (FLASH_OPTCR)
• Flash option control register (FLASH_OPTCR1)
Table 10. Option byte organization
+-------------+---------+--------------------------------------------------------+
| AXI address | [63:16] | [15:0] |
+=============+=========+========================================================+
| 0x1FFF 0000 | | ROP & user option bytes (RDP & USER) |
+-------------+---------+--------------------------------------------------------+
| 0x1FFF 0008 | | IWDG_STOP, IWDG_STBY and nDBANK, nDBOOT and |
| | | Write protection nWRP/NWRPDB (sector 0 to 11) and user |
| | | option bytes |
+-------------+---------+--------------------------------------------------------+
| 0x1FFF 0010 | | BOOT_ADD0 |
+-------------+---------+--------------------------------------------------------+
| 0x1FFF 0018 | | BOOT_ADD1 |
+-------------+---------+--------------------------------------------------------+
User and read protection options bytes
Memory address: 0x1FFF 0000
ST programmed value: 0x5500AAFF
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
+====+====+====+====+====+====+====+====+====+====+====+====+====+====+====+====+
| | | | | | | | | | | | | | | | |
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| |
+-------------------------------------------------------------------------------+
+-----------------------+-------+-------+-------+------+-------+------+---+---+
| 15 14 13 12 11 10 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+=======================+=======+=======+=======+======+=======+======+===+===+
| RDP | nRST_ | nRST
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