SAWG reset control

sawg_rst.diff

diff --git a/artiq/firmware/ksupport/api.rs b/artiq/firmware/ksupport/api.rs
index 20efa141..86b5e952 100644
--- a/artiq/firmware/ksupport/api.rs
+++ b/artiq/firmware/ksupport/api.rs
@@ -121,4 +121,6 @@ static mut API: &'static [(&'static str, *const ())] = &[
     api!(spi_set_config = ::nrt_bus::spi::set_config),
     api!(spi_write = ::nrt_bus::spi::write),
     api!(spi_read = ::nrt_bus::spi::read),
+
+    api!(sawg_rst = ::board_misoc::csr::sawg_rst::reset_write)
 ];
diff --git a/artiq/gateware/rtio/phy/sawg.py b/artiq/gateware/rtio/phy/sawg.py
index 7968eb2b..6df58e09 100644
--- a/artiq/gateware/rtio/phy/sawg.py
+++ b/artiq/gateware/rtio/phy/sawg.py
@@ -8,7 +8,7 @@ from artiq.gateware.dsp.sawg import Channel as _Channel
 
 _Phy = namedtuple("Phy", "rtlink probes overrides")
 
-_ChannelPHY = ClockDomainsRenamer("rio_phy")(_Channel)
+_ChannelPHY = ClockDomainsRenamer("rio_sawg")(_Channel)
 
 
 class Channel(_ChannelPHY):
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index abb61497..7c06e67b 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -5,6 +5,7 @@ import os
 import warnings
 
 from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.cores import gpio
 from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
@@ -114,9 +115,18 @@ class RTMCommon:
         self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
 
 
+class SAWGResetCtl(Module, AutoCSR):
+    def __init__(self):
+        self.reset = CSRStorage(reset=1)
+        self.clock_domains.cd_rio_sawg = ClockDomain()
+        self.comb += self.cd_rio_sawg.clk.eq(ClockSignal("jesd"))
+        self.specials += AsyncResetSynchronizer(self.cd_rio_sawg, self.reset.storage)
+
+
 class Standalone(MiniSoC, AMPSoC, RTMCommon):
     mem_map = {
         "cri_con":       0x10000000,
+        "sawg_rst":      0x10100000,
         "rtio":          0x11000000,
         "rtio_dma":      0x12000000,
         "serwb":         0x13000000,
@@ -215,6 +225,9 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
             self.rtio_core.coarse_ts, self.ad9154_crg.jref)
         self.csr_devices.append("sysref_sampler")
 
+        self.submodules.sawg_rst = SAWGResetCtl()
+        self.register_kernel_cpu_csrdevice("sawg_rst")
+
 
 class Master(MiniSoC, AMPSoC, RTMCommon):
     mem_map = {