Skip to content

Instantly share code, notes, and snippets.

Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save sbourdeauducq/7888cf228c9d4fa7a34175853c89d7ee to your computer and use it in GitHub Desktop.
Save sbourdeauducq/7888cf228c9d4fa7a34175853c89d7ee to your computer and use it in GitHub Desktop.
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index abb614977..4fc80c5b3 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -251,14 +251,14 @@ class Master(MiniSoC, AMPSoC, RTMCommon):
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
- self.config["SI5324_SAYMA_REF"] = None
+ self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.comb += [
platform.request("sfp_tx_disable", i).eq(0)
for i in range(2)
]
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
- clock_pads=platform.request("dac_refclk", 0),
+ clock_pads=platform.request("si5324_clkout", 0),
data_pads=[platform.request("sfp", i) for i in range(2)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment