schegde

# This script compares conv2d operation between PyTorch and TensorRT for specified number of runs: NUM_RUNS,
# for the specified STRIDE, and prints the results
import torch
import torch.nn as nn
import numpy as np
import time

from polygraphy.backend.onnxrt import OnnxrtRunner, SessionFromOnnx
from polygraphy.backend.trt import CreateConfig as CreateTrtConfig, EngineFromNetwork, NetworkFromOnnxPath, TrtRunner
from polygraphy.comparator import Comparator

schegde

# This script compares conv2d operation between PyTorch and ONNX-TensorRT for specified number of runs: NUM_RUNS,
# for the specified STRIDE, and prints the percentage of output element mismatch, for list of tolerances TOL specified

import torch
import torch.nn as nn
import onnx
import onnx_tensorrt.backend as backend
import numpy as np
import time

schegde

PS-PL communication in a linux based Zynq SoC system.

This documents 2 approaches of data communication between PS and PL of Xilinx Zynq based SoCs. A major challenge in designing hardware-software co-design systems is the PS-PL communiction. The PL components interface to PS through AXI protocol standard, and present themselves as AXI slaves or AXI masters to the PS. The PS provides high performance AXI slave ports for PL AXI masters to communicate with the main memory (DRAM). The 2 approaches of data communication are Programmed I/O and Direct Memory Access (and a potential 3rd one: PL peripheral directly mastering the DDR without DMA(?))

---

Programmed I/O

For low bandwidth control path interface, userspace application can be easily developed using PS-programmed I/O. In this, the PS uses the AXI MM Master interface to communicate with AXI MM slave interface peripherals. This is a processor load-store based approach, wherein PS picks up data from DDR, and writes to the memory mapped