集積システム入門3-2

wiresim.rb

class WiredelaySim
  def initialize(opt)
    @mode, @n = opt.map(&:upcase)
    @n = @n.to_i
    @label_r = @label_c = 1
    @label_node = 'A'
  end

  def header
    """* task3-#{@mode}-#{@n}
.INCLUDE mos_model3
.options post
    """
  end

  def footer
    """.tran .001ns 10ns
.end"""
  end

  def subckt
    """Vdd Vdd 0 2.5

.subckt INVIN In Out Vdd
m1 Out In 0   0   cmosn l=0.25u w=32u
m2 Out In Vdd Vdd cmosp l=0.25u w=64u
.ends

.subckt INVOUT In Out Vdd
m1 Out In 0   0   cmosn l=0.25u w=2u
m2 Out In Vdd Vdd cmosp l=0.25u w=4u
.ends
    """
  end

  def circuit
    ret = ""
    c = 0.32 * 2000
    r = 0.08 * 2000 / 0.5

    ret += "V0 In 0 PWL(0ns 0 4ns 0 4.1ns 2.5 8.1ns 2.5 8.2ns 0)\n"
    ret += "Xin In #{@label_node} Vdd INVIN\n"

    if @mode == 'PI'
      @n.times do |i|
        if i == 0
          ret += "C#{@label_c} #{@label_node} 0 #{c / (2 * @n)}f\n" 
          @label_c += 1
        end
        ret += "R#{@label_r} #{@label_node} #{@label_node.succ} #{r / @n}\n"
        @label_node.succ!
        if i != @n - 1
          ret += "C#{@label_c} #{@label_node} 0 #{c / @n}f\n"
        else
          ret += "C#{@label_c} #{@label_node} 0 #{c / (2 * @n)}f\n"
        end
        @label_r += 1
        @label_c += 1
      end
    elsif @mode == 'T'
      @n.times do |i|
        if i == 0
          ret += "R#{@label_r} #{@label_node} #{@label_node.succ} #{r / (2 * @n)}\n" 
          @label_node.succ!
          @label_r += 1
        end
        ret += "C#{@label_c} #{@label_node} 0 #{c / @n}f\n"
        if i != @n - 1
          ret += "R#{@label_r} #{@label_node} #{@label_node.succ} #{r / @n}fn"
        else
          ret += "R#{@label_r} #{@label_node} #{@label_node.succ} #{r / (2 * @n)}\n"
        end
        @label_node.succ!
        @label_r += 1
        @label_c += 1
      end
    elsif @mode == 'L'
      @n.times do |i|
        ret += "R#{@label_r} #{@label_node} #{@label_node.succ} #{r / @n}\n"
        ret += "C#{@label_c} #{@label_node.succ} 0 #{c / @n}f\n"
        @label_node.succ!
      end
    end

    ret += "Xout #{@label_node} Out Vdd INVOUT\n"
    ret += "Cout Out 0 12f\n"
    ret += "\n"
    ret
  end

  def print
    puts self.header 
    puts self.subckt 
    puts self.circuit 
    puts self.footer
  end
end

sim = WiredelaySim.new ARGV
sim.print