Example of running the Scala FIRRTL compiler and the MLIR FIRRTL compiler on the same Chisel hardware description using scala-cli. This requires an installation of CIRCT, i.e., `firtool` must be on your `$PATH`.

Foo.scala

//> using scala "2.13"
//> using lib "edu.berkeley.cs::chisel3:3.5.1"
//> using lib "com.sifive::chisel-circt:0.3.0"
//> using mainClass "Foo"

import chisel3._
import chisel3.stage.{ChiselStage => SFC}
import circt.stage.{ChiselStage => MFC}

class Foo extends RawModule {
  val a, b, c, d, e = IO(Input(Bool()))
  val out1, out2 = IO(Output(Bool()))

  val x = a ^ b ^ c ^ d ^ e
  val y = a ^ b ^ c ^ d
  dontTouch(x)
  dontTouch(y)

  out1 := x
  out2 := y
}

object Foo extends App {
  println(SFC.emitVerilog(new Foo))
  println(MFC.emitSystemVerilog(new Foo))
}