gcc compilation comparison for Xtensa® CPU (ESP32)

gistfile1.txt

long count = 0;
void loop() {
    if (count++ >= 2000000)
    {
        count = 0;
        delay(1000);
    }
}


00000000 <_Z4loopv>:
   0:	004136        	entry	a1, 32
   3:	000091        	l32r	a9, fffc0004 <_Z4loopv+0xfffc0004>
   6:	0000a1        	l32r	a10, fffc0008 <_Z4loopv+0xfffc0008>
   9:	0988      		l32i.n	a8, a9, 0
   b:	052a87        	blt	a10, a8, 14 <_Z4loopv+0x14>
   e:	881b      		addi.n	a8, a8, 1
  10:	0989      		s32i.n	a8, a9, 0
  12:	f01d      		retw.n
  
						// count = 0;
  14:	080c      		movi.n	a8, 0
  						// delay(1000); 
  16:	e8a3a2        	movi	a10, 0x3e8
  19:	0989      		s32i.n	a8, a9, 0
  1b:	000081        	l32r	a8, fffc001c <_Z4loopv+0xfffc001c>
  1e:	0008e0        	callx8	a8
  21:	f01d      		retw.n

==========================================================================

long count = 0;
void loop() {
    if (count++ % 2000000 == 0)
    {
        delay(1000);
    }
}


00000000 <_Z4loopv>:
   0:	004136        	entry	a1, 32
   3:	000081        	l32r	a8, fffc0004 <_Z4loopv+0xfffc0004>
   6:	0898      		l32i.n	a9, a8, 0
   8:	a91b      		addi.n	a10, a9, 1								
   a:	08a9      		s32i.n	a10, a8, 0
   c:	000081        	l32r	a8, fffc000c <_Z4loopv+0xfffc000c>		 
   f:	31af90        	srai	a10, a9, 31
						// Multiply signed high (slow!)
  12:	b28980        	mulsh	a8, a9, a8							
  15:	318380        	srai	a8, a8, 19
  18:	c088a0        	sub	a8, a8, a10
  1b:	0000a1        	l32r	a10, fffc001c <_Z4loopv+0xfffc001c>
						// Multiply low
  1e:	8288a0        	mull	a8, a8, a10							
  21:	089987        	bne	a9, a8, 2d <_Z4loopv+0x2d>
  
						// delay(1000); 
  24:	e8a3a2        	movi	a10, 0x3e8
  27:	000081        	l32r	a8, fffc0028 <_Z4loopv+0xfffc0028>
  2a:	0008e0        	callx8	a8
  2d:	f01d      		retw.n

==========================================================================

long count = 0;
void loop() {
    if (count++ % 2097152 == 0)
    {
        delay(1000);
    }
}


00000000 <_Z4loopv>:
   0:	004136        	entry	a1, 32
   3:	000091        	l32r	a9, fffc0004 <_Z4loopv+0xfffc0004>
   6:	0988      		l32i.n	a8, a9, 0
   8:	a81b      		addi.n	a10, a8, 1								
   a:	0069a2        	s32i	a10, a9, 0
   d:	000091        	l32r	a9, fffc0010 <_Z4loopv+0xfffc0010>
// Branch if all/any bits specified by a mask in one register are set in another register (pretty fast!)
  10:	088897        	bany	a8, a9, 1c <_Z4loopv+0x1c>			
  
  						// delay(1000); 
  13:	e8a3a2        	movi	a10, 0x3e8	
  16:	000081        	l32r	a8, fffc0018 <_Z4loopv+0xfffc0018>
  19:	0008e0        	callx8	a8
  1c:	f01d      		retw.n