Skip to content

Instantly share code, notes, and snippets.

@sergev

sergev/rp2040-hello-uart-quick.trace

Created October 3, 2023 07:36
Show Gist options
  • Save sergev/546851c3032db9b65810f03b69c44006 to your computer and use it in GitHub Desktop.
Save sergev/546851c3032db9b65810f03b69c44006 to your computer and use it in GitHub Desktop.
Download ZIP
Run 'hello world' on RP2040 simulator, skip ROM
Raw
rp2040-hello-uart-quick.trace
RP2040 Simulator, Version 0.1
Code 0x10000000-0x10001e23 size 7716 bytes
Code 0x10001e24-0x10001fa3 size 384 bytes
(0) Read ROM [0] = 20041f00
(1) msp = 20041f00
(2) 100001f6: 481f ldr r0, [pc, #124]
(2) Read Flash [10000274] = d0000000
(3) r0 = d0000000
(4) 100001f8: 6800 ldr r0, [r0, #0]
(4) Read CPUID = 00000000
(5) r0 = 00000000
(6) 100001fa: 2800 cmp r0, #0
(6) nzcv = .11.
(7) 100001fc: d12f bne 0x1000025e
(8) 100001fe: a40d add r4, pc, #52
(8) r4 = 10000234
(9) 10000200: cc0e ldmia r4!, {r1, r2, r3}
(9) Read Flash [10000234] = 10001e24
(10) r1 = 10001e24
(10) Read Flash [10000238] = 200000c0
(11) r2 = 200000c0
(11) Read Flash [1000023c] = 20000240
(12) r3 = 20000240
(12) r4 = 10000240
(13) 10000202: 2900 cmp r1, #0
(13) nzcv = ..1.
(14) 10000204: d002 beq 0x1000020c
(16) 10000206: f000f812 bl 0x1000022e
(16) lr = 1000020a
(17) 1000022e: 429a cmp r2, r3
(17) nzcv = 1...
(18) 10000230: d3fb bcc 0x1000022a
(19) 1000022a: c901 ldmia r1!, {r0}
(19) Read Flash [10001e24] = b53023d0
(20) r0 = b53023d0
(20) r1 = 10001e28
(21) 1000022c: c201 stmia r2!, {r0}
(21) Write SRAM [200000c0] = b53023d0
(22) r2 = 200000c4
(23) 1000022e: 429a cmp r2, r3
(24) 10000230: d3fb bcc 0x1000022a
(25) 1000022a: c901 ldmia r1!, {r0}
(25) Read Flash [10001e28] = 061b2500
(26) r0 = 061b2500
(26) r1 = 10001e2c
(27) 1000022c: c201 stmia r2!, {r0}
(27) Write SRAM [200000c4] = 061b2500
(28) r2 = 200000c8
(29) 1000022e: 429a cmp r2, r3
(30) 10000230: d3fb bcc 0x1000022a
(31) 1000022a: c901 ldmia r1!, {r0}
(31) Read Flash [10001e2c] = 575d2400
(32) r0 = 575d2400
(32) r1 = 10001e30
(33) 1000022c: c201 stmia r2!, {r0}
(33) Write SRAM [200000c8] = 575d2400
(34) r2 = 200000cc
(35) 1000022e: 429a cmp r2, r3
(36) 10000230: d3fb bcc 0x1000022a
(37) 1000022a: c901 ldmia r1!, {r0}
(37) Read Flash [10001e30] = 6803e006
(38) r0 = 6803e006
(38) r1 = 10001e34
(39) 1000022c: c201 stmia r2!, {r0}
(39) Write SRAM [200000cc] = 6803e006
(40) r2 = 200000d0
(41) 1000022e: 429a cmp r2, r3
(42) 10000230: d3fb bcc 0x1000022a
(43) 1000022a: c901 ldmia r1!, {r0}
(43) Read Flash [10001e34] = 8f5ff3bf
(44) r0 = 8f5ff3bf
(44) r1 = 10001e38
(45) 1000022c: c201 stmia r2!, {r0}
(45) Write SRAM [200000d0] = 8f5ff3bf
(46) r2 = 200000d4
(47) 1000022e: 429a cmp r2, r3
(48) 10000230: d3fb bcc 0x1000022a
(49) 1000022a: c901 ldmia r1!, {r0}
(49) Read Flash [10001e38] = f381601c
(50) r0 = f381601c
(50) r1 = 10001e3c
(51) 1000022c: c201 stmia r2!, {r0}
(51) Write SRAM [200000d4] = f381601c
(52) r2 = 200000d8
(53) 1000022e: 429a cmp r2, r3
(54) 10000230: d3fb bcc 0x1000022a
(55) 1000022a: c901 ldmia r1!, {r0}
(55) Read Flash [10001e3c] = bf208810
(56) r0 = bf208810
(56) r1 = 10001e40
(57) 1000022c: c201 stmia r2!, {r0}
(57) Write SRAM [200000d8] = bf208810
(58) r2 = 200000dc
(59) 1000022e: 429a cmp r2, r3
(60) 10000230: d3fb bcc 0x1000022a
(61) 1000022a: c901 ldmia r1!, {r0}
(61) Read Flash [10001e40] = f3ef6802
(62) r0 = f3ef6802
(62) r1 = 10001e44
(63) 1000022c: c201 stmia r2!, {r0}
(63) Write SRAM [200000dc] = f3ef6802
(64) r2 = 200000e0
(65) 1000022e: 429a cmp r2, r3
(66) 10000230: d3fb bcc 0x1000022a
(67) 1000022a: c901 ldmia r1!, {r0}
(67) Read Flash [10001e44] = b6728110
(68) r0 = b6728110
(68) r1 = 10001e48
(69) 1000022c: c201 stmia r2!, {r0}
(69) Write SRAM [200000e0] = b6728110
(70) r2 = 200000e4
(71) 1000022e: 429a cmp r2, r3
(72) 10000230: d3fb bcc 0x1000022a
(73) 1000022a: c901 ldmia r1!, {r0}
(73) Read Flash [10001e48] = 2b006813
(74) r0 = 2b006813
(74) r1 = 10001e4c
(75) 1000022c: c201 stmia r2!, {r0}
(75) Write SRAM [200000e4] = 2b006813
(76) r2 = 200000e8
(77) 1000022e: 429a cmp r2, r3
(78) 10000230: d3fb bcc 0x1000022a
(79) 1000022a: c901 ldmia r1!, {r0}
(79) Read Flash [10001e4c] = f3bfd0fc
(80) r0 = f3bfd0fc
(80) r1 = 10001e50
(81) 1000022c: c201 stmia r2!, {r0}
(81) Write SRAM [200000e8] = f3bfd0fc
(82) r2 = 200000ec
(83) 1000022e: 429a cmp r2, r3
(84) 10000230: d3fb bcc 0x1000022a
(85) 1000022a: c901 ldmia r1!, {r0}
(85) Read Flash [10001e50] = 79038f5f
(86) r0 = 79038f5f
(86) r1 = 10001e54
(87) 1000022c: c201 stmia r2!, {r0}
(87) Write SRAM [200000ec] = 79038f5f
(88) r2 = 200000f0
(89) 1000022e: 429a cmp r2, r3
(90) 10000230: d3fb bcc 0x1000022a
(91) 1000022a: c901 ldmia r1!, {r0}
(91) Read Flash [10001e54] = d9ec2b7f
(92) r0 = d9ec2b7f
(92) r1 = 10001e58
(93) 1000022c: c201 stmia r2!, {r0}
(93) Write SRAM [200000f0] = d9ec2b7f
(94) r2 = 200000f4
(95) 1000022e: 429a cmp r2, r3
(96) 10000230: d3fb bcc 0x1000022a
(97) 1000022a: c901 ldmia r1!, {r0}
(97) Read Flash [10001e58] = 68037105
(98) r0 = 68037105
(98) r1 = 10001e5c
(99) 1000022c: c201 stmia r2!, {r0}
(99) Write SRAM [200000f4] = 68037105
(100) r2 = 200000f8
(101) 1000022e: 429a cmp r2, r3
(102) 10000230: d3fb bcc 0x1000022a
(103) 1000022a: c901 ldmia r1!, {r0}
(103) Read Flash [10001e5c] = 8f5ff3bf
(104) r0 = 8f5ff3bf
(104) r1 = 10001e60
(105) 1000022c: c201 stmia r2!, {r0}
(105) Write SRAM [200000f8] = 8f5ff3bf
(106) r2 = 200000fc
(107) 1000022e: 429a cmp r2, r3
(108) 10000230: d3fb bcc 0x1000022a
(109) 1000022a: c901 ldmia r1!, {r0}
(109) Read Flash [10001e60] = 601a2200
(110) r0 = 601a2200
(110) r1 = 10001e64
(111) 1000022c: c201 stmia r2!, {r0}
(111) Write SRAM [200000fc] = 601a2200
(112) r2 = 20000100
(113) 1000022e: 429a cmp r2, r3
(114) 10000230: d3fb bcc 0x1000022a
(115) 1000022a: c901 ldmia r1!, {r0}
(115) Read Flash [10001e64] = 8810f381
(116) r0 = 8810f381
(116) r1 = 10001e68
(117) 1000022c: c201 stmia r2!, {r0}
(117) Write SRAM [20000100] = 8810f381
(118) r2 = 20000104
(119) 1000022e: 429a cmp r2, r3
(120) 10000230: d3fb bcc 0x1000022a
(121) 1000022a: c901 ldmia r1!, {r0}
(121) Read Flash [10001e68] = 46c0bd30
(122) r0 = 46c0bd30
(122) r1 = 10001e6c
(123) 1000022c: c201 stmia r2!, {r0}
(123) Write SRAM [20000104] = 46c0bd30
(124) r2 = 20000108
(125) 1000022e: 429a cmp r2, r3
(126) 10000230: d3fb bcc 0x1000022a
(127) 1000022a: c901 ldmia r1!, {r0}
(127) Read Flash [10001e6c] = 68000003
(128) r0 = 68000003
(128) r1 = 10001e70
(129) 1000022c: c201 stmia r2!, {r0}
(129) Write SRAM [20000108] = 68000003
(130) r2 = 2000010c
(131) 1000022e: 429a cmp r2, r3
(132) 10000230: d3fb bcc 0x1000022a
(133) 1000022a: c901 ldmia r1!, {r0}
(133) Read Flash [10001e70] = 8c10f3ef
(134) r0 = 8c10f3ef
(134) r1 = 10001e74
(135) 1000022c: c201 stmia r2!, {r0}
(135) Write SRAM [2000010c] = 8c10f3ef
(136) r2 = 20000110
(137) 1000022e: 429a cmp r2, r3
(138) 10000230: d3fb bcc 0x1000022a
(139) 1000022a: c901 ldmia r1!, {r0}
(139) Read Flash [10001e74] = 6802b672
(140) r0 = 6802b672
(140) r1 = 10001e78
(141) 1000022c: c201 stmia r2!, {r0}
(141) Write SRAM [20000110] = 6802b672
(142) r2 = 20000114
(143) 1000022e: 429a cmp r2, r3
(144) 10000230: d3fb bcc 0x1000022a
(145) 1000022a: c901 ldmia r1!, {r0}
(145) Read Flash [10001e78] = d0fc2a00
(146) r0 = d0fc2a00
(146) r1 = 10001e7c
(147) 1000022c: c201 stmia r2!, {r0}
(147) Write SRAM [20000114] = d0fc2a00
(148) r2 = 20000118
(149) 1000022e: 429a cmp r2, r3
(150) 10000230: d3fb bcc 0x1000022a
(151) 1000022a: c901 ldmia r1!, {r0}
(151) Read Flash [10001e7c] = 8f5ff3bf
(152) r0 = 8f5ff3bf
(152) r1 = 10001e80
(153) 1000022c: c201 stmia r2!, {r0}
(153) Write SRAM [20000118] = 8f5ff3bf
(154) r2 = 2000011c
(155) 1000022e: 429a cmp r2, r3
(156) 10000230: d3fb bcc 0x1000022a
(157) 1000022a: c901 ldmia r1!, {r0}
(157) Read Flash [10001e80] = 569a2204
(158) r0 = 569a2204
(158) r1 = 10001e84
(159) 1000022c: c201 stmia r2!, {r0}
(159) Write SRAM [2000011c] = 569a2204
(160) r2 = 20000120
(161) 1000022e: 429a cmp r2, r3
(162) 10000230: d3fb bcc 0x1000022a
(163) 1000022a: c901 ldmia r1!, {r0}
(163) Read Flash [10001e84] = db042a00
(164) r0 = db042a00
(164) r1 = 10001e88
(165) 1000022c: c201 stmia r2!, {r0}
(165) Write SRAM [20000120] = db042a00
(166) r2 = 20000124
(167) 1000022e: 429a cmp r2, r3
(168) 10000230: d3fb bcc 0x1000022a
(169) 1000022a: c901 ldmia r1!, {r0}
(169) Read Flash [10001e88] = d0002900
(170) r0 = d0002900
(170) r1 = 10001e8c
(171) 1000022c: c201 stmia r2!, {r0}
(171) Write SRAM [20000124] = d0002900
(172) r2 = 20000128
(173) 1000022e: 429a cmp r2, r3
(174) 10000230: d3fb bcc 0x1000022a
(175) 1000022a: c901 ldmia r1!, {r0}
(175) Read Flash [10001e8c] = 2000600a
(176) r0 = 2000600a
(176) r1 = 10001e90
(177) 1000022c: c201 stmia r2!, {r0}
(177) Write SRAM [20000128] = 2000600a
(178) r2 = 2000012c
(179) 1000022e: 429a cmp r2, r3
(180) 10000230: d3fb bcc 0x1000022a
(181) 1000022a: c901 ldmia r1!, {r0}
(181) Read Flash [10001e90] = 22d0e004
(182) r0 = 22d0e004
(182) r1 = 10001e94
(183) 1000022c: c201 stmia r2!, {r0}
(183) Write SRAM [2000012c] = 22d0e004
(184) r2 = 20000130
(185) 1000022e: 429a cmp r2, r3
(186) 10000230: d3fb bcc 0x1000022a
(187) 1000022a: c901 ldmia r1!, {r0}
(187) Read Flash [10001e94] = 06122001
(188) r0 = 06122001
(188) r1 = 10001e98
(189) 1000022c: c201 stmia r2!, {r0}
(189) Write SRAM [20000130] = 06122001
(190) r2 = 20000134
(191) 1000022e: 429a cmp r2, r3
(192) 10000230: d3fb bcc 0x1000022a
(193) 1000022a: c901 ldmia r1!, {r0}
(193) Read Flash [10001e98] = 711a6812
(194) r0 = 711a6812
(194) r1 = 10001e9c
(195) 1000022c: c201 stmia r2!, {r0}
(195) Write SRAM [20000134] = 711a6812
(196) r2 = 20000138
(197) 1000022e: 429a cmp r2, r3
(198) 10000230: d3fb bcc 0x1000022a
(199) 1000022a: c901 ldmia r1!, {r0}
(199) Read Flash [10001e9c] = f3bf681b
(200) r0 = f3bf681b
(200) r1 = 10001ea0
(201) 1000022c: c201 stmia r2!, {r0}
(201) Write SRAM [20000138] = f3bf681b
(202) r2 = 2000013c
(203) 1000022e: 429a cmp r2, r3
(204) 10000230: d3fb bcc 0x1000022a
(205) 1000022a: c901 ldmia r1!, {r0}
(205) Read Flash [10001ea0] = 22008f5f
(206) r0 = 22008f5f
(206) r1 = 10001ea4
(207) 1000022c: c201 stmia r2!, {r0}
(207) Write SRAM [2000013c] = 22008f5f
(208) r2 = 20000140
(209) 1000022e: 429a cmp r2, r3
(210) 10000230: d3fb bcc 0x1000022a
(211) 1000022a: c901 ldmia r1!, {r0}
(211) Read Flash [10001ea4] = f38c601a
(212) r0 = f38c601a
(212) r1 = 10001ea8
(213) 1000022c: c201 stmia r2!, {r0}
(213) Write SRAM [20000140] = f38c601a
(214) r2 = 20000144
(215) 1000022e: 429a cmp r2, r3
(216) 10000230: d3fb bcc 0x1000022a
(217) 1000022a: c901 ldmia r1!, {r0}
(217) Read Flash [10001ea8] = 47708810
(218) r0 = 47708810
(218) r1 = 10001eac
(219) 1000022c: c201 stmia r2!, {r0}
(219) Write SRAM [20000144] = 47708810
(220) r2 = 20000148
(221) 1000022e: 429a cmp r2, r3
(222) 10000230: d3fb bcc 0x1000022a
(223) 1000022a: c901 ldmia r1!, {r0}
(223) Read Flash [10001eac] = f3ef6802
(224) r0 = f3ef6802
(224) r1 = 10001eb0
(225) 1000022c: c201 stmia r2!, {r0}
(225) Write SRAM [20000148] = f3ef6802
(226) r2 = 2000014c
(227) 1000022e: 429a cmp r2, r3
(228) 10000230: d3fb bcc 0x1000022a
(229) 1000022a: c901 ldmia r1!, {r0}
(229) Read Flash [10001eb0] = b6728110
(230) r0 = b6728110
(230) r1 = 10001eb4
(231) 1000022c: c201 stmia r2!, {r0}
(231) Write SRAM [2000014c] = b6728110
(232) r2 = 20000150
(233) 1000022e: 429a cmp r2, r3
(234) 10000230: d3fb bcc 0x1000022a
(235) 1000022a: c901 ldmia r1!, {r0}
(235) Read Flash [10001eb4] = 2b006813
(236) r0 = 2b006813
(236) r1 = 10001eb8
(237) 1000022c: c201 stmia r2!, {r0}
(237) Write SRAM [20000150] = 2b006813
(238) r2 = 20000154
(239) 1000022e: 429a cmp r2, r3
(240) 10000230: d3fb bcc 0x1000022a
(241) 1000022a: c901 ldmia r1!, {r0}
(241) Read Flash [10001eb8] = f3bfd0fc
(242) r0 = f3bfd0fc
(242) r1 = 10001ebc
(243) 1000022c: c201 stmia r2!, {r0}
(243) Write SRAM [20000154] = f3bfd0fc
(244) r2 = 20000158
(245) 1000022e: 429a cmp r2, r3
(246) 10000230: d3fb bcc 0x1000022a
(247) 1000022a: c901 ldmia r1!, {r0}
(247) Read Flash [10001ebc] = 23ff8f5f
(248) r0 = 23ff8f5f
(248) r1 = 10001ec0
(249) 1000022c: c201 stmia r2!, {r0}
(249) Write SRAM [20000158] = 23ff8f5f
(250) r2 = 2000015c
(251) 1000022e: 429a cmp r2, r3
(252) 10000230: d3fb bcc 0x1000022a
(253) 1000022a: c901 ldmia r1!, {r0}
(253) Read Flash [10001ec0] = 68037103
(254) r0 = 68037103
(254) r1 = 10001ec4
(255) 1000022c: c201 stmia r2!, {r0}
(255) Write SRAM [2000015c] = 68037103
(256) r2 = 20000160
(257) 1000022e: 429a cmp r2, r3
(258) 10000230: d3fb bcc 0x1000022a
(259) 1000022a: c901 ldmia r1!, {r0}
(259) Read Flash [10001ec4] = 8f5ff3bf
(260) r0 = 8f5ff3bf
(260) r1 = 10001ec8
(261) 1000022c: c201 stmia r2!, {r0}
(261) Write SRAM [20000160] = 8f5ff3bf
(262) r2 = 20000164
(263) 1000022e: 429a cmp r2, r3
(264) 10000230: d3fb bcc 0x1000022a
(265) 1000022a: c901 ldmia r1!, {r0}
(265) Read Flash [10001ec8] = 601a2200
(266) r0 = 601a2200
(266) r1 = 10001ecc
(267) 1000022c: c201 stmia r2!, {r0}
(267) Write SRAM [20000164] = 601a2200
(268) r2 = 20000168
(269) 1000022e: 429a cmp r2, r3
(270) 10000230: d3fb bcc 0x1000022a
(271) 1000022a: c901 ldmia r1!, {r0}
(271) Read Flash [10001ecc] = 8810f381
(272) r0 = 8810f381
(272) r1 = 10001ed0
(273) 1000022c: c201 stmia r2!, {r0}
(273) Write SRAM [20000168] = 8810f381
(274) r2 = 2000016c
(275) 1000022e: 429a cmp r2, r3
(276) 10000230: d3fb bcc 0x1000022a
(277) 1000022a: c901 ldmia r1!, {r0}
(277) Read Flash [10001ed0] = 4770bf40
(278) r0 = 4770bf40
(278) r1 = 10001ed4
(279) 1000022c: c201 stmia r2!, {r0}
(279) Write SRAM [2000016c] = 4770bf40
(280) r2 = 20000170
(281) 1000022e: 429a cmp r2, r3
(282) 10000230: d3fb bcc 0x1000022a
(283) 1000022a: c901 ldmia r1!, {r0}
(283) Read Flash [10001ed4] = 46c04770
(284) r0 = 46c04770
(284) r1 = 10001ed8
(285) 1000022c: c201 stmia r2!, {r0}
(285) Write SRAM [20000170] = 46c04770
(286) r2 = 20000174
(287) 1000022e: 429a cmp r2, r3
(288) 10000230: d3fb bcc 0x1000022a
(289) 1000022a: c901 ldmia r1!, {r0}
(289) Read Flash [10001ed8] = 00000010
(290) r0 = 00000010
(290) r1 = 10001edc
(291) 1000022c: c201 stmia r2!, {r0}
(291) Write SRAM [20000174] = 00000010
(292) r2 = 20000178
(293) 1000022e: 429a cmp r2, r3
(294) 10000230: d3fb bcc 0x1000022a
(295) 1000022a: c901 ldmia r1!, {r0}
(295) Read Flash [10001edc] = 00000000
(296) r0 = 00000000
(296) r1 = 10001ee0
(297) 1000022c: c201 stmia r2!, {r0}
(297) Write SRAM [20000178] = 00000000
(298) r2 = 2000017c
(299) 1000022e: 429a cmp r2, r3
(300) 10000230: d3fb bcc 0x1000022a
(301) 1000022a: c901 ldmia r1!, {r0}
(301) Read Flash [10001ee0] = 00010000
(302) r0 = 00010000
(302) r1 = 10001ee4
(303) 1000022c: c201 stmia r2!, {r0}
(303) Write SRAM [2000017c] = 00010000
(304) r2 = 20000180
(305) 1000022e: 429a cmp r2, r3
(306) 10000230: d3fb bcc 0x1000022a
(307) 1000022a: c901 ldmia r1!, {r0}
(307) Read Flash [10001ee4] = 00000000
(308) r0 = 00000000
(308) r1 = 10001ee8
(309) 1000022c: c201 stmia r2!, {r0}
(309) Write SRAM [20000180] = 00000000
(310) r2 = 20000184
(311) 1000022e: 429a cmp r2, r3
(312) 10000230: d3fb bcc 0x1000022a
(313) 1000022a: c901 ldmia r1!, {r0}
(313) Read Flash [10001ee8] = 00000000
(314) r0 = 00000000
(314) r1 = 10001eec
(315) 1000022c: c201 stmia r2!, {r0}
(315) Write SRAM [20000184] = 00000000
(316) r2 = 20000188
(317) 1000022e: 429a cmp r2, r3
(318) 10000230: d3fb bcc 0x1000022a
(319) 1000022a: c901 ldmia r1!, {r0}
(319) Read Flash [10001eec] = 00020000
(320) r0 = 00020000
(320) r1 = 10001ef0
(321) 1000022c: c201 stmia r2!, {r0}
(321) Write SRAM [20000188] = 00020000
(322) r2 = 2000018c
(323) 1000022e: 429a cmp r2, r3
(324) 10000230: d3fb bcc 0x1000022a
(325) 1000022a: c901 ldmia r1!, {r0}
(325) Read Flash [10001ef0] = 00000000
(326) r0 = 00000000
(326) r1 = 10001ef4
(327) 1000022c: c201 stmia r2!, {r0}
(327) Write SRAM [2000018c] = 00000000
(328) r2 = 20000190
(329) 1000022e: 429a cmp r2, r3
(330) 10000230: d3fb bcc 0x1000022a
(331) 1000022a: c901 ldmia r1!, {r0}
(331) Read Flash [10001ef4] = 00000000
(332) r0 = 00000000
(332) r1 = 10001ef8
(333) 1000022c: c201 stmia r2!, {r0}
(333) Write SRAM [20000190] = 00000000
(334) r2 = 20000194
(335) 1000022e: 429a cmp r2, r3
(336) 10000230: d3fb bcc 0x1000022a
(337) 1000022a: c901 ldmia r1!, {r0}
(337) Read Flash [10001ef8] = 00030000
(338) r0 = 00030000
(338) r1 = 10001efc
(339) 1000022c: c201 stmia r2!, {r0}
(339) Write SRAM [20000194] = 00030000
(340) r2 = 20000198
(341) 1000022e: 429a cmp r2, r3
(342) 10000230: d3fb bcc 0x1000022a
(343) 1000022a: c901 ldmia r1!, {r0}
(343) Read Flash [10001efc] = 00000000
(344) r0 = 00000000
(344) r1 = 10001f00
(345) 1000022c: c201 stmia r2!, {r0}
(345) Write SRAM [20000198] = 00000000
(346) r2 = 2000019c
(347) 1000022e: 429a cmp r2, r3
(348) 10000230: d3fb bcc 0x1000022a
(349) 1000022a: c901 ldmia r1!, {r0}
(349) Read Flash [10001f00] = 00000000
(350) r0 = 00000000
(350) r1 = 10001f04
(351) 1000022c: c201 stmia r2!, {r0}
(351) Write SRAM [2000019c] = 00000000
(352) r2 = 200001a0
(353) 1000022e: 429a cmp r2, r3
(354) 10000230: d3fb bcc 0x1000022a
(355) 1000022a: c901 ldmia r1!, {r0}
(355) Read Flash [10001f04] = 00ff0000
(356) r0 = 00ff0000
(356) r1 = 10001f08
(357) 1000022c: c201 stmia r2!, {r0}
(357) Write SRAM [200001a0] = 00ff0000
(358) r2 = 200001a4
(359) 1000022e: 429a cmp r2, r3
(360) 10000230: d3fb bcc 0x1000022a
(361) 1000022a: c901 ldmia r1!, {r0}
(361) Read Flash [10001f08] = 00000000
(362) r0 = 00000000
(362) r1 = 10001f0c
(363) 1000022c: c201 stmia r2!, {r0}
(363) Write SRAM [200001a4] = 00000000
(364) r2 = 200001a8
(365) 1000022e: 429a cmp r2, r3
(366) 10000230: d3fb bcc 0x1000022a
(367) 1000022a: c901 ldmia r1!, {r0}
(367) Read Flash [10001f0c] = 6848b500
(368) r0 = 6848b500
(368) r1 = 10001f10
(369) 1000022c: c201 stmia r2!, {r0}
(369) Write SRAM [200001a8] = 6848b500
(370) r2 = 200001ac
(371) 1000022e: 429a cmp r2, r3
(372) 10000230: d3fb bcc 0x1000022a
(373) 1000022a: c901 ldmia r1!, {r0}
(373) Read Flash [10001f10] = 468e3101
(374) r0 = 468e3101
(374) r1 = 10001f14
(375) 1000022c: c201 stmia r2!, {r0}
(375) Write SRAM [200001ac] = 468e3101
(376) r2 = 200001b0
(377) 1000022e: 429a cmp r2, r3
(378) 10000230: d3fb bcc 0x1000022a
(379) 1000022a: c901 ldmia r1!, {r0}
(379) Read Flash [10001f14] = 46704700
(380) r0 = 46704700
(380) r1 = 10001f18
(381) 1000022c: c201 stmia r2!, {r0}
(381) Write SRAM [200001b0] = 46704700
(382) r2 = 200001b4
(383) 1000022e: 429a cmp r2, r3
(384) 10000230: d3fb bcc 0x1000022a
(385) 1000022a: c901 ldmia r1!, {r0}
(385) Read Flash [10001f18] = 49013809
(386) r0 = 49013809
(386) r1 = 10001f1c
(387) 1000022c: c201 stmia r2!, {r0}
(387) Write SRAM [200001b4] = 49013809
(388) r2 = 200001b8
(389) 1000022e: 429a cmp r2, r3
(390) 10000230: d3fb bcc 0x1000022a
(391) 1000022a: c901 ldmia r1!, {r0}
(391) Read Flash [10001f1c] = bd004788
(392) r0 = bd004788
(392) r1 = 10001f20
(393) 1000022c: c201 stmia r2!, {r0}
(393) Write SRAM [200001b8] = bd004788
(394) r2 = 200001bc
(395) 1000022e: 429a cmp r2, r3
(396) 10000230: d3fb bcc 0x1000022a
(397) 1000022a: c901 ldmia r1!, {r0}
(397) Read Flash [10001f20] = 10000631
(398) r0 = 10000631
(398) r1 = 10001f24
(399) 1000022c: c201 stmia r2!, {r0}
(399) Write SRAM [200001bc] = 10000631
(400) r2 = 200001c0
(401) 1000022e: 429a cmp r2, r3
(402) 10000230: d3fb bcc 0x1000022a
(403) 1000022a: c901 ldmia r1!, {r0}
(403) Read Flash [10001f24] = 200001d8
(404) r0 = 200001d8
(404) r1 = 10001f28
(405) 1000022c: c201 stmia r2!, {r0}
(405) Write SRAM [200001c0] = 200001d8
(406) r2 = 200001c4
(407) 1000022e: 429a cmp r2, r3
(408) 10000230: d3fb bcc 0x1000022a
(409) 1000022a: c901 ldmia r1!, {r0}
(409) Read Flash [10001f28] = 00000000
(410) r0 = 00000000
(410) r1 = 10001f2c
(411) 1000022c: c201 stmia r2!, {r0}
(411) Write SRAM [200001c4] = 00000000
(412) r2 = 200001c8
(413) 1000022e: 429a cmp r2, r3
(414) 10000230: d3fb bcc 0x1000022a
(415) 1000022a: c901 ldmia r1!, {r0}
(415) Read Flash [10001f2c] = 20000268
(416) r0 = 20000268
(416) r1 = 10001f30
(417) 1000022c: c201 stmia r2!, {r0}
(417) Write SRAM [200001c8] = 20000268
(418) r2 = 200001cc
(419) 1000022e: 429a cmp r2, r3
(420) 10000230: d3fb bcc 0x1000022a
(421) 1000022a: c901 ldmia r1!, {r0}
(421) Read Flash [10001f30] = 20000578
(422) r0 = 20000578
(422) r1 = 10001f34
(423) 1000022c: c201 stmia r2!, {r0}
(423) Write SRAM [200001cc] = 20000578
(424) r2 = 200001d0
(425) 1000022e: 429a cmp r2, r3
(426) 10000230: d3fb bcc 0x1000022a
(427) 1000022a: c901 ldmia r1!, {r0}
(427) Read Flash [10001f34] = 00000000
(428) r0 = 00000000
(428) r1 = 10001f38
(429) 1000022c: c201 stmia r2!, {r0}
(429) Write SRAM [200001d0] = 00000000
(430) r2 = 200001d4
(431) 1000022e: 429a cmp r2, r3
(432) 10000230: d3fb bcc 0x1000022a
(433) 1000022a: c901 ldmia r1!, {r0}
(433) Read Flash [10001f38] = 00000000
(434) r0 = 00000000
(434) r1 = 10001f3c
(435) 1000022c: c201 stmia r2!, {r0}
(435) Write SRAM [200001d4] = 00000000
(436) r2 = 200001d8
(437) 1000022e: 429a cmp r2, r3
(438) 10000230: d3fb bcc 0x1000022a
(439) 1000022a: c901 ldmia r1!, {r0}
(439) Read Flash [10001f3c] = 20000588
(440) r0 = 20000588
(440) r1 = 10001f40
(441) 1000022c: c201 stmia r2!, {r0}
(441) Write SRAM [200001d8] = 20000588
(442) r2 = 200001dc
(443) 1000022e: 429a cmp r2, r3
(444) 10000230: d3fb bcc 0x1000022a
(445) 1000022a: c901 ldmia r1!, {r0}
(445) Read Flash [10001f40] = 00000000
(446) r0 = 00000000
(446) r1 = 10001f44
(447) 1000022c: c201 stmia r2!, {r0}
(447) Write SRAM [200001dc] = 00000000
(448) r2 = 200001e0
(449) 1000022e: 429a cmp r2, r3
(450) 10000230: d3fb bcc 0x1000022a
(451) 1000022a: c901 ldmia r1!, {r0}
(451) Read Flash [10001f44] = 00000000
(452) r0 = 00000000
(452) r1 = 10001f48
(453) 1000022c: c201 stmia r2!, {r0}
(453) Write SRAM [200001e0] = 00000000
(454) r2 = 200001e4
(455) 1000022e: 429a cmp r2, r3
(456) 10000230: d3fb bcc 0x1000022a
(457) 1000022a: c901 ldmia r1!, {r0}
(457) Read Flash [10001f48] = 00000010
(458) r0 = 00000010
(458) r1 = 10001f4c
(459) 1000022c: c201 stmia r2!, {r0}
(459) Write SRAM [200001e4] = 00000010
(460) r2 = 200001e8
(461) 1000022e: 429a cmp r2, r3
(462) 10000230: d3fb bcc 0x1000022a
(463) 1000022a: c901 ldmia r1!, {r0}
(463) Read Flash [10001f4c] = 00000000
(464) r0 = 00000000
(464) r1 = 10001f50
(465) 1000022c: c201 stmia r2!, {r0}
(465) Write SRAM [200001e8] = 00000000
(466) r2 = 200001ec
(467) 1000022e: 429a cmp r2, r3
(468) 10000230: d3fb bcc 0x1000022a
(469) 1000022a: c901 ldmia r1!, {r0}
(469) Read Flash [10001f50] = 00000000
(470) r0 = 00000000
(470) r1 = 10001f54
(471) 1000022c: c201 stmia r2!, {r0}
(471) Write SRAM [200001ec] = 00000000
(472) r2 = 200001f0
(473) 1000022e: 429a cmp r2, r3
(474) 10000230: d3fb bcc 0x1000022a
(475) 1000022a: c901 ldmia r1!, {r0}
(475) Read Flash [10001f54] = 00003350
(476) r0 = 00003350
(476) r1 = 10001f58
(477) 1000022c: c201 stmia r2!, {r0}
(477) Write SRAM [200001f0] = 00003350
(478) r2 = 200001f4
(479) 1000022e: 429a cmp r2, r3
(480) 10000230: d3fb bcc 0x1000022a
(481) 1000022a: c901 ldmia r1!, {r0}
(481) Read Flash [10001f58] = 0000334c
(482) r0 = 0000334c
(482) r1 = 10001f5c
(483) 1000022c: c201 stmia r2!, {r0}
(483) Write SRAM [200001f4] = 0000334c
(484) r2 = 200001f8
(485) 1000022e: 429a cmp r2, r3
(486) 10000230: d3fb bcc 0x1000022a
(487) 1000022a: c901 ldmia r1!, {r0}
(487) Read Flash [10001f5c] = 00003354
(488) r0 = 00003354
(488) r1 = 10001f60
(489) 1000022c: c201 stmia r2!, {r0}
(489) Write SRAM [200001f8] = 00003354
(490) r2 = 200001fc
(491) 1000022e: 429a cmp r2, r3
(492) 10000230: d3fb bcc 0x1000022a
(493) 1000022a: c901 ldmia r1!, {r0}
(493) Read Flash [10001f60] = 00003352
(494) r0 = 00003352
(494) r1 = 10001f64
(495) 1000022c: c201 stmia r2!, {r0}
(495) Write SRAM [200001fc] = 00003352
(496) r2 = 20000200
(497) 1000022e: 429a cmp r2, r3
(498) 10000230: d3fb bcc 0x1000022a
(499) 1000022a: c901 ldmia r1!, {r0}
(499) Read Flash [10001f64] = 0000534d
(500) r0 = 0000534d
(500) r1 = 10001f68
(501) 1000022c: c201 stmia r2!, {r0}
(501) Write SRAM [20000200] = 0000534d
(502) r2 = 20000204
(503) 1000022e: 429a cmp r2, r3
(504) 10000230: d3fb bcc 0x1000022a
(505) 1000022a: c901 ldmia r1!, {r0}
(505) Read Flash [10001f68] = 0000434d
(506) r0 = 0000434d
(506) r1 = 10001f6c
(507) 1000022c: c201 stmia r2!, {r0}
(507) Write SRAM [20000204] = 0000434d
(508) r2 = 20000208
(509) 1000022e: 429a cmp r2, r3
(510) 10000230: d3fb bcc 0x1000022a
(511) 1000022a: c901 ldmia r1!, {r0}
(511) Read Flash [10001f6c] = 00003453
(512) r0 = 00003453
(512) r1 = 10001f70
(513) 1000022c: c201 stmia r2!, {r0}
(513) Write SRAM [20000208] = 00003453
(514) r2 = 2000020c
(515) 1000022e: 429a cmp r2, r3
(516) 10000230: d3fb bcc 0x1000022a
(517) 1000022a: c901 ldmia r1!, {r0}
(517) Read Flash [10001f70] = 00003443
(518) r0 = 00003443
(518) r1 = 10001f74
(519) 1000022c: c201 stmia r2!, {r0}
(519) Write SRAM [2000020c] = 00003443
(520) r2 = 20000210
(521) 1000022e: 429a cmp r2, r3
(522) 10000230: d3fb bcc 0x1000022a
(523) 1000022a: c901 ldmia r1!, {r0}
(523) Read Flash [10001f74] = 10001b95
(524) r0 = 10001b95
(524) r1 = 10001f78
(525) 1000022c: c201 stmia r2!, {r0}
(525) Write SRAM [20000210] = 10001b95
(526) r2 = 20000214
(527) 1000022e: 429a cmp r2, r3
(528) 10000230: d3fb bcc 0x1000022a
(529) 1000022a: c901 ldmia r1!, {r0}
(529) Read Flash [10001f78] = 00000000
(530) r0 = 00000000
(530) r1 = 10001f7c
(531) 1000022c: c201 stmia r2!, {r0}
(531) Write SRAM [20000214] = 00000000
(532) r2 = 20000218
(533) 1000022e: 429a cmp r2, r3
(534) 10000230: d3fb bcc 0x1000022a
(535) 1000022a: c901 ldmia r1!, {r0}
(535) Read Flash [10001f7c] = 10001be1
(536) r0 = 10001be1
(536) r1 = 10001f80
(537) 1000022c: c201 stmia r2!, {r0}
(537) Write SRAM [20000218] = 10001be1
(538) r2 = 2000021c
(539) 1000022e: 429a cmp r2, r3
(540) 10000230: d3fb bcc 0x1000022a
(541) 1000022a: c901 ldmia r1!, {r0}
(541) Read Flash [10001f80] = 00000000
(542) r0 = 00000000
(542) r1 = 10001f84
(543) 1000022c: c201 stmia r2!, {r0}
(543) Write SRAM [2000021c] = 00000000
(544) r2 = 20000220
(545) 1000022e: 429a cmp r2, r3
(546) 10000230: d3fb bcc 0x1000022a
(547) 1000022a: c901 ldmia r1!, {r0}
(547) Read Flash [10001f84] = 00000100
(548) r0 = 00000100
(548) r1 = 10001f88
(549) 1000022c: c201 stmia r2!, {r0}
(549) Write SRAM [20000220] = 00000100
(550) r2 = 20000224
(551) 1000022e: 429a cmp r2, r3
(552) 10000230: d3fb bcc 0x1000022a
(553) 1000022a: c901 ldmia r1!, {r0}
(553) Read Flash [10001f88] = 00000000
(554) r0 = 00000000
(554) r1 = 10001f8c
(555) 1000022c: c201 stmia r2!, {r0}
(555) Write SRAM [20000224] = 00000000
(556) r2 = 20000228
(557) 1000022e: 429a cmp r2, r3
(558) 10000230: d3fb bcc 0x1000022a
(559) 1000022a: c901 ldmia r1!, {r0}
(559) Read Flash [10001f8c] = 00000000
(560) r0 = 00000000
(560) r1 = 10001f90
(561) 1000022c: c201 stmia r2!, {r0}
(561) Write SRAM [20000228] = 00000000
(562) r2 = 2000022c
(563) 1000022e: 429a cmp r2, r3
(564) 10000230: d3fb bcc 0x1000022a
(565) 1000022a: c901 ldmia r1!, {r0}
(565) Read Flash [10001f90] = 10001921
(566) r0 = 10001921
(566) r1 = 10001f94
(567) 1000022c: c201 stmia r2!, {r0}
(567) Write SRAM [2000022c] = 10001921
(568) r2 = 20000230
(569) 1000022e: 429a cmp r2, r3
(570) 10000230: d3fb bcc 0x1000022a
(571) 1000022a: c901 ldmia r1!, {r0}
(571) Read Flash [10001f94] = 1000170d
(572) r0 = 1000170d
(572) r1 = 10001f98
(573) 1000022c: c201 stmia r2!, {r0}
(573) Write SRAM [20000230] = 1000170d
(574) r2 = 20000234
(575) 1000022e: 429a cmp r2, r3
(576) 10000230: d3fb bcc 0x1000022a
(577) 1000022a: c901 ldmia r1!, {r0}
(577) Read Flash [10001f98] = 100017cd
(578) r0 = 100017cd
(578) r1 = 10001f9c
(579) 1000022c: c201 stmia r2!, {r0}
(579) Write SRAM [20000234] = 100017cd
(580) r2 = 20000238
(581) 1000022e: 429a cmp r2, r3
(582) 10000230: d3fb bcc 0x1000022a
(583) 1000022a: c901 ldmia r1!, {r0}
(583) Read Flash [10001f9c] = 10001891
(584) r0 = 10001891
(584) r1 = 10001fa0
(585) 1000022c: c201 stmia r2!, {r0}
(585) Write SRAM [20000238] = 10001891
(586) r2 = 2000023c
(587) 1000022e: 429a cmp r2, r3
(588) 10000230: d3fb bcc 0x1000022a
(589) 1000022a: c901 ldmia r1!, {r0}
(589) Read Flash [10001fa0] = 100002ed
(590) r0 = 100002ed
(590) r1 = 10001fa4
(591) 1000022c: c201 stmia r2!, {r0}
(591) Write SRAM [2000023c] = 100002ed
(592) r2 = 20000240
(593) 1000022e: 429a cmp r2, r3
(593) nzcv = .11.
(594) 10000230: d3fb bcc 0x1000022a
(595) 10000232: 4770 bx lr
(596) 1000020a: e7f9 b 0x10000200
(597) 10000200: cc0e ldmia r4!, {r1, r2, r3}
(597) Read Flash [10000240] = 10001fa4
(598) r1 = 10001fa4
(598) Read Flash [10000244] = 20040000
(599) r2 = 20040000
(599) Read Flash [10000248] = 20040000
(600) r3 = 20040000
(600) r4 = 1000024c
(601) 10000202: 2900 cmp r1, #0
(601) nzcv = ..1.
(602) 10000204: d002 beq 0x1000020c
(604) 10000206: f000f812 bl 0x1000022e
(604) lr = 1000020a
(605) 1000022e: 429a cmp r2, r3
(605) nzcv = .11.
(606) 10000230: d3fb bcc 0x1000022a
(607) 10000232: 4770 bx lr
(608) 1000020a: e7f9 b 0x10000200
(609) 10000200: cc0e ldmia r4!, {r1, r2, r3}
(609) Read Flash [1000024c] = 10001fa4
(610) r1 = 10001fa4
(610) Read Flash [10000250] = 20041000
(611) r2 = 20041000
(611) Read Flash [10000254] = 20041000
(612) r3 = 20041000
(612) r4 = 10000258
(613) 10000202: 2900 cmp r1, #0
(613) nzcv = ..1.
(614) 10000204: d002 beq 0x1000020c
(616) 10000206: f000f812 bl 0x1000022e
(616) lr = 1000020a
(617) 1000022e: 429a cmp r2, r3
(617) nzcv = .11.
(618) 10000230: d3fb bcc 0x1000022a
(619) 10000232: 4770 bx lr
(620) 1000020a: e7f9 b 0x10000200
(621) 10000200: cc0e ldmia r4!, {r1, r2, r3}
(621) Read Flash [10000258] = 00000000
(622) r1 = 00000000
(622) Read Flash [1000025c] = 480b4770
(623) r2 = 480b4770
(623) Read Flash [10000260] = fa5cf001
(624) r3 = fa5cf001
(624) r4 = 10000264
(625) 10000202: 2900 cmp r1, #0
(626) 10000204: d002 beq 0x1000020c
(627) 1000020c: 491a ldr r1, [pc, #104]
(627) Read Flash [10000278] = 20000240
(628) r1 = 20000240
(629) 1000020e: 4a1b ldr r2, [pc, #108]
(629) Read Flash [1000027c] = 20000610
(630) r2 = 20000610
(631) 10000210: 2000 movs r0, #0
(631) r0 = 00000000
(632) 10000212: e000 b 0x10000216
(633) 10000216: 4291 cmp r1, r2
(633) nzcv = 1...
(634) 10000218: d1fc bne 0x10000214
(635) 10000214: c101 stmia r1!, {r0}
(635) Write SRAM [20000240] = 00000000
(636) r1 = 20000244
(637) 10000216: 4291 cmp r1, r2
(638) 10000218: d1fc bne 0x10000214
(639) 10000214: c101 stmia r1!, {r0}
(639) Write SRAM [20000244] = 00000000
(640) r1 = 20000248
(641) 10000216: 4291 cmp r1, r2
(642) 10000218: d1fc bne 0x10000214
(643) 10000214: c101 stmia r1!, {r0}
(643) Write SRAM [20000248] = 00000000
(644) r1 = 2000024c
(645) 10000216: 4291 cmp r1, r2
(646) 10000218: d1fc bne 0x10000214
(647) 10000214: c101 stmia r1!, {r0}
(647) Write SRAM [2000024c] = 00000000
(648) r1 = 20000250
(649) 10000216: 4291 cmp r1, r2
(650) 10000218: d1fc bne 0x10000214
(651) 10000214: c101 stmia r1!, {r0}
(651) Write SRAM [20000250] = 00000000
(652) r1 = 20000254
(653) 10000216: 4291 cmp r1, r2
(654) 10000218: d1fc bne 0x10000214
(655) 10000214: c101 stmia r1!, {r0}
(655) Write SRAM [20000254] = 00000000
(656) r1 = 20000258
(657) 10000216: 4291 cmp r1, r2
(658) 10000218: d1fc bne 0x10000214
(659) 10000214: c101 stmia r1!, {r0}
(659) Write SRAM [20000258] = 00000000
(660) r1 = 2000025c
(661) 10000216: 4291 cmp r1, r2
(662) 10000218: d1fc bne 0x10000214
(663) 10000214: c101 stmia r1!, {r0}
(663) Write SRAM [2000025c] = 00000000
(664) r1 = 20000260
(665) 10000216: 4291 cmp r1, r2
(666) 10000218: d1fc bne 0x10000214
(667) 10000214: c101 stmia r1!, {r0}
(667) Write SRAM [20000260] = 00000000
(668) r1 = 20000264
(669) 10000216: 4291 cmp r1, r2
(670) 10000218: d1fc bne 0x10000214
(671) 10000214: c101 stmia r1!, {r0}
(671) Write SRAM [20000264] = 00000000
(672) r1 = 20000268
(673) 10000216: 4291 cmp r1, r2
(674) 10000218: d1fc bne 0x10000214
(675) 10000214: c101 stmia r1!, {r0}
(675) Write SRAM [20000268] = 00000000
(676) r1 = 2000026c
(677) 10000216: 4291 cmp r1, r2
(678) 10000218: d1fc bne 0x10000214
(679) 10000214: c101 stmia r1!, {r0}
(679) Write SRAM [2000026c] = 00000000
(680) r1 = 20000270
(681) 10000216: 4291 cmp r1, r2
(682) 10000218: d1fc bne 0x10000214
(683) 10000214: c101 stmia r1!, {r0}
(683) Write SRAM [20000270] = 00000000
(684) r1 = 20000274
(685) 10000216: 4291 cmp r1, r2
(686) 10000218: d1fc bne 0x10000214
(687) 10000214: c101 stmia r1!, {r0}
(687) Write SRAM [20000274] = 00000000
(688) r1 = 20000278
(689) 10000216: 4291 cmp r1, r2
(690) 10000218: d1fc bne 0x10000214
(691) 10000214: c101 stmia r1!, {r0}
(691) Write SRAM [20000278] = 00000000
(692) r1 = 2000027c
(693) 10000216: 4291 cmp r1, r2
(694) 10000218: d1fc bne 0x10000214
(695) 10000214: c101 stmia r1!, {r0}
(695) Write SRAM [2000027c] = 00000000
(696) r1 = 20000280
(697) 10000216: 4291 cmp r1, r2
(698) 10000218: d1fc bne 0x10000214
(699) 10000214: c101 stmia r1!, {r0}
(699) Write SRAM [20000280] = 00000000
(700) r1 = 20000284
(701) 10000216: 4291 cmp r1, r2
(702) 10000218: d1fc bne 0x10000214
(703) 10000214: c101 stmia r1!, {r0}
(703) Write SRAM [20000284] = 00000000
(704) r1 = 20000288
(705) 10000216: 4291 cmp r1, r2
(706) 10000218: d1fc bne 0x10000214
(707) 10000214: c101 stmia r1!, {r0}
(707) Write SRAM [20000288] = 00000000
(708) r1 = 2000028c
(709) 10000216: 4291 cmp r1, r2
(710) 10000218: d1fc bne 0x10000214
(711) 10000214: c101 stmia r1!, {r0}
(711) Write SRAM [2000028c] = 00000000
(712) r1 = 20000290
(713) 10000216: 4291 cmp r1, r2
(714) 10000218: d1fc bne 0x10000214
(715) 10000214: c101 stmia r1!, {r0}
(715) Write SRAM [20000290] = 00000000
(716) r1 = 20000294
(717) 10000216: 4291 cmp r1, r2
(718) 10000218: d1fc bne 0x10000214
(719) 10000214: c101 stmia r1!, {r0}
(719) Write SRAM [20000294] = 00000000
(720) r1 = 20000298
(721) 10000216: 4291 cmp r1, r2
(722) 10000218: d1fc bne 0x10000214
(723) 10000214: c101 stmia r1!, {r0}
(723) Write SRAM [20000298] = 00000000
(724) r1 = 2000029c
(725) 10000216: 4291 cmp r1, r2
(726) 10000218: d1fc bne 0x10000214
(727) 10000214: c101 stmia r1!, {r0}
(727) Write SRAM [2000029c] = 00000000
(728) r1 = 200002a0
(729) 10000216: 4291 cmp r1, r2
(730) 10000218: d1fc bne 0x10000214
(731) 10000214: c101 stmia r1!, {r0}
(731) Write SRAM [200002a0] = 00000000
(732) r1 = 200002a4
(733) 10000216: 4291 cmp r1, r2
(734) 10000218: d1fc bne 0x10000214
(735) 10000214: c101 stmia r1!, {r0}
(735) Write SRAM [200002a4] = 00000000
(736) r1 = 200002a8
(737) 10000216: 4291 cmp r1, r2
(738) 10000218: d1fc bne 0x10000214
(739) 10000214: c101 stmia r1!, {r0}
(739) Write SRAM [200002a8] = 00000000
(740) r1 = 200002ac
(741) 10000216: 4291 cmp r1, r2
(742) 10000218: d1fc bne 0x10000214
(743) 10000214: c101 stmia r1!, {r0}
(743) Write SRAM [200002ac] = 00000000
(744) r1 = 200002b0
(745) 10000216: 4291 cmp r1, r2
(746) 10000218: d1fc bne 0x10000214
(747) 10000214: c101 stmia r1!, {r0}
(747) Write SRAM [200002b0] = 00000000
(748) r1 = 200002b4
(749) 10000216: 4291 cmp r1, r2
(750) 10000218: d1fc bne 0x10000214
(751) 10000214: c101 stmia r1!, {r0}
(751) Write SRAM [200002b4] = 00000000
(752) r1 = 200002b8
(753) 10000216: 4291 cmp r1, r2
(754) 10000218: d1fc bne 0x10000214
(755) 10000214: c101 stmia r1!, {r0}
(755) Write SRAM [200002b8] = 00000000
(756) r1 = 200002bc
(757) 10000216: 4291 cmp r1, r2
(758) 10000218: d1fc bne 0x10000214
(759) 10000214: c101 stmia r1!, {r0}
(759) Write SRAM [200002bc] = 00000000
(760) r1 = 200002c0
(761) 10000216: 4291 cmp r1, r2
(762) 10000218: d1fc bne 0x10000214
(763) 10000214: c101 stmia r1!, {r0}
(763) Write SRAM [200002c0] = 00000000
(764) r1 = 200002c4
(765) 10000216: 4291 cmp r1, r2
(766) 10000218: d1fc bne 0x10000214
(767) 10000214: c101 stmia r1!, {r0}
(767) Write SRAM [200002c4] = 00000000
(768) r1 = 200002c8
(769) 10000216: 4291 cmp r1, r2
(770) 10000218: d1fc bne 0x10000214
(771) 10000214: c101 stmia r1!, {r0}
(771) Write SRAM [200002c8] = 00000000
(772) r1 = 200002cc
(773) 10000216: 4291 cmp r1, r2
(774) 10000218: d1fc bne 0x10000214
(775) 10000214: c101 stmia r1!, {r0}
(775) Write SRAM [200002cc] = 00000000
(776) r1 = 200002d0
(777) 10000216: 4291 cmp r1, r2
(778) 10000218: d1fc bne 0x10000214
(779) 10000214: c101 stmia r1!, {r0}
(779) Write SRAM [200002d0] = 00000000
(780) r1 = 200002d4
(781) 10000216: 4291 cmp r1, r2
(782) 10000218: d1fc bne 0x10000214
(783) 10000214: c101 stmia r1!, {r0}
(783) Write SRAM [200002d4] = 00000000
(784) r1 = 200002d8
(785) 10000216: 4291 cmp r1, r2
(786) 10000218: d1fc bne 0x10000214
(787) 10000214: c101 stmia r1!, {r0}
(787) Write SRAM [200002d8] = 00000000
(788) r1 = 200002dc
(789) 10000216: 4291 cmp r1, r2
(790) 10000218: d1fc bne 0x10000214
(791) 10000214: c101 stmia r1!, {r0}
(791) Write SRAM [200002dc] = 00000000
(792) r1 = 200002e0
(793) 10000216: 4291 cmp r1, r2
(794) 10000218: d1fc bne 0x10000214
(795) 10000214: c101 stmia r1!, {r0}
(795) Write SRAM [200002e0] = 00000000
(796) r1 = 200002e4
(797) 10000216: 4291 cmp r1, r2
(798) 10000218: d1fc bne 0x10000214
(799) 10000214: c101 stmia r1!, {r0}
(799) Write SRAM [200002e4] = 00000000
(800) r1 = 200002e8
(801) 10000216: 4291 cmp r1, r2
(802) 10000218: d1fc bne 0x10000214
(803) 10000214: c101 stmia r1!, {r0}
(803) Write SRAM [200002e8] = 00000000
(804) r1 = 200002ec
(805) 10000216: 4291 cmp r1, r2
(806) 10000218: d1fc bne 0x10000214
(807) 10000214: c101 stmia r1!, {r0}
(807) Write SRAM [200002ec] = 00000000
(808) r1 = 200002f0
(809) 10000216: 4291 cmp r1, r2
(810) 10000218: d1fc bne 0x10000214
(811) 10000214: c101 stmia r1!, {r0}
(811) Write SRAM [200002f0] = 00000000
(812) r1 = 200002f4
(813) 10000216: 4291 cmp r1, r2
(814) 10000218: d1fc bne 0x10000214
(815) 10000214: c101 stmia r1!, {r0}
(815) Write SRAM [200002f4] = 00000000
(816) r1 = 200002f8
(817) 10000216: 4291 cmp r1, r2
(818) 10000218: d1fc bne 0x10000214
(819) 10000214: c101 stmia r1!, {r0}
(819) Write SRAM [200002f8] = 00000000
(820) r1 = 200002fc
(821) 10000216: 4291 cmp r1, r2
(822) 10000218: d1fc bne 0x10000214
(823) 10000214: c101 stmia r1!, {r0}
(823) Write SRAM [200002fc] = 00000000
(824) r1 = 20000300
(825) 10000216: 4291 cmp r1, r2
(826) 10000218: d1fc bne 0x10000214
(827) 10000214: c101 stmia r1!, {r0}
(827) Write SRAM [20000300] = 00000000
(828) r1 = 20000304
(829) 10000216: 4291 cmp r1, r2
(830) 10000218: d1fc bne 0x10000214
(831) 10000214: c101 stmia r1!, {r0}
(831) Write SRAM [20000304] = 00000000
(832) r1 = 20000308
(833) 10000216: 4291 cmp r1, r2
(834) 10000218: d1fc bne 0x10000214
(835) 10000214: c101 stmia r1!, {r0}
(835) Write SRAM [20000308] = 00000000
(836) r1 = 2000030c
(837) 10000216: 4291 cmp r1, r2
(838) 10000218: d1fc bne 0x10000214
(839) 10000214: c101 stmia r1!, {r0}
(839) Write SRAM [2000030c] = 00000000
(840) r1 = 20000310
(841) 10000216: 4291 cmp r1, r2
(842) 10000218: d1fc bne 0x10000214
(843) 10000214: c101 stmia r1!, {r0}
(843) Write SRAM [20000310] = 00000000
(844) r1 = 20000314
(845) 10000216: 4291 cmp r1, r2
(846) 10000218: d1fc bne 0x10000214
(847) 10000214: c101 stmia r1!, {r0}
(847) Write SRAM [20000314] = 00000000
(848) r1 = 20000318
(849) 10000216: 4291 cmp r1, r2
(850) 10000218: d1fc bne 0x10000214
(851) 10000214: c101 stmia r1!, {r0}
(851) Write SRAM [20000318] = 00000000
(852) r1 = 2000031c
(853) 10000216: 4291 cmp r1, r2
(854) 10000218: d1fc bne 0x10000214
(855) 10000214: c101 stmia r1!, {r0}
(855) Write SRAM [2000031c] = 00000000
(856) r1 = 20000320
(857) 10000216: 4291 cmp r1, r2
(858) 10000218: d1fc bne 0x10000214
(859) 10000214: c101 stmia r1!, {r0}
(859) Write SRAM [20000320] = 00000000
(860) r1 = 20000324
(861) 10000216: 4291 cmp r1, r2
(862) 10000218: d1fc bne 0x10000214
(863) 10000214: c101 stmia r1!, {r0}
(863) Write SRAM [20000324] = 00000000
(864) r1 = 20000328
(865) 10000216: 4291 cmp r1, r2
(866) 10000218: d1fc bne 0x10000214
(867) 10000214: c101 stmia r1!, {r0}
(867) Write SRAM [20000328] = 00000000
(868) r1 = 2000032c
(869) 10000216: 4291 cmp r1, r2
(870) 10000218: d1fc bne 0x10000214
(871) 10000214: c101 stmia r1!, {r0}
(871) Write SRAM [2000032c] = 00000000
(872) r1 = 20000330
(873) 10000216: 4291 cmp r1, r2
(874) 10000218: d1fc bne 0x10000214
(875) 10000214: c101 stmia r1!, {r0}
(875) Write SRAM [20000330] = 00000000
(876) r1 = 20000334
(877) 10000216: 4291 cmp r1, r2
(878) 10000218: d1fc bne 0x10000214
(879) 10000214: c101 stmia r1!, {r0}
(879) Write SRAM [20000334] = 00000000
(880) r1 = 20000338
(881) 10000216: 4291 cmp r1, r2
(882) 10000218: d1fc bne 0x10000214
(883) 10000214: c101 stmia r1!, {r0}
(883) Write SRAM [20000338] = 00000000
(884) r1 = 2000033c
(885) 10000216: 4291 cmp r1, r2
(886) 10000218: d1fc bne 0x10000214
(887) 10000214: c101 stmia r1!, {r0}
(887) Write SRAM [2000033c] = 00000000
(888) r1 = 20000340
(889) 10000216: 4291 cmp r1, r2
(890) 10000218: d1fc bne 0x10000214
(891) 10000214: c101 stmia r1!, {r0}
(891) Write SRAM [20000340] = 00000000
(892) r1 = 20000344
(893) 10000216: 4291 cmp r1, r2
(894) 10000218: d1fc bne 0x10000214
(895) 10000214: c101 stmia r1!, {r0}
(895) Write SRAM [20000344] = 00000000
(896) r1 = 20000348
(897) 10000216: 4291 cmp r1, r2
(898) 10000218: d1fc bne 0x10000214
(899) 10000214: c101 stmia r1!, {r0}
(899) Write SRAM [20000348] = 00000000
(900) r1 = 2000034c
(901) 10000216: 4291 cmp r1, r2
(902) 10000218: d1fc bne 0x10000214
(903) 10000214: c101 stmia r1!, {r0}
(903) Write SRAM [2000034c] = 00000000
(904) r1 = 20000350
(905) 10000216: 4291 cmp r1, r2
(906) 10000218: d1fc bne 0x10000214
(907) 10000214: c101 stmia r1!, {r0}
(907) Write SRAM [20000350] = 00000000
(908) r1 = 20000354
(909) 10000216: 4291 cmp r1, r2
(910) 10000218: d1fc bne 0x10000214
(911) 10000214: c101 stmia r1!, {r0}
(911) Write SRAM [20000354] = 00000000
(912) r1 = 20000358
(913) 10000216: 4291 cmp r1, r2
(914) 10000218: d1fc bne 0x10000214
(915) 10000214: c101 stmia r1!, {r0}
(915) Write SRAM [20000358] = 00000000
(916) r1 = 2000035c
(917) 10000216: 4291 cmp r1, r2
(918) 10000218: d1fc bne 0x10000214
(919) 10000214: c101 stmia r1!, {r0}
(919) Write SRAM [2000035c] = 00000000
(920) r1 = 20000360
(921) 10000216: 4291 cmp r1, r2
(922) 10000218: d1fc bne 0x10000214
(923) 10000214: c101 stmia r1!, {r0}
(923) Write SRAM [20000360] = 00000000
(924) r1 = 20000364
(925) 10000216: 4291 cmp r1, r2
(926) 10000218: d1fc bne 0x10000214
(927) 10000214: c101 stmia r1!, {r0}
(927) Write SRAM [20000364] = 00000000
(928) r1 = 20000368
(929) 10000216: 4291 cmp r1, r2
(930) 10000218: d1fc bne 0x10000214
(931) 10000214: c101 stmia r1!, {r0}
(931) Write SRAM [20000368] = 00000000
(932) r1 = 2000036c
(933) 10000216: 4291 cmp r1, r2
(934) 10000218: d1fc bne 0x10000214
(935) 10000214: c101 stmia r1!, {r0}
(935) Write SRAM [2000036c] = 00000000
(936) r1 = 20000370
(937) 10000216: 4291 cmp r1, r2
(938) 10000218: d1fc bne 0x10000214
(939) 10000214: c101 stmia r1!, {r0}
(939) Write SRAM [20000370] = 00000000
(940) r1 = 20000374
(941) 10000216: 4291 cmp r1, r2
(942) 10000218: d1fc bne 0x10000214
(943) 10000214: c101 stmia r1!, {r0}
(943) Write SRAM [20000374] = 00000000
(944) r1 = 20000378
(945) 10000216: 4291 cmp r1, r2
(946) 10000218: d1fc bne 0x10000214
(947) 10000214: c101 stmia r1!, {r0}
(947) Write SRAM [20000378] = 00000000
(948) r1 = 2000037c
(949) 10000216: 4291 cmp r1, r2
(950) 10000218: d1fc bne 0x10000214
(951) 10000214: c101 stmia r1!, {r0}
(951) Write SRAM [2000037c] = 00000000
(952) r1 = 20000380
(953) 10000216: 4291 cmp r1, r2
(954) 10000218: d1fc bne 0x10000214
(955) 10000214: c101 stmia r1!, {r0}
(955) Write SRAM [20000380] = 00000000
(956) r1 = 20000384
(957) 10000216: 4291 cmp r1, r2
(958) 10000218: d1fc bne 0x10000214
(959) 10000214: c101 stmia r1!, {r0}
(959) Write SRAM [20000384] = 00000000
(960) r1 = 20000388
(961) 10000216: 4291 cmp r1, r2
(962) 10000218: d1fc bne 0x10000214
(963) 10000214: c101 stmia r1!, {r0}
(963) Write SRAM [20000388] = 00000000
(964) r1 = 2000038c
(965) 10000216: 4291 cmp r1, r2
(966) 10000218: d1fc bne 0x10000214
(967) 10000214: c101 stmia r1!, {r0}
(967) Write SRAM [2000038c] = 00000000
(968) r1 = 20000390
(969) 10000216: 4291 cmp r1, r2
(970) 10000218: d1fc bne 0x10000214
(971) 10000214: c101 stmia r1!, {r0}
(971) Write SRAM [20000390] = 00000000
(972) r1 = 20000394
(973) 10000216: 4291 cmp r1, r2
(974) 10000218: d1fc bne 0x10000214
(975) 10000214: c101 stmia r1!, {r0}
(975) Write SRAM [20000394] = 00000000
(976) r1 = 20000398
(977) 10000216: 4291 cmp r1, r2
(978) 10000218: d1fc bne 0x10000214
(979) 10000214: c101 stmia r1!, {r0}
(979) Write SRAM [20000398] = 00000000
(980) r1 = 2000039c
(981) 10000216: 4291 cmp r1, r2
(982) 10000218: d1fc bne 0x10000214
(983) 10000214: c101 stmia r1!, {r0}
(983) Write SRAM [2000039c] = 00000000
(984) r1 = 200003a0
(985) 10000216: 4291 cmp r1, r2
(986) 10000218: d1fc bne 0x10000214
(987) 10000214: c101 stmia r1!, {r0}
(987) Write SRAM [200003a0] = 00000000
(988) r1 = 200003a4
(989) 10000216: 4291 cmp r1, r2
(990) 10000218: d1fc bne 0x10000214
(991) 10000214: c101 stmia r1!, {r0}
(991) Write SRAM [200003a4] = 00000000
(992) r1 = 200003a8
(993) 10000216: 4291 cmp r1, r2
(994) 10000218: d1fc bne 0x10000214
(995) 10000214: c101 stmia r1!, {r0}
(995) Write SRAM [200003a8] = 00000000
(996) r1 = 200003ac
(997) 10000216: 4291 cmp r1, r2
(998) 10000218: d1fc bne 0x10000214
(999) 10000214: c101 stmia r1!, {r0}
(999) Write SRAM [200003ac] = 00000000
(1000) r1 = 200003b0
(1001) 10000216: 4291 cmp r1, r2
(1002) 10000218: d1fc bne 0x10000214
(1003) 10000214: c101 stmia r1!, {r0}
(1003) Write SRAM [200003b0] = 00000000
(1004) r1 = 200003b4
(1005) 10000216: 4291 cmp r1, r2
(1006) 10000218: d1fc bne 0x10000214
(1007) 10000214: c101 stmia r1!, {r0}
(1007) Write SRAM [200003b4] = 00000000
(1008) r1 = 200003b8
(1009) 10000216: 4291 cmp r1, r2
(1010) 10000218: d1fc bne 0x10000214
(1011) 10000214: c101 stmia r1!, {r0}
(1011) Write SRAM [200003b8] = 00000000
(1012) r1 = 200003bc
(1013) 10000216: 4291 cmp r1, r2
(1014) 10000218: d1fc bne 0x10000214
(1015) 10000214: c101 stmia r1!, {r0}
(1015) Write SRAM [200003bc] = 00000000
(1016) r1 = 200003c0
(1017) 10000216: 4291 cmp r1, r2
(1018) 10000218: d1fc bne 0x10000214
(1019) 10000214: c101 stmia r1!, {r0}
(1019) Write SRAM [200003c0] = 00000000
(1020) r1 = 200003c4
(1021) 10000216: 4291 cmp r1, r2
(1022) 10000218: d1fc bne 0x10000214
(1023) 10000214: c101 stmia r1!, {r0}
(1023) Write SRAM [200003c4] = 00000000
(1024) r1 = 200003c8
(1025) 10000216: 4291 cmp r1, r2
(1026) 10000218: d1fc bne 0x10000214
(1027) 10000214: c101 stmia r1!, {r0}
(1027) Write SRAM [200003c8] = 00000000
(1028) r1 = 200003cc
(1029) 10000216: 4291 cmp r1, r2
(1030) 10000218: d1fc bne 0x10000214
(1031) 10000214: c101 stmia r1!, {r0}
(1031) Write SRAM [200003cc] = 00000000
(1032) r1 = 200003d0
(1033) 10000216: 4291 cmp r1, r2
(1034) 10000218: d1fc bne 0x10000214
(1035) 10000214: c101 stmia r1!, {r0}
(1035) Write SRAM [200003d0] = 00000000
(1036) r1 = 200003d4
(1037) 10000216: 4291 cmp r1, r2
(1038) 10000218: d1fc bne 0x10000214
(1039) 10000214: c101 stmia r1!, {r0}
(1039) Write SRAM [200003d4] = 00000000
(1040) r1 = 200003d8
(1041) 10000216: 4291 cmp r1, r2
(1042) 10000218: d1fc bne 0x10000214
(1043) 10000214: c101 stmia r1!, {r0}
(1043) Write SRAM [200003d8] = 00000000
(1044) r1 = 200003dc
(1045) 10000216: 4291 cmp r1, r2
(1046) 10000218: d1fc bne 0x10000214
(1047) 10000214: c101 stmia r1!, {r0}
(1047) Write SRAM [200003dc] = 00000000
(1048) r1 = 200003e0
(1049) 10000216: 4291 cmp r1, r2
(1050) 10000218: d1fc bne 0x10000214
(1051) 10000214: c101 stmia r1!, {r0}
(1051) Write SRAM [200003e0] = 00000000
(1052) r1 = 200003e4
(1053) 10000216: 4291 cmp r1, r2
(1054) 10000218: d1fc bne 0x10000214
(1055) 10000214: c101 stmia r1!, {r0}
(1055) Write SRAM [200003e4] = 00000000
(1056) r1 = 200003e8
(1057) 10000216: 4291 cmp r1, r2
(1058) 10000218: d1fc bne 0x10000214
(1059) 10000214: c101 stmia r1!, {r0}
(1059) Write SRAM [200003e8] = 00000000
(1060) r1 = 200003ec
(1061) 10000216: 4291 cmp r1, r2
(1062) 10000218: d1fc bne 0x10000214
(1063) 10000214: c101 stmia r1!, {r0}
(1063) Write SRAM [200003ec] = 00000000
(1064) r1 = 200003f0
(1065) 10000216: 4291 cmp r1, r2
(1066) 10000218: d1fc bne 0x10000214
(1067) 10000214: c101 stmia r1!, {r0}
(1067) Write SRAM [200003f0] = 00000000
(1068) r1 = 200003f4
(1069) 10000216: 4291 cmp r1, r2
(1070) 10000218: d1fc bne 0x10000214
(1071) 10000214: c101 stmia r1!, {r0}
(1071) Write SRAM [200003f4] = 00000000
(1072) r1 = 200003f8
(1073) 10000216: 4291 cmp r1, r2
(1074) 10000218: d1fc bne 0x10000214
(1075) 10000214: c101 stmia r1!, {r0}
(1075) Write SRAM [200003f8] = 00000000
(1076) r1 = 200003fc
(1077) 10000216: 4291 cmp r1, r2
(1078) 10000218: d1fc bne 0x10000214
(1079) 10000214: c101 stmia r1!, {r0}
(1079) Write SRAM [200003fc] = 00000000
(1080) r1 = 20000400
(1081) 10000216: 4291 cmp r1, r2
(1082) 10000218: d1fc bne 0x10000214
(1083) 10000214: c101 stmia r1!, {r0}
(1083) Write SRAM [20000400] = 00000000
(1084) r1 = 20000404
(1085) 10000216: 4291 cmp r1, r2
(1086) 10000218: d1fc bne 0x10000214
(1087) 10000214: c101 stmia r1!, {r0}
(1087) Write SRAM [20000404] = 00000000
(1088) r1 = 20000408
(1089) 10000216: 4291 cmp r1, r2
(1090) 10000218: d1fc bne 0x10000214
(1091) 10000214: c101 stmia r1!, {r0}
(1091) Write SRAM [20000408] = 00000000
(1092) r1 = 2000040c
(1093) 10000216: 4291 cmp r1, r2
(1094) 10000218: d1fc bne 0x10000214
(1095) 10000214: c101 stmia r1!, {r0}
(1095) Write SRAM [2000040c] = 00000000
(1096) r1 = 20000410
(1097) 10000216: 4291 cmp r1, r2
(1098) 10000218: d1fc bne 0x10000214
(1099) 10000214: c101 stmia r1!, {r0}
(1099) Write SRAM [20000410] = 00000000
(1100) r1 = 20000414
(1101) 10000216: 4291 cmp r1, r2
(1102) 10000218: d1fc bne 0x10000214
(1103) 10000214: c101 stmia r1!, {r0}
(1103) Write SRAM [20000414] = 00000000
(1104) r1 = 20000418
(1105) 10000216: 4291 cmp r1, r2
(1106) 10000218: d1fc bne 0x10000214
(1107) 10000214: c101 stmia r1!, {r0}
(1107) Write SRAM [20000418] = 00000000
(1108) r1 = 2000041c
(1109) 10000216: 4291 cmp r1, r2
(1110) 10000218: d1fc bne 0x10000214
(1111) 10000214: c101 stmia r1!, {r0}
(1111) Write SRAM [2000041c] = 00000000
(1112) r1 = 20000420
(1113) 10000216: 4291 cmp r1, r2
(1114) 10000218: d1fc bne 0x10000214
(1115) 10000214: c101 stmia r1!, {r0}
(1115) Write SRAM [20000420] = 00000000
(1116) r1 = 20000424
(1117) 10000216: 4291 cmp r1, r2
(1118) 10000218: d1fc bne 0x10000214
(1119) 10000214: c101 stmia r1!, {r0}
(1119) Write SRAM [20000424] = 00000000
(1120) r1 = 20000428
(1121) 10000216: 4291 cmp r1, r2
(1122) 10000218: d1fc bne 0x10000214
(1123) 10000214: c101 stmia r1!, {r0}
(1123) Write SRAM [20000428] = 00000000
(1124) r1 = 2000042c
(1125) 10000216: 4291 cmp r1, r2
(1126) 10000218: d1fc bne 0x10000214
(1127) 10000214: c101 stmia r1!, {r0}
(1127) Write SRAM [2000042c] = 00000000
(1128) r1 = 20000430
(1129) 10000216: 4291 cmp r1, r2
(1130) 10000218: d1fc bne 0x10000214
(1131) 10000214: c101 stmia r1!, {r0}
(1131) Write SRAM [20000430] = 00000000
(1132) r1 = 20000434
(1133) 10000216: 4291 cmp r1, r2
(1134) 10000218: d1fc bne 0x10000214
(1135) 10000214: c101 stmia r1!, {r0}
(1135) Write SRAM [20000434] = 00000000
(1136) r1 = 20000438
(1137) 10000216: 4291 cmp r1, r2
(1138) 10000218: d1fc bne 0x10000214
(1139) 10000214: c101 stmia r1!, {r0}
(1139) Write SRAM [20000438] = 00000000
(1140) r1 = 2000043c
(1141) 10000216: 4291 cmp r1, r2
(1142) 10000218: d1fc bne 0x10000214
(1143) 10000214: c101 stmia r1!, {r0}
(1143) Write SRAM [2000043c] = 00000000
(1144) r1 = 20000440
(1145) 10000216: 4291 cmp r1, r2
(1146) 10000218: d1fc bne 0x10000214
(1147) 10000214: c101 stmia r1!, {r0}
(1147) Write SRAM [20000440] = 00000000
(1148) r1 = 20000444
(1149) 10000216: 4291 cmp r1, r2
(1150) 10000218: d1fc bne 0x10000214
(1151) 10000214: c101 stmia r1!, {r0}
(1151) Write SRAM [20000444] = 00000000
(1152) r1 = 20000448
(1153) 10000216: 4291 cmp r1, r2
(1154) 10000218: d1fc bne 0x10000214
(1155) 10000214: c101 stmia r1!, {r0}
(1155) Write SRAM [20000448] = 00000000
(1156) r1 = 2000044c
(1157) 10000216: 4291 cmp r1, r2
(1158) 10000218: d1fc bne 0x10000214
(1159) 10000214: c101 stmia r1!, {r0}
(1159) Write SRAM [2000044c] = 00000000
(1160) r1 = 20000450
(1161) 10000216: 4291 cmp r1, r2
(1162) 10000218: d1fc bne 0x10000214
(1163) 10000214: c101 stmia r1!, {r0}
(1163) Write SRAM [20000450] = 00000000
(1164) r1 = 20000454
(1165) 10000216: 4291 cmp r1, r2
(1166) 10000218: d1fc bne 0x10000214
(1167) 10000214: c101 stmia r1!, {r0}
(1167) Write SRAM [20000454] = 00000000
(1168) r1 = 20000458
(1169) 10000216: 4291 cmp r1, r2
(1170) 10000218: d1fc bne 0x10000214
(1171) 10000214: c101 stmia r1!, {r0}
(1171) Write SRAM [20000458] = 00000000
(1172) r1 = 2000045c
(1173) 10000216: 4291 cmp r1, r2
(1174) 10000218: d1fc bne 0x10000214
(1175) 10000214: c101 stmia r1!, {r0}
(1175) Write SRAM [2000045c] = 00000000
(1176) r1 = 20000460
(1177) 10000216: 4291 cmp r1, r2
(1178) 10000218: d1fc bne 0x10000214
(1179) 10000214: c101 stmia r1!, {r0}
(1179) Write SRAM [20000460] = 00000000
(1180) r1 = 20000464
(1181) 10000216: 4291 cmp r1, r2
(1182) 10000218: d1fc bne 0x10000214
(1183) 10000214: c101 stmia r1!, {r0}
(1183) Write SRAM [20000464] = 00000000
(1184) r1 = 20000468
(1185) 10000216: 4291 cmp r1, r2
(1186) 10000218: d1fc bne 0x10000214
(1187) 10000214: c101 stmia r1!, {r0}
(1187) Write SRAM [20000468] = 00000000
(1188) r1 = 2000046c
(1189) 10000216: 4291 cmp r1, r2
(1190) 10000218: d1fc bne 0x10000214
(1191) 10000214: c101 stmia r1!, {r0}
(1191) Write SRAM [2000046c] = 00000000
(1192) r1 = 20000470
(1193) 10000216: 4291 cmp r1, r2
(1194) 10000218: d1fc bne 0x10000214
(1195) 10000214: c101 stmia r1!, {r0}
(1195) Write SRAM [20000470] = 00000000
(1196) r1 = 20000474
(1197) 10000216: 4291 cmp r1, r2
(1198) 10000218: d1fc bne 0x10000214
(1199) 10000214: c101 stmia r1!, {r0}
(1199) Write SRAM [20000474] = 00000000
(1200) r1 = 20000478
(1201) 10000216: 4291 cmp r1, r2
(1202) 10000218: d1fc bne 0x10000214
(1203) 10000214: c101 stmia r1!, {r0}
(1203) Write SRAM [20000478] = 00000000
(1204) r1 = 2000047c
(1205) 10000216: 4291 cmp r1, r2
(1206) 10000218: d1fc bne 0x10000214
(1207) 10000214: c101 stmia r1!, {r0}
(1207) Write SRAM [2000047c] = 00000000
(1208) r1 = 20000480
(1209) 10000216: 4291 cmp r1, r2
(1210) 10000218: d1fc bne 0x10000214
(1211) 10000214: c101 stmia r1!, {r0}
(1211) Write SRAM [20000480] = 00000000
(1212) r1 = 20000484
(1213) 10000216: 4291 cmp r1, r2
(1214) 10000218: d1fc bne 0x10000214
(1215) 10000214: c101 stmia r1!, {r0}
(1215) Write SRAM [20000484] = 00000000
(1216) r1 = 20000488
(1217) 10000216: 4291 cmp r1, r2
(1218) 10000218: d1fc bne 0x10000214
(1219) 10000214: c101 stmia r1!, {r0}
(1219) Write SRAM [20000488] = 00000000
(1220) r1 = 2000048c
(1221) 10000216: 4291 cmp r1, r2
(1222) 10000218: d1fc bne 0x10000214
(1223) 10000214: c101 stmia r1!, {r0}
(1223) Write SRAM [2000048c] = 00000000
(1224) r1 = 20000490
(1225) 10000216: 4291 cmp r1, r2
(1226) 10000218: d1fc bne 0x10000214
(1227) 10000214: c101 stmia r1!, {r0}
(1227) Write SRAM [20000490] = 00000000
(1228) r1 = 20000494
(1229) 10000216: 4291 cmp r1, r2
(1230) 10000218: d1fc bne 0x10000214
(1231) 10000214: c101 stmia r1!, {r0}
(1231) Write SRAM [20000494] = 00000000
(1232) r1 = 20000498
(1233) 10000216: 4291 cmp r1, r2
(1234) 10000218: d1fc bne 0x10000214
(1235) 10000214: c101 stmia r1!, {r0}
(1235) Write SRAM [20000498] = 00000000
(1236) r1 = 2000049c
(1237) 10000216: 4291 cmp r1, r2
(1238) 10000218: d1fc bne 0x10000214
(1239) 10000214: c101 stmia r1!, {r0}
(1239) Write SRAM [2000049c] = 00000000
(1240) r1 = 200004a0
(1241) 10000216: 4291 cmp r1, r2
(1242) 10000218: d1fc bne 0x10000214
(1243) 10000214: c101 stmia r1!, {r0}
(1243) Write SRAM [200004a0] = 00000000
(1244) r1 = 200004a4
(1245) 10000216: 4291 cmp r1, r2
(1246) 10000218: d1fc bne 0x10000214
(1247) 10000214: c101 stmia r1!, {r0}
(1247) Write SRAM [200004a4] = 00000000
(1248) r1 = 200004a8
(1249) 10000216: 4291 cmp r1, r2
(1250) 10000218: d1fc bne 0x10000214
(1251) 10000214: c101 stmia r1!, {r0}
(1251) Write SRAM [200004a8] = 00000000
(1252) r1 = 200004ac
(1253) 10000216: 4291 cmp r1, r2
(1254) 10000218: d1fc bne 0x10000214
(1255) 10000214: c101 stmia r1!, {r0}
(1255) Write SRAM [200004ac] = 00000000
(1256) r1 = 200004b0
(1257) 10000216: 4291 cmp r1, r2
(1258) 10000218: d1fc bne 0x10000214
(1259) 10000214: c101 stmia r1!, {r0}
(1259) Write SRAM [200004b0] = 00000000
(1260) r1 = 200004b4
(1261) 10000216: 4291 cmp r1, r2
(1262) 10000218: d1fc bne 0x10000214
(1263) 10000214: c101 stmia r1!, {r0}
(1263) Write SRAM [200004b4] = 00000000
(1264) r1 = 200004b8
(1265) 10000216: 4291 cmp r1, r2
(1266) 10000218: d1fc bne 0x10000214
(1267) 10000214: c101 stmia r1!, {r0}
(1267) Write SRAM [200004b8] = 00000000
(1268) r1 = 200004bc
(1269) 10000216: 4291 cmp r1, r2
(1270) 10000218: d1fc bne 0x10000214
(1271) 10000214: c101 stmia r1!, {r0}
(1271) Write SRAM [200004bc] = 00000000
(1272) r1 = 200004c0
(1273) 10000216: 4291 cmp r1, r2
(1274) 10000218: d1fc bne 0x10000214
(1275) 10000214: c101 stmia r1!, {r0}
(1275) Write SRAM [200004c0] = 00000000
(1276) r1 = 200004c4
(1277) 10000216: 4291 cmp r1, r2
(1278) 10000218: d1fc bne 0x10000214
(1279) 10000214: c101 stmia r1!, {r0}
(1279) Write SRAM [200004c4] = 00000000
(1280) r1 = 200004c8
(1281) 10000216: 4291 cmp r1, r2
(1282) 10000218: d1fc bne 0x10000214
(1283) 10000214: c101 stmia r1!, {r0}
(1283) Write SRAM [200004c8] = 00000000
(1284) r1 = 200004cc
(1285) 10000216: 4291 cmp r1, r2
(1286) 10000218: d1fc bne 0x10000214
(1287) 10000214: c101 stmia r1!, {r0}
(1287) Write SRAM [200004cc] = 00000000
(1288) r1 = 200004d0
(1289) 10000216: 4291 cmp r1, r2
(1290) 10000218: d1fc bne 0x10000214
(1291) 10000214: c101 stmia r1!, {r0}
(1291) Write SRAM [200004d0] = 00000000
(1292) r1 = 200004d4
(1293) 10000216: 4291 cmp r1, r2
(1294) 10000218: d1fc bne 0x10000214
(1295) 10000214: c101 stmia r1!, {r0}
(1295) Write SRAM [200004d4] = 00000000
(1296) r1 = 200004d8
(1297) 10000216: 4291 cmp r1, r2
(1298) 10000218: d1fc bne 0x10000214
(1299) 10000214: c101 stmia r1!, {r0}
(1299) Write SRAM [200004d8] = 00000000
(1300) r1 = 200004dc
(1301) 10000216: 4291 cmp r1, r2
(1302) 10000218: d1fc bne 0x10000214
(1303) 10000214: c101 stmia r1!, {r0}
(1303) Write SRAM [200004dc] = 00000000
(1304) r1 = 200004e0
(1305) 10000216: 4291 cmp r1, r2
(1306) 10000218: d1fc bne 0x10000214
(1307) 10000214: c101 stmia r1!, {r0}
(1307) Write SRAM [200004e0] = 00000000
(1308) r1 = 200004e4
(1309) 10000216: 4291 cmp r1, r2
(1310) 10000218: d1fc bne 0x10000214
(1311) 10000214: c101 stmia r1!, {r0}
(1311) Write SRAM [200004e4] = 00000000
(1312) r1 = 200004e8
(1313) 10000216: 4291 cmp r1, r2
(1314) 10000218: d1fc bne 0x10000214
(1315) 10000214: c101 stmia r1!, {r0}
(1315) Write SRAM [200004e8] = 00000000
(1316) r1 = 200004ec
(1317) 10000216: 4291 cmp r1, r2
(1318) 10000218: d1fc bne 0x10000214
(1319) 10000214: c101 stmia r1!, {r0}
(1319) Write SRAM [200004ec] = 00000000
(1320) r1 = 200004f0
(1321) 10000216: 4291 cmp r1, r2
(1322) 10000218: d1fc bne 0x10000214
(1323) 10000214: c101 stmia r1!, {r0}
(1323) Write SRAM [200004f0] = 00000000
(1324) r1 = 200004f4
(1325) 10000216: 4291 cmp r1, r2
(1326) 10000218: d1fc bne 0x10000214
(1327) 10000214: c101 stmia r1!, {r0}
(1327) Write SRAM [200004f4] = 00000000
(1328) r1 = 200004f8
(1329) 10000216: 4291 cmp r1, r2
(1330) 10000218: d1fc bne 0x10000214
(1331) 10000214: c101 stmia r1!, {r0}
(1331) Write SRAM [200004f8] = 00000000
(1332) r1 = 200004fc
(1333) 10000216: 4291 cmp r1, r2
(1334) 10000218: d1fc bne 0x10000214
(1335) 10000214: c101 stmia r1!, {r0}
(1335) Write SRAM [200004fc] = 00000000
(1336) r1 = 20000500
(1337) 10000216: 4291 cmp r1, r2
(1338) 10000218: d1fc bne 0x10000214
(1339) 10000214: c101 stmia r1!, {r0}
(1339) Write SRAM [20000500] = 00000000
(1340) r1 = 20000504
(1341) 10000216: 4291 cmp r1, r2
(1342) 10000218: d1fc bne 0x10000214
(1343) 10000214: c101 stmia r1!, {r0}
(1343) Write SRAM [20000504] = 00000000
(1344) r1 = 20000508
(1345) 10000216: 4291 cmp r1, r2
(1346) 10000218: d1fc bne 0x10000214
(1347) 10000214: c101 stmia r1!, {r0}
(1347) Write SRAM [20000508] = 00000000
(1348) r1 = 2000050c
(1349) 10000216: 4291 cmp r1, r2
(1350) 10000218: d1fc bne 0x10000214
(1351) 10000214: c101 stmia r1!, {r0}
(1351) Write SRAM [2000050c] = 00000000
(1352) r1 = 20000510
(1353) 10000216: 4291 cmp r1, r2
(1354) 10000218: d1fc bne 0x10000214
(1355) 10000214: c101 stmia r1!, {r0}
(1355) Write SRAM [20000510] = 00000000
(1356) r1 = 20000514
(1357) 10000216: 4291 cmp r1, r2
(1358) 10000218: d1fc bne 0x10000214
(1359) 10000214: c101 stmia r1!, {r0}
(1359) Write SRAM [20000514] = 00000000
(1360) r1 = 20000518
(1361) 10000216: 4291 cmp r1, r2
(1362) 10000218: d1fc bne 0x10000214
(1363) 10000214: c101 stmia r1!, {r0}
(1363) Write SRAM [20000518] = 00000000
(1364) r1 = 2000051c
(1365) 10000216: 4291 cmp r1, r2
(1366) 10000218: d1fc bne 0x10000214
(1367) 10000214: c101 stmia r1!, {r0}
(1367) Write SRAM [2000051c] = 00000000
(1368) r1 = 20000520
(1369) 10000216: 4291 cmp r1, r2
(1370) 10000218: d1fc bne 0x10000214
(1371) 10000214: c101 stmia r1!, {r0}
(1371) Write SRAM [20000520] = 00000000
(1372) r1 = 20000524
(1373) 10000216: 4291 cmp r1, r2
(1374) 10000218: d1fc bne 0x10000214
(1375) 10000214: c101 stmia r1!, {r0}
(1375) Write SRAM [20000524] = 00000000
(1376) r1 = 20000528
(1377) 10000216: 4291 cmp r1, r2
(1378) 10000218: d1fc bne 0x10000214
(1379) 10000214: c101 stmia r1!, {r0}
(1379) Write SRAM [20000528] = 00000000
(1380) r1 = 2000052c
(1381) 10000216: 4291 cmp r1, r2
(1382) 10000218: d1fc bne 0x10000214
(1383) 10000214: c101 stmia r1!, {r0}
(1383) Write SRAM [2000052c] = 00000000
(1384) r1 = 20000530
(1385) 10000216: 4291 cmp r1, r2
(1386) 10000218: d1fc bne 0x10000214
(1387) 10000214: c101 stmia r1!, {r0}
(1387) Write SRAM [20000530] = 00000000
(1388) r1 = 20000534
(1389) 10000216: 4291 cmp r1, r2
(1390) 10000218: d1fc bne 0x10000214
(1391) 10000214: c101 stmia r1!, {r0}
(1391) Write SRAM [20000534] = 00000000
(1392) r1 = 20000538
(1393) 10000216: 4291 cmp r1, r2
(1394) 10000218: d1fc bne 0x10000214
(1395) 10000214: c101 stmia r1!, {r0}
(1395) Write SRAM [20000538] = 00000000
(1396) r1 = 2000053c
(1397) 10000216: 4291 cmp r1, r2
(1398) 10000218: d1fc bne 0x10000214
(1399) 10000214: c101 stmia r1!, {r0}
(1399) Write SRAM [2000053c] = 00000000
(1400) r1 = 20000540
(1401) 10000216: 4291 cmp r1, r2
(1402) 10000218: d1fc bne 0x10000214
(1403) 10000214: c101 stmia r1!, {r0}
(1403) Write SRAM [20000540] = 00000000
(1404) r1 = 20000544
(1405) 10000216: 4291 cmp r1, r2
(1406) 10000218: d1fc bne 0x10000214
(1407) 10000214: c101 stmia r1!, {r0}
(1407) Write SRAM [20000544] = 00000000
(1408) r1 = 20000548
(1409) 10000216: 4291 cmp r1, r2
(1410) 10000218: d1fc bne 0x10000214
(1411) 10000214: c101 stmia r1!, {r0}
(1411) Write SRAM [20000548] = 00000000
(1412) r1 = 2000054c
(1413) 10000216: 4291 cmp r1, r2
(1414) 10000218: d1fc bne 0x10000214
(1415) 10000214: c101 stmia r1!, {r0}
(1415) Write SRAM [2000054c] = 00000000
(1416) r1 = 20000550
(1417) 10000216: 4291 cmp r1, r2
(1418) 10000218: d1fc bne 0x10000214
(1419) 10000214: c101 stmia r1!, {r0}
(1419) Write SRAM [20000550] = 00000000
(1420) r1 = 20000554
(1421) 10000216: 4291 cmp r1, r2
(1422) 10000218: d1fc bne 0x10000214
(1423) 10000214: c101 stmia r1!, {r0}
(1423) Write SRAM [20000554] = 00000000
(1424) r1 = 20000558
(1425) 10000216: 4291 cmp r1, r2
(1426) 10000218: d1fc bne 0x10000214
(1427) 10000214: c101 stmia r1!, {r0}
(1427) Write SRAM [20000558] = 00000000
(1428) r1 = 2000055c
(1429) 10000216: 4291 cmp r1, r2
(1430) 10000218: d1fc bne 0x10000214
(1431) 10000214: c101 stmia r1!, {r0}
(1431) Write SRAM [2000055c] = 00000000
(1432) r1 = 20000560
(1433) 10000216: 4291 cmp r1, r2
(1434) 10000218: d1fc bne 0x10000214
(1435) 10000214: c101 stmia r1!, {r0}
(1435) Write SRAM [20000560] = 00000000
(1436) r1 = 20000564
(1437) 10000216: 4291 cmp r1, r2
(1438) 10000218: d1fc bne 0x10000214
(1439) 10000214: c101 stmia r1!, {r0}
(1439) Write SRAM [20000564] = 00000000
(1440) r1 = 20000568
(1441) 10000216: 4291 cmp r1, r2
(1442) 10000218: d1fc bne 0x10000214
(1443) 10000214: c101 stmia r1!, {r0}
(1443) Write SRAM [20000568] = 00000000
(1444) r1 = 2000056c
(1445) 10000216: 4291 cmp r1, r2
(1446) 10000218: d1fc bne 0x10000214
(1447) 10000214: c101 stmia r1!, {r0}
(1447) Write SRAM [2000056c] = 00000000
(1448) r1 = 20000570
(1449) 10000216: 4291 cmp r1, r2
(1450) 10000218: d1fc bne 0x10000214
(1451) 10000214: c101 stmia r1!, {r0}
(1451) Write SRAM [20000570] = 00000000
(1452) r1 = 20000574
(1453) 10000216: 4291 cmp r1, r2
(1454) 10000218: d1fc bne 0x10000214
(1455) 10000214: c101 stmia r1!, {r0}
(1455) Write SRAM [20000574] = 00000000
(1456) r1 = 20000578
(1457) 10000216: 4291 cmp r1, r2
(1458) 10000218: d1fc bne 0x10000214
(1459) 10000214: c101 stmia r1!, {r0}
(1459) Write SRAM [20000578] = 00000000
(1460) r1 = 2000057c
(1461) 10000216: 4291 cmp r1, r2
(1462) 10000218: d1fc bne 0x10000214
(1463) 10000214: c101 stmia r1!, {r0}
(1463) Write SRAM [2000057c] = 00000000
(1464) r1 = 20000580
(1465) 10000216: 4291 cmp r1, r2
(1466) 10000218: d1fc bne 0x10000214
(1467) 10000214: c101 stmia r1!, {r0}
(1467) Write SRAM [20000580] = 00000000
(1468) r1 = 20000584
(1469) 10000216: 4291 cmp r1, r2
(1470) 10000218: d1fc bne 0x10000214
(1471) 10000214: c101 stmia r1!, {r0}
(1471) Write SRAM [20000584] = 00000000
(1472) r1 = 20000588
(1473) 10000216: 4291 cmp r1, r2
(1474) 10000218: d1fc bne 0x10000214
(1475) 10000214: c101 stmia r1!, {r0}
(1475) Write SRAM [20000588] = 00000000
(1476) r1 = 2000058c
(1477) 10000216: 4291 cmp r1, r2
(1478) 10000218: d1fc bne 0x10000214
(1479) 10000214: c101 stmia r1!, {r0}
(1479) Write SRAM [2000058c] = 00000000
(1480) r1 = 20000590
(1481) 10000216: 4291 cmp r1, r2
(1482) 10000218: d1fc bne 0x10000214
(1483) 10000214: c101 stmia r1!, {r0}
(1483) Write SRAM [20000590] = 00000000
(1484) r1 = 20000594
(1485) 10000216: 4291 cmp r1, r2
(1486) 10000218: d1fc bne 0x10000214
(1487) 10000214: c101 stmia r1!, {r0}
(1487) Write SRAM [20000594] = 00000000
(1488) r1 = 20000598
(1489) 10000216: 4291 cmp r1, r2
(1490) 10000218: d1fc bne 0x10000214
(1491) 10000214: c101 stmia r1!, {r0}
(1491) Write SRAM [20000598] = 00000000
(1492) r1 = 2000059c
(1493) 10000216: 4291 cmp r1, r2
(1494) 10000218: d1fc bne 0x10000214
(1495) 10000214: c101 stmia r1!, {r0}
(1495) Write SRAM [2000059c] = 00000000
(1496) r1 = 200005a0
(1497) 10000216: 4291 cmp r1, r2
(1498) 10000218: d1fc bne 0x10000214
(1499) 10000214: c101 stmia r1!, {r0}
(1499) Write SRAM [200005a0] = 00000000
(1500) r1 = 200005a4
(1501) 10000216: 4291 cmp r1, r2
(1502) 10000218: d1fc bne 0x10000214
(1503) 10000214: c101 stmia r1!, {r0}
(1503) Write SRAM [200005a4] = 00000000
(1504) r1 = 200005a8
(1505) 10000216: 4291 cmp r1, r2
(1506) 10000218: d1fc bne 0x10000214
(1507) 10000214: c101 stmia r1!, {r0}
(1507) Write SRAM [200005a8] = 00000000
(1508) r1 = 200005ac
(1509) 10000216: 4291 cmp r1, r2
(1510) 10000218: d1fc bne 0x10000214
(1511) 10000214: c101 stmia r1!, {r0}
(1511) Write SRAM [200005ac] = 00000000
(1512) r1 = 200005b0
(1513) 10000216: 4291 cmp r1, r2
(1514) 10000218: d1fc bne 0x10000214
(1515) 10000214: c101 stmia r1!, {r0}
(1515) Write SRAM [200005b0] = 00000000
(1516) r1 = 200005b4
(1517) 10000216: 4291 cmp r1, r2
(1518) 10000218: d1fc bne 0x10000214
(1519) 10000214: c101 stmia r1!, {r0}
(1519) Write SRAM [200005b4] = 00000000
(1520) r1 = 200005b8
(1521) 10000216: 4291 cmp r1, r2
(1522) 10000218: d1fc bne 0x10000214
(1523) 10000214: c101 stmia r1!, {r0}
(1523) Write SRAM [200005b8] = 00000000
(1524) r1 = 200005bc
(1525) 10000216: 4291 cmp r1, r2
(1526) 10000218: d1fc bne 0x10000214
(1527) 10000214: c101 stmia r1!, {r0}
(1527) Write SRAM [200005bc] = 00000000
(1528) r1 = 200005c0
(1529) 10000216: 4291 cmp r1, r2
(1530) 10000218: d1fc bne 0x10000214
(1531) 10000214: c101 stmia r1!, {r0}
(1531) Write SRAM [200005c0] = 00000000
(1532) r1 = 200005c4
(1533) 10000216: 4291 cmp r1, r2
(1534) 10000218: d1fc bne 0x10000214
(1535) 10000214: c101 stmia r1!, {r0}
(1535) Write SRAM [200005c4] = 00000000
(1536) r1 = 200005c8
(1537) 10000216: 4291 cmp r1, r2
(1538) 10000218: d1fc bne 0x10000214
(1539) 10000214: c101 stmia r1!, {r0}
(1539) Write SRAM [200005c8] = 00000000
(1540) r1 = 200005cc
(1541) 10000216: 4291 cmp r1, r2
(1542) 10000218: d1fc bne 0x10000214
(1543) 10000214: c101 stmia r1!, {r0}
(1543) Write SRAM [200005cc] = 00000000
(1544) r1 = 200005d0
(1545) 10000216: 4291 cmp r1, r2
(1546) 10000218: d1fc bne 0x10000214
(1547) 10000214: c101 stmia r1!, {r0}
(1547) Write SRAM [200005d0] = 00000000
(1548) r1 = 200005d4
(1549) 10000216: 4291 cmp r1, r2
(1550) 10000218: d1fc bne 0x10000214
(1551) 10000214: c101 stmia r1!, {r0}
(1551) Write SRAM [200005d4] = 00000000
(1552) r1 = 200005d8
(1553) 10000216: 4291 cmp r1, r2
(1554) 10000218: d1fc bne 0x10000214
(1555) 10000214: c101 stmia r1!, {r0}
(1555) Write SRAM [200005d8] = 00000000
(1556) r1 = 200005dc
(1557) 10000216: 4291 cmp r1, r2
(1558) 10000218: d1fc bne 0x10000214
(1559) 10000214: c101 stmia r1!, {r0}
(1559) Write SRAM [200005dc] = 00000000
(1560) r1 = 200005e0
(1561) 10000216: 4291 cmp r1, r2
(1562) 10000218: d1fc bne 0x10000214
(1563) 10000214: c101 stmia r1!, {r0}
(1563) Write SRAM [200005e0] = 00000000
(1564) r1 = 200005e4
(1565) 10000216: 4291 cmp r1, r2
(1566) 10000218: d1fc bne 0x10000214
(1567) 10000214: c101 stmia r1!, {r0}
(1567) Write SRAM [200005e4] = 00000000
(1568) r1 = 200005e8
(1569) 10000216: 4291 cmp r1, r2
(1570) 10000218: d1fc bne 0x10000214
(1571) 10000214: c101 stmia r1!, {r0}
(1571) Write SRAM [200005e8] = 00000000
(1572) r1 = 200005ec
(1573) 10000216: 4291 cmp r1, r2
(1574) 10000218: d1fc bne 0x10000214
(1575) 10000214: c101 stmia r1!, {r0}
(1575) Write SRAM [200005ec] = 00000000
(1576) r1 = 200005f0
(1577) 10000216: 4291 cmp r1, r2
(1578) 10000218: d1fc bne 0x10000214
(1579) 10000214: c101 stmia r1!, {r0}
(1579) Write SRAM [200005f0] = 00000000
(1580) r1 = 200005f4
(1581) 10000216: 4291 cmp r1, r2
(1582) 10000218: d1fc bne 0x10000214
(1583) 10000214: c101 stmia r1!, {r0}
(1583) Write SRAM [200005f4] = 00000000
(1584) r1 = 200005f8
(1585) 10000216: 4291 cmp r1, r2
(1586) 10000218: d1fc bne 0x10000214
(1587) 10000214: c101 stmia r1!, {r0}
(1587) Write SRAM [200005f8] = 00000000
(1588) r1 = 200005fc
(1589) 10000216: 4291 cmp r1, r2
(1590) 10000218: d1fc bne 0x10000214
(1591) 10000214: c101 stmia r1!, {r0}
(1591) Write SRAM [200005fc] = 00000000
(1592) r1 = 20000600
(1593) 10000216: 4291 cmp r1, r2
(1594) 10000218: d1fc bne 0x10000214
(1595) 10000214: c101 stmia r1!, {r0}
(1595) Write SRAM [20000600] = 00000000
(1596) r1 = 20000604
(1597) 10000216: 4291 cmp r1, r2
(1598) 10000218: d1fc bne 0x10000214
(1599) 10000214: c101 stmia r1!, {r0}
(1599) Write SRAM [20000604] = 00000000
(1600) r1 = 20000608
(1601) 10000216: 4291 cmp r1, r2
(1602) 10000218: d1fc bne 0x10000214
(1603) 10000214: c101 stmia r1!, {r0}
(1603) Write SRAM [20000608] = 00000000
(1604) r1 = 2000060c
(1605) 10000216: 4291 cmp r1, r2
(1606) 10000218: d1fc bne 0x10000214
(1607) 10000214: c101 stmia r1!, {r0}
(1607) Write SRAM [2000060c] = 00000000
(1608) r1 = 20000610
(1609) 10000216: 4291 cmp r1, r2
(1609) nzcv = .11.
(1610) 10000218: d1fc bne 0x10000214
(1611) 1000021a: 4919 ldr r1, [pc, #100]
(1611) Read Flash [10000280] = 10001201
(1612) r1 = 10001201
(1613) 1000021c: 4788 blx r1
(1613) lr = 1000021e
(1614) 10001200: 4b2b ldr r3, [pc, #172]
(1614) Read Flash [100012b0] = 4000e000
(1615) r3 = 4000e000
(1616) 10001202: 4a2c ldr r2, [pc, #176]
(1616) Read Flash [100012b4] = fefbcdbf
(1617) r2 = fefbcdbf
(1618) 10001204: b570 push {r4, r5, r6, lr}
(1618) Write SRAM [20041efc] = 1000021e
(1619) Write SRAM [20041ef8] = 00000000
(1620) Write SRAM [20041ef4] = 00000000
(1621) Write SRAM [20041ef0] = 10000264
(1622) msp = 20041ef0
(1623) 10001206: 601a str r2, [r3, #0]
(1623) Write RESET:set = fefbcdbf
(1625) 10001208: 4a2b ldr r2, [pc, #172]
(1625) Read Flash [100012b8] = 003c7ffe
(1626) r2 = 003c7ffe
(1627) 1000120a: 4b2c ldr r3, [pc, #176]
(1627) Read Flash [100012bc] = 4000f000
(1628) r3 = 4000f000
(1629) 1000120c: 492c ldr r1, [pc, #176]
(1629) Read Flash [100012c0] = 4000c000
(1630) r1 = 4000c000
(1631) 1000120e: 601a str r2, [r3, #0]
(1631) Write RESET:clr = 003c7ffe
(1633) 10001210: 0014 movs r4, r2
(1633) r4 = 003c7ffe
(1633) nzcv = ..1.
(1634) 10001212: 688b ldr r3, [r1, #8]
(1634) Read RESET_DONE = 003c7ffe
(1635) r3 = 003c7ffe
(1636) 10001214: 439c bics r4, r3
(1636) r4 = 00000000
(1636) nzcv = .11.
(1637) 10001216: d1fb bne 0x10001210
(1638) 10001218: 4d2a ldr r5, [pc, #168]
(1638) Read Flash [100012c4] = 2000022c
(1639) r5 = 2000022c
(1640) 1000121a: 4e2b ldr r6, [pc, #172]
(1640) Read Flash [100012c8] = 2000023c
(1641) r6 = 2000023c
(1642) 1000121c: 42b5 cmp r5, r6
(1642) nzcv = 1...
(1643) 1000121e: d208 bcs 0x10001232
(1644) 10001220: 3e01 sub r6, #1
(1644) r6 = 2000023b
(1644) nzcv = ..1.
(1645) 10001222: 1b76 sub r6, r6, r5
(1645) r6 = 0000000f
(1646) 10001224: 08b6 lsrs r6, r6, #2
(1646) r6 = 00000003
(1647) 10001226: cd08 ldmia r5!, {r3}
(1647) Read SRAM [2000022c] = 10001921
(1648) r3 = 10001921
(1648) r5 = 20000230
(1649) 10001228: 4798 blx r3
(1649) lr = 1000122a
(1650) 10001920: 4801 ldr r0, [pc, #4]
(1650) Read Flash [10001928] = 20000200
(1651) r0 = 20000200
(1652) 10001922: 2104 movs r1, #4
(1652) r1 = 00000004
(1653) 10001924: 4b01 ldr r3, [pc, #4]
(1653) Read Flash [1000192c] = 1000173d
(1654) r3 = 1000173d
(1655) 10001926: 4718 bx r3
(1656) 1000173c: b5f8 push {r3, r4, r5, r6, r7, lr}
(1656) Write SRAM [20041eec] = 1000122a
(1657) Write SRAM [20041ee8] = 00000000
(1658) Write SRAM [20041ee4] = 00000003
(1659) Write SRAM [20041ee0] = 20000230
(1660) Write SRAM [20041edc] = 00000000
(1661) Write SRAM [20041ed8] = 1000173d
(1662) msp = 20041ed8
(1663) 1000173e: 4647 mov r7, r8
(1663) r7 = 00000000
(1664) 10001740: 46ce mov lr, r9
(1664) lr = 00000000
(1665) 10001742: b580 push {r7, lr}
(1665) Write SRAM [20041ed4] = 00000000
(1666) Write SRAM [20041ed0] = 00000000
(1667) msp = 20041ed0
(1668) 10001744: 1e0f movs r7, r1
(1668) r7 = 00000004
(1669) 10001746: d019 beq 0x1000177c
(1670) 10001748: 2314 movs r3, #20
(1670) r3 = 00000014
(1671) 1000174a: 4699 mov r9, r3
(1671) r9 = 00000014
(1672) 1000174c: 3304 add r3, #4
(1672) r3 = 00000018
(1672) nzcv = ....
(1673) 1000174e: 0004 movs r4, r0
(1673) r4 = 20000200
(1674) 10001750: 2500 movs r5, #0
(1674) r5 = 00000000
(1674) nzcv = .1..
(1675) 10001752: 2601 movs r6, #1
(1675) r6 = 00000001
(1675) nzcv = ....
(1676) 10001754: 4698 mov r8, r3
(1676) r8 = 00000018
(1677) 10001756: 464b mov r3, r9
(1677) r3 = 00000014
(1678) 10001758: 8818 ldrh r0, [r3, #0]
(1678) Read ROM [14] = 007a
(1679) r0 = 0000007a
(1680) 1000175a: 4643 mov r3, r8
(1680) r3 = 00000018
(1681) 1000175c: 6821 ldr r1, [r4, #0]
(1681) Read SRAM [20000200] = 0000534d
(1682) r1 = 0000534d
(1683) 1000175e: 881b ldrh r3, [r3, #0]
(1683) Read ROM [18] = 001d
(1684) r3 = 0000001d
(1685) 10001760: 4798 blx r3
(1685) lr = 10001762
(1686) 0000001c: 2300 movs r3, #0
(1686) r3 = 00000000
(1686) nzcv = .1..
(1687) 0000001e: 8802 ldrh r2, [r0, #0]
(1687) Read ROM [7a] = 3350
(1688) r2 = 00003350
(1689) 00000020: 429a cmp r2, r3
(1689) nzcv = ..1.
(1690) 00000022: d003 beq 0x0000002c
(1691) 00000024: 8843 ldrh r3, [r0, #2]
(1691) Read ROM [7c] = 0309
(1692) r3 = 00000309
(1693) 00000026: 3004 add r0, #4
(1693) r0 = 0000007e
(1693) nzcv = ....
(1694) 00000028: 4291 cmp r1, r2
(1694) nzcv = ..1.
(1695) 0000002a: d1f7 bne 0x0000001c
(1696) 0000001c: 2300 movs r3, #0
(1696) r3 = 00000000
(1696) nzcv = .11.
(1697) 0000001e: 8802 ldrh r2, [r0, #0]
(1697) Read ROM [7e] = 3352
(1698) r2 = 00003352
(1699) 00000020: 429a cmp r2, r3
(1699) nzcv = ..1.
(1700) 00000022: d003 beq 0x0000002c
(1701) 00000024: 8843 ldrh r3, [r0, #2]
(1701) Read ROM [80] = 032d
(1702) r3 = 0000032d
(1703) 00000026: 3004 add r0, #4
(1703) r0 = 00000082
(1703) nzcv = ....
(1704) 00000028: 4291 cmp r1, r2
(1704) nzcv = ..1.
(1705) 0000002a: d1f7 bne 0x0000001c
(1706) 0000001c: 2300 movs r3, #0
(1706) r3 = 00000000
(1706) nzcv = .11.
(1707) 0000001e: 8802 ldrh r2, [r0, #0]
(1707) Read ROM [82] = 334c
(1708) r2 = 0000334c
(1709) 00000020: 429a cmp r2, r3
(1709) nzcv = ..1.
(1710) 00000022: d003 beq 0x0000002c
(1711) 00000024: 8843 ldrh r3, [r0, #2]
(1711) Read ROM [84] = 0357
(1712) r3 = 00000357
(1713) 00000026: 3004 add r0, #4
(1713) r0 = 00000086
(1713) nzcv = ....
(1714) 00000028: 4291 cmp r1, r2
(1714) nzcv = ..1.
(1715) 0000002a: d1f7 bne 0x0000001c
(1716) 0000001c: 2300 movs r3, #0
(1716) r3 = 00000000
(1716) nzcv = .11.
(1717) 0000001e: 8802 ldrh r2, [r0, #0]
(1717) Read ROM [86] = 3354
(1718) r2 = 00003354
(1719) 00000020: 429a cmp r2, r3
(1719) nzcv = ..1.
(1720) 00000022: d003 beq 0x0000002c
(1721) 00000024: 8843 ldrh r3, [r0, #2]
(1721) Read ROM [88] = 038f
(1722) r3 = 0000038f
(1723) 00000026: 3004 add r0, #4
(1723) r0 = 0000008a
(1723) nzcv = ....
(1724) 00000028: 4291 cmp r1, r2
(1724) nzcv = ..1.
(1725) 0000002a: d1f7 bne 0x0000001c
(1726) 0000001c: 2300 movs r3, #0
(1726) r3 = 00000000
(1726) nzcv = .11.
(1727) 0000001e: 8802 ldrh r2, [r0, #0]
(1727) Read ROM [8a] = 534d
(1728) r2 = 0000534d
(1729) 00000020: 429a cmp r2, r3
(1729) nzcv = ..1.
(1730) 00000022: d003 beq 0x0000002c
(1731) 00000024: 8843 ldrh r3, [r0, #2]
(1731) Read ROM [8c] = 26b9
(1732) r3 = 000026b9
(1733) 00000026: 3004 add r0, #4
(1733) r0 = 0000008e
(1733) nzcv = ....
(1734) 00000028: 4291 cmp r1, r2
(1734) nzcv = .11.
(1735) 0000002a: d1f7 bne 0x0000001c
(1736) 0000002c: 1c18 movs r0, r3
(1736) r0 = 000026b9
(1736) nzcv = ....
(1737) 0000002e: 4770 bx lr
(1738) 10001762: c401 stmia r4!, {r0}
(1738) Write SRAM [20000200] = 000026b9
(1739) r4 = 20000204
(1740) 10001764: 1e43 sub r3, r0, #1
(1740) r3 = 000026b8
(1740) nzcv = ..1.
(1741) 10001766: 4198 sbc r0, r3
(1741) r0 = 00000001
(1742) 10001768: 3501 add r5, #1
(1742) r5 = 00000001
(1742) nzcv = ....
(1743) 1000176a: 4240 neg r0, r0
(1743) r0 = ffffffff
(1743) nzcv = 1...
(1744) 1000176c: 4006 ands r6, r0
(1744) r6 = 00000001
(1744) nzcv = ....
(1745) 1000176e: 42af cmp r7, r5
(1745) nzcv = ..1.
(1746) 10001770: d1f1 bne 0x10001756
(1747) 10001756: 464b mov r3, r9
(1747) r3 = 00000014
(1748) 10001758: 8818 ldrh r0, [r3, #0]
(1748) Read ROM [14] = 007a
(1749) r0 = 0000007a
(1750) 1000175a: 4643 mov r3, r8
(1750) r3 = 00000018
(1751) 1000175c: 6821 ldr r1, [r4, #0]
(1751) Read SRAM [20000204] = 0000434d
(1752) r1 = 0000434d
(1753) 1000175e: 881b ldrh r3, [r3, #0]
(1753) Read ROM [18] = 001d
(1754) r3 = 0000001d
(1755) 10001760: 4798 blx r3
(1755) lr = 10001762
(1756) 0000001c: 2300 movs r3, #0
(1756) r3 = 00000000
(1756) nzcv = .11.
(1757) 0000001e: 8802 ldrh r2, [r0, #0]
(1757) Read ROM [7a] = 3350
(1758) r2 = 00003350
(1759) 00000020: 429a cmp r2, r3
(1759) nzcv = ..1.
(1760) 00000022: d003 beq 0x0000002c
(1761) 00000024: 8843 ldrh r3, [r0, #2]
(1761) Read ROM [7c] = 0309
(1762) r3 = 00000309
(1763) 00000026: 3004 add r0, #4
(1763) r0 = 0000007e
(1763) nzcv = ....
(1764) 00000028: 4291 cmp r1, r2
(1764) nzcv = ..1.
(1765) 0000002a: d1f7 bne 0x0000001c
(1766) 0000001c: 2300 movs r3, #0
(1766) r3 = 00000000
(1766) nzcv = .11.
(1767) 0000001e: 8802 ldrh r2, [r0, #0]
(1767) Read ROM [7e] = 3352
(1768) r2 = 00003352
(1769) 00000020: 429a cmp r2, r3
(1769) nzcv = ..1.
(1770) 00000022: d003 beq 0x0000002c
(1771) 00000024: 8843 ldrh r3, [r0, #2]
(1771) Read ROM [80] = 032d
(1772) r3 = 0000032d
(1773) 00000026: 3004 add r0, #4
(1773) r0 = 00000082
(1773) nzcv = ....
(1774) 00000028: 4291 cmp r1, r2
(1774) nzcv = ..1.
(1775) 0000002a: d1f7 bne 0x0000001c
(1776) 0000001c: 2300 movs r3, #0
(1776) r3 = 00000000
(1776) nzcv = .11.
(1777) 0000001e: 8802 ldrh r2, [r0, #0]
(1777) Read ROM [82] = 334c
(1778) r2 = 0000334c
(1779) 00000020: 429a cmp r2, r3
(1779) nzcv = ..1.
(1780) 00000022: d003 beq 0x0000002c
(1781) 00000024: 8843 ldrh r3, [r0, #2]
(1781) Read ROM [84] = 0357
(1782) r3 = 00000357
(1783) 00000026: 3004 add r0, #4
(1783) r0 = 00000086
(1783) nzcv = ....
(1784) 00000028: 4291 cmp r1, r2
(1784) nzcv = ..1.
(1785) 0000002a: d1f7 bne 0x0000001c
(1786) 0000001c: 2300 movs r3, #0
(1786) r3 = 00000000
(1786) nzcv = .11.
(1787) 0000001e: 8802 ldrh r2, [r0, #0]
(1787) Read ROM [86] = 3354
(1788) r2 = 00003354
(1789) 00000020: 429a cmp r2, r3
(1789) nzcv = ..1.
(1790) 00000022: d003 beq 0x0000002c
(1791) 00000024: 8843 ldrh r3, [r0, #2]
(1791) Read ROM [88] = 038f
(1792) r3 = 0000038f
(1793) 00000026: 3004 add r0, #4
(1793) r0 = 0000008a
(1793) nzcv = ....
(1794) 00000028: 4291 cmp r1, r2
(1794) nzcv = ..1.
(1795) 0000002a: d1f7 bne 0x0000001c
(1796) 0000001c: 2300 movs r3, #0
(1796) r3 = 00000000
(1796) nzcv = .11.
(1797) 0000001e: 8802 ldrh r2, [r0, #0]
(1797) Read ROM [8a] = 534d
(1798) r2 = 0000534d
(1799) 00000020: 429a cmp r2, r3
(1799) nzcv = ..1.
(1800) 00000022: d003 beq 0x0000002c
(1801) 00000024: 8843 ldrh r3, [r0, #2]
(1801) Read ROM [8c] = 26b9
(1802) r3 = 000026b9
(1803) 00000026: 3004 add r0, #4
(1803) r0 = 0000008e
(1803) nzcv = ....
(1804) 00000028: 4291 cmp r1, r2
(1804) nzcv = 1...
(1805) 0000002a: d1f7 bne 0x0000001c
(1806) 0000001c: 2300 movs r3, #0
(1806) r3 = 00000000
(1806) nzcv = .1..
(1807) 0000001e: 8802 ldrh r2, [r0, #0]
(1807) Read ROM [8e] = 3453
(1808) r2 = 00003453
(1809) 00000020: 429a cmp r2, r3
(1809) nzcv = ..1.
(1810) 00000022: d003 beq 0x0000002c
(1811) 00000024: 8843 ldrh r3, [r0, #2]
(1811) Read ROM [90] = 26ad
(1812) r3 = 000026ad
(1813) 00000026: 3004 add r0, #4
(1813) r0 = 00000092
(1813) nzcv = ....
(1814) 00000028: 4291 cmp r1, r2
(1814) nzcv = ..1.
(1815) 0000002a: d1f7 bne 0x0000001c
(1816) 0000001c: 2300 movs r3, #0
(1816) r3 = 00000000
(1816) nzcv = .11.
(1817) 0000001e: 8802 ldrh r2, [r0, #0]
(1817) Read ROM [92] = 434d
(1818) r2 = 0000434d
(1819) 00000020: 429a cmp r2, r3
(1819) nzcv = ..1.
(1820) 00000022: d003 beq 0x0000002c
(1821) 00000024: 8843 ldrh r3, [r0, #2]
(1821) Read ROM [94] = 261d
(1822) r3 = 0000261d
(1823) 00000026: 3004 add r0, #4
(1823) r0 = 00000096
(1823) nzcv = ....
(1824) 00000028: 4291 cmp r1, r2
(1824) nzcv = .11.
(1825) 0000002a: d1f7 bne 0x0000001c
(1826) 0000002c: 1c18 movs r0, r3
(1826) r0 = 0000261d
(1826) nzcv = ....
(1827) 0000002e: 4770 bx lr
(1828) 10001762: c401 stmia r4!, {r0}
(1828) Write SRAM [20000204] = 0000261d
(1829) r4 = 20000208
(1830) 10001764: 1e43 sub r3, r0, #1
(1830) r3 = 0000261c
(1830) nzcv = ..1.
(1831) 10001766: 4198 sbc r0, r3
(1831) r0 = 00000001
(1832) 10001768: 3501 add r5, #1
(1832) r5 = 00000002
(1832) nzcv = ....
(1833) 1000176a: 4240 neg r0, r0
(1833) r0 = ffffffff
(1833) nzcv = 1...
(1834) 1000176c: 4006 ands r6, r0
(1834) r6 = 00000001
(1834) nzcv = ....
(1835) 1000176e: 42af cmp r7, r5
(1835) nzcv = ..1.
(1836) 10001770: d1f1 bne 0x10001756
(1837) 10001756: 464b mov r3, r9
(1837) r3 = 00000014
(1838) 10001758: 8818 ldrh r0, [r3, #0]
(1838) Read ROM [14] = 007a
(1839) r0 = 0000007a
(1840) 1000175a: 4643 mov r3, r8
(1840) r3 = 00000018
(1841) 1000175c: 6821 ldr r1, [r4, #0]
(1841) Read SRAM [20000208] = 00003453
(1842) r1 = 00003453
(1843) 1000175e: 881b ldrh r3, [r3, #0]
(1843) Read ROM [18] = 001d
(1844) r3 = 0000001d
(1845) 10001760: 4798 blx r3
(1845) lr = 10001762
(1846) 0000001c: 2300 movs r3, #0
(1846) r3 = 00000000
(1846) nzcv = .11.
(1847) 0000001e: 8802 ldrh r2, [r0, #0]
(1847) Read ROM [7a] = 3350
(1848) r2 = 00003350
(1849) 00000020: 429a cmp r2, r3
(1849) nzcv = ..1.
(1850) 00000022: d003 beq 0x0000002c
(1851) 00000024: 8843 ldrh r3, [r0, #2]
(1851) Read ROM [7c] = 0309
(1852) r3 = 00000309
(1853) 00000026: 3004 add r0, #4
(1853) r0 = 0000007e
(1853) nzcv = ....
(1854) 00000028: 4291 cmp r1, r2
(1854) nzcv = ..1.
(1855) 0000002a: d1f7 bne 0x0000001c
(1856) 0000001c: 2300 movs r3, #0
(1856) r3 = 00000000
(1856) nzcv = .11.
(1857) 0000001e: 8802 ldrh r2, [r0, #0]
(1857) Read ROM [7e] = 3352
(1858) r2 = 00003352
(1859) 00000020: 429a cmp r2, r3
(1859) nzcv = ..1.
(1860) 00000022: d003 beq 0x0000002c
(1861) 00000024: 8843 ldrh r3, [r0, #2]
(1861) Read ROM [80] = 032d
(1862) r3 = 0000032d
(1863) 00000026: 3004 add r0, #4
(1863) r0 = 00000082
(1863) nzcv = ....
(1864) 00000028: 4291 cmp r1, r2
(1864) nzcv = ..1.
(1865) 0000002a: d1f7 bne 0x0000001c
(1866) 0000001c: 2300 movs r3, #0
(1866) r3 = 00000000
(1866) nzcv = .11.
(1867) 0000001e: 8802 ldrh r2, [r0, #0]
(1867) Read ROM [82] = 334c
(1868) r2 = 0000334c
(1869) 00000020: 429a cmp r2, r3
(1869) nzcv = ..1.
(1870) 00000022: d003 beq 0x0000002c
(1871) 00000024: 8843 ldrh r3, [r0, #2]
(1871) Read ROM [84] = 0357
(1872) r3 = 00000357
(1873) 00000026: 3004 add r0, #4
(1873) r0 = 00000086
(1873) nzcv = ....
(1874) 00000028: 4291 cmp r1, r2
(1874) nzcv = ..1.
(1875) 0000002a: d1f7 bne 0x0000001c
(1876) 0000001c: 2300 movs r3, #0
(1876) r3 = 00000000
(1876) nzcv = .11.
(1877) 0000001e: 8802 ldrh r2, [r0, #0]
(1877) Read ROM [86] = 3354
(1878) r2 = 00003354
(1879) 00000020: 429a cmp r2, r3
(1879) nzcv = ..1.
(1880) 00000022: d003 beq 0x0000002c
(1881) 00000024: 8843 ldrh r3, [r0, #2]
(1881) Read ROM [88] = 038f
(1882) r3 = 0000038f
(1883) 00000026: 3004 add r0, #4
(1883) r0 = 0000008a
(1883) nzcv = ....
(1884) 00000028: 4291 cmp r1, r2
(1884) nzcv = ..1.
(1885) 0000002a: d1f7 bne 0x0000001c
(1886) 0000001c: 2300 movs r3, #0
(1886) r3 = 00000000
(1886) nzcv = .11.
(1887) 0000001e: 8802 ldrh r2, [r0, #0]
(1887) Read ROM [8a] = 534d
(1888) r2 = 0000534d
(1889) 00000020: 429a cmp r2, r3
(1889) nzcv = ..1.
(1890) 00000022: d003 beq 0x0000002c
(1891) 00000024: 8843 ldrh r3, [r0, #2]
(1891) Read ROM [8c] = 26b9
(1892) r3 = 000026b9
(1893) 00000026: 3004 add r0, #4
(1893) r0 = 0000008e
(1893) nzcv = ....
(1894) 00000028: 4291 cmp r1, r2
(1894) nzcv = 1...
(1895) 0000002a: d1f7 bne 0x0000001c
(1896) 0000001c: 2300 movs r3, #0
(1896) r3 = 00000000
(1896) nzcv = .1..
(1897) 0000001e: 8802 ldrh r2, [r0, #0]
(1897) Read ROM [8e] = 3453
(1898) r2 = 00003453
(1899) 00000020: 429a cmp r2, r3
(1899) nzcv = ..1.
(1900) 00000022: d003 beq 0x0000002c
(1901) 00000024: 8843 ldrh r3, [r0, #2]
(1901) Read ROM [90] = 26ad
(1902) r3 = 000026ad
(1903) 00000026: 3004 add r0, #4
(1903) r0 = 00000092
(1903) nzcv = ....
(1904) 00000028: 4291 cmp r1, r2
(1904) nzcv = .11.
(1905) 0000002a: d1f7 bne 0x0000001c
(1906) 0000002c: 1c18 movs r0, r3
(1906) r0 = 000026ad
(1906) nzcv = ....
(1907) 0000002e: 4770 bx lr
(1908) 10001762: c401 stmia r4!, {r0}
(1908) Write SRAM [20000208] = 000026ad
(1909) r4 = 2000020c
(1910) 10001764: 1e43 sub r3, r0, #1
(1910) r3 = 000026ac
(1910) nzcv = ..1.
(1911) 10001766: 4198 sbc r0, r3
(1911) r0 = 00000001
(1912) 10001768: 3501 add r5, #1
(1912) r5 = 00000003
(1912) nzcv = ....
(1913) 1000176a: 4240 neg r0, r0
(1913) r0 = ffffffff
(1913) nzcv = 1...
(1914) 1000176c: 4006 ands r6, r0
(1914) r6 = 00000001
(1914) nzcv = ....
(1915) 1000176e: 42af cmp r7, r5
(1915) nzcv = ..1.
(1916) 10001770: d1f1 bne 0x10001756
(1917) 10001756: 464b mov r3, r9
(1917) r3 = 00000014
(1918) 10001758: 8818 ldrh r0, [r3, #0]
(1918) Read ROM [14] = 007a
(1919) r0 = 0000007a
(1920) 1000175a: 4643 mov r3, r8
(1920) r3 = 00000018
(1921) 1000175c: 6821 ldr r1, [r4, #0]
(1921) Read SRAM [2000020c] = 00003443
(1922) r1 = 00003443
(1923) 1000175e: 881b ldrh r3, [r3, #0]
(1923) Read ROM [18] = 001d
(1924) r3 = 0000001d
(1925) 10001760: 4798 blx r3
(1925) lr = 10001762
(1926) 0000001c: 2300 movs r3, #0
(1926) r3 = 00000000
(1926) nzcv = .11.
(1927) 0000001e: 8802 ldrh r2, [r0, #0]
(1927) Read ROM [7a] = 3350
(1928) r2 = 00003350
(1929) 00000020: 429a cmp r2, r3
(1929) nzcv = ..1.
(1930) 00000022: d003 beq 0x0000002c
(1931) 00000024: 8843 ldrh r3, [r0, #2]
(1931) Read ROM [7c] = 0309
(1932) r3 = 00000309
(1933) 00000026: 3004 add r0, #4
(1933) r0 = 0000007e
(1933) nzcv = ....
(1934) 00000028: 4291 cmp r1, r2
(1934) nzcv = ..1.
(1935) 0000002a: d1f7 bne 0x0000001c
(1936) 0000001c: 2300 movs r3, #0
(1936) r3 = 00000000
(1936) nzcv = .11.
(1937) 0000001e: 8802 ldrh r2, [r0, #0]
(1937) Read ROM [7e] = 3352
(1938) r2 = 00003352
(1939) 00000020: 429a cmp r2, r3
(1939) nzcv = ..1.
(1940) 00000022: d003 beq 0x0000002c
(1941) 00000024: 8843 ldrh r3, [r0, #2]
(1941) Read ROM [80] = 032d
(1942) r3 = 0000032d
(1943) 00000026: 3004 add r0, #4
(1943) r0 = 00000082
(1943) nzcv = ....
(1944) 00000028: 4291 cmp r1, r2
(1944) nzcv = ..1.
(1945) 0000002a: d1f7 bne 0x0000001c
(1946) 0000001c: 2300 movs r3, #0
(1946) r3 = 00000000
(1946) nzcv = .11.
(1947) 0000001e: 8802 ldrh r2, [r0, #0]
(1947) Read ROM [82] = 334c
(1948) r2 = 0000334c
(1949) 00000020: 429a cmp r2, r3
(1949) nzcv = ..1.
(1950) 00000022: d003 beq 0x0000002c
(1951) 00000024: 8843 ldrh r3, [r0, #2]
(1951) Read ROM [84] = 0357
(1952) r3 = 00000357
(1953) 00000026: 3004 add r0, #4
(1953) r0 = 00000086
(1953) nzcv = ....
(1954) 00000028: 4291 cmp r1, r2
(1954) nzcv = ..1.
(1955) 0000002a: d1f7 bne 0x0000001c
(1956) 0000001c: 2300 movs r3, #0
(1956) r3 = 00000000
(1956) nzcv = .11.
(1957) 0000001e: 8802 ldrh r2, [r0, #0]
(1957) Read ROM [86] = 3354
(1958) r2 = 00003354
(1959) 00000020: 429a cmp r2, r3
(1959) nzcv = ..1.
(1960) 00000022: d003 beq 0x0000002c
(1961) 00000024: 8843 ldrh r3, [r0, #2]
(1961) Read ROM [88] = 038f
(1962) r3 = 0000038f
(1963) 00000026: 3004 add r0, #4
(1963) r0 = 0000008a
(1963) nzcv = ....
(1964) 00000028: 4291 cmp r1, r2
(1964) nzcv = ..1.
(1965) 0000002a: d1f7 bne 0x0000001c
(1966) 0000001c: 2300 movs r3, #0
(1966) r3 = 00000000
(1966) nzcv = .11.
(1967) 0000001e: 8802 ldrh r2, [r0, #0]
(1967) Read ROM [8a] = 534d
(1968) r2 = 0000534d
(1969) 00000020: 429a cmp r2, r3
(1969) nzcv = ..1.
(1970) 00000022: d003 beq 0x0000002c
(1971) 00000024: 8843 ldrh r3, [r0, #2]
(1971) Read ROM [8c] = 26b9
(1972) r3 = 000026b9
(1973) 00000026: 3004 add r0, #4
(1973) r0 = 0000008e
(1973) nzcv = ....
(1974) 00000028: 4291 cmp r1, r2
(1974) nzcv = 1...
(1975) 0000002a: d1f7 bne 0x0000001c
(1976) 0000001c: 2300 movs r3, #0
(1976) r3 = 00000000
(1976) nzcv = .1..
(1977) 0000001e: 8802 ldrh r2, [r0, #0]
(1977) Read ROM [8e] = 3453
(1978) r2 = 00003453
(1979) 00000020: 429a cmp r2, r3
(1979) nzcv = ..1.
(1980) 00000022: d003 beq 0x0000002c
(1981) 00000024: 8843 ldrh r3, [r0, #2]
(1981) Read ROM [90] = 26ad
(1982) r3 = 000026ad
(1983) 00000026: 3004 add r0, #4
(1983) r0 = 00000092
(1983) nzcv = ....
(1984) 00000028: 4291 cmp r1, r2
(1984) nzcv = 1...
(1985) 0000002a: d1f7 bne 0x0000001c
(1986) 0000001c: 2300 movs r3, #0
(1986) r3 = 00000000
(1986) nzcv = .1..
(1987) 0000001e: 8802 ldrh r2, [r0, #0]
(1987) Read ROM [92] = 434d
(1988) r2 = 0000434d
(1989) 00000020: 429a cmp r2, r3
(1989) nzcv = ..1.
(1990) 00000022: d003 beq 0x0000002c
(1991) 00000024: 8843 ldrh r3, [r0, #2]
(1991) Read ROM [94] = 261d
(1992) r3 = 0000261d
(1993) 00000026: 3004 add r0, #4
(1993) r0 = 00000096
(1993) nzcv = ....
(1994) 00000028: 4291 cmp r1, r2
(1994) nzcv = 1...
(1995) 0000002a: d1f7 bne 0x0000001c
(1996) 0000001c: 2300 movs r3, #0
(1996) r3 = 00000000
(1996) nzcv = .1..
(1997) 0000001e: 8802 ldrh r2, [r0, #0]
(1997) Read ROM [96] = 3443
(1998) r2 = 00003443
(1999) 00000020: 429a cmp r2, r3
(1999) nzcv = ..1.
(2000) 00000022: d003 beq 0x0000002c
(2001) 00000024: 8843 ldrh r3, [r0, #2]
(2001) Read ROM [98] = 2605
(2002) r3 = 00002605
(2003) 00000026: 3004 add r0, #4
(2003) r0 = 0000009a
(2003) nzcv = ....
(2004) 00000028: 4291 cmp r1, r2
(2004) nzcv = .11.
(2005) 0000002a: d1f7 bne 0x0000001c
(2006) 0000002c: 1c18 movs r0, r3
(2006) r0 = 00002605
(2006) nzcv = ....
(2007) 0000002e: 4770 bx lr
(2008) 10001762: c401 stmia r4!, {r0}
(2008) Write SRAM [2000020c] = 00002605
(2009) r4 = 20000210
(2010) 10001764: 1e43 sub r3, r0, #1
(2010) r3 = 00002604
(2010) nzcv = ..1.
(2011) 10001766: 4198 sbc r0, r3
(2011) r0 = 00000001
(2012) 10001768: 3501 add r5, #1
(2012) r5 = 00000004
(2012) nzcv = ....
(2013) 1000176a: 4240 neg r0, r0
(2013) r0 = ffffffff
(2013) nzcv = 1...
(2014) 1000176c: 4006 ands r6, r0
(2014) r6 = 00000001
(2014) nzcv = ....
(2015) 1000176e: 42af cmp r7, r5
(2015) nzcv = .11.
(2016) 10001770: d1f1 bne 0x10001756
(2017) 10001772: 0030 movs r0, r6
(2017) r0 = 00000001
(2017) nzcv = ..1.
(2018) 10001774: bcc0 pop {r6, r7}
(2018) Read SRAM [20041ed0] = 00000000
(2019) r6 = 00000000
(2019) Read SRAM [20041ed4] = 00000000
(2020) r7 = 00000000
(2020) msp = 20041ed8
(2021) 10001776: 46b9 mov r9, r7
(2021) r9 = 00000000
(2022) 10001778: 46b0 mov r8, r6
(2022) r8 = 00000000
(2023) 1000177a: bdf8 pop {r3, r4, r5, r6, r7, pc}
(2023) Read SRAM [20041ed8] = 1000173d
(2024) r3 = 1000173d
(2024) Read SRAM [20041edc] = 00000000
(2025) r4 = 00000000
(2025) Read SRAM [20041ee0] = 20000230
(2026) r5 = 20000230
(2026) Read SRAM [20041ee4] = 00000003
(2027) r6 = 00000003
(2027) Read SRAM [20041ee8] = 00000000
(2028) r7 = 00000000
(2028) Read SRAM [20041eec] = 1000122a
(2029) msp = 20041ef0
(2030) 1000122a: 0023 movs r3, r4
(2030) r3 = 00000000
(2030) nzcv = .11.
(2031) 1000122c: 3401 add r4, #1
(2031) r4 = 00000001
(2031) nzcv = ....
(2032) 1000122e: 42b3 cmp r3, r6
(2032) nzcv = 1...
(2033) 10001230: d1f9 bne 0x10001226
(2034) 10001226: cd08 ldmia r5!, {r3}
(2034) Read SRAM [20000230] = 1000170d
(2035) r3 = 1000170d
(2035) r5 = 20000234
(2036) 10001228: 4798 blx r3
(2036) lr = 1000122a
(2037) 1000170c: 4801 ldr r0, [pc, #4]
(2037) Read Flash [10001714] = 200001f0
(2038) r0 = 200001f0
(2039) 1000170e: 2104 movs r1, #4
(2039) r1 = 00000004
(2039) nzcv = ....
(2040) 10001710: 4b01 ldr r3, [pc, #4]
(2040) Read Flash [10001718] = 1000173d
(2041) r3 = 1000173d
(2042) 10001712: 4718 bx r3
(2043) 1000173c: b5f8 push {r3, r4, r5, r6, r7, lr}
(2043) Write SRAM [20041eec] = 1000122a
(2044) Write SRAM [20041ee8] = 00000000
(2045) Write SRAM [20041ee4] = 00000003
(2046) Write SRAM [20041ee0] = 20000234
(2047) Write SRAM [20041edc] = 00000001
(2048) Write SRAM [20041ed8] = 1000173d
(2049) msp = 20041ed8
(2050) 1000173e: 4647 mov r7, r8
(2050) r7 = 00000000
(2051) 10001740: 46ce mov lr, r9
(2051) lr = 00000000
(2052) 10001742: b580 push {r7, lr}
(2052) Write SRAM [20041ed4] = 00000000
(2053) Write SRAM [20041ed0] = 00000000
(2054) msp = 20041ed0
(2055) 10001744: 1e0f movs r7, r1
(2055) r7 = 00000004
(2055) nzcv = ..1.
(2056) 10001746: d019 beq 0x1000177c
(2057) 10001748: 2314 movs r3, #20
(2057) r3 = 00000014
(2058) 1000174a: 4699 mov r9, r3
(2058) r9 = 00000014
(2059) 1000174c: 3304 add r3, #4
(2059) r3 = 00000018
(2059) nzcv = ....
(2060) 1000174e: 0004 movs r4, r0
(2060) r4 = 200001f0
(2061) 10001750: 2500 movs r5, #0
(2061) r5 = 00000000
(2061) nzcv = .1..
(2062) 10001752: 2601 movs r6, #1
(2062) r6 = 00000001
(2062) nzcv = ....
(2063) 10001754: 4698 mov r8, r3
(2063) r8 = 00000018
(2064) 10001756: 464b mov r3, r9
(2064) r3 = 00000014
(2065) 10001758: 8818 ldrh r0, [r3, #0]
(2065) Read ROM [14] = 007a
(2066) r0 = 0000007a
(2067) 1000175a: 4643 mov r3, r8
(2067) r3 = 00000018
(2068) 1000175c: 6821 ldr r1, [r4, #0]
(2068) Read SRAM [200001f0] = 00003350
(2069) r1 = 00003350
(2070) 1000175e: 881b ldrh r3, [r3, #0]
(2070) Read ROM [18] = 001d
(2071) r3 = 0000001d
(2072) 10001760: 4798 blx r3
(2072) lr = 10001762
(2073) 0000001c: 2300 movs r3, #0
(2073) r3 = 00000000
(2073) nzcv = .1..
(2074) 0000001e: 8802 ldrh r2, [r0, #0]
(2074) Read ROM [7a] = 3350
(2075) r2 = 00003350
(2076) 00000020: 429a cmp r2, r3
(2076) nzcv = ..1.
(2077) 00000022: d003 beq 0x0000002c
(2078) 00000024: 8843 ldrh r3, [r0, #2]
(2078) Read ROM [7c] = 0309
(2079) r3 = 00000309
(2080) 00000026: 3004 add r0, #4
(2080) r0 = 0000007e
(2080) nzcv = ....
(2081) 00000028: 4291 cmp r1, r2
(2081) nzcv = .11.
(2082) 0000002a: d1f7 bne 0x0000001c
(2083) 0000002c: 1c18 movs r0, r3
(2083) r0 = 00000309
(2083) nzcv = ....
(2084) 0000002e: 4770 bx lr
(2085) 10001762: c401 stmia r4!, {r0}
(2085) Write SRAM [200001f0] = 00000309
(2086) r4 = 200001f4
(2087) 10001764: 1e43 sub r3, r0, #1
(2087) r3 = 00000308
(2087) nzcv = ..1.
(2088) 10001766: 4198 sbc r0, r3
(2088) r0 = 00000001
(2089) 10001768: 3501 add r5, #1
(2089) r5 = 00000001
(2089) nzcv = ....
(2090) 1000176a: 4240 neg r0, r0
(2090) r0 = ffffffff
(2090) nzcv = 1...
(2091) 1000176c: 4006 ands r6, r0
(2091) r6 = 00000001
(2091) nzcv = ....
(2092) 1000176e: 42af cmp r7, r5
(2092) nzcv = ..1.
(2093) 10001770: d1f1 bne 0x10001756
(2094) 10001756: 464b mov r3, r9
(2094) r3 = 00000014
(2095) 10001758: 8818 ldrh r0, [r3, #0]
(2095) Read ROM [14] = 007a
(2096) r0 = 0000007a
(2097) 1000175a: 4643 mov r3, r8
(2097) r3 = 00000018
(2098) 1000175c: 6821 ldr r1, [r4, #0]
(2098) Read SRAM [200001f4] = 0000334c
(2099) r1 = 0000334c
(2100) 1000175e: 881b ldrh r3, [r3, #0]
(2100) Read ROM [18] = 001d
(2101) r3 = 0000001d
(2102) 10001760: 4798 blx r3
(2102) lr = 10001762
(2103) 0000001c: 2300 movs r3, #0
(2103) r3 = 00000000
(2103) nzcv = .11.
(2104) 0000001e: 8802 ldrh r2, [r0, #0]
(2104) Read ROM [7a] = 3350
(2105) r2 = 00003350
(2106) 00000020: 429a cmp r2, r3
(2106) nzcv = ..1.
(2107) 00000022: d003 beq 0x0000002c
(2108) 00000024: 8843 ldrh r3, [r0, #2]
(2108) Read ROM [7c] = 0309
(2109) r3 = 00000309
(2110) 00000026: 3004 add r0, #4
(2110) r0 = 0000007e
(2110) nzcv = ....
(2111) 00000028: 4291 cmp r1, r2
(2111) nzcv = 1...
(2112) 0000002a: d1f7 bne 0x0000001c
(2113) 0000001c: 2300 movs r3, #0
(2113) r3 = 00000000
(2113) nzcv = .1..
(2114) 0000001e: 8802 ldrh r2, [r0, #0]
(2114) Read ROM [7e] = 3352
(2115) r2 = 00003352
(2116) 00000020: 429a cmp r2, r3
(2116) nzcv = ..1.
(2117) 00000022: d003 beq 0x0000002c
(2118) 00000024: 8843 ldrh r3, [r0, #2]
(2118) Read ROM [80] = 032d
(2119) r3 = 0000032d
(2120) 00000026: 3004 add r0, #4
(2120) r0 = 00000082
(2120) nzcv = ....
(2121) 00000028: 4291 cmp r1, r2
(2121) nzcv = 1...
(2122) 0000002a: d1f7 bne 0x0000001c
(2123) 0000001c: 2300 movs r3, #0
(2123) r3 = 00000000
(2123) nzcv = .1..
(2124) 0000001e: 8802 ldrh r2, [r0, #0]
(2124) Read ROM [82] = 334c
(2125) r2 = 0000334c
(2126) 00000020: 429a cmp r2, r3
(2126) nzcv = ..1.
(2127) 00000022: d003 beq 0x0000002c
(2128) 00000024: 8843 ldrh r3, [r0, #2]
(2128) Read ROM [84] = 0357
(2129) r3 = 00000357
(2130) 00000026: 3004 add r0, #4
(2130) r0 = 00000086
(2130) nzcv = ....
(2131) 00000028: 4291 cmp r1, r2
(2131) nzcv = .11.
(2132) 0000002a: d1f7 bne 0x0000001c
(2133) 0000002c: 1c18 movs r0, r3
(2133) r0 = 00000357
(2133) nzcv = ....
(2134) 0000002e: 4770 bx lr
(2135) 10001762: c401 stmia r4!, {r0}
(2135) Write SRAM [200001f4] = 00000357
(2136) r4 = 200001f8
(2137) 10001764: 1e43 sub r3, r0, #1
(2137) r3 = 00000356
(2137) nzcv = ..1.
(2138) 10001766: 4198 sbc r0, r3
(2138) r0 = 00000001
(2139) 10001768: 3501 add r5, #1
(2139) r5 = 00000002
(2139) nzcv = ....
(2140) 1000176a: 4240 neg r0, r0
(2140) r0 = ffffffff
(2140) nzcv = 1...
(2141) 1000176c: 4006 ands r6, r0
(2141) r6 = 00000001
(2141) nzcv = ....
(2142) 1000176e: 42af cmp r7, r5
(2142) nzcv = ..1.
(2143) 10001770: d1f1 bne 0x10001756
(2144) 10001756: 464b mov r3, r9
(2144) r3 = 00000014
(2145) 10001758: 8818 ldrh r0, [r3, #0]
(2145) Read ROM [14] = 007a
(2146) r0 = 0000007a
(2147) 1000175a: 4643 mov r3, r8
(2147) r3 = 00000018
(2148) 1000175c: 6821 ldr r1, [r4, #0]
(2148) Read SRAM [200001f8] = 00003354
(2149) r1 = 00003354
(2150) 1000175e: 881b ldrh r3, [r3, #0]
(2150) Read ROM [18] = 001d
(2151) r3 = 0000001d
(2152) 10001760: 4798 blx r3
(2152) lr = 10001762
(2153) 0000001c: 2300 movs r3, #0
(2153) r3 = 00000000
(2153) nzcv = .11.
(2154) 0000001e: 8802 ldrh r2, [r0, #0]
(2154) Read ROM [7a] = 3350
(2155) r2 = 00003350
(2156) 00000020: 429a cmp r2, r3
(2156) nzcv = ..1.
(2157) 00000022: d003 beq 0x0000002c
(2158) 00000024: 8843 ldrh r3, [r0, #2]
(2158) Read ROM [7c] = 0309
(2159) r3 = 00000309
(2160) 00000026: 3004 add r0, #4
(2160) r0 = 0000007e
(2160) nzcv = ....
(2161) 00000028: 4291 cmp r1, r2
(2161) nzcv = ..1.
(2162) 0000002a: d1f7 bne 0x0000001c
(2163) 0000001c: 2300 movs r3, #0
(2163) r3 = 00000000
(2163) nzcv = .11.
(2164) 0000001e: 8802 ldrh r2, [r0, #0]
(2164) Read ROM [7e] = 3352
(2165) r2 = 00003352
(2166) 00000020: 429a cmp r2, r3
(2166) nzcv = ..1.
(2167) 00000022: d003 beq 0x0000002c
(2168) 00000024: 8843 ldrh r3, [r0, #2]
(2168) Read ROM [80] = 032d
(2169) r3 = 0000032d
(2170) 00000026: 3004 add r0, #4
(2170) r0 = 00000082
(2170) nzcv = ....
(2171) 00000028: 4291 cmp r1, r2
(2171) nzcv = ..1.
(2172) 0000002a: d1f7 bne 0x0000001c
(2173) 0000001c: 2300 movs r3, #0
(2173) r3 = 00000000
(2173) nzcv = .11.
(2174) 0000001e: 8802 ldrh r2, [r0, #0]
(2174) Read ROM [82] = 334c
(2175) r2 = 0000334c
(2176) 00000020: 429a cmp r2, r3
(2176) nzcv = ..1.
(2177) 00000022: d003 beq 0x0000002c
(2178) 00000024: 8843 ldrh r3, [r0, #2]
(2178) Read ROM [84] = 0357
(2179) r3 = 00000357
(2180) 00000026: 3004 add r0, #4
(2180) r0 = 00000086
(2180) nzcv = ....
(2181) 00000028: 4291 cmp r1, r2
(2181) nzcv = ..1.
(2182) 0000002a: d1f7 bne 0x0000001c
(2183) 0000001c: 2300 movs r3, #0
(2183) r3 = 00000000
(2183) nzcv = .11.
(2184) 0000001e: 8802 ldrh r2, [r0, #0]
(2184) Read ROM [86] = 3354
(2185) r2 = 00003354
(2186) 00000020: 429a cmp r2, r3
(2186) nzcv = ..1.
(2187) 00000022: d003 beq 0x0000002c
(2188) 00000024: 8843 ldrh r3, [r0, #2]
(2188) Read ROM [88] = 038f
(2189) r3 = 0000038f
(2190) 00000026: 3004 add r0, #4
(2190) r0 = 0000008a
(2190) nzcv = ....
(2191) 00000028: 4291 cmp r1, r2
(2191) nzcv = .11.
(2192) 0000002a: d1f7 bne 0x0000001c
(2193) 0000002c: 1c18 movs r0, r3
(2193) r0 = 0000038f
(2193) nzcv = ....
(2194) 0000002e: 4770 bx lr
(2195) 10001762: c401 stmia r4!, {r0}
(2195) Write SRAM [200001f8] = 0000038f
(2196) r4 = 200001fc
(2197) 10001764: 1e43 sub r3, r0, #1
(2197) r3 = 0000038e
(2197) nzcv = ..1.
(2198) 10001766: 4198 sbc r0, r3
(2198) r0 = 00000001
(2199) 10001768: 3501 add r5, #1
(2199) r5 = 00000003
(2199) nzcv = ....
(2200) 1000176a: 4240 neg r0, r0
(2200) r0 = ffffffff
(2200) nzcv = 1...
(2201) 1000176c: 4006 ands r6, r0
(2201) r6 = 00000001
(2201) nzcv = ....
(2202) 1000176e: 42af cmp r7, r5
(2202) nzcv = ..1.
(2203) 10001770: d1f1 bne 0x10001756
(2204) 10001756: 464b mov r3, r9
(2204) r3 = 00000014
(2205) 10001758: 8818 ldrh r0, [r3, #0]
(2205) Read ROM [14] = 007a
(2206) r0 = 0000007a
(2207) 1000175a: 4643 mov r3, r8
(2207) r3 = 00000018
(2208) 1000175c: 6821 ldr r1, [r4, #0]
(2208) Read SRAM [200001fc] = 00003352
(2209) r1 = 00003352
(2210) 1000175e: 881b ldrh r3, [r3, #0]
(2210) Read ROM [18] = 001d
(2211) r3 = 0000001d
(2212) 10001760: 4798 blx r3
(2212) lr = 10001762
(2213) 0000001c: 2300 movs r3, #0
(2213) r3 = 00000000
(2213) nzcv = .11.
(2214) 0000001e: 8802 ldrh r2, [r0, #0]
(2214) Read ROM [7a] = 3350
(2215) r2 = 00003350
(2216) 00000020: 429a cmp r2, r3
(2216) nzcv = ..1.
(2217) 00000022: d003 beq 0x0000002c
(2218) 00000024: 8843 ldrh r3, [r0, #2]
(2218) Read ROM [7c] = 0309
(2219) r3 = 00000309
(2220) 00000026: 3004 add r0, #4
(2220) r0 = 0000007e
(2220) nzcv = ....
(2221) 00000028: 4291 cmp r1, r2
(2221) nzcv = ..1.
(2222) 0000002a: d1f7 bne 0x0000001c
(2223) 0000001c: 2300 movs r3, #0
(2223) r3 = 00000000
(2223) nzcv = .11.
(2224) 0000001e: 8802 ldrh r2, [r0, #0]
(2224) Read ROM [7e] = 3352
(2225) r2 = 00003352
(2226) 00000020: 429a cmp r2, r3
(2226) nzcv = ..1.
(2227) 00000022: d003 beq 0x0000002c
(2228) 00000024: 8843 ldrh r3, [r0, #2]
(2228) Read ROM [80] = 032d
(2229) r3 = 0000032d
(2230) 00000026: 3004 add r0, #4
(2230) r0 = 00000082
(2230) nzcv = ....
(2231) 00000028: 4291 cmp r1, r2
(2231) nzcv = .11.
(2232) 0000002a: d1f7 bne 0x0000001c
(2233) 0000002c: 1c18 movs r0, r3
(2233) r0 = 0000032d
(2233) nzcv = ....
(2234) 0000002e: 4770 bx lr
(2235) 10001762: c401 stmia r4!, {r0}
(2235) Write SRAM [200001fc] = 0000032d
(2236) r4 = 20000200
(2237) 10001764: 1e43 sub r3, r0, #1
(2237) r3 = 0000032c
(2237) nzcv = ..1.
(2238) 10001766: 4198 sbc r0, r3
(2238) r0 = 00000001
(2239) 10001768: 3501 add r5, #1
(2239) r5 = 00000004
(2239) nzcv = ....
(2240) 1000176a: 4240 neg r0, r0
(2240) r0 = ffffffff
(2240) nzcv = 1...
(2241) 1000176c: 4006 ands r6, r0
(2241) r6 = 00000001
(2241) nzcv = ....
(2242) 1000176e: 42af cmp r7, r5
(2242) nzcv = .11.
(2243) 10001770: d1f1 bne 0x10001756
(2244) 10001772: 0030 movs r0, r6
(2244) r0 = 00000001
(2244) nzcv = ..1.
(2245) 10001774: bcc0 pop {r6, r7}
(2245) Read SRAM [20041ed0] = 00000000
(2246) r6 = 00000000
(2246) Read SRAM [20041ed4] = 00000000
(2247) r7 = 00000000
(2247) msp = 20041ed8
(2248) 10001776: 46b9 mov r9, r7
(2248) r9 = 00000000
(2249) 10001778: 46b0 mov r8, r6
(2249) r8 = 00000000
(2250) 1000177a: bdf8 pop {r3, r4, r5, r6, r7, pc}
(2250) Read SRAM [20041ed8] = 1000173d
(2251) r3 = 1000173d
(2251) Read SRAM [20041edc] = 00000001
(2252) r4 = 00000001
(2252) Read SRAM [20041ee0] = 20000234
(2253) r5 = 20000234
(2253) Read SRAM [20041ee4] = 00000003
(2254) r6 = 00000003
(2254) Read SRAM [20041ee8] = 00000000
(2255) r7 = 00000000
(2255) Read SRAM [20041eec] = 1000122a
(2256) msp = 20041ef0
(2257) 1000122a: 0023 movs r3, r4
(2257) r3 = 00000001
(2258) 1000122c: 3401 add r4, #1
(2258) r4 = 00000002
(2258) nzcv = ....
(2259) 1000122e: 42b3 cmp r3, r6
(2259) nzcv = 1...
(2260) 10001230: d1f9 bne 0x10001226
(2261) 10001226: cd08 ldmia r5!, {r3}
(2261) Read SRAM [20000234] = 100017cd
(2262) r3 = 100017cd
(2262) r5 = 20000238
(2263) 10001228: 4798 blx r3
(2263) lr = 1000122a
(2264) 100017cc: 2313 movs r3, #19
(2264) r3 = 00000013
(2264) nzcv = ....
(2265) 100017ce: b570 push {r4, r5, r6, lr}
(2265) Write SRAM [20041eec] = 1000122a
(2266) Write SRAM [20041ee8] = 00000003
(2267) Write SRAM [20041ee4] = 20000238
(2268) Write SRAM [20041ee0] = 00000002
(2269) msp = 20041ee0
(2270) 100017d0: 781d ldrb r5, [r3, #0]
(2270) Read ROM [13] = 03
(2271) r5 = 00000003
(2272) 100017d2: 2d01 cmp r5, #1
(2272) nzcv = ..1.
(2273) 100017d4: d015 beq 0x10001802
(2274) 100017d6: dd10 ble 0x100017fa
(2275) 100017d8: 481d ldr r0, [pc, #116]
(2275) Read Flash [10001850] = 00004453
(2276) r0 = 00004453
(2278) 100017da: f7ffffa7 bl 0x1000172c
(2278) lr = 100017de
(2279) 1000172c: 2316 movs r3, #22
(2279) r3 = 00000016
(2280) 1000172e: b510 push {r4, lr}
(2280) Write SRAM [20041edc] = 100017de
(2281) Write SRAM [20041ed8] = 00000002
(2282) msp = 20041ed8
(2283) 10001730: 0001 movs r1, r0
(2283) r1 = 00004453
(2284) 10001732: 8818 ldrh r0, [r3, #0]
(2284) Read ROM [16] = 00c4
(2285) r0 = 000000c4
(2286) 10001734: 3302 add r3, #2
(2286) r3 = 00000018
(2286) nzcv = ....
(2287) 10001736: 881b ldrh r3, [r3, #0]
(2287) Read ROM [18] = 001d
(2288) r3 = 0000001d
(2289) 10001738: 4798 blx r3
(2289) lr = 1000173a
(2290) 0000001c: 2300 movs r3, #0
(2290) r3 = 00000000
(2290) nzcv = .1..
(2291) 0000001e: 8802 ldrh r2, [r0, #0]
(2291) Read ROM [c4] = 5247
(2292) r2 = 00005247
(2293) 00000020: 429a cmp r2, r3
(2293) nzcv = ..1.
(2294) 00000022: d003 beq 0x0000002c
(2295) 00000024: 8843 ldrh r3, [r0, #2]
(2295) Read ROM [c6] = 0050
(2296) r3 = 00000050
(2297) 00000026: 3004 add r0, #4
(2297) r0 = 000000c8
(2297) nzcv = ....
(2298) 00000028: 4291 cmp r1, r2
(2298) nzcv = 1...
(2299) 0000002a: d1f7 bne 0x0000001c
(2300) 0000001c: 2300 movs r3, #0
(2300) r3 = 00000000
(2300) nzcv = .1..
(2301) 0000001e: 8802 ldrh r2, [r0, #0]
(2301) Read ROM [c8] = 5243
(2302) r2 = 00005243
(2303) 00000020: 429a cmp r2, r3
(2303) nzcv = ..1.
(2304) 00000022: d003 beq 0x0000002c
(2305) 00000024: 8843 ldrh r3, [r0, #2]
(2305) Read ROM [ca] = 0058
(2306) r3 = 00000058
(2307) 00000026: 3004 add r0, #4
(2307) r0 = 000000cc
(2307) nzcv = ....
(2308) 00000028: 4291 cmp r1, r2
(2308) nzcv = 1...
(2309) 0000002a: d1f7 bne 0x0000001c
(2310) 0000001c: 2300 movs r3, #0
(2310) r3 = 00000000
(2310) nzcv = .1..
(2311) 0000001e: 8802 ldrh r2, [r0, #0]
(2311) Read ROM [cc] = 4653
(2312) r2 = 00004653
(2313) 00000020: 429a cmp r2, r3
(2313) nzcv = ..1.
(2314) 00000022: d003 beq 0x0000002c
(2315) 00000024: 8843 ldrh r3, [r0, #2]
(2315) Read ROM [ce] = 01cc
(2316) r3 = 000001cc
(2317) 00000026: 3004 add r0, #4
(2317) r0 = 000000d0
(2317) nzcv = ....
(2318) 00000028: 4291 cmp r1, r2
(2318) nzcv = 1...
(2319) 0000002a: d1f7 bne 0x0000001c
(2320) 0000001c: 2300 movs r3, #0
(2320) r3 = 00000000
(2320) nzcv = .1..
(2321) 0000001e: 8802 ldrh r2, [r0, #0]
(2321) Read ROM [d0] = 4453
(2322) r2 = 00004453
(2323) 00000020: 429a cmp r2, r3
(2323) nzcv = ..1.
(2324) 00000022: d003 beq 0x0000002c
(2325) 00000024: 8843 ldrh r3, [r0, #2]
(2325) Read ROM [d2] = 024c
(2326) r3 = 0000024c
(2327) 00000026: 3004 add r0, #4
(2327) r0 = 000000d4
(2327) nzcv = ....
(2328) 00000028: 4291 cmp r1, r2
(2328) nzcv = .11.
(2329) 0000002a: d1f7 bne 0x0000001c
(2330) 0000002c: 1c18 movs r0, r3
(2330) r0 = 0000024c
(2330) nzcv = ....
(2331) 0000002e: 4770 bx lr
(2332) 1000173a: bd10 pop {r4, pc}
(2332) Read SRAM [20041ed8] = 00000002
(2333) r4 = 00000002
(2333) Read SRAM [20041edc] = 100017de
(2334) msp = 20041ee0
(2335) 100017de: 4c1d ldr r4, [pc, #116]
(2335) Read Flash [10001854] = 20000368
(2336) r4 = 20000368
(2337) 100017e0: 0001 movs r1, r0
(2337) r1 = 0000024c
(2338) 100017e2: 2280 movs r2, #128
(2338) r2 = 00000080
(2339) 100017e4: 0020 movs r0, r4
(2339) r0 = 20000368
(2341) 100017e6: f000f8a3 bl 0x10001930
(2341) lr = 100017ea
(2342) 10001930: 4b01 ldr r3, [pc, #4]
(2342) Read Flash [10001938] = 20000200
(2343) r3 = 20000200
(2344) 10001932: 685b ldr r3, [r3, #4]
(2344) Read SRAM [20000204] = 0000261d
(2345) r3 = 0000261d
(2346) 10001934: 4718 bx r3
(2347) 0000261c: 4684 mov ip, r0
(2347) ip = 20000368
(2348) 0000261e: 2a08 cmp r2, #8
(2348) nzcv = ..1.
(2349) 00002620: d32e bcc 0x00002680
(2350) 00002622: 1a43 sub r3, r0, r1
(2350) r3 = 2000011c
(2351) 00002624: 079b lsls r3, r3, #30
(2351) r3 = 00000000
(2351) nzcv = .11.
(2352) 00002626: d1f2 bne 0x0000260e
(2353) 00002628: b470 push {r4, r5, r6}
(2353) Write SRAM [20041edc] = 00000003
(2354) Write SRAM [20041ed8] = 00000003
(2355) Write SRAM [20041ed4] = 20000368
(2356) msp = 20041ed4
(2357) 0000262a: 1a09 sub r1, r1, r0
(2357) r1 = dffffee4
(2357) nzcv = 1...
(2358) 0000262c: 1c05 movs r5, r0
(2358) r5 = 20000368
(2358) nzcv = ....
(2359) 0000262e: 0843 lsrs r3, r0, #1
(2359) r3 = 100001b4
(2360) 00002630: d302 bcc 0x00002638
(2361) 00002638: 0883 lsrs r3, r0, #2
(2361) r3 = 080000da
(2362) 0000263a: d302 bcc 0x00002642
(2363) 00002642: 1809 add r1, r1, r0
(2363) r1 = 0000024c
(2363) nzcv = ..1.
(2364) 00002644: 1a2d sub r5, r5, r0
(2364) r5 = 00000000
(2364) nzcv = .11.
(2365) 00002646: 1952 add r2, r2, r5
(2365) r2 = 00000080
(2365) nzcv = ....
(2366) 00002648: 3a10 sub r2, #16
(2366) r2 = 00000070
(2366) nzcv = ..1.
(2367) 0000264a: d303 bcc 0x00002654
(2368) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2368) Read ROM [24c] = 00002e3d
(2369) r3 = 00002e3d
(2369) Read ROM [250] = 00002e31
(2370) r4 = 00002e31
(2370) Read ROM [254] = 00002f99
(2371) r5 = 00002f99
(2371) Read ROM [258] = 000030f5
(2372) r6 = 000030f5
(2372) r1 = 0000025c
(2373) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2373) Write SRAM [20000368] = 00002e3d
(2374) Write SRAM [2000036c] = 00002e31
(2375) Write SRAM [20000370] = 00002f99
(2376) Write SRAM [20000374] = 000030f5
(2377) r0 = 20000378
(2378) 00002650: 3a10 sub r2, #16
(2378) r2 = 00000060
(2379) 00002652: d2fb bcs 0x0000264c
(2380) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2380) Read ROM [25c] = 00003447
(2381) r3 = 00003447
(2381) Read ROM [260] = 00003447
(2382) r4 = 00003447
(2382) Read ROM [264] = 000032b9
(2383) r5 = 000032b9
(2383) Read ROM [268] = 00003541
(2384) r6 = 00003541
(2384) r1 = 0000026c
(2385) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2385) Write SRAM [20000378] = 00003447
(2386) Write SRAM [2000037c] = 00003447
(2387) Write SRAM [20000380] = 000032b9
(2388) Write SRAM [20000384] = 00003541
(2389) r0 = 20000388
(2390) 00002650: 3a10 sub r2, #16
(2390) r2 = 00000050
(2391) 00002652: d2fb bcs 0x0000264c
(2392) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2392) Read ROM [26c] = 00003543
(2393) r3 = 00003543
(2393) Read ROM [270] = 0000354f
(2394) r4 = 0000354f
(2394) Read ROM [274] = 00003551
(2395) r5 = 00003551
(2395) Read ROM [278] = 0000369f
(2396) r6 = 0000369f
(2396) r1 = 0000027c
(2397) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2397) Write SRAM [20000388] = 00003543
(2398) Write SRAM [2000038c] = 0000354f
(2399) Write SRAM [20000390] = 00003551
(2400) Write SRAM [20000394] = 0000369f
(2401) r0 = 20000398
(2402) 00002650: 3a10 sub r2, #16
(2402) r2 = 00000040
(2403) 00002652: d2fb bcs 0x0000264c
(2404) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2404) Read ROM [27c] = 000036a1
(2405) r3 = 000036a1
(2405) Read ROM [280] = 00003697
(2406) r4 = 00003697
(2406) Read ROM [284] = 00003699
(2407) r5 = 00003699
(2407) Read ROM [288] = 0000380d
(2408) r6 = 0000380d
(2408) r1 = 0000028c
(2409) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2409) Write SRAM [20000398] = 000036a1
(2410) Write SRAM [2000039c] = 00003697
(2411) Write SRAM [200003a0] = 00003699
(2412) Write SRAM [200003a4] = 0000380d
(2413) r0 = 200003a8
(2414) 00002650: 3a10 sub r2, #16
(2414) r2 = 00000030
(2415) 00002652: d2fb bcs 0x0000264c
(2416) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2416) Read ROM [28c] = 0000381d
(2417) r3 = 0000381d
(2417) Read ROM [290] = 000037ed
(2418) r4 = 000037ed
(2418) Read ROM [294] = 00003831
(2419) r5 = 00003831
(2419) Read ROM [298] = 00003b3d
(2420) r6 = 00003b3d
(2420) r1 = 0000029c
(2421) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2421) Write SRAM [200003a8] = 0000381d
(2422) Write SRAM [200003ac] = 000037ed
(2423) Write SRAM [200003b0] = 00003831
(2424) Write SRAM [200003b4] = 00003b3d
(2425) r0 = 200003b8
(2426) 00002650: 3a10 sub r2, #16
(2426) r2 = 00000020
(2427) 00002652: d2fb bcs 0x0000264c
(2428) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2428) Read ROM [29c] = 00003bd9
(2429) r3 = 00003bd9
(2429) Read ROM [2a0] = 0000344b
(2430) r4 = 0000344b
(2430) Read ROM [2a4] = 00003929
(2431) r5 = 00003929
(2431) Read ROM [2a8] = 000036ad
(2432) r6 = 000036ad
(2432) r1 = 000002ac
(2433) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2433) Write SRAM [200003b8] = 00003bd9
(2434) Write SRAM [200003bc] = 0000344b
(2435) Write SRAM [200003c0] = 00003929
(2436) Write SRAM [200003c4] = 000036ad
(2437) r0 = 200003c8
(2438) 00002650: 3a10 sub r2, #16
(2438) r2 = 00000010
(2439) 00002652: d2fb bcs 0x0000264c
(2440) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2440) Read ROM [2ac] = 000036af
(2441) r3 = 000036af
(2441) Read ROM [2b0] = 000036a7
(2442) r4 = 000036a7
(2442) Read ROM [2b4] = 000036a9
(2443) r5 = 000036a9
(2443) Read ROM [2b8] = 0000359d
(2444) r6 = 0000359d
(2444) r1 = 000002bc
(2445) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2445) Write SRAM [200003c8] = 000036af
(2446) Write SRAM [200003cc] = 000036a7
(2447) Write SRAM [200003d0] = 000036a9
(2448) Write SRAM [200003d4] = 0000359d
(2449) r0 = 200003d8
(2450) 00002650: 3a10 sub r2, #16
(2450) r2 = 00000000
(2450) nzcv = .11.
(2451) 00002652: d2fb bcs 0x0000264c
(2452) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2452) Read ROM [2bc] = 0000359f
(2453) r3 = 0000359f
(2453) Read ROM [2c0] = 000035b7
(2454) r4 = 000035b7
(2454) Read ROM [2c4] = 000035b9
(2455) r5 = 000035b9
(2455) Read ROM [2c8] = 0000363f
(2456) r6 = 0000363f
(2456) r1 = 000002cc
(2457) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2457) Write SRAM [200003d8] = 0000359f
(2458) Write SRAM [200003dc] = 000035b7
(2459) Write SRAM [200003e0] = 000035b9
(2460) Write SRAM [200003e4] = 0000363f
(2461) r0 = 200003e8
(2462) 00002650: 3a10 sub r2, #16
(2462) r2 = fffffff0
(2462) nzcv = 1...
(2463) 00002652: d2fb bcs 0x0000264c
(2464) 00002654: 0752 lsls r2, r2, #29
(2464) r2 = 00000000
(2464) nzcv = .1..
(2465) 00002656: d301 bcc 0x0000265c
(2466) 0000265c: 0052 lsls r2, r2, #1
(2466) r2 = 00000000
(2467) 0000265e: d301 bcc 0x00002664
(2468) 00002664: d009 beq 0x0000267a
(2469) 0000267a: bc70 pop {r4, r5, r6}
(2469) Read SRAM [20041ed4] = 20000368
(2470) r4 = 20000368
(2470) Read SRAM [20041ed8] = 00000003
(2471) r5 = 00000003
(2471) Read SRAM [20041edc] = 00000003
(2472) r6 = 00000003
(2472) msp = 20041ee0
(2473) 0000267c: 4660 mov r0, ip
(2473) r0 = 20000368
(2474) 0000267e: 4770 bx lr
(2475) 100017ea: 2d02 cmp r5, #2
(2475) nzcv = ..1.
(2476) 100017ec: d02d beq 0x1000184a
(2477) 100017ee: 481a ldr r0, [pc, #104]
(2477) Read Flash [10001858] = 0000334c
(2478) r0 = 0000334c
(2480) 100017f0: f7ffff94 bl 0x1000171c
(2480) lr = 100017f4
(2481) 1000171c: 2314 movs r3, #20
(2481) r3 = 00000014
(2482) 1000171e: b510 push {r4, lr}
(2482) Write SRAM [20041edc] = 100017f4
(2483) Write SRAM [20041ed8] = 20000368
(2484) msp = 20041ed8
(2485) 10001720: 0001 movs r1, r0
(2485) r1 = 0000334c
(2486) 10001722: 8818 ldrh r0, [r3, #0]
(2486) Read ROM [14] = 007a
(2487) r0 = 0000007a
(2488) 10001724: 3304 add r3, #4
(2488) r3 = 00000018
(2488) nzcv = ....
(2489) 10001726: 881b ldrh r3, [r3, #0]
(2489) Read ROM [18] = 001d
(2490) r3 = 0000001d
(2491) 10001728: 4798 blx r3
(2491) lr = 1000172a
(2492) 0000001c: 2300 movs r3, #0
(2492) r3 = 00000000
(2492) nzcv = .1..
(2493) 0000001e: 8802 ldrh r2, [r0, #0]
(2493) Read ROM [7a] = 3350
(2494) r2 = 00003350
(2495) 00000020: 429a cmp r2, r3
(2495) nzcv = ..1.
(2496) 00000022: d003 beq 0x0000002c
(2497) 00000024: 8843 ldrh r3, [r0, #2]
(2497) Read ROM [7c] = 0309
(2498) r3 = 00000309
(2499) 00000026: 3004 add r0, #4
(2499) r0 = 0000007e
(2499) nzcv = ....
(2500) 00000028: 4291 cmp r1, r2
(2500) nzcv = 1...
(2501) 0000002a: d1f7 bne 0x0000001c
(2502) 0000001c: 2300 movs r3, #0
(2502) r3 = 00000000
(2502) nzcv = .1..
(2503) 0000001e: 8802 ldrh r2, [r0, #0]
(2503) Read ROM [7e] = 3352
(2504) r2 = 00003352
(2505) 00000020: 429a cmp r2, r3
(2505) nzcv = ..1.
(2506) 00000022: d003 beq 0x0000002c
(2507) 00000024: 8843 ldrh r3, [r0, #2]
(2507) Read ROM [80] = 032d
(2508) r3 = 0000032d
(2509) 00000026: 3004 add r0, #4
(2509) r0 = 00000082
(2509) nzcv = ....
(2510) 00000028: 4291 cmp r1, r2
(2510) nzcv = 1...
(2511) 0000002a: d1f7 bne 0x0000001c
(2512) 0000001c: 2300 movs r3, #0
(2512) r3 = 00000000
(2512) nzcv = .1..
(2513) 0000001e: 8802 ldrh r2, [r0, #0]
(2513) Read ROM [82] = 334c
(2514) r2 = 0000334c
(2515) 00000020: 429a cmp r2, r3
(2515) nzcv = ..1.
(2516) 00000022: d003 beq 0x0000002c
(2517) 00000024: 8843 ldrh r3, [r0, #2]
(2517) Read ROM [84] = 0357
(2518) r3 = 00000357
(2519) 00000026: 3004 add r0, #4
(2519) r0 = 00000086
(2519) nzcv = ....
(2520) 00000028: 4291 cmp r1, r2
(2520) nzcv = .11.
(2521) 0000002a: d1f7 bne 0x0000001c
(2522) 0000002c: 1c18 movs r0, r3
(2522) r0 = 00000357
(2522) nzcv = ....
(2523) 0000002e: 4770 bx lr
(2524) 1000172a: bd10 pop {r4, pc}
(2524) Read SRAM [20041ed8] = 20000368
(2525) r4 = 20000368
(2525) Read SRAM [20041edc] = 100017f4
(2526) msp = 20041ee0
(2527) 100017f4: 4b19 ldr r3, [pc, #100]
(2527) Read Flash [1000185c] = 200005ec
(2528) r3 = 200005ec
(2529) 100017f6: 6018 str r0, [r3, #0]
(2529) Write SRAM [200005ec] = 00000357
(2531) 100017f8: bd70 pop {r4, r5, r6, pc}
(2531) Read SRAM [20041ee0] = 00000002
(2532) r4 = 00000002
(2532) Read SRAM [20041ee4] = 20000238
(2533) r5 = 20000238
(2533) Read SRAM [20041ee8] = 00000003
(2534) r6 = 00000003
(2534) Read SRAM [20041eec] = 1000122a
(2535) msp = 20041ef0
(2536) 1000122a: 0023 movs r3, r4
(2536) r3 = 00000002
(2537) 1000122c: 3401 add r4, #1
(2537) r4 = 00000003
(2538) 1000122e: 42b3 cmp r3, r6
(2538) nzcv = 1...
(2539) 10001230: d1f9 bne 0x10001226
(2540) 10001226: cd08 ldmia r5!, {r3}
(2540) Read SRAM [20000238] = 10001891
(2541) r3 = 10001891
(2541) r5 = 2000023c
(2542) 10001228: 4798 blx r3
(2542) lr = 1000122a
(2543) 10001890: 2313 movs r3, #19
(2543) r3 = 00000013
(2543) nzcv = ....
(2544) 10001892: b510 push {r4, lr}
(2544) Write SRAM [20041eec] = 1000122a
(2545) Write SRAM [20041ee8] = 00000003
(2546) msp = 20041ee8
(2547) 10001894: 4812 ldr r0, [pc, #72]
(2547) Read Flash [100018e0] = 00004653
(2548) r0 = 00004653
(2549) 10001896: 781c ldrb r4, [r3, #0]
(2549) Read ROM [13] = 03
(2550) r4 = 00000003
(2552) 10001898: f7ffff48 bl 0x1000172c
(2552) lr = 1000189c
(2553) 1000172c: 2316 movs r3, #22
(2553) r3 = 00000016
(2554) 1000172e: b510 push {r4, lr}
(2554) Write SRAM [20041ee4] = 1000189c
(2555) Write SRAM [20041ee0] = 00000003
(2556) msp = 20041ee0
(2557) 10001730: 0001 movs r1, r0
(2557) r1 = 00004653
(2558) 10001732: 8818 ldrh r0, [r3, #0]
(2558) Read ROM [16] = 00c4
(2559) r0 = 000000c4
(2560) 10001734: 3302 add r3, #2
(2560) r3 = 00000018
(2561) 10001736: 881b ldrh r3, [r3, #0]
(2561) Read ROM [18] = 001d
(2562) r3 = 0000001d
(2563) 10001738: 4798 blx r3
(2563) lr = 1000173a
(2564) 0000001c: 2300 movs r3, #0
(2564) r3 = 00000000
(2564) nzcv = .1..
(2565) 0000001e: 8802 ldrh r2, [r0, #0]
(2565) Read ROM [c4] = 5247
(2566) r2 = 00005247
(2567) 00000020: 429a cmp r2, r3
(2567) nzcv = ..1.
(2568) 00000022: d003 beq 0x0000002c
(2569) 00000024: 8843 ldrh r3, [r0, #2]
(2569) Read ROM [c6] = 0050
(2570) r3 = 00000050
(2571) 00000026: 3004 add r0, #4
(2571) r0 = 000000c8
(2571) nzcv = ....
(2572) 00000028: 4291 cmp r1, r2
(2572) nzcv = 1...
(2573) 0000002a: d1f7 bne 0x0000001c
(2574) 0000001c: 2300 movs r3, #0
(2574) r3 = 00000000
(2574) nzcv = .1..
(2575) 0000001e: 8802 ldrh r2, [r0, #0]
(2575) Read ROM [c8] = 5243
(2576) r2 = 00005243
(2577) 00000020: 429a cmp r2, r3
(2577) nzcv = ..1.
(2578) 00000022: d003 beq 0x0000002c
(2579) 00000024: 8843 ldrh r3, [r0, #2]
(2579) Read ROM [ca] = 0058
(2580) r3 = 00000058
(2581) 00000026: 3004 add r0, #4
(2581) r0 = 000000cc
(2581) nzcv = ....
(2582) 00000028: 4291 cmp r1, r2
(2582) nzcv = 1...
(2583) 0000002a: d1f7 bne 0x0000001c
(2584) 0000001c: 2300 movs r3, #0
(2584) r3 = 00000000
(2584) nzcv = .1..
(2585) 0000001e: 8802 ldrh r2, [r0, #0]
(2585) Read ROM [cc] = 4653
(2586) r2 = 00004653
(2587) 00000020: 429a cmp r2, r3
(2587) nzcv = ..1.
(2588) 00000022: d003 beq 0x0000002c
(2589) 00000024: 8843 ldrh r3, [r0, #2]
(2589) Read ROM [ce] = 01cc
(2590) r3 = 000001cc
(2591) 00000026: 3004 add r0, #4
(2591) r0 = 000000d0
(2591) nzcv = ....
(2592) 00000028: 4291 cmp r1, r2
(2592) nzcv = .11.
(2593) 0000002a: d1f7 bne 0x0000001c
(2594) 0000002c: 1c18 movs r0, r3
(2594) r0 = 000001cc
(2594) nzcv = ....
(2595) 0000002e: 4770 bx lr
(2596) 1000173a: bd10 pop {r4, pc}
(2596) Read SRAM [20041ee0] = 00000003
(2597) r4 = 00000003
(2597) Read SRAM [20041ee4] = 1000189c
(2598) msp = 20041ee8
(2599) 1000189c: 0001 movs r1, r0
(2599) r1 = 000001cc
(2600) 1000189e: 2c01 cmp r4, #1
(2600) nzcv = ..1.
(2601) 100018a0: d00a beq 0x100018b8
(2602) 100018a2: dd03 ble 0x100018ac
(2603) 100018a4: 2280 movs r2, #128
(2603) r2 = 00000080
(2604) 100018a6: 480f ldr r0, [pc, #60]
(2604) Read Flash [100018e4] = 20000468
(2605) r0 = 20000468
(2607) 100018a8: f000f842 bl 0x10001930
(2607) lr = 100018ac
(2608) 10001930: 4b01 ldr r3, [pc, #4]
(2608) Read Flash [10001938] = 20000200
(2609) r3 = 20000200
(2610) 10001932: 685b ldr r3, [r3, #4]
(2610) Read SRAM [20000204] = 0000261d
(2611) r3 = 0000261d
(2612) 10001934: 4718 bx r3
(2613) 0000261c: 4684 mov ip, r0
(2613) ip = 20000468
(2614) 0000261e: 2a08 cmp r2, #8
(2615) 00002620: d32e bcc 0x00002680
(2616) 00002622: 1a43 sub r3, r0, r1
(2616) r3 = 2000029c
(2617) 00002624: 079b lsls r3, r3, #30
(2617) r3 = 00000000
(2617) nzcv = .11.
(2618) 00002626: d1f2 bne 0x0000260e
(2619) 00002628: b470 push {r4, r5, r6}
(2619) Write SRAM [20041ee4] = 00000003
(2620) Write SRAM [20041ee0] = 2000023c
(2621) Write SRAM [20041edc] = 00000003
(2622) msp = 20041edc
(2623) 0000262a: 1a09 sub r1, r1, r0
(2623) r1 = dffffd64
(2623) nzcv = 1...
(2624) 0000262c: 1c05 movs r5, r0
(2624) r5 = 20000468
(2624) nzcv = ....
(2625) 0000262e: 0843 lsrs r3, r0, #1
(2625) r3 = 10000234
(2626) 00002630: d302 bcc 0x00002638
(2627) 00002638: 0883 lsrs r3, r0, #2
(2627) r3 = 0800011a
(2628) 0000263a: d302 bcc 0x00002642
(2629) 00002642: 1809 add r1, r1, r0
(2629) r1 = 000001cc
(2629) nzcv = ..1.
(2630) 00002644: 1a2d sub r5, r5, r0
(2630) r5 = 00000000
(2630) nzcv = .11.
(2631) 00002646: 1952 add r2, r2, r5
(2631) r2 = 00000080
(2631) nzcv = ....
(2632) 00002648: 3a10 sub r2, #16
(2632) r2 = 00000070
(2632) nzcv = ..1.
(2633) 0000264a: d303 bcc 0x00002654
(2634) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2634) Read ROM [1cc] = 00002b45
(2635) r3 = 00002b45
(2635) Read ROM [1d0] = 00002b41
(2636) r4 = 00002b41
(2636) Read ROM [1d4] = 00002c0d
(2637) r5 = 00002c0d
(2637) Read ROM [1d8] = 00002cd9
(2638) r6 = 00002cd9
(2638) r1 = 000001dc
(2639) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2639) Write SRAM [20000468] = 00002b45
(2640) Write SRAM [2000046c] = 00002b41
(2641) Write SRAM [20000470] = 00002c0d
(2642) Write SRAM [20000474] = 00002cd9
(2643) r0 = 20000478
(2644) 00002650: 3a10 sub r2, #16
(2644) r2 = 00000060
(2645) 00002652: d2fb bcs 0x0000264c
(2646) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2646) Read ROM [1dc] = 00002803
(2647) r3 = 00002803
(2647) Read ROM [1e0] = 00002803
(2648) r4 = 00002803
(2648) Read ROM [1e4] = 00002d8d
(2649) r5 = 00002d8d
(2649) Read ROM [1e8] = 00002829
(2650) r6 = 00002829
(2650) r1 = 000001ec
(2651) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2651) Write SRAM [20000478] = 00002803
(2652) Write SRAM [2000047c] = 00002803
(2653) Write SRAM [20000480] = 00002d8d
(2654) Write SRAM [20000484] = 00002829
(2655) r0 = 20000488
(2656) 00002650: 3a10 sub r2, #16
(2656) r2 = 00000050
(2657) 00002652: d2fb bcs 0x0000264c
(2658) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2658) Read ROM [1ec] = 0000282b
(2659) r3 = 0000282b
(2659) Read ROM [1f0] = 0000285d
(2660) r4 = 0000285d
(2660) Read ROM [1f4] = 0000285f
(2661) r5 = 0000285f
(2661) Read ROM [1f8] = 000028b3
(2662) r6 = 000028b3
(2662) r1 = 000001fc
(2663) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2663) Write SRAM [20000488] = 0000282b
(2664) Write SRAM [2000048c] = 0000285d
(2665) Write SRAM [20000490] = 0000285f
(2666) Write SRAM [20000494] = 000028b3
(2667) r0 = 20000498
(2668) 00002650: 3a10 sub r2, #16
(2668) r2 = 00000040
(2669) 00002652: d2fb bcs 0x0000264c
(2670) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2670) Read ROM [1fc] = 000028b5
(2671) r3 = 000028b5
(2671) Read ROM [200] = 000028c3
(2672) r4 = 000028c3
(2672) Read ROM [204] = 000028c5
(2673) r5 = 000028c5
(2673) Read ROM [208] = 0000299b
(2674) r6 = 0000299b
(2674) r1 = 0000020c
(2675) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2675) Write SRAM [20000498] = 000028b5
(2676) Write SRAM [2000049c] = 000028c3
(2677) Write SRAM [200004a0] = 000028c5
(2678) Write SRAM [200004a4] = 0000299b
(2679) r0 = 200004a8
(2680) 00002650: 3a10 sub r2, #16
(2680) r2 = 00000030
(2681) 00002652: d2fb bcs 0x0000264c
(2682) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2682) Read ROM [20c] = 00002951
(2683) r3 = 00002951
(2683) Read ROM [210] = 000029b9
(2684) r4 = 000029b9
(2684) Read ROM [214] = 00002951
(2685) r5 = 00002951
(2685) Read ROM [218] = 000029c1
(2686) r6 = 000029c1
(2686) r1 = 0000021c
(2687) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2687) Write SRAM [200004a8] = 00002951
(2688) Write SRAM [200004ac] = 000029b9
(2689) Write SRAM [200004b0] = 00002951
(2690) Write SRAM [200004b4] = 000029c1
(2691) r0 = 200004b8
(2692) 00002650: 3a10 sub r2, #16
(2692) r2 = 00000020
(2693) 00002652: d2fb bcs 0x0000264c
(2694) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2694) Read ROM [21c] = 00002a2b
(2695) r3 = 00002a2b
(2695) Read ROM [220] = 000027e7
(2696) r4 = 000027e7
(2696) Read ROM [224] = 00002a4f
(2697) r5 = 00002a4f
(2697) Read ROM [228] = 0000288b
(2698) r6 = 0000288b
(2698) r1 = 0000022c
(2699) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2699) Write SRAM [200004b8] = 00002a2b
(2700) Write SRAM [200004bc] = 000027e7
(2701) Write SRAM [200004c0] = 00002a4f
(2702) Write SRAM [200004c4] = 0000288b
(2703) r0 = 200004c8
(2704) 00002650: 3a10 sub r2, #16
(2704) r2 = 00000010
(2705) 00002652: d2fb bcs 0x0000264c
(2706) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2706) Read ROM [22c] = 0000288d
(2707) r3 = 0000288d
(2707) Read ROM [230] = 00002879
(2708) r4 = 00002879
(2708) Read ROM [234] = 0000287b
(2709) r5 = 0000287b
(2709) Read ROM [238] = 0000355d
(2710) r6 = 0000355d
(2710) r1 = 0000023c
(2711) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2711) Write SRAM [200004c8] = 0000288d
(2712) Write SRAM [200004cc] = 00002879
(2713) Write SRAM [200004d0] = 0000287b
(2714) Write SRAM [200004d4] = 0000355d
(2715) r0 = 200004d8
(2716) 00002650: 3a10 sub r2, #16
(2716) r2 = 00000000
(2716) nzcv = .11.
(2717) 00002652: d2fb bcs 0x0000264c
(2718) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(2718) Read ROM [23c] = 0000355f
(2719) r3 = 0000355f
(2719) Read ROM [240] = 00003567
(2720) r4 = 00003567
(2720) Read ROM [244] = 00003569
(2721) r5 = 00003569
(2721) Read ROM [248] = 00003619
(2722) r6 = 00003619
(2722) r1 = 0000024c
(2723) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(2723) Write SRAM [200004d8] = 0000355f
(2724) Write SRAM [200004dc] = 00003567
(2725) Write SRAM [200004e0] = 00003569
(2726) Write SRAM [200004e4] = 00003619
(2727) r0 = 200004e8
(2728) 00002650: 3a10 sub r2, #16
(2728) r2 = fffffff0
(2728) nzcv = 1...
(2729) 00002652: d2fb bcs 0x0000264c
(2730) 00002654: 0752 lsls r2, r2, #29
(2730) r2 = 00000000
(2730) nzcv = .1..
(2731) 00002656: d301 bcc 0x0000265c
(2732) 0000265c: 0052 lsls r2, r2, #1
(2732) r2 = 00000000
(2733) 0000265e: d301 bcc 0x00002664
(2734) 00002664: d009 beq 0x0000267a
(2735) 0000267a: bc70 pop {r4, r5, r6}
(2735) Read SRAM [20041edc] = 00000003
(2736) r4 = 00000003
(2736) Read SRAM [20041ee0] = 2000023c
(2737) r5 = 2000023c
(2737) Read SRAM [20041ee4] = 00000003
(2738) r6 = 00000003
(2738) msp = 20041ee8
(2739) 0000267c: 4660 mov r0, ip
(2739) r0 = 20000468
(2740) 0000267e: 4770 bx lr
(2741) 100018ac: 480e ldr r0, [pc, #56]
(2741) Read Flash [100018e8] = 0000334c
(2742) r0 = 0000334c
(2744) 100018ae: f7ffff35 bl 0x1000171c
(2744) lr = 100018b2
(2745) 1000171c: 2314 movs r3, #20
(2745) r3 = 00000014
(2745) nzcv = ....
(2746) 1000171e: b510 push {r4, lr}
(2746) Write SRAM [20041ee4] = 100018b2
(2747) Write SRAM [20041ee0] = 00000003
(2748) msp = 20041ee0
(2749) 10001720: 0001 movs r1, r0
(2749) r1 = 0000334c
(2750) 10001722: 8818 ldrh r0, [r3, #0]
(2750) Read ROM [14] = 007a
(2751) r0 = 0000007a
(2752) 10001724: 3304 add r3, #4
(2752) r3 = 00000018
(2753) 10001726: 881b ldrh r3, [r3, #0]
(2753) Read ROM [18] = 001d
(2754) r3 = 0000001d
(2755) 10001728: 4798 blx r3
(2755) lr = 1000172a
(2756) 0000001c: 2300 movs r3, #0
(2756) r3 = 00000000
(2756) nzcv = .1..
(2757) 0000001e: 8802 ldrh r2, [r0, #0]
(2757) Read ROM [7a] = 3350
(2758) r2 = 00003350
(2759) 00000020: 429a cmp r2, r3
(2759) nzcv = ..1.
(2760) 00000022: d003 beq 0x0000002c
(2761) 00000024: 8843 ldrh r3, [r0, #2]
(2761) Read ROM [7c] = 0309
(2762) r3 = 00000309
(2763) 00000026: 3004 add r0, #4
(2763) r0 = 0000007e
(2763) nzcv = ....
(2764) 00000028: 4291 cmp r1, r2
(2764) nzcv = 1...
(2765) 0000002a: d1f7 bne 0x0000001c
(2766) 0000001c: 2300 movs r3, #0
(2766) r3 = 00000000
(2766) nzcv = .1..
(2767) 0000001e: 8802 ldrh r2, [r0, #0]
(2767) Read ROM [7e] = 3352
(2768) r2 = 00003352
(2769) 00000020: 429a cmp r2, r3
(2769) nzcv = ..1.
(2770) 00000022: d003 beq 0x0000002c
(2771) 00000024: 8843 ldrh r3, [r0, #2]
(2771) Read ROM [80] = 032d
(2772) r3 = 0000032d
(2773) 00000026: 3004 add r0, #4
(2773) r0 = 00000082
(2773) nzcv = ....
(2774) 00000028: 4291 cmp r1, r2
(2774) nzcv = 1...
(2775) 0000002a: d1f7 bne 0x0000001c
(2776) 0000001c: 2300 movs r3, #0
(2776) r3 = 00000000
(2776) nzcv = .1..
(2777) 0000001e: 8802 ldrh r2, [r0, #0]
(2777) Read ROM [82] = 334c
(2778) r2 = 0000334c
(2779) 00000020: 429a cmp r2, r3
(2779) nzcv = ..1.
(2780) 00000022: d003 beq 0x0000002c
(2781) 00000024: 8843 ldrh r3, [r0, #2]
(2781) Read ROM [84] = 0357
(2782) r3 = 00000357
(2783) 00000026: 3004 add r0, #4
(2783) r0 = 00000086
(2783) nzcv = ....
(2784) 00000028: 4291 cmp r1, r2
(2784) nzcv = .11.
(2785) 0000002a: d1f7 bne 0x0000001c
(2786) 0000002c: 1c18 movs r0, r3
(2786) r0 = 00000357
(2786) nzcv = ....
(2787) 0000002e: 4770 bx lr
(2788) 1000172a: bd10 pop {r4, pc}
(2788) Read SRAM [20041ee0] = 00000003
(2789) r4 = 00000003
(2789) Read SRAM [20041ee4] = 100018b2
(2790) msp = 20041ee8
(2791) 100018b2: 4b0e ldr r3, [pc, #56]
(2791) Read Flash [100018ec] = 200005ec
(2792) r3 = 200005ec
(2793) 100018b4: 6018 str r0, [r3, #0]
(2793) Write SRAM [200005ec] = 00000357
(2795) 100018b6: bd10 pop {r4, pc}
(2795) Read SRAM [20041ee8] = 00000003
(2796) r4 = 00000003
(2796) Read SRAM [20041eec] = 1000122a
(2797) msp = 20041ef0
(2798) 1000122a: 0023 movs r3, r4
(2798) r3 = 00000003
(2799) 1000122c: 3401 add r4, #1
(2799) r4 = 00000004
(2800) 1000122e: 42b3 cmp r3, r6
(2800) nzcv = .11.
(2801) 10001230: d1f9 bne 0x10001226
(2803) 10001232: f000f87b bl 0x1000132c
(2803) lr = 10001236
(2804) 1000132c: b510 push {r4, lr}
(2804) Write SRAM [20041eec] = 10001236
(2805) Write SRAM [20041ee8] = 00000004
(2806) msp = 20041ee8
(2807) 1000132e: 200c movs r0, #12
(2807) r0 = 0000000c
(2807) nzcv = ..1.
(2808) 10001330: b082 sub sp, #8
(2808) msp = 20041ee0
(2810) 10001332: f000f9af bl 0x10001694
(2810) lr = 10001336
(2811) 10001694: 2380 movs r3, #128
(2811) r3 = 00000080
(2812) 10001696: 4a02 ldr r2, [pc, #8]
(2812) Read Flash [100016a0] = 40058000
(2813) r2 = 40058000
(2814) 10001698: 009b lsls r3, r3, #2
(2814) r3 = 00000200
(2814) nzcv = ....
(2815) 1000169a: 4303 orrs r3, r0
(2815) r3 = 0000020c
(2816) 1000169c: 62d3 str r3, [r2, #44]
(2816) Write WATCHDOG_TICK = 0000020c
(2818) 1000169e: 4770 bx lr
(2820) 10001336: f7fff82f bl 0x10000398
(2820) lr = 1000133a
(2821) 10000398: 4b02 ldr r3, [pc, #8]
(2821) Read Flash [100003a4] = 4006c000
(2822) r3 = 4006c000
(2823) 1000039a: 6818 ldr r0, [r3, #0]
(2823) Read TBMAN_PLATFORM = 00000001
(2824) r0 = 00000001
(2825) 1000039c: 0780 lsls r0, r0, #30
(2825) r0 = 40000000
(2826) 1000039e: 0fc0 lsrs r0, r0, #31
(2826) r0 = 00000000
(2826) nzcv = .11.
(2827) 100003a0: 4770 bx lr
(2828) 1000133a: 2800 cmp r0, #0
(2829) 1000133c: d010 beq 0x10001360
(2830) 10001360: 4c80 ldr r4, [pc, #512]
(2830) Read Flash [10001564] = 40008000
(2831) r4 = 40008000
(2832) 10001362: 67a0 str r0, [r4, #120]
(2832) Write CLK_SYS_RESUS_CTRL = 00000000
(2835) 10001364: f000f99e bl 0x100016a4
(2835) lr = 10001368
(2836) 100016a4: 23aa movs r3, #170
(2836) r3 = 000000aa
(2836) nzcv = ..1.
(2837) 100016a6: 4a06 ldr r2, [pc, #24]
(2837) Read Flash [100016c0] = 40024000
(2838) r2 = 40024000
(2839) 100016a8: 011b lsls r3, r3, #4
(2839) r3 = 00000aa0
(2839) nzcv = ....
(2840) 100016aa: 6013 str r3, [r2, #0]
(2840) Write XOSC_CTRL = 00000aa0
(2842) 100016ac: 232f movs r3, #47
(2842) r3 = 0000002f
(2843) 100016ae: 4905 ldr r1, [pc, #20]
(2843) Read Flash [100016c4] = 00fab000
(2844) r1 = 00fab000
(2845) 100016b0: 60d3 str r3, [r2, #12]
(2845) Write XOSC_STARTUP = 0000002f
(2847) 100016b2: 4b05 ldr r3, [pc, #20]
(2847) Read Flash [100016c8] = 40026000
(2848) r3 = 40026000
(2849) 100016b4: 6019 str r1, [r3, #0]
(2849) Write XOSC_CTRL:set = 00fab000
(2851) 100016b6: 6853 ldr r3, [r2, #4]
(2851) Read XOSC_STATUS = 80000000
(2852) r3 = 80000000
(2853) 100016b8: 2b00 cmp r3, #0
(2853) nzcv = 1.1.
(2854) 100016ba: dafc bge 0x100016b6
(2855) 100016bc: 4770 bx lr
(2856) 10001368: 2201 movs r2, #1
(2856) r2 = 00000001
(2856) nzcv = ..1.
(2857) 1000136a: 4b7f ldr r3, [pc, #508]
(2857) Read Flash [10001568] = 4000b03c
(2858) r3 = 4000b03c
(2859) 1000136c: 601a str r2, [r3, #0]
(2859) Write CLK_SYS_CTRL:clr = 00000001
(2861) 1000136e: 6c63 ldr r3, [r4, #68]
(2861) Read CLK_SYS_SELECTED = 00000001
(2862) r3 = 00000001
(2863) 10001370: 2b01 cmp r3, #1
(2863) nzcv = .11.
(2864) 10001372: d1fc bne 0x1000136e
(2865) 10001374: 2203 movs r2, #3
(2865) r2 = 00000003
(2865) nzcv = ..1.
(2866) 10001376: 4b7d ldr r3, [pc, #500]
(2866) Read Flash [1000156c] = 4000b030
(2867) r3 = 4000b030
(2868) 10001378: 601a str r2, [r3, #0]
(2868) Write CLK_REF_CTRL:clr = 00000003
(2870) 1000137a: 4a7a ldr r2, [pc, #488]
(2870) Read Flash [10001564] = 40008000
(2871) r2 = 40008000
(2872) 1000137c: 6b93 ldr r3, [r2, #56]
(2872) Read CLK_REF_SELECTED = 00000001
(2873) r3 = 00000001
(2874) 1000137e: 2b01 cmp r3, #1
(2874) nzcv = .11.
(2875) 10001380: d1fc bne 0x1000137c
(2876) 10001382: 3301 add r3, #1
(2876) r3 = 00000002
(2876) nzcv = ....
(2877) 10001384: 2101 movs r1, #1
(2877) r1 = 00000001
(2878) 10001386: 4a7a ldr r2, [pc, #488]
(2878) Read Flash [10001570] = 59682f00
(2879) r2 = 59682f00
(2880) 10001388: 487a ldr r0, [pc, #488]
(2880) Read Flash [10001574] = 40028000
(2881) r0 = 40028000
(2882) 1000138a: 9300 str r3, [sp, #0]
(2882) Write SRAM [20041ee0] = 00000002
(2884) 1000138c: 3304 add r3, #4
(2884) r3 = 00000006
(2886) 1000138e: f000f92d bl 0x100015ec
(2886) lr = 10001392
(2887) 100015ec: b5f8 push {r3, r4, r5, r6, r7, lr}
(2887) Write SRAM [20041edc] = 10001392
(2888) Write SRAM [20041ed8] = 00000000
(2889) Write SRAM [20041ed4] = 00000003
(2890) Write SRAM [20041ed0] = 2000023c
(2891) Write SRAM [20041ecc] = 40008000
(2892) Write SRAM [20041ec8] = 00000006
(2893) msp = 20041ec8
(2894) 100015ee: 0004 movs r4, r0
(2894) r4 = 40028000
(2895) 100015f0: 200c movs r0, #12
(2895) r0 = 0000000c
(2896) 100015f2: 0017 movs r7, r2
(2896) r7 = 59682f00
(2897) 100015f4: 001d movs r5, r3
(2897) r5 = 00000006
(2898) 100015f6: 000e movs r6, r1
(2898) r6 = 00000001
(2900) 100015f8: f000f8c2 bl 0x10001780
(2900) lr = 100015fc
(2901) 10001780: 4a11 ldr r2, [pc, #68]
(2901) Read Flash [100017c8] = d0000000
(2902) r2 = d0000000
(2903) 10001782: 6f93 ldr r3, [r2, #120]
(2903) Read DIV_CSR = 00000001
(2904) r3 = 00000001
(2905) 10001784: 089b lsrs r3, r3, #2
(2905) r3 = 00000000
(2905) nzcv = .1..
(2906) 10001786: d213 bcs 0x100017b0
(2907) 10001788: 6610 str r0, [r2, #96]
(2907) Write DIV_UDIVIDEND = 0000000c
(2909) 1000178a: 6651 str r1, [r2, #100]
(2909) Write DIV_UDIVISOR = 00000001
(2911) 1000178c: 2900 cmp r1, #0
(2911) nzcv = ..1.
(2912) 1000178e: d005 beq 0x1000179c
(2913) 10001790: e7ff b 0x10001792
(2914) 10001792: e7ff b 0x10001794
(2915) 10001794: e7ff b 0x10001796
(2916) 10001796: 6f51 ldr r1, [r2, #116]
(2916) Read DIV_REMAINDER = 00000000
(2917) r1 = 00000000
(2918) 10001798: 6f10 ldr r0, [r2, #112]
(2918) Read DIV_QUOTIENT = 0000000c
(2919) r0 = 0000000c
(2920) 1000179a: 4770 bx lr
(2921) 100015fc: 0143 lsls r3, r0, #5
(2921) r3 = 00000180
(2921) nzcv = ....
(2922) 100015fe: 1a1b sub r3, r3, r0
(2922) r3 = 00000174
(2922) nzcv = ..1.
(2923) 10001600: 0199 lsls r1, r3, #6
(2923) r1 = 00005d00
(2923) nzcv = ....
(2924) 10001602: 1ac9 sub r1, r1, r3
(2924) r1 = 00005b8c
(2924) nzcv = ..1.
(2925) 10001604: 00c9 lsls r1, r1, #3
(2925) r1 = 0002dc60
(2925) nzcv = ....
(2926) 10001606: 1809 add r1, r1, r0
(2926) r1 = 0002dc6c
(2927) 10001608: 0189 lsls r1, r1, #6
(2927) r1 = 00b71b00
(2928) 1000160a: 0038 movs r0, r7
(2928) r0 = 59682f00
(2930) 1000160c: f000f8b8 bl 0x10001780
(2930) lr = 10001610
(2931) 10001780: 4a11 ldr r2, [pc, #68]
(2931) Read Flash [100017c8] = d0000000
(2932) r2 = d0000000
(2933) 10001782: 6f93 ldr r3, [r2, #120]
(2933) Read DIV_CSR = 00000001
(2934) r3 = 00000001
(2935) 10001784: 089b lsrs r3, r3, #2
(2935) r3 = 00000000
(2935) nzcv = .1..
(2936) 10001786: d213 bcs 0x100017b0
(2937) 10001788: 6610 str r0, [r2, #96]
(2937) Write DIV_UDIVIDEND = 59682f00
(2939) 1000178a: 6651 str r1, [r2, #100]
(2939) Write DIV_UDIVISOR = 00b71b00
(2941) 1000178c: 2900 cmp r1, #0
(2941) nzcv = ..1.
(2942) 1000178e: d005 beq 0x1000179c
(2943) 10001790: e7ff b 0x10001792
(2944) 10001792: e7ff b 0x10001794
(2945) 10001794: e7ff b 0x10001796
(2946) 10001796: 6f51 ldr r1, [r2, #116]
(2946) Read DIV_REMAINDER = 00000000
(2947) r1 = 00000000
(2948) 10001798: 6f10 ldr r0, [r2, #112]
(2948) Read DIV_QUOTIENT = 0000007d
(2949) r0 = 0000007d
(2950) 1000179a: 4770 bx lr
(2951) 10001610: 9b06 ldr r3, [sp, #24]
(2951) Read SRAM [20041ee0] = 00000002
(2952) r3 = 00000002
(2953) 10001612: 0429 lsls r1, r5, #16
(2953) r1 = 00060000
(2953) nzcv = ....
(2954) 10001614: 031b lsls r3, r3, #12
(2954) r3 = 00002000
(2955) 10001616: 4319 orrs r1, r3
(2955) r1 = 00062000
(2956) 10001618: 6823 ldr r3, [r4, #0]
(2956) Read PLL_SYS_CS = 80000000
(2957) r3 = 80000000
(2958) 1000161a: 2b00 cmp r3, #0
(2958) nzcv = 1.1.
(2959) 1000161c: db20 blt 0x10001660
(2960) 10001660: 233f movs r3, #63
(2960) r3 = 0000003f
(2960) nzcv = ..1.
(2961) 10001662: 6822 ldr r2, [r4, #0]
(2961) Read PLL_SYS_CS = 80000000
(2962) r2 = 80000000
(2963) 10001664: 4013 ands r3, r2
(2963) r3 = 00000000
(2963) nzcv = .11.
(2964) 10001666: 42b3 cmp r3, r6
(2964) nzcv = 1...
(2965) 10001668: d1d9 bne 0x1000161e
(2966) 1000161e: 4b19 ldr r3, [pc, #100]
(2966) Read Flash [10001684] = bffd4000
(2967) r3 = bffd4000
(2968) 10001620: 4d19 ldr r5, [pc, #100]
(2968) Read Flash [10001688] = 4000c000
(2969) r5 = 4000c000
(2970) 10001622: 18e3 add r3, r4, r3
(2970) r3 = ffffc000
(2971) 10001624: 425a neg r2, r3
(2971) r2 = 00004000
(2971) nzcv = ....
(2972) 10001626: 4153 adc r3, r2
(2972) r3 = 00000000
(2972) nzcv = .11.
(2973) 10001628: 2280 movs r2, #128
(2973) r2 = 00000080
(2973) nzcv = ..1.
(2974) 1000162a: 0152 lsls r2, r2, #5
(2974) r2 = 00001000
(2974) nzcv = ....
(2975) 1000162c: 4694 mov ip, r2
(2975) ip = 00001000
(2976) 1000162e: 031b lsls r3, r3, #12
(2976) r3 = 00000000
(2976) nzcv = .1..
(2977) 10001630: 4a16 ldr r2, [pc, #88]
(2977) Read Flash [1000168c] = 4000e000
(2978) r2 = 4000e000
(2979) 10001632: 4463 add r3, ip
(2979) r3 = 00001000
(2980) 10001634: 6013 str r3, [r2, #0]
(2980) Write RESET:set = 00001000
(2982) 10001636: 4a16 ldr r2, [pc, #88]
(2982) Read Flash [10001690] = 4000f000
(2983) r2 = 4000f000
(2984) 10001638: 6013 str r3, [r2, #0]
(2984) Write RESET:clr = 00001000
(2986) 1000163a: 001f movs r7, r3
(2986) r7 = 00001000
(2986) nzcv = ....
(2987) 1000163c: 68aa ldr r2, [r5, #8]
(2987) Read RESET_DONE = 003c7ffe
(2988) r2 = 003c7ffe
(2989) 1000163e: 4397 bics r7, r2
(2989) r7 = 00000000
(2989) nzcv = .1..
(2990) 10001640: d1fb bne 0x1000163a
(2991) 10001642: 23c0 movs r3, #192
(2991) r3 = 000000c0
(2991) nzcv = ....
(2992) 10001644: 1d22 add r2, r4, #4
(2992) r2 = 40028004
(2993) 10001646: 019b lsls r3, r3, #6
(2993) r3 = 00003000
(2994) 10001648: 4313 orrs r3, r2
(2994) r3 = 4002b004
(2995) 1000164a: 2221 movs r2, #33
(2995) r2 = 00000021
(2996) 1000164c: 6026 str r6, [r4, #0]
(2996) Write PLL_SYS_CS = 00000001
(2998) 1000164e: 60a0 str r0, [r4, #8]
(2998) Write PLL_SYS_FBDIV_INT = 0000007d
(3000) 10001650: 601a str r2, [r3, #0]
(3000) Write PLL_SYS_PWR:clr = 00000021
(3002) 10001652: 6822 ldr r2, [r4, #0]
(3002) Read PLL_SYS_CS = 80000000
(3003) r2 = 80000000
(3004) 10001654: 2a00 cmp r2, #0
(3004) nzcv = 1.1.
(3005) 10001656: dafc bge 0x10001652
(3006) 10001658: 2208 movs r2, #8
(3006) r2 = 00000008
(3006) nzcv = ..1.
(3007) 1000165a: 60e1 str r1, [r4, #12]
(3007) Write PLL_SYS_PRIM = 00062000
(3009) 1000165c: 601a str r2, [r3, #0]
(3009) Write PLL_SYS_PWR:clr = 00000008
(3011) 1000165e: bdf8 pop {r3, r4, r5, r6, r7, pc}
(3011) Read SRAM [20041ec8] = 00000006
(3012) r3 = 00000006
(3012) Read SRAM [20041ecc] = 40008000
(3013) r4 = 40008000
(3013) Read SRAM [20041ed0] = 2000023c
(3014) r5 = 2000023c
(3014) Read SRAM [20041ed4] = 00000003
(3015) r6 = 00000003
(3015) Read SRAM [20041ed8] = 00000000
(3016) r7 = 00000000
(3016) Read SRAM [20041edc] = 10001392
(3017) msp = 20041ee0
(3018) 10001392: 2305 movs r3, #5
(3018) r3 = 00000005
(3019) 10001394: 4a78 ldr r2, [pc, #480]
(3019) Read Flash [10001578] = 47868c00
(3020) r2 = 47868c00
(3021) 10001396: 9300 str r3, [sp, #0]
(3021) Write SRAM [20041ee0] = 00000005
(3023) 10001398: 2101 movs r1, #1
(3023) r1 = 00000001
(3024) 1000139a: 4878 ldr r0, [pc, #480]
(3024) Read Flash [1000157c] = 4002c000
(3025) r0 = 4002c000
(3027) 1000139c: f000f926 bl 0x100015ec
(3027) lr = 100013a0
(3028) 100015ec: b5f8 push {r3, r4, r5, r6, r7, lr}
(3028) Write SRAM [20041edc] = 100013a0
(3029) Write SRAM [20041ed8] = 00000000
(3030) Write SRAM [20041ed4] = 00000003
(3031) Write SRAM [20041ed0] = 2000023c
(3032) Write SRAM [20041ecc] = 40008000
(3033) Write SRAM [20041ec8] = 00000005
(3034) msp = 20041ec8
(3035) 100015ee: 0004 movs r4, r0
(3035) r4 = 4002c000
(3036) 100015f0: 200c movs r0, #12
(3036) r0 = 0000000c
(3037) 100015f2: 0017 movs r7, r2
(3037) r7 = 47868c00
(3038) 100015f4: 001d movs r5, r3
(3038) r5 = 00000005
(3039) 100015f6: 000e movs r6, r1
(3039) r6 = 00000001
(3041) 100015f8: f000f8c2 bl 0x10001780
(3041) lr = 100015fc
(3042) 10001780: 4a11 ldr r2, [pc, #68]
(3042) Read Flash [100017c8] = d0000000
(3043) r2 = d0000000
(3044) 10001782: 6f93 ldr r3, [r2, #120]
(3044) Read DIV_CSR = 00000001
(3045) r3 = 00000001
(3046) 10001784: 089b lsrs r3, r3, #2
(3046) r3 = 00000000
(3046) nzcv = .1..
(3047) 10001786: d213 bcs 0x100017b0
(3048) 10001788: 6610 str r0, [r2, #96]
(3048) Write DIV_UDIVIDEND = 0000000c
(3050) 1000178a: 6651 str r1, [r2, #100]
(3050) Write DIV_UDIVISOR = 00000001
(3052) 1000178c: 2900 cmp r1, #0
(3052) nzcv = ..1.
(3053) 1000178e: d005 beq 0x1000179c
(3054) 10001790: e7ff b 0x10001792
(3055) 10001792: e7ff b 0x10001794
(3056) 10001794: e7ff b 0x10001796
(3057) 10001796: 6f51 ldr r1, [r2, #116]
(3057) Read DIV_REMAINDER = 00000000
(3058) r1 = 00000000
(3059) 10001798: 6f10 ldr r0, [r2, #112]
(3059) Read DIV_QUOTIENT = 0000000c
(3060) r0 = 0000000c
(3061) 1000179a: 4770 bx lr
(3062) 100015fc: 0143 lsls r3, r0, #5
(3062) r3 = 00000180
(3062) nzcv = ....
(3063) 100015fe: 1a1b sub r3, r3, r0
(3063) r3 = 00000174
(3063) nzcv = ..1.
(3064) 10001600: 0199 lsls r1, r3, #6
(3064) r1 = 00005d00
(3064) nzcv = ....
(3065) 10001602: 1ac9 sub r1, r1, r3
(3065) r1 = 00005b8c
(3065) nzcv = ..1.
(3066) 10001604: 00c9 lsls r1, r1, #3
(3066) r1 = 0002dc60
(3066) nzcv = ....
(3067) 10001606: 1809 add r1, r1, r0
(3067) r1 = 0002dc6c
(3068) 10001608: 0189 lsls r1, r1, #6
(3068) r1 = 00b71b00
(3069) 1000160a: 0038 movs r0, r7
(3069) r0 = 47868c00
(3071) 1000160c: f000f8b8 bl 0x10001780
(3071) lr = 10001610
(3072) 10001780: 4a11 ldr r2, [pc, #68]
(3072) Read Flash [100017c8] = d0000000
(3073) r2 = d0000000
(3074) 10001782: 6f93 ldr r3, [r2, #120]
(3074) Read DIV_CSR = 00000001
(3075) r3 = 00000001
(3076) 10001784: 089b lsrs r3, r3, #2
(3076) r3 = 00000000
(3076) nzcv = .1..
(3077) 10001786: d213 bcs 0x100017b0
(3078) 10001788: 6610 str r0, [r2, #96]
(3078) Write DIV_UDIVIDEND = 47868c00
(3080) 1000178a: 6651 str r1, [r2, #100]
(3080) Write DIV_UDIVISOR = 00b71b00
(3082) 1000178c: 2900 cmp r1, #0
(3082) nzcv = ..1.
(3083) 1000178e: d005 beq 0x1000179c
(3084) 10001790: e7ff b 0x10001792
(3085) 10001792: e7ff b 0x10001794
(3086) 10001794: e7ff b 0x10001796
(3087) 10001796: 6f51 ldr r1, [r2, #116]
(3087) Read DIV_REMAINDER = 00000000
(3088) r1 = 00000000
(3089) 10001798: 6f10 ldr r0, [r2, #112]
(3089) Read DIV_QUOTIENT = 00000064
(3090) r0 = 00000064
(3091) 1000179a: 4770 bx lr
(3092) 10001610: 9b06 ldr r3, [sp, #24]
(3092) Read SRAM [20041ee0] = 00000005
(3093) r3 = 00000005
(3094) 10001612: 0429 lsls r1, r5, #16
(3094) r1 = 00050000
(3094) nzcv = ....
(3095) 10001614: 031b lsls r3, r3, #12
(3095) r3 = 00005000
(3096) 10001616: 4319 orrs r1, r3
(3096) r1 = 00055000
(3097) 10001618: 6823 ldr r3, [r4, #0]
(3097) Read PLL_USB_CS = 80000000
(3098) r3 = 80000000
(3099) 1000161a: 2b00 cmp r3, #0
(3099) nzcv = 1.1.
(3100) 1000161c: db20 blt 0x10001660
(3101) 10001660: 233f movs r3, #63
(3101) r3 = 0000003f
(3101) nzcv = ..1.
(3102) 10001662: 6822 ldr r2, [r4, #0]
(3102) Read PLL_USB_CS = 80000000
(3103) r2 = 80000000
(3104) 10001664: 4013 ands r3, r2
(3104) r3 = 00000000
(3104) nzcv = .11.
(3105) 10001666: 42b3 cmp r3, r6
(3105) nzcv = 1...
(3106) 10001668: d1d9 bne 0x1000161e
(3107) 1000161e: 4b19 ldr r3, [pc, #100]
(3107) Read Flash [10001684] = bffd4000
(3108) r3 = bffd4000
(3109) 10001620: 4d19 ldr r5, [pc, #100]
(3109) Read Flash [10001688] = 4000c000
(3110) r5 = 4000c000
(3111) 10001622: 18e3 add r3, r4, r3
(3111) r3 = 00000000
(3111) nzcv = .11.
(3112) 10001624: 425a neg r2, r3
(3112) r2 = 00000000
(3113) 10001626: 4153 adc r3, r2
(3113) r3 = 00000001
(3113) nzcv = ....
(3114) 10001628: 2280 movs r2, #128
(3114) r2 = 00000080
(3115) 1000162a: 0152 lsls r2, r2, #5
(3115) r2 = 00001000
(3116) 1000162c: 4694 mov ip, r2
(3116) ip = 00001000
(3117) 1000162e: 031b lsls r3, r3, #12
(3117) r3 = 00001000
(3118) 10001630: 4a16 ldr r2, [pc, #88]
(3118) Read Flash [1000168c] = 4000e000
(3119) r2 = 4000e000
(3120) 10001632: 4463 add r3, ip
(3120) r3 = 00002000
(3121) 10001634: 6013 str r3, [r2, #0]
(3121) Write RESET:set = 00002000
(3123) 10001636: 4a16 ldr r2, [pc, #88]
(3123) Read Flash [10001690] = 4000f000
(3124) r2 = 4000f000
(3125) 10001638: 6013 str r3, [r2, #0]
(3125) Write RESET:clr = 00002000
(3127) 1000163a: 001f movs r7, r3
(3127) r7 = 00002000
(3128) 1000163c: 68aa ldr r2, [r5, #8]
(3128) Read RESET_DONE = 003c7ffe
(3129) r2 = 003c7ffe
(3130) 1000163e: 4397 bics r7, r2
(3130) r7 = 00000000
(3130) nzcv = .1..
(3131) 10001640: d1fb bne 0x1000163a
(3132) 10001642: 23c0 movs r3, #192
(3132) r3 = 000000c0
(3132) nzcv = ....
(3133) 10001644: 1d22 add r2, r4, #4
(3133) r2 = 4002c004
(3134) 10001646: 019b lsls r3, r3, #6
(3134) r3 = 00003000
(3135) 10001648: 4313 orrs r3, r2
(3135) r3 = 4002f004
(3136) 1000164a: 2221 movs r2, #33
(3136) r2 = 00000021
(3137) 1000164c: 6026 str r6, [r4, #0]
(3137) Write PLL_USB_CS = 00000001
(3139) 1000164e: 60a0 str r0, [r4, #8]
(3139) Write PLL_USB_FBDIV_INT = 00000064
(3141) 10001650: 601a str r2, [r3, #0]
(3141) Write PLL_USB_PWR:clr = 00000021
(3143) 10001652: 6822 ldr r2, [r4, #0]
(3143) Read PLL_USB_CS = 80000000
(3144) r2 = 80000000
(3145) 10001654: 2a00 cmp r2, #0
(3145) nzcv = 1.1.
(3146) 10001656: dafc bge 0x10001652
(3147) 10001658: 2208 movs r2, #8
(3147) r2 = 00000008
(3147) nzcv = ..1.
(3148) 1000165a: 60e1 str r1, [r4, #12]
(3148) Write PLL_USB_PRIM = 00055000
(3150) 1000165c: 601a str r2, [r3, #0]
(3150) Write PLL_USB_PWR:clr = 00000008
(3152) 1000165e: bdf8 pop {r3, r4, r5, r6, r7, pc}
(3152) Read SRAM [20041ec8] = 00000005
(3153) r3 = 00000005
(3153) Read SRAM [20041ecc] = 40008000
(3154) r4 = 40008000
(3154) Read SRAM [20041ed0] = 2000023c
(3155) r5 = 2000023c
(3155) Read SRAM [20041ed4] = 00000003
(3156) r6 = 00000003
(3156) Read SRAM [20041ed8] = 00000000
(3157) r7 = 00000000
(3157) Read SRAM [20041edc] = 100013a0
(3158) msp = 20041ee0
(3159) 100013a0: 4b77 ldr r3, [pc, #476]
(3159) Read Flash [10001580] = 40008030
(3160) r3 = 40008030
(3161) 100013a2: 685a ldr r2, [r3, #4]
(3161) Read CLK_REF_DIV = 00000000
(3162) r2 = 00000000
(3163) 100013a4: 2aff cmp r2, #255
(3163) nzcv = 1...
(3164) 100013a6: d802 bhi 0x100013ae
(3165) 100013a8: 2280 movs r2, #128
(3165) r2 = 00000080
(3165) nzcv = ....
(3166) 100013aa: 0052 lsls r2, r2, #1
(3166) r2 = 00000100
(3167) 100013ac: 605a str r2, [r3, #4]
(3167) Write CLK_REF_DIV = 00000100
(3169) 100013ae: 2280 movs r2, #128
(3169) r2 = 00000080
(3170) 100013b0: 4b6e ldr r3, [pc, #440]
(3170) Read Flash [1000156c] = 4000b030
(3171) r3 = 4000b030
(3172) 100013b2: 4c69 ldr r4, [pc, #420]
(3172) Read Flash [10001558] = 20000240
(3173) r4 = 20000240
(3174) 100013b4: 0112 lsls r2, r2, #4
(3174) r2 = 00000800
(3175) 100013b6: 601a str r2, [r3, #0]
(3175) Write CLK_REF_CTRL:clr = 00000800
(3177) 100013b8: 6921 ldr r1, [r4, #16]
(3177) Read SRAM [20000250] = 00000000
(3178) r1 = 00000000
(3179) 100013ba: 2900 cmp r1, #0
(3179) nzcv = .11.
(3180) 100013bc: d005 beq 0x100013ca
(3181) 100013ca: 22e0 movs r2, #224
(3181) r2 = 000000e0
(3181) nzcv = ..1.
(3182) 100013cc: 4b6c ldr r3, [pc, #432]
(3182) Read Flash [10001580] = 40008030
(3183) r3 = 40008030
(3184) 100013ce: 486d ldr r0, [pc, #436]
(3184) Read Flash [10001584] = 40009030
(3185) r0 = 40009030
(3186) 100013d0: 6819 ldr r1, [r3, #0]
(3186) Read CLK_REF_CTRL = 00000000
(3187) r1 = 00000000
(3188) 100013d2: 400a ands r2, r1
(3188) r2 = 00000000
(3188) nzcv = .11.
(3189) 100013d4: 6002 str r2, [r0, #0]
(3189) Write CLK_REF_CTRL:xor = 00000000
(3191) 100013d6: 2202 movs r2, #2
(3191) r2 = 00000002
(3191) nzcv = ..1.
(3192) 100013d8: 6819 ldr r1, [r3, #0]
(3192) Read CLK_REF_CTRL = 00000000
(3193) r1 = 00000000
(3194) 100013da: 4051 eors r1, r2
(3194) r1 = 00000002
(3195) 100013dc: 3201 add r2, #1
(3195) r2 = 00000003
(3195) nzcv = ....
(3196) 100013de: 400a ands r2, r1
(3196) r2 = 00000002
(3197) 100013e0: 2104 movs r1, #4
(3197) r1 = 00000004
(3198) 100013e2: 6002 str r2, [r0, #0]
(3198) Write CLK_REF_CTRL:xor = 00000002
(3200) 100013e4: 689a ldr r2, [r3, #8]
(3200) Read CLK_REF_SELECTED = 00000004
(3201) r2 = 00000004
(3202) 100013e6: 4211 tst r1, r2
(3203) 100013e8: d0fc beq 0x100013e4
(3204) 100013ea: 2180 movs r1, #128
(3204) r1 = 00000080
(3205) 100013ec: 4a66 ldr r2, [pc, #408]
(3205) Read Flash [10001588] = 4000a030
(3206) r2 = 4000a030
(3207) 100013ee: 0109 lsls r1, r1, #4
(3207) r1 = 00000800
(3208) 100013f0: 6011 str r1, [r2, #0]
(3208) Write CLK_REF_CTRL:set = 00000800
(3210) 100013f2: 2280 movs r2, #128
(3210) r2 = 00000080
(3211) 100013f4: 0052 lsls r2, r2, #1
(3211) r2 = 00000100
(3212) 100013f6: 605a str r2, [r3, #4]
(3212) Write CLK_REF_DIV = 00000100
(3214) 100013f8: 4b64 ldr r3, [pc, #400]
(3214) Read Flash [1000158c] = 00b71b00
(3215) r3 = 00b71b00
(3216) 100013fa: 6123 str r3, [r4, #16]
(3216) Write SRAM [20000250] = 00b71b00
(3218) 100013fc: 4b64 ldr r3, [pc, #400]
(3218) Read Flash [10001590] = 4000803c
(3219) r3 = 4000803c
(3220) 100013fe: 6859 ldr r1, [r3, #4]
(3220) Read CLK_SYS_DIV = 00000000
(3221) r1 = 00000000
(3222) 10001400: 29ff cmp r1, #255
(3222) nzcv = 1...
(3223) 10001402: d800 bhi 0x10001406
(3224) 10001404: 605a str r2, [r3, #4]
(3224) Write CLK_SYS_DIV = 00000100
(3226) 10001406: 2203 movs r2, #3
(3226) r2 = 00000003
(3226) nzcv = ....
(3227) 10001408: 2101 movs r1, #1
(3227) r1 = 00000001
(3228) 1000140a: 4b57 ldr r3, [pc, #348]
(3228) Read Flash [10001568] = 4000b03c
(3229) r3 = 4000b03c
(3230) 1000140c: 601a str r2, [r3, #0]
(3230) Write CLK_SYS_CTRL:clr = 00000003
(3232) 1000140e: 4a60 ldr r2, [pc, #384]
(3232) Read Flash [10001590] = 4000803c
(3233) r2 = 4000803c
(3234) 10001410: 6893 ldr r3, [r2, #8]
(3234) Read CLK_SYS_SELECTED = 00000001
(3235) r3 = 00000001
(3236) 10001412: 4219 tst r1, r3
(3237) 10001414: d0fc beq 0x10001410
(3238) 10001416: 23e0 movs r3, #224
(3238) r3 = 000000e0
(3239) 10001418: 6810 ldr r0, [r2, #0]
(3239) Read CLK_SYS_CTRL = 00000000
(3240) r0 = 00000000
(3241) 1000141a: 4003 ands r3, r0
(3241) r3 = 00000000
(3241) nzcv = .1..
(3242) 1000141c: 485d ldr r0, [pc, #372]
(3242) Read Flash [10001594] = 4000903c
(3243) r0 = 4000903c
(3244) 1000141e: 6003 str r3, [r0, #0]
(3244) Write CLK_SYS_CTRL:xor = 00000000
(3246) 10001420: 6812 ldr r2, [r2, #0]
(3246) Read CLK_SYS_CTRL = 00000000
(3247) r2 = 00000000
(3248) 10001422: 2303 movs r3, #3
(3248) r3 = 00000003
(3248) nzcv = ....
(3249) 10001424: 404a eors r2, r1
(3249) r2 = 00000001
(3250) 10001426: 2102 movs r1, #2
(3250) r1 = 00000002
(3251) 10001428: 4013 ands r3, r2
(3251) r3 = 00000001
(3252) 1000142a: 4a59 ldr r2, [pc, #356]
(3252) Read Flash [10001590] = 4000803c
(3253) r2 = 4000803c
(3254) 1000142c: 6003 str r3, [r0, #0]
(3254) Write CLK_SYS_CTRL:xor = 00000001
(3256) 1000142e: 6893 ldr r3, [r2, #8]
(3256) Read CLK_SYS_SELECTED = 00000002
(3257) r3 = 00000002
(3258) 10001430: 4219 tst r1, r3
(3259) 10001432: d0fc beq 0x1000142e
(3260) 10001434: 2180 movs r1, #128
(3260) r1 = 00000080
(3261) 10001436: 4b58 ldr r3, [pc, #352]
(3261) Read Flash [10001598] = 4000a03c
(3262) r3 = 4000a03c
(3263) 10001438: 0109 lsls r1, r1, #4
(3263) r1 = 00000800
(3264) 1000143a: 6019 str r1, [r3, #0]
(3264) Write CLK_SYS_CTRL:set = 00000800
(3266) 1000143c: 2180 movs r1, #128
(3266) r1 = 00000080
(3267) 1000143e: 4b57 ldr r3, [pc, #348]
(3267) Read Flash [1000159c] = 07735940
(3268) r3 = 07735940
(3269) 10001440: 0049 lsls r1, r1, #1
(3269) r1 = 00000100
(3270) 10001442: 6051 str r1, [r2, #4]
(3270) Write CLK_SYS_DIV = 00000100
(3272) 10001444: 6163 str r3, [r4, #20]
(3272) Write SRAM [20000254] = 07735940
(3274) 10001446: 4b56 ldr r3, [pc, #344]
(3274) Read Flash [100015a0] = 40008054
(3275) r3 = 40008054
(3276) 10001448: 685a ldr r2, [r3, #4]
(3276) Read CLK_USB_DIV = 00000000
(3277) r2 = 00000000
(3278) 1000144a: 2aff cmp r2, #255
(3278) nzcv = 1...
(3279) 1000144c: d800 bhi 0x10001450
(3280) 1000144e: 6059 str r1, [r3, #4]
(3280) Write CLK_USB_DIV = 00000100
(3282) 10001450: 2280 movs r2, #128
(3282) r2 = 00000080
(3282) nzcv = ....
(3283) 10001452: 4b54 ldr r3, [pc, #336]
(3283) Read Flash [100015a4] = 4000b054
(3284) r3 = 4000b054
(3285) 10001454: 0112 lsls r2, r2, #4
(3285) r2 = 00000800
(3286) 10001456: 601a str r2, [r3, #0]
(3286) Write CLK_USB_CTRL:clr = 00000800
(3288) 10001458: 69e1 ldr r1, [r4, #28]
(3288) Read SRAM [2000025c] = 00000000
(3289) r1 = 00000000
(3290) 1000145a: 2900 cmp r1, #0
(3290) nzcv = .11.
(3291) 1000145c: d005 beq 0x1000146a
(3292) 1000146a: 23e0 movs r3, #224
(3292) r3 = 000000e0
(3292) nzcv = ..1.
(3293) 1000146c: 4a4c ldr r2, [pc, #304]
(3293) Read Flash [100015a0] = 40008054
(3294) r2 = 40008054
(3295) 1000146e: 6811 ldr r1, [r2, #0]
(3295) Read CLK_USB_CTRL = 00000000
(3296) r1 = 00000000
(3297) 10001470: 400b ands r3, r1
(3297) r3 = 00000000
(3297) nzcv = .11.
(3298) 10001472: 494d ldr r1, [pc, #308]
(3298) Read Flash [100015a8] = 40009054
(3299) r1 = 40009054
(3300) 10001474: 600b str r3, [r1, #0]
(3300) Write CLK_USB_CTRL:xor = 00000000
(3302) 10001476: 2180 movs r1, #128
(3302) r1 = 00000080
(3302) nzcv = ..1.
(3303) 10001478: 4b4c ldr r3, [pc, #304]
(3303) Read Flash [100015ac] = 4000a054
(3304) r3 = 4000a054
(3305) 1000147a: 0109 lsls r1, r1, #4
(3305) r1 = 00000800
(3305) nzcv = ....
(3306) 1000147c: 6019 str r1, [r3, #0]
(3306) Write CLK_USB_CTRL:set = 00000800
(3308) 1000147e: 2180 movs r1, #128
(3308) r1 = 00000080
(3309) 10001480: 4b36 ldr r3, [pc, #216]
(3309) Read Flash [1000155c] = 02dc6c00
(3310) r3 = 02dc6c00
(3311) 10001482: 0049 lsls r1, r1, #1
(3311) r1 = 00000100
(3312) 10001484: 6051 str r1, [r2, #4]
(3312) Write CLK_USB_DIV = 00000100
(3314) 10001486: 61e3 str r3, [r4, #28]
(3314) Write SRAM [2000025c] = 02dc6c00
(3316) 10001488: 4b49 ldr r3, [pc, #292]
(3316) Read Flash [100015b0] = 40008060
(3317) r3 = 40008060
(3318) 1000148a: 685a ldr r2, [r3, #4]
(3318) Read CLK_ADC_DIV = 00000000
(3319) r2 = 00000000
(3320) 1000148c: 2aff cmp r2, #255
(3320) nzcv = 1...
(3321) 1000148e: d800 bhi 0x10001492
(3322) 10001490: 6059 str r1, [r3, #4]
(3322) Write CLK_ADC_DIV = 00000100
(3324) 10001492: 2280 movs r2, #128
(3324) r2 = 00000080
(3324) nzcv = ....
(3325) 10001494: 4b47 ldr r3, [pc, #284]
(3325) Read Flash [100015b4] = 4000b060
(3326) r3 = 4000b060
(3327) 10001496: 0112 lsls r2, r2, #4
(3327) r2 = 00000800
(3328) 10001498: 601a str r2, [r3, #0]
(3328) Write CLK_ADC_CTRL:clr = 00000800
(3330) 1000149a: 6a21 ldr r1, [r4, #32]
(3330) Read SRAM [20000260] = 00000000
(3331) r1 = 00000000
(3332) 1000149c: 2900 cmp r1, #0
(3332) nzcv = .11.
(3333) 1000149e: d005 beq 0x100014ac
(3334) 100014ac: 23e0 movs r3, #224
(3334) r3 = 000000e0
(3334) nzcv = ..1.
(3335) 100014ae: 4a40 ldr r2, [pc, #256]
(3335) Read Flash [100015b0] = 40008060
(3336) r2 = 40008060
(3337) 100014b0: 6811 ldr r1, [r2, #0]
(3337) Read CLK_ADC_CTRL = 00000000
(3338) r1 = 00000000
(3339) 100014b2: 400b ands r3, r1
(3339) r3 = 00000000
(3339) nzcv = .11.
(3340) 100014b4: 4940 ldr r1, [pc, #256]
(3340) Read Flash [100015b8] = 40009060
(3341) r1 = 40009060
(3342) 100014b6: 600b str r3, [r1, #0]
(3342) Write CLK_ADC_CTRL:xor = 00000000
(3344) 100014b8: 2180 movs r1, #128
(3344) r1 = 00000080
(3344) nzcv = ..1.
(3345) 100014ba: 4b40 ldr r3, [pc, #256]
(3345) Read Flash [100015bc] = 4000a060
(3346) r3 = 4000a060
(3347) 100014bc: 0109 lsls r1, r1, #4
(3347) r1 = 00000800
(3347) nzcv = ....
(3348) 100014be: 6019 str r1, [r3, #0]
(3348) Write CLK_ADC_CTRL:set = 00000800
(3350) 100014c0: 2380 movs r3, #128
(3350) r3 = 00000080
(3351) 100014c2: 005b lsls r3, r3, #1
(3351) r3 = 00000100
(3352) 100014c4: 6053 str r3, [r2, #4]
(3352) Write CLK_ADC_DIV = 00000100
(3354) 100014c6: 2280 movs r2, #128
(3354) r2 = 00000080
(3355) 100014c8: 4b24 ldr r3, [pc, #144]
(3355) Read Flash [1000155c] = 02dc6c00
(3356) r3 = 02dc6c00
(3357) 100014ca: 02d2 lsls r2, r2, #11
(3357) r2 = 00040000
(3358) 100014cc: 6223 str r3, [r4, #32]
(3358) Write SRAM [20000260] = 02dc6c00
(3360) 100014ce: 4b3c ldr r3, [pc, #240]
(3360) Read Flash [100015c0] = 4000806c
(3361) r3 = 4000806c
(3362) 100014d0: 6859 ldr r1, [r3, #4]
(3362) Read CLK_RTC_DIV = 00000000
(3363) r1 = 00000000
(3364) 100014d2: 4291 cmp r1, r2
(3364) nzcv = 1...
(3365) 100014d4: d200 bcs 0x100014d8
(3366) 100014d6: 605a str r2, [r3, #4]
(3366) Write CLK_RTC_DIV = 00040000
(3368) 100014d8: 2280 movs r2, #128
(3368) r2 = 00000080
(3368) nzcv = ....
(3369) 100014da: 4b3a ldr r3, [pc, #232]
(3369) Read Flash [100015c4] = 4000b06c
(3370) r3 = 4000b06c
(3371) 100014dc: 0112 lsls r2, r2, #4
(3371) r2 = 00000800
(3372) 100014de: 601a str r2, [r3, #0]
(3372) Write CLK_RTC_CTRL:clr = 00000800
(3374) 100014e0: 6a61 ldr r1, [r4, #36]
(3374) Read SRAM [20000264] = 00000000
(3375) r1 = 00000000
(3376) 100014e2: 2900 cmp r1, #0
(3376) nzcv = .11.
(3377) 100014e4: d005 beq 0x100014f2
(3378) 100014f2: 23e0 movs r3, #224
(3378) r3 = 000000e0
(3378) nzcv = ..1.
(3379) 100014f4: 4a32 ldr r2, [pc, #200]
(3379) Read Flash [100015c0] = 4000806c
(3380) r2 = 4000806c
(3381) 100014f6: 6811 ldr r1, [r2, #0]
(3381) Read CLK_RTC_CTRL = 00000000
(3382) r1 = 00000000
(3383) 100014f8: 400b ands r3, r1
(3383) r3 = 00000000
(3383) nzcv = .11.
(3384) 100014fa: 4933 ldr r1, [pc, #204]
(3384) Read Flash [100015c8] = 4000906c
(3385) r1 = 4000906c
(3386) 100014fc: 600b str r3, [r1, #0]
(3386) Write CLK_RTC_CTRL:xor = 00000000
(3388) 100014fe: 2180 movs r1, #128
(3388) r1 = 00000080
(3388) nzcv = ..1.
(3389) 10001500: 4b32 ldr r3, [pc, #200]
(3389) Read Flash [100015cc] = 4000a06c
(3390) r3 = 4000a06c
(3391) 10001502: 0109 lsls r1, r1, #4
(3391) r1 = 00000800
(3391) nzcv = ....
(3392) 10001504: 6019 str r1, [r3, #0]
(3392) Write CLK_RTC_CTRL:set = 00000800
(3394) 10001506: 2380 movs r3, #128
(3394) r3 = 00000080
(3395) 10001508: 02db lsls r3, r3, #11
(3395) r3 = 00040000
(3396) 1000150a: 6053 str r3, [r2, #4]
(3396) Write CLK_RTC_DIV = 00040000
(3398) 1000150c: 4b14 ldr r3, [pc, #80]
(3398) Read Flash [10001560] = 0000b71b
(3399) r3 = 0000b71b
(3400) 1000150e: 6263 str r3, [r4, #36]
(3400) Write SRAM [20000264] = 0000b71b
(3402) 10001510: 4b2f ldr r3, [pc, #188]
(3402) Read Flash [100015d0] = 40008048
(3403) r3 = 40008048
(3404) 10001512: 685a ldr r2, [r3, #4]
(3404) Read CLK_PERI_DIV:unimplemented = 00000000
(3405) r2 = 00000000
(3406) 10001514: 2aff cmp r2, #255
(3406) nzcv = 1...
(3407) 10001516: d802 bhi 0x1000151e
(3408) 10001518: 2280 movs r2, #128
(3408) r2 = 00000080
(3408) nzcv = ....
(3409) 1000151a: 0052 lsls r2, r2, #1
(3409) r2 = 00000100
(3410) 1000151c: 605a str r2, [r3, #4]
(3410) Write CLK_PERI_DIV:unimplemented = 00000100
(3412) 1000151e: 2280 movs r2, #128
(3412) r2 = 00000080
(3413) 10001520: 4b2c ldr r3, [pc, #176]
(3413) Read Flash [100015d4] = 4000b048
(3414) r3 = 4000b048
(3415) 10001522: 0112 lsls r2, r2, #4
(3415) r2 = 00000800
(3416) 10001524: 601a str r2, [r3, #0]
(3416) Write CLK_PERI_CTRL:clr = 00000800
(3418) 10001526: 69a1 ldr r1, [r4, #24]
(3418) Read SRAM [20000258] = 00000000
(3419) r1 = 00000000
(3420) 10001528: 2900 cmp r1, #0
(3420) nzcv = .11.
(3421) 1000152a: d005 beq 0x10001538
(3422) 10001538: 23e0 movs r3, #224
(3422) r3 = 000000e0
(3422) nzcv = ..1.
(3423) 1000153a: 4a25 ldr r2, [pc, #148]
(3423) Read Flash [100015d0] = 40008048
(3424) r2 = 40008048
(3425) 1000153c: 6811 ldr r1, [r2, #0]
(3425) Read CLK_PERI_CTRL = 00000000
(3426) r1 = 00000000
(3427) 1000153e: 400b ands r3, r1
(3427) r3 = 00000000
(3427) nzcv = .11.
(3428) 10001540: 4925 ldr r1, [pc, #148]
(3428) Read Flash [100015d8] = 40009048
(3429) r1 = 40009048
(3430) 10001542: 600b str r3, [r1, #0]
(3430) Write CLK_PERI_CTRL:xor = 00000000
(3432) 10001544: 2180 movs r1, #128
(3432) r1 = 00000080
(3432) nzcv = ..1.
(3433) 10001546: 4b25 ldr r3, [pc, #148]
(3433) Read Flash [100015dc] = 4000a048
(3434) r3 = 4000a048
(3435) 10001548: 0109 lsls r1, r1, #4
(3435) r1 = 00000800
(3435) nzcv = ....
(3436) 1000154a: 6019 str r1, [r3, #0]
(3436) Write CLK_PERI_CTRL:set = 00000800
(3438) 1000154c: 2380 movs r3, #128
(3438) r3 = 00000080
(3439) 1000154e: 005b lsls r3, r3, #1
(3439) r3 = 00000100
(3440) 10001550: 6053 str r3, [r2, #4]
(3440) Write CLK_PERI_DIV:unimplemented = 00000100
(3442) 10001552: 4b12 ldr r3, [pc, #72]
(3442) Read Flash [1000159c] = 07735940
(3443) r3 = 07735940
(3444) 10001554: 61a3 str r3, [r4, #24]
(3444) Write SRAM [20000258] = 07735940
(3446) 10001556: e701 b 0x1000135c
(3447) 1000135c: b002 add sp, #8
(3447) msp = 20041ee8
(3448) 1000135e: bd10 pop {r4, pc}
(3448) Read SRAM [20041ee8] = 00000004
(3449) r4 = 00000004
(3449) Read SRAM [20041eec] = 10001236
(3450) msp = 20041ef0
(3451) 10001236: 4a25 ldr r2, [pc, #148]
(3451) Read Flash [100012cc] = 01ffffff
(3452) r2 = 01ffffff
(3453) 10001238: 4b20 ldr r3, [pc, #128]
(3453) Read Flash [100012bc] = 4000f000
(3454) r3 = 4000f000
(3455) 1000123a: 601a str r2, [r3, #0]
(3455) Write RESET:clr = 01ffffff
(3457) 1000123c: 4a20 ldr r2, [pc, #128]
(3457) Read Flash [100012c0] = 4000c000
(3458) r2 = 4000c000
(3459) 1000123e: 6893 ldr r3, [r2, #8]
(3459) Read RESET_DONE = 01ffffff
(3460) r3 = 01ffffff
(3461) 10001240: 43db mvns r3, r3
(3461) r3 = fe000000
(3461) nzcv = 1...
(3462) 10001242: 01db lsls r3, r3, #7
(3462) r3 = 00000000
(3462) nzcv = .11.
(3463) 10001244: 09dd lsrs r5, r3, #7
(3463) r5 = 00000000
(3463) nzcv = .1..
(3464) 10001246: 2b00 cmp r3, #0
(3464) nzcv = .11.
(3465) 10001248: d1f9 bne 0x1000123e
(3466) 1000124a: 2240 movs r2, #64
(3466) r2 = 00000040
(3466) nzcv = ..1.
(3467) 1000124c: 4b20 ldr r3, [pc, #128]
(3467) Read Flash [100012d0] = 4001f000
(3468) r3 = 4001f000
(3469) 1000124e: 4e21 ldr r6, [pc, #132]
(3469) Read Flash [100012d4] = 2000022c
(3470) r6 = 2000022c
(3471) 10001250: 4c21 ldr r4, [pc, #132]
(3471) Read Flash [100012d8] = 20000224
(3472) r4 = 20000224
(3473) 10001252: 679a str r2, [r3, #120]
(3473) Write BANK0_GPIO29:clr = 00000040
(3475) 10001254: 675a str r2, [r3, #116]
(3475) Write BANK0_GPIO28:clr = 00000040
(3477) 10001256: 671a str r2, [r3, #112]
(3477) Write BANK0_GPIO27:clr = 00000040
(3479) 10001258: 66da str r2, [r3, #108]
(3479) Write BANK0_GPIO26:clr = 00000040
(3481) 1000125a: 42b4 cmp r4, r6
(3481) nzcv = 1...
(3482) 1000125c: d208 bcs 0x10001270
(3483) 1000125e: 6823 ldr r3, [r4, #0]
(3483) Read SRAM [20000224] = 00000000
(3484) r3 = 00000000
(3485) 10001260: 0020 movs r0, r4
(3485) r0 = 20000224
(3485) nzcv = ....
(3486) 10001262: 3408 add r4, #8
(3486) r4 = 2000022c
(3487) 10001264: 2b00 cmp r3, #0
(3487) nzcv = .11.
(3488) 10001266: d01f beq 0x100012a8
(3490) 100012a8: f7ffff1e bl 0x100010e8
(3490) lr = 100012ac
(3491) 100010e8: b510 push {r4, lr}
(3491) Write SRAM [20041eec] = 100012ac
(3492) Write SRAM [20041ee8] = 2000022c
(3493) msp = 20041ee8
(3494) 100010ea: 0004 movs r4, r0
(3494) r4 = 20000224
(3494) nzcv = ..1.
(3496) 100010ec: f7fff96a bl 0x100003c4
(3496) lr = 100010f0
(3497) 100003c4: 4a04 ldr r2, [pc, #16]
(3497) Read Flash [100003d8] = 20000174
(3498) r2 = 20000174
(3499) 100003c6: 7810 ldrb r0, [r2, #0]
(3499) Read SRAM [20000174] = 10
(3500) r0 = 00000010
(3501) 100003c8: 1c43 add r3, r0, #1
(3501) r3 = 00000011
(3501) nzcv = ....
(3502) 100003ca: b2db uxtb r3, r3
(3502) r3 = 00000011
(3503) 100003cc: 2b17 cmp r3, #23
(3503) nzcv = 1...
(3504) 100003ce: d900 bls 0x100003d2
(3505) 100003d2: 7013 strb r3, [r2, #0]
(3505) Write SRAM [20000174] = 11
(3507) 100003d4: 4770 bx lr
(3508) 100010f0: 0001 movs r1, r0
(3508) r1 = 00000010
(3508) nzcv = ....
(3509) 100010f2: 0020 movs r0, r4
(3509) r0 = 20000224
(3511) 100010f4: f7fffb08 bl 0x10000708
(3511) lr = 100010f8
(3512) 10000708: 4b02 ldr r3, [pc, #8]
(3512) Read Flash [10000714] = 34000040
(3513) r3 = 34000040
(3514) 1000070a: 469c mov ip, r3
(3514) ip = 34000040
(3515) 1000070c: 4461 add r1, ip
(3515) r1 = 34000050
(3516) 1000070e: 0089 lsls r1, r1, #2
(3516) r1 = d0000140
(3516) nzcv = 1...
(3517) 10000710: 6001 str r1, [r0, #0]
(3517) Write SRAM [20000224] = d0000140
(3519) 10000712: 4770 bx lr
(3520) 100010f8: 23ff movs r3, #255
(3520) r3 = 000000ff
(3520) nzcv = ....
(3521) 100010fa: 7123 strb r3, [r4, #4]
(3521) Write SRAM [20000228] = ff
(3524) 100010fc: f3bf8f5f dmb #15
(3525) 10001100: bd10 pop {r4, pc}
(3525) Read SRAM [20041ee8] = 2000022c
(3526) r4 = 2000022c
(3526) Read SRAM [20041eec] = 100012ac
(3527) msp = 20041ef0
(3528) 100012ac: e7d5 b 0x1000125a
(3529) 1000125a: 42b4 cmp r4, r6
(3529) nzcv = .11.
(3530) 1000125c: d208 bcs 0x10001270
(3531) 10001270: 4c1a ldr r4, [pc, #104]
(3531) Read Flash [100012dc] = 20000000
(3532) r4 = 20000000
(3533) 10001272: 4e1b ldr r6, [pc, #108]
(3533) Read Flash [100012e0] = e000ed00
(3534) r6 = e000ed00
(3535) 10001274: 22c0 movs r2, #192
(3535) r2 = 000000c0
(3535) nzcv = ..1.
(3536) 10001276: 68b1 ldr r1, [r6, #8]
(3536) Read M0PLUS_VTOR = 10000100
(3537) r1 = 10000100
(3538) 10001278: 0020 movs r0, r4
(3538) r0 = 20000000
(3540) 1000127a: f000fb59 bl 0x10001930
(3540) lr = 1000127e
(3541) 10001930: 4b01 ldr r3, [pc, #4]
(3541) Read Flash [10001938] = 20000200
(3542) r3 = 20000200
(3543) 10001932: 685b ldr r3, [r3, #4]
(3543) Read SRAM [20000204] = 0000261d
(3544) r3 = 0000261d
(3545) 10001934: 4718 bx r3
(3546) 0000261c: 4684 mov ip, r0
(3546) ip = 20000000
(3547) 0000261e: 2a08 cmp r2, #8
(3548) 00002620: d32e bcc 0x00002680
(3549) 00002622: 1a43 sub r3, r0, r1
(3549) r3 = 0fffff00
(3550) 00002624: 079b lsls r3, r3, #30
(3550) r3 = 00000000
(3550) nzcv = .1..
(3551) 00002626: d1f2 bne 0x0000260e
(3552) 00002628: b470 push {r4, r5, r6}
(3552) Write SRAM [20041eec] = e000ed00
(3553) Write SRAM [20041ee8] = 00000000
(3554) Write SRAM [20041ee4] = 20000000
(3555) msp = 20041ee4
(3556) 0000262a: 1a09 sub r1, r1, r0
(3556) r1 = f0000100
(3556) nzcv = 1...
(3557) 0000262c: 1c05 movs r5, r0
(3557) r5 = 20000000
(3557) nzcv = ....
(3558) 0000262e: 0843 lsrs r3, r0, #1
(3558) r3 = 10000000
(3559) 00002630: d302 bcc 0x00002638
(3560) 00002638: 0883 lsrs r3, r0, #2
(3560) r3 = 08000000
(3561) 0000263a: d302 bcc 0x00002642
(3562) 00002642: 1809 add r1, r1, r0
(3562) r1 = 10000100
(3562) nzcv = ..1.
(3563) 00002644: 1a2d sub r5, r5, r0
(3563) r5 = 00000000
(3563) nzcv = .11.
(3564) 00002646: 1952 add r2, r2, r5
(3564) r2 = 000000c0
(3564) nzcv = ....
(3565) 00002648: 3a10 sub r2, #16
(3565) r2 = 000000b0
(3565) nzcv = ..1.
(3566) 0000264a: d303 bcc 0x00002654
(3567) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3567) Read Flash [10000100] = 20042000
(3568) r3 = 20042000
(3568) Read Flash [10000104] = 100001f7
(3569) r4 = 100001f7
(3569) Read Flash [10000108] = 100001c3
(3570) r5 = 100001c3
(3570) Read Flash [1000010c] = 100001c5
(3571) r6 = 100001c5
(3571) r1 = 10000110
(3572) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3572) Write SRAM [20000000] = 20042000
(3573) Write SRAM [20000004] = 100001f7
(3574) Write SRAM [20000008] = 100001c3
(3575) Write SRAM [2000000c] = 100001c5
(3576) r0 = 20000010
(3577) 00002650: 3a10 sub r2, #16
(3577) r2 = 000000a0
(3578) 00002652: d2fb bcs 0x0000264c
(3579) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3579) Read Flash [10000110] = 100001c1
(3580) r3 = 100001c1
(3580) Read Flash [10000114] = 100001c1
(3581) r4 = 100001c1
(3581) Read Flash [10000118] = 100001c1
(3582) r5 = 100001c1
(3582) Read Flash [1000011c] = 100001c1
(3583) r6 = 100001c1
(3583) r1 = 10000120
(3584) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3584) Write SRAM [20000010] = 100001c1
(3585) Write SRAM [20000014] = 100001c1
(3586) Write SRAM [20000018] = 100001c1
(3587) Write SRAM [2000001c] = 100001c1
(3588) r0 = 20000020
(3589) 00002650: 3a10 sub r2, #16
(3589) r2 = 00000090
(3590) 00002652: d2fb bcs 0x0000264c
(3591) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3591) Read Flash [10000120] = 100001c1
(3592) r3 = 100001c1
(3592) Read Flash [10000124] = 100001c1
(3593) r4 = 100001c1
(3593) Read Flash [10000128] = 100001c1
(3594) r5 = 100001c1
(3594) Read Flash [1000012c] = 100001c7
(3595) r6 = 100001c7
(3595) r1 = 10000130
(3596) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3596) Write SRAM [20000020] = 100001c1
(3597) Write SRAM [20000024] = 100001c1
(3598) Write SRAM [20000028] = 100001c1
(3599) Write SRAM [2000002c] = 100001c7
(3600) r0 = 20000030
(3601) 00002650: 3a10 sub r2, #16
(3601) r2 = 00000080
(3602) 00002652: d2fb bcs 0x0000264c
(3603) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3603) Read Flash [10000130] = 100001c1
(3604) r3 = 100001c1
(3604) Read Flash [10000134] = 100001c1
(3605) r4 = 100001c1
(3605) Read Flash [10000138] = 100001c9
(3606) r5 = 100001c9
(3606) Read Flash [1000013c] = 100001cb
(3607) r6 = 100001cb
(3607) r1 = 10000140
(3608) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3608) Write SRAM [20000030] = 100001c1
(3609) Write SRAM [20000034] = 100001c1
(3610) Write SRAM [20000038] = 100001c9
(3611) Write SRAM [2000003c] = 100001cb
(3612) r0 = 20000040
(3613) 00002650: 3a10 sub r2, #16
(3613) r2 = 00000070
(3614) 00002652: d2fb bcs 0x0000264c
(3615) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3615) Read Flash [10000140] = 100001cd
(3616) r3 = 100001cd
(3616) Read Flash [10000144] = 100001cd
(3617) r4 = 100001cd
(3617) Read Flash [10000148] = 100001cd
(3618) r5 = 100001cd
(3618) Read Flash [1000014c] = 100001cd
(3619) r6 = 100001cd
(3619) r1 = 10000150
(3620) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3620) Write SRAM [20000040] = 100001cd
(3621) Write SRAM [20000044] = 100001cd
(3622) Write SRAM [20000048] = 100001cd
(3623) Write SRAM [2000004c] = 100001cd
(3624) r0 = 20000050
(3625) 00002650: 3a10 sub r2, #16
(3625) r2 = 00000060
(3626) 00002652: d2fb bcs 0x0000264c
(3627) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3627) Read Flash [10000150] = 100001cd
(3628) r3 = 100001cd
(3628) Read Flash [10000154] = 100001cd
(3629) r4 = 100001cd
(3629) Read Flash [10000158] = 100001cd
(3630) r5 = 100001cd
(3630) Read Flash [1000015c] = 100001cd
(3631) r6 = 100001cd
(3631) r1 = 10000160
(3632) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3632) Write SRAM [20000050] = 100001cd
(3633) Write SRAM [20000054] = 100001cd
(3634) Write SRAM [20000058] = 100001cd
(3635) Write SRAM [2000005c] = 100001cd
(3636) r0 = 20000060
(3637) 00002650: 3a10 sub r2, #16
(3637) r2 = 00000050
(3638) 00002652: d2fb bcs 0x0000264c
(3639) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3639) Read Flash [10000160] = 100001cd
(3640) r3 = 100001cd
(3640) Read Flash [10000164] = 100001cd
(3641) r4 = 100001cd
(3641) Read Flash [10000168] = 100001cd
(3642) r5 = 100001cd
(3642) Read Flash [1000016c] = 100001cd
(3643) r6 = 100001cd
(3643) r1 = 10000170
(3644) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3644) Write SRAM [20000060] = 100001cd
(3645) Write SRAM [20000064] = 100001cd
(3646) Write SRAM [20000068] = 100001cd
(3647) Write SRAM [2000006c] = 100001cd
(3648) r0 = 20000070
(3649) 00002650: 3a10 sub r2, #16
(3649) r2 = 00000040
(3650) 00002652: d2fb bcs 0x0000264c
(3651) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3651) Read Flash [10000170] = 100001cd
(3652) r3 = 100001cd
(3652) Read Flash [10000174] = 100001cd
(3653) r4 = 100001cd
(3653) Read Flash [10000178] = 100001cd
(3654) r5 = 100001cd
(3654) Read Flash [1000017c] = 100001cd
(3655) r6 = 100001cd
(3655) r1 = 10000180
(3656) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3656) Write SRAM [20000070] = 100001cd
(3657) Write SRAM [20000074] = 100001cd
(3658) Write SRAM [20000078] = 100001cd
(3659) Write SRAM [2000007c] = 100001cd
(3660) r0 = 20000080
(3661) 00002650: 3a10 sub r2, #16
(3661) r2 = 00000030
(3662) 00002652: d2fb bcs 0x0000264c
(3663) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3663) Read Flash [10000180] = 100001cd
(3664) r3 = 100001cd
(3664) Read Flash [10000184] = 100001cd
(3665) r4 = 100001cd
(3665) Read Flash [10000188] = 100001cd
(3666) r5 = 100001cd
(3666) Read Flash [1000018c] = 100001cd
(3667) r6 = 100001cd
(3667) r1 = 10000190
(3668) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3668) Write SRAM [20000080] = 100001cd
(3669) Write SRAM [20000084] = 100001cd
(3670) Write SRAM [20000088] = 100001cd
(3671) Write SRAM [2000008c] = 100001cd
(3672) r0 = 20000090
(3673) 00002650: 3a10 sub r2, #16
(3673) r2 = 00000020
(3674) 00002652: d2fb bcs 0x0000264c
(3675) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3675) Read Flash [10000190] = 100001cd
(3676) r3 = 100001cd
(3676) Read Flash [10000194] = 100001cd
(3677) r4 = 100001cd
(3677) Read Flash [10000198] = 100001cd
(3678) r5 = 100001cd
(3678) Read Flash [1000019c] = 100001cd
(3679) r6 = 100001cd
(3679) r1 = 100001a0
(3680) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3680) Write SRAM [20000090] = 100001cd
(3681) Write SRAM [20000094] = 100001cd
(3682) Write SRAM [20000098] = 100001cd
(3683) Write SRAM [2000009c] = 100001cd
(3684) r0 = 200000a0
(3685) 00002650: 3a10 sub r2, #16
(3685) r2 = 00000010
(3686) 00002652: d2fb bcs 0x0000264c
(3687) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3687) Read Flash [100001a0] = 100001cd
(3688) r3 = 100001cd
(3688) Read Flash [100001a4] = 100001cd
(3689) r4 = 100001cd
(3689) Read Flash [100001a8] = 100001cd
(3690) r5 = 100001cd
(3690) Read Flash [100001ac] = 100001cd
(3691) r6 = 100001cd
(3691) r1 = 100001b0
(3692) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3692) Write SRAM [200000a0] = 100001cd
(3693) Write SRAM [200000a4] = 100001cd
(3694) Write SRAM [200000a8] = 100001cd
(3695) Write SRAM [200000ac] = 100001cd
(3696) r0 = 200000b0
(3697) 00002650: 3a10 sub r2, #16
(3697) r2 = 00000000
(3697) nzcv = .11.
(3698) 00002652: d2fb bcs 0x0000264c
(3699) 0000264c: c978 ldmia r1!, {r3, r4, r5, r6}
(3699) Read Flash [100001b0] = 100001cd
(3700) r3 = 100001cd
(3700) Read Flash [100001b4] = 100001cd
(3701) r4 = 100001cd
(3701) Read Flash [100001b8] = 100001cd
(3702) r5 = 100001cd
(3702) Read Flash [100001bc] = 100001cd
(3703) r6 = 100001cd
(3703) r1 = 100001c0
(3704) 0000264e: c078 stmia r0!, {r3, r4, r5, r6}
(3704) Write SRAM [200000b0] = 100001cd
(3705) Write SRAM [200000b4] = 100001cd
(3706) Write SRAM [200000b8] = 100001cd
(3707) Write SRAM [200000bc] = 100001cd
(3708) r0 = 200000c0
(3709) 00002650: 3a10 sub r2, #16
(3709) r2 = fffffff0
(3709) nzcv = 1...
(3710) 00002652: d2fb bcs 0x0000264c
(3711) 00002654: 0752 lsls r2, r2, #29
(3711) r2 = 00000000
(3711) nzcv = .1..
(3712) 00002656: d301 bcc 0x0000265c
(3713) 0000265c: 0052 lsls r2, r2, #1
(3713) r2 = 00000000
(3714) 0000265e: d301 bcc 0x00002664
(3715) 00002664: d009 beq 0x0000267a
(3716) 0000267a: bc70 pop {r4, r5, r6}
(3716) Read SRAM [20041ee4] = 20000000
(3717) r4 = 20000000
(3717) Read SRAM [20041ee8] = 00000000
(3718) r5 = 00000000
(3718) Read SRAM [20041eec] = e000ed00
(3719) r6 = e000ed00
(3719) msp = 20041ef0
(3720) 0000267c: 4660 mov r0, ip
(3720) r0 = 20000000
(3721) 0000267e: 4770 bx lr
(3722) 1000127e: 60b4 str r4, [r6, #8]
(3722) Write M0PLUS_VTOR = 20000000
(3725) 10001280: f7fff892 bl 0x100003a8
(3725) lr = 10001284
(3726) 100003a8: 2100 movs r1, #0
(3726) r1 = 00000000
(3727) 100003aa: 4b04 ldr r3, [pc, #16]
(3727) Read Flash [100003bc] = d0000100
(3728) r3 = d0000100
(3729) 100003ac: 4a04 ldr r2, [pc, #16]
(3729) Read Flash [100003c0] = d0000180
(3730) r2 = d0000180
(3732) 100003ae: f3bf8f5f dmb #15
(3733) 100003b2: c302 stmia r3!, {r1}
(3733) Write SPINLOCK0 = 00000000
(3734) r3 = d0000104
(3735) 100003b4: 4293 cmp r3, r2
(3735) nzcv = 1...
(3736) 100003b6: d1fa bne 0x100003ae
(3738) 100003ae: f3bf8f5f dmb #15
(3739) 100003b2: c302 stmia r3!, {r1}
(3739) Write SPINLOCK1 = 00000000
(3740) r3 = d0000108
(3741) 100003b4: 4293 cmp r3, r2
(3742) 100003b6: d1fa bne 0x100003ae
(3744) 100003ae: f3bf8f5f dmb #15
(3745) 100003b2: c302 stmia r3!, {r1}
(3745) Write SPINLOCK2 = 00000000
(3746) r3 = d000010c
(3747) 100003b4: 4293 cmp r3, r2
(3748) 100003b6: d1fa bne 0x100003ae
(3750) 100003ae: f3bf8f5f dmb #15
(3751) 100003b2: c302 stmia r3!, {r1}
(3751) Write SPINLOCK3 = 00000000
(3752) r3 = d0000110
(3753) 100003b4: 4293 cmp r3, r2
(3754) 100003b6: d1fa bne 0x100003ae
(3756) 100003ae: f3bf8f5f dmb #15
(3757) 100003b2: c302 stmia r3!, {r1}
(3757) Write SPINLOCK4 = 00000000
(3758) r3 = d0000114
(3759) 100003b4: 4293 cmp r3, r2
(3760) 100003b6: d1fa bne 0x100003ae
(3762) 100003ae: f3bf8f5f dmb #15
(3763) 100003b2: c302 stmia r3!, {r1}
(3763) Write SPINLOCK5 = 00000000
(3764) r3 = d0000118
(3765) 100003b4: 4293 cmp r3, r2
(3766) 100003b6: d1fa bne 0x100003ae
(3768) 100003ae: f3bf8f5f dmb #15
(3769) 100003b2: c302 stmia r3!, {r1}
(3769) Write SPINLOCK6 = 00000000
(3770) r3 = d000011c
(3771) 100003b4: 4293 cmp r3, r2
(3772) 100003b6: d1fa bne 0x100003ae
(3774) 100003ae: f3bf8f5f dmb #15
(3775) 100003b2: c302 stmia r3!, {r1}
(3775) Write SPINLOCK7 = 00000000
(3776) r3 = d0000120
(3777) 100003b4: 4293 cmp r3, r2
(3778) 100003b6: d1fa bne 0x100003ae
(3780) 100003ae: f3bf8f5f dmb #15
(3781) 100003b2: c302 stmia r3!, {r1}
(3781) Write SPINLOCK8 = 00000000
(3782) r3 = d0000124
(3783) 100003b4: 4293 cmp r3, r2
(3784) 100003b6: d1fa bne 0x100003ae
(3786) 100003ae: f3bf8f5f dmb #15
(3787) 100003b2: c302 stmia r3!, {r1}
(3787) Write SPINLOCK9 = 00000000
(3788) r3 = d0000128
(3789) 100003b4: 4293 cmp r3, r2
(3790) 100003b6: d1fa bne 0x100003ae
(3792) 100003ae: f3bf8f5f dmb #15
(3793) 100003b2: c302 stmia r3!, {r1}
(3793) Write SPINLOCK10 = 00000000
(3794) r3 = d000012c
(3795) 100003b4: 4293 cmp r3, r2
(3796) 100003b6: d1fa bne 0x100003ae
(3798) 100003ae: f3bf8f5f dmb #15
(3799) 100003b2: c302 stmia r3!, {r1}
(3799) Write SPINLOCK11 = 00000000
(3800) r3 = d0000130
(3801) 100003b4: 4293 cmp r3, r2
(3802) 100003b6: d1fa bne 0x100003ae
(3804) 100003ae: f3bf8f5f dmb #15
(3805) 100003b2: c302 stmia r3!, {r1}
(3805) Write SPINLOCK12 = 00000000
(3806) r3 = d0000134
(3807) 100003b4: 4293 cmp r3, r2
(3808) 100003b6: d1fa bne 0x100003ae
(3810) 100003ae: f3bf8f5f dmb #15
(3811) 100003b2: c302 stmia r3!, {r1}
(3811) Write SPINLOCK13 = 00000000
(3812) r3 = d0000138
(3813) 100003b4: 4293 cmp r3, r2
(3814) 100003b6: d1fa bne 0x100003ae
(3816) 100003ae: f3bf8f5f dmb #15
(3817) 100003b2: c302 stmia r3!, {r1}
(3817) Write SPINLOCK14 = 00000000
(3818) r3 = d000013c
(3819) 100003b4: 4293 cmp r3, r2
(3820) 100003b6: d1fa bne 0x100003ae
(3822) 100003ae: f3bf8f5f dmb #15
(3823) 100003b2: c302 stmia r3!, {r1}
(3823) Write SPINLOCK15 = 00000000
(3824) r3 = d0000140
(3825) 100003b4: 4293 cmp r3, r2
(3826) 100003b6: d1fa bne 0x100003ae
(3828) 100003ae: f3bf8f5f dmb #15
(3829) 100003b2: c302 stmia r3!, {r1}
(3829) Write SPINLOCK16 = 00000000
(3830) r3 = d0000144
(3831) 100003b4: 4293 cmp r3, r2
(3832) 100003b6: d1fa bne 0x100003ae
(3834) 100003ae: f3bf8f5f dmb #15
(3835) 100003b2: c302 stmia r3!, {r1}
(3835) Write SPINLOCK17 = 00000000
(3836) r3 = d0000148
(3837) 100003b4: 4293 cmp r3, r2
(3838) 100003b6: d1fa bne 0x100003ae
(3840) 100003ae: f3bf8f5f dmb #15
(3841) 100003b2: c302 stmia r3!, {r1}
(3841) Write SPINLOCK18 = 00000000
(3842) r3 = d000014c
(3843) 100003b4: 4293 cmp r3, r2
(3844) 100003b6: d1fa bne 0x100003ae
(3846) 100003ae: f3bf8f5f dmb #15
(3847) 100003b2: c302 stmia r3!, {r1}
(3847) Write SPINLOCK19 = 00000000
(3848) r3 = d0000150
(3849) 100003b4: 4293 cmp r3, r2
(3850) 100003b6: d1fa bne 0x100003ae
(3852) 100003ae: f3bf8f5f dmb #15
(3853) 100003b2: c302 stmia r3!, {r1}
(3853) Write SPINLOCK20 = 00000000
(3854) r3 = d0000154
(3855) 100003b4: 4293 cmp r3, r2
(3856) 100003b6: d1fa bne 0x100003ae
(3858) 100003ae: f3bf8f5f dmb #15
(3859) 100003b2: c302 stmia r3!, {r1}
(3859) Write SPINLOCK21 = 00000000
(3860) r3 = d0000158
(3861) 100003b4: 4293 cmp r3, r2
(3862) 100003b6: d1fa bne 0x100003ae
(3864) 100003ae: f3bf8f5f dmb #15
(3865) 100003b2: c302 stmia r3!, {r1}
(3865) Write SPINLOCK22 = 00000000
(3866) r3 = d000015c
(3867) 100003b4: 4293 cmp r3, r2
(3868) 100003b6: d1fa bne 0x100003ae
(3870) 100003ae: f3bf8f5f dmb #15
(3871) 100003b2: c302 stmia r3!, {r1}
(3871) Write SPINLOCK23 = 00000000
(3872) r3 = d0000160
(3873) 100003b4: 4293 cmp r3, r2
(3874) 100003b6: d1fa bne 0x100003ae
(3876) 100003ae: f3bf8f5f dmb #15
(3877) 100003b2: c302 stmia r3!, {r1}
(3877) Write SPINLOCK24 = 00000000
(3878) r3 = d0000164
(3879) 100003b4: 4293 cmp r3, r2
(3880) 100003b6: d1fa bne 0x100003ae
(3882) 100003ae: f3bf8f5f dmb #15
(3883) 100003b2: c302 stmia r3!, {r1}
(3883) Write SPINLOCK25 = 00000000
(3884) r3 = d0000168
(3885) 100003b4: 4293 cmp r3, r2
(3886) 100003b6: d1fa bne 0x100003ae
(3888) 100003ae: f3bf8f5f dmb #15
(3889) 100003b2: c302 stmia r3!, {r1}
(3889) Write SPINLOCK26 = 00000000
(3890) r3 = d000016c
(3891) 100003b4: 4293 cmp r3, r2
(3892) 100003b6: d1fa bne 0x100003ae
(3894) 100003ae: f3bf8f5f dmb #15
(3895) 100003b2: c302 stmia r3!, {r1}
(3895) Write SPINLOCK27 = 00000000
(3896) r3 = d0000170
(3897) 100003b4: 4293 cmp r3, r2
(3898) 100003b6: d1fa bne 0x100003ae
(3900) 100003ae: f3bf8f5f dmb #15
(3901) 100003b2: c302 stmia r3!, {r1}
(3901) Write SPINLOCK28 = 00000000
(3902) r3 = d0000174
(3903) 100003b4: 4293 cmp r3, r2
(3904) 100003b6: d1fa bne 0x100003ae
(3906) 100003ae: f3bf8f5f dmb #15
(3907) 100003b2: c302 stmia r3!, {r1}
(3907) Write SPINLOCK29 = 00000000
(3908) r3 = d0000178
(3909) 100003b4: 4293 cmp r3, r2
(3910) 100003b6: d1fa bne 0x100003ae
(3912) 100003ae: f3bf8f5f dmb #15
(3913) 100003b2: c302 stmia r3!, {r1}
(3913) Write SPINLOCK30 = 00000000
(3914) r3 = d000017c
(3915) 100003b4: 4293 cmp r3, r2
(3916) 100003b6: d1fa bne 0x100003ae
(3918) 100003ae: f3bf8f5f dmb #15
(3919) 100003b2: c302 stmia r3!, {r1}
(3919) Write SPINLOCK31 = 00000000
(3920) r3 = d0000180
(3921) 100003b4: 4293 cmp r3, r2
(3921) nzcv = .11.
(3922) 100003b6: d1fa bne 0x100003ae
(3923) 100003b8: 4770 bx lr
(3925) 10001284: f7fffa2e bl 0x100006e4
(3925) lr = 10001288
(3926) 100006e4: 4b05 ldr r3, [pc, #20]
(3926) Read Flash [100006fc] = 80808080
(3927) r3 = 80808080
(3928) 100006e6: 4a06 ldr r2, [pc, #24]
(3928) Read Flash [10000700] = e000e400
(3929) r2 = e000e400
(3930) 100006e8: 6013 str r3, [r2, #0]
(3930) Write M0PLUS_NVIC_IPR0 = 80808080
(3932) 100006ea: 4a06 ldr r2, [pc, #24]
(3932) Read Flash [10000704] = e000e404
(3933) r2 = e000e404
(3934) 100006ec: 6013 str r3, [r2, #0]
(3934) Write M0PLUS_NVIC_IPR1 = 80808080
(3936) 100006ee: 6053 str r3, [r2, #4]
(3936) Write M0PLUS_NVIC_IPR2 = 80808080
(3938) 100006f0: 6093 str r3, [r2, #8]
(3938) Write M0PLUS_NVIC_IPR3 = 80808080
(3940) 100006f2: 60d3 str r3, [r2, #12]
(3940) Write M0PLUS_NVIC_IPR4 = 80808080
(3942) 100006f4: 6113 str r3, [r2, #16]
(3942) Write M0PLUS_NVIC_IPR5 = 80808080
(3944) 100006f6: 6153 str r3, [r2, #20]
(3944) Write M0PLUS_NVIC_IPR6 = 80808080
(3946) 100006f8: 6193 str r3, [r2, #24]
(3946) Write M0PLUS_NVIC_IPR7 = 80808080
(3948) 100006fa: 4770 bx lr
(3950) 10001288: f7fffbbe bl 0x10000a08
(3950) lr = 1000128c
(3951) 10000a08: b510 push {r4, lr}
(3951) Write SRAM [20041eec] = 1000128c
(3952) Write SRAM [20041ee8] = 20000000
(3953) msp = 20041ee8
(3954) 10000a0a: 4c12 ldr r4, [pc, #72]
(3954) Read Flash [10000a54] = 200001c0
(3955) r4 = 200001c0
(3956) 10000a0c: 6863 ldr r3, [r4, #4]
(3956) Read SRAM [200001c4] = 00000000
(3957) r3 = 00000000
(3958) 10000a0e: 2b00 cmp r3, #0
(3959) 10000a10: d004 beq 0x10000a1c
(3960) 10000a1c: 0023 movs r3, r4
(3960) r3 = 200001c0
(3960) nzcv = ..1.
(3961) 10000a1e: 4a0f ldr r2, [pc, #60]
(3961) Read Flash [10000a5c] = 10000719
(3962) r2 = 10000719
(3963) 10000a20: 2110 movs r1, #16
(3963) r1 = 00000010
(3964) 10000a22: 6820 ldr r0, [r4, #0]
(3964) Read SRAM [200001c0] = 200001d8
(3965) r0 = 200001d8
(3967) 10000a24: f000f992 bl 0x10000d4c
(3967) lr = 10000a28
(3968) 10000d4c: b510 push {r4, lr}
(3968) Write SRAM [20041ee4] = 10000a28
(3969) Write SRAM [20041ee0] = 200001c0
(3970) msp = 20041ee0
(3971) 10000d4e: 6083 str r3, [r0, #8]
(3971) Write SRAM [200001e0] = 200001c0
(3973) 10000d50: 2300 movs r3, #0
(3973) r3 = 00000000
(3973) nzcv = .11.
(3974) 10000d52: b2cc uxtb r4, r1
(3974) r4 = 00000010
(3975) 10000d54: 7343 strb r3, [r0, #13]
(3975) Write SRAM [200001e5] = 00
(3977) 10000d56: 3301 add r3, #1
(3977) r3 = 00000001
(3977) nzcv = ....
(3978) 10000d58: 6042 str r2, [r0, #4]
(3978) Write SRAM [200001dc] = 10000719
(3980) 10000d5a: 7304 strb r4, [r0, #12]
(3980) Write SRAM [200001e4] = 10
(3982) 10000d5c: 7383 strb r3, [r0, #14]
(3982) Write SRAM [200001e6] = 01
(3984) 10000d5e: 73c4 strb r4, [r0, #15]
(3984) Write SRAM [200001e7] = 10
(3986) 10000d60: 6800 ldr r0, [r0, #0]
(3986) Read SRAM [200001d8] = 20000588
(3987) r0 = 20000588
(3988) 10000d62: 1c42 add r2, r0, #1
(3988) r2 = 20000589
(3989) 10000d64: 2c01 cmp r4, #1
(3989) nzcv = ..1.
(3990) 10000d66: d905 bls 0x10000d74
(3991) 10000d68: 3301 add r3, #1
(3991) r3 = 00000002
(3991) nzcv = ....
(3992) 10000d6a: b2db uxtb r3, r3
(3992) r3 = 00000002
(3993) 10000d6c: 7013 strb r3, [r2, #0]
(3993) Write SRAM [20000589] = 02
(3995) 10000d6e: 3203 add r2, #3
(3995) r2 = 2000058c
(3996) 10000d70: 429c cmp r4, r3
(3996) nzcv = ..1.
(3997) 10000d72: d1f9 bne 0x10000d68
(3998) 10000d68: 3301 add r3, #1
(3998) r3 = 00000003
(3998) nzcv = ....
(3999) 10000d6a: b2db uxtb r3, r3
(3999) r3 = 00000003
(4000) 10000d6c: 7013 strb r3, [r2, #0]
(4000) Write SRAM [2000058c] = 03
(4002) 10000d6e: 3203 add r2, #3
(4002) r2 = 2000058f
(4003) 10000d70: 429c cmp r4, r3
(4003) nzcv = ..1.
(4004) 10000d72: d1f9 bne 0x10000d68
(4005) 10000d68: 3301 add r3, #1
(4005) r3 = 00000004
(4005) nzcv = ....
(4006) 10000d6a: b2db uxtb r3, r3
(4006) r3 = 00000004
(4007) 10000d6c: 7013 strb r3, [r2, #0]
(4007) Write SRAM [2000058f] = 04
(4009) 10000d6e: 3203 add r2, #3
(4009) r2 = 20000592
(4010) 10000d70: 429c cmp r4, r3
(4010) nzcv = ..1.
(4011) 10000d72: d1f9 bne 0x10000d68
(4012) 10000d68: 3301 add r3, #1
(4012) r3 = 00000005
(4012) nzcv = ....
(4013) 10000d6a: b2db uxtb r3, r3
(4013) r3 = 00000005
(4014) 10000d6c: 7013 strb r3, [r2, #0]
(4014) Write SRAM [20000592] = 05
(4016) 10000d6e: 3203 add r2, #3
(4016) r2 = 20000595
(4017) 10000d70: 429c cmp r4, r3
(4017) nzcv = ..1.
(4018) 10000d72: d1f9 bne 0x10000d68
(4019) 10000d68: 3301 add r3, #1
(4019) r3 = 00000006
(4019) nzcv = ....
(4020) 10000d6a: b2db uxtb r3, r3
(4020) r3 = 00000006
(4021) 10000d6c: 7013 strb r3, [r2, #0]
(4021) Write SRAM [20000595] = 06
(4023) 10000d6e: 3203 add r2, #3
(4023) r2 = 20000598
(4024) 10000d70: 429c cmp r4, r3
(4024) nzcv = ..1.
(4025) 10000d72: d1f9 bne 0x10000d68
(4026) 10000d68: 3301 add r3, #1
(4026) r3 = 00000007
(4026) nzcv = ....
(4027) 10000d6a: b2db uxtb r3, r3
(4027) r3 = 00000007
(4028) 10000d6c: 7013 strb r3, [r2, #0]
(4028) Write SRAM [20000598] = 07
(4030) 10000d6e: 3203 add r2, #3
(4030) r2 = 2000059b
(4031) 10000d70: 429c cmp r4, r3
(4031) nzcv = ..1.
(4032) 10000d72: d1f9 bne 0x10000d68
(4033) 10000d68: 3301 add r3, #1
(4033) r3 = 00000008
(4033) nzcv = ....
(4034) 10000d6a: b2db uxtb r3, r3
(4034) r3 = 00000008
(4035) 10000d6c: 7013 strb r3, [r2, #0]
(4035) Write SRAM [2000059b] = 08
(4037) 10000d6e: 3203 add r2, #3
(4037) r2 = 2000059e
(4038) 10000d70: 429c cmp r4, r3
(4038) nzcv = ..1.
(4039) 10000d72: d1f9 bne 0x10000d68
(4040) 10000d68: 3301 add r3, #1
(4040) r3 = 00000009
(4040) nzcv = ....
(4041) 10000d6a: b2db uxtb r3, r3
(4041) r3 = 00000009
(4042) 10000d6c: 7013 strb r3, [r2, #0]
(4042) Write SRAM [2000059e] = 09
(4044) 10000d6e: 3203 add r2, #3
(4044) r2 = 200005a1
(4045) 10000d70: 429c cmp r4, r3
(4045) nzcv = ..1.
(4046) 10000d72: d1f9 bne 0x10000d68
(4047) 10000d68: 3301 add r3, #1
(4047) r3 = 0000000a
(4047) nzcv = ....
(4048) 10000d6a: b2db uxtb r3, r3
(4048) r3 = 0000000a
(4049) 10000d6c: 7013 strb r3, [r2, #0]
(4049) Write SRAM [200005a1] = 0a
(4051) 10000d6e: 3203 add r2, #3
(4051) r2 = 200005a4
(4052) 10000d70: 429c cmp r4, r3
(4052) nzcv = ..1.
(4053) 10000d72: d1f9 bne 0x10000d68
(4054) 10000d68: 3301 add r3, #1
(4054) r3 = 0000000b
(4054) nzcv = ....
(4055) 10000d6a: b2db uxtb r3, r3
(4055) r3 = 0000000b
(4056) 10000d6c: 7013 strb r3, [r2, #0]
(4056) Write SRAM [200005a4] = 0b
(4058) 10000d6e: 3203 add r2, #3
(4058) r2 = 200005a7
(4059) 10000d70: 429c cmp r4, r3
(4059) nzcv = ..1.
(4060) 10000d72: d1f9 bne 0x10000d68
(4061) 10000d68: 3301 add r3, #1
(4061) r3 = 0000000c
(4061) nzcv = ....
(4062) 10000d6a: b2db uxtb r3, r3
(4062) r3 = 0000000c
(4063) 10000d6c: 7013 strb r3, [r2, #0]
(4063) Write SRAM [200005a7] = 0c
(4065) 10000d6e: 3203 add r2, #3
(4065) r2 = 200005aa
(4066) 10000d70: 429c cmp r4, r3
(4066) nzcv = ..1.
(4067) 10000d72: d1f9 bne 0x10000d68
(4068) 10000d68: 3301 add r3, #1
(4068) r3 = 0000000d
(4068) nzcv = ....
(4069) 10000d6a: b2db uxtb r3, r3
(4069) r3 = 0000000d
(4070) 10000d6c: 7013 strb r3, [r2, #0]
(4070) Write SRAM [200005aa] = 0d
(4072) 10000d6e: 3203 add r2, #3
(4072) r2 = 200005ad
(4073) 10000d70: 429c cmp r4, r3
(4073) nzcv = ..1.
(4074) 10000d72: d1f9 bne 0x10000d68
(4075) 10000d68: 3301 add r3, #1
(4075) r3 = 0000000e
(4075) nzcv = ....
(4076) 10000d6a: b2db uxtb r3, r3
(4076) r3 = 0000000e
(4077) 10000d6c: 7013 strb r3, [r2, #0]
(4077) Write SRAM [200005ad] = 0e
(4079) 10000d6e: 3203 add r2, #3
(4079) r2 = 200005b0
(4080) 10000d70: 429c cmp r4, r3
(4080) nzcv = ..1.
(4081) 10000d72: d1f9 bne 0x10000d68
(4082) 10000d68: 3301 add r3, #1
(4082) r3 = 0000000f
(4082) nzcv = ....
(4083) 10000d6a: b2db uxtb r3, r3
(4083) r3 = 0000000f
(4084) 10000d6c: 7013 strb r3, [r2, #0]
(4084) Write SRAM [200005b0] = 0f
(4086) 10000d6e: 3203 add r2, #3
(4086) r2 = 200005b3
(4087) 10000d70: 429c cmp r4, r3
(4087) nzcv = ..1.
(4088) 10000d72: d1f9 bne 0x10000d68
(4089) 10000d68: 3301 add r3, #1
(4089) r3 = 00000010
(4089) nzcv = ....
(4090) 10000d6a: b2db uxtb r3, r3
(4090) r3 = 00000010
(4091) 10000d6c: 7013 strb r3, [r2, #0]
(4091) Write SRAM [200005b3] = 10
(4093) 10000d6e: 3203 add r2, #3
(4093) r2 = 200005b6
(4094) 10000d70: 429c cmp r4, r3
(4094) nzcv = .11.
(4095) 10000d72: d1f9 bne 0x10000d68
(4096) 10000d74: 23ff movs r3, #255
(4096) r3 = 000000ff
(4096) nzcv = ..1.
(4097) 10000d76: 400b ands r3, r1
(4097) r3 = 00000010
(4098) 10000d78: 005a lsls r2, r3, #1
(4098) r2 = 00000020
(4098) nzcv = ....
(4099) 10000d7a: 18d3 add r3, r2, r3
(4099) r3 = 00000030
(4100) 10000d7c: 18c0 add r0, r0, r3
(4100) r0 = 200005b8
(4101) 10000d7e: 2300 movs r3, #0
(4101) r3 = 00000000
(4101) nzcv = .1..
(4102) 10000d80: 3803 sub r0, #3
(4102) r0 = 200005b5
(4102) nzcv = ..1.
(4103) 10000d82: 7043 strb r3, [r0, #1]
(4103) Write SRAM [200005b6] = 00
(4105) 10000d84: bd10 pop {r4, pc}
(4105) Read SRAM [20041ee0] = 200001c0
(4106) r4 = 200001c0
(4106) Read SRAM [20041ee4] = 10000a28
(4107) msp = 20041ee8
(4108) 10000a28: 2003 movs r0, #3
(4108) r0 = 00000003
(4110) 10000a2a: f000f87b bl 0x10000b24
(4110) lr = 10000a2e
(4111) 10000b24: b510 push {r4, lr}
(4111) Write SRAM [20041ee4] = 10000a2e
(4112) Write SRAM [20041ee0] = 200001c0
(4113) msp = 20041ee0
(4114) 10000b26: 4b03 ldr r3, [pc, #12]
(4114) Read Flash [10000b34] = 2000060c
(4115) r3 = 2000060c
(4116) 10000b28: 0001 movs r1, r0
(4116) r1 = 00000003
(4117) 10000b2a: 0018 movs r0, r3
(4117) r0 = 2000060c
(4118) 10000b2c: 4a02 ldr r2, [pc, #8]
(4118) Read Flash [10000b38] = 10001d14
(4119) r2 = 10001d14
(4121) 10000b2e: f7fffc11 bl 0x10000354
(4121) lr = 10000b32
(4122) 10000354: b570 push {r4, r5, r6, lr}
(4122) Write SRAM [20041edc] = 10000b32
(4123) Write SRAM [20041ed8] = e000ed00
(4124) Write SRAM [20041ed4] = 00000000
(4125) Write SRAM [20041ed0] = 200001c0
(4126) msp = 20041ed0
(4128) 10000356: f3ef8c10 mrs ip, PRIMASK
(4128) ip = 00000000
(4129) 1000035a: b672 cpsid i
(4129) primask = 00000001
(4130) 1000035c: 4d0d ldr r5, [pc, #52]
(4130) Read Flash [10000394] = d000012c
(4131) r5 = d000012c
(4132) 1000035e: 682b ldr r3, [r5, #0]
(4132) Read SPINLOCK11 = 00000800
(4133) r3 = 00000800
(4134) 10000360: 2b00 cmp r3, #0
(4135) 10000362: d0fc beq 0x1000035e
(4137) 10000364: f3bf8f5f dmb #15
(4138) 10000368: 2407 movs r4, #7
(4138) r4 = 00000007
(4139) 1000036a: 08cb lsrs r3, r1, #3
(4139) r3 = 00000000
(4139) nzcv = .1..
(4140) 1000036c: 18c6 add r6, r0, r3
(4140) r6 = 2000060c
(4140) nzcv = ....
(4141) 1000036e: 5cc0 ldrb r0, [r0, r3]
(4141) Read SRAM [2000060c] = 00
(4142) r0 = 00000000
(4143) 10000370: 2301 movs r3, #1
(4143) r3 = 00000001
(4144) 10000372: 400c ands r4, r1
(4144) r4 = 00000003
(4145) 10000374: 40a3 lsls r3, r4
(4145) r3 = 00000008
(4146) 10000376: 001c movs r4, r3
(4146) r4 = 00000008
(4147) 10000378: 4004 ands r4, r0
(4147) r4 = 00000000
(4147) nzcv = .1..
(4148) 1000037a: 4203 tst r3, r0
(4149) 1000037c: d107 bne 0x1000038e
(4150) 1000037e: 4318 orrs r0, r3
(4150) r0 = 00000008
(4150) nzcv = ....
(4151) 10000380: 7030 strb r0, [r6, #0]
(4151) Write SRAM [2000060c] = 08
(4154) 10000382: f3bf8f5f dmb #15
(4155) 10000386: 602c str r4, [r5, #0]
(4155) Write SPINLOCK11 = 00000000
(4158) 10000388: f38c8810 msr PRIMASK, ip
(4158) primask = 00000000
(4159) 1000038c: bd70 pop {r4, r5, r6, pc}
(4159) Read SRAM [20041ed0] = 200001c0
(4160) r4 = 200001c0
(4160) Read SRAM [20041ed4] = 00000000
(4161) r5 = 00000000
(4161) Read SRAM [20041ed8] = e000ed00
(4162) r6 = e000ed00
(4162) Read SRAM [20041edc] = 10000b32
(4163) msp = 20041ee0
(4164) 10000b32: bd10 pop {r4, pc}
(4164) Read SRAM [20041ee0] = 200001c0
(4165) r4 = 200001c0
(4165) Read SRAM [20041ee4] = 10000a2e
(4166) msp = 20041ee8
(4167) 10000a2e: 2003 movs r0, #3
(4167) r0 = 00000003
(4169) 10000a30: f000f942 bl 0x10000cb8
(4169) lr = 10000a34
(4171) 10000cb8: f3ef8c10 mrs ip, PRIMASK
(4171) ip = 00000000
(4172) 10000cbc: b672 cpsid i
(4172) primask = 00000001
(4173) 10000cbe: 490a ldr r1, [pc, #40]
(4173) Read Flash [10000ce8] = d0000128
(4174) r1 = d0000128
(4175) 10000cc0: 680b ldr r3, [r1, #0]
(4175) Read SPINLOCK10 = 00000400
(4176) r3 = 00000400
(4177) 10000cc2: 2b00 cmp r3, #0
(4177) nzcv = ..1.
(4178) 10000cc4: d0fc beq 0x10000cc0
(4180) 10000cc6: f3bf8f5f dmb #15
(4181) 10000cca: 2301 movs r3, #1
(4181) r3 = 00000001
(4182) 10000ccc: 4083 lsls r3, r0
(4182) r3 = 00000008
(4182) nzcv = ....
(4183) 10000cce: 4a07 ldr r2, [pc, #28]
(4183) Read Flash [10000cec] = 40054000
(4184) r2 = 40054000
(4185) 10000cd0: 4807 ldr r0, [pc, #28]
(4185) Read Flash [10000cf0] = 2000060e
(4186) r0 = 2000060e
(4187) 10000cd2: 6213 str r3, [r2, #32]
(4187) Write TIMER_ARMED = 00000008
(4189) 10000cd4: 7802 ldrb r2, [r0, #0]
(4189) Read SRAM [2000060e] = 00
(4190) r2 = 00000000
(4191) 10000cd6: 439a bics r2, r3
(4191) r2 = 00000000
(4191) nzcv = .1..
(4192) 10000cd8: 7002 strb r2, [r0, #0]
(4192) Write SRAM [2000060e] = 00
(4195) 10000cda: f3bf8f5f dmb #15
(4196) 10000cde: 2300 movs r3, #0
(4196) r3 = 00000000
(4197) 10000ce0: 600b str r3, [r1, #0]
(4197) Write SPINLOCK10 = 00000000
(4200) 10000ce2: f38c8810 msr PRIMASK, ip
(4200) primask = 00000000
(4201) 10000ce6: 4770 bx lr
(4202) 10000a34: 2003 movs r0, #3
(4202) r0 = 00000003
(4202) nzcv = ....
(4203) 10000a36: 490a ldr r1, [pc, #40]
(4203) Read Flash [10000a60] = 10000845
(4204) r1 = 10000845
(4206) 10000a38: f000f88a bl 0x10000b50
(4206) lr = 10000a3c
(4207) 10000b50: b570 push {r4, r5, r6, lr}
(4207) Write SRAM [20041ee4] = 10000a3c
(4208) Write SRAM [20041ee0] = e000ed00
(4209) Write SRAM [20041edc] = 00000000
(4210) Write SRAM [20041ed8] = 200001c0
(4211) msp = 20041ed8
(4212) 10000b52: 0004 movs r4, r0
(4212) r4 = 00000003
(4213) 10000b54: 000d movs r5, r1
(4213) r5 = 10000845
(4215) 10000b56: f3ef8610 mrs r6, PRIMASK
(4215) r6 = 00000000
(4216) 10000b5a: b672 cpsid i
(4216) primask = 00000001
(4217) 10000b5c: 4a1a ldr r2, [pc, #104]
(4217) Read Flash [10000bc8] = d0000128
(4218) r2 = d0000128
(4219) 10000b5e: 6813 ldr r3, [r2, #0]
(4219) Read SPINLOCK10 = 00000400
(4220) r3 = 00000400
(4221) 10000b60: 2b00 cmp r3, #0
(4221) nzcv = ..1.
(4222) 10000b62: d0fc beq 0x10000b5e
(4224) 10000b64: f3bf8f5f dmb #15
(4225) 10000b68: 2d00 cmp r5, #0
(4226) 10000b6a: d01b beq 0x10000ba4
(4227) 10000b6c: 0020 movs r0, r4
(4227) r0 = 00000003
(4229) 10000b6e: f7fffc47 bl 0x10000400
(4229) lr = 10000b72
(4230) 10000400: 4b02 ldr r3, [pc, #8]
(4230) Read Flash [1000040c] = e000ed00
(4231) r3 = e000ed00
(4232) 10000402: 3010 add r0, #16
(4232) r0 = 00000013
(4232) nzcv = ....
(4233) 10000404: 689b ldr r3, [r3, #8]
(4233) Read M0PLUS_VTOR = 20000000
(4234) r3 = 20000000
(4235) 10000406: 0080 lsls r0, r0, #2
(4235) r0 = 0000004c
(4236) 10000408: 58c0 ldr r0, [r0, r3]
(4236) Read SRAM [2000004c] = 100001cd
(4237) r0 = 100001cd
(4238) 1000040a: 4770 bx lr
(4239) 10000b72: 4916 ldr r1, [pc, #88]
(4239) Read Flash [10000bcc] = 10000a6d
(4240) r1 = 10000a6d
(4241) 10000b74: 4281 cmp r1, r0
(4241) nzcv = ..1.
(4242) 10000b76: d00a beq 0x10000b8e
(4243) 10000b78: 0020 movs r0, r4
(4243) r0 = 00000003
(4245) 10000b7a: f7fffc49 bl 0x10000410
(4245) lr = 10000b7e
(4246) 10000410: b570 push {r4, r5, r6, lr}
(4246) Write SRAM [20041ed4] = 10000b7e
(4247) Write SRAM [20041ed0] = 00000000
(4248) Write SRAM [20041ecc] = 10000845
(4249) Write SRAM [20041ec8] = 00000003
(4250) msp = 20041ec8
(4251) 10000412: 000d movs r5, r1
(4251) r5 = 10000a6d
(4253) 10000414: f3ef8610 mrs r6, PRIMASK
(4253) r6 = 00000001
(4254) 10000418: b672 cpsid i
(4254) primask = 00000001
(4255) 1000041a: 4a0f ldr r2, [pc, #60]
(4255) Read Flash [10000458] = d0000124
(4256) r2 = d0000124
(4257) 1000041c: 6813 ldr r3, [r2, #0]
(4257) Read SPINLOCK9 = 00000200
(4258) r3 = 00000200
(4259) 1000041e: 2b00 cmp r3, #0
(4260) 10000420: d0fc beq 0x1000041c
(4262) 10000422: f3bf8f5f dmb #15
(4263) 10000426: 4b0d ldr r3, [pc, #52]
(4263) Read Flash [1000045c] = e000ed00
(4264) r3 = e000ed00
(4265) 10000428: 3010 add r0, #16
(4265) r0 = 00000013
(4265) nzcv = ....
(4266) 1000042a: 689b ldr r3, [r3, #8]
(4266) Read M0PLUS_VTOR = 20000000
(4267) r3 = 20000000
(4268) 1000042c: 0084 lsls r4, r0, #2
(4268) r4 = 0000004c
(4269) 1000042e: 591b ldr r3, [r3, r4]
(4269) Read SRAM [2000004c] = 100001cd
(4270) r3 = 100001cd
(4271) 10000430: 4a0b ldr r2, [pc, #44]
(4271) Read Flash [10000460] = 100001cd
(4272) r2 = 100001cd
(4273) 10000432: 4293 cmp r3, r2
(4273) nzcv = .11.
(4274) 10000434: d003 beq 0x1000043e
(4275) 1000043e: 4b07 ldr r3, [pc, #28]
(4275) Read Flash [1000045c] = e000ed00
(4276) r3 = e000ed00
(4277) 10000440: 689b ldr r3, [r3, #8]
(4277) Read M0PLUS_VTOR = 20000000
(4278) r3 = 20000000
(4279) 10000442: 511d str r5, [r3, r4]
(4279) Write SRAM [2000004c] = 10000a6d
(4282) 10000444: f3bf8f5f dmb #15
(4284) 10000448: f3bf8f5f dmb #15
(4285) 1000044c: 2200 movs r2, #0
(4285) r2 = 00000000
(4286) 1000044e: 4b02 ldr r3, [pc, #8]
(4286) Read Flash [10000458] = d0000124
(4287) r3 = d0000124
(4288) 10000450: 601a str r2, [r3, #0]
(4288) Write SPINLOCK9 = 00000000
(4291) 10000452: f3868810 msr PRIMASK, r6
(4291) primask = 00000001
(4292) 10000456: bd70 pop {r4, r5, r6, pc}
(4292) Read SRAM [20041ec8] = 00000003
(4293) r4 = 00000003
(4293) Read SRAM [20041ecc] = 10000845
(4294) r5 = 10000845
(4294) Read SRAM [20041ed0] = 00000000
(4295) r6 = 00000000
(4295) Read SRAM [20041ed4] = 10000b7e
(4296) msp = 20041ed8
(4297) 10000b7e: 2101 movs r1, #1
(4297) r1 = 00000001
(4297) nzcv = ..1.
(4298) 10000b80: 0020 movs r0, r4
(4298) r0 = 00000003
(4300) 10000b82: f7fffc2b bl 0x100003dc
(4300) lr = 10000b86
(4301) 100003dc: 2301 movs r3, #1
(4301) r3 = 00000001
(4302) 100003de: 4083 lsls r3, r0
(4302) r3 = 00000008
(4302) nzcv = ....
(4303) 100003e0: 2900 cmp r1, #0
(4303) nzcv = ..1.
(4304) 100003e2: d004 beq 0x100003ee
(4305) 100003e4: 4a03 ldr r2, [pc, #12]
(4305) Read Flash [100003f4] = e000e280
(4306) r2 = e000e280
(4307) 100003e6: 6013 str r3, [r2, #0]
(4307) Write M0PLUS_NVIC_ICPR = 00000008
(4309) 100003e8: 4a03 ldr r2, [pc, #12]
(4309) Read Flash [100003f8] = e000e100
(4310) r2 = e000e100
(4311) 100003ea: 6013 str r3, [r2, #0]
(4311) Write M0PLUS_NVIC_ISER = 00000008
(4313) 100003ec: 4770 bx lr
(4314) 10000b86: 2301 movs r3, #1
(4314) r3 = 00000001
(4315) 10000b88: 40a3 lsls r3, r4
(4315) r3 = 00000008
(4315) nzcv = ....
(4316) 10000b8a: 4a11 ldr r2, [pc, #68]
(4316) Read Flash [10000bd0] = 40056038
(4317) r2 = 40056038
(4318) 10000b8c: 6013 str r3, [r2, #0]
(4318) Write TIMER_INTE:set = 00000008
(4320) 10000b8e: 4b11 ldr r3, [pc, #68]
(4320) Read Flash [10000bd4] = 20000568
(4321) r3 = 20000568
(4322) 10000b90: 00a4 lsls r4, r4, #2
(4322) r4 = 0000000c
(4323) 10000b92: 50e5 str r5, [r4, r3]
(4323) Write SRAM [20000574] = 10000845
(4326) 10000b94: f3bf8f5f dmb #15
(4327) 10000b98: 2200 movs r2, #0
(4327) r2 = 00000000
(4327) nzcv = .1..
(4328) 10000b9a: 4b0b ldr r3, [pc, #44]
(4328) Read Flash [10000bc8] = d0000128
(4329) r3 = d0000128
(4330) 10000b9c: 601a str r2, [r3, #0]
(4330) Write SPINLOCK10 = 00000000
(4333) 10000b9e: f3868810 msr PRIMASK, r6
(4333) primask = 00000000
(4334) 10000ba2: bd70 pop {r4, r5, r6, pc}
(4334) Read SRAM [20041ed8] = 200001c0
(4335) r4 = 200001c0
(4335) Read SRAM [20041edc] = 00000000
(4336) r5 = 00000000
(4336) Read SRAM [20041ee0] = e000ed00
(4337) r6 = e000ed00
(4337) Read SRAM [20041ee4] = 10000a3c
(4338) msp = 20041ee8
(4340) 10000a3c: f7fffcc2 bl 0x100003c4
(4340) lr = 10000a40
(4341) 100003c4: 4a04 ldr r2, [pc, #16]
(4341) Read Flash [100003d8] = 20000174
(4342) r2 = 20000174
(4343) 100003c6: 7810 ldrb r0, [r2, #0]
(4343) Read SRAM [20000174] = 11
(4344) r0 = 00000011
(4345) 100003c8: 1c43 add r3, r0, #1
(4345) r3 = 00000012
(4345) nzcv = ....
(4346) 100003ca: b2db uxtb r3, r3
(4346) r3 = 00000012
(4347) 100003cc: 2b17 cmp r3, #23
(4347) nzcv = 1...
(4348) 100003ce: d900 bls 0x100003d2
(4349) 100003d2: 7013 strb r3, [r2, #0]
(4349) Write SRAM [20000174] = 12
(4351) 100003d4: 4770 bx lr
(4352) 10000a40: 4b08 ldr r3, [pc, #32]
(4352) Read Flash [10000a64] = 34000040
(4353) r3 = 34000040
(4354) 10000a42: 469c mov ip, r3
(4354) ip = 34000040
(4355) 10000a44: 2303 movs r3, #3
(4355) r3 = 00000003
(4355) nzcv = ....
(4356) 10000a46: 4460 add r0, ip
(4356) r0 = 34000051
(4357) 10000a48: 7523 strb r3, [r4, #20]
(4357) Write SRAM [200001d4] = 03
(4359) 10000a4a: 4b07 ldr r3, [pc, #28]
(4359) Read Flash [10000a68] = 200005dc
(4360) r3 = 200005dc
(4361) 10000a4c: 0080 lsls r0, r0, #2
(4361) r0 = d0000144
(4361) nzcv = 1...
(4362) 10000a4e: 6060 str r0, [r4, #4]
(4362) Write SRAM [200001c4] = d0000144
(4364) 10000a50: 60dc str r4, [r3, #12]
(4364) Write SRAM [200005e8] = 200001c0
(4366) 10000a52: e7de b 0x10000a12
(4367) 10000a12: 210a movs r1, #10
(4367) r1 = 0000000a
(4367) nzcv = ....
(4368) 10000a14: 4810 ldr r0, [pc, #64]
(4368) Read Flash [10000a58] = 200005f0
(4369) r0 = 200005f0
(4371) 10000a16: f7fffe77 bl 0x10000708
(4371) lr = 10000a1a
(4372) 10000708: 4b02 ldr r3, [pc, #8]
(4372) Read Flash [10000714] = 34000040
(4373) r3 = 34000040
(4374) 1000070a: 469c mov ip, r3
(4374) ip = 34000040
(4375) 1000070c: 4461 add r1, ip
(4375) r1 = 3400004a
(4376) 1000070e: 0089 lsls r1, r1, #2
(4376) r1 = d0000128
(4376) nzcv = 1...
(4377) 10000710: 6001 str r1, [r0, #0]
(4377) Write SRAM [200005f0] = d0000128
(4379) 10000712: 4770 bx lr
(4380) 10000a1a: bd10 pop {r4, pc}
(4380) Read SRAM [20041ee8] = 20000000
(4381) r4 = 20000000
(4381) Read SRAM [20041eec] = 1000128c
(4382) msp = 20041ef0
(4383) 1000128c: 4c15 ldr r4, [pc, #84]
(4383) Read Flash [100012e4] = 2000023c
(4384) r4 = 2000023c
(4385) 1000128e: 4e16 ldr r6, [pc, #88]
(4385) Read Flash [100012e8] = 20000240
(4386) r6 = 20000240
(4387) 10001290: 42b4 cmp r4, r6
(4388) 10001292: d208 bcs 0x100012a6
(4389) 10001294: 3e01 sub r6, #1
(4389) r6 = 2000023f
(4389) nzcv = ..1.
(4390) 10001296: 1b36 sub r6, r6, r4
(4390) r6 = 00000003
(4391) 10001298: 08b6 lsrs r6, r6, #2
(4391) r6 = 00000000
(4391) nzcv = .11.
(4392) 1000129a: cc08 ldmia r4!, {r3}
(4392) Read SRAM [2000023c] = 100002ed
(4393) r3 = 100002ed
(4393) r4 = 20000240
(4394) 1000129c: 4798 blx r3
(4394) lr = 1000129e
(4395) 100002ec: 4b05 ldr r3, [pc, #20]
(4395) Read Flash [10000304] = 00000000
(4396) r3 = 00000000
(4397) 100002ee: b510 push {r4, lr}
(4397) Write SRAM [20041eec] = 1000129e
(4398) Write SRAM [20041ee8] = 20000240
(4399) msp = 20041ee8
(4400) 100002f0: 2b00 cmp r3, #0
(4401) 100002f2: d003 beq 0x100002fc
(4403) 100002fc: f7ffffe2 bl 0x100002c4
(4403) lr = 10000300
(4404) 100002c4: 4806 ldr r0, [pc, #24]
(4404) Read Flash [100002e0] = 20000240
(4405) r0 = 20000240
(4406) 100002c6: 4907 ldr r1, [pc, #28]
(4406) Read Flash [100002e4] = 20000240
(4407) r1 = 20000240
(4408) 100002c8: 1a09 sub r1, r1, r0
(4408) r1 = 00000000
(4409) 100002ca: 108b asrs r3, r1, #2
(4409) r3 = 00000000
(4409) nzcv = .1..
(4410) 100002cc: 0fc9 lsrs r1, r1, #31
(4410) r1 = 00000000
(4411) 100002ce: 18c9 add r1, r1, r3
(4411) r1 = 00000000
(4412) 100002d0: b510 push {r4, lr}
(4412) Write SRAM [20041ee4] = 10000300
(4413) Write SRAM [20041ee0] = 20000240
(4414) msp = 20041ee0
(4415) 100002d2: 1049 asrs r1, r1, #1
(4415) r1 = 00000000
(4416) 100002d4: d003 beq 0x100002de
(4417) 100002de: bd10 pop {r4, pc}
(4417) Read SRAM [20041ee0] = 20000240
(4418) r4 = 20000240
(4418) Read SRAM [20041ee4] = 10000300
(4419) msp = 20041ee8
(4420) 10000300: bd10 pop {r4, pc}
(4420) Read SRAM [20041ee8] = 20000240
(4421) r4 = 20000240
(4421) Read SRAM [20041eec] = 1000129e
(4422) msp = 20041ef0
(4423) 1000129e: 002b movs r3, r5
(4423) r3 = 00000000
(4424) 100012a0: 3501 add r5, #1
(4424) r5 = 00000001
(4424) nzcv = ....
(4425) 100012a2: 429e cmp r6, r3
(4425) nzcv = .11.
(4426) 100012a4: d1f9 bne 0x1000129a
(4427) 100012a6: bd70 pop {r4, r5, r6, pc}
(4427) Read SRAM [20041ef0] = 10000264
(4428) r4 = 10000264
(4428) Read SRAM [20041ef4] = 00000000
(4429) r5 = 00000000
(4429) Read SRAM [20041ef8] = 00000000
(4430) r6 = 00000000
(4430) Read SRAM [20041efc] = 1000021e
(4431) msp = 20041f00
(4432) 1000021e: 4919 ldr r1, [pc, #100]
(4432) Read Flash [10000284] = 10000311
(4433) r1 = 10000311
(4434) 10000220: 4788 blx r1
(4434) lr = 10000222
(4435) 10000310: b510 push {r4, lr}
(4435) Write SRAM [20041efc] = 10000222
(4436) Write SRAM [20041ef8] = 10000264
(4437) msp = 20041ef8
(4439) 10000312: f001fc3b bl 0x10001b8c
(4439) lr = 10000316
(4440) 10001b8c: b510 push {r4, lr}
(4440) Write SRAM [20041ef4] = 10000316
(4441) Write SRAM [20041ef0] = 10000264
(4442) msp = 20041ef0
(4444) 10001b8e: f000f843 bl 0x10001c18
(4444) lr = 10001b92
(4445) 10001c18: 21e1 movs r1, #225
(4445) r1 = 000000e1
(4445) nzcv = ..1.
(4446) 10001c1a: b510 push {r4, lr}
(4446) Write SRAM [20041eec] = 10001b92
(4447) Write SRAM [20041ee8] = 10000264
(4448) msp = 20041ee8
(4449) 10001c1c: 4b0b ldr r3, [pc, #44]
(4449) Read Flash [10001c4c] = 10001e20
(4450) r3 = 10001e20
(4451) 10001c1e: 480c ldr r0, [pc, #48]
(4451) Read Flash [10001c50] = 40034000
(4452) r0 = 40034000
(4453) 10001c20: 781b ldrb r3, [r3, #0]
(4453) Read Flash [10001e20] = ec
(4454) r3 = 000000ec
(4455) 10001c22: 4b0c ldr r3, [pc, #48]
(4455) Read Flash [10001c54] = 10001e1c
(4456) r3 = 10001e1c
(4457) 10001c24: 0249 lsls r1, r1, #9
(4457) r1 = 0001c200
(4457) nzcv = ....
(4458) 10001c26: 781b ldrb r3, [r3, #0]
(4458) Read Flash [10001e1c] = f8
(4459) r3 = 000000f8
(4460) 10001c28: 4b0b ldr r3, [pc, #44]
(4460) Read Flash [10001c58] = 20000608
(4461) r3 = 20000608
(4462) 10001c2a: 6018 str r0, [r3, #0]
(4462) Write SRAM [20000608] = 40034000
(4465) 10001c2c: f7fffa78 bl 0x10001120
(4465) lr = 10001c30
(4466) 10001120: b5f8 push {r3, r4, r5, r6, r7, lr}
(4466) Write SRAM [20041ee4] = 10001c30
(4467) Write SRAM [20041ee0] = 00000000
(4468) Write SRAM [20041edc] = 00000000
(4469) Write SRAM [20041ed8] = 00000000
(4470) Write SRAM [20041ed4] = 10000264
(4471) Write SRAM [20041ed0] = 20000608
(4472) msp = 20041ed0
(4473) 10001122: 0004 movs r4, r0
(4473) r4 = 40034000
(4474) 10001124: 2006 movs r0, #6
(4474) r0 = 00000006
(4475) 10001126: 000d movs r5, r1
(4475) r5 = 0001c200
(4477) 10001128: f000fa5a bl 0x100015e0
(4477) lr = 1000112c
(4478) 100015e0: 4b01 ldr r3, [pc, #4]
(4478) Read Flash [100015e8] = 20000240
(4479) r3 = 20000240
(4480) 100015e2: 0080 lsls r0, r0, #2
(4480) r0 = 00000018
(4481) 100015e4: 58c0 ldr r0, [r0, r3]
(4481) Read SRAM [20000258] = 07735940
(4482) r0 = 07735940
(4483) 100015e6: 4770 bx lr
(4484) 1000112c: 2800 cmp r0, #0
(4484) nzcv = ..1.
(4485) 1000112e: d044 beq 0x100011ba
(4486) 10001130: 4b2a ldr r3, [pc, #168]
(4486) Read Flash [100011dc] = bffc8000
(4487) r3 = bffc8000
(4488) 10001132: 492b ldr r1, [pc, #172]
(4488) Read Flash [100011e0] = 4000c000
(4489) r1 = 4000c000
(4490) 10001134: 18e2 add r2, r4, r3
(4490) r2 = ffffc000
(4490) nzcv = 1...
(4491) 10001136: 4253 neg r3, r2
(4491) r3 = 00004000
(4491) nzcv = ....
(4492) 10001138: 415a adc r2, r3
(4492) r2 = 00000000
(4492) nzcv = .11.
(4493) 1000113a: 2380 movs r3, #128
(4493) r3 = 00000080
(4493) nzcv = ..1.
(4494) 1000113c: 03db lsls r3, r3, #15
(4494) r3 = 00400000
(4494) nzcv = ....
(4495) 1000113e: 469c mov ip, r3
(4495) ip = 00400000
(4496) 10001140: 0592 lsls r2, r2, #22
(4496) r2 = 00000000
(4496) nzcv = .1..
(4497) 10001142: 4b28 ldr r3, [pc, #160]
(4497) Read Flash [100011e4] = 4000e000
(4498) r3 = 4000e000
(4499) 10001144: 4462 add r2, ip
(4499) r2 = 00400000
(4500) 10001146: 601a str r2, [r3, #0]
(4500) Write RESET:set = 00400000
(4502) 10001148: 4b27 ldr r3, [pc, #156]
(4502) Read Flash [100011e8] = 4000f000
(4503) r3 = 4000f000
(4504) 1000114a: 601a str r2, [r3, #0]
(4504) Write RESET:clr = 00400000
(4506) 1000114c: 0010 movs r0, r2
(4506) r0 = 00400000
(4506) nzcv = ....
(4507) 1000114e: 688b ldr r3, [r1, #8]
(4507) Read RESET_DONE = 01ffffff
(4508) r3 = 01ffffff
(4509) 10001150: 4398 bics r0, r3
(4509) r0 = 00000000
(4509) nzcv = .1..
(4510) 10001152: d1fb bne 0x1000114c
(4511) 10001154: 4b21 ldr r3, [pc, #132]
(4511) Read Flash [100011dc] = bffc8000
(4512) r3 = bffc8000
(4513) 10001156: 4a25 ldr r2, [pc, #148]
(4513) Read Flash [100011ec] = 20000604
(4514) r2 = 20000604
(4515) 10001158: 18e3 add r3, r4, r3
(4515) r3 = ffffc000
(4515) nzcv = 1...
(4516) 1000115a: 4259 neg r1, r3
(4516) r1 = 00004000
(4516) nzcv = ....
(4517) 1000115c: 414b adc r3, r1
(4517) r3 = 00000000
(4517) nzcv = .11.
(4518) 1000115e: 2180 movs r1, #128
(4518) r1 = 00000080
(4518) nzcv = ..1.
(4519) 10001160: 005b lsls r3, r3, #1
(4519) r3 = 00000000
(4519) nzcv = .1..
(4520) 10001162: 0049 lsls r1, r1, #1
(4520) r1 = 00000100
(4520) nzcv = ....
(4521) 10001164: 2006 movs r0, #6
(4521) r0 = 00000006
(4522) 10001166: 5299 strh r1, [r3, r2]
(4522) Write SRAM [20000604] = 0100
(4525) 10001168: f000fa3a bl 0x100015e0
(4525) lr = 1000116c
(4526) 100015e0: 4b01 ldr r3, [pc, #4]
(4526) Read Flash [100015e8] = 20000240
(4527) r3 = 20000240
(4528) 100015e2: 0080 lsls r0, r0, #2
(4528) r0 = 00000018
(4529) 100015e4: 58c0 ldr r0, [r0, r3]
(4529) Read SRAM [20000258] = 07735940
(4530) r0 = 07735940
(4531) 100015e6: 4770 bx lr
(4532) 1000116c: 0029 movs r1, r5
(4532) r1 = 0001c200
(4533) 1000116e: 00c0 lsls r0, r0, #3
(4533) r0 = 3b9aca00
(4535) 10001170: f000fb06 bl 0x10001780
(4535) lr = 10001174
(4536) 10001780: 4a11 ldr r2, [pc, #68]
(4536) Read Flash [100017c8] = d0000000
(4537) r2 = d0000000
(4538) 10001782: 6f93 ldr r3, [r2, #120]
(4538) Read DIV_CSR = 00000001
(4539) r3 = 00000001
(4540) 10001784: 089b lsrs r3, r3, #2
(4540) r3 = 00000000
(4540) nzcv = .1..
(4541) 10001786: d213 bcs 0x100017b0
(4542) 10001788: 6610 str r0, [r2, #96]
(4542) Write DIV_UDIVIDEND = 3b9aca00
(4544) 1000178a: 6651 str r1, [r2, #100]
(4544) Write DIV_UDIVISOR = 0001c200
(4546) 1000178c: 2900 cmp r1, #0
(4546) nzcv = ..1.
(4547) 1000178e: d005 beq 0x1000179c
(4548) 10001790: e7ff b 0x10001792
(4549) 10001792: e7ff b 0x10001794
(4550) 10001794: e7ff b 0x10001796
(4551) 10001796: 6f51 ldr r1, [r2, #116]
(4551) Read DIV_REMAINDER = 0000fa00
(4552) r1 = 0000fa00
(4553) 10001798: 6f10 ldr r0, [r2, #112]
(4553) Read DIV_QUOTIENT = 000021e8
(4554) r0 = 000021e8
(4555) 1000179a: 4770 bx lr
(4556) 10001174: 09c3 lsrs r3, r0, #7
(4556) r3 = 00000043
(4557) 10001176: d121 bne 0x100011bc
(4558) 100011bc: 4a0d ldr r2, [pc, #52]
(4558) Read Flash [100011f4] = 0000fffe
(4559) r2 = 0000fffe
(4560) 100011be: 4293 cmp r3, r2
(4560) nzcv = 1...
(4561) 100011c0: d903 bls 0x100011ca
(4562) 100011ca: 227f movs r2, #127
(4562) r2 = 0000007f
(4562) nzcv = ....
(4563) 100011cc: 4002 ands r2, r0
(4563) r2 = 00000068
(4564) 100011ce: 3201 add r2, #1
(4564) r2 = 00000069
(4565) 100011d0: 0852 lsrs r2, r2, #1
(4565) r2 = 00000034
(4565) nzcv = ..1.
(4566) 100011d2: 019f lsls r7, r3, #6
(4566) r7 = 000010c0
(4566) nzcv = ....
(4567) 100011d4: 0019 movs r1, r3
(4567) r1 = 00000043
(4568) 100011d6: 18bf add r7, r7, r2
(4568) r7 = 000010f4
(4569) 100011d8: 0013 movs r3, r2
(4569) r3 = 00000034
(4570) 100011da: e7cf b 0x1000117c
(4571) 1000117c: 0026 movs r6, r4
(4571) r6 = 40034000
(4572) 1000117e: 2580 movs r5, #128
(4572) r5 = 00000080
(4573) 10001180: 6261 str r1, [r4, #36]
(4573) Write UART0_IBRD = 00000043
(4575) 10001182: 62a3 str r3, [r4, #40]
(4575) Write UART0_FBRD = 00000034
(4577) 10001184: 2300 movs r3, #0
(4577) r3 = 00000000
(4577) nzcv = .1..
(4578) 10001186: 362c add r6, #44
(4578) r6 = 4003402c
(4578) nzcv = ....
(4579) 10001188: 01ad lsls r5, r5, #6
(4579) r5 = 00002000
(4580) 1000118a: 4335 orrs r5, r6
(4580) r5 = 4003602c
(4581) 1000118c: 602b str r3, [r5, #0]
(4581) Write UART0_LCR_H:set = 00000000
(4583) 1000118e: 2006 movs r0, #6
(4583) r0 = 00000006
(4585) 10001190: f000fa26 bl 0x100015e0
(4585) lr = 10001194
(4586) 100015e0: 4b01 ldr r3, [pc, #4]
(4586) Read Flash [100015e8] = 20000240
(4587) r3 = 20000240
(4588) 100015e2: 0080 lsls r0, r0, #2
(4588) r0 = 00000018
(4589) 100015e4: 58c0 ldr r0, [r0, r3]
(4589) Read SRAM [20000258] = 07735940
(4590) r0 = 07735940
(4591) 100015e6: 4770 bx lr
(4592) 10001194: 0039 movs r1, r7
(4592) r1 = 000010f4
(4593) 10001196: 0080 lsls r0, r0, #2
(4593) r0 = 1dcd6500
(4595) 10001198: f000faf2 bl 0x10001780
(4595) lr = 1000119c
(4596) 10001780: 4a11 ldr r2, [pc, #68]
(4596) Read Flash [100017c8] = d0000000
(4597) r2 = d0000000
(4598) 10001782: 6f93 ldr r3, [r2, #120]
(4598) Read DIV_CSR = 00000001
(4599) r3 = 00000001
(4600) 10001784: 089b lsrs r3, r3, #2
(4600) r3 = 00000000
(4600) nzcv = .1..
(4601) 10001786: d213 bcs 0x100017b0
(4602) 10001788: 6610 str r0, [r2, #96]
(4602) Write DIV_UDIVIDEND = 1dcd6500
(4604) 1000178a: 6651 str r1, [r2, #100]
(4604) Write DIV_UDIVISOR = 000010f4
(4606) 1000178c: 2900 cmp r1, #0
(4606) nzcv = ..1.
(4607) 1000178e: d005 beq 0x1000179c
(4608) 10001790: e7ff b 0x10001792
(4609) 10001792: e7ff b 0x10001794
(4610) 10001794: e7ff b 0x10001796
(4611) 10001796: 6f51 ldr r1, [r2, #116]
(4611) Read DIV_REMAINDER = 00000654
(4612) r1 = 00000654
(4613) 10001798: 6f10 ldr r0, [r2, #112]
(4613) Read DIV_QUOTIENT = 0001c207
(4614) r0 = 0001c207
(4615) 1000179a: 4770 bx lr
(4616) 1000119c: 2260 movs r2, #96
(4616) r2 = 00000060
(4617) 1000119e: 6ae3 ldr r3, [r4, #44]
(4617) Read UART0_LCR_H = 00000000
(4618) r3 = 00000000
(4619) 100011a0: 4053 eors r3, r2
(4619) r3 = 00000060
(4620) 100011a2: 320e add r2, #14
(4620) r2 = 0000006e
(4620) nzcv = ....
(4621) 100011a4: 401a ands r2, r3
(4621) r2 = 00000060
(4622) 100011a6: 2380 movs r3, #128
(4622) r3 = 00000080
(4623) 100011a8: 015b lsls r3, r3, #5
(4623) r3 = 00001000
(4624) 100011aa: 4333 orrs r3, r6
(4624) r3 = 4003502c
(4625) 100011ac: 601a str r2, [r3, #0]
(4625) Write UART0_LCR_H:xor = 00000060
(4627) 100011ae: 4b10 ldr r3, [pc, #64]
(4627) Read Flash [100011f0] = 00000301
(4628) r3 = 00000301
(4629) 100011b0: 6323 str r3, [r4, #48]
(4629) Write UART0_CR = 00000301
(4631) 100011b2: 2310 movs r3, #16
(4631) r3 = 00000010
(4632) 100011b4: 602b str r3, [r5, #0]
(4632) Write UART0_LCR_H:set = 00000010
(4634) 100011b6: 3b0d sub r3, #13
(4634) r3 = 00000003
(4634) nzcv = ..1.
(4635) 100011b8: 64a3 str r3, [r4, #72]
(4635) Write UART0_DMACR = 00000003
(4637) 100011ba: bdf8 pop {r3, r4, r5, r6, r7, pc}
(4637) Read SRAM [20041ed0] = 20000608
(4638) r3 = 20000608
(4638) Read SRAM [20041ed4] = 10000264
(4639) r4 = 10000264
(4639) Read SRAM [20041ed8] = 00000000
(4640) r5 = 00000000
(4640) Read SRAM [20041edc] = 00000000
(4641) r6 = 00000000
(4641) Read SRAM [20041ee0] = 00000000
(4642) r7 = 00000000
(4642) Read SRAM [20041ee4] = 10001c30
(4643) msp = 20041ee8
(4644) 10001c30: 2102 movs r1, #2
(4644) r1 = 00000002
(4645) 10001c32: 2000 movs r0, #0
(4645) r0 = 00000000
(4645) nzcv = .11.
(4647) 10001c34: f7fefb76 bl 0x10000324
(4647) lr = 10001c38
(4648) 10000324: 4a09 ldr r2, [pc, #36]
(4648) Read Flash [1000034c] = 4001c004
(4649) r2 = 4001c004
(4650) 10000326: b510 push {r4, lr}
(4650) Write SRAM [20041ee4] = 10001c38
(4651) Write SRAM [20041ee0] = 10000264
(4652) msp = 20041ee0
(4653) 10000328: 4694 mov ip, r2
(4653) ip = 4001c004
(4654) 1000032a: 2440 movs r4, #64
(4654) r4 = 00000040
(4654) nzcv = ..1.
(4655) 1000032c: 0083 lsls r3, r0, #2
(4655) r3 = 00000000
(4655) nzcv = .1..
(4656) 1000032e: 4463 add r3, ip
(4656) r3 = 4001c004
(4657) 10000330: 681a ldr r2, [r3, #0]
(4657) Read BANK0_GPIO0 = 00000000
(4658) r2 = 00000000
(4659) 10000332: 00c0 lsls r0, r0, #3
(4659) r0 = 00000000
(4660) 10000334: 4062 eors r2, r4
(4660) r2 = 00000040
(4660) nzcv = ....
(4661) 10000336: 3480 add r4, #128
(4661) r4 = 000000c0
(4662) 10000338: 4014 ands r4, r2
(4662) r4 = 00000040
(4663) 1000033a: 2280 movs r2, #128
(4663) r2 = 00000080
(4664) 1000033c: 0152 lsls r2, r2, #5
(4664) r2 = 00001000
(4665) 1000033e: 4313 orrs r3, r2
(4665) r3 = 4001d004
(4666) 10000340: 601c str r4, [r3, #0]
(4666) Write BANK0_GPIO0:xor = 00000040
(4668) 10000342: 4b03 ldr r3, [pc, #12]
(4668) Read Flash [10000350] = 40014000
(4669) r3 = 40014000
(4670) 10000344: 469c mov ip, r3
(4670) ip = 40014000
(4671) 10000346: 4460 add r0, ip
(4671) r0 = 40014000
(4672) 10000348: 6041 str r1, [r0, #4]
(4672) Write GPIO0_CTRL = 00000002
(4674) 1000034a: bd10 pop {r4, pc}
(4674) Read SRAM [20041ee0] = 10000264
(4675) r4 = 10000264
(4675) Read SRAM [20041ee4] = 10001c38
(4676) msp = 20041ee8
(4677) 10001c38: 2102 movs r1, #2
(4677) r1 = 00000002
(4678) 10001c3a: 2001 movs r0, #1
(4678) r0 = 00000001
(4680) 10001c3c: f7fefb72 bl 0x10000324
(4680) lr = 10001c40
(4681) 10000324: 4a09 ldr r2, [pc, #36]
(4681) Read Flash [1000034c] = 4001c004
(4682) r2 = 4001c004
(4683) 10000326: b510 push {r4, lr}
(4683) Write SRAM [20041ee4] = 10001c40
(4684) Write SRAM [20041ee0] = 10000264
(4685) msp = 20041ee0
(4686) 10000328: 4694 mov ip, r2
(4686) ip = 4001c004
(4687) 1000032a: 2440 movs r4, #64
(4687) r4 = 00000040
(4688) 1000032c: 0083 lsls r3, r0, #2
(4688) r3 = 00000004
(4689) 1000032e: 4463 add r3, ip
(4689) r3 = 4001c008
(4690) 10000330: 681a ldr r2, [r3, #0]
(4690) Read BANK0_GPIO1 = 00000000
(4691) r2 = 00000000
(4692) 10000332: 00c0 lsls r0, r0, #3
(4692) r0 = 00000008
(4693) 10000334: 4062 eors r2, r4
(4693) r2 = 00000040
(4694) 10000336: 3480 add r4, #128
(4694) r4 = 000000c0
(4695) 10000338: 4014 ands r4, r2
(4695) r4 = 00000040
(4696) 1000033a: 2280 movs r2, #128
(4696) r2 = 00000080
(4697) 1000033c: 0152 lsls r2, r2, #5
(4697) r2 = 00001000
(4698) 1000033e: 4313 orrs r3, r2
(4698) r3 = 4001d008
(4699) 10000340: 601c str r4, [r3, #0]
(4699) Write BANK0_GPIO1:xor = 00000040
(4701) 10000342: 4b03 ldr r3, [pc, #12]
(4701) Read Flash [10000350] = 40014000
(4702) r3 = 40014000
(4703) 10000344: 469c mov ip, r3
(4703) ip = 40014000
(4704) 10000346: 4460 add r0, ip
(4704) r0 = 40014008
(4705) 10000348: 6041 str r1, [r0, #4]
(4705) Write GPIO1_CTRL = 00000002
(4707) 1000034a: bd10 pop {r4, pc}
(4707) Read SRAM [20041ee0] = 10000264
(4708) r4 = 10000264
(4708) Read SRAM [20041ee4] = 10001c40
(4709) msp = 20041ee8
(4710) 10001c40: 2101 movs r1, #1
(4710) r1 = 00000001
(4711) 10001c42: 4806 ldr r0, [pc, #24]
(4711) Read Flash [10001c5c] = 20000210
(4712) r0 = 20000210
(4714) 10001c44: f7ffff8a bl 0x10001b5c
(4714) lr = 10001c48
(4715) 10001b5c: 4a0a ldr r2, [pc, #40]
(4715) Read Flash [10001b88] = 200005b8
(4716) r2 = 200005b8
(4717) 10001b5e: 6813 ldr r3, [r2, #0]
(4717) Read SRAM [200005b8] = 00000000
(4718) r3 = 00000000
(4719) 10001b60: 2b00 cmp r3, #0
(4719) nzcv = .11.
(4720) 10001b62: d105 bne 0x10001b70
(4721) 10001b64: e00c b 0x10001b80
(4722) 10001b80: 2900 cmp r1, #0
(4722) nzcv = ..1.
(4723) 10001b82: d0fc beq 0x10001b7e
(4724) 10001b84: 6010 str r0, [r2, #0]
(4724) Write SRAM [200005b8] = 20000210
(4726) 10001b86: e7fa b 0x10001b7e
(4727) 10001b7e: 4770 bx lr
(4728) 10001c48: bd10 pop {r4, pc}
(4728) Read SRAM [20041ee8] = 10000264
(4729) r4 = 10000264
(4729) Read SRAM [20041eec] = 10001b92
(4730) msp = 20041ef0
(4731) 10001b92: bd10 pop {r4, pc}
(4731) Read SRAM [20041ef0] = 10000264
(4732) r4 = 10000264
(4732) Read SRAM [20041ef4] = 10000316
(4733) msp = 20041ef8
(4734) 10000316: 4802 ldr r0, [pc, #8]
(4734) Read Flash [10000320] = 10001d00
(4735) r0 = 10001d00
(4737) 10000318: f001fbac bl 0x10001a74
(4737) lr = 1000031c
(4738) 10001a74: b5f0 push {r4, r5, r6, r7, lr}
(4738) Write SRAM [20041ef4] = 1000031c
(4739) Write SRAM [20041ef0] = 00000000
(4740) Write SRAM [20041eec] = 00000000
(4741) Write SRAM [20041ee8] = 00000000
(4742) Write SRAM [20041ee4] = 10000264
(4743) msp = 20041ee4
(4744) 10001a76: 46de mov lr, fp
(4744) lr = 00000000
(4745) 10001a78: 4645 mov r5, r8
(4745) r5 = 00000000
(4746) 10001a7a: 464e mov r6, r9
(4746) r6 = 00000000
(4747) 10001a7c: 4657 mov r7, sl
(4747) r7 = 00000000
(4748) 10001a7e: b5e0 push {r5, r6, r7, lr}
(4748) Write SRAM [20041ee0] = 00000000
(4749) Write SRAM [20041edc] = 00000000
(4750) Write SRAM [20041ed8] = 00000000
(4751) Write SRAM [20041ed4] = 00000000
(4752) msp = 20041ed4
(4753) 10001a80: b083 sub sp, #12
(4753) msp = 20041ec8
(4754) 10001a82: 0006 movs r6, r0
(4754) r6 = 10001d00
(4756) 10001a84: f000f8ec bl 0x10001c60
(4756) lr = 10001a88
(4757) 10001c60: b510 push {r4, lr}
(4757) Write SRAM [20041ec4] = 10001a88
(4758) Write SRAM [20041ec0] = 10000264
(4759) msp = 20041ec0
(4760) 10001c62: 0783 lsls r3, r0, #30
(4760) r3 = 00000000
(4760) nzcv = .1..
(4761) 10001c64: d00a beq 0x10001c7c
(4762) 10001c7c: 0003 movs r3, r0
(4762) r3 = 10001d00
(4762) nzcv = ....
(4763) 10001c7e: 6819 ldr r1, [r3, #0]
(4763) Read Flash [10001d00] = 6c6c6548
(4764) r1 = 6c6c6548
(4765) 10001c80: 4a0c ldr r2, [pc, #48]
(4765) Read Flash [10001cb4] = fefefeff
(4766) r2 = fefefeff
(4767) 10001c82: 4c0d ldr r4, [pc, #52]
(4767) Read Flash [10001cb8] = 80808080
(4768) r4 = 80808080
(4769) 10001c84: 188a add r2, r1, r2
(4769) r2 = 6b6b6447
(4769) nzcv = ..1.
(4770) 10001c86: 438a bics r2, r1
(4770) r2 = 03030007
(4771) 10001c88: 4222 tst r2, r4
(4771) nzcv = .11.
(4772) 10001c8a: d10f bne 0x10001cac
(4773) 10001c8c: 6859 ldr r1, [r3, #4]
(4773) Read Flash [10001d04] = 7266206f
(4774) r1 = 7266206f
(4775) 10001c8e: 4a09 ldr r2, [pc, #36]
(4775) Read Flash [10001cb4] = fefefeff
(4776) r2 = fefefeff
(4777) 10001c90: 3304 add r3, #4
(4777) r3 = 10001d04
(4777) nzcv = ....
(4778) 10001c92: 188a add r2, r1, r2
(4778) r2 = 71651f6e
(4778) nzcv = ..1.
(4779) 10001c94: 438a bics r2, r1
(4779) r2 = 01011f00
(4780) 10001c96: 4222 tst r2, r4
(4780) nzcv = .11.
(4781) 10001c98: d108 bne 0x10001cac
(4782) 10001c9a: 6859 ldr r1, [r3, #4]
(4782) Read Flash [10001d08] = 55206d6f
(4783) r1 = 55206d6f
(4784) 10001c9c: 4a05 ldr r2, [pc, #20]
(4784) Read Flash [10001cb4] = fefefeff
(4785) r2 = fefefeff
(4786) 10001c9e: 3304 add r3, #4
(4786) r3 = 10001d08
(4786) nzcv = ....
(4787) 10001ca0: 188a add r2, r1, r2
(4787) r2 = 541f6c6e
(4787) nzcv = ..1.
(4788) 10001ca2: 438a bics r2, r1
(4788) r2 = 001f0000
(4789) 10001ca4: 4222 tst r2, r4
(4789) nzcv = .11.
(4790) 10001ca6: d0f1 beq 0x10001c8c
(4791) 10001c8c: 6859 ldr r1, [r3, #4]
(4791) Read Flash [10001d0c] = 21545241
(4792) r1 = 21545241
(4793) 10001c8e: 4a09 ldr r2, [pc, #36]
(4793) Read Flash [10001cb4] = fefefeff
(4794) r2 = fefefeff
(4795) 10001c90: 3304 add r3, #4
(4795) r3 = 10001d0c
(4795) nzcv = ....
(4796) 10001c92: 188a add r2, r1, r2
(4796) r2 = 20535140
(4796) nzcv = ..1.
(4797) 10001c94: 438a bics r2, r1
(4797) r2 = 00030100
(4798) 10001c96: 4222 tst r2, r4
(4798) nzcv = .11.
(4799) 10001c98: d108 bne 0x10001cac
(4800) 10001c9a: 6859 ldr r1, [r3, #4]
(4800) Read Flash [10001d10] = 00000000
(4801) r1 = 00000000
(4802) 10001c9c: 4a05 ldr r2, [pc, #20]
(4802) Read Flash [10001cb4] = fefefeff
(4803) r2 = fefefeff
(4804) 10001c9e: 3304 add r3, #4
(4804) r3 = 10001d10
(4804) nzcv = ....
(4805) 10001ca0: 188a add r2, r1, r2
(4805) r2 = fefefeff
(4805) nzcv = 1...
(4806) 10001ca2: 438a bics r2, r1
(4806) r2 = fefefeff
(4807) 10001ca4: 4222 tst r2, r4
(4808) 10001ca6: d0f1 beq 0x10001c8c
(4809) 10001ca8: e000 b 0x10001cac
(4810) 10001cac: 781a ldrb r2, [r3, #0]
(4810) Read Flash [10001d10] = 00
(4811) r2 = 00000000
(4812) 10001cae: 2a00 cmp r2, #0
(4812) nzcv = .11.
(4813) 10001cb0: d1fb bne 0x10001caa
(4814) 10001cb2: e7e1 b 0x10001c78
(4815) 10001c78: 1a18 sub r0, r3, r0
(4815) r0 = 00000010
(4815) nzcv = ..1.
(4816) 10001c7a: bd10 pop {r4, pc}
(4816) Read SRAM [20041ec0] = 10000264
(4817) r4 = 10000264
(4817) Read SRAM [20041ec4] = 10001a88
(4818) msp = 20041ec8
(4819) 10001a88: 23d0 movs r3, #208
(4819) r3 = 000000d0
(4820) 10001a8a: 061b lsls r3, r3, #24
(4820) r3 = d0000000
(4820) nzcv = 1...
(4821) 10001a8c: 681c ldr r4, [r3, #0]
(4821) Read CPUID = 00000000
(4822) r4 = 00000000
(4823) 10001a8e: 4b30 ldr r3, [pc, #192]
(4823) Read Flash [10001b50] = 20000224
(4824) r3 = 20000224
(4825) 10001a90: 0005 movs r5, r0
(4825) r5 = 00000010
(4825) nzcv = ....
(4826) 10001a92: a901 add r1, sp, #4
(4826) r1 = 20041ecc
(4827) 10001a94: 0018 movs r0, r3
(4827) r0 = 20000224
(4828) 10001a96: 469b mov fp, r3
(4828) fp = 20000224
(4830) 10001a98: f000f922 bl 0x10001ce0
(4830) lr = 10001a9c
(4831) 10001ce0: b401 push {r0}
(4831) Write SRAM [20041ec4] = 20000224
(4832) msp = 20041ec4
(4833) 10001ce2: 4802 ldr r0, [pc, #8]
(4833) Read Flash [10001cec] = 20000109
(4834) r0 = 20000109
(4835) 10001ce4: 4684 mov ip, r0
(4835) ip = 20000109
(4836) 10001ce6: bc01 pop {r0}
(4836) Read SRAM [20041ec4] = 20000224
(4837) r0 = 20000224
(4837) msp = 20041ec8
(4838) 10001ce8: 4760 bx ip
(4839) 20000108: 0003 movs r3, r0
(4839) r3 = 20000224
(4840) 2000010a: 6800 ldr r0, [r0, #0]
(4840) Read SRAM [20000224] = d0000140
(4841) r0 = d0000140
(4843) 2000010c: f3ef8c10 mrs ip, PRIMASK
(4843) ip = 00000000
(4844) 20000110: b672 cpsid i
(4844) primask = 00000001
(4845) 20000112: 6802 ldr r2, [r0, #0]
(4845) Read SPINLOCK16 = 00010000
(4846) r2 = 00010000
(4847) 20000114: 2a00 cmp r2, #0
(4847) nzcv = ..1.
(4848) 20000116: d0fc beq 0x20000112
(4850) 20000118: f3bf8f5f dmb #15
(4851) 2000011c: 2204 movs r2, #4
(4851) r2 = 00000004
(4852) 2000011e: 569a ldrsb r2, [r3, r2]
(4852) Read SRAM [20000228] = ff
(4853) r2 = ffffffff
(4854) 20000120: 2a00 cmp r2, #0
(4854) nzcv = 1.1.
(4855) 20000122: db04 blt 0x2000012e
(4856) 2000012e: 22d0 movs r2, #208
(4856) r2 = 000000d0
(4856) nzcv = ..1.
(4857) 20000130: 2001 movs r0, #1
(4857) r0 = 00000001
(4858) 20000132: 0612 lsls r2, r2, #24
(4858) r2 = d0000000
(4858) nzcv = 1...
(4859) 20000134: 6812 ldr r2, [r2, #0]
(4859) Read CPUID = 00000000
(4860) r2 = 00000000
(4861) 20000136: 711a strb r2, [r3, #4]
(4861) Write SRAM [20000228] = 00
(4863) 20000138: 681b ldr r3, [r3, #0]
(4863) Read SRAM [20000224] = d0000140
(4864) r3 = d0000140
(4866) 2000013a: f3bf8f5f dmb #15
(4867) 2000013e: 2200 movs r2, #0
(4867) r2 = 00000000
(4867) nzcv = .1..
(4868) 20000140: 601a str r2, [r3, #0]
(4868) Write SPINLOCK16 = 00000000
(4871) 20000142: f38c8810 msr PRIMASK, ip
(4871) primask = 00000000
(4872) 20000146: 4770 bx lr
(4873) 10001a9c: 4680 mov r8, r0
(4873) r8 = 00000001
(4874) 10001a9e: 2800 cmp r0, #0
(4874) nzcv = ..1.
(4875) 10001aa0: d03d beq 0x10001b1e
(4876) 10001aa2: 4b2c ldr r3, [pc, #176]
(4876) Read Flash [10001b54] = 200005b8
(4877) r3 = 200005b8
(4878) 10001aa4: 681c ldr r4, [r3, #0]
(4878) Read SRAM [200005b8] = 20000210
(4879) r4 = 20000210
(4880) 10001aa6: 469a mov sl, r3
(4880) sl = 200005b8
(4881) 10001aa8: 2c00 cmp r4, #0
(4882) 10001aaa: d047 beq 0x10001b3c
(4883) 10001aac: 230a movs r3, #10
(4883) r3 = 0000000a
(4884) 10001aae: 4f2a ldr r7, [pc, #168]
(4884) Read Flash [10001b58] = 200005bc
(4885) r7 = 200005bc
(4886) 10001ab0: 4699 mov r9, r3
(4886) r9 = 0000000a
(4887) 10001ab2: e002 b 0x10001aba
(4888) 10001aba: 6823 ldr r3, [r4, #0]
(4888) Read SRAM [20000210] = 10001b95
(4889) r3 = 10001b95
(4890) 10001abc: 2b00 cmp r3, #0
(4891) 10001abe: d0f9 beq 0x10001ab4
(4892) 10001ac0: 683b ldr r3, [r7, #0]
(4892) Read SRAM [200005bc] = 00000000
(4893) r3 = 00000000
(4894) 10001ac2: 2b00 cmp r3, #0
(4894) nzcv = .11.
(4895) 10001ac4: d001 beq 0x10001aca
(4896) 10001aca: 0020 movs r0, r4
(4896) r0 = 20000210
(4896) nzcv = ..1.
(4897) 10001acc: 002a movs r2, r5
(4897) r2 = 00000010
(4898) 10001ace: 0031 movs r1, r6
(4898) r1 = 10001d00
(4900) 10001ad0: f7ffff34 bl 0x1000193c
(4900) lr = 10001ad4
(4901) 1000193c: b5f0 push {r4, r5, r6, r7, lr}
(4901) Write SRAM [20041ec4] = 10001ad4
(4902) Write SRAM [20041ec0] = 200005bc
(4903) Write SRAM [20041ebc] = 10001d00
(4904) Write SRAM [20041eb8] = 00000010
(4905) Write SRAM [20041eb4] = 20000210
(4906) msp = 20041eb4
(4907) 1000193e: 46c6 mov lr, r8
(4907) lr = 00000001
(4908) 10001940: b500 push {lr}
(4908) Write SRAM [20041eb0] = 00000001
(4909) msp = 20041eb0
(4910) 10001942: 7c43 ldrb r3, [r0, #17]
(4910) Read SRAM [20000221] = 01
(4911) r3 = 00000001
(4912) 10001944: 0007 movs r7, r0
(4912) r7 = 20000210
(4913) 10001946: 000d movs r5, r1
(4913) r5 = 10001d00
(4914) 10001948: 0016 movs r6, r2
(4914) r6 = 00000010
(4915) 1000194a: 2b00 cmp r3, #0
(4916) 1000194c: d038 beq 0x100019c0
(4917) 1000194e: 2a00 cmp r2, #0
(4918) 10001950: dd2e ble 0x100019b0
(4919) 10001952: 2100 movs r1, #0
(4919) r1 = 00000000
(4919) nzcv = .11.
(4920) 10001954: 1e6a sub r2, r5, #1
(4920) r2 = 10001cff
(4920) nzcv = ..1.
(4921) 10001956: 4690 mov r8, r2
(4921) r8 = 10001cff
(4922) 10001958: 5c6a ldrb r2, [r5, r1]
(4922) Read Flash [10001d00] = 48
(4923) r2 = 00000048
(4924) 1000195a: 7c03 ldrb r3, [r0, #16]
(4924) Read SRAM [20000220] = 00
(4925) r3 = 00000000
(4926) 1000195c: 1c4c add r4, r1, #1
(4926) r4 = 00000001
(4926) nzcv = ....
(4927) 1000195e: 2000 movs r0, #0
(4927) r0 = 00000000
(4927) nzcv = .1..
(4928) 10001960: 2a0a cmp r2, #10
(4928) nzcv = ..1.
(4929) 10001962: d00c beq 0x1000197e
(4930) 10001964: 42a6 cmp r6, r4
(4931) 10001966: d016 beq 0x10001996
(4932) 10001968: 4643 mov r3, r8
(4932) r3 = 10001cff
(4933) 1000196a: 5d1b ldrb r3, [r3, r4]
(4933) Read Flash [10001d00] = 48
(4934) r3 = 00000048
(4935) 1000196c: 0021 movs r1, r4
(4935) r1 = 00000001
(4936) 1000196e: 3b0d sub r3, #13
(4936) r3 = 0000003b
(4937) 10001970: 425a neg r2, r3
(4937) r2 = ffffffc5
(4937) nzcv = 1...
(4938) 10001972: 4153 adc r3, r2
(4938) r3 = 00000000
(4938) nzcv = .11.
(4939) 10001974: 5c6a ldrb r2, [r5, r1]
(4939) Read Flash [10001d01] = 65
(4940) r2 = 00000065
(4941) 10001976: b2db uxtb r3, r3
(4941) r3 = 00000000
(4942) 10001978: 1c4c add r4, r1, #1
(4942) r4 = 00000002
(4942) nzcv = ....
(4943) 1000197a: 2a0a cmp r2, #10
(4943) nzcv = ..1.
(4944) 1000197c: d1f2 bne 0x10001964
(4945) 10001964: 42a6 cmp r6, r4
(4946) 10001966: d016 beq 0x10001996
(4947) 10001968: 4643 mov r3, r8
(4947) r3 = 10001cff
(4948) 1000196a: 5d1b ldrb r3, [r3, r4]
(4948) Read Flash [10001d01] = 65
(4949) r3 = 00000065
(4950) 1000196c: 0021 movs r1, r4
(4950) r1 = 00000002
(4951) 1000196e: 3b0d sub r3, #13
(4951) r3 = 00000058
(4952) 10001970: 425a neg r2, r3
(4952) r2 = ffffffa8
(4952) nzcv = 1...
(4953) 10001972: 4153 adc r3, r2
(4953) r3 = 00000000
(4953) nzcv = .11.
(4954) 10001974: 5c6a ldrb r2, [r5, r1]
(4954) Read Flash [10001d02] = 6c
(4955) r2 = 0000006c
(4956) 10001976: b2db uxtb r3, r3
(4956) r3 = 00000000
(4957) 10001978: 1c4c add r4, r1, #1
(4957) r4 = 00000003
(4957) nzcv = ....
(4958) 1000197a: 2a0a cmp r2, #10
(4958) nzcv = ..1.
(4959) 1000197c: d1f2 bne 0x10001964
(4960) 10001964: 42a6 cmp r6, r4
(4961) 10001966: d016 beq 0x10001996
(4962) 10001968: 4643 mov r3, r8
(4962) r3 = 10001cff
(4963) 1000196a: 5d1b ldrb r3, [r3, r4]
(4963) Read Flash [10001d02] = 6c
(4964) r3 = 0000006c
(4965) 1000196c: 0021 movs r1, r4
(4965) r1 = 00000003
(4966) 1000196e: 3b0d sub r3, #13
(4966) r3 = 0000005f
(4967) 10001970: 425a neg r2, r3
(4967) r2 = ffffffa1
(4967) nzcv = 1...
(4968) 10001972: 4153 adc r3, r2
(4968) r3 = 00000000
(4968) nzcv = .11.
(4969) 10001974: 5c6a ldrb r2, [r5, r1]
(4969) Read Flash [10001d03] = 6c
(4970) r2 = 0000006c
(4971) 10001976: b2db uxtb r3, r3
(4971) r3 = 00000000
(4972) 10001978: 1c4c add r4, r1, #1
(4972) r4 = 00000004
(4972) nzcv = ....
(4973) 1000197a: 2a0a cmp r2, #10
(4973) nzcv = ..1.
(4974) 1000197c: d1f2 bne 0x10001964
(4975) 10001964: 42a6 cmp r6, r4
(4976) 10001966: d016 beq 0x10001996
(4977) 10001968: 4643 mov r3, r8
(4977) r3 = 10001cff
(4978) 1000196a: 5d1b ldrb r3, [r3, r4]
(4978) Read Flash [10001d03] = 6c
(4979) r3 = 0000006c
(4980) 1000196c: 0021 movs r1, r4
(4980) r1 = 00000004
(4981) 1000196e: 3b0d sub r3, #13
(4981) r3 = 0000005f
(4982) 10001970: 425a neg r2, r3
(4982) r2 = ffffffa1
(4982) nzcv = 1...
(4983) 10001972: 4153 adc r3, r2
(4983) r3 = 00000000
(4983) nzcv = .11.
(4984) 10001974: 5c6a ldrb r2, [r5, r1]
(4984) Read Flash [10001d04] = 6f
(4985) r2 = 0000006f
(4986) 10001976: b2db uxtb r3, r3
(4986) r3 = 00000000
(4987) 10001978: 1c4c add r4, r1, #1
(4987) r4 = 00000005
(4987) nzcv = ....
(4988) 1000197a: 2a0a cmp r2, #10
(4988) nzcv = ..1.
(4989) 1000197c: d1f2 bne 0x10001964
(4990) 10001964: 42a6 cmp r6, r4
(4991) 10001966: d016 beq 0x10001996
(4992) 10001968: 4643 mov r3, r8
(4992) r3 = 10001cff
(4993) 1000196a: 5d1b ldrb r3, [r3, r4]
(4993) Read Flash [10001d04] = 6f
(4994) r3 = 0000006f
(4995) 1000196c: 0021 movs r1, r4
(4995) r1 = 00000005
(4996) 1000196e: 3b0d sub r3, #13
(4996) r3 = 00000062
(4997) 10001970: 425a neg r2, r3
(4997) r2 = ffffff9e
(4997) nzcv = 1...
(4998) 10001972: 4153 adc r3, r2
(4998) r3 = 00000000
(4998) nzcv = .11.
(4999) 10001974: 5c6a ldrb r2, [r5, r1]
(4999) Read Flash [10001d05] = 20
(5000) r2 = 00000020
(5001) 10001976: b2db uxtb r3, r3
(5001) r3 = 00000000
(5002) 10001978: 1c4c add r4, r1, #1
(5002) r4 = 00000006
(5002) nzcv = ....
(5003) 1000197a: 2a0a cmp r2, #10
(5003) nzcv = ..1.
(5004) 1000197c: d1f2 bne 0x10001964
(5005) 10001964: 42a6 cmp r6, r4
(5006) 10001966: d016 beq 0x10001996
(5007) 10001968: 4643 mov r3, r8
(5007) r3 = 10001cff
(5008) 1000196a: 5d1b ldrb r3, [r3, r4]
(5008) Read Flash [10001d05] = 20
(5009) r3 = 00000020
(5010) 1000196c: 0021 movs r1, r4
(5010) r1 = 00000006
(5011) 1000196e: 3b0d sub r3, #13
(5011) r3 = 00000013
(5012) 10001970: 425a neg r2, r3
(5012) r2 = ffffffed
(5012) nzcv = 1...
(5013) 10001972: 4153 adc r3, r2
(5013) r3 = 00000000
(5013) nzcv = .11.
(5014) 10001974: 5c6a ldrb r2, [r5, r1]
(5014) Read Flash [10001d06] = 66
(5015) r2 = 00000066
(5016) 10001976: b2db uxtb r3, r3
(5016) r3 = 00000000
(5017) 10001978: 1c4c add r4, r1, #1
(5017) r4 = 00000007
(5017) nzcv = ....
(5018) 1000197a: 2a0a cmp r2, #10
(5018) nzcv = ..1.
(5019) 1000197c: d1f2 bne 0x10001964
(5020) 10001964: 42a6 cmp r6, r4
(5021) 10001966: d016 beq 0x10001996
(5022) 10001968: 4643 mov r3, r8
(5022) r3 = 10001cff
(5023) 1000196a: 5d1b ldrb r3, [r3, r4]
(5023) Read Flash [10001d06] = 66
(5024) r3 = 00000066
(5025) 1000196c: 0021 movs r1, r4
(5025) r1 = 00000007
(5026) 1000196e: 3b0d sub r3, #13
(5026) r3 = 00000059
(5027) 10001970: 425a neg r2, r3
(5027) r2 = ffffffa7
(5027) nzcv = 1...
(5028) 10001972: 4153 adc r3, r2
(5028) r3 = 00000000
(5028) nzcv = .11.
(5029) 10001974: 5c6a ldrb r2, [r5, r1]
(5029) Read Flash [10001d07] = 72
(5030) r2 = 00000072
(5031) 10001976: b2db uxtb r3, r3
(5031) r3 = 00000000
(5032) 10001978: 1c4c add r4, r1, #1
(5032) r4 = 00000008
(5032) nzcv = ....
(5033) 1000197a: 2a0a cmp r2, #10
(5033) nzcv = ..1.
(5034) 1000197c: d1f2 bne 0x10001964
(5035) 10001964: 42a6 cmp r6, r4
(5036) 10001966: d016 beq 0x10001996
(5037) 10001968: 4643 mov r3, r8
(5037) r3 = 10001cff
(5038) 1000196a: 5d1b ldrb r3, [r3, r4]
(5038) Read Flash [10001d07] = 72
(5039) r3 = 00000072
(5040) 1000196c: 0021 movs r1, r4
(5040) r1 = 00000008
(5041) 1000196e: 3b0d sub r3, #13
(5041) r3 = 00000065
(5042) 10001970: 425a neg r2, r3
(5042) r2 = ffffff9b
(5042) nzcv = 1...
(5043) 10001972: 4153 adc r3, r2
(5043) r3 = 00000000
(5043) nzcv = .11.
(5044) 10001974: 5c6a ldrb r2, [r5, r1]
(5044) Read Flash [10001d08] = 6f
(5045) r2 = 0000006f
(5046) 10001976: b2db uxtb r3, r3
(5046) r3 = 00000000
(5047) 10001978: 1c4c add r4, r1, #1
(5047) r4 = 00000009
(5047) nzcv = ....
(5048) 1000197a: 2a0a cmp r2, #10
(5048) nzcv = ..1.
(5049) 1000197c: d1f2 bne 0x10001964
(5050) 10001964: 42a6 cmp r6, r4
(5051) 10001966: d016 beq 0x10001996
(5052) 10001968: 4643 mov r3, r8
(5052) r3 = 10001cff
(5053) 1000196a: 5d1b ldrb r3, [r3, r4]
(5053) Read Flash [10001d08] = 6f
(5054) r3 = 0000006f
(5055) 1000196c: 0021 movs r1, r4
(5055) r1 = 00000009
(5056) 1000196e: 3b0d sub r3, #13
(5056) r3 = 00000062
(5057) 10001970: 425a neg r2, r3
(5057) r2 = ffffff9e
(5057) nzcv = 1...
(5058) 10001972: 4153 adc r3, r2
(5058) r3 = 00000000
(5058) nzcv = .11.
(5059) 10001974: 5c6a ldrb r2, [r5, r1]
(5059) Read Flash [10001d09] = 6d
(5060) r2 = 0000006d
(5061) 10001976: b2db uxtb r3, r3
(5061) r3 = 00000000
(5062) 10001978: 1c4c add r4, r1, #1
(5062) r4 = 0000000a
(5062) nzcv = ....
(5063) 1000197a: 2a0a cmp r2, #10
(5063) nzcv = ..1.
(5064) 1000197c: d1f2 bne 0x10001964
(5065) 10001964: 42a6 cmp r6, r4
(5066) 10001966: d016 beq 0x10001996
(5067) 10001968: 4643 mov r3, r8
(5067) r3 = 10001cff
(5068) 1000196a: 5d1b ldrb r3, [r3, r4]
(5068) Read Flash [10001d09] = 6d
(5069) r3 = 0000006d
(5070) 1000196c: 0021 movs r1, r4
(5070) r1 = 0000000a
(5071) 1000196e: 3b0d sub r3, #13
(5071) r3 = 00000060
(5072) 10001970: 425a neg r2, r3
(5072) r2 = ffffffa0
(5072) nzcv = 1...
(5073) 10001972: 4153 adc r3, r2
(5073) r3 = 00000000
(5073) nzcv = .11.
(5074) 10001974: 5c6a ldrb r2, [r5, r1]
(5074) Read Flash [10001d0a] = 20
(5075) r2 = 00000020
(5076) 10001976: b2db uxtb r3, r3
(5076) r3 = 00000000
(5077) 10001978: 1c4c add r4, r1, #1
(5077) r4 = 0000000b
(5077) nzcv = ....
(5078) 1000197a: 2a0a cmp r2, #10
(5078) nzcv = ..1.
(5079) 1000197c: d1f2 bne 0x10001964
(5080) 10001964: 42a6 cmp r6, r4
(5081) 10001966: d016 beq 0x10001996
(5082) 10001968: 4643 mov r3, r8
(5082) r3 = 10001cff
(5083) 1000196a: 5d1b ldrb r3, [r3, r4]
(5083) Read Flash [10001d0a] = 20
(5084) r3 = 00000020
(5085) 1000196c: 0021 movs r1, r4
(5085) r1 = 0000000b
(5086) 1000196e: 3b0d sub r3, #13
(5086) r3 = 00000013
(5087) 10001970: 425a neg r2, r3
(5087) r2 = ffffffed
(5087) nzcv = 1...
(5088) 10001972: 4153 adc r3, r2
(5088) r3 = 00000000
(5088) nzcv = .11.
(5089) 10001974: 5c6a ldrb r2, [r5, r1]
(5089) Read Flash [10001d0b] = 55
(5090) r2 = 00000055
(5091) 10001976: b2db uxtb r3, r3
(5091) r3 = 00000000
(5092) 10001978: 1c4c add r4, r1, #1
(5092) r4 = 0000000c
(5092) nzcv = ....
(5093) 1000197a: 2a0a cmp r2, #10
(5093) nzcv = ..1.
(5094) 1000197c: d1f2 bne 0x10001964
(5095) 10001964: 42a6 cmp r6, r4
(5096) 10001966: d016 beq 0x10001996
(5097) 10001968: 4643 mov r3, r8
(5097) r3 = 10001cff
(5098) 1000196a: 5d1b ldrb r3, [r3, r4]
(5098) Read Flash [10001d0b] = 55
(5099) r3 = 00000055
(5100) 1000196c: 0021 movs r1, r4
(5100) r1 = 0000000c
(5101) 1000196e: 3b0d sub r3, #13
(5101) r3 = 00000048
(5102) 10001970: 425a neg r2, r3
(5102) r2 = ffffffb8
(5102) nzcv = 1...
(5103) 10001972: 4153 adc r3, r2
(5103) r3 = 00000000
(5103) nzcv = .11.
(5104) 10001974: 5c6a ldrb r2, [r5, r1]
(5104) Read Flash [10001d0c] = 41
(5105) r2 = 00000041
(5106) 10001976: b2db uxtb r3, r3
(5106) r3 = 00000000
(5107) 10001978: 1c4c add r4, r1, #1
(5107) r4 = 0000000d
(5107) nzcv = ....
(5108) 1000197a: 2a0a cmp r2, #10
(5108) nzcv = ..1.
(5109) 1000197c: d1f2 bne 0x10001964
(5110) 10001964: 42a6 cmp r6, r4
(5111) 10001966: d016 beq 0x10001996
(5112) 10001968: 4643 mov r3, r8
(5112) r3 = 10001cff
(5113) 1000196a: 5d1b ldrb r3, [r3, r4]
(5113) Read Flash [10001d0c] = 41
(5114) r3 = 00000041
(5115) 1000196c: 0021 movs r1, r4
(5115) r1 = 0000000d
(5116) 1000196e: 3b0d sub r3, #13
(5116) r3 = 00000034
(5117) 10001970: 425a neg r2, r3
(5117) r2 = ffffffcc
(5117) nzcv = 1...
(5118) 10001972: 4153 adc r3, r2
(5118) r3 = 00000000
(5118) nzcv = .11.
(5119) 10001974: 5c6a ldrb r2, [r5, r1]
(5119) Read Flash [10001d0d] = 52
(5120) r2 = 00000052
(5121) 10001976: b2db uxtb r3, r3
(5121) r3 = 00000000
(5122) 10001978: 1c4c add r4, r1, #1
(5122) r4 = 0000000e
(5122) nzcv = ....
(5123) 1000197a: 2a0a cmp r2, #10
(5123) nzcv = ..1.
(5124) 1000197c: d1f2 bne 0x10001964
(5125) 10001964: 42a6 cmp r6, r4
(5126) 10001966: d016 beq 0x10001996
(5127) 10001968: 4643 mov r3, r8
(5127) r3 = 10001cff
(5128) 1000196a: 5d1b ldrb r3, [r3, r4]
(5128) Read Flash [10001d0d] = 52
(5129) r3 = 00000052
(5130) 1000196c: 0021 movs r1, r4
(5130) r1 = 0000000e
(5131) 1000196e: 3b0d sub r3, #13
(5131) r3 = 00000045
(5132) 10001970: 425a neg r2, r3
(5132) r2 = ffffffbb
(5132) nzcv = 1...
(5133) 10001972: 4153 adc r3, r2
(5133) r3 = 00000000
(5133) nzcv = .11.
(5134) 10001974: 5c6a ldrb r2, [r5, r1]
(5134) Read Flash [10001d0e] = 54
(5135) r2 = 00000054
(5136) 10001976: b2db uxtb r3, r3
(5136) r3 = 00000000
(5137) 10001978: 1c4c add r4, r1, #1
(5137) r4 = 0000000f
(5137) nzcv = ....
(5138) 1000197a: 2a0a cmp r2, #10
(5138) nzcv = ..1.
(5139) 1000197c: d1f2 bne 0x10001964
(5140) 10001964: 42a6 cmp r6, r4
(5141) 10001966: d016 beq 0x10001996
(5142) 10001968: 4643 mov r3, r8
(5142) r3 = 10001cff
(5143) 1000196a: 5d1b ldrb r3, [r3, r4]
(5143) Read Flash [10001d0e] = 54
(5144) r3 = 00000054
(5145) 1000196c: 0021 movs r1, r4
(5145) r1 = 0000000f
(5146) 1000196e: 3b0d sub r3, #13
(5146) r3 = 00000047
(5147) 10001970: 425a neg r2, r3
(5147) r2 = ffffffb9
(5147) nzcv = 1...
(5148) 10001972: 4153 adc r3, r2
(5148) r3 = 00000000
(5148) nzcv = .11.
(5149) 10001974: 5c6a ldrb r2, [r5, r1]
(5149) Read Flash [10001d0f] = 21
(5150) r2 = 00000021
(5151) 10001976: b2db uxtb r3, r3
(5151) r3 = 00000000
(5152) 10001978: 1c4c add r4, r1, #1
(5152) r4 = 00000010
(5152) nzcv = ....
(5153) 1000197a: 2a0a cmp r2, #10
(5153) nzcv = ..1.
(5154) 1000197c: d1f2 bne 0x10001964
(5155) 10001964: 42a6 cmp r6, r4
(5155) nzcv = .11.
(5156) 10001966: d016 beq 0x10001996
(5157) 10001996: 4286 cmp r6, r0
(5157) nzcv = ..1.
(5158) 10001998: dd03 ble 0x100019a2
(5159) 1000199a: 1a31 sub r1, r6, r0
(5159) r1 = 00000010
(5160) 1000199c: 683b ldr r3, [r7, #0]
(5160) Read SRAM [20000210] = 10001b95
(5161) r3 = 10001b95
(5162) 1000199e: 1828 add r0, r5, r0
(5162) r0 = 10001d00
(5162) nzcv = ....
(5163) 100019a0: 4798 blx r3
(5163) lr = 100019a2
(5164) 10001b94: b5f0 push {r4, r5, r6, r7, lr}
(5164) Write SRAM [20041eac] = 100019a2
(5165) Write SRAM [20041ea8] = 20000210
(5166) Write SRAM [20041ea4] = 00000010
(5167) Write SRAM [20041ea0] = 10001d00
(5168) Write SRAM [20041e9c] = 00000010
(5169) msp = 20041e9c
(5170) 10001b96: 2900 cmp r1, #0
(5170) nzcv = ..1.
(5171) 10001b98: dd15 ble 0x10001bc6
(5172) 10001b9a: 4b0e ldr r3, [pc, #56]
(5172) Read Flash [10001bd4] = 20000608
(5173) r3 = 20000608
(5174) 10001b9c: 270d movs r7, #13
(5174) r7 = 0000000d
(5175) 10001b9e: 681a ldr r2, [r3, #0]
(5175) Read SRAM [20000608] = 40034000
(5176) r2 = 40034000
(5177) 10001ba0: 4b0d ldr r3, [pc, #52]
(5177) Read Flash [10001bd8] = bffc8000
(5178) r3 = bffc8000
(5179) 10001ba2: 4c0e ldr r4, [pc, #56]
(5179) Read Flash [10001bdc] = 20000604
(5180) r4 = 20000604
(5181) 10001ba4: 18d3 add r3, r2, r3
(5181) r3 = ffffc000
(5181) nzcv = 1...
(5182) 10001ba6: 425d neg r5, r3
(5182) r5 = 00004000
(5182) nzcv = ....
(5183) 10001ba8: 416b adc r3, r5
(5183) r3 = 00000000
(5183) nzcv = .11.
(5184) 10001baa: 1845 add r5, r0, r1
(5184) r5 = 10001d10
(5184) nzcv = ....
(5185) 10001bac: 2120 movs r1, #32
(5185) r1 = 00000020
(5186) 10001bae: 005b lsls r3, r3, #1
(5186) r3 = 00000000
(5186) nzcv = .1..
(5187) 10001bb0: 5f1e ldrsh r6, [r3, r4]
(5187) Read SRAM [20000604] = 0100
(5188) r6 = 00000100
(5189) 10001bb2: 7804 ldrb r4, [r0, #0]
(5189) Read Flash [10001d00] = 48
(5190) r4 = 00000048
(5191) 10001bb4: 42a6 cmp r6, r4
(5191) nzcv = ..1.
(5192) 10001bb6: d007 beq 0x10001bc8
(5193) 10001bb8: 6993 ldr r3, [r2, #24]
(5193) Read UART0_FR = 00000000
(5194) r3 = 00000000
(5195) 10001bba: 4219 tst r1, r3
(5195) nzcv = .11.
(5196) 10001bbc: d1fc bne 0x10001bb8
(5197) 10001bbe: 3001 add r0, #1
(5197) r0 = 10001d01
(5197) nzcv = ....
(5198) 10001bc0: 6014 str r4, [r2, #0]
(5198) Write UART0_DR = 00000048
(5200) 10001bc2: 42a8 cmp r0, r5
(5200) nzcv = 1...
(5201) 10001bc4: d1f5 bne 0x10001bb2
(5202) 10001bb2: 7804 ldrb r4, [r0, #0]
(5202) Read Flash [10001d01] = 65
(5203) r4 = 00000065
(5204) 10001bb4: 42a6 cmp r6, r4
(5204) nzcv = ..1.
(5205) 10001bb6: d007 beq 0x10001bc8
(5206) 10001bb8: 6993 ldr r3, [r2, #24]
(5206) Read UART0_FR = 00000000
(5207) r3 = 00000000
(5208) 10001bba: 4219 tst r1, r3
(5208) nzcv = .11.
(5209) 10001bbc: d1fc bne 0x10001bb8
(5210) 10001bbe: 3001 add r0, #1
(5210) r0 = 10001d02
(5210) nzcv = ....
(5211) 10001bc0: 6014 str r4, [r2, #0]
(5211) Write UART0_DR = 00000065
(5213) 10001bc2: 42a8 cmp r0, r5
(5213) nzcv = 1...
(5214) 10001bc4: d1f5 bne 0x10001bb2
(5215) 10001bb2: 7804 ldrb r4, [r0, #0]
(5215) Read Flash [10001d02] = 6c
(5216) r4 = 0000006c
(5217) 10001bb4: 42a6 cmp r6, r4
(5217) nzcv = ..1.
(5218) 10001bb6: d007 beq 0x10001bc8
(5219) 10001bb8: 6993 ldr r3, [r2, #24]
(5219) Read UART0_FR = 00000000
(5220) r3 = 00000000
(5221) 10001bba: 4219 tst r1, r3
(5221) nzcv = .11.
(5222) 10001bbc: d1fc bne 0x10001bb8
(5223) 10001bbe: 3001 add r0, #1
(5223) r0 = 10001d03
(5223) nzcv = ....
(5224) 10001bc0: 6014 str r4, [r2, #0]
(5224) Write UART0_DR = 0000006c
(5226) 10001bc2: 42a8 cmp r0, r5
(5226) nzcv = 1...
(5227) 10001bc4: d1f5 bne 0x10001bb2
(5228) 10001bb2: 7804 ldrb r4, [r0, #0]
(5228) Read Flash [10001d03] = 6c
(5229) r4 = 0000006c
(5230) 10001bb4: 42a6 cmp r6, r4
(5230) nzcv = ..1.
(5231) 10001bb6: d007 beq 0x10001bc8
(5232) 10001bb8: 6993 ldr r3, [r2, #24]
(5232) Read UART0_FR = 00000000
(5233) r3 = 00000000
(5234) 10001bba: 4219 tst r1, r3
(5234) nzcv = .11.
(5235) 10001bbc: d1fc bne 0x10001bb8
(5236) 10001bbe: 3001 add r0, #1
(5236) r0 = 10001d04
(5236) nzcv = ....
(5237) 10001bc0: 6014 str r4, [r2, #0]
(5237) Write UART0_DR = 0000006c
(5239) 10001bc2: 42a8 cmp r0, r5
(5239) nzcv = 1...
(5240) 10001bc4: d1f5 bne 0x10001bb2
(5241) 10001bb2: 7804 ldrb r4, [r0, #0]
(5241) Read Flash [10001d04] = 6f
(5242) r4 = 0000006f
(5243) 10001bb4: 42a6 cmp r6, r4
(5243) nzcv = ..1.
(5244) 10001bb6: d007 beq 0x10001bc8
(5245) 10001bb8: 6993 ldr r3, [r2, #24]
(5245) Read UART0_FR = 00000000
(5246) r3 = 00000000
(5247) 10001bba: 4219 tst r1, r3
(5247) nzcv = .11.
(5248) 10001bbc: d1fc bne 0x10001bb8
(5249) 10001bbe: 3001 add r0, #1
(5249) r0 = 10001d05
(5249) nzcv = ....
(5250) 10001bc0: 6014 str r4, [r2, #0]
(5250) Write UART0_DR = 0000006f
(5252) 10001bc2: 42a8 cmp r0, r5
(5252) nzcv = 1...
(5253) 10001bc4: d1f5 bne 0x10001bb2
(5254) 10001bb2: 7804 ldrb r4, [r0, #0]
(5254) Read Flash [10001d05] = 20
(5255) r4 = 00000020
(5256) 10001bb4: 42a6 cmp r6, r4
(5256) nzcv = ..1.
(5257) 10001bb6: d007 beq 0x10001bc8
(5258) 10001bb8: 6993 ldr r3, [r2, #24]
(5258) Read UART0_FR = 00000000
(5259) r3 = 00000000
(5260) 10001bba: 4219 tst r1, r3
(5260) nzcv = .11.
(5261) 10001bbc: d1fc bne 0x10001bb8
(5262) 10001bbe: 3001 add r0, #1
(5262) r0 = 10001d06
(5262) nzcv = ....
(5263) 10001bc0: 6014 str r4, [r2, #0]
(5263) Write UART0_DR = 00000020
(5265) 10001bc2: 42a8 cmp r0, r5
(5265) nzcv = 1...
(5266) 10001bc4: d1f5 bne 0x10001bb2
(5267) 10001bb2: 7804 ldrb r4, [r0, #0]
(5267) Read Flash [10001d06] = 66
(5268) r4 = 00000066
(5269) 10001bb4: 42a6 cmp r6, r4
(5269) nzcv = ..1.
(5270) 10001bb6: d007 beq 0x10001bc8
(5271) 10001bb8: 6993 ldr r3, [r2, #24]
(5271) Read UART0_FR = 00000000
(5272) r3 = 00000000
(5273) 10001bba: 4219 tst r1, r3
(5273) nzcv = .11.
(5274) 10001bbc: d1fc bne 0x10001bb8
(5275) 10001bbe: 3001 add r0, #1
(5275) r0 = 10001d07
(5275) nzcv = ....
(5276) 10001bc0: 6014 str r4, [r2, #0]
(5276) Write UART0_DR = 00000066
(5278) 10001bc2: 42a8 cmp r0, r5
(5278) nzcv = 1...
(5279) 10001bc4: d1f5 bne 0x10001bb2
(5280) 10001bb2: 7804 ldrb r4, [r0, #0]
(5280) Read Flash [10001d07] = 72
(5281) r4 = 00000072
(5282) 10001bb4: 42a6 cmp r6, r4
(5282) nzcv = ..1.
(5283) 10001bb6: d007 beq 0x10001bc8
(5284) 10001bb8: 6993 ldr r3, [r2, #24]
(5284) Read UART0_FR = 00000000
(5285) r3 = 00000000
(5286) 10001bba: 4219 tst r1, r3
(5286) nzcv = .11.
(5287) 10001bbc: d1fc bne 0x10001bb8
(5288) 10001bbe: 3001 add r0, #1
(5288) r0 = 10001d08
(5288) nzcv = ....
(5289) 10001bc0: 6014 str r4, [r2, #0]
(5289) Write UART0_DR = 00000072
(5291) 10001bc2: 42a8 cmp r0, r5
(5291) nzcv = 1...
(5292) 10001bc4: d1f5 bne 0x10001bb2
(5293) 10001bb2: 7804 ldrb r4, [r0, #0]
(5293) Read Flash [10001d08] = 6f
(5294) r4 = 0000006f
(5295) 10001bb4: 42a6 cmp r6, r4
(5295) nzcv = ..1.
(5296) 10001bb6: d007 beq 0x10001bc8
(5297) 10001bb8: 6993 ldr r3, [r2, #24]
(5297) Read UART0_FR = 00000000
(5298) r3 = 00000000
(5299) 10001bba: 4219 tst r1, r3
(5299) nzcv = .11.
(5300) 10001bbc: d1fc bne 0x10001bb8
(5301) 10001bbe: 3001 add r0, #1
(5301) r0 = 10001d09
(5301) nzcv = ....
(5302) 10001bc0: 6014 str r4, [r2, #0]
(5302) Write UART0_DR = 0000006f
(5304) 10001bc2: 42a8 cmp r0, r5
(5304) nzcv = 1...
(5305) 10001bc4: d1f5 bne 0x10001bb2
(5306) 10001bb2: 7804 ldrb r4, [r0, #0]
(5306) Read Flash [10001d09] = 6d
(5307) r4 = 0000006d
(5308) 10001bb4: 42a6 cmp r6, r4
(5308) nzcv = ..1.
(5309) 10001bb6: d007 beq 0x10001bc8
(5310) 10001bb8: 6993 ldr r3, [r2, #24]
(5310) Read UART0_FR = 00000000
(5311) r3 = 00000000
(5312) 10001bba: 4219 tst r1, r3
(5312) nzcv = .11.
(5313) 10001bbc: d1fc bne 0x10001bb8
(5314) 10001bbe: 3001 add r0, #1
(5314) r0 = 10001d0a
(5314) nzcv = ....
(5315) 10001bc0: 6014 str r4, [r2, #0]
(5315) Write UART0_DR = 0000006d
(5317) 10001bc2: 42a8 cmp r0, r5
(5317) nzcv = 1...
(5318) 10001bc4: d1f5 bne 0x10001bb2
(5319) 10001bb2: 7804 ldrb r4, [r0, #0]
(5319) Read Flash [10001d0a] = 20
(5320) r4 = 00000020
(5321) 10001bb4: 42a6 cmp r6, r4
(5321) nzcv = ..1.
(5322) 10001bb6: d007 beq 0x10001bc8
(5323) 10001bb8: 6993 ldr r3, [r2, #24]
(5323) Read UART0_FR = 00000000
(5324) r3 = 00000000
(5325) 10001bba: 4219 tst r1, r3
(5325) nzcv = .11.
(5326) 10001bbc: d1fc bne 0x10001bb8
(5327) 10001bbe: 3001 add r0, #1
(5327) r0 = 10001d0b
(5327) nzcv = ....
(5328) 10001bc0: 6014 str r4, [r2, #0]
(5328) Write UART0_DR = 00000020
(5330) 10001bc2: 42a8 cmp r0, r5
(5330) nzcv = 1...
(5331) 10001bc4: d1f5 bne 0x10001bb2
(5332) 10001bb2: 7804 ldrb r4, [r0, #0]
(5332) Read Flash [10001d0b] = 55
(5333) r4 = 00000055
(5334) 10001bb4: 42a6 cmp r6, r4
(5334) nzcv = ..1.
(5335) 10001bb6: d007 beq 0x10001bc8
(5336) 10001bb8: 6993 ldr r3, [r2, #24]
(5336) Read UART0_FR = 00000000
(5337) r3 = 00000000
(5338) 10001bba: 4219 tst r1, r3
(5338) nzcv = .11.
(5339) 10001bbc: d1fc bne 0x10001bb8
(5340) 10001bbe: 3001 add r0, #1
(5340) r0 = 10001d0c
(5340) nzcv = ....
(5341) 10001bc0: 6014 str r4, [r2, #0]
(5341) Write UART0_DR = 00000055
(5343) 10001bc2: 42a8 cmp r0, r5
(5343) nzcv = 1...
(5344) 10001bc4: d1f5 bne 0x10001bb2
(5345) 10001bb2: 7804 ldrb r4, [r0, #0]
(5345) Read Flash [10001d0c] = 41
(5346) r4 = 00000041
(5347) 10001bb4: 42a6 cmp r6, r4
(5347) nzcv = ..1.
(5348) 10001bb6: d007 beq 0x10001bc8
(5349) 10001bb8: 6993 ldr r3, [r2, #24]
(5349) Read UART0_FR = 00000000
(5350) r3 = 00000000
(5351) 10001bba: 4219 tst r1, r3
(5351) nzcv = .11.
(5352) 10001bbc: d1fc bne 0x10001bb8
(5353) 10001bbe: 3001 add r0, #1
(5353) r0 = 10001d0d
(5353) nzcv = ....
(5354) 10001bc0: 6014 str r4, [r2, #0]
(5354) Write UART0_DR = 00000041
(5356) 10001bc2: 42a8 cmp r0, r5
(5356) nzcv = 1...
(5357) 10001bc4: d1f5 bne 0x10001bb2
(5358) 10001bb2: 7804 ldrb r4, [r0, #0]
(5358) Read Flash [10001d0d] = 52
(5359) r4 = 00000052
(5360) 10001bb4: 42a6 cmp r6, r4
(5360) nzcv = ..1.
(5361) 10001bb6: d007 beq 0x10001bc8
(5362) 10001bb8: 6993 ldr r3, [r2, #24]
(5362) Read UART0_FR = 00000000
(5363) r3 = 00000000
(5364) 10001bba: 4219 tst r1, r3
(5364) nzcv = .11.
(5365) 10001bbc: d1fc bne 0x10001bb8
(5366) 10001bbe: 3001 add r0, #1
(5366) r0 = 10001d0e
(5366) nzcv = ....
(5367) 10001bc0: 6014 str r4, [r2, #0]
(5367) Write UART0_DR = 00000052
(5369) 10001bc2: 42a8 cmp r0, r5
(5369) nzcv = 1...
(5370) 10001bc4: d1f5 bne 0x10001bb2
(5371) 10001bb2: 7804 ldrb r4, [r0, #0]
(5371) Read Flash [10001d0e] = 54
(5372) r4 = 00000054
(5373) 10001bb4: 42a6 cmp r6, r4
(5373) nzcv = ..1.
(5374) 10001bb6: d007 beq 0x10001bc8
(5375) 10001bb8: 6993 ldr r3, [r2, #24]
(5375) Read UART0_FR = 00000000
(5376) r3 = 00000000
(5377) 10001bba: 4219 tst r1, r3
(5377) nzcv = .11.
(5378) 10001bbc: d1fc bne 0x10001bb8
(5379) 10001bbe: 3001 add r0, #1
(5379) r0 = 10001d0f
(5379) nzcv = ....
(5380) 10001bc0: 6014 str r4, [r2, #0]
(5380) Write UART0_DR = 00000054
(5382) 10001bc2: 42a8 cmp r0, r5
(5382) nzcv = 1...
(5383) 10001bc4: d1f5 bne 0x10001bb2
(5384) 10001bb2: 7804 ldrb r4, [r0, #0]
(5384) Read Flash [10001d0f] = 21
(5385) r4 = 00000021
(5386) 10001bb4: 42a6 cmp r6, r4
(5386) nzcv = ..1.
(5387) 10001bb6: d007 beq 0x10001bc8
(5388) 10001bb8: 6993 ldr r3, [r2, #24]
(5388) Read UART0_FR = 00000000
(5389) r3 = 00000000
(5390) 10001bba: 4219 tst r1, r3
(5390) nzcv = .11.
(5391) 10001bbc: d1fc bne 0x10001bb8
(5392) 10001bbe: 3001 add r0, #1
(5392) r0 = 10001d10
(5392) nzcv = ....
(5393) 10001bc0: 6014 str r4, [r2, #0]
(5393) Write UART0_DR = 00000021
(5395) 10001bc2: 42a8 cmp r0, r5
(5395) nzcv = .11.
(5396) 10001bc4: d1f5 bne 0x10001bb2
(5397) 10001bc6: bdf0 pop {r4, r5, r6, r7, pc}
(5397) Read SRAM [20041e9c] = 00000010
(5398) r4 = 00000010
(5398) Read SRAM [20041ea0] = 10001d00
(5399) r5 = 10001d00
(5399) Read SRAM [20041ea4] = 00000010
(5400) r6 = 00000010
(5400) Read SRAM [20041ea8] = 20000210
(5401) r7 = 20000210
(5401) Read SRAM [20041eac] = 100019a2
(5402) msp = 20041eb0
(5403) 100019a2: 19ad add r5, r5, r6
(5403) r5 = 10001d10
(5403) nzcv = ....
(5404) 100019a4: 3d01 sub r5, #1
(5404) r5 = 10001d0f
(5404) nzcv = ..1.
(5405) 100019a6: 782b ldrb r3, [r5, #0]
(5405) Read Flash [10001d0f] = 21
(5406) r3 = 00000021
(5407) 100019a8: 3b0d sub r3, #13
(5407) r3 = 00000014
(5408) 100019aa: 425a neg r2, r3
(5408) r2 = ffffffec
(5408) nzcv = 1...
(5409) 100019ac: 4153 adc r3, r2
(5409) r3 = 00000000
(5409) nzcv = .11.
(5410) 100019ae: 743b strb r3, [r7, #16]
(5410) Write SRAM [20000220] = 00
(5412) 100019b0: bc80 pop {r7}
(5412) Read SRAM [20041eb0] = 00000001
(5413) r7 = 00000001
(5413) msp = 20041eb4
(5414) 100019b2: 46b8 mov r8, r7
(5414) r8 = 00000001
(5415) 100019b4: bdf0 pop {r4, r5, r6, r7, pc}
(5415) Read SRAM [20041eb4] = 20000210
(5416) r4 = 20000210
(5416) Read SRAM [20041eb8] = 00000010
(5417) r5 = 00000010
(5417) Read SRAM [20041ebc] = 10001d00
(5418) r6 = 10001d00
(5418) Read SRAM [20041ec0] = 200005bc
(5419) r7 = 200005bc
(5419) Read SRAM [20041ec4] = 10001ad4
(5420) msp = 20041ec8
(5421) 10001ad4: 466b mov r3, sp
(5421) r3 = 20041ec8
(5422) 10001ad6: 464a mov r2, r9
(5422) r2 = 0000000a
(5423) 10001ad8: 0020 movs r0, r4
(5423) r0 = 20000210
(5423) nzcv = ..1.
(5424) 10001ada: 711a strb r2, [r3, #4]
(5424) Write SRAM [20041ecc] = 0a
(5426) 10001adc: a901 add r1, sp, #4
(5426) r1 = 20041ecc
(5427) 10001ade: 2201 movs r2, #1
(5427) r2 = 00000001
(5429) 10001ae0: f7ffff2c bl 0x1000193c
(5429) lr = 10001ae4
(5430) 1000193c: b5f0 push {r4, r5, r6, r7, lr}
(5430) Write SRAM [20041ec4] = 10001ae4
(5431) Write SRAM [20041ec0] = 200005bc
(5432) Write SRAM [20041ebc] = 10001d00
(5433) Write SRAM [20041eb8] = 00000010
(5434) Write SRAM [20041eb4] = 20000210
(5435) msp = 20041eb4
(5436) 1000193e: 46c6 mov lr, r8
(5436) lr = 00000001
(5437) 10001940: b500 push {lr}
(5437) Write SRAM [20041eb0] = 00000001
(5438) msp = 20041eb0
(5439) 10001942: 7c43 ldrb r3, [r0, #17]
(5439) Read SRAM [20000221] = 01
(5440) r3 = 00000001
(5441) 10001944: 0007 movs r7, r0
(5441) r7 = 20000210
(5442) 10001946: 000d movs r5, r1
(5442) r5 = 20041ecc
(5443) 10001948: 0016 movs r6, r2
(5443) r6 = 00000001
(5444) 1000194a: 2b00 cmp r3, #0
(5445) 1000194c: d038 beq 0x100019c0
(5446) 1000194e: 2a00 cmp r2, #0
(5447) 10001950: dd2e ble 0x100019b0
(5448) 10001952: 2100 movs r1, #0
(5448) r1 = 00000000
(5448) nzcv = .11.
(5449) 10001954: 1e6a sub r2, r5, #1
(5449) r2 = 20041ecb
(5449) nzcv = ..1.
(5450) 10001956: 4690 mov r8, r2
(5450) r8 = 20041ecb
(5451) 10001958: 5c6a ldrb r2, [r5, r1]
(5451) Read SRAM [20041ecc] = 0a
(5452) r2 = 0000000a
(5453) 1000195a: 7c03 ldrb r3, [r0, #16]
(5453) Read SRAM [20000220] = 00
(5454) r3 = 00000000
(5455) 1000195c: 1c4c add r4, r1, #1
(5455) r4 = 00000001
(5455) nzcv = ....
(5456) 1000195e: 2000 movs r0, #0
(5456) r0 = 00000000
(5456) nzcv = .1..
(5457) 10001960: 2a0a cmp r2, #10
(5457) nzcv = .11.
(5458) 10001962: d00c beq 0x1000197e
(5459) 1000197e: 2b00 cmp r3, #0
(5460) 10001980: d1f0 bne 0x10001964
(5461) 10001982: 4281 cmp r1, r0
(5462) 10001984: dc17 bgt 0x100019b6
(5463) 10001986: 2102 movs r1, #2
(5463) r1 = 00000002
(5463) nzcv = ..1.
(5464) 10001988: 4810 ldr r0, [pc, #64]
(5464) Read Flash [100019cc] = 10001dbc
(5465) r0 = 10001dbc
(5466) 1000198a: 683b ldr r3, [r7, #0]
(5466) Read SRAM [20000210] = 10001b95
(5467) r3 = 10001b95
(5468) 1000198c: 4798 blx r3
(5468) lr = 1000198e
(5469) 10001b94: b5f0 push {r4, r5, r6, r7, lr}
(5469) Write SRAM [20041eac] = 1000198e
(5470) Write SRAM [20041ea8] = 20000210
(5471) Write SRAM [20041ea4] = 00000001
(5472) Write SRAM [20041ea0] = 20041ecc
(5473) Write SRAM [20041e9c] = 00000001
(5474) msp = 20041e9c
(5475) 10001b96: 2900 cmp r1, #0
(5476) 10001b98: dd15 ble 0x10001bc6
(5477) 10001b9a: 4b0e ldr r3, [pc, #56]
(5477) Read Flash [10001bd4] = 20000608
(5478) r3 = 20000608
(5479) 10001b9c: 270d movs r7, #13
(5479) r7 = 0000000d
(5480) 10001b9e: 681a ldr r2, [r3, #0]
(5480) Read SRAM [20000608] = 40034000
(5481) r2 = 40034000
(5482) 10001ba0: 4b0d ldr r3, [pc, #52]
(5482) Read Flash [10001bd8] = bffc8000
(5483) r3 = bffc8000
(5484) 10001ba2: 4c0e ldr r4, [pc, #56]
(5484) Read Flash [10001bdc] = 20000604
(5485) r4 = 20000604
(5486) 10001ba4: 18d3 add r3, r2, r3
(5486) r3 = ffffc000
(5486) nzcv = 1...
(5487) 10001ba6: 425d neg r5, r3
(5487) r5 = 00004000
(5487) nzcv = ....
(5488) 10001ba8: 416b adc r3, r5
(5488) r3 = 00000000
(5488) nzcv = .11.
(5489) 10001baa: 1845 add r5, r0, r1
(5489) r5 = 10001dbe
(5489) nzcv = ....
(5490) 10001bac: 2120 movs r1, #32
(5490) r1 = 00000020
(5491) 10001bae: 005b lsls r3, r3, #1
(5491) r3 = 00000000
(5491) nzcv = .1..
(5492) 10001bb0: 5f1e ldrsh r6, [r3, r4]
(5492) Read SRAM [20000604] = 0100
(5493) r6 = 00000100
(5494) 10001bb2: 7804 ldrb r4, [r0, #0]
(5494) Read Flash [10001dbc] = 0d
(5495) r4 = 0000000d
(5496) 10001bb4: 42a6 cmp r6, r4
(5496) nzcv = ..1.
(5497) 10001bb6: d007 beq 0x10001bc8
(5498) 10001bb8: 6993 ldr r3, [r2, #24]
(5498) Read UART0_FR = 00000000
(5499) r3 = 00000000
(5500) 10001bba: 4219 tst r1, r3
(5500) nzcv = .11.
(5501) 10001bbc: d1fc bne 0x10001bb8
(5502) 10001bbe: 3001 add r0, #1
(5502) r0 = 10001dbd
(5502) nzcv = ....
(5503) 10001bc0: 6014 str r4, [r2, #0]
(5503) Write UART0_DR = 0000000d
(5505) 10001bc2: 42a8 cmp r0, r5
(5505) nzcv = 1...
(5506) 10001bc4: d1f5 bne 0x10001bb2
(5507) 10001bb2: 7804 ldrb r4, [r0, #0]
(5507) Read Flash [10001dbd] = 0a
(5508) r4 = 0000000a
(5509) 10001bb4: 42a6 cmp r6, r4
(5509) nzcv = ..1.
(5510) 10001bb6: d007 beq 0x10001bc8
(5511) 10001bb8: 6993 ldr r3, [r2, #24]
(5511) Read UART0_FR = 00000000
(5512) r3 = 00000000
(5513) 10001bba: 4219 tst r1, r3
(5513) nzcv = .11.
(5514) 10001bbc: d1fc bne 0x10001bb8
(5515) 10001bbe: 3001 add r0, #1
(5515) r0 = 10001dbe
(5515) nzcv = ....
(5516) 10001bc0: 6014 str r4, [r2, #0]
(5516) Write UART0_DR = 0000000a
(5518) 10001bc2: 42a8 cmp r0, r5
(5518) nzcv = .11.
(5519) 10001bc4: d1f5 bne 0x10001bb2
(5520) 10001bc6: bdf0 pop {r4, r5, r6, r7, pc}
(5520) Read SRAM [20041e9c] = 00000001
(5521) r4 = 00000001
(5521) Read SRAM [20041ea0] = 20041ecc
(5522) r5 = 20041ecc
(5522) Read SRAM [20041ea4] = 00000001
(5523) r6 = 00000001
(5523) Read SRAM [20041ea8] = 20000210
(5524) r7 = 20000210
(5524) Read SRAM [20041eac] = 1000198e
(5525) msp = 20041eb0
(5526) 1000198e: 42a6 cmp r6, r4
(5527) 10001990: d007 beq 0x100019a2
(5528) 100019a2: 19ad add r5, r5, r6
(5528) r5 = 20041ecd
(5528) nzcv = ....
(5529) 100019a4: 3d01 sub r5, #1
(5529) r5 = 20041ecc
(5529) nzcv = ..1.
(5530) 100019a6: 782b ldrb r3, [r5, #0]
(5530) Read SRAM [20041ecc] = 0a
(5531) r3 = 0000000a
(5532) 100019a8: 3b0d sub r3, #13
(5532) r3 = fffffffd
(5532) nzcv = 1...
(5533) 100019aa: 425a neg r2, r3
(5533) r2 = 00000003
(5533) nzcv = ....
(5534) 100019ac: 4153 adc r3, r2
(5534) r3 = 00000000
(5534) nzcv = .11.
(5535) 100019ae: 743b strb r3, [r7, #16]
(5535) Write SRAM [20000220] = 00
(5537) 100019b0: bc80 pop {r7}
(5537) Read SRAM [20041eb0] = 00000001
(5538) r7 = 00000001
(5538) msp = 20041eb4
(5539) 100019b2: 46b8 mov r8, r7
(5539) r8 = 00000001
(5540) 100019b4: bdf0 pop {r4, r5, r6, r7, pc}
(5540) Read SRAM [20041eb4] = 20000210
(5541) r4 = 20000210
(5541) Read SRAM [20041eb8] = 00000010
(5542) r5 = 00000010
(5542) Read SRAM [20041ebc] = 10001d00
(5543) r6 = 10001d00
(5543) Read SRAM [20041ec0] = 200005bc
(5544) r7 = 200005bc
(5544) Read SRAM [20041ec4] = 10001ae4
(5545) msp = 20041ec8
(5546) 10001ae4: 68e4 ldr r4, [r4, #12]
(5546) Read SRAM [2000021c] = 00000000
(5547) r4 = 00000000
(5548) 10001ae6: 2c00 cmp r4, #0
(5549) 10001ae8: d1e7 bne 0x10001aba
(5550) 10001aea: 4643 mov r3, r8
(5550) r3 = 00000001
(5551) 10001aec: 2b00 cmp r3, #0
(5551) nzcv = ..1.
(5552) 10001aee: d125 bne 0x10001b3c
(5553) 10001b3c: 4658 mov r0, fp
(5553) r0 = 20000224
(5555) 10001b3e: f000f8bf bl 0x10001cc0
(5555) lr = 10001b42
(5556) 10001cc0: b401 push {r0}
(5556) Write SRAM [20041ec4] = 20000224
(5557) msp = 20041ec4
(5558) 10001cc2: 4802 ldr r0, [pc, #8]
(5558) Read Flash [10001ccc] = 20000149
(5559) r0 = 20000149
(5560) 10001cc4: 4684 mov ip, r0
(5560) ip = 20000149
(5561) 10001cc6: bc01 pop {r0}
(5561) Read SRAM [20041ec4] = 20000224
(5562) r0 = 20000224
(5562) msp = 20041ec8
(5563) 10001cc8: 4760 bx ip
(5564) 20000148: 6802 ldr r2, [r0, #0]
(5564) Read SRAM [20000224] = d0000140
(5565) r2 = d0000140
(5567) 2000014a: f3ef8110 mrs r1, PRIMASK
(5567) r1 = 00000000
(5568) 2000014e: b672 cpsid i
(5568) primask = 00000001
(5569) 20000150: 6813 ldr r3, [r2, #0]
(5569) Read SPINLOCK16 = 00010000
(5570) r3 = 00010000
(5571) 20000152: 2b00 cmp r3, #0
(5572) 20000154: d0fc beq 0x20000150
(5574) 20000156: f3bf8f5f dmb #15
(5575) 2000015a: 23ff movs r3, #255
(5575) r3 = 000000ff
(5576) 2000015c: 7103 strb r3, [r0, #4]
(5576) Write SRAM [20000228] = ff
(5578) 2000015e: 6803 ldr r3, [r0, #0]
(5578) Read SRAM [20000224] = d0000140
(5579) r3 = d0000140
(5581) 20000160: f3bf8f5f dmb #15
(5582) 20000164: 2200 movs r2, #0
(5582) r2 = 00000000
(5582) nzcv = .11.
(5583) 20000166: 601a str r2, [r3, #0]
(5583) Write SPINLOCK16 = 00000000
(5586) 20000168: f3818810 msr PRIMASK, r1
(5586) primask = 00000000
(5587) 2000016c: bf40 sev
(5588) 2000016e: 4770 bx lr
(5589) 10001b42: e7d5 b 0x10001af0
(5590) 10001af0: 4653 mov r3, sl
(5590) r3 = 200005b8
(5591) 10001af2: 681c ldr r4, [r3, #0]
(5591) Read SRAM [200005b8] = 20000210
(5592) r4 = 20000210
(5593) 10001af4: 2c00 cmp r4, #0
(5593) nzcv = ..1.
(5594) 10001af6: d006 beq 0x10001b06
(5595) 10001af8: 6863 ldr r3, [r4, #4]
(5595) Read SRAM [20000214] = 00000000
(5596) r3 = 00000000
(5597) 10001afa: 2b00 cmp r3, #0
(5597) nzcv = .11.
(5598) 10001afc: d00b beq 0x10001b16
(5599) 10001b16: 68e4 ldr r4, [r4, #12]
(5599) Read SRAM [2000021c] = 00000000
(5600) r4 = 00000000
(5601) 10001b18: 2c00 cmp r4, #0
(5602) 10001b1a: d1ed bne 0x10001af8
(5603) 10001b1c: e7f3 b 0x10001b06
(5604) 10001b06: 0028 movs r0, r5
(5604) r0 = 00000010
(5604) nzcv = ..1.
(5605) 10001b08: b003 add sp, #12
(5605) msp = 20041ed4
(5606) 10001b0a: bcf0 pop {r4, r5, r6, r7}
(5606) Read SRAM [20041ed4] = 00000000
(5607) r4 = 00000000
(5607) Read SRAM [20041ed8] = 00000000
(5608) r5 = 00000000
(5608) Read SRAM [20041edc] = 00000000
(5609) r6 = 00000000
(5609) Read SRAM [20041ee0] = 00000000
(5610) r7 = 00000000
(5610) msp = 20041ee4
(5611) 10001b0c: 46bb mov fp, r7
(5611) fp = 00000000
(5612) 10001b0e: 46b2 mov sl, r6
(5612) sl = 00000000
(5613) 10001b10: 46a9 mov r9, r5
(5613) r9 = 00000000
(5614) 10001b12: 46a0 mov r8, r4
(5614) r8 = 00000000
(5615) 10001b14: bdf0 pop {r4, r5, r6, r7, pc}
(5615) Read SRAM [20041ee4] = 10000264
(5616) r4 = 10000264
(5616) Read SRAM [20041ee8] = 00000000
(5617) r5 = 00000000
(5617) Read SRAM [20041eec] = 00000000
(5618) r6 = 00000000
(5618) Read SRAM [20041ef0] = 00000000
(5619) r7 = 00000000
(5619) Read SRAM [20041ef4] = 1000031c
(5620) msp = 20041ef8
(5621) 1000031c: df01 svc 1
(5621) Done
Elapsed time: 0.039 seconds
System clock: 5621 ticks
Simulated: 3854 instructions
Simulation rate: 144 kHz, 98824 instructions/sec
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment